From 65b69a91e56eeea0403cb3b5165f31f80a32049b Mon Sep 17 00:00:00 2001 From: Matthew Flatt Date: Tue, 4 Aug 2020 15:05:13 +0000 Subject: [PATCH] add needed store fence in list-bits management --- racket/src/ChezScheme/c/alloc.c | 5 +++-- racket/src/ChezScheme/c/version.h | 10 ++++++++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/racket/src/ChezScheme/c/alloc.c b/racket/src/ChezScheme/c/alloc.c index 833cb5abe7..03f009a834 100644 --- a/racket/src/ChezScheme/c/alloc.c +++ b/racket/src/ChezScheme/c/alloc.c @@ -475,9 +475,10 @@ void S_list_bits_set(p, bits) ptr p; iptr bits; { memset(list_bits, 0, segment_bitmap_bytes); - /* FIXME: A write fence is needed here to make sure `list_bits` is - zeroed for everyone who sees it. On x86, TSO takes care of that + /* A store fence is needed here to make sure `list_bits` is zeroed + for everyone who sees it. On x86, TSO takes care of that ordering already. */ + STORE_FENCE(); /* beware: racy write here */ si->list_bits = list_bits; diff --git a/racket/src/ChezScheme/c/version.h b/racket/src/ChezScheme/c/version.h index 4ac55ca09d..45fe7444d6 100644 --- a/racket/src/ChezScheme/c/version.h +++ b/racket/src/ChezScheme/c/version.h @@ -468,3 +468,13 @@ typedef char tputsputcchar; /* Use "/dev/urandom" everywhere except Windows */ #define USE_DEV_URANDOM_UUID + +#if defined(__arm64__) || defined(__arm32__) +# define STORE_FENCE() __asm__ __volatile__ ("dmb ishst" : : : "memory") +#elif defined(__powerpc64__) +# define STORE_FENCE() __asm__ __volatile__ ("lwsync" : : : "memory") +#elif defined(__powerpc__) || defined(__POWERPC__) +# define STORE_FENCE() __asm__ __volatile__ ("sync" : : : "memory") +#else +# define STORE_FENCE() /* empty */ +#endif