From 67c00aaa7de0a504a235083db474347d5e6334f1 Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Fri, 9 Oct 2020 18:10:57 +0200 Subject: [PATCH] Fix ARMv7 build using Thumb-2 (#3431) This ensures that the moveq instruction is inside an IT block. Backward compatible change - still builds on ARMv6 with Thumb. This breakage is generally not noticeable on a RPi3 because, although the CPU is ARMv7, it is generally running an ARMv6 OS. --- racket/src/ChezScheme/c/atomic.h | 1 + racket/src/ChezScheme/s/mkheader.ss | 2 ++ 2 files changed, 3 insertions(+) diff --git a/racket/src/ChezScheme/c/atomic.h b/racket/src/ChezScheme/c/atomic.h index ade52a72fa..54db9f44de 100644 --- a/racket/src/ChezScheme/c/atomic.h +++ b/racket/src/ChezScheme/c/atomic.h @@ -83,6 +83,7 @@ FORCEINLINE int S_cas_any_fence(volatile void *addr, void *old_val, void *new_va "strex r7, %3, [%1, #0]\n\t" "cmp r7, #0\n\t" "bne 1f\n\t" + "it eq\n\t" "moveq %0, #1\n\t" "1:\n\t" : "=&r" (ret) diff --git a/racket/src/ChezScheme/s/mkheader.ss b/racket/src/ChezScheme/s/mkheader.ss index 8e13572e1a..dbf3eb5d6c 100644 --- a/racket/src/ChezScheme/s/mkheader.ss +++ b/racket/src/ChezScheme/s/mkheader.ss @@ -752,6 +752,7 @@ (pr " \"cmp r7, #0\\n\\t\"\\~%") (pr " \"bne 0b\\n\\t\"\\~%") (pr " \"cmp r12, #0\\n\\t\"\\~%") + (pr " \"it eq\\n\\t\"\\~%") (pr " \"moveq %0, #1\\n\\t\"\\~%") (pr " : \"=&r\" (ret)\\~%") (pr " : \"r\" (addr)\\~%") @@ -767,6 +768,7 @@ (pr " \"cmp r7, #0\\n\\t\"\\~%") (pr " \"bne 0b\\n\\t\"\\~%") (pr " \"cmp r12, #0\\n\\t\"\\~%") + (pr " \"it eq\\n\\t\"\\~%") (pr " \"moveq %0, #1\\n\\t\"\\~%") (pr " : \"=&r\" (ret)\\~%") (pr " : \"r\" (addr)\\~%")