suzanne.soy/racket
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unbreak arm32

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original commit: 83221c32b4e8654f0f7d3b3857b7efab5be2bad4
This commit is contained in:
Matthew Flatt 2020-07-12 06:00:00 -06:00
parent 802daa10b1
commit a4fb72e84c
1 changed files with 9 additions and 9 deletions
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18
s/mkheader.ss
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@ -656,8 +656,8 @@
(pr " \"cmp r12, #0\\n\\t\"\\~%") (pr " \"cmp r12, #0\\n\\t\"\\~%")
(pr " \"bne 1f\\n\\t\"\\~%") (pr " \"bne 1f\\n\\t\"\\~%")
(pr " \"mov r12, #1\\n\\t\"\\~%") (pr " \"mov r12, #1\\n\\t\"\\~%")
(pr " \"strex x7, r12, [%0]\\n\\t\"\\~%") (pr " \"strex r7, r12, [%0]\\n\\t\"\\~%")
(pr " \"cmp x7, #0\\n\\t\"\\~%") (pr " \"cmp r7, #0\\n\\t\"\\~%")
(pr " \"beq 2f\\n\\t\"\\~%") (pr " \"beq 2f\\n\\t\"\\~%")
(pr " \"1:\\n\\t\"\\~%") (pr " \"1:\\n\\t\"\\~%")
(pr " \"ldr r12, [%0, #0]\\n\\t\"\\~%") (pr " \"ldr r12, [%0, #0]\\n\\t\"\\~%")
@ -667,7 +667,7 @@
(pr " \"2:\\n\\t\"\\~%") (pr " \"2:\\n\\t\"\\~%")
(pr " : \\~%") (pr " : \\~%")
(pr " : \"r\" (addr)\\~%") (pr " : \"r\" (addr)\\~%")
(pr " : \"cc\", \"memory\", \"r12\", \"x7\")~%") (pr " : \"cc\", \"memory\", \"r12\", \"r7\")~%")
(nl) (nl)
(pr "#define UNLOCK(addr) \\~%") (pr "#define UNLOCK(addr) \\~%")
@ -683,14 +683,14 @@
(pr " \"0:\\n\\t\"\\~%") (pr " \"0:\\n\\t\"\\~%")
(pr " \"ldrex r12, [%1, #0]\\n\\t\"\\~%") (pr " \"ldrex r12, [%1, #0]\\n\\t\"\\~%")
(pr " \"add r12, r12, #1\\n\\t\"\\~%") (pr " \"add r12, r12, #1\\n\\t\"\\~%")
(pr " \"strex x7, r12, [%1]\\n\\t\"\\~%") (pr " \"strex r7, r12, [%1]\\n\\t\"\\~%")
(pr " \"cmp x7, #0\\n\\t\"\\~%") (pr " \"cmp r7, #0\\n\\t\"\\~%")
(pr " \"bne 0b\\n\\t\"\\~%") (pr " \"bne 0b\\n\\t\"\\~%")
(pr " \"cmp r12, #0\\n\\t\"\\~%") (pr " \"cmp r12, #0\\n\\t\"\\~%")
(pr " \"moveq %0, #1\\n\\t\"\\~%") (pr " \"moveq %0, #1\\n\\t\"\\~%")
(pr " : \"=&r\" (ret)\\~%") (pr " : \"=&r\" (ret)\\~%")
(pr " : \"r\" (addr)\\~%") (pr " : \"r\" (addr)\\~%")
(pr " : \"cc\", \"memory\", \"r12\", \"x7\")~%") (pr " : \"cc\", \"memory\", \"r12\", \"r7\")~%")
(nl) (nl)
(pr "#define LOCKED_DECR(addr, ret) \\~%") (pr "#define LOCKED_DECR(addr, ret) \\~%")
@ -698,14 +698,14 @@
(pr " \"0:\\n\\t\"\\~%") (pr " \"0:\\n\\t\"\\~%")
(pr " \"ldrex r12, [%1, #0]\\n\\t\"\\~%") (pr " \"ldrex r12, [%1, #0]\\n\\t\"\\~%")
(pr " \"sub r12, r12, #1\\n\\t\"\\~%") (pr " \"sub r12, r12, #1\\n\\t\"\\~%")
(pr " \"strex x7, r12, [%1]\\n\\t\"\\~%") (pr " \"strex r7, r12, [%1]\\n\\t\"\\~%")
(pr " \"cmp x7, #0\\n\\t\"\\~%") (pr " \"cmp r7, #0\\n\\t\"\\~%")
(pr " \"bne 0b\\n\\t\"\\~%") (pr " \"bne 0b\\n\\t\"\\~%")
(pr " \"cmp r12, #0\\n\\t\"\\~%") (pr " \"cmp r12, #0\\n\\t\"\\~%")
(pr " \"moveq %0, #1\\n\\t\"\\~%") (pr " \"moveq %0, #1\\n\\t\"\\~%")
(pr " : \"=&r\" (ret)\\~%") (pr " : \"=&r\" (ret)\\~%")
(pr " : \"r\" (addr)\\~%") (pr " : \"r\" (addr)\\~%")
(pr " : \"cc\", \"memory\", \"r12\", \"x7\")~%")] (pr " : \"cc\", \"memory\", \"r12\", \"r7\")~%")]
[(arm64) [(arm64)
(pr "#define INITLOCK(addr) \\~%") (pr "#define INITLOCK(addr) \\~%")
(pr " __asm__ __volatile__ (\"mov x12, #0\\n\\t\"\\~%") (pr " __asm__ __volatile__ (\"mov x12, #0\\n\\t\"\\~%")