From c0af3a253b7e6ff7d36720f561cfc5ded5213881 Mon Sep 17 00:00:00 2001 From: Matthew Flatt Date: Fri, 30 Apr 2021 12:21:16 -0600 Subject: [PATCH] Chez Scheme: fix fence preproceddore conditional for AArch64 The memory-fence macros were not being used on non-Apple AArch64. --- racket/src/ChezScheme/c/atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/racket/src/ChezScheme/c/atomic.h b/racket/src/ChezScheme/c/atomic.h index 8610394748..5fb98e0dde 100644 --- a/racket/src/ChezScheme/c/atomic.h +++ b/racket/src/ChezScheme/c/atomic.h @@ -1,6 +1,6 @@ #if !defined(PTHREADS) # define STORE_FENCE() do { } while (0) -#elif defined(__arm64__) +#elif defined(__arm64__) || defined(__aarch64__) # define STORE_FENCE() __asm__ __volatile__ ("dmb ishst" : : : "memory") # define ACQUIRE_FENCE() __asm__ __volatile__ ("dmb ish" : : : "memory") # define RELEASE_FENCE() ACQUIRE_FENCE() @@ -35,7 +35,7 @@ #if !defined(PTHREADS) # define CAS_ANY_FENCE(a, old, new) ((*(a) == (old)) ? (*(a) = (new), 1) : 0) -#elif defined(__arm64__) +#elif defined(__arm64__) || defined(__aarch64__) FORCEINLINE int CAS_LOAD_ACQUIRE(volatile void *addr, void *old_val, void *new_val) { long ret; __asm__ __volatile__ ("mov %0, #0\n\t"