diff --git a/src/racket/sconfig.h b/src/racket/sconfig.h
index 612a5c0c9a..8e65f352cd 100644
--- a/src/racket/sconfig.h
+++ b/src/racket/sconfig.h
@@ -1347,7 +1347,7 @@
 
  /* MZ_USE_JIT_I386 enables the JIT for x86 */
 
- /* MZ_USE_JIT_X86_65 enables the JIT for x86_64 */
+ /* MZ_USE_JIT_X86_64 enables the JIT for x86_64 */
 
  /* MZ_USE_JIT_PPC enables the JIT for PowerPC */
 
diff --git a/src/racket/src/future.c b/src/racket/src/future.c
index ae8ddc8bef..cbbb9a6c13 100644
--- a/src/racket/src/future.c
+++ b/src/racket/src/future.c
@@ -526,15 +526,23 @@ void scheme_future_block_until_gc()
   }
 
   if (cpucount > 1) {
-    /* `cpucount' is not actually a complete test for whether mfence
-       should work, but the probability of someone using futures
-       on a multiprocessor system without SSE2 seems very low. */
-#ifdef _MSC_VER
-    __asm { 
-      mfence 
-        }
-#else
-    asm("mfence");
+    /* In principle, we need some sort of fence to ensure that future
+       threads see the change to the fuel pointer. The MFENCE
+       instruction would do that, but it requires SSE2. The CPUID
+       instruction is a non-privileged serializing instruction that
+       should be available on any x86 platform that runs threads. */
+#if defined(i386) || defined(__i386__) || defined(__x86_64) || defined(__x86_64__) || defined(__amd64__)
+# ifdef _MSC_VER
+    {
+      int r[4];
+      __cpuid(r, 0);
+    }
+# else
+    {
+      int _eax, _ebx, _ecx, _edx, op = 0;
+      asm ("cpuid" : "=a" (_eax), "=b" (_ebx), "=c" (_ecx), "=d" (_edx) : "a" (op));
+    }
+# endif
 #endif
   }