kind of fixed lpddr2 detection, added addressing modes for 512mb and 1gb lpddr2 chips, documented some timing related stuff
This commit is contained in:
kristina
parent
f9187ed13a
commit
41ff22199e
454
sdram.c
454
sdram.c
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@ -1,5 +1,6 @@
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/*=============================================================================
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Copyright (C) 2016 Kristina Brooks
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Copyright (C) 2016 Julian Brown
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All rights reserved.
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This program is free software; you can redistribute it and/or
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@ -17,37 +18,96 @@ VideoCoreIV SDRAM initialization code.
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=============================================================================*/
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#include "lib/common.h"
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#include "hardware.h"
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#include <common.h>
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#include <hardware.h>
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/*
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Registers
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=========
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SC: AC Timing (Page 202)
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SB: ???
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SD: AC Timing (Page 202)
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SE: AC Timing (Page 202)
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PT1:
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Minimum Idle time after first CKE assertion
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Minimum CKE low time after completion of power ramp
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PT2:
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DAI Duration
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*/
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extern uint32_t g_CPUID;
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#define MR_REQUEST_SUCCESS(x) ((SD_MR_TIMEOUT_SET & x) != SD_MR_TIMEOUT_SET)
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#define MR_GET_RDATA(x) ((x & SD_MR_RDATA_SET) >> SD_MR_RDATA_LSB)
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#define RAM_TEST_ADDR 0xC0000000
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#define RAM_TEST_PATTERN 0xAAAAAAAA
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#define SIP_DEBUG(x) x
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#define SCLKU_DEBUG(x) //SIP_DEBUG(x)
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ALWAYS_INLINE inline void sdram_clkman_update_begin() {
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#define BIST_pvt 0x20
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#define BIST_reset 0x10
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#define PVT_calibrate_request 0x1
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#define logf(fmt, ...) printf("[SDRAM::%s]: " fmt, __FUNCTION__, ##__VA_ARGS__);
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unsigned g_RAMSize = RAM_SIZE_UNKNOWN;
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static const char* lpddr2_manufacturer_name(uint32_t mr) {
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switch (mr) {
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case 1: return "Samsung";
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case 2: return "Qimonda";
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case 3: return "Elpida";
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case 4: return "Etron";
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case 5: return "Nanya";
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case 6: return "Hynix";
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default: return "Unknown";
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}
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}
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#define MR8_DENSITY_SHIFT 0x2
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#define MR8_DENSITY_MASK (0xF << 0x2)
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static unsigned lpddr2_size(uint32_t mr) {
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switch (mr) {
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case 0x58: return RAM_SIZE_1GB;
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case 0x18: return RAM_SIZE_512MB;
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case 0x14: return RAM_SIZE_256MB;
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case 0x10: return RAM_SIZE_128MB;
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default: return RAM_SIZE_UNKNOWN;
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}
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}
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const char* size_to_string[] = {
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"1GB",
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"512MB",
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"256MB",
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"128MB",
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"UNKNOWN"
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};
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/*****************************************************************************
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* Guts
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*****************************************************************************/
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ALWAYS_INLINE inline void clkman_update_begin() {
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CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_UPDATE_SET;
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SCLKU_DEBUG(printf("%s: waiting for ACCPT (%X) ...\n", __FUNCTION__, CM_SDCCTL));
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SCLKU_DEBUG(logf("waiting for ACCPT (%X) ...\n", CM_SDCCTL));
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for (;;) if (CM_SDCCTL & CM_SDCCTL_ACCPT_SET) break;
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SCLKU_DEBUG(printf("%s: ACCPT received! (%X)\n", __FUNCTION__, CM_SDCCTL));
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SCLKU_DEBUG(logf("ACCPT received! (%X)\n", CM_SDCCTL));
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}
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ALWAYS_INLINE inline void sdram_clkman_update_end() {
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ALWAYS_INLINE inline void clkman_update_end() {
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CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_UPDATE_CLR);
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SCLKU_DEBUG(printf("%s: waiting for ACCPT clear (%X) ...\n", __FUNCTION__, CM_SDCCTL));
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SCLKU_DEBUG(logf("waiting for ACCPT clear (%X) ...\n", CM_SDCCTL));
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for (;;) if ((CM_SDCCTL & CM_SDCCTL_ACCPT_SET) == 0) break;
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SCLKU_DEBUG(printf("%s: ACCPT cleared! (%X)\n", __FUNCTION__, CM_SDCCTL));
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SCLKU_DEBUG(logf("ACCPT cleared! (%X)\n", CM_SDCCTL));
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}
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ALWAYS_INLINE void sdram_reset_phy_lines() {
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SIP_DEBUG(printf("%s: resetting APHY/DPHY lines ...\n", __FUNCTION__));
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ALWAYS_INLINE void reset_phy_dll() {
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SIP_DEBUG(logf("resetting aphy and dphy dlls ...\n", __FUNCTION__));
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/* politely tell sdc that we'll be messing with address lines */
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APHY_CSR_PHY_BIST_CNTRL_SPR = 0x30;
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@ -64,77 +124,182 @@ ALWAYS_INLINE void sdram_reset_phy_lines() {
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DPHY_CSR_GLBL_DQ_DLL_RESET = 0x0;
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APHY_CSR_GLBL_ADDR_DLL_RESET = 0x0;
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SIP_DEBUG(printf("%s: waiting for DPHY master PLL to lock ...\n", __FUNCTION__));
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SIP_DEBUG(logf("waiting for dphy master dll to lock ...\n", __FUNCTION__));
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for (;;) if ((DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT & 0xFFFF) == 0xFFFF) break;
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SIP_DEBUG(printf("%s: DPHY master PLL locked!\n", __FUNCTION__));
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SIP_DEBUG(logf("dphy master dll locked!\n", __FUNCTION__));
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}
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void sdram_init_late() {
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typedef struct {
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uint32_t max_freq;
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uint32_t RL;
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uint32_t tRPab;
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uint32_t tRPpb;
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uint32_t tRCD;
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uint32_t tWR;
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uint32_t tRASmin;
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uint32_t tRRD;
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uint32_t tWTR;
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uint32_t tXSR;
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uint32_t tXP;
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uint32_t tRFCab;
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uint32_t tRTP;
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uint32_t tCKE;
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uint32_t tCKESR;
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uint32_t tDQSCKMAXx2;
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uint32_t tRASmax;
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uint32_t tFAW;
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uint32_t tRC;
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uint32_t tREFI;
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uint32_t tINIT1;
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uint32_t tINIT3;
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uint32_t tINIT5;
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uint32_t rowbits;
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uint32_t colbits;
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uint32_t banklow;
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} lpddr2_timings_t;
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// 7.8 / (1.0 / 400)
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lpddr2_timings_t g_InitSdramParameters = {
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/* SA (us) */
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.tREFI = 3113, //Refresh rate: 3113 * (1.0 / 400) = 7.78us
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/* SC (ns) */
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.tRFCab = 50,
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.tRRD = 2,
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.tWR = 7,
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.tWTR = 4,
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/* SD (ns) */
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.tRPab = 7,
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.tRC = 24,
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.tXP = 1,
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.tRASmin = 15,
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.tRPpb = 6,
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.tRCD = 6,
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/* SE (ns) */
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.tFAW = 18,
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.tRTP = 1,
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.tXSR = 54,
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/* PT */
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.tINIT1 = 40, // Minimum CKE low time after completion of power ramp: 40 * (1.0 / 0.4) = 100ns
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.tINIT3 = 79800, // Minimum Idle time after first CKE assertion: 79800 * (1.0 / 400) = 199.5us ~ 200us
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.tINIT5 = 3990, //Max DAI: 3990* (1.0 / 400) = 9.9us ~ 10us
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/* SB */
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.rowbits = 2,
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.colbits = 1,
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.banklow = 2
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};
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void reset_with_timing(lpddr2_timings_t* T) {
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uint32_t ctrl = 0x4;
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SD_CS = (SD_CS & ~(SD_CS_DEL_KEEP_SET|SD_CS_DPD_SET|SD_CS_RESTRT_SET)) | SD_CS_STBY_SET;
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/* wait for SDRAM controller to go down */
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SIP_DEBUG(printf("%s: waiting for SDRAM controller to go down (%X) ...\n", __FUNCTION__, SD_CS));
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SIP_DEBUG(logf("waiting for SDRAM controller to go down (%X) ...\n", SD_CS));
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for (;;) if ((SD_CS & SD_CS_SDUP_SET) == 0) break;
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SIP_DEBUG(printf("%s: SDRAM controller down!\n", __FUNCTION__));
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SIP_DEBUG(logf("SDRAM controller down!\n"));
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/* disable SDRAM clock */
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sdram_clkman_update_begin();
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clkman_update_begin();
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CM_SDCCTL = (CM_SDCCTL & ~(CM_SDCCTL_ENAB_SET|CM_SDCCTL_CTRL_SET)) | CM_PASSWORD;
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sdram_clkman_update_end();
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clkman_update_end();
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SIP_DEBUG(printf("%s: SDRAM clock disabled!\n", __FUNCTION__));
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SIP_DEBUG(logf("SDRAM clock disabled!\n"));
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/* left */
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/*
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* Migrate over to master PLL.
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*/
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APHY_CSR_DDR_PLL_PWRDWN = 0;
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APHY_CSR_DDR_PLL_GLOBAL_RESET = 0;
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APHY_CSR_DDR_PLL_POST_DIV_RESET = 0;
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APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 = (1 << 16) | 0x53 /* magic */;
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/* 400MHz */
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APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 = (1 << 16) | 0x53;
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APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 = 0;
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APHY_CSR_DDR_PLL_MDIV_VALUE = 0;
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APHY_CSR_DDR_PLL_GLOBAL_RESET = 1;
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SIP_DEBUG(printf("%s: waiting for APHY DDR PLL to lock ...\n", __FUNCTION__));
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SIP_DEBUG(logf("waiting for master ddr pll to lock ...\n"));
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for (;;) if (APHY_CSR_DDR_PLL_LOCK_STATUS & (1 << 16)) break;
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SIP_DEBUG(printf("%s: APHY DDR PLL locked!\n", __FUNCTION__));
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SIP_DEBUG(logf("master ddr pll locked!\n"));
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APHY_CSR_DDR_PLL_POST_DIV_RESET = 1;
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sdram_clkman_update_begin();
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APHY_CSR_DDR_PLL_POST_DIV_RESET = 1;
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clkman_update_begin();
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CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR);
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sdram_clkman_update_end();
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clkman_update_end();
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SIP_DEBUG(printf("%s: CM_SDCCTL = 0x%X\n", __FUNCTION__, CM_SDCCTL));
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SD_SA =
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(T->tREFI << SD_SA_RFSH_T_LSB)
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| SD_SA_PGEHLDE_SET
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| SD_SA_CLKSTOP_SET
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| SD_SA_POWSAVE_SET
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| 0x3214;
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/* second stage magic values */
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SD_SA = 0x0C293395;
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SD_SB = 0x0F9;
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SD_SC = 0x32200743;
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SD_SD = 0x71810F66;
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SD_SE = 0x10412136;
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SD_PT1 = 0x137B828;
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SD_PT2 = 0x0F96;
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SD_MRT = 0x3;
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SD_SB =
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SD_SB_REORDER_SET
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| (T->banklow << SD_SB_BANKLOW_LSB)
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| SD_SB_EIGHTBANK_SET
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| (T->rowbits << SD_SB_ROWBITS_LSB)
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| (T->colbits << SD_SB_COLBITS_LSB);
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sdram_reset_phy_lines();
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logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T->banklow, T->rowbits, T->colbits, SD_SB);
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SD_SC =
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(T->tRFCab << SD_SC_T_RFC_LSB)
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| (T->tRRD << SD_SC_T_RRD_LSB)
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| (T->tWR << SD_SC_T_WR_LSB)
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| (T->tWTR << SD_SC_T_WTR_LSB)
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| (3 << SD_SC_WL_LSB);
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SD_SD =
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(T->tRPab << SD_SD_T_RPab_LSB)
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| (T->tRC << SD_SD_T_RC_LSB)
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| (T->tXP << SD_SD_T_XP_LSB)
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| (T->tRASmin << SD_SD_T_RAS_LSB)
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| (T->tRPpb << SD_SD_T_RPpb_LSB)
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| (T->tRCD << SD_SD_T_RCD_LSB);
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SD_SE =
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(1 << SD_SE_RL_EN_LSB)
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| (4 << SD_SE_RL_LSB)
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| (T->tFAW << SD_SE_T_FAW_LSB)
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| (T->tRTP << SD_SE_T_RTP_LSB)
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| (T->tXSR << SD_SE_T_XSR_LSB);
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SD_PT1 =
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(T->tINIT3 << SD_PT1_T_INIT3_LSB)
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| (T->tINIT1 << SD_PT1_T_INIT1_LSB);
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SD_PT2 =
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T->tINIT5 << SD_PT2_T_INIT5_LSB;
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SD_MRT =
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0x3 << SD_MRT_T_MRW_LSB;
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reset_phy_dll();
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/* wait for address line pll to come back */
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SIP_DEBUG(printf("%s: waiting for APHY global PLL to lock ...\n", __FUNCTION__));
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SIP_DEBUG(logf("waiting for address dll to lock ...\n"));
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for (;;) if (APHY_CSR_GLBL_ADR_DLL_LOCK_STAT == 3) break;
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SIP_DEBUG(printf("%s: APHY global PLL locked!\n", __FUNCTION__));
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SIP_DEBUG(logf("address dll locked!\n"));
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/* tell sdc we're done messing with address lines */
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APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
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/* woo, turn on sdram! */
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SD_CS = (0x200042 & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;
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SD_CS =
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(((4 << SD_CS_ASHDN_T_LSB)
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| SD_CS_STATEN_SET
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| SD_CS_EN_SET)
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& ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET;
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}
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unsigned int sdram_read_mr(unsigned int addr) {
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unsigned int read_mr(unsigned int addr) {
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while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
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SD_MR = addr & 0xFF;
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unsigned int mrr;
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@ -142,7 +307,7 @@ unsigned int sdram_read_mr(unsigned int addr) {
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return mrr;
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}
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unsigned int sdram_write_mr(unsigned int addr, unsigned int data, bool wait) {
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unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) {
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while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
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SD_MR = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET;
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@ -161,98 +326,78 @@ unsigned int sdram_write_mr(unsigned int addr, unsigned int data, bool wait) {
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}
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}
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void sdram_reset_phy() {
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printf("%s: resetting SDRAM PHY ...\n", __FUNCTION__);
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void reset_phy() {
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logf("%s: resetting SDRAM PHY ...\n", __FUNCTION__);
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/* reset PHYC */
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SD_PHYC = SD_PHYC_PHYRST_SET;
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udelay(64);
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SD_PHYC = 0;
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printf("%s: resetting DPHY CTRL ...\n", __FUNCTION__);
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logf("%s: resetting DPHY CTRL ...\n", __FUNCTION__);
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DPHY_CSR_DQ_PHY_MISC_CTRL = 0x7;
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DPHY_CSR_DQ_PAD_MISC_CTRL = 0x0;
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DPHY_CSR_BOOT_READ_DQS_GATE_CTRL = 0x11;
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sdram_reset_phy_lines();
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reset_phy_dll();
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APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0;
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}
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static void sdram_set_clock_source(unsigned int source, unsigned int div_) {
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CM_SDCDIV = CM_PASSWORD | (div_ << CM_SDCDIV_DIV_LSB);
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static void switch_to_cprman_clock(unsigned int source, unsigned int div) {
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CM_SDCDIV = CM_PASSWORD | (div << CM_SDCDIV_DIV_LSB);
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CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_SRC_CLR) | source;
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CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_ENAB_SET;
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printf("%s: source set to %d, div to %d, waiting for BUSY set (%X) ... \n", __FUNCTION__, source, div_, CM_SDCCTL);
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logf("switching sdram to cprman clock (src=%d, div=%d), waiting for busy (%X) ...\n", source, div, CM_SDCCTL);
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for (;;) if (CM_SDCCTL & CM_SDCCTL_BUSY_SET) break;
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printf("%s: BUSY set! (%X)\n", __FUNCTION__, CM_SDCCTL);
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logf("busy set, switch complete!\n");
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}
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static void sdram_init_clkman()
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static void init_clkman()
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{
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uint32_t ctrl = 0;
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sdram_clkman_update_begin();
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clkman_update_begin();
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CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR);
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sdram_clkman_update_end();
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clkman_update_end();
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}
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static const char* lpddr2_manufacturer_name(uint32_t mr) {
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switch (mr) {
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case 1: return "Samsung";
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case 2: return "Qimonda";
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case 3: return "Elpida";
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case 4: return "Etron";
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case 5: return "Nanya";
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case 6: return "Hynix";
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default: return "Unknown";
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}
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}
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#define CALL_INIT_CLKMAN init_clkman();
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static const char* lpddr2_density(uint32_t mr) {
|
||||
/*
|
||||
* i'm so stupid, why did i not notice that LPDDR2
|
||||
* spec listed those as bits, not bytes *sigh*
|
||||
*/
|
||||
switch ((mr & 0x33) >> 3) {
|
||||
case 1: return "128MB";
|
||||
case 2: return "256MB";
|
||||
case 3: return "512MB";
|
||||
case 4: return "1GB";
|
||||
case 5: return "2GB";
|
||||
case 6: return "4GB";
|
||||
default: return "Unknown";
|
||||
}
|
||||
}
|
||||
|
||||
static void sdram_calibrate() {
|
||||
/*****************************************************************************
|
||||
* Calibration
|
||||
*****************************************************************************/
|
||||
|
||||
static void calibrate_pvt_early() {
|
||||
/* some hw revisions require different slews */
|
||||
bool st = ((g_CPUID >> 4) & 0xFFF) == 0x14;
|
||||
uint32_t dq_slew = (st ? 2 : 3);
|
||||
|
||||
/* i don't get it, the spec says do not use this register */
|
||||
sdram_write_mr(0xFF, 0, true);
|
||||
write_mr(0xFF, 0, true);
|
||||
/* RL = 6 / WL = 3 */
|
||||
sdram_write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, true);
|
||||
write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, true);
|
||||
|
||||
APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL = 0x333;
|
||||
DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = (dq_slew << 8) | (dq_slew << 4) | 3;
|
||||
|
||||
printf("%s: DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", __FUNCTION__, DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL);
|
||||
logf("DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL);
|
||||
|
||||
/* tell sdc we want to calibrate */
|
||||
APHY_CSR_PHY_BIST_CNTRL_SPR = 0x20;
|
||||
APHY_CSR_PHY_BIST_CNTRL_SPR = BIST_pvt;
|
||||
|
||||
APHY_CSR_ADDR_PVT_COMP_CTRL = 0x1;
|
||||
printf("%s: waiting for address PVT calibration ...\n", __FUNCTION__);
|
||||
/* pvt compensation */
|
||||
APHY_CSR_ADDR_PVT_COMP_CTRL = PVT_calibrate_request;
|
||||
logf("waiting for address PVT calibration ...\n");
|
||||
for (;;) if (APHY_CSR_ADDR_PVT_COMP_STATUS & 2) break;
|
||||
|
||||
DPHY_CSR_DQ_PVT_COMP_CTRL = 0x1;
|
||||
printf("%s: waiting for data PVT calibration ...\n", __FUNCTION__);
|
||||
DPHY_CSR_DQ_PVT_COMP_CTRL = PVT_calibrate_request;
|
||||
logf("waiting for data PVT calibration ...\n");
|
||||
for (;;) if (DPHY_CSR_DQ_PVT_COMP_STATUS & 2) break;
|
||||
|
||||
/* tell sdc we're done calibrating */
|
||||
|
|
@ -261,33 +406,87 @@ static void sdram_calibrate() {
|
|||
/* send calibration command */
|
||||
uint32_t old_mrt = SD_MRT;
|
||||
SD_MRT = 20;
|
||||
printf("%s: waiting for SDRAM calibration command ...\n", __FUNCTION__);
|
||||
logf("waiting for SDRAM calibration command ...\n");
|
||||
SD_MR = LPDDR2_MR_CALIBRATION | (0xFF << 8) | SD_MR_RW_SET | SD_MR_HI_Z_SET;
|
||||
while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {}
|
||||
SD_MRT = old_mrt;
|
||||
|
||||
sdram_write_mr(LPDDR2_MR_IO_CONFIG, st ? 3 : 2, false);
|
||||
write_mr(LPDDR2_MR_IO_CONFIG, st ? 3 : 2, false);
|
||||
}
|
||||
|
||||
static void sdram_selftest()
|
||||
{
|
||||
volatile uint32_t* p = (volatile uint32_t*)RAM_TEST_ADDR;
|
||||
|
||||
printf("Testing SDRAM ...\n");
|
||||
/*****************************************************************************
|
||||
* Late init
|
||||
*****************************************************************************/
|
||||
|
||||
for (int i = 0; i < 0x100000; i++) {
|
||||
p[i] = RAM_TEST_PATTERN;
|
||||
if (p[i] != RAM_TEST_PATTERN)
|
||||
panic("sdram initialization failed (idx=%d exptected=0x%x got=0x%x)", i, RAM_TEST_PATTERN, p[i]);
|
||||
static void init_late() {
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
* Self-test
|
||||
*****************************************************************************/
|
||||
|
||||
#define RT_BASE 0xC0000000
|
||||
|
||||
#define RT_PAT0 0xAAAAAAAA
|
||||
#define RT_PAT1 0xFF00AA00
|
||||
#define RT_PAT2 0x99999999
|
||||
|
||||
#define RT_ASSERT(i_, expected) \
|
||||
if (ram[(i_)] != expected) { \
|
||||
logf("ERROR: At 0x%X, was expecting 0x%X from read, got 0x%X instead!\n", \
|
||||
(uint32_t)&ram[(i_)], \
|
||||
expected, \
|
||||
ram[(i_)]); \
|
||||
panic("SDRAM self test failed!"); \
|
||||
}
|
||||
|
||||
printf("SDRAM test successful!\n");
|
||||
static void selftest_at(uint32_t addr) {
|
||||
volatile uint32_t* ram = (volatile uint32_t*)addr;
|
||||
|
||||
logf("Testing region at 0x%X ...\n", addr);
|
||||
|
||||
for (int i = 0; i < 0x1000; i += 4) {
|
||||
ram[i] = RT_PAT0;
|
||||
ram[i + 1] = RT_PAT1;
|
||||
ram[i + 2] = RT_PAT2;
|
||||
ram[i + 3] = RT_PAT0;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 0x1000; i += 4) {
|
||||
RT_ASSERT(i, RT_PAT0);
|
||||
RT_ASSERT(i + 1, RT_PAT1);
|
||||
RT_ASSERT(i + 2, RT_PAT2);
|
||||
RT_ASSERT(i + 3, RT_PAT0);
|
||||
}
|
||||
}
|
||||
|
||||
static void selftest()
|
||||
{
|
||||
logf("Starting self test ...\n");
|
||||
|
||||
selftest_at(RT_BASE);
|
||||
|
||||
if (g_RAMSize == RAM_SIZE_256MB || g_RAMSize == RAM_SIZE_512MB || g_RAMSize == RAM_SIZE_1GB) {
|
||||
selftest_at(RT_BASE + 0xFF00000);
|
||||
}
|
||||
if (g_RAMSize == RAM_SIZE_512MB || g_RAMSize == RAM_SIZE_1GB) {
|
||||
selftest_at(RT_BASE + 0x1FF00000);
|
||||
}
|
||||
if (g_RAMSize == RAM_SIZE_1GB) {
|
||||
selftest_at(RT_BASE + 0x2FF00000);
|
||||
selftest_at(RT_BASE + 0x3FF00000);
|
||||
}
|
||||
|
||||
logf("Self test successful!\n");
|
||||
}
|
||||
|
||||
#undef RT_ASSERT
|
||||
|
||||
void sdram_init() {
|
||||
uint32_t vendor_id, bc;
|
||||
|
||||
printf("%s: (0) SD_CS = 0x%X\n", __FUNCTION__, SD_CS);
|
||||
logf("(0) SD_CS = 0x%X\n", SD_CS);
|
||||
|
||||
PM_SMPS = PM_PASSWORD | 0x1;
|
||||
A2W_SMPS_LDO1 = A2W_PASSWORD | 0x40000;
|
||||
|
|
@ -301,14 +500,14 @@ void sdram_init() {
|
|||
* the calibration sequence.
|
||||
*/
|
||||
|
||||
sdram_set_clock_source(CM_SRC_OSC, 1);
|
||||
|
||||
sdram_init_clkman();
|
||||
switch_to_cprman_clock(CM_SRC_OSC, 1);
|
||||
|
||||
sdram_reset_phy();
|
||||
CALL_INIT_CLKMAN;
|
||||
|
||||
reset_phy();
|
||||
|
||||
/* magic values */
|
||||
SD_SA = 0x6E3395;
|
||||
SD_SA = 0x006E3395;
|
||||
SD_SB = 0x0F9;
|
||||
SD_SC = 0x6000431;
|
||||
SD_SD = 0x10000011;
|
||||
|
|
@ -319,32 +518,37 @@ void sdram_init() {
|
|||
SD_CS = 0x200042;
|
||||
|
||||
/* wait for SDRAM controller */
|
||||
printf("%s: waiting for SDUP (%X) ...\n", __FUNCTION__, SD_CS);
|
||||
logf("waiting for SDUP (%X) ...\n", SD_CS);
|
||||
for (;;) if (SD_CS & SD_CS_SDUP_SET) break;
|
||||
printf("%s: SDRAM controller has arrived! (%X)\n", __FUNCTION__, SD_CS);
|
||||
logf("SDRAM controller has arrived! (%X)\n", SD_CS);
|
||||
|
||||
/* RL = 6 / WL = 3 */
|
||||
sdram_write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false);
|
||||
sdram_calibrate();
|
||||
write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false);
|
||||
calibrate_pvt_early();
|
||||
|
||||
/* identify installed memory */
|
||||
vendor_id = sdram_read_mr(LPDDR2_MR_MANUFACTURER_ID);
|
||||
vendor_id = read_mr(LPDDR2_MR_MANUFACTURER_ID);
|
||||
if (!MR_REQUEST_SUCCESS(vendor_id)) {
|
||||
panic("vendor id memory register read timed out");
|
||||
}
|
||||
vendor_id = MR_GET_RDATA(vendor_id);
|
||||
|
||||
bc = sdram_read_mr(LPDDR2_MR_METRICS);
|
||||
bc = read_mr(LPDDR2_MR_METRICS);
|
||||
if (!MR_REQUEST_SUCCESS(bc)) {
|
||||
panic("basic configuration memory register read timed out");
|
||||
}
|
||||
bc = MR_GET_RDATA(bc);
|
||||
|
||||
printf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n",
|
||||
g_RAMSize = lpddr2_size(bc);
|
||||
|
||||
logf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n",
|
||||
lpddr2_manufacturer_name(vendor_id),
|
||||
lpddr2_density(bc),
|
||||
size_to_string[g_RAMSize],
|
||||
bc);
|
||||
|
||||
if (g_RAMSize == RAM_SIZE_UNKNOWN)
|
||||
panic("unknown ram size (MR8 response was 0x%X)", bc);
|
||||
|
||||
/*
|
||||
* STEP 2:
|
||||
* after calibration, enable high-freq SDRAM PLL. because we're
|
||||
|
|
@ -354,7 +558,21 @@ void sdram_init() {
|
|||
* mess with SDRAM clock it would need to do that.
|
||||
*/
|
||||
|
||||
sdram_init_late();
|
||||
sdram_selftest();
|
||||
if (g_RAMSize == RAM_SIZE_1GB) {
|
||||
logf("*** USING LOW tREFI (~7.8us) FOR 1GB, YOUR RAM MAY LEAK!!!!\n");
|
||||
|
||||
g_InitSdramParameters.colbits = 3;
|
||||
g_InitSdramParameters.rowbits = 3;
|
||||
g_InitSdramParameters.banklow = 3;
|
||||
}
|
||||
else if (g_RAMSize == RAM_SIZE_512MB) {
|
||||
logf("*** USING LOW tREFI (~7.8us) FOR 512MB, YOUR RAM MAY LEAK!!!!\n");
|
||||
|
||||
g_InitSdramParameters.colbits = 2;
|
||||
}
|
||||
|
||||
reset_with_timing(&g_InitSdramParameters);
|
||||
init_late();
|
||||
selftest();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user