From 49a15e3a39fc566c5e775b53c277841e29856b0e Mon Sep 17 00:00:00 2001 From: kristina Date: Mon, 16 May 2016 03:01:46 +0100 Subject: [PATCH] Initial commit --- LICENSE | 241 + Makefile | 81 + README.md | 34 + arm_chainloader/Makefile | 72 + arm_chainloader/chainloader.h | 5 + arm_chainloader/drivers/uart.c | 10 + arm_chainloader/firmware_rendezvous.c | 34 + arm_chainloader/linker.lds | 10 + arm_chainloader/main.c | 7 + arm_chainloader/start.s | 24 + arm_loader.c | 276 + bcm2708_chip/README.txt | 29 + bcm2708_chip/apb_arbiter_control.h | 7 + bcm2708_chip/apb_async_bridge_ctrl.h | 245 + bcm2708_chip/arm_control.h | 404 + bcm2708_chip/aux_io.h | 170 + bcm2708_chip/ave_in.h | 334 + bcm2708_chip/ave_out.h | 216 + bcm2708_chip/axi_dma0.h | 257 + bcm2708_chip/axi_dma1.h | 257 + bcm2708_chip/axi_dma15.h | 257 + bcm2708_chip/axi_dma2.h | 257 + bcm2708_chip/axi_dma3.h | 257 + bcm2708_chip/axi_dma4.h | 257 + bcm2708_chip/axi_dma5.h | 257 + bcm2708_chip/axi_dma6.h | 257 + bcm2708_chip/axi_dma7.h | 247 + bcm2708_chip/axi_dma8.h | 247 + bcm2708_chip/axi_dma_lite10.h | 229 + bcm2708_chip/axi_dma_lite11.h | 229 + bcm2708_chip/axi_dma_lite12.h | 229 + bcm2708_chip/axi_dma_lite13.h | 229 + bcm2708_chip/axi_dma_lite14.h | 229 + bcm2708_chip/axi_dma_lite7.h | 229 + bcm2708_chip/axi_dma_lite8.h | 229 + bcm2708_chip/axi_dma_lite9.h | 229 + bcm2708_chip/axi_dma_top.h | 165 + bcm2708_chip/axi_performance0.h | 259 + bcm2708_chip/axi_performance1.h | 259 + bcm2708_chip/cam0.h | 199 + bcm2708_chip/cam0_a0.h | 131 + bcm2708_chip/cam1.h | 199 + bcm2708_chip/cam1_a0.h | 131 + bcm2708_chip/camccp.h | 138 + bcm2708_chip/ccp2tx.h | 260 + bcm2708_chip/ccp2tx_a0.h | 30 + bcm2708_chip/cdp.h | 19 + bcm2708_chip/clkman_image.h | 75 + bcm2708_chip/cpg.h | 36 + bcm2708_chip/cpi.h | 48 + bcm2708_chip/cpr_apb2wtap.h | 2037 +++++ bcm2708_chip/cpr_apb2wtap_a0.h | 985 ++ bcm2708_chip/cpr_clkman.h | 2400 +++++ bcm2708_chip/cpr_clkman_a0.h | 4299 +++++++++ bcm2708_chip/cpr_powman.h | 840 ++ bcm2708_chip/cpr_powman_a0.h | 809 ++ bcm2708_chip/cryptohw.h | 67 + bcm2708_chip/csi2.h | 433 + bcm2708_chip/dpi.h | 7 + bcm2708_chip/dsi.h | 178 + bcm2708_chip/dsi4.h | 124 + bcm2708_chip/emmc.h | 1276 +++ bcm2708_chip/flow_config.tcl | 2 + bcm2708_chip/fpga_microblaze.h | 44 + bcm2708_chip/fpga_peripheral.h | 206 + bcm2708_chip/gpio.h | 735 ++ bcm2708_chip/h264.h | 6 + bcm2708_chip/hardware.h | 142 + bcm2708_chip/hdcp.h | 37 + bcm2708_chip/hdmi.h | 319 + bcm2708_chip/hdmicore.h | 1256 +++ bcm2708_chip/hvs.h | 297 + bcm2708_chip/i2c0.h | 34 + bcm2708_chip/i2c1.h | 34 + bcm2708_chip/i2c2.h | 34 + bcm2708_chip/i2c_spi_slv.h | 427 + bcm2708_chip/intctrl0.h | 83 + bcm2708_chip/intctrl1.h | 83 + bcm2708_chip/isp.h | 6 + bcm2708_chip/israel_bg_dctram.h | 8284 +++++++++++++++++ bcm2708_chip/israel_bg_instr.h | 608 ++ bcm2708_chip/israel_dsp_registers.h | 1358 +++ bcm2708_chip/jpeg_top.h | 31 + bcm2708_chip/l2_cache_ctrl.h | 88 + bcm2708_chip/mphi.h | 717 ++ bcm2708_chip/multicore_sync.h | 446 + bcm2708_chip/nexus_uba.h | 6 + bcm2708_chip/otp.h | 33 + bcm2708_chip/pcm.h | 367 + bcm2708_chip/perfmon.h | 11 + bcm2708_chip/peri_image_arb_ctrl.h | 36 + bcm2708_chip/pixel_valve0.h | 42 + bcm2708_chip/pixel_valve1.h | 42 + bcm2708_chip/pixel_valve2.h | 42 + bcm2708_chip/pwm.h | 276 + bcm2708_chip/register_map.h | 87 + bcm2708_chip/register_map_macros.h | 1774 ++++ bcm2708_chip/rng.h | 18 + bcm2708_chip/rng_a0.h | 43 + bcm2708_chip/rnghw.h | 44 + bcm2708_chip/sdc_addr_front.h | 39 + bcm2708_chip/sdc_ctrl.h | 1316 +++ bcm2708_chip/sdc_dq_front.h | 40 + bcm2708_chip/sdhost.h | 259 + bcm2708_chip/slimbus.h | 311 + bcm2708_chip/slimbus_a0.h | 227 + bcm2708_chip/smi.h | 650 ++ bcm2708_chip/spi_master.h | 107 + bcm2708_chip/sv_chip_regmap.h | 11455 ++++++++++++++++++++++++ bcm2708_chip/system_arbiter_ctrl.h | 437 + bcm2708_chip/tectl.h | 30 + bcm2708_chip/tectl_a0.h | 21 + bcm2708_chip/tempsens.h | 71 + bcm2708_chip/testbus.h | 219 + bcm2708_chip/thread_ctrl.h | 119 + bcm2708_chip/timer.h | 32 + bcm2708_chip/txp.h | 137 + bcm2708_chip/uart.h | 169 + bcm2708_chip/usb.h | 2889 ++++++ bcm2708_chip/v3d.h | 306 + bcm2708_chip/vcodec.h | 793 ++ bcm2708_chip/vec.h | 140 + bcm2708_chip/vpu_arb_ctrl.h | 70 + bcm2708_chip/vpu_l1_cache_ctrl.h | 455 + buildall.sh | 19 + chainloader_inc.s | 28 + ghetto.s | 12 + hardware.h | 74 + hardware_vc4.h | 1829 ++++ lib/common.h | 55 + lib/memcpy.c | 11 + lib/panic.c | 36 + lib/stdarg.h | 9 + lib/udelay.c | 37 + lib/xprintf.c | 191 + lib/xprintf.h | 36 + romstage.c | 183 + sdram.c | 360 + start.s | 165 + trap.c | 53 + 140 files changed, 63473 insertions(+) create mode 100755 LICENSE create mode 100755 Makefile create mode 100755 README.md create mode 100755 arm_chainloader/Makefile create mode 100755 arm_chainloader/chainloader.h create mode 100755 arm_chainloader/drivers/uart.c create mode 100755 arm_chainloader/firmware_rendezvous.c create mode 100755 arm_chainloader/linker.lds create mode 100755 arm_chainloader/main.c create mode 100755 arm_chainloader/start.s create mode 100755 arm_loader.c create mode 100755 bcm2708_chip/README.txt create mode 100755 bcm2708_chip/apb_arbiter_control.h create mode 100755 bcm2708_chip/apb_async_bridge_ctrl.h create mode 100755 bcm2708_chip/arm_control.h create mode 100755 bcm2708_chip/aux_io.h create mode 100755 bcm2708_chip/ave_in.h create mode 100755 bcm2708_chip/ave_out.h create mode 100755 bcm2708_chip/axi_dma0.h create mode 100755 bcm2708_chip/axi_dma1.h create mode 100755 bcm2708_chip/axi_dma15.h create mode 100755 bcm2708_chip/axi_dma2.h create mode 100755 bcm2708_chip/axi_dma3.h create mode 100755 bcm2708_chip/axi_dma4.h create mode 100755 bcm2708_chip/axi_dma5.h create mode 100755 bcm2708_chip/axi_dma6.h create mode 100755 bcm2708_chip/axi_dma7.h create mode 100755 bcm2708_chip/axi_dma8.h create mode 100755 bcm2708_chip/axi_dma_lite10.h create mode 100755 bcm2708_chip/axi_dma_lite11.h create mode 100755 bcm2708_chip/axi_dma_lite12.h create mode 100755 bcm2708_chip/axi_dma_lite13.h create mode 100755 bcm2708_chip/axi_dma_lite14.h create mode 100755 bcm2708_chip/axi_dma_lite7.h create mode 100755 bcm2708_chip/axi_dma_lite8.h create mode 100755 bcm2708_chip/axi_dma_lite9.h create mode 100755 bcm2708_chip/axi_dma_top.h create mode 100755 bcm2708_chip/axi_performance0.h create mode 100755 bcm2708_chip/axi_performance1.h create mode 100755 bcm2708_chip/cam0.h create mode 100755 bcm2708_chip/cam0_a0.h create mode 100755 bcm2708_chip/cam1.h create mode 100755 bcm2708_chip/cam1_a0.h create mode 100755 bcm2708_chip/camccp.h create mode 100755 bcm2708_chip/ccp2tx.h create mode 100755 bcm2708_chip/ccp2tx_a0.h create mode 100755 bcm2708_chip/cdp.h create mode 100755 bcm2708_chip/clkman_image.h create mode 100755 bcm2708_chip/cpg.h create mode 100755 bcm2708_chip/cpi.h create mode 100755 bcm2708_chip/cpr_apb2wtap.h create mode 100755 bcm2708_chip/cpr_apb2wtap_a0.h create mode 100755 bcm2708_chip/cpr_clkman.h create mode 100755 bcm2708_chip/cpr_clkman_a0.h create mode 100755 bcm2708_chip/cpr_powman.h create mode 100755 bcm2708_chip/cpr_powman_a0.h create mode 100755 bcm2708_chip/cryptohw.h create mode 100755 bcm2708_chip/csi2.h create mode 100755 bcm2708_chip/dpi.h create mode 100755 bcm2708_chip/dsi.h create mode 100755 bcm2708_chip/dsi4.h create mode 100755 bcm2708_chip/emmc.h create mode 100755 bcm2708_chip/flow_config.tcl create mode 100755 bcm2708_chip/fpga_microblaze.h create mode 100755 bcm2708_chip/fpga_peripheral.h create mode 100755 bcm2708_chip/gpio.h create mode 100755 bcm2708_chip/h264.h create mode 100755 bcm2708_chip/hardware.h create mode 100755 bcm2708_chip/hdcp.h create mode 100755 bcm2708_chip/hdmi.h create mode 100755 bcm2708_chip/hdmicore.h create mode 100755 bcm2708_chip/hvs.h create mode 100755 bcm2708_chip/i2c0.h create mode 100755 bcm2708_chip/i2c1.h create mode 100755 bcm2708_chip/i2c2.h create mode 100755 bcm2708_chip/i2c_spi_slv.h create mode 100755 bcm2708_chip/intctrl0.h create mode 100755 bcm2708_chip/intctrl1.h create mode 100755 bcm2708_chip/isp.h create mode 100755 bcm2708_chip/israel_bg_dctram.h create mode 100755 bcm2708_chip/israel_bg_instr.h create mode 100755 bcm2708_chip/israel_dsp_registers.h create mode 100755 bcm2708_chip/jpeg_top.h create mode 100755 bcm2708_chip/l2_cache_ctrl.h create mode 100755 bcm2708_chip/mphi.h create mode 100755 bcm2708_chip/multicore_sync.h create mode 100755 bcm2708_chip/nexus_uba.h create mode 100755 bcm2708_chip/otp.h create mode 100755 bcm2708_chip/pcm.h create mode 100755 bcm2708_chip/perfmon.h create mode 100755 bcm2708_chip/peri_image_arb_ctrl.h create mode 100755 bcm2708_chip/pixel_valve0.h create mode 100755 bcm2708_chip/pixel_valve1.h create mode 100755 bcm2708_chip/pixel_valve2.h create mode 100755 bcm2708_chip/pwm.h create mode 100755 bcm2708_chip/register_map.h create mode 100755 bcm2708_chip/register_map_macros.h create mode 100755 bcm2708_chip/rng.h create mode 100755 bcm2708_chip/rng_a0.h create mode 100755 bcm2708_chip/rnghw.h create mode 100755 bcm2708_chip/sdc_addr_front.h create mode 100755 bcm2708_chip/sdc_ctrl.h create mode 100755 bcm2708_chip/sdc_dq_front.h create mode 100755 bcm2708_chip/sdhost.h create mode 100755 bcm2708_chip/slimbus.h create mode 100755 bcm2708_chip/slimbus_a0.h create mode 100755 bcm2708_chip/smi.h create mode 100755 bcm2708_chip/spi_master.h create mode 100755 bcm2708_chip/sv_chip_regmap.h create mode 100755 bcm2708_chip/system_arbiter_ctrl.h create mode 100755 bcm2708_chip/tectl.h create mode 100755 bcm2708_chip/tectl_a0.h create mode 100755 bcm2708_chip/tempsens.h create mode 100755 bcm2708_chip/testbus.h create mode 100755 bcm2708_chip/thread_ctrl.h create mode 100755 bcm2708_chip/timer.h create mode 100755 bcm2708_chip/txp.h create mode 100755 bcm2708_chip/uart.h create mode 100755 bcm2708_chip/usb.h create mode 100755 bcm2708_chip/v3d.h create mode 100755 bcm2708_chip/vcodec.h create mode 100755 bcm2708_chip/vec.h create mode 100755 bcm2708_chip/vpu_arb_ctrl.h create mode 100755 bcm2708_chip/vpu_l1_cache_ctrl.h create mode 100755 buildall.sh create mode 100755 chainloader_inc.s create mode 100755 ghetto.s create mode 100755 hardware.h create mode 100755 hardware_vc4.h create mode 100755 lib/common.h create mode 100755 lib/memcpy.c create mode 100755 lib/panic.c create mode 100755 lib/stdarg.h create mode 100755 lib/udelay.c create mode 100755 lib/xprintf.c create mode 100755 lib/xprintf.h create mode 100755 romstage.c create mode 100755 sdram.c create mode 100755 start.s create mode 100755 trap.c diff --git a/LICENSE b/LICENSE new file mode 100755 index 0000000..2f6a216 --- /dev/null +++ b/LICENSE @@ -0,0 +1,241 @@ +Code copyrighted to Broadom Corporation is released under BSD 3-Clause License +============================================================================== + +Copyright (c) 2009-2014, Broadcom Corporation All rights reserved. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, +OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO +YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF +THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING +RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO +OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS diff --git a/Makefile b/Makefile new file mode 100755 index 0000000..898bf05 --- /dev/null +++ b/Makefile @@ -0,0 +1,81 @@ + +TARGET_BOOTCODE = bootcode.bin + +# +# when building bootcode.bin, always ensure start.s is at the top, providing +# the 0x200 byte long header and some init code. +# +SRCS = \ + start.s \ + romstage.c \ + sdram.c \ + arm_loader.c \ + trap.c \ + lib/xprintf.c \ + lib/panic.c \ + lib/udelay.c \ + lib/memcpy.c \ + chainloader_inc.s + +ARCH = vc4 + +BUILD_DIR = build +TARGET_BUILD_DIR = $(BUILD_DIR)/$(ARCH)-objects +PRODUCT_DIRECTORY = $(BUILD_DIR) + +NO_COLOR="" +OK_COLOR="" +ERROR_COLOR="" +WARN_COLOR="" + +.PHONY: default all clean create_build_directory device + +default: $(TARGET_BOOTCODE) + +OBJ := $(addprefix $(TARGET_BUILD_DIR)/, $(addsuffix .o, $(basename $(SRCS)))) + +CROSS_COMPILE = /Developer/vc4-toolchain/prefix/bin/vc4-elf- +CC = $(CROSS_COMPILE)gcc +AS = $(CC) +OBJCOPY = $(CROSS_COMPILE)objcopy +LINKFLAGS = -nostdlib -nostartfiles +CFLAGS = -c -nostdlib -std=c11 +ASFLAGS = -c -nostdlib -x assembler-with-cpp + +HEADERS := \ + $(shell find . -type f -name '*.h') \ + $(shell find . -type f -name '*.hpp') + +create_build_directory: + @mkdir -p $(TARGET_BUILD_DIR) + @mkdir -p $(PRODUCT_DIRECTORY) + +CREATE_SUBDIR = \ + @DIR="$(dir $@)"; \ + if [ ! -d $$DIR ]; then mkdir -p $$DIR; fi + + +# +# rules to build c/asm files. +# +$(TARGET_BUILD_DIR)/%.o: %.c $(HEADERS) + $(CREATE_SUBDIR) + @echo $(WARN_COLOR)CC $(NO_COLOR) $@ + @$(CC) $(CFLAGS) $< -o $@ + +$(TARGET_BUILD_DIR)/%.o: %.s $(HEADERS) + $(CREATE_SUBDIR) + @echo $(WARN_COLOR)AS $(NO_COLOR) $@ + @$(AS) $(ASFLAGS) $< -o $@ + +.PRECIOUS: $(OBJ) + +$(TARGET_BOOTCODE): create_build_directory $(OBJ) + @echo $(WARN_COLOR)LD $(NO_COLOR) $@.elf + @$(CC) $(LINKFLAGS) $(OBJ) -o $(PRODUCT_DIRECTORY)/$@.elf + @echo $(WARN_COLOR)OBJ$(NO_COLOR) $@ + @$(OBJCOPY) -O binary $(PRODUCT_DIRECTORY)/$@.elf $(PRODUCT_DIRECTORY)/$@ + +clean: + @echo $(ERROR_COLOR)CLEAN$(NO_COLOR) + @-rm -rf ./$(BUILD_DIR) \ No newline at end of file diff --git a/README.md b/README.md new file mode 100755 index 0000000..6cc1def --- /dev/null +++ b/README.md @@ -0,0 +1,34 @@ +# Minimal Raspberry Pi VPU firmware +This is a small firmware for RPi VPU (VideoCore4) versions 1/2/3 that is capable of initializing UART, VPU PLL (PLLC) and ARM itself. It's intended to be used instead of stock `bootcode.bin` on RPi's SD card. You **need** to have UART to see anything meaningful as far as output goes. + +This has been tested on RPi1 Model B (Hynix PoP DDR), RPi 2 Model B and RPi 3 Model B (both Elpida DDR). + +If you want to contact me because you're interested in contributing, you can message `kristina` on Freenode, but I would suggest talking in `#raspberrypi-internals` instead. + +## Building + +You need Julian Brown's VC4 toolchain to build this (https://github.com/puppeh/vc4-toolchain) as well as a arm-none-eabi-toolchain. You can tweak the paths to it in CROSS_COMPILE in `Makefile` (for VC4) and for ARM in `arm_chainloader/Makefile`. After you've done it, run `buildall.sh` and you should have a blob in `build/bootcode.bin`. + +## Technical Details +The firmware is split into two parts, a VC4 part and and ARM part. The VC4 part initializes PLLC and moves VPU over to it, and then brings up UART. It then performs SDRAM initialization, making SDRAM available at `0xC0000000` (uncached alias). The ARM loader will do ARM initialization and then copy the ARM bootloader that's embedded in it to the alias. It will then map it to `0x0` in ARM's memory space and start ARM. The code under `arm_chainloader` is what will run on the ARM. + +The current makefiles in the ARM part of it aim at **RPi1** (ie. ARMv6) but they can be changed to ARMv7 if you want to build it for a newer model. I tested it on all RPi models and it works without any issues as far as I can tell (ARM can access peripherals and memory just fine as AXI supervisor). + +**Beware:** This doesn't handle SMP at the moment so if you run this on RPi2 and above, all ARM cores will start executing the ARM bootloader code at the start which could cause problems. I will fix this soon. + +## Issues + * PLL rate on ARM is slow, it's a bit annoying. Need to tweak the PLL rate later. + * Code that prints SDRAM capacity is a bit wrong, I need to fix it, but it makes no functional difference. + * At the moment the ARM side of the bootloader doesn't do anything aside from printing a line to UART. I'm going to add an SDHOST driver to load the next stage bootloader to it at some point. + * It only maps a small amount of memory at the moment. You can tweak it in `arm_loader.c` if you want. + +## Does/Will it boot Linux? + +Eventually maybe. Since `start.elf` is responsible for clock and power management (all registers in the `cpr` block), these drivers will have to be rewritten on ARM (or even on the open source VC4) to have any meaningful peripherals working properly (for example HDMI/DMA/Pixel Valve/Whatever). UART and GPIOs do work though. + +## Thanks To + * **Herman Hermitage** for his VC4 documentation and for helping me with working out suitable ARM PLL configurations. + * **Julian Brown** for reviewing my code and for his awesome VC4 toolchain. + * **phire** for reviewing my code. + * **Broadcom** for their header release. + * Various other people not mentioned here. \ No newline at end of file diff --git a/arm_chainloader/Makefile b/arm_chainloader/Makefile new file mode 100755 index 0000000..05b8945 --- /dev/null +++ b/arm_chainloader/Makefile @@ -0,0 +1,72 @@ + +TARGET_ARM_CHAINLOADER = arm_chainloader.bin + +SRCS = \ + start.s \ + drivers/uart.c \ + ../lib/xprintf.c \ + firmware_rendezvous.c \ + main.c + +ARCH = armv6zk + +BUILD_DIR = build +TARGET_BUILD_DIR = $(BUILD_DIR)/$(ARCH)-objects +PRODUCT_DIRECTORY = $(BUILD_DIR) + +NO_COLOR="" +OK_COLOR="" +ERROR_COLOR="" +WARN_COLOR="" + +.PHONY: default all clean create_build_directory device + +default: $(TARGET_ARM_CHAINLOADER) + +OBJ := $(addprefix $(TARGET_BUILD_DIR)/, $(addsuffix .o, $(basename $(SRCS)))) + +CROSS_COMPILE = arm-none-eabi- +CC = $(CROSS_COMPILE)gcc +AS = $(CC) +OBJCOPY = $(CROSS_COMPILE)objcopy +LINKFLAGS = -nostdlib -march=$(ARCH) -Wl,--build-id=none -T linker.lds +COMMON_FLAGS = -c -nostdlib -nostartfiles -ffreestanding -march=$(ARCH) -I../ -I./ -mfpu=vfp -mfloat-abi=hard -mtune=arm1176jzf-s +CFLAGS = $(COMMON_FLAGS) -std=c11 +ASFLAGS = $(COMMON_FLAGS) -x assembler-with-cpp + +HEADERS := \ + $(shell find . -type f -name '*.h') \ + $(shell find . -type f -name '*.hpp') + +create_build_directory: + @mkdir -p $(TARGET_BUILD_DIR) + @mkdir -p $(PRODUCT_DIRECTORY) + +CREATE_SUBDIR = \ + @DIR="$(dir $@)"; \ + if [ ! -d $$DIR ]; then mkdir -p $$DIR; fi + +# +# rules to build c/asm files. +# +$(TARGET_BUILD_DIR)/%.o: %.c $(HEADERS) + $(CREATE_SUBDIR) + @echo $(WARN_COLOR)CC $(NO_COLOR) $@ + @$(CC) $(CFLAGS) $< -o $@ + +$(TARGET_BUILD_DIR)/%.o: %.s $(HEADERS) + $(CREATE_SUBDIR) + @echo $(WARN_COLOR)AS $(NO_COLOR) $@ + @$(AS) $(ASFLAGS) $< -o $@ + +.PRECIOUS: $(OBJ) + +$(TARGET_ARM_CHAINLOADER): create_build_directory $(OBJ) + @echo $(WARN_COLOR)LD $(NO_COLOR) $@.elf + @$(CC) $(LINKFLAGS) $(OBJ) -o $(PRODUCT_DIRECTORY)/$@.elf -lgcc + @echo $(WARN_COLOR)OBJ$(NO_COLOR) $@ + @$(OBJCOPY) -O binary $(PRODUCT_DIRECTORY)/$@.elf $(PRODUCT_DIRECTORY)/$@ + +clean: + @echo $(ERROR_COLOR)CLEAN$(NO_COLOR) + @-rm -rf ./$(BUILD_DIR) \ No newline at end of file diff --git a/arm_chainloader/chainloader.h b/arm_chainloader/chainloader.h new file mode 100755 index 0000000..4aa7626 --- /dev/null +++ b/arm_chainloader/chainloader.h @@ -0,0 +1,5 @@ +#pragma once + +#include + +#define printf xprintf \ No newline at end of file diff --git a/arm_chainloader/drivers/uart.c b/arm_chainloader/drivers/uart.c new file mode 100755 index 0000000..3b20ac1 --- /dev/null +++ b/arm_chainloader/drivers/uart.c @@ -0,0 +1,10 @@ +#include + +void uart_putc(unsigned int ch) +{ + while(1) { + if (mmio_read32(AUX_MU_LSR_REG) & 0x20) + break; + } + mmio_write32(AUX_MU_IO_REG, ch); +} diff --git a/arm_chainloader/firmware_rendezvous.c b/arm_chainloader/firmware_rendezvous.c new file mode 100755 index 0000000..0b8064a --- /dev/null +++ b/arm_chainloader/firmware_rendezvous.c @@ -0,0 +1,34 @@ +#include +#include +#include + +extern void main(); +extern void uart_putc(int c); + +void _firmware_rendezvous() { + /* Channels to talk to the firmware */ + volatile uint32_t* arm_membase = (volatile uint32_t*)0x0; + volatile uint32_t* comm1 = arm_membase + 8; + volatile uint32_t* comm2 = arm_membase + 9; + volatile uint32_t* comm3 = arm_membase + 10; + volatile uint32_t* comm4 = arm_membase + 11; + + *comm1 = 0xCAFEEEEE; + + /* + * check if we have peripheral access + * if so, we don't need the VPU anymore + */ + if (ARM_ID != ARM_IDVAL) { + *comm1 = 0xDEADCAFE; + return; + } + + *comm4 = VPU_KILL_COMMAND; + + /* stall for a bit to let the VPU commit suicide */ + for (int i = 0; i < 0x10000; i++) + *comm2 = i; + + main(); +} \ No newline at end of file diff --git a/arm_chainloader/linker.lds b/arm_chainloader/linker.lds new file mode 100755 index 0000000..672df5d --- /dev/null +++ b/arm_chainloader/linker.lds @@ -0,0 +1,10 @@ +MEMORY +{ + ram : ORIGIN = 0x0, LENGTH = 0x100000 +} + +SECTIONS +{ + .text : { *(.text*) } > ram + .bss : { *(.bss*) } > ram +} \ No newline at end of file diff --git a/arm_chainloader/main.c b/arm_chainloader/main.c new file mode 100755 index 0000000..c6903e1 --- /dev/null +++ b/arm_chainloader/main.c @@ -0,0 +1,7 @@ +#include +#include +#include + +void main() { + printf("%s: arm_chainloader started on ARM, continuing boot from here ...\n", __FUNCTION__); +} \ No newline at end of file diff --git a/arm_chainloader/start.s b/arm_chainloader/start.s new file mode 100755 index 0000000..3d04b40 --- /dev/null +++ b/arm_chainloader/start.s @@ -0,0 +1,24 @@ +.text +.globl _start +_start: + /* vectors */ + nop + nop + nop + nop + nop + nop + nop + nop + + /* comm chan */ + nop + nop + nop + nop + + mov sp, #0x2000000 + b _firmware_rendezvous + +L_deadloop: + b L_deadloop diff --git a/arm_loader.c b/arm_loader.c new file mode 100755 index 0000000..748a810 --- /dev/null +++ b/arm_loader.c @@ -0,0 +1,276 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +ARM initialization stuff. + +=============================================================================*/ + +#include "lib/common.h" +#include "hardware.h" + + +extern char L_arm_code_start; +extern char L_arm_code_end; + +#define ARM_MEMORY_BASE 0xC0000000 +#define ARM_BKPT_OPCODE 0xE1200070 + +/* XXX: What is this? */ +#define PM_UNK_CFG_CLR 0xFFFCFFFF + +static bool arm_power_wait_bit(uint32_t bit) { + for (int i = 0; i < 20; i++) { + if (PM_PROC & bit) { + return true; + } + udelay(100); + } + return false; +} + +static inline void arm_assert_global_reset() { + printf("%s: RSTN ...\n", __FUNCTION__); + PM_PROC |= PM_PASSWORD | PM_PROC_ARMRSTN_SET; + udelay(300); +} + +static void arm_enable_power() { + uint32_t pmv; + + printf("%s: INIT PM_PROC: 0x%X\n", __FUNCTION__, PM_PROC); + + printf("%s: requesting power up ...\n", __FUNCTION__); + + /* deassert all reset lines */ + pmv = ((PM_PROC & PM_PROC_ARMRSTN_CLR) & PM_UNK_CFG_CLR) | PM_PASSWORD; + + PM_PROC = pmv; + + pmv |= PM_PROC_POWUP_SET; + udelay(10); + PM_PROC = pmv; + + printf("%s: POWUP PM_PROC: 0x%X\n", __FUNCTION__, PM_PROC); + + /* wait for POWOK */ + printf("%s: waiting for power up ...\n", __FUNCTION__); + for (int i = 1; i < 5; i++) { + if (!arm_power_wait_bit(PM_PROC_POWOK_SET)) { + /* only go up to 3 */ + if (i == 4) { + panic("timed out waiting for power up, state of PM_PROC is: 0x%X", PM_PROC); + } + + pmv = (pmv & PM_UNK_CFG_CLR) | (i << PM_PROC_CFG_LSB); + printf("%s: timed out, trying different CFG: 0x%X \n", __FUNCTION__, pmv); + PM_PROC = pmv; + } + } + + pmv |= PM_PROC_ISPOW_SET; + PM_PROC = pmv; + + pmv |= PM_PROC_MEMREP_SET; + PM_PROC = pmv; + + printf("%s: waiting for MRDONE ...\n", __FUNCTION__); + if (!arm_power_wait_bit(PM_PROC_MRDONE_SET)) { + panic("timed out waiting for MRDONE, state of PM_PROC is: 0x%X", PM_PROC); + } + + printf("%s: setting ISFUNC ...\n", __FUNCTION__); + + pmv |= PM_PROC_ISFUNC_SET; + PM_PROC = pmv; + + printf("%s: ARM power domain initialized succesfully, state of PM_PROC is: 0x%X!\n", __FUNCTION__, PM_PROC); +} + +static void arm_bresp_cycle_write(uint32_t bits) { + ARM_CONTROL0 = (ARM_CONTROL0 & ~(ARM_C0_BRESP1|ARM_C0_BRESP2)) | bits; + printf("0x%X,", bits); + udelay(30); +} + +static uint32_t g_BrespTab[] = { + 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x18, 0x0, + 0x10, 0x14, 0x10, 0x1C, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0, + 0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x10, 0x14, 0x18, 0x1C, 0x10, 0x14, 0x10, 0x0, + 0x10, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0, + 0x10, 0x14, 0x18, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x18, 0x0 +}; +static void arm_bresp_cycle() { + /* my little axi - peripherals are magic */ + printf("Cycling AXI bits ...\n\t", __FUNCTION__); + + for (int i = 0; i < sizeof(g_BrespTab)/sizeof(g_BrespTab[0]); i++) { + arm_bresp_cycle_write(g_BrespTab[i]); + + if (i && ((i % 14) == 0)) + printf("\n\t"); + } + + printf("\n"); +} + +void arm_setup_bridge(bool bresp_cycle) { + printf("%s: setting up async bridge ...\n", __FUNCTION__); + + if (bresp_cycle) { + arm_assert_global_reset(); + arm_bresp_cycle(); + arm_assert_global_reset(); + udelay(300); + } + + ARM_CONTROL1 &= ~ARM_C1_REQSTOP; + udelay(300); + + if (!bresp_cycle) + arm_assert_global_reset(); + + printf("%s: bridge init done, PM_PROC is now: 0x%X!\n", __FUNCTION__, PM_PROC); +} + +static void arm_set_clock_source(unsigned int source) { + CM_ARMCTL = CM_PASSWORD | source | CM_ARMCTL_ENAB_SET; +} + +static void arm_enable_clock() { + printf("%s: initializing PLLB ...\n", __FUNCTION__); + + /* oscillator->pllb */ + A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLBEN_SET; + + A2W_PLLB_FRAC = A2W_PASSWORD | 0xeaaa8; + A2W_PLLB_CTRL = A2W_PASSWORD | 48 | 0x1000; + + CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET; + CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET; + + A2W_PLLB_ANA3 = A2W_PASSWORD | 0x100; + A2W_PLLB_ANA2 = A2W_PASSWORD | 0x0; + A2W_PLLB_ANA1 = A2W_PASSWORD | 0x140000; + A2W_PLLB_ANA0 = A2W_PASSWORD | 0x0; + + A2W_PLLB_DIG3 = A2W_PASSWORD | 0x0; + A2W_PLLB_DIG2 = A2W_PASSWORD | 0x400000; + A2W_PLLB_DIG1 = A2W_PASSWORD | 0x3a; + A2W_PLLB_DIG0 = A2W_PASSWORD | 48 | 0xAAA000; + + A2W_PLLB_CTRL = A2W_PASSWORD | 48 | 0x21000; + + A2W_PLLB_DIG3 = A2W_PASSWORD | 0x2; + A2W_PLLB_DIG2 = A2W_PASSWORD | 0x402401; + A2W_PLLB_DIG1 = A2W_PASSWORD | 0x403a; + A2W_PLLB_DIG0 = A2W_PASSWORD | 48 | 0xAAA000; + + A2W_PLLB_ARM = A2W_PASSWORD | 2; + + CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET | CM_PLLB_LOADARM_SET; + CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET; + CM_PLLB = CM_PASSWORD; + + arm_set_clock_source(4); + + printf("KAIP = 0x%X\n", A2W_PLLB_ANA_KAIP); + printf("MULTI = 0x%X\n", A2W_PLLB_ANA_MULTI); + + printf("%s: ARM clock succesfully initialized!\n", __FUNCTION__); +} + +static void arm_load_code() { + uint32_t* mem = (uint32_t*)(ARM_MEMORY_BASE); + + uint8_t* start = &L_arm_code_start; + uint8_t* end = &L_arm_code_end; + uint32_t size = (uint32_t)(end - start); + + bcopy(start, mem, size); + + printf("%s: copied %d bytes to 0x%X!\n", __FUNCTION__, size, ARM_MEMORY_BASE); + + /* verify */ + for (int i = 0; i < size; i++) { + uint8_t* mem8 = (uint8_t*)(mem); + if (start[i] != mem8[i]) + panic("copy failed at 0x%X expected 0x%X, got 0x%X", (uint32_t)&mem8[i], + *((uint32_t*)&mem8[i]), + *((uint32_t*)&start[i])); + } +} + +static void arm_pmap_enter(uint32_t bus_address, uint32_t arm_address) { + volatile uint32_t* tte = &ARM_TRANSLATE; + uint32_t index = arm_address >> 24; + uint32_t pte = bus_address >> 21; + + tte[index] = pte; + + printf("Translation: [0x%X => 0x%X] 0x%X => 0x%X\n", index * 4, bus_address >> 21, bus_address, arm_address); +} + +/* +#define ARM_C0_PRIO_PER 0x00F00000 // per priority mask +#define ARM_C0_PRIO_L2 0x0F000000 +#define ARM_C0_PRIO_UC 0xF0000000 + */ + +void arm_init() { + printf("ARM LOADER: build date %s %s\n", __DATE__, __TIME__); + + printf("%s: starting ARM initialization!\n", __FUNCTION__); + + arm_load_code(); + + printf("%s: original memstart: 0x%X\n", __FUNCTION__, *((volatile uint32_t*)ARM_MEMORY_BASE)); + + for (uint32_t i = 0; i < 6; i++) { + uint32_t offset = i * 0x1000000; + arm_pmap_enter(0xC0000000 + offset, 0x0 + offset); + } + + arm_pmap_enter(VC4_PERIPH_BASE, ARM_PERIPH_BASE); + + /* see if the ARM block is responding */ + printf("%s: ARM ID: 0x%X C0: 0x%X\n", __FUNCTION__, ARM_ID, ARM_CONTROL0); + + /* + * enable peripheral access, map arm secure bits to axi secure bits 1:1 and + * set the mem size for who knows what reason. + */ + ARM_CONTROL0 |= 0x000 | ARM_C0_APROTSYST | ARM_C0_SIZ1G | ARM_C0_FULLPERI; + + printf("%s: using C0: 0x%X\n", __FUNCTION__, ARM_CONTROL0); + + arm_enable_clock(); + arm_enable_power(); + /* start io bridge */ + arm_setup_bridge(true); + printf("%s: polling ARM state ...\n", __FUNCTION__); + + volatile uint32_t* arm_membase = (volatile uint32_t*)ARM_MEMORY_BASE; + + /* skip vectors and get to comm chan */ + arm_membase += 8; + + for (;;/*int i = 0; i < 10; i++*/) { + if (arm_membase[3] == VPU_KILL_COMMAND) { + panic("ARM requested VPU halt, gooodbye VPU ..."); + } + printf("0x%X 0x%X 0x%X 0x%X\n", arm_membase[0], arm_membase[1], arm_membase[2], arm_membase[3]); + udelay(5000); + } +} \ No newline at end of file diff --git a/bcm2708_chip/README.txt b/bcm2708_chip/README.txt new file mode 100755 index 0000000..50d048b --- /dev/null +++ b/bcm2708_chip/README.txt @@ -0,0 +1,29 @@ +This dir contains all the register map files for the design +The bulk of it is created with the create_regs script (run create_regs) which +parses the *_regs files in the hdl dirs and creates the individual files + +The top level file is chip/hdl/bcm2708_regs.tcl which defines the contents +and off sets of the chip level memory map. + +Create regs then searches the dir tree for each object mentioned in bcm2708_regs.tcl +and locates its "object_regs.tcl" file + +It then generates all the .h .inc ... files. + +These are then all lumped together in a register_map.h register_map.inc etc file + + + +The general procedure to modify this is + + + +check out all of chip/verification/code/vcinclude +run create_regs in this dir +revert all unchanged files in vcinclude +check the modified ones and checkl them in if they are ok. + + +Note: +If create regs cant find a _regs.tcl file it will crash +If it finds two files with the same name it will crash diff --git a/bcm2708_chip/apb_arbiter_control.h b/bcm2708_chip/apb_arbiter_control.h new file mode 100755 index 0000000..a0f04fa --- /dev/null +++ b/bcm2708_chip/apb_arbiter_control.h @@ -0,0 +1,7 @@ +// This file was generated by the create_regs script +#define ACR_BASE 0x7e80a000 +#define ACR_APB_ID 0x61726272 +#define ACR_control HW_REGISTER_RW( 0x7e80a000 ) + #define ACR_control_MASK 0x0000ffff + #define ACR_control_WIDTH 16 + #define ACR_control_RESET 0000000000 diff --git a/bcm2708_chip/apb_async_bridge_ctrl.h b/bcm2708_chip/apb_async_bridge_ctrl.h new file mode 100755 index 0000000..339f473 --- /dev/null +++ b/bcm2708_chip/apb_async_bridge_ctrl.h @@ -0,0 +1,245 @@ +// This file was generated by the create_regs script +#define ASB_BASE 0x7e00a000 +#define ASB_APB_ID 0x62726467 +#define ASB_AXI_BRDG_VERSION HW_REGISTER_RW( 0x7e00a000 ) + #define ASB_AXI_BRDG_VERSION_MASK 0x000000ff + #define ASB_AXI_BRDG_VERSION_WIDTH 8 + #define ASB_AXI_BRDG_VERSION_RESET 0000000000 +#define ASB_CPR_CTRL HW_REGISTER_RW( 0x7e00a004 ) + #define ASB_CPR_CTRL_MASK 0x00ffffff + #define ASB_CPR_CTRL_WIDTH 24 + #define ASB_CPR_CTRL_RESET 0x00000007 + #define ASB_CPR_CTRL_CLR_REQ_BITS 0:0 + #define ASB_CPR_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_CPR_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_CPR_CTRL_CLR_REQ_MSB 0 + #define ASB_CPR_CTRL_CLR_REQ_LSB 0 + #define ASB_CPR_CTRL_CLR_ACK_BITS 1:1 + #define ASB_CPR_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_CPR_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_CPR_CTRL_CLR_ACK_MSB 1 + #define ASB_CPR_CTRL_CLR_ACK_LSB 1 + #define ASB_CPR_CTRL_EMPTY_BITS 2:2 + #define ASB_CPR_CTRL_EMPTY_SET 0x00000004 + #define ASB_CPR_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_CPR_CTRL_EMPTY_MSB 2 + #define ASB_CPR_CTRL_EMPTY_LSB 2 + #define ASB_CPR_CTRL_FULL_BITS 3:3 + #define ASB_CPR_CTRL_FULL_SET 0x00000008 + #define ASB_CPR_CTRL_FULL_CLR 0xfffffff7 + #define ASB_CPR_CTRL_FULL_MSB 3 + #define ASB_CPR_CTRL_FULL_LSB 3 + #define ASB_CPR_CTRL_RCOUNT_BITS 13:4 + #define ASB_CPR_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_CPR_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_CPR_CTRL_RCOUNT_MSB 13 + #define ASB_CPR_CTRL_RCOUNT_LSB 4 + #define ASB_CPR_CTRL_WCOUNT_BITS 23:14 + #define ASB_CPR_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_CPR_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_CPR_CTRL_WCOUNT_MSB 23 + #define ASB_CPR_CTRL_WCOUNT_LSB 14 +#define ASB_V3D_S_CTRL HW_REGISTER_RW( 0x7e00a008 ) + #define ASB_V3D_S_CTRL_MASK 0x00ffffff + #define ASB_V3D_S_CTRL_WIDTH 24 + #define ASB_V3D_S_CTRL_RESET 0x00000007 + #define ASB_V3D_S_CTRL_CLR_REQ_BITS 0:0 + #define ASB_V3D_S_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_V3D_S_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_V3D_S_CTRL_CLR_REQ_MSB 0 + #define ASB_V3D_S_CTRL_CLR_REQ_LSB 0 + #define ASB_V3D_S_CTRL_CLR_ACK_BITS 1:1 + #define ASB_V3D_S_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_V3D_S_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_V3D_S_CTRL_CLR_ACK_MSB 1 + #define ASB_V3D_S_CTRL_CLR_ACK_LSB 1 + #define ASB_V3D_S_CTRL_EMPTY_BITS 2:2 + #define ASB_V3D_S_CTRL_EMPTY_SET 0x00000004 + #define ASB_V3D_S_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_V3D_S_CTRL_EMPTY_MSB 2 + #define ASB_V3D_S_CTRL_EMPTY_LSB 2 + #define ASB_V3D_S_CTRL_FULL_BITS 3:3 + #define ASB_V3D_S_CTRL_FULL_SET 0x00000008 + #define ASB_V3D_S_CTRL_FULL_CLR 0xfffffff7 + #define ASB_V3D_S_CTRL_FULL_MSB 3 + #define ASB_V3D_S_CTRL_FULL_LSB 3 + #define ASB_V3D_S_CTRL_RCOUNT_BITS 13:4 + #define ASB_V3D_S_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_V3D_S_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_V3D_S_CTRL_RCOUNT_MSB 13 + #define ASB_V3D_S_CTRL_RCOUNT_LSB 4 + #define ASB_V3D_S_CTRL_WCOUNT_BITS 23:14 + #define ASB_V3D_S_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_V3D_S_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_V3D_S_CTRL_WCOUNT_MSB 23 + #define ASB_V3D_S_CTRL_WCOUNT_LSB 14 +#define ASB_V3D_M_CTRL HW_REGISTER_RW( 0x7e00a00c ) + #define ASB_V3D_M_CTRL_MASK 0x00ffffff + #define ASB_V3D_M_CTRL_WIDTH 24 + #define ASB_V3D_M_CTRL_RESET 0x00000007 + #define ASB_V3D_M_CTRL_CLR_REQ_BITS 0:0 + #define ASB_V3D_M_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_V3D_M_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_V3D_M_CTRL_CLR_REQ_MSB 0 + #define ASB_V3D_M_CTRL_CLR_REQ_LSB 0 + #define ASB_V3D_M_CTRL_CLR_ACK_BITS 1:1 + #define ASB_V3D_M_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_V3D_M_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_V3D_M_CTRL_CLR_ACK_MSB 1 + #define ASB_V3D_M_CTRL_CLR_ACK_LSB 1 + #define ASB_V3D_M_CTRL_EMPTY_BITS 2:2 + #define ASB_V3D_M_CTRL_EMPTY_SET 0x00000004 + #define ASB_V3D_M_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_V3D_M_CTRL_EMPTY_MSB 2 + #define ASB_V3D_M_CTRL_EMPTY_LSB 2 + #define ASB_V3D_M_CTRL_FULL_BITS 3:3 + #define ASB_V3D_M_CTRL_FULL_SET 0x00000008 + #define ASB_V3D_M_CTRL_FULL_CLR 0xfffffff7 + #define ASB_V3D_M_CTRL_FULL_MSB 3 + #define ASB_V3D_M_CTRL_FULL_LSB 3 + #define ASB_V3D_M_CTRL_RCOUNT_BITS 13:4 + #define ASB_V3D_M_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_V3D_M_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_V3D_M_CTRL_RCOUNT_MSB 13 + #define ASB_V3D_M_CTRL_RCOUNT_LSB 4 + #define ASB_V3D_M_CTRL_WCOUNT_BITS 23:14 + #define ASB_V3D_M_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_V3D_M_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_V3D_M_CTRL_WCOUNT_MSB 23 + #define ASB_V3D_M_CTRL_WCOUNT_LSB 14 +#define ASB_ISP_S_CTRL HW_REGISTER_RW( 0x7e00a010 ) + #define ASB_ISP_S_CTRL_MASK 0x00ffffff + #define ASB_ISP_S_CTRL_WIDTH 24 + #define ASB_ISP_S_CTRL_RESET 0x00000007 + #define ASB_ISP_S_CTRL_CLR_REQ_BITS 0:0 + #define ASB_ISP_S_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_ISP_S_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_ISP_S_CTRL_CLR_REQ_MSB 0 + #define ASB_ISP_S_CTRL_CLR_REQ_LSB 0 + #define ASB_ISP_S_CTRL_CLR_ACK_BITS 1:1 + #define ASB_ISP_S_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_ISP_S_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_ISP_S_CTRL_CLR_ACK_MSB 1 + #define ASB_ISP_S_CTRL_CLR_ACK_LSB 1 + #define ASB_ISP_S_CTRL_EMPTY_BITS 2:2 + #define ASB_ISP_S_CTRL_EMPTY_SET 0x00000004 + #define ASB_ISP_S_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_ISP_S_CTRL_EMPTY_MSB 2 + #define ASB_ISP_S_CTRL_EMPTY_LSB 2 + #define ASB_ISP_S_CTRL_FULL_BITS 3:3 + #define ASB_ISP_S_CTRL_FULL_SET 0x00000008 + #define ASB_ISP_S_CTRL_FULL_CLR 0xfffffff7 + #define ASB_ISP_S_CTRL_FULL_MSB 3 + #define ASB_ISP_S_CTRL_FULL_LSB 3 + #define ASB_ISP_S_CTRL_RCOUNT_BITS 13:4 + #define ASB_ISP_S_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_ISP_S_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_ISP_S_CTRL_RCOUNT_MSB 13 + #define ASB_ISP_S_CTRL_RCOUNT_LSB 4 + #define ASB_ISP_S_CTRL_WCOUNT_BITS 23:14 + #define ASB_ISP_S_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_ISP_S_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_ISP_S_CTRL_WCOUNT_MSB 23 + #define ASB_ISP_S_CTRL_WCOUNT_LSB 14 +#define ASB_ISP_M_CTRL HW_REGISTER_RW( 0x7e00a014 ) + #define ASB_ISP_M_CTRL_MASK 0x00ffffff + #define ASB_ISP_M_CTRL_WIDTH 24 + #define ASB_ISP_M_CTRL_RESET 0x00000007 + #define ASB_ISP_M_CTRL_CLR_REQ_BITS 0:0 + #define ASB_ISP_M_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_ISP_M_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_ISP_M_CTRL_CLR_REQ_MSB 0 + #define ASB_ISP_M_CTRL_CLR_REQ_LSB 0 + #define ASB_ISP_M_CTRL_CLR_ACK_BITS 1:1 + #define ASB_ISP_M_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_ISP_M_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_ISP_M_CTRL_CLR_ACK_MSB 1 + #define ASB_ISP_M_CTRL_CLR_ACK_LSB 1 + #define ASB_ISP_M_CTRL_EMPTY_BITS 2:2 + #define ASB_ISP_M_CTRL_EMPTY_SET 0x00000004 + #define ASB_ISP_M_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_ISP_M_CTRL_EMPTY_MSB 2 + #define ASB_ISP_M_CTRL_EMPTY_LSB 2 + #define ASB_ISP_M_CTRL_FULL_BITS 3:3 + #define ASB_ISP_M_CTRL_FULL_SET 0x00000008 + #define ASB_ISP_M_CTRL_FULL_CLR 0xfffffff7 + #define ASB_ISP_M_CTRL_FULL_MSB 3 + #define ASB_ISP_M_CTRL_FULL_LSB 3 + #define ASB_ISP_M_CTRL_RCOUNT_BITS 13:4 + #define ASB_ISP_M_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_ISP_M_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_ISP_M_CTRL_RCOUNT_MSB 13 + #define ASB_ISP_M_CTRL_RCOUNT_LSB 4 + #define ASB_ISP_M_CTRL_WCOUNT_BITS 23:14 + #define ASB_ISP_M_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_ISP_M_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_ISP_M_CTRL_WCOUNT_MSB 23 + #define ASB_ISP_M_CTRL_WCOUNT_LSB 14 +#define ASB_H264_S_CTRL HW_REGISTER_RW( 0x7e00a018 ) + #define ASB_H264_S_CTRL_MASK 0x00ffffff + #define ASB_H264_S_CTRL_WIDTH 24 + #define ASB_H264_S_CTRL_RESET 0x00000007 + #define ASB_H264_S_CTRL_CLR_REQ_BITS 0:0 + #define ASB_H264_S_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_H264_S_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_H264_S_CTRL_CLR_REQ_MSB 0 + #define ASB_H264_S_CTRL_CLR_REQ_LSB 0 + #define ASB_H264_S_CTRL_CLR_ACK_BITS 1:1 + #define ASB_H264_S_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_H264_S_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_H264_S_CTRL_CLR_ACK_MSB 1 + #define ASB_H264_S_CTRL_CLR_ACK_LSB 1 + #define ASB_H264_S_CTRL_EMPTY_BITS 2:2 + #define ASB_H264_S_CTRL_EMPTY_SET 0x00000004 + #define ASB_H264_S_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_H264_S_CTRL_EMPTY_MSB 2 + #define ASB_H264_S_CTRL_EMPTY_LSB 2 + #define ASB_H264_S_CTRL_FULL_BITS 3:3 + #define ASB_H264_S_CTRL_FULL_SET 0x00000008 + #define ASB_H264_S_CTRL_FULL_CLR 0xfffffff7 + #define ASB_H264_S_CTRL_FULL_MSB 3 + #define ASB_H264_S_CTRL_FULL_LSB 3 + #define ASB_H264_S_CTRL_RCOUNT_BITS 13:4 + #define ASB_H264_S_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_H264_S_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_H264_S_CTRL_RCOUNT_MSB 13 + #define ASB_H264_S_CTRL_RCOUNT_LSB 4 + #define ASB_H264_S_CTRL_WCOUNT_BITS 23:14 + #define ASB_H264_S_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_H264_S_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_H264_S_CTRL_WCOUNT_MSB 23 + #define ASB_H264_S_CTRL_WCOUNT_LSB 14 +#define ASB_H264_M_CTRL HW_REGISTER_RW( 0x7e00a01c ) + #define ASB_H264_M_CTRL_MASK 0x00ffffff + #define ASB_H264_M_CTRL_WIDTH 24 + #define ASB_H264_M_CTRL_RESET 0x00000007 + #define ASB_H264_M_CTRL_CLR_REQ_BITS 0:0 + #define ASB_H264_M_CTRL_CLR_REQ_SET 0x00000001 + #define ASB_H264_M_CTRL_CLR_REQ_CLR 0xfffffffe + #define ASB_H264_M_CTRL_CLR_REQ_MSB 0 + #define ASB_H264_M_CTRL_CLR_REQ_LSB 0 + #define ASB_H264_M_CTRL_CLR_ACK_BITS 1:1 + #define ASB_H264_M_CTRL_CLR_ACK_SET 0x00000002 + #define ASB_H264_M_CTRL_CLR_ACK_CLR 0xfffffffd + #define ASB_H264_M_CTRL_CLR_ACK_MSB 1 + #define ASB_H264_M_CTRL_CLR_ACK_LSB 1 + #define ASB_H264_M_CTRL_EMPTY_BITS 2:2 + #define ASB_H264_M_CTRL_EMPTY_SET 0x00000004 + #define ASB_H264_M_CTRL_EMPTY_CLR 0xfffffffb + #define ASB_H264_M_CTRL_EMPTY_MSB 2 + #define ASB_H264_M_CTRL_EMPTY_LSB 2 + #define ASB_H264_M_CTRL_FULL_BITS 3:3 + #define ASB_H264_M_CTRL_FULL_SET 0x00000008 + #define ASB_H264_M_CTRL_FULL_CLR 0xfffffff7 + #define ASB_H264_M_CTRL_FULL_MSB 3 + #define ASB_H264_M_CTRL_FULL_LSB 3 + #define ASB_H264_M_CTRL_RCOUNT_BITS 13:4 + #define ASB_H264_M_CTRL_RCOUNT_SET 0x00003ff0 + #define ASB_H264_M_CTRL_RCOUNT_CLR 0xffffc00f + #define ASB_H264_M_CTRL_RCOUNT_MSB 13 + #define ASB_H264_M_CTRL_RCOUNT_LSB 4 + #define ASB_H264_M_CTRL_WCOUNT_BITS 23:14 + #define ASB_H264_M_CTRL_WCOUNT_SET 0x00ffc000 + #define ASB_H264_M_CTRL_WCOUNT_CLR 0xff003fff + #define ASB_H264_M_CTRL_WCOUNT_MSB 23 + #define ASB_H264_M_CTRL_WCOUNT_LSB 14 diff --git a/bcm2708_chip/arm_control.h b/bcm2708_chip/arm_control.h new file mode 100755 index 0000000..8d249dc --- /dev/null +++ b/bcm2708_chip/arm_control.h @@ -0,0 +1,404 @@ +// +// Definitions and addresses forthe ARM CONTROL logic +// This file is manually generated. +// +// + +#define ARM_BASE 0x7E00B000 + +// Basic configuration +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) +#define ARM_C0_SIZ128M 0x00000000 +#define ARM_C0_SIZ256M 0x00000001 +#define ARM_C0_SIZ512M 0x00000002 +#define ARM_C0_SIZ1G 0x00000003 +#define ARM_C0_BRESP0 0x00000000 +#define ARM_C0_BRESP1 0x00000004 +#define ARM_C0_BRESP2 0x00000008 +#define ARM_C0_BOOTHI 0x00000010 +#define ARM_C0_UNUSED05 0x00000020 // free +#define ARM_C0_FULLPERI 0x00000040 +#define ARM_C0_UNUSED78 0x00000180 // free +#define ARM_C0_JTAGMASK 0x00000E00 +#define ARM_C0_JTAGOFF 0x00000000 +#define ARM_C0_JTAGBASH 0x00000800 // Debug on GPIO off +#define ARM_C0_JTAGGPIO 0x00000C00 // Debug on GPIO on +#define ARM_C0_APROTMSK 0x0000F000 +#define ARM_C0_DBG0SYNC 0x00010000 // VPU0 halt sync +#define ARM_C0_DBG1SYNC 0x00020000 // VPU1 halt sync +#define ARM_C0_SWDBGREQ 0x00040000 // HW debug request +#define ARM_C0_PASSHALT 0x00080000 // ARM halt passed to debugger +#define ARM_C0_PRIO_PER 0x00F00000 // per priority mask +#define ARM_C0_PRIO_L2 0x0F000000 +#define ARM_C0_PRIO_UC 0xF0000000 + +#define ARM_C0_APROTPASS 0x0000A000 // Translate 1:1 +#define ARM_C0_APROTUSER 0x00000000 // Only user mode +#define ARM_C0_APROTSYST 0x0000F000 // Only system mode + + +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) +#define ARM_C1_TIMER 0x00000001 // re-route timer IRQ to VC +#define ARM_C1_MAIL 0x00000002 // re-route Mail IRQ to VC +#define ARM_C1_BELL0 0x00000004 // re-route Doorbell 0 to VC +#define ARM_C1_BELL1 0x00000008 // re-route Doorbell 1 to VC +#define ARM_C1_PERSON 0x00000100 // peripherals on +#define ARM_C1_REQSTOP 0x00000200 // ASYNC bridge request stop + +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) +#define ARM_S_ACKSTOP 0x80000000 // Bridge stopped +#define ARM_S_READPEND 0x000003FF // pending reads counter +#define ARM_S_WRITPEND 0x000FFC00 // pending writes counter + +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) +#define ARM_EH_PERIBURST 0x00000001 // Burst write seen on peri bus +#define ARM_EH_ILLADDRS1 0x00000002 // Address bits 25-27 error +#define ARM_EH_ILLADDRS2 0x00000004 // Address bits 31-28 error +#define ARM_EH_VPU0HALT 0x00000008 // VPU0 halted & in debug mode +#define ARM_EH_VPU1HALT 0x00000010 // VPU1 halted & in debug mode +#define ARM_EH_ARMHALT 0x00000020 // ARM in halted debug mode + +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) +#define ARM_IDVAL 0x364D5241 + +// Translation memory +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) +// 32 locations: 0x100.. 0x17F +// 32 spare means we CAN go to 64 pages.... + + +// Interrupts +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) // Top IRQ bits +#define ARM_I0_TIMER 0x00000001 // timer IRQ +#define ARM_I0_MAIL 0x00000002 // Mail IRQ +#define ARM_I0_BELL0 0x00000004 // Doorbell 0 +#define ARM_I0_BELL1 0x00000008 // Doorbell 1 +#define ARM_I0_BANK1 0x00000100 // Bank1 IRQ +#define ARM_I0_BANK2 0x00000200 // Bank2 IRQ + +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) // All bank1 IRQ bits +// todo: all I1_interrupt sources +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) // All bank2 IRQ bits +// todo: all I2_interrupt sources + +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) // FIQ control +#define ARM_IF_INDEX 0x0000007F // FIQ select +#define ARM_IF_ENABLE 0x00000080 // FIQ enable +#define ARM_IF_VCMASK 0x0000003F // FIQ = (index from VC source) +#define ARM_IF_TIMER 0x00000040 // FIQ = ARM timer +#define ARM_IF_MAIL 0x00000041 // FIQ = ARM Mail +#define ARM_IF_BELL0 0x00000042 // FIQ = ARM Doorbell 0 +#define ARM_IF_BELL1 0x00000043 // FIQ = ARM Doorbell 1 +#define ARM_IF_VP0HALT 0x00000044 // FIQ = VPU0 Halt seen +#define ARM_IF_VP1HALT 0x00000045 // FIQ = VPU1 Halt seen +#define ARM_IF_ILLEGAL 0x00000046 // FIQ = Illegal access seen + +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) // Bank1 enable bits +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) // Bank2 enable bits +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) // ARM irqs enable bits +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) // Bank1 disable bits +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) // Bank2 disable bits +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) // ARM irqs disable bits +#define ARM_IE_TIMER 0x00000001 // Timer IRQ +#define ARM_IE_MAIL 0x00000002 // Mail IRQ +#define ARM_IE_BELL0 0x00000004 // Doorbell 0 +#define ARM_IE_BELL1 0x00000008 // Doorbell 1 +#define ARM_IE_VP0HALT 0x00000010 // VPU0 Halt +#define ARM_IE_VP1HALT 0x00000020 // VPU1 Halt +#define ARM_IE_ILLEGAL 0x00000040 // Illegal access seen + +// Timer +// For reg. fields see sp804 spec. +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) + +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) +#define TIMER_CTRL_DBGHALT (1 << 8) +#define TIMER_CTRL_ENAFREE (1 << 9) +#define TIMER_CTRL_FREEDIV_SHIFT 16) +#define TIMER_CTRL_FREEDIV_MASK 0xff + +// +// Semaphores, Doorbells, Mailboxes +#define ARM_SBM_OWN0 (ARM_BASE+0x800) +#define ARM_SBM_OWN1 (ARM_BASE+0x900) +#define ARM_SBM_OWN2 (ARM_BASE+0xA00) +#define ARM_SBM_OWN3 (ARM_BASE+0xB00) + +// +// MAILBOXES +// Register flags are common across all +// owner registers. See end of this section +//========================================= +// Semaphores, Doorbells, Mailboxes Owner 0 +//========================================= +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) +// MAILBOX 0 access in Owner 0 area +// Some addresses should ONLY be used by owner 0 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) // .. 0x8C (4 locations) +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) // .. 0x8C (4 locations) Normal read +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) // none-pop read +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) // Sender read (only LS 2 bits) +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) // Status read +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) // Config read/write +// MAILBOX 1 access in Owner 0 area +// Owner 0 should only WRITE to this mailbox +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) // .. 0xAC (4 locations) +//#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) // DO NOT USE THIS !!!!! +//#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) // DO NOT USE THIS !!!!! +//#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) // DO NOT USE THIS !!!!! +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) // Status read +//#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) // DO NOT USE THIS !!!!! +// General SEM, BELL, MAIL config/status +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) // semaphore clear/debug register +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) // Doorbells clear/debug register +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) // ALL interrupts +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) // IRQS pending for owner 0 + +// Semaphores, Doorbells, Mailboxes Owner 1 +//========================================= +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) +// MAILBOX 0 access in Owner 0 area +// Owner 1 should only WRITE to this mailbox +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) // .. 0x8C (4 locations) +//#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) // DO NOT USE THIS !!!!! +//#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) // DO NOT USE THIS !!!!! +//#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) // DO NOT USE THIS !!!!! +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) // Status read +//#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) // DO NOT USE THIS !!!!! +// MAILBOX 1 access in Owner 0 area +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) // .. 0xAC (4 locations) +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) // .. 0xAC (4 locations) Normal read +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) // none-pop read +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) // Sender read (only LS 2 bits) +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) // Status read +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) +// General SEM, BELL, MAIL config/status +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) // semaphore clear/debug register +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) // Doorbells clear/debug register +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) // IRQS pending for owner 1 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) // ALL interrupts + +// Semaphores, Doorbells, Mailboxes Owner 2 +//========================================= +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) +// MAILBOX 0 access in Owner 2 area +// Owner 2 should only WRITE to this mailbox +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) // .. 0x8C (4 locations) +//#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) // DO NOT USE THIS !!!!! +//#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) // DO NOT USE THIS !!!!! +//#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) // DO NOT USE THIS !!!!! +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) // Status read +//#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) // DO NOT USE THIS !!!!! +// MAILBOX 1 access in Owner 2 area +// Owner 2 should only WRITE to this mailbox +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) // .. 0xAC (4 locations) +//#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) // DO NOT USE THIS !!!!! +//#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) // DO NOT USE THIS !!!!! +//#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) // DO NOT USE THIS !!!!! +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) // Status read +//#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) // DO NOT USE THIS !!!!! +// General SEM, BELL, MAIL config/status +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) // semaphore clear/debug register +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) // Doorbells clear/debug register +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) // IRQS pending for owner 2 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) // ALL interrupts + +// Semaphores, Doorbells, Mailboxes Owner 3 +//========================================= +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) +// MAILBOX 0 access in Owner 3 area +// Owner 3 should only WRITE to this mailbox +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) // .. 0x8C (4 locations) +//#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) // DO NOT USE THIS !!!!! +//#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) // DO NOT USE THIS !!!!! +//#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) // DO NOT USE THIS !!!!! +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) // Status read +//#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) // DO NOT USE THIS !!!!! +// MAILBOX 1 access in Owner 3 area +// Owner 3 should only WRITE to this mailbox +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) // .. 0xAC (4 locations) +//#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) // DO NOT USE THIS !!!!! +//#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) // DO NOT USE THIS !!!!! +//#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) // DO NOT USE THIS !!!!! +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) // Status read +//#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) // DO NOT USE THIS !!!!! +// General SEM, BELL, MAIL config/status +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) // semaphore clear/debug register +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) // Doorbells clear/debug register +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) // IRQS pending for owner 3 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) // ALL interrupts + + + +/////////////////////////////////////////// +// MAILBOX FLAGS. VALID FOR ALL OWNERS // +/////////////////////////////////////////// + +// MAILBOX status register (...0x98) +#define ARM_MS_FULL 0x80000000 +#define ARM_MS_EMPTY 0x40000000 +#define ARM_MS_LEVEL 0x400000FF // Max. value depdnds on mailbox depth parameter + +// MAILBOX config/status register (...0x9C) +// ANY write to this register clears the error bits! +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 // mailbox irq enable: has data +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 // mailbox irq enable: has space +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 // mailbox irq enable: Opp. is empty +#define ARM_MC_MAIL_CLEAR 0x00000008 // mailbox clear write 1, then 0 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 // mailbox irq pending: has space +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 // mailbox irq pending: Opp. is empty +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 // mailbox irq pending +// Bit 7 is unused +#define ARM_MC_ERRNOOWN 0x00000100 // error : none owner read from mailbox +#define ARM_MC_ERROVERFLW 0x00000200 // error : write to fill mailbox +#define ARM_MC_ERRUNDRFLW 0x00000400 // error : read from empty mailbox + +// Semaphore clear/debug register (...0xE0) +#define ARM_SD_OWN0 0x00000003 // Owner of sem 0 +#define ARM_SD_OWN1 0x0000000C // Owner of sem 1 +#define ARM_SD_OWN2 0x00000030 // Owner of sem 2 +#define ARM_SD_OWN3 0x000000C0 // Owner of sem 3 +#define ARM_SD_OWN4 0x00000300 // Owner of sem 4 +#define ARM_SD_OWN5 0x00000C00 // Owner of sem 5 +#define ARM_SD_OWN6 0x00003000 // Owner of sem 6 +#define ARM_SD_OWN7 0x0000C000 // Owner of sem 7 +#define ARM_SD_SEM0 0x00010000 // Status of sem 0 +#define ARM_SD_SEM1 0x00020000 // Status of sem 1 +#define ARM_SD_SEM2 0x00040000 // Status of sem 2 +#define ARM_SD_SEM3 0x00080000 // Status of sem 3 +#define ARM_SD_SEM4 0x00100000 // Status of sem 4 +#define ARM_SD_SEM5 0x00200000 // Status of sem 5 +#define ARM_SD_SEM6 0x00400000 // Status of sem 6 +#define ARM_SD_SEM7 0x00800000 // Status of sem 7 + +// Doorbell status registers (...0x40-4C) +#define ARM_DS_ACTIVE 0x00000004 // Doorbell rung since last read? +#define ARM_DS_OWNER 0x00000003 // Owner + +// Doorbells clear/debug register (...0xE4) +#define ARM_BD_OWN0 0x00000003 // Owner of doorbell 0 +#define ARM_BD_OWN1 0x0000000C // Owner of doorbell 1 +#define ARM_BD_OWN2 0x00000030 // Owner of doorbell 2 +#define ARM_BD_OWN3 0x000000C0 // Owner of doorbell 3 +#define ARM_BD_BELL0 0x00000100 // Status of doorbell 0 +#define ARM_BD_BELL1 0x00000200 // Status of doorbell 1 +#define ARM_BD_BELL2 0x00000400 // Status of doorbell 2 +#define ARM_BD_BELL3 0x00000800 // Status of doorbell 3 + +// MY IRQS register (...0xF8) +#define ARM_MYIRQ_BELL 0x00000001 // This owner has a doorbell IRQ +#define ARM_MYIRQ_MAIL 0x00000002 // This owner has a mailbox IRQ + +// ALL IRQS register (...0xF8) +#define ARM_AIS_BELL0 0x00000001 // Doorbell 0 IRQ pending +#define ARM_AIS_BELL1 0x00000002 // Doorbell 1 IRQ pending +#define ARM_AIS_BELL2 0x00000004 // Doorbell 2 IRQ pending +#define ARM_AIS_BELL3 0x00000008 // Doorbell 3 IRQ pending +#define ARM_AIS0_HAVEDATA 0x00000010 // MAIL 0 has data IRQ pending +#define ARM_AIS0_HAVESPAC 0x00000020 // MAIL 0 has space IRQ pending +#define ARM_AIS0_OPPEMPTY 0x00000040 // MAIL 0 opposite is empty IRQ +#define ARM_AIS1_HAVEDATA 0x00000080 // MAIL 1 has data IRQ pending +#define ARM_AIS1_HAVESPAC 0x00000100 // MAIL 1 has space IRQ pending +#define ARM_AIS1_OPPEMPTY 0x00000200 // MAIL 1 opposite is empty IRQ +// Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM +// Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC +// +// ARM JTAG BASH +// +#define AJB_BASE 0x7e2000c0 + +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) +#define AJB_BITS0 0x000000 +#define AJB_BITS4 0x000004 +#define AJB_BITS8 0x000008 +#define AJB_BITS12 0x00000C +#define AJB_BITS16 0x000010 +#define AJB_BITS20 0x000014 +#define AJB_BITS24 0x000018 +#define AJB_BITS28 0x00001C +#define AJB_BITS32 0x000020 +#define AJB_BITS34 0x000022 +#define AJB_OUT_MS 0x000040 +#define AJB_OUT_LS 0x000000 +#define AJB_INV_CLK 0x000080 +#define AJB_D0_RISE 0x000100 +#define AJB_D0_FALL 0x000000 +#define AJB_D1_RISE 0x000200 +#define AJB_D1_FALL 0x000000 +#define AJB_IN_RISE 0x000400 +#define AJB_IN_FALL 0x000000 +#define AJB_ENABLE 0x000800 +#define AJB_HOLD0 0x000000 +#define AJB_HOLD1 0x001000 +#define AJB_HOLD2 0x002000 +#define AJB_HOLD3 0x003000 +#define AJB_RESETN 0x004000 +#define AJB_CLKSHFT 16 +#define AJB_BUSY 0x80000000 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) diff --git a/bcm2708_chip/aux_io.h b/bcm2708_chip/aux_io.h new file mode 100755 index 0000000..ff4fe9a --- /dev/null +++ b/bcm2708_chip/aux_io.h @@ -0,0 +1,170 @@ +// +// Auxiliary I/O header file +// + +#define AUX_IO_BASE 0x7E215000 +#define AUX_IRQ (AUX_IO_BASE+0x000) +#define AUX_ENABLES (AUX_IO_BASE+0x004) +#define AUX_ENABLE_MINIUART 0x01 +#define AUX_ENABLE_SPI0 0x02 +#define AUX_ENABLE_SPI1 0x04 + + +// +// Micro UART +// +// Baud rate = sysclk/(8*(BAUD_REG+1)) + +#define AUX_MU_IO_REG (AUX_IO_BASE+0x040) // Write=TX read=RX +#define AUX_MU_BDLS_REG (AUX_IO_BASE+0x040) // Baudrate LS +#define AUX_MU_BDMS_REG (AUX_IO_BASE+0x044) // Baudrate MS. + +#define AUX_MU_IER_REG (AUX_IO_BASE+0x044) // IRQ enbl. reg. +#define AUX_MU_IER_RXIRQEN 0x01 // +#define AUX_MU_IER_TXIRQEN 0x02 // +// Line interrupts are not supported + +#define AUX_MU_IIR_REG (AUX_IO_BASE+0x048) // IRQ status reg +#define AUX_MU_IIR_NOIRQS 0x01 // No irq pending +#define AUX_MU_IIR_IRQ 0x06 // 10 = rec irq, 01 = tx irq +// Timeout is not supported + +#define AUX_MU_FCR_REG (AUX_IO_BASE+0x048) // FIFO control reg +#define AUX_MU_FCR_RXCLR 0x02 // Flush receive FF +#define AUX_MU_FCR_TXCLR 0x04 // Flush transmit fifo + + +#define AUX_MU_LCR_REG (AUX_IO_BASE+0x04C) // Line control reg. +#define AUX_MU_LCR_7BITS 0x02 // 7 bits mode +#define AUX_MU_LCR_8BITS 0x03 // 8 bits mode +#define AUX_MU_LCR_BREAK 0x40 // send break +#define AUX_MU_LCR_DLAB 0x80 // DLAB access +// 5 & 6 bits are not supported +// 2 stop bits are not supported +// Parity bits are not supported + +#define AUX_MU_MCR_REG (AUX_IO_BASE+0x050) // Modem control reg. +#define AUX_MU_MCR_RTS 0x02 // Set RTS high +// DTR is not supported +// Out1/2 are not supported +// Loopback is not supported + +#define AUX_MU_LSR_REG (AUX_IO_BASE+0x054) // Line status reg. +#define AUX_MU_LSR_DR 0x01 // Receive Data ready +#define AUX_MU_LSR_OE 0x02 // Receiver overrun error +#define AUX_MU_LSR_THRE 0x20 // Transmitter holding register +#define AUX_MU_LSR_TEMT 0x40 // Transmitter empty +// Parity bits (and thus errors) are not supported +// Framing errors are not detected +// Break detect is not (yet) supported + +#define AUX_MU_MSR_REG (AUX_IO_BASE+0x058) // Modem status reg. +#define AUX_MU_MSR_CTS 0x10 +// Delta CTS not supported +// DCE,DCD not supportred + +#define AUX_MU_SCRATCH (AUX_IO_BASE+0x05C) // Scratch reg. + +// None 16550 features +#define AUX_MU_CNTL_REG (AUX_IO_BASE+0x060) // AUX control reg. +#define AUX_MU_CNTL_REC_ENBL 0x01 // receiver enable +#define AUX_MU_CNTL_TRN_ENBL 0x02 // transmitter enable +#define AUX_MU_CNTL_AUTO_RTR 0x04 // RTR set by RX FF level +#define AUX_MU_CNTL_AUTO_CTS 0x08 // CTS auto stops transmitter +#define AUX_MU_CNTL_FLOW3 0x00 // Stop on RX FF 3 entries left +#define AUX_MU_CNTL_FLOW2 0x10 // Stop on RX FF 2 entries left +#define AUX_MU_CNTL_FLOW1 0x20 // Stop on RX FF 1 entries left +#define AUX_MU_CNTL_FLOW4 0x30 // Stop on RX FF 4 entries left +#define AUX_MU_CNTL_AURTRINV 0x40 // Invert AUTO RTR polarity +#define AUX_MU_CNTL_AUCTSINV 0x80 // Invert AUTO CTS polarity + + +#define AUX_MU_STAT_REG (AUX_IO_BASE+0x064) // AUX status reg. +#define AUX_MU_STAT_RX_DATA 0x00000001 // RX FF has value +#define AUX_MU_STAT_TX_SPACE 0x00000002 // TX FF has space (not full) +#define AUX_MU_STAT_RX_IDLE 0x00000004 // Receiver is idle +#define AUX_MU_STAT_TX_IDLE 0x00000008 // Transmitter is idle +#define AUX_MU_STAT_RX_OFLW 0x00000010 // Receiver FF overflow error +#define AUX_MU_STAT_TX_FULL 0x00000020 // Transmit FF full +#define AUX_MU_STAT_RTR 0x00000040 // Status of the RTR line +#define AUX_MU_STAT_CTS 0x00000080 // Status of the CTS line (fully synced) +#define AUX_MU_STAT_TXEMPTY 0x00000100 // TX FF is empty +#define AUX_MU_STAT_TXDONE 0x00000200 // TX FF is empty and TX is idle +#define AUX_MU_STAT_RXFILL 0x00FF0000 // RX FF fill level +#define AUX_MU_STAT_TXFILL 0xFF000000 // TX FF fill level + +#define AUX_MU_BAUD_REG (AUX_IO_BASE+0x068) // Baudrate reg (16 bits) + // Baud rate = sysclk/(8*(BAUD_REG+1)) + +// +// SPI 0 (SPI1 in the device!) +// +#define AUX_SPI0_CNTL0_REG (AUX_IO_BASE+0x080) // control reg 0 +#define AUX_SPI_CNTL0_BITS 0x0000003F // Number of bits to send/receive +#define AUX_SPI_CNTL0_OUTMS 0x00000040 // Shift MS bit out first) +#define AUX_SPI_CNTL0_INVCLK 0x00000080 // Invert SPI_CLK +#define AUX_SPI_CNTL0_OUTRISE 0x00000100 // data out leaves on rising clock edge +#define AUX_SPI_CNTL0_OUTFALL 0x00000000 // data out leaves on falling clock edge +#define AUX_SPI_CNTL0_FFCLR 0x00000200 // Reset fifos (Set and clear bit) +#define AUX_SPI_CNTL0_INRISE 0x00000400 // data in on rising clock edge +#define AUX_SPI_CNTL0_INFALL 0x00000000 // data in on falling clock edge +#define AUX_SPI_CNTL0_SERENBL 0x00000800 // Serial enable (does not disable FFs) +#define AUX_SPI_CNTL0_HOLD0 0x00000000 // Dout hold 0 sys clock cycles +#define AUX_SPI_CNTL0_HOLD4 0x00001000 // Dout hold 4 sys clock cycle +#define AUX_SPI_CNTL0_HOLD7 0x00002000 // Dout hold 7 sys clock cycles +#define AUX_SPI_CNTL0_HOLD10 0x00003000 // Dout hold 10 sys clock cycles +#define AUX_SPI_CNTL0_VARWID 0x00004000 // Variable width mode (din[15-12]=bits) +#define AUX_SPI_CNTL0_CSFROMFF 0x00008000 // CS pattern comesfrom MS 3 TX FIFO bits +#define AUX_SPI_CNTL0_POSTIN 0x00010000 // Load last bit after cycles finished +#define AUX_SPI_CNTL0_CS_HIGH 0x000E0000 // All CS are high +#define AUX_SPI_CNTL0_CS0_N 0x000C0000 // CS 0 low +#define AUX_SPI_CNTL0_CS1_N 0x000A0000 // CS 1 low +#define AUX_SPI_CNTL0_CS2_N 0x00060000 // CS 2 low +#define AUX_SPI_CNTL0_CSA_N 0x00000000 // ALL CS low (test only) +#define AUX_SPI_CNTL0_SPEED 0xFFF00000 // SPI clock = sysclock/(2xspeed) +#define AUX_SPI_CNTL0_SPEEDSHFT 20 // Speed shift left value + +#define AUX_SPI0_CNTL1_REG (AUX_IO_BASE+0x084) // control reg 1 +#define AUX_SPI_CNTL1_HOLDIN 0x00000001 // Do not clear DIN register at start +#define AUX_SPI_CNTL1_INMS 0x00000002 // Shift data in MS first MS--->LS +//#define AUX_SPI_CNTL1_CS_NOW 0x00000004 // Assert CS pattern now +#define AUX_SPI_CNTL1_EMPTYIRQ 0x00000040 // IRQ on TX Fifo empty +#define AUX_SPI_CNTL1_DONEIRQ 0x00000080 // IRQ on IDLE AND TxFifo empty +#define AUX_SPI_CNTL1_CSPLUS1 0x00000100 // CS HI plus 1 bit +#define AUX_SPI_CNTL1_CSPLUS2 0x00000200 // CS HI plus 2 bit +#define AUX_SPI_CNTL1_CSPLUS3 0x00000300 // CS HI plus 3 bit +#define AUX_SPI_CNTL1_CSPLUS4 0x00000400 // CS HI plus 4 bit +#define AUX_SPI_CNTL1_CSPLUS5 0x00000500 // CS HI plus 5 bit +#define AUX_SPI_CNTL1_CSPLUS6 0x00000600 // CS HI plus 6 bit +#define AUX_SPI_CNTL1_CSPLUS7 0x00000700 // CS HI plus 7 bit + +#define AUX_SPI0_STAT_REG (AUX_IO_BASE+0x088) // Status reg. +#define AUX_SPI_STAT_BITCNT 0x0000003F // Bits remaining to be shifted out +#define AUX_SPI_STAT_BUSY 0x00000040 // FSM is busy +#define AUX_SPI_STAT_RXEMPTY 0x00000080 // RX FF is empty +#define AUX_SPI_STAT_RXFULL 0x00000100 // RX FF is full +#define AUX_SPI_STAT_TXEMPTY 0x00000200 // TX FF is empyt +#define AUX_SPI_STAT_TXFULL 0x00000400 // TX FF is full +#define AUX_SPI_STAT_RXFILL 0x000F0000 // RX FF fill level +#define AUX_SPI_STAT_TXFILL 0x0F000000 // TX FF fill level +#define AUX_SPI0_PEEK_REG (AUX_IO_BASE+0x08C) // Read but do not take from FF +#define AUX_SPI0_IO_REG (AUX_IO_BASE+0x0A0) // Write = TX, read=RX +#define AUX_SPI0_TXHOLD_REG (AUX_IO_BASE+0x0B0) // Write = TX keep cs, read=RX + + + +// +// SPI 1 (SPI2 in the device!) +// +#define AUX_SPI1_CNTL0_REG (AUX_IO_BASE+0x0C0) +#define AUX_SPI1_CNTL1_REG (AUX_IO_BASE+0x0C4) +#define AUX_SPI1_STAT_REG (AUX_IO_BASE+0x0C8) +#define AUX_SPI1_PEEK_REG (AUX_IO_BASE+0x0CC) +#define AUX_SPI1_IO_REG (AUX_IO_BASE+0x0E0) +#define AUX_SPI1_TXHOLD_REG (AUX_IO_BASE+0x0F0) // Write = TX keep cs, read=RX + +// +// Some usefull GPIO macros +// +#define CLR_GPIO(g) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))&= ~(7<<(((g)%10)*3)) +#define SET_GPIO_ALT(g,a) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))|= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) diff --git a/bcm2708_chip/ave_in.h b/bcm2708_chip/ave_in.h new file mode 100755 index 0000000..d35fccf --- /dev/null +++ b/bcm2708_chip/ave_in.h @@ -0,0 +1,334 @@ +// This file was generated by the create_regs script +#define AVE_IN_BASE 0x7e910000 +#define AVE_IN_APB_ID 0x61766530 +#define AVE_IN_CTRL HW_REGISTER_RW( 0x7e910000 ) + #define AVE_IN_CTRL_MASK 0x87ffffff + #define AVE_IN_CTRL_WIDTH 32 + #define AVE_IN_CTRL_RESET 0x08000080 + #define AVE_IN_CTRL_ENABLE_BITS 31:31 + #define AVE_IN_CTRL_ENABLE_SET 0x80000000 + #define AVE_IN_CTRL_ENABLE_CLR 0x7fffffff + #define AVE_IN_CTRL_ENABLE_MSB 31 + #define AVE_IN_CTRL_ENABLE_LSB 31 + #define AVE_IN_CTRL_PRIORITY_LIMIT_BITS 26:24 + #define AVE_IN_CTRL_PRIORITY_LIMIT_SET 0x07000000 + #define AVE_IN_CTRL_PRIORITY_LIMIT_CLR 0xf8ffffff + #define AVE_IN_CTRL_PRIORITY_LIMIT_MSB 26 + #define AVE_IN_CTRL_PRIORITY_LIMIT_LSB 24 + #define AVE_IN_CTRL_HIGH_PRIORITY_BITS 23:20 + #define AVE_IN_CTRL_HIGH_PRIORITY_SET 0x00f00000 + #define AVE_IN_CTRL_HIGH_PRIORITY_CLR 0xff0fffff + #define AVE_IN_CTRL_HIGH_PRIORITY_MSB 23 + #define AVE_IN_CTRL_HIGH_PRIORITY_LSB 20 + #define AVE_IN_CTRL_LOW_PRIORITY_BITS 19:16 + #define AVE_IN_CTRL_LOW_PRIORITY_SET 0x000f0000 + #define AVE_IN_CTRL_LOW_PRIORITY_CLR 0xfff0ffff + #define AVE_IN_CTRL_LOW_PRIORITY_MSB 19 + #define AVE_IN_CTRL_LOW_PRIORITY_LSB 16 + #define AVE_IN_CTRL_EN_OVERRUN_ABORT_BITS 15:15 + #define AVE_IN_CTRL_EN_OVERRUN_ABORT_SET 0x00008000 + #define AVE_IN_CTRL_EN_OVERRUN_ABORT_CLR 0xffff7fff + #define AVE_IN_CTRL_EN_OVERRUN_ABORT_MSB 15 + #define AVE_IN_CTRL_EN_OVERRUN_ABORT_LSB 15 + #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_BITS 14:14 + #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_SET 0x00004000 + #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_CLR 0xffffbfff + #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_MSB 14 + #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_LSB 14 + #define AVE_IN_CTRL_BYTE_ORDER_BITS 13:11 + #define AVE_IN_CTRL_BYTE_ORDER_SET 0x00003800 + #define AVE_IN_CTRL_BYTE_ORDER_CLR 0xffffc7ff + #define AVE_IN_CTRL_BYTE_ORDER_MSB 13 + #define AVE_IN_CTRL_BYTE_ORDER_LSB 11 + #define AVE_IN_CTRL_FRAME_MODE_BITS 10:9 + #define AVE_IN_CTRL_FRAME_MODE_SET 0x00000600 + #define AVE_IN_CTRL_FRAME_MODE_CLR 0xfffff9ff + #define AVE_IN_CTRL_FRAME_MODE_MSB 10 + #define AVE_IN_CTRL_FRAME_MODE_LSB 9 + #define AVE_IN_CTRL_LENGTH_IN_PXLS_BITS 8:8 + #define AVE_IN_CTRL_LENGTH_IN_PXLS_SET 0x00000100 + #define AVE_IN_CTRL_LENGTH_IN_PXLS_CLR 0xfffffeff + #define AVE_IN_CTRL_LENGTH_IN_PXLS_MSB 8 + #define AVE_IN_CTRL_LENGTH_IN_PXLS_LSB 8 + #define AVE_IN_CTRL_PRIV_MODE_BITS 7:7 + #define AVE_IN_CTRL_PRIV_MODE_SET 0x00000080 + #define AVE_IN_CTRL_PRIV_MODE_CLR 0xffffff7f + #define AVE_IN_CTRL_PRIV_MODE_MSB 7 + #define AVE_IN_CTRL_PRIV_MODE_LSB 7 + #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_BITS 6:6 + #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_SET 0x00000040 + #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_CLR 0xffffffbf + #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_MSB 6 + #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_LSB 6 + #define AVE_IN_CTRL_HSYNC_IRQ_EN_BITS 5:5 + #define AVE_IN_CTRL_HSYNC_IRQ_EN_SET 0x00000020 + #define AVE_IN_CTRL_HSYNC_IRQ_EN_CLR 0xffffffdf + #define AVE_IN_CTRL_HSYNC_IRQ_EN_MSB 5 + #define AVE_IN_CTRL_HSYNC_IRQ_EN_LSB 5 + #define AVE_IN_CTRL_LINE_IRQ_EN_BITS 4:4 + #define AVE_IN_CTRL_LINE_IRQ_EN_SET 0x00000010 + #define AVE_IN_CTRL_LINE_IRQ_EN_CLR 0xffffffef + #define AVE_IN_CTRL_LINE_IRQ_EN_MSB 4 + #define AVE_IN_CTRL_LINE_IRQ_EN_LSB 4 + #define AVE_IN_CTRL_BUF_SER_IRQ_EN_BITS 3:3 + #define AVE_IN_CTRL_BUF_SER_IRQ_EN_SET 0x00000008 + #define AVE_IN_CTRL_BUF_SER_IRQ_EN_CLR 0xfffffff7 + #define AVE_IN_CTRL_BUF_SER_IRQ_EN_MSB 3 + #define AVE_IN_CTRL_BUF_SER_IRQ_EN_LSB 3 + #define AVE_IN_CTRL_BUF1_IRQ_EN_BITS 2:2 + #define AVE_IN_CTRL_BUF1_IRQ_EN_SET 0x00000004 + #define AVE_IN_CTRL_BUF1_IRQ_EN_CLR 0xfffffffb + #define AVE_IN_CTRL_BUF1_IRQ_EN_MSB 2 + #define AVE_IN_CTRL_BUF1_IRQ_EN_LSB 2 + #define AVE_IN_CTRL_BUF0_IRQ_EN_BITS 1:1 + #define AVE_IN_CTRL_BUF0_IRQ_EN_SET 0x00000002 + #define AVE_IN_CTRL_BUF0_IRQ_EN_CLR 0xfffffffd + #define AVE_IN_CTRL_BUF0_IRQ_EN_MSB 1 + #define AVE_IN_CTRL_BUF0_IRQ_EN_LSB 1 + #define AVE_IN_CTRL_OVERRUN_IRQ_EN_BITS 0:0 + #define AVE_IN_CTRL_OVERRUN_IRQ_EN_SET 0x00000001 + #define AVE_IN_CTRL_OVERRUN_IRQ_EN_CLR 0xfffffffe + #define AVE_IN_CTRL_OVERRUN_IRQ_EN_MSB 0 + #define AVE_IN_CTRL_OVERRUN_IRQ_EN_LSB 0 +#define AVE_IN_STATUS HW_REGISTER_RW( 0x7e910004 ) + #define AVE_IN_STATUS_MASK 0x9f733f7f + #define AVE_IN_STATUS_WIDTH 32 + #define AVE_IN_STATUS_RESET 0000000000 + #define AVE_IN_STATUS_CAPTURING_BITS 31:31 + #define AVE_IN_STATUS_CAPTURING_SET 0x80000000 + #define AVE_IN_STATUS_CAPTURING_CLR 0x7fffffff + #define AVE_IN_STATUS_CAPTURING_MSB 31 + #define AVE_IN_STATUS_CAPTURING_LSB 31 + #define AVE_IN_STATUS_OVERRUN_CNT_BITS 28:24 + #define AVE_IN_STATUS_OVERRUN_CNT_SET 0x1f000000 + #define AVE_IN_STATUS_OVERRUN_CNT_CLR 0xe0ffffff + #define AVE_IN_STATUS_OVERRUN_CNT_MSB 28 + #define AVE_IN_STATUS_OVERRUN_CNT_LSB 24 + #define AVE_IN_STATUS_AXI_STATE_BITS 22:20 + #define AVE_IN_STATUS_AXI_STATE_SET 0x00700000 + #define AVE_IN_STATUS_AXI_STATE_CLR 0xff8fffff + #define AVE_IN_STATUS_AXI_STATE_MSB 22 + #define AVE_IN_STATUS_AXI_STATE_LSB 20 + #define AVE_IN_STATUS_CURRENT_BUF_BITS 17:17 + #define AVE_IN_STATUS_CURRENT_BUF_SET 0x00020000 + #define AVE_IN_STATUS_CURRENT_BUF_CLR 0xfffdffff + #define AVE_IN_STATUS_CURRENT_BUF_MSB 17 + #define AVE_IN_STATUS_CURRENT_BUF_LSB 17 + #define AVE_IN_STATUS_MAX_HIT_BITS 16:16 + #define AVE_IN_STATUS_MAX_HIT_SET 0x00010000 + #define AVE_IN_STATUS_MAX_HIT_CLR 0xfffeffff + #define AVE_IN_STATUS_MAX_HIT_MSB 16 + #define AVE_IN_STATUS_MAX_HIT_LSB 16 + #define AVE_IN_STATUS_CSYNC_FIELD_BITS 13:13 + #define AVE_IN_STATUS_CSYNC_FIELD_SET 0x00002000 + #define AVE_IN_STATUS_CSYNC_FIELD_CLR 0xffffdfff + #define AVE_IN_STATUS_CSYNC_FIELD_MSB 13 + #define AVE_IN_STATUS_CSYNC_FIELD_LSB 13 + #define AVE_IN_STATUS_VFORM_FIELD_BITS 12:12 + #define AVE_IN_STATUS_VFORM_FIELD_SET 0x00001000 + #define AVE_IN_STATUS_VFORM_FIELD_CLR 0xffffefff + #define AVE_IN_STATUS_VFORM_FIELD_MSB 12 + #define AVE_IN_STATUS_VFORM_FIELD_LSB 12 + #define AVE_IN_STATUS_EVEN_FIELD_BITS 11:11 + #define AVE_IN_STATUS_EVEN_FIELD_SET 0x00000800 + #define AVE_IN_STATUS_EVEN_FIELD_CLR 0xfffff7ff + #define AVE_IN_STATUS_EVEN_FIELD_MSB 11 + #define AVE_IN_STATUS_EVEN_FIELD_LSB 11 + #define AVE_IN_STATUS_INTERLACED_BITS 10:10 + #define AVE_IN_STATUS_INTERLACED_SET 0x00000400 + #define AVE_IN_STATUS_INTERLACED_CLR 0xfffffbff + #define AVE_IN_STATUS_INTERLACED_MSB 10 + #define AVE_IN_STATUS_INTERLACED_LSB 10 + #define AVE_IN_STATUS_FRAME_RATE_BITS 9:8 + #define AVE_IN_STATUS_FRAME_RATE_SET 0x00000300 + #define AVE_IN_STATUS_FRAME_RATE_CLR 0xfffffcff + #define AVE_IN_STATUS_FRAME_RATE_MSB 9 + #define AVE_IN_STATUS_FRAME_RATE_LSB 8 + #define AVE_IN_STATUS_FRAME_RATE_DET_BITS 6:6 + #define AVE_IN_STATUS_FRAME_RATE_DET_SET 0x00000040 + #define AVE_IN_STATUS_FRAME_RATE_DET_CLR 0xffffffbf + #define AVE_IN_STATUS_FRAME_RATE_DET_MSB 6 + #define AVE_IN_STATUS_FRAME_RATE_DET_LSB 6 + #define AVE_IN_STATUS_HSYNC_DET_BITS 5:5 + #define AVE_IN_STATUS_HSYNC_DET_SET 0x00000020 + #define AVE_IN_STATUS_HSYNC_DET_CLR 0xffffffdf + #define AVE_IN_STATUS_HSYNC_DET_MSB 5 + #define AVE_IN_STATUS_HSYNC_DET_LSB 5 + #define AVE_IN_STATUS_LINE_NUM_HIT_BITS 4:4 + #define AVE_IN_STATUS_LINE_NUM_HIT_SET 0x00000010 + #define AVE_IN_STATUS_LINE_NUM_HIT_CLR 0xffffffef + #define AVE_IN_STATUS_LINE_NUM_HIT_MSB 4 + #define AVE_IN_STATUS_LINE_NUM_HIT_LSB 4 + #define AVE_IN_STATUS_BUF_NOT_SERV_BITS 3:3 + #define AVE_IN_STATUS_BUF_NOT_SERV_SET 0x00000008 + #define AVE_IN_STATUS_BUF_NOT_SERV_CLR 0xfffffff7 + #define AVE_IN_STATUS_BUF_NOT_SERV_MSB 3 + #define AVE_IN_STATUS_BUF_NOT_SERV_LSB 3 + #define AVE_IN_STATUS_BUF1_COMPL_BITS 2:2 + #define AVE_IN_STATUS_BUF1_COMPL_SET 0x00000004 + #define AVE_IN_STATUS_BUF1_COMPL_CLR 0xfffffffb + #define AVE_IN_STATUS_BUF1_COMPL_MSB 2 + #define AVE_IN_STATUS_BUF1_COMPL_LSB 2 + #define AVE_IN_STATUS_BUF0_COMPL_BITS 1:1 + #define AVE_IN_STATUS_BUF0_COMPL_SET 0x00000002 + #define AVE_IN_STATUS_BUF0_COMPL_CLR 0xfffffffd + #define AVE_IN_STATUS_BUF0_COMPL_MSB 1 + #define AVE_IN_STATUS_BUF0_COMPL_LSB 1 + #define AVE_IN_STATUS_OVERRUN_DET_BITS 0:0 + #define AVE_IN_STATUS_OVERRUN_DET_SET 0x00000001 + #define AVE_IN_STATUS_OVERRUN_DET_CLR 0xfffffffe + #define AVE_IN_STATUS_OVERRUN_DET_MSB 0 + #define AVE_IN_STATUS_OVERRUN_DET_LSB 0 +#define AVE_IN_BUF0_ADDRESS HW_REGISTER_RW( 0x7e910008 ) + #define AVE_IN_BUF0_ADDRESS_MASK 0xffffffff + #define AVE_IN_BUF0_ADDRESS_WIDTH 32 + #define AVE_IN_BUF0_ADDRESS_RESET 0000000000 + #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_BITS 31:0 + #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_SET 0xffffffff + #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_CLR 0x00000000 + #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_MSB 31 + #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_LSB 0 +#define AVE_IN_BUF1_ADDRESS HW_REGISTER_RW( 0x7e91000c ) + #define AVE_IN_BUF1_ADDRESS_MASK 0xffffffff + #define AVE_IN_BUF1_ADDRESS_WIDTH 32 + #define AVE_IN_BUF1_ADDRESS_RESET 0000000000 + #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_BITS 31:0 + #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_SET 0xffffffff + #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_CLR 0x00000000 + #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_MSB 31 + #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_LSB 0 +#define AVE_IN_MAX_TRANSFER HW_REGISTER_RW( 0x7e910010 ) + #define AVE_IN_MAX_TRANSFER_MASK 0xffffffff + #define AVE_IN_MAX_TRANSFER_WIDTH 32 + #define AVE_IN_MAX_TRANSFER_RESET 0000000000 + #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_BITS 31:0 + #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_SET 0xffffffff + #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_CLR 0x00000000 + #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_MSB 31 + #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_LSB 0 +#define AVE_IN_LINE_LENGTH HW_REGISTER_RW( 0x7e910014 ) + #define AVE_IN_LINE_LENGTH_MASK 0x00000fff + #define AVE_IN_LINE_LENGTH_WIDTH 12 + #define AVE_IN_LINE_LENGTH_RESET 0000000000 + #define AVE_IN_LINE_LENGTH_LINE_LENGTH_BITS 11:0 + #define AVE_IN_LINE_LENGTH_LINE_LENGTH_SET 0x00000fff + #define AVE_IN_LINE_LENGTH_LINE_LENGTH_CLR 0xfffff000 + #define AVE_IN_LINE_LENGTH_LINE_LENGTH_MSB 11 + #define AVE_IN_LINE_LENGTH_LINE_LENGTH_LSB 0 +#define AVE_IN_CURRENT_ADDRESS HW_REGISTER_RW( 0x7e910018 ) + #define AVE_IN_CURRENT_ADDRESS_MASK 0xffffffff + #define AVE_IN_CURRENT_ADDRESS_WIDTH 32 + #define AVE_IN_CURRENT_ADDRESS_RESET 0000000000 + #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_BITS 31:0 + #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_SET 0xffffffff + #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_CLR 0x00000000 + #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_MSB 31 + #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_LSB 0 +#define AVE_IN_CURRENT_LINE_BUF0 HW_REGISTER_RW( 0x7e91001c ) + #define AVE_IN_CURRENT_LINE_BUF0_MASK 0x80000fff + #define AVE_IN_CURRENT_LINE_BUF0_WIDTH 32 + #define AVE_IN_CURRENT_LINE_BUF0_RESET 0000000000 + #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_BITS 11:0 + #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_SET 0x00000fff + #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_CLR 0xfffff000 + #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_MSB 11 + #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_LSB 0 + #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_BITS 31:31 + #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_SET 0x80000000 + #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_CLR 0x7fffffff + #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_MSB 31 + #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_LSB 31 +#define AVE_IN_CURRENT_LINE_BUF1 HW_REGISTER_RW( 0x7e910020 ) + #define AVE_IN_CURRENT_LINE_BUF1_MASK 0x80000fff + #define AVE_IN_CURRENT_LINE_BUF1_WIDTH 32 + #define AVE_IN_CURRENT_LINE_BUF1_RESET 0000000000 + #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_BITS 11:0 + #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_SET 0x00000fff + #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_CLR 0xfffff000 + #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_MSB 11 + #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_LSB 0 + #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_BITS 31:31 + #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_SET 0x80000000 + #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_CLR 0x7fffffff + #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_MSB 31 + #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_LSB 31 +#define AVE_IN_CURRENT_LINE_NUM HW_REGISTER_RW( 0x7e910024 ) + #define AVE_IN_CURRENT_LINE_NUM_MASK 0xe0000fff + #define AVE_IN_CURRENT_LINE_NUM_WIDTH 32 + #define AVE_IN_CURRENT_LINE_NUM_RESET 0000000000 + #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_BITS 11:0 + #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_SET 0x00000fff + #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_CLR 0xfffff000 + #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_MSB 11 + #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_LSB 0 + #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_BITS 29:29 + #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_SET 0x20000000 + #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_CLR 0xdfffffff + #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_MSB 29 + #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_LSB 29 + #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_BITS 30:30 + #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_SET 0x40000000 + #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_CLR 0xbfffffff + #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_MSB 30 + #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_LSB 30 + #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_BITS 31:31 + #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_SET 0x80000000 + #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_CLR 0x7fffffff + #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_MSB 31 + #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_LSB 31 +#define AVE_IN_OVERRUN_ADDRESS HW_REGISTER_RW( 0x7e910028 ) + #define AVE_IN_OVERRUN_ADDRESS_MASK 0xffffffff + #define AVE_IN_OVERRUN_ADDRESS_WIDTH 32 + #define AVE_IN_OVERRUN_ADDRESS_RESET 0000000000 + #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_BITS 31:0 + #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_SET 0xffffffff + #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_CLR 0x00000000 + #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_MSB 31 + #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_LSB 0 +#define AVE_IN_LINE_NUM_INT HW_REGISTER_RW( 0x7e91002c ) + #define AVE_IN_LINE_NUM_INT_MASK 0x00000fff + #define AVE_IN_LINE_NUM_INT_WIDTH 12 + #define AVE_IN_LINE_NUM_INT_RESET 0000000000 + #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_BITS 11:0 + #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_SET 0x00000fff + #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_CLR 0xfffff000 + #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_MSB 11 + #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_LSB 0 +#define AVE_IN_CALC_LINE_STEP HW_REGISTER_RW( 0x7e910030 ) + #define AVE_IN_CALC_LINE_STEP_MASK 0x00000fff + #define AVE_IN_CALC_LINE_STEP_WIDTH 12 + #define AVE_IN_CALC_LINE_STEP_RESET 0000000000 + #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_BITS 11:0 + #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_SET 0x00000fff + #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_CLR 0xfffff000 + #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_MSB 11 + #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_LSB 0 +#define AVE_IN_OUTSTANDING_BUFF0 HW_REGISTER_RW( 0x7e910034 ) + #define AVE_IN_OUTSTANDING_BUFF0_MASK 0x000000ff + #define AVE_IN_OUTSTANDING_BUFF0_WIDTH 8 + #define AVE_IN_OUTSTANDING_BUFF0_RESET 0000000000 +#define AVE_IN_OUTSTANDING_BUFF1 HW_REGISTER_RW( 0x7e910038 ) + #define AVE_IN_OUTSTANDING_BUFF1_MASK 0x000000ff + #define AVE_IN_OUTSTANDING_BUFF1_WIDTH 8 + #define AVE_IN_OUTSTANDING_BUFF1_RESET 0000000000 +#define AVE_IN_CHAR_CTRL HW_REGISTER_RW( 0x7e91003c ) + #define AVE_IN_CHAR_CTRL_MASK 0x8000000f + #define AVE_IN_CHAR_CTRL_WIDTH 32 + #define AVE_IN_CHAR_CTRL_RESET 0000000000 +#define AVE_IN_SYNC_CTRL HW_REGISTER_RW( 0x7e910040 ) + #define AVE_IN_SYNC_CTRL_MASK 0x0000008f + #define AVE_IN_SYNC_CTRL_WIDTH 8 + #define AVE_IN_SYNC_CTRL_RESET 0000000000 +#define AVE_IN_FRAME_NUM HW_REGISTER_RW( 0x7e910044 ) + #define AVE_IN_FRAME_NUM_MASK 0x00000fff + #define AVE_IN_FRAME_NUM_WIDTH 12 + #define AVE_IN_FRAME_NUM_RESET 0000000000 + #define AVE_IN_FRAME_NUM_FRAME_NUM_BITS 11:0 + #define AVE_IN_FRAME_NUM_FRAME_NUM_SET 0x00000fff + #define AVE_IN_FRAME_NUM_FRAME_NUM_CLR 0xfffff000 + #define AVE_IN_FRAME_NUM_FRAME_NUM_MSB 11 + #define AVE_IN_FRAME_NUM_FRAME_NUM_LSB 0 +#define AVE_IN_BLOCK_ID HW_REGISTER_RW( 0x7e910060 ) + #define AVE_IN_BLOCK_ID_MASK 0xffffffff + #define AVE_IN_BLOCK_ID_WIDTH 32 + #define AVE_IN_BLOCK_ID_RESET 0x61766530 diff --git a/bcm2708_chip/ave_out.h b/bcm2708_chip/ave_out.h new file mode 100755 index 0000000..ab7262e --- /dev/null +++ b/bcm2708_chip/ave_out.h @@ -0,0 +1,216 @@ +// This file was generated by the create_regs script +#define AVE_OUT_BASE 0x7e240000 +#define AVE_OUT_APB_ID 0x61766538 +#define AVE_OUT_CTRL HW_REGISTER_RW( 0x7e240000 ) + #define AVE_OUT_CTRL_MASK 0xc0fff13f + #define AVE_OUT_CTRL_WIDTH 32 + #define AVE_OUT_CTRL_RESET 0x40000100 + #define AVE_OUT_CTRL_ENABLE_BITS 31:31 + #define AVE_OUT_CTRL_ENABLE_SET 0x80000000 + #define AVE_OUT_CTRL_ENABLE_CLR 0x7fffffff + #define AVE_OUT_CTRL_ENABLE_MSB 31 + #define AVE_OUT_CTRL_ENABLE_LSB 31 + #define AVE_OUT_CTRL_SOFT_RESET_BITS 30:30 + #define AVE_OUT_CTRL_SOFT_RESET_SET 0x40000000 + #define AVE_OUT_CTRL_SOFT_RESET_CLR 0xbfffffff + #define AVE_OUT_CTRL_SOFT_RESET_MSB 30 + #define AVE_OUT_CTRL_SOFT_RESET_LSB 30 + #define AVE_OUT_CTRL_BYTE_SWAP_BITS 23:19 + #define AVE_OUT_CTRL_BYTE_SWAP_SET 0x00f80000 + #define AVE_OUT_CTRL_BYTE_SWAP_CLR 0xff07ffff + #define AVE_OUT_CTRL_BYTE_SWAP_MSB 23 + #define AVE_OUT_CTRL_BYTE_SWAP_LSB 19 + #define AVE_OUT_CTRL_INVERT_DSYNC_BITS 18:18 + #define AVE_OUT_CTRL_INVERT_DSYNC_SET 0x00040000 + #define AVE_OUT_CTRL_INVERT_DSYNC_CLR 0xfffbffff + #define AVE_OUT_CTRL_INVERT_DSYNC_MSB 18 + #define AVE_OUT_CTRL_INVERT_DSYNC_LSB 18 + #define AVE_OUT_CTRL_INVERT_CSYNC_BITS 17:17 + #define AVE_OUT_CTRL_INVERT_CSYNC_SET 0x00020000 + #define AVE_OUT_CTRL_INVERT_CSYNC_CLR 0xfffdffff + #define AVE_OUT_CTRL_INVERT_CSYNC_MSB 17 + #define AVE_OUT_CTRL_INVERT_CSYNC_LSB 17 + #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_BITS 16:16 + #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_SET 0x00010000 + #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_CLR 0xfffeffff + #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_MSB 16 + #define AVE_OUT_CTRL_INVERT_EVEN_FIELD_LSB 16 + #define AVE_OUT_CTRL_INVERT_VSYNC_BITS 15:15 + #define AVE_OUT_CTRL_INVERT_VSYNC_SET 0x00008000 + #define AVE_OUT_CTRL_INVERT_VSYNC_CLR 0xffff7fff + #define AVE_OUT_CTRL_INVERT_VSYNC_MSB 15 + #define AVE_OUT_CTRL_INVERT_VSYNC_LSB 15 + #define AVE_OUT_CTRL_INVERT_HSYNC_BITS 14:14 + #define AVE_OUT_CTRL_INVERT_HSYNC_SET 0x00004000 + #define AVE_OUT_CTRL_INVERT_HSYNC_CLR 0xffffbfff + #define AVE_OUT_CTRL_INVERT_HSYNC_MSB 14 + #define AVE_OUT_CTRL_INVERT_HSYNC_LSB 14 + #define AVE_OUT_CTRL_NTSC_PAL_IDENT_BITS 13:13 + #define AVE_OUT_CTRL_NTSC_PAL_IDENT_SET 0x00002000 + #define AVE_OUT_CTRL_NTSC_PAL_IDENT_CLR 0xffffdfff + #define AVE_OUT_CTRL_NTSC_PAL_IDENT_MSB 13 + #define AVE_OUT_CTRL_NTSC_PAL_IDENT_LSB 13 + #define AVE_OUT_CTRL_INTERLEAVE_BITS 12:12 + #define AVE_OUT_CTRL_INTERLEAVE_SET 0x00001000 + #define AVE_OUT_CTRL_INTERLEAVE_CLR 0xffffefff + #define AVE_OUT_CTRL_INTERLEAVE_MSB 12 + #define AVE_OUT_CTRL_INTERLEAVE_LSB 12 + #define AVE_OUT_CTRL_PRIV_ACCESS_BITS 8:8 + #define AVE_OUT_CTRL_PRIV_ACCESS_SET 0x00000100 + #define AVE_OUT_CTRL_PRIV_ACCESS_CLR 0xfffffeff + #define AVE_OUT_CTRL_PRIV_ACCESS_MSB 8 + #define AVE_OUT_CTRL_PRIV_ACCESS_LSB 8 + #define AVE_OUT_CTRL_MODE_BITS 5:4 + #define AVE_OUT_CTRL_MODE_SET 0x00000030 + #define AVE_OUT_CTRL_MODE_CLR 0xffffffcf + #define AVE_OUT_CTRL_MODE_MSB 5 + #define AVE_OUT_CTRL_MODE_LSB 4 + #define AVE_OUT_CTRL_REFRESH_RATE_BITS 3:2 + #define AVE_OUT_CTRL_REFRESH_RATE_SET 0x0000000c + #define AVE_OUT_CTRL_REFRESH_RATE_CLR 0xfffffff3 + #define AVE_OUT_CTRL_REFRESH_RATE_MSB 3 + #define AVE_OUT_CTRL_REFRESH_RATE_LSB 2 + #define AVE_OUT_CTRL_COEFF_IRQ_EN_BITS 1:1 + #define AVE_OUT_CTRL_COEFF_IRQ_EN_SET 0x00000002 + #define AVE_OUT_CTRL_COEFF_IRQ_EN_CLR 0xfffffffd + #define AVE_OUT_CTRL_COEFF_IRQ_EN_MSB 1 + #define AVE_OUT_CTRL_COEFF_IRQ_EN_LSB 1 + #define AVE_OUT_CTRL_ERROR_IRQ_EN_BITS 0:0 + #define AVE_OUT_CTRL_ERROR_IRQ_EN_SET 0x00000001 + #define AVE_OUT_CTRL_ERROR_IRQ_EN_CLR 0xfffffffe + #define AVE_OUT_CTRL_ERROR_IRQ_EN_MSB 0 + #define AVE_OUT_CTRL_ERROR_IRQ_EN_LSB 0 +#define AVE_OUT_STATUS HW_REGISTER_RW( 0x7e240004 ) + #define AVE_OUT_STATUS_MASK 0x000003f7 + #define AVE_OUT_STATUS_WIDTH 10 + #define AVE_OUT_STATUS_RESET 0000000000 + #define AVE_OUT_STATUS_VSYNC_BITS 9:9 + #define AVE_OUT_STATUS_VSYNC_SET 0x00000200 + #define AVE_OUT_STATUS_VSYNC_CLR 0xfffffdff + #define AVE_OUT_STATUS_VSYNC_MSB 9 + #define AVE_OUT_STATUS_VSYNC_LSB 9 + #define AVE_OUT_STATUS_VBACK_PORCH_BITS 8:8 + #define AVE_OUT_STATUS_VBACK_PORCH_SET 0x00000100 + #define AVE_OUT_STATUS_VBACK_PORCH_CLR 0xfffffeff + #define AVE_OUT_STATUS_VBACK_PORCH_MSB 8 + #define AVE_OUT_STATUS_VBACK_PORCH_LSB 8 + #define AVE_OUT_STATUS_VFRONT_PORCH_BITS 7:7 + #define AVE_OUT_STATUS_VFRONT_PORCH_SET 0x00000080 + #define AVE_OUT_STATUS_VFRONT_PORCH_CLR 0xffffff7f + #define AVE_OUT_STATUS_VFRONT_PORCH_MSB 7 + #define AVE_OUT_STATUS_VFRONT_PORCH_LSB 7 + #define AVE_OUT_STATUS_HSYNC_BITS 6:6 + #define AVE_OUT_STATUS_HSYNC_SET 0x00000040 + #define AVE_OUT_STATUS_HSYNC_CLR 0xffffffbf + #define AVE_OUT_STATUS_HSYNC_MSB 6 + #define AVE_OUT_STATUS_HSYNC_LSB 6 + #define AVE_OUT_STATUS_HBACK_PORCH_BITS 5:5 + #define AVE_OUT_STATUS_HBACK_PORCH_SET 0x00000020 + #define AVE_OUT_STATUS_HBACK_PORCH_CLR 0xffffffdf + #define AVE_OUT_STATUS_HBACK_PORCH_MSB 5 + #define AVE_OUT_STATUS_HBACK_PORCH_LSB 5 + #define AVE_OUT_STATUS_HFRONT_PORCH_BITS 4:4 + #define AVE_OUT_STATUS_HFRONT_PORCH_SET 0x00000010 + #define AVE_OUT_STATUS_HFRONT_PORCH_CLR 0xffffffef + #define AVE_OUT_STATUS_HFRONT_PORCH_MSB 4 + #define AVE_OUT_STATUS_HFRONT_PORCH_LSB 4 + #define AVE_OUT_STATUS_COEFF_ERROR_BITS 2:2 + #define AVE_OUT_STATUS_COEFF_ERROR_SET 0x00000004 + #define AVE_OUT_STATUS_COEFF_ERROR_CLR 0xfffffffb + #define AVE_OUT_STATUS_COEFF_ERROR_MSB 2 + #define AVE_OUT_STATUS_COEFF_ERROR_LSB 2 + #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_BITS 1:1 + #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_SET 0x00000002 + #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_CLR 0xfffffffd + #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_MSB 1 + #define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_LSB 1 + #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_BITS 0:0 + #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_SET 0x00000001 + #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_CLR 0xfffffffe + #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_MSB 0 + #define AVE_OUT_STATUS_PXL_FORMAT_ERROR_LSB 0 +#define AVE_OUT_OFFSET HW_REGISTER_RW( 0x7e240008 ) + #define AVE_OUT_OFFSET_MASK 0x80ffffff + #define AVE_OUT_OFFSET_WIDTH 32 + #define AVE_OUT_OFFSET_RESET 0x80109090 + #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_BITS 31:31 + #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_SET 0x80000000 + #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_CLR 0x7fffffff + #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_MSB 31 + #define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_LSB 31 + #define AVE_OUT_OFFSET_RED_OFFSET_BITS 23:16 + #define AVE_OUT_OFFSET_RED_OFFSET_SET 0x00ff0000 + #define AVE_OUT_OFFSET_RED_OFFSET_CLR 0xff00ffff + #define AVE_OUT_OFFSET_RED_OFFSET_MSB 23 + #define AVE_OUT_OFFSET_RED_OFFSET_LSB 16 + #define AVE_OUT_OFFSET_GREEN_OFFSET_BITS 15:8 + #define AVE_OUT_OFFSET_GREEN_OFFSET_SET 0x0000ff00 + #define AVE_OUT_OFFSET_GREEN_OFFSET_CLR 0xffff00ff + #define AVE_OUT_OFFSET_GREEN_OFFSET_MSB 15 + #define AVE_OUT_OFFSET_GREEN_OFFSET_LSB 8 + #define AVE_OUT_OFFSET_BLUE_OFFSET_BITS 7:0 + #define AVE_OUT_OFFSET_BLUE_OFFSET_SET 0x000000ff + #define AVE_OUT_OFFSET_BLUE_OFFSET_CLR 0xffffff00 + #define AVE_OUT_OFFSET_BLUE_OFFSET_MSB 7 + #define AVE_OUT_OFFSET_BLUE_OFFSET_LSB 0 +#define AVE_OUT_Y_COEFF HW_REGISTER_RW( 0x7e24000c ) + #define AVE_OUT_Y_COEFF_MASK 0x3fffffff + #define AVE_OUT_Y_COEFF_WIDTH 30 + #define AVE_OUT_Y_COEFF_RESET 0x0994b43a + #define AVE_OUT_Y_COEFF_RED_COEFF_BITS 29:20 + #define AVE_OUT_Y_COEFF_RED_COEFF_SET 0x3ff00000 + #define AVE_OUT_Y_COEFF_RED_COEFF_CLR 0xc00fffff + #define AVE_OUT_Y_COEFF_RED_COEFF_MSB 29 + #define AVE_OUT_Y_COEFF_RED_COEFF_LSB 20 + #define AVE_OUT_Y_COEFF_GREEN_COEFF_BITS 19:10 + #define AVE_OUT_Y_COEFF_GREEN_COEFF_SET 0x000ffc00 + #define AVE_OUT_Y_COEFF_GREEN_COEFF_CLR 0xfff003ff + #define AVE_OUT_Y_COEFF_GREEN_COEFF_MSB 19 + #define AVE_OUT_Y_COEFF_GREEN_COEFF_LSB 10 + #define AVE_OUT_Y_COEFF_BLUE_COEFF_BITS 9:0 + #define AVE_OUT_Y_COEFF_BLUE_COEFF_SET 0x000003ff + #define AVE_OUT_Y_COEFF_BLUE_COEFF_CLR 0xfffffc00 + #define AVE_OUT_Y_COEFF_BLUE_COEFF_MSB 9 + #define AVE_OUT_Y_COEFF_BLUE_COEFF_LSB 0 +#define AVE_OUT_CB_COEFF HW_REGISTER_RW( 0x7e240010 ) + #define AVE_OUT_CB_COEFF_MASK 0x3fffffff + #define AVE_OUT_CB_COEFF_WIDTH 30 + #define AVE_OUT_CB_COEFF_RESET 0x3a9d5900 + #define AVE_OUT_CB_COEFF_RED_COEFF_BITS 29:20 + #define AVE_OUT_CB_COEFF_RED_COEFF_SET 0x3ff00000 + #define AVE_OUT_CB_COEFF_RED_COEFF_CLR 0xc00fffff + #define AVE_OUT_CB_COEFF_RED_COEFF_MSB 29 + #define AVE_OUT_CB_COEFF_RED_COEFF_LSB 20 + #define AVE_OUT_CB_COEFF_GREEN_COEFF_BITS 19:10 + #define AVE_OUT_CB_COEFF_GREEN_COEFF_SET 0x000ffc00 + #define AVE_OUT_CB_COEFF_GREEN_COEFF_CLR 0xfff003ff + #define AVE_OUT_CB_COEFF_GREEN_COEFF_MSB 19 + #define AVE_OUT_CB_COEFF_GREEN_COEFF_LSB 10 + #define AVE_OUT_CB_COEFF_BLUE_COEFF_BITS 9:0 + #define AVE_OUT_CB_COEFF_BLUE_COEFF_SET 0x000003ff + #define AVE_OUT_CB_COEFF_BLUE_COEFF_CLR 0xfffffc00 + #define AVE_OUT_CB_COEFF_BLUE_COEFF_MSB 9 + #define AVE_OUT_CB_COEFF_BLUE_COEFF_LSB 0 +#define AVE_OUT_CR_COEFF HW_REGISTER_RW( 0x7e240014 ) + #define AVE_OUT_CR_COEFF_MASK 0x3fffffff + #define AVE_OUT_CR_COEFF_WIDTH 30 + #define AVE_OUT_CR_COEFF_RESET 0x100ca7d6 + #define AVE_OUT_CR_COEFF_RED_COEFF_BITS 29:20 + #define AVE_OUT_CR_COEFF_RED_COEFF_SET 0x3ff00000 + #define AVE_OUT_CR_COEFF_RED_COEFF_CLR 0xc00fffff + #define AVE_OUT_CR_COEFF_RED_COEFF_MSB 29 + #define AVE_OUT_CR_COEFF_RED_COEFF_LSB 20 + #define AVE_OUT_CR_COEFF_GREEN_COEFF_BITS 19:10 + #define AVE_OUT_CR_COEFF_GREEN_COEFF_SET 0x000ffc00 + #define AVE_OUT_CR_COEFF_GREEN_COEFF_CLR 0xfff003ff + #define AVE_OUT_CR_COEFF_GREEN_COEFF_MSB 19 + #define AVE_OUT_CR_COEFF_GREEN_COEFF_LSB 10 + #define AVE_OUT_CR_COEFF_BLUE_COEFF_BITS 9:0 + #define AVE_OUT_CR_COEFF_BLUE_COEFF_SET 0x000003ff + #define AVE_OUT_CR_COEFF_BLUE_COEFF_CLR 0xfffffc00 + #define AVE_OUT_CR_COEFF_BLUE_COEFF_MSB 9 + #define AVE_OUT_CR_COEFF_BLUE_COEFF_LSB 0 +#define AVE_OUT_BLOCK_ID HW_REGISTER_RW( 0x7e240060 ) + #define AVE_OUT_BLOCK_ID_MASK 0xffffffff + #define AVE_OUT_BLOCK_ID_WIDTH 32 + #define AVE_OUT_BLOCK_ID_RESET 0x61766538 diff --git a/bcm2708_chip/axi_dma0.h b/bcm2708_chip/axi_dma0.h new file mode 100755 index 0000000..897e88b --- /dev/null +++ b/bcm2708_chip/axi_dma0.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA0_BASE 0x7e007000 +#define DMA0_CS HW_REGISTER_RW( 0x7e007000 ) + #define DMA0_CS_MASK 0xf0ff017f + #define DMA0_CS_WIDTH 32 + #define DMA0_CS_RESET 0000000000 + #define DMA0_CS_RESET_BITS 31:31 + #define DMA0_CS_RESET_SET 0x80000000 + #define DMA0_CS_RESET_CLR 0x7fffffff + #define DMA0_CS_RESET_MSB 31 + #define DMA0_CS_RESET_LSB 31 + #define DMA0_CS_ABORT_BITS 30:30 + #define DMA0_CS_ABORT_SET 0x40000000 + #define DMA0_CS_ABORT_CLR 0xbfffffff + #define DMA0_CS_ABORT_MSB 30 + #define DMA0_CS_ABORT_LSB 30 + #define DMA0_CS_DISDEBUG_BITS 29:29 + #define DMA0_CS_DISDEBUG_SET 0x20000000 + #define DMA0_CS_DISDEBUG_CLR 0xdfffffff + #define DMA0_CS_DISDEBUG_MSB 29 + #define DMA0_CS_DISDEBUG_LSB 29 + #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA0_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA0_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA0_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA0_CS_PANIC_PRIORITY_MSB 23 + #define DMA0_CS_PANIC_PRIORITY_LSB 20 + #define DMA0_CS_PRIORITY_BITS 19:16 + #define DMA0_CS_PRIORITY_SET 0x000f0000 + #define DMA0_CS_PRIORITY_CLR 0xfff0ffff + #define DMA0_CS_PRIORITY_MSB 19 + #define DMA0_CS_PRIORITY_LSB 16 + #define DMA0_CS_ERROR_BITS 8:8 + #define DMA0_CS_ERROR_SET 0x00000100 + #define DMA0_CS_ERROR_CLR 0xfffffeff + #define DMA0_CS_ERROR_MSB 8 + #define DMA0_CS_ERROR_LSB 8 + #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA0_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA0_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA0_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA0_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA0_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA0_CS_PAUSED_BITS 4:4 + #define DMA0_CS_PAUSED_SET 0x00000010 + #define DMA0_CS_PAUSED_CLR 0xffffffef + #define DMA0_CS_PAUSED_MSB 4 + #define DMA0_CS_PAUSED_LSB 4 + #define DMA0_CS_DREQ_BITS 3:3 + #define DMA0_CS_DREQ_SET 0x00000008 + #define DMA0_CS_DREQ_CLR 0xfffffff7 + #define DMA0_CS_DREQ_MSB 3 + #define DMA0_CS_DREQ_LSB 3 + #define DMA0_CS_INT_BITS 2:2 + #define DMA0_CS_INT_SET 0x00000004 + #define DMA0_CS_INT_CLR 0xfffffffb + #define DMA0_CS_INT_MSB 2 + #define DMA0_CS_INT_LSB 2 + #define DMA0_CS_END_BITS 1:1 + #define DMA0_CS_END_SET 0x00000002 + #define DMA0_CS_END_CLR 0xfffffffd + #define DMA0_CS_END_MSB 1 + #define DMA0_CS_END_LSB 1 + #define DMA0_CS_ACTIVE_BITS 0:0 + #define DMA0_CS_ACTIVE_SET 0x00000001 + #define DMA0_CS_ACTIVE_CLR 0xfffffffe + #define DMA0_CS_ACTIVE_MSB 0 + #define DMA0_CS_ACTIVE_LSB 0 +#define DMA0_CONBLK_AD HW_REGISTER_RW( 0x7e007004 ) + #define DMA0_CONBLK_AD_MASK 0xffffffe0 + #define DMA0_CONBLK_AD_WIDTH 32 + #define DMA0_CONBLK_AD_RESET 0000000000 + #define DMA0_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA0_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA0_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA0_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA0_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA0_TI HW_REGISTER_RO( 0x7e007008 ) + #define DMA0_TI_MASK 0x07fffffb + #define DMA0_TI_WIDTH 27 + #define DMA0_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA0_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA0_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA0_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA0_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA0_TI_WAITS_BITS 25:21 + #define DMA0_TI_WAITS_SET 0x03e00000 + #define DMA0_TI_WAITS_CLR 0xfc1fffff + #define DMA0_TI_WAITS_MSB 25 + #define DMA0_TI_WAITS_LSB 21 + #define DMA0_TI_PERMAP_BITS 20:16 + #define DMA0_TI_PERMAP_SET 0x001f0000 + #define DMA0_TI_PERMAP_CLR 0xffe0ffff + #define DMA0_TI_PERMAP_MSB 20 + #define DMA0_TI_PERMAP_LSB 16 + #define DMA0_TI_BURST_LENGTH_BITS 15:12 + #define DMA0_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA0_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA0_TI_BURST_LENGTH_MSB 15 + #define DMA0_TI_BURST_LENGTH_LSB 12 + #define DMA0_TI_SRC_IGNORE_BITS 11:11 + #define DMA0_TI_SRC_IGNORE_SET 0x00000800 + #define DMA0_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA0_TI_SRC_IGNORE_MSB 11 + #define DMA0_TI_SRC_IGNORE_LSB 11 + #define DMA0_TI_SRC_DREQ_BITS 10:10 + #define DMA0_TI_SRC_DREQ_SET 0x00000400 + #define DMA0_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA0_TI_SRC_DREQ_MSB 10 + #define DMA0_TI_SRC_DREQ_LSB 10 + #define DMA0_TI_SRC_WIDTH_BITS 9:9 + #define DMA0_TI_SRC_WIDTH_SET 0x00000200 + #define DMA0_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA0_TI_SRC_WIDTH_MSB 9 + #define DMA0_TI_SRC_WIDTH_LSB 9 + #define DMA0_TI_SRC_INC_BITS 8:8 + #define DMA0_TI_SRC_INC_SET 0x00000100 + #define DMA0_TI_SRC_INC_CLR 0xfffffeff + #define DMA0_TI_SRC_INC_MSB 8 + #define DMA0_TI_SRC_INC_LSB 8 + #define DMA0_TI_DEST_IGNORE_BITS 7:7 + #define DMA0_TI_DEST_IGNORE_SET 0x00000080 + #define DMA0_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA0_TI_DEST_IGNORE_MSB 7 + #define DMA0_TI_DEST_IGNORE_LSB 7 + #define DMA0_TI_DEST_DREQ_BITS 6:6 + #define DMA0_TI_DEST_DREQ_SET 0x00000040 + #define DMA0_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA0_TI_DEST_DREQ_MSB 6 + #define DMA0_TI_DEST_DREQ_LSB 6 + #define DMA0_TI_DEST_WIDTH_BITS 5:5 + #define DMA0_TI_DEST_WIDTH_SET 0x00000020 + #define DMA0_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA0_TI_DEST_WIDTH_MSB 5 + #define DMA0_TI_DEST_WIDTH_LSB 5 + #define DMA0_TI_DEST_INC_BITS 4:4 + #define DMA0_TI_DEST_INC_SET 0x00000010 + #define DMA0_TI_DEST_INC_CLR 0xffffffef + #define DMA0_TI_DEST_INC_MSB 4 + #define DMA0_TI_DEST_INC_LSB 4 + #define DMA0_TI_WAIT_RESP_BITS 3:3 + #define DMA0_TI_WAIT_RESP_SET 0x00000008 + #define DMA0_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA0_TI_WAIT_RESP_MSB 3 + #define DMA0_TI_WAIT_RESP_LSB 3 + #define DMA0_TI_TDMODE_BITS 1:1 + #define DMA0_TI_TDMODE_SET 0x00000002 + #define DMA0_TI_TDMODE_CLR 0xfffffffd + #define DMA0_TI_TDMODE_MSB 1 + #define DMA0_TI_TDMODE_LSB 1 + #define DMA0_TI_INTEN_BITS 0:0 + #define DMA0_TI_INTEN_SET 0x00000001 + #define DMA0_TI_INTEN_CLR 0xfffffffe + #define DMA0_TI_INTEN_MSB 0 + #define DMA0_TI_INTEN_LSB 0 +#define DMA0_SOURCE_AD HW_REGISTER_RO( 0x7e00700c ) + #define DMA0_SOURCE_AD_MASK 0xffffffff + #define DMA0_SOURCE_AD_WIDTH 32 + #define DMA0_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA0_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA0_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA0_SOURCE_AD_S_ADDR_MSB 31 + #define DMA0_SOURCE_AD_S_ADDR_LSB 0 +#define DMA0_DEST_AD HW_REGISTER_RO( 0x7e007010 ) + #define DMA0_DEST_AD_MASK 0xffffffff + #define DMA0_DEST_AD_WIDTH 32 + #define DMA0_DEST_AD_D_ADDR_BITS 31:0 + #define DMA0_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA0_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA0_DEST_AD_D_ADDR_MSB 31 + #define DMA0_DEST_AD_D_ADDR_LSB 0 +#define DMA0_TXFR_LEN HW_REGISTER_RO( 0x7e007014 ) + #define DMA0_TXFR_LEN_MASK 0x3fffffff + #define DMA0_TXFR_LEN_WIDTH 30 + #define DMA0_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA0_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA0_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA0_TXFR_LEN_YLENGTH_MSB 29 + #define DMA0_TXFR_LEN_YLENGTH_LSB 16 + #define DMA0_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA0_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA0_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA0_TXFR_LEN_XLENGTH_MSB 15 + #define DMA0_TXFR_LEN_XLENGTH_LSB 0 +#define DMA0_STRIDE HW_REGISTER_RO( 0x7e007018 ) + #define DMA0_STRIDE_MASK 0xffffffff + #define DMA0_STRIDE_WIDTH 32 + #define DMA0_STRIDE_D_STRIDE_BITS 31:16 + #define DMA0_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA0_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA0_STRIDE_D_STRIDE_MSB 31 + #define DMA0_STRIDE_D_STRIDE_LSB 16 + #define DMA0_STRIDE_S_STRIDE_BITS 15:0 + #define DMA0_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA0_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA0_STRIDE_S_STRIDE_MSB 15 + #define DMA0_STRIDE_S_STRIDE_LSB 0 +#define DMA0_NEXTCONBK HW_REGISTER_RO( 0x7e00701c ) + #define DMA0_NEXTCONBK_MASK 0xffffffe0 + #define DMA0_NEXTCONBK_WIDTH 32 + #define DMA0_NEXTCONBK_ADDR_BITS 31:5 + #define DMA0_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA0_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA0_NEXTCONBK_ADDR_MSB 31 + #define DMA0_NEXTCONBK_ADDR_LSB 5 +#define DMA0_DEBUG HW_REGISTER_RW( 0x7e007020 ) + #define DMA0_DEBUG_MASK 0x1ffffff7 + #define DMA0_DEBUG_WIDTH 29 + #define DMA0_DEBUG_RESET 0000000000 + #define DMA0_DEBUG_LITE_BITS 28:28 + #define DMA0_DEBUG_LITE_SET 0x10000000 + #define DMA0_DEBUG_LITE_CLR 0xefffffff + #define DMA0_DEBUG_LITE_MSB 28 + #define DMA0_DEBUG_LITE_LSB 28 + #define DMA0_DEBUG_VERSION_BITS 27:25 + #define DMA0_DEBUG_VERSION_SET 0x0e000000 + #define DMA0_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA0_DEBUG_VERSION_MSB 27 + #define DMA0_DEBUG_VERSION_LSB 25 + #define DMA0_DEBUG_DMA_STATE_BITS 24:16 + #define DMA0_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA0_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA0_DEBUG_DMA_STATE_MSB 24 + #define DMA0_DEBUG_DMA_STATE_LSB 16 + #define DMA0_DEBUG_DMA_ID_BITS 15:8 + #define DMA0_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA0_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA0_DEBUG_DMA_ID_MSB 15 + #define DMA0_DEBUG_DMA_ID_LSB 8 + #define DMA0_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA0_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA0_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA0_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA0_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA0_DEBUG_READ_ERROR_BITS 2:2 + #define DMA0_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA0_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA0_DEBUG_READ_ERROR_MSB 2 + #define DMA0_DEBUG_READ_ERROR_LSB 2 + #define DMA0_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA0_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA0_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA0_DEBUG_FIFO_ERROR_MSB 1 + #define DMA0_DEBUG_FIFO_ERROR_LSB 1 + #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma1.h b/bcm2708_chip/axi_dma1.h new file mode 100755 index 0000000..fa68999 --- /dev/null +++ b/bcm2708_chip/axi_dma1.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA1_BASE 0x7e007100 +#define DMA1_CS HW_REGISTER_RW( 0x7e007100 ) + #define DMA1_CS_MASK 0xf0ff017f + #define DMA1_CS_WIDTH 32 + #define DMA1_CS_RESET 0000000000 + #define DMA1_CS_RESET_BITS 31:31 + #define DMA1_CS_RESET_SET 0x80000000 + #define DMA1_CS_RESET_CLR 0x7fffffff + #define DMA1_CS_RESET_MSB 31 + #define DMA1_CS_RESET_LSB 31 + #define DMA1_CS_ABORT_BITS 30:30 + #define DMA1_CS_ABORT_SET 0x40000000 + #define DMA1_CS_ABORT_CLR 0xbfffffff + #define DMA1_CS_ABORT_MSB 30 + #define DMA1_CS_ABORT_LSB 30 + #define DMA1_CS_DISDEBUG_BITS 29:29 + #define DMA1_CS_DISDEBUG_SET 0x20000000 + #define DMA1_CS_DISDEBUG_CLR 0xdfffffff + #define DMA1_CS_DISDEBUG_MSB 29 + #define DMA1_CS_DISDEBUG_LSB 29 + #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA1_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA1_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA1_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA1_CS_PANIC_PRIORITY_MSB 23 + #define DMA1_CS_PANIC_PRIORITY_LSB 20 + #define DMA1_CS_PRIORITY_BITS 19:16 + #define DMA1_CS_PRIORITY_SET 0x000f0000 + #define DMA1_CS_PRIORITY_CLR 0xfff0ffff + #define DMA1_CS_PRIORITY_MSB 19 + #define DMA1_CS_PRIORITY_LSB 16 + #define DMA1_CS_ERROR_BITS 8:8 + #define DMA1_CS_ERROR_SET 0x00000100 + #define DMA1_CS_ERROR_CLR 0xfffffeff + #define DMA1_CS_ERROR_MSB 8 + #define DMA1_CS_ERROR_LSB 8 + #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA1_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA1_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA1_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA1_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA1_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA1_CS_PAUSED_BITS 4:4 + #define DMA1_CS_PAUSED_SET 0x00000010 + #define DMA1_CS_PAUSED_CLR 0xffffffef + #define DMA1_CS_PAUSED_MSB 4 + #define DMA1_CS_PAUSED_LSB 4 + #define DMA1_CS_DREQ_BITS 3:3 + #define DMA1_CS_DREQ_SET 0x00000008 + #define DMA1_CS_DREQ_CLR 0xfffffff7 + #define DMA1_CS_DREQ_MSB 3 + #define DMA1_CS_DREQ_LSB 3 + #define DMA1_CS_INT_BITS 2:2 + #define DMA1_CS_INT_SET 0x00000004 + #define DMA1_CS_INT_CLR 0xfffffffb + #define DMA1_CS_INT_MSB 2 + #define DMA1_CS_INT_LSB 2 + #define DMA1_CS_END_BITS 1:1 + #define DMA1_CS_END_SET 0x00000002 + #define DMA1_CS_END_CLR 0xfffffffd + #define DMA1_CS_END_MSB 1 + #define DMA1_CS_END_LSB 1 + #define DMA1_CS_ACTIVE_BITS 0:0 + #define DMA1_CS_ACTIVE_SET 0x00000001 + #define DMA1_CS_ACTIVE_CLR 0xfffffffe + #define DMA1_CS_ACTIVE_MSB 0 + #define DMA1_CS_ACTIVE_LSB 0 +#define DMA1_CONBLK_AD HW_REGISTER_RW( 0x7e007104 ) + #define DMA1_CONBLK_AD_MASK 0xffffffe0 + #define DMA1_CONBLK_AD_WIDTH 32 + #define DMA1_CONBLK_AD_RESET 0000000000 + #define DMA1_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA1_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA1_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA1_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA1_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA1_TI HW_REGISTER_RO( 0x7e007108 ) + #define DMA1_TI_MASK 0x07fffffb + #define DMA1_TI_WIDTH 27 + #define DMA1_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA1_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA1_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA1_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA1_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA1_TI_WAITS_BITS 25:21 + #define DMA1_TI_WAITS_SET 0x03e00000 + #define DMA1_TI_WAITS_CLR 0xfc1fffff + #define DMA1_TI_WAITS_MSB 25 + #define DMA1_TI_WAITS_LSB 21 + #define DMA1_TI_PERMAP_BITS 20:16 + #define DMA1_TI_PERMAP_SET 0x001f0000 + #define DMA1_TI_PERMAP_CLR 0xffe0ffff + #define DMA1_TI_PERMAP_MSB 20 + #define DMA1_TI_PERMAP_LSB 16 + #define DMA1_TI_BURST_LENGTH_BITS 15:12 + #define DMA1_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA1_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA1_TI_BURST_LENGTH_MSB 15 + #define DMA1_TI_BURST_LENGTH_LSB 12 + #define DMA1_TI_SRC_IGNORE_BITS 11:11 + #define DMA1_TI_SRC_IGNORE_SET 0x00000800 + #define DMA1_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA1_TI_SRC_IGNORE_MSB 11 + #define DMA1_TI_SRC_IGNORE_LSB 11 + #define DMA1_TI_SRC_DREQ_BITS 10:10 + #define DMA1_TI_SRC_DREQ_SET 0x00000400 + #define DMA1_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA1_TI_SRC_DREQ_MSB 10 + #define DMA1_TI_SRC_DREQ_LSB 10 + #define DMA1_TI_SRC_WIDTH_BITS 9:9 + #define DMA1_TI_SRC_WIDTH_SET 0x00000200 + #define DMA1_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA1_TI_SRC_WIDTH_MSB 9 + #define DMA1_TI_SRC_WIDTH_LSB 9 + #define DMA1_TI_SRC_INC_BITS 8:8 + #define DMA1_TI_SRC_INC_SET 0x00000100 + #define DMA1_TI_SRC_INC_CLR 0xfffffeff + #define DMA1_TI_SRC_INC_MSB 8 + #define DMA1_TI_SRC_INC_LSB 8 + #define DMA1_TI_DEST_IGNORE_BITS 7:7 + #define DMA1_TI_DEST_IGNORE_SET 0x00000080 + #define DMA1_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA1_TI_DEST_IGNORE_MSB 7 + #define DMA1_TI_DEST_IGNORE_LSB 7 + #define DMA1_TI_DEST_DREQ_BITS 6:6 + #define DMA1_TI_DEST_DREQ_SET 0x00000040 + #define DMA1_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA1_TI_DEST_DREQ_MSB 6 + #define DMA1_TI_DEST_DREQ_LSB 6 + #define DMA1_TI_DEST_WIDTH_BITS 5:5 + #define DMA1_TI_DEST_WIDTH_SET 0x00000020 + #define DMA1_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA1_TI_DEST_WIDTH_MSB 5 + #define DMA1_TI_DEST_WIDTH_LSB 5 + #define DMA1_TI_DEST_INC_BITS 4:4 + #define DMA1_TI_DEST_INC_SET 0x00000010 + #define DMA1_TI_DEST_INC_CLR 0xffffffef + #define DMA1_TI_DEST_INC_MSB 4 + #define DMA1_TI_DEST_INC_LSB 4 + #define DMA1_TI_WAIT_RESP_BITS 3:3 + #define DMA1_TI_WAIT_RESP_SET 0x00000008 + #define DMA1_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA1_TI_WAIT_RESP_MSB 3 + #define DMA1_TI_WAIT_RESP_LSB 3 + #define DMA1_TI_TDMODE_BITS 1:1 + #define DMA1_TI_TDMODE_SET 0x00000002 + #define DMA1_TI_TDMODE_CLR 0xfffffffd + #define DMA1_TI_TDMODE_MSB 1 + #define DMA1_TI_TDMODE_LSB 1 + #define DMA1_TI_INTEN_BITS 0:0 + #define DMA1_TI_INTEN_SET 0x00000001 + #define DMA1_TI_INTEN_CLR 0xfffffffe + #define DMA1_TI_INTEN_MSB 0 + #define DMA1_TI_INTEN_LSB 0 +#define DMA1_SOURCE_AD HW_REGISTER_RO( 0x7e00710c ) + #define DMA1_SOURCE_AD_MASK 0xffffffff + #define DMA1_SOURCE_AD_WIDTH 32 + #define DMA1_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA1_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA1_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA1_SOURCE_AD_S_ADDR_MSB 31 + #define DMA1_SOURCE_AD_S_ADDR_LSB 0 +#define DMA1_DEST_AD HW_REGISTER_RO( 0x7e007110 ) + #define DMA1_DEST_AD_MASK 0xffffffff + #define DMA1_DEST_AD_WIDTH 32 + #define DMA1_DEST_AD_D_ADDR_BITS 31:0 + #define DMA1_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA1_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA1_DEST_AD_D_ADDR_MSB 31 + #define DMA1_DEST_AD_D_ADDR_LSB 0 +#define DMA1_TXFR_LEN HW_REGISTER_RO( 0x7e007114 ) + #define DMA1_TXFR_LEN_MASK 0x3fffffff + #define DMA1_TXFR_LEN_WIDTH 30 + #define DMA1_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA1_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA1_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA1_TXFR_LEN_YLENGTH_MSB 29 + #define DMA1_TXFR_LEN_YLENGTH_LSB 16 + #define DMA1_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA1_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA1_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA1_TXFR_LEN_XLENGTH_MSB 15 + #define DMA1_TXFR_LEN_XLENGTH_LSB 0 +#define DMA1_STRIDE HW_REGISTER_RO( 0x7e007118 ) + #define DMA1_STRIDE_MASK 0xffffffff + #define DMA1_STRIDE_WIDTH 32 + #define DMA1_STRIDE_D_STRIDE_BITS 31:16 + #define DMA1_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA1_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA1_STRIDE_D_STRIDE_MSB 31 + #define DMA1_STRIDE_D_STRIDE_LSB 16 + #define DMA1_STRIDE_S_STRIDE_BITS 15:0 + #define DMA1_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA1_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA1_STRIDE_S_STRIDE_MSB 15 + #define DMA1_STRIDE_S_STRIDE_LSB 0 +#define DMA1_NEXTCONBK HW_REGISTER_RO( 0x7e00711c ) + #define DMA1_NEXTCONBK_MASK 0xffffffe0 + #define DMA1_NEXTCONBK_WIDTH 32 + #define DMA1_NEXTCONBK_ADDR_BITS 31:5 + #define DMA1_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA1_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA1_NEXTCONBK_ADDR_MSB 31 + #define DMA1_NEXTCONBK_ADDR_LSB 5 +#define DMA1_DEBUG HW_REGISTER_RW( 0x7e007120 ) + #define DMA1_DEBUG_MASK 0x1ffffff7 + #define DMA1_DEBUG_WIDTH 29 + #define DMA1_DEBUG_RESET 0000000000 + #define DMA1_DEBUG_LITE_BITS 28:28 + #define DMA1_DEBUG_LITE_SET 0x10000000 + #define DMA1_DEBUG_LITE_CLR 0xefffffff + #define DMA1_DEBUG_LITE_MSB 28 + #define DMA1_DEBUG_LITE_LSB 28 + #define DMA1_DEBUG_VERSION_BITS 27:25 + #define DMA1_DEBUG_VERSION_SET 0x0e000000 + #define DMA1_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA1_DEBUG_VERSION_MSB 27 + #define DMA1_DEBUG_VERSION_LSB 25 + #define DMA1_DEBUG_DMA_STATE_BITS 24:16 + #define DMA1_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA1_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA1_DEBUG_DMA_STATE_MSB 24 + #define DMA1_DEBUG_DMA_STATE_LSB 16 + #define DMA1_DEBUG_DMA_ID_BITS 15:8 + #define DMA1_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA1_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA1_DEBUG_DMA_ID_MSB 15 + #define DMA1_DEBUG_DMA_ID_LSB 8 + #define DMA1_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA1_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA1_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA1_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA1_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA1_DEBUG_READ_ERROR_BITS 2:2 + #define DMA1_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA1_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA1_DEBUG_READ_ERROR_MSB 2 + #define DMA1_DEBUG_READ_ERROR_LSB 2 + #define DMA1_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA1_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA1_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA1_DEBUG_FIFO_ERROR_MSB 1 + #define DMA1_DEBUG_FIFO_ERROR_LSB 1 + #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma15.h b/bcm2708_chip/axi_dma15.h new file mode 100755 index 0000000..170f80c --- /dev/null +++ b/bcm2708_chip/axi_dma15.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA15_BASE 0x7ee05000 +#define DMA15_CS HW_REGISTER_RW( 0x7ee05000 ) + #define DMA15_CS_MASK 0xf0ff017f + #define DMA15_CS_WIDTH 32 + #define DMA15_CS_RESET 0000000000 + #define DMA15_CS_RESET_BITS 31:31 + #define DMA15_CS_RESET_SET 0x80000000 + #define DMA15_CS_RESET_CLR 0x7fffffff + #define DMA15_CS_RESET_MSB 31 + #define DMA15_CS_RESET_LSB 31 + #define DMA15_CS_ABORT_BITS 30:30 + #define DMA15_CS_ABORT_SET 0x40000000 + #define DMA15_CS_ABORT_CLR 0xbfffffff + #define DMA15_CS_ABORT_MSB 30 + #define DMA15_CS_ABORT_LSB 30 + #define DMA15_CS_DISDEBUG_BITS 29:29 + #define DMA15_CS_DISDEBUG_SET 0x20000000 + #define DMA15_CS_DISDEBUG_CLR 0xdfffffff + #define DMA15_CS_DISDEBUG_MSB 29 + #define DMA15_CS_DISDEBUG_LSB 29 + #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA15_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA15_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA15_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA15_CS_PANIC_PRIORITY_MSB 23 + #define DMA15_CS_PANIC_PRIORITY_LSB 20 + #define DMA15_CS_PRIORITY_BITS 19:16 + #define DMA15_CS_PRIORITY_SET 0x000f0000 + #define DMA15_CS_PRIORITY_CLR 0xfff0ffff + #define DMA15_CS_PRIORITY_MSB 19 + #define DMA15_CS_PRIORITY_LSB 16 + #define DMA15_CS_ERROR_BITS 8:8 + #define DMA15_CS_ERROR_SET 0x00000100 + #define DMA15_CS_ERROR_CLR 0xfffffeff + #define DMA15_CS_ERROR_MSB 8 + #define DMA15_CS_ERROR_LSB 8 + #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA15_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA15_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA15_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA15_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA15_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA15_CS_PAUSED_BITS 4:4 + #define DMA15_CS_PAUSED_SET 0x00000010 + #define DMA15_CS_PAUSED_CLR 0xffffffef + #define DMA15_CS_PAUSED_MSB 4 + #define DMA15_CS_PAUSED_LSB 4 + #define DMA15_CS_DREQ_BITS 3:3 + #define DMA15_CS_DREQ_SET 0x00000008 + #define DMA15_CS_DREQ_CLR 0xfffffff7 + #define DMA15_CS_DREQ_MSB 3 + #define DMA15_CS_DREQ_LSB 3 + #define DMA15_CS_INT_BITS 2:2 + #define DMA15_CS_INT_SET 0x00000004 + #define DMA15_CS_INT_CLR 0xfffffffb + #define DMA15_CS_INT_MSB 2 + #define DMA15_CS_INT_LSB 2 + #define DMA15_CS_END_BITS 1:1 + #define DMA15_CS_END_SET 0x00000002 + #define DMA15_CS_END_CLR 0xfffffffd + #define DMA15_CS_END_MSB 1 + #define DMA15_CS_END_LSB 1 + #define DMA15_CS_ACTIVE_BITS 0:0 + #define DMA15_CS_ACTIVE_SET 0x00000001 + #define DMA15_CS_ACTIVE_CLR 0xfffffffe + #define DMA15_CS_ACTIVE_MSB 0 + #define DMA15_CS_ACTIVE_LSB 0 +#define DMA15_CONBLK_AD HW_REGISTER_RW( 0x7ee05004 ) + #define DMA15_CONBLK_AD_MASK 0xffffffe0 + #define DMA15_CONBLK_AD_WIDTH 32 + #define DMA15_CONBLK_AD_RESET 0000000000 + #define DMA15_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA15_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA15_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA15_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA15_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA15_TI HW_REGISTER_RO( 0x7ee05008 ) + #define DMA15_TI_MASK 0x07fffffb + #define DMA15_TI_WIDTH 27 + #define DMA15_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA15_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA15_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA15_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA15_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA15_TI_WAITS_BITS 25:21 + #define DMA15_TI_WAITS_SET 0x03e00000 + #define DMA15_TI_WAITS_CLR 0xfc1fffff + #define DMA15_TI_WAITS_MSB 25 + #define DMA15_TI_WAITS_LSB 21 + #define DMA15_TI_PERMAP_BITS 20:16 + #define DMA15_TI_PERMAP_SET 0x001f0000 + #define DMA15_TI_PERMAP_CLR 0xffe0ffff + #define DMA15_TI_PERMAP_MSB 20 + #define DMA15_TI_PERMAP_LSB 16 + #define DMA15_TI_BURST_LENGTH_BITS 15:12 + #define DMA15_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA15_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA15_TI_BURST_LENGTH_MSB 15 + #define DMA15_TI_BURST_LENGTH_LSB 12 + #define DMA15_TI_SRC_IGNORE_BITS 11:11 + #define DMA15_TI_SRC_IGNORE_SET 0x00000800 + #define DMA15_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA15_TI_SRC_IGNORE_MSB 11 + #define DMA15_TI_SRC_IGNORE_LSB 11 + #define DMA15_TI_SRC_DREQ_BITS 10:10 + #define DMA15_TI_SRC_DREQ_SET 0x00000400 + #define DMA15_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA15_TI_SRC_DREQ_MSB 10 + #define DMA15_TI_SRC_DREQ_LSB 10 + #define DMA15_TI_SRC_WIDTH_BITS 9:9 + #define DMA15_TI_SRC_WIDTH_SET 0x00000200 + #define DMA15_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA15_TI_SRC_WIDTH_MSB 9 + #define DMA15_TI_SRC_WIDTH_LSB 9 + #define DMA15_TI_SRC_INC_BITS 8:8 + #define DMA15_TI_SRC_INC_SET 0x00000100 + #define DMA15_TI_SRC_INC_CLR 0xfffffeff + #define DMA15_TI_SRC_INC_MSB 8 + #define DMA15_TI_SRC_INC_LSB 8 + #define DMA15_TI_DEST_IGNORE_BITS 7:7 + #define DMA15_TI_DEST_IGNORE_SET 0x00000080 + #define DMA15_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA15_TI_DEST_IGNORE_MSB 7 + #define DMA15_TI_DEST_IGNORE_LSB 7 + #define DMA15_TI_DEST_DREQ_BITS 6:6 + #define DMA15_TI_DEST_DREQ_SET 0x00000040 + #define DMA15_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA15_TI_DEST_DREQ_MSB 6 + #define DMA15_TI_DEST_DREQ_LSB 6 + #define DMA15_TI_DEST_WIDTH_BITS 5:5 + #define DMA15_TI_DEST_WIDTH_SET 0x00000020 + #define DMA15_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA15_TI_DEST_WIDTH_MSB 5 + #define DMA15_TI_DEST_WIDTH_LSB 5 + #define DMA15_TI_DEST_INC_BITS 4:4 + #define DMA15_TI_DEST_INC_SET 0x00000010 + #define DMA15_TI_DEST_INC_CLR 0xffffffef + #define DMA15_TI_DEST_INC_MSB 4 + #define DMA15_TI_DEST_INC_LSB 4 + #define DMA15_TI_WAIT_RESP_BITS 3:3 + #define DMA15_TI_WAIT_RESP_SET 0x00000008 + #define DMA15_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA15_TI_WAIT_RESP_MSB 3 + #define DMA15_TI_WAIT_RESP_LSB 3 + #define DMA15_TI_TDMODE_BITS 1:1 + #define DMA15_TI_TDMODE_SET 0x00000002 + #define DMA15_TI_TDMODE_CLR 0xfffffffd + #define DMA15_TI_TDMODE_MSB 1 + #define DMA15_TI_TDMODE_LSB 1 + #define DMA15_TI_INTEN_BITS 0:0 + #define DMA15_TI_INTEN_SET 0x00000001 + #define DMA15_TI_INTEN_CLR 0xfffffffe + #define DMA15_TI_INTEN_MSB 0 + #define DMA15_TI_INTEN_LSB 0 +#define DMA15_SOURCE_AD HW_REGISTER_RO( 0x7ee0500c ) + #define DMA15_SOURCE_AD_MASK 0xffffffff + #define DMA15_SOURCE_AD_WIDTH 32 + #define DMA15_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA15_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA15_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA15_SOURCE_AD_S_ADDR_MSB 31 + #define DMA15_SOURCE_AD_S_ADDR_LSB 0 +#define DMA15_DEST_AD HW_REGISTER_RO( 0x7ee05010 ) + #define DMA15_DEST_AD_MASK 0xffffffff + #define DMA15_DEST_AD_WIDTH 32 + #define DMA15_DEST_AD_D_ADDR_BITS 31:0 + #define DMA15_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA15_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA15_DEST_AD_D_ADDR_MSB 31 + #define DMA15_DEST_AD_D_ADDR_LSB 0 +#define DMA15_TXFR_LEN HW_REGISTER_RO( 0x7ee05014 ) + #define DMA15_TXFR_LEN_MASK 0x3fffffff + #define DMA15_TXFR_LEN_WIDTH 30 + #define DMA15_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA15_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA15_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA15_TXFR_LEN_YLENGTH_MSB 29 + #define DMA15_TXFR_LEN_YLENGTH_LSB 16 + #define DMA15_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA15_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA15_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA15_TXFR_LEN_XLENGTH_MSB 15 + #define DMA15_TXFR_LEN_XLENGTH_LSB 0 +#define DMA15_STRIDE HW_REGISTER_RO( 0x7ee05018 ) + #define DMA15_STRIDE_MASK 0xffffffff + #define DMA15_STRIDE_WIDTH 32 + #define DMA15_STRIDE_D_STRIDE_BITS 31:16 + #define DMA15_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA15_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA15_STRIDE_D_STRIDE_MSB 31 + #define DMA15_STRIDE_D_STRIDE_LSB 16 + #define DMA15_STRIDE_S_STRIDE_BITS 15:0 + #define DMA15_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA15_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA15_STRIDE_S_STRIDE_MSB 15 + #define DMA15_STRIDE_S_STRIDE_LSB 0 +#define DMA15_NEXTCONBK HW_REGISTER_RO( 0x7ee0501c ) + #define DMA15_NEXTCONBK_MASK 0xffffffe0 + #define DMA15_NEXTCONBK_WIDTH 32 + #define DMA15_NEXTCONBK_ADDR_BITS 31:5 + #define DMA15_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA15_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA15_NEXTCONBK_ADDR_MSB 31 + #define DMA15_NEXTCONBK_ADDR_LSB 5 +#define DMA15_DEBUG HW_REGISTER_RW( 0x7ee05020 ) + #define DMA15_DEBUG_MASK 0x1ffffff7 + #define DMA15_DEBUG_WIDTH 29 + #define DMA15_DEBUG_RESET 0000000000 + #define DMA15_DEBUG_LITE_BITS 28:28 + #define DMA15_DEBUG_LITE_SET 0x10000000 + #define DMA15_DEBUG_LITE_CLR 0xefffffff + #define DMA15_DEBUG_LITE_MSB 28 + #define DMA15_DEBUG_LITE_LSB 28 + #define DMA15_DEBUG_VERSION_BITS 27:25 + #define DMA15_DEBUG_VERSION_SET 0x0e000000 + #define DMA15_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA15_DEBUG_VERSION_MSB 27 + #define DMA15_DEBUG_VERSION_LSB 25 + #define DMA15_DEBUG_DMA_STATE_BITS 24:16 + #define DMA15_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA15_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA15_DEBUG_DMA_STATE_MSB 24 + #define DMA15_DEBUG_DMA_STATE_LSB 16 + #define DMA15_DEBUG_DMA_ID_BITS 15:8 + #define DMA15_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA15_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA15_DEBUG_DMA_ID_MSB 15 + #define DMA15_DEBUG_DMA_ID_LSB 8 + #define DMA15_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA15_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA15_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA15_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA15_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA15_DEBUG_READ_ERROR_BITS 2:2 + #define DMA15_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA15_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA15_DEBUG_READ_ERROR_MSB 2 + #define DMA15_DEBUG_READ_ERROR_LSB 2 + #define DMA15_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA15_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA15_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA15_DEBUG_FIFO_ERROR_MSB 1 + #define DMA15_DEBUG_FIFO_ERROR_LSB 1 + #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma2.h b/bcm2708_chip/axi_dma2.h new file mode 100755 index 0000000..81b4ed9 --- /dev/null +++ b/bcm2708_chip/axi_dma2.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA2_BASE 0x7e007200 +#define DMA2_CS HW_REGISTER_RW( 0x7e007200 ) + #define DMA2_CS_MASK 0xf0ff017f + #define DMA2_CS_WIDTH 32 + #define DMA2_CS_RESET 0000000000 + #define DMA2_CS_RESET_BITS 31:31 + #define DMA2_CS_RESET_SET 0x80000000 + #define DMA2_CS_RESET_CLR 0x7fffffff + #define DMA2_CS_RESET_MSB 31 + #define DMA2_CS_RESET_LSB 31 + #define DMA2_CS_ABORT_BITS 30:30 + #define DMA2_CS_ABORT_SET 0x40000000 + #define DMA2_CS_ABORT_CLR 0xbfffffff + #define DMA2_CS_ABORT_MSB 30 + #define DMA2_CS_ABORT_LSB 30 + #define DMA2_CS_DISDEBUG_BITS 29:29 + #define DMA2_CS_DISDEBUG_SET 0x20000000 + #define DMA2_CS_DISDEBUG_CLR 0xdfffffff + #define DMA2_CS_DISDEBUG_MSB 29 + #define DMA2_CS_DISDEBUG_LSB 29 + #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA2_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA2_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA2_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA2_CS_PANIC_PRIORITY_MSB 23 + #define DMA2_CS_PANIC_PRIORITY_LSB 20 + #define DMA2_CS_PRIORITY_BITS 19:16 + #define DMA2_CS_PRIORITY_SET 0x000f0000 + #define DMA2_CS_PRIORITY_CLR 0xfff0ffff + #define DMA2_CS_PRIORITY_MSB 19 + #define DMA2_CS_PRIORITY_LSB 16 + #define DMA2_CS_ERROR_BITS 8:8 + #define DMA2_CS_ERROR_SET 0x00000100 + #define DMA2_CS_ERROR_CLR 0xfffffeff + #define DMA2_CS_ERROR_MSB 8 + #define DMA2_CS_ERROR_LSB 8 + #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA2_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA2_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA2_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA2_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA2_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA2_CS_PAUSED_BITS 4:4 + #define DMA2_CS_PAUSED_SET 0x00000010 + #define DMA2_CS_PAUSED_CLR 0xffffffef + #define DMA2_CS_PAUSED_MSB 4 + #define DMA2_CS_PAUSED_LSB 4 + #define DMA2_CS_DREQ_BITS 3:3 + #define DMA2_CS_DREQ_SET 0x00000008 + #define DMA2_CS_DREQ_CLR 0xfffffff7 + #define DMA2_CS_DREQ_MSB 3 + #define DMA2_CS_DREQ_LSB 3 + #define DMA2_CS_INT_BITS 2:2 + #define DMA2_CS_INT_SET 0x00000004 + #define DMA2_CS_INT_CLR 0xfffffffb + #define DMA2_CS_INT_MSB 2 + #define DMA2_CS_INT_LSB 2 + #define DMA2_CS_END_BITS 1:1 + #define DMA2_CS_END_SET 0x00000002 + #define DMA2_CS_END_CLR 0xfffffffd + #define DMA2_CS_END_MSB 1 + #define DMA2_CS_END_LSB 1 + #define DMA2_CS_ACTIVE_BITS 0:0 + #define DMA2_CS_ACTIVE_SET 0x00000001 + #define DMA2_CS_ACTIVE_CLR 0xfffffffe + #define DMA2_CS_ACTIVE_MSB 0 + #define DMA2_CS_ACTIVE_LSB 0 +#define DMA2_CONBLK_AD HW_REGISTER_RW( 0x7e007204 ) + #define DMA2_CONBLK_AD_MASK 0xffffffe0 + #define DMA2_CONBLK_AD_WIDTH 32 + #define DMA2_CONBLK_AD_RESET 0000000000 + #define DMA2_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA2_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA2_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA2_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA2_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA2_TI HW_REGISTER_RO( 0x7e007208 ) + #define DMA2_TI_MASK 0x07fffffb + #define DMA2_TI_WIDTH 27 + #define DMA2_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA2_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA2_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA2_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA2_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA2_TI_WAITS_BITS 25:21 + #define DMA2_TI_WAITS_SET 0x03e00000 + #define DMA2_TI_WAITS_CLR 0xfc1fffff + #define DMA2_TI_WAITS_MSB 25 + #define DMA2_TI_WAITS_LSB 21 + #define DMA2_TI_PERMAP_BITS 20:16 + #define DMA2_TI_PERMAP_SET 0x001f0000 + #define DMA2_TI_PERMAP_CLR 0xffe0ffff + #define DMA2_TI_PERMAP_MSB 20 + #define DMA2_TI_PERMAP_LSB 16 + #define DMA2_TI_BURST_LENGTH_BITS 15:12 + #define DMA2_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA2_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA2_TI_BURST_LENGTH_MSB 15 + #define DMA2_TI_BURST_LENGTH_LSB 12 + #define DMA2_TI_SRC_IGNORE_BITS 11:11 + #define DMA2_TI_SRC_IGNORE_SET 0x00000800 + #define DMA2_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA2_TI_SRC_IGNORE_MSB 11 + #define DMA2_TI_SRC_IGNORE_LSB 11 + #define DMA2_TI_SRC_DREQ_BITS 10:10 + #define DMA2_TI_SRC_DREQ_SET 0x00000400 + #define DMA2_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA2_TI_SRC_DREQ_MSB 10 + #define DMA2_TI_SRC_DREQ_LSB 10 + #define DMA2_TI_SRC_WIDTH_BITS 9:9 + #define DMA2_TI_SRC_WIDTH_SET 0x00000200 + #define DMA2_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA2_TI_SRC_WIDTH_MSB 9 + #define DMA2_TI_SRC_WIDTH_LSB 9 + #define DMA2_TI_SRC_INC_BITS 8:8 + #define DMA2_TI_SRC_INC_SET 0x00000100 + #define DMA2_TI_SRC_INC_CLR 0xfffffeff + #define DMA2_TI_SRC_INC_MSB 8 + #define DMA2_TI_SRC_INC_LSB 8 + #define DMA2_TI_DEST_IGNORE_BITS 7:7 + #define DMA2_TI_DEST_IGNORE_SET 0x00000080 + #define DMA2_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA2_TI_DEST_IGNORE_MSB 7 + #define DMA2_TI_DEST_IGNORE_LSB 7 + #define DMA2_TI_DEST_DREQ_BITS 6:6 + #define DMA2_TI_DEST_DREQ_SET 0x00000040 + #define DMA2_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA2_TI_DEST_DREQ_MSB 6 + #define DMA2_TI_DEST_DREQ_LSB 6 + #define DMA2_TI_DEST_WIDTH_BITS 5:5 + #define DMA2_TI_DEST_WIDTH_SET 0x00000020 + #define DMA2_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA2_TI_DEST_WIDTH_MSB 5 + #define DMA2_TI_DEST_WIDTH_LSB 5 + #define DMA2_TI_DEST_INC_BITS 4:4 + #define DMA2_TI_DEST_INC_SET 0x00000010 + #define DMA2_TI_DEST_INC_CLR 0xffffffef + #define DMA2_TI_DEST_INC_MSB 4 + #define DMA2_TI_DEST_INC_LSB 4 + #define DMA2_TI_WAIT_RESP_BITS 3:3 + #define DMA2_TI_WAIT_RESP_SET 0x00000008 + #define DMA2_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA2_TI_WAIT_RESP_MSB 3 + #define DMA2_TI_WAIT_RESP_LSB 3 + #define DMA2_TI_TDMODE_BITS 1:1 + #define DMA2_TI_TDMODE_SET 0x00000002 + #define DMA2_TI_TDMODE_CLR 0xfffffffd + #define DMA2_TI_TDMODE_MSB 1 + #define DMA2_TI_TDMODE_LSB 1 + #define DMA2_TI_INTEN_BITS 0:0 + #define DMA2_TI_INTEN_SET 0x00000001 + #define DMA2_TI_INTEN_CLR 0xfffffffe + #define DMA2_TI_INTEN_MSB 0 + #define DMA2_TI_INTEN_LSB 0 +#define DMA2_SOURCE_AD HW_REGISTER_RO( 0x7e00720c ) + #define DMA2_SOURCE_AD_MASK 0xffffffff + #define DMA2_SOURCE_AD_WIDTH 32 + #define DMA2_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA2_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA2_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA2_SOURCE_AD_S_ADDR_MSB 31 + #define DMA2_SOURCE_AD_S_ADDR_LSB 0 +#define DMA2_DEST_AD HW_REGISTER_RO( 0x7e007210 ) + #define DMA2_DEST_AD_MASK 0xffffffff + #define DMA2_DEST_AD_WIDTH 32 + #define DMA2_DEST_AD_D_ADDR_BITS 31:0 + #define DMA2_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA2_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA2_DEST_AD_D_ADDR_MSB 31 + #define DMA2_DEST_AD_D_ADDR_LSB 0 +#define DMA2_TXFR_LEN HW_REGISTER_RO( 0x7e007214 ) + #define DMA2_TXFR_LEN_MASK 0x3fffffff + #define DMA2_TXFR_LEN_WIDTH 30 + #define DMA2_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA2_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA2_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA2_TXFR_LEN_YLENGTH_MSB 29 + #define DMA2_TXFR_LEN_YLENGTH_LSB 16 + #define DMA2_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA2_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA2_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA2_TXFR_LEN_XLENGTH_MSB 15 + #define DMA2_TXFR_LEN_XLENGTH_LSB 0 +#define DMA2_STRIDE HW_REGISTER_RO( 0x7e007218 ) + #define DMA2_STRIDE_MASK 0xffffffff + #define DMA2_STRIDE_WIDTH 32 + #define DMA2_STRIDE_D_STRIDE_BITS 31:16 + #define DMA2_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA2_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA2_STRIDE_D_STRIDE_MSB 31 + #define DMA2_STRIDE_D_STRIDE_LSB 16 + #define DMA2_STRIDE_S_STRIDE_BITS 15:0 + #define DMA2_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA2_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA2_STRIDE_S_STRIDE_MSB 15 + #define DMA2_STRIDE_S_STRIDE_LSB 0 +#define DMA2_NEXTCONBK HW_REGISTER_RO( 0x7e00721c ) + #define DMA2_NEXTCONBK_MASK 0xffffffe0 + #define DMA2_NEXTCONBK_WIDTH 32 + #define DMA2_NEXTCONBK_ADDR_BITS 31:5 + #define DMA2_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA2_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA2_NEXTCONBK_ADDR_MSB 31 + #define DMA2_NEXTCONBK_ADDR_LSB 5 +#define DMA2_DEBUG HW_REGISTER_RW( 0x7e007220 ) + #define DMA2_DEBUG_MASK 0x1ffffff7 + #define DMA2_DEBUG_WIDTH 29 + #define DMA2_DEBUG_RESET 0000000000 + #define DMA2_DEBUG_LITE_BITS 28:28 + #define DMA2_DEBUG_LITE_SET 0x10000000 + #define DMA2_DEBUG_LITE_CLR 0xefffffff + #define DMA2_DEBUG_LITE_MSB 28 + #define DMA2_DEBUG_LITE_LSB 28 + #define DMA2_DEBUG_VERSION_BITS 27:25 + #define DMA2_DEBUG_VERSION_SET 0x0e000000 + #define DMA2_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA2_DEBUG_VERSION_MSB 27 + #define DMA2_DEBUG_VERSION_LSB 25 + #define DMA2_DEBUG_DMA_STATE_BITS 24:16 + #define DMA2_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA2_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA2_DEBUG_DMA_STATE_MSB 24 + #define DMA2_DEBUG_DMA_STATE_LSB 16 + #define DMA2_DEBUG_DMA_ID_BITS 15:8 + #define DMA2_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA2_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA2_DEBUG_DMA_ID_MSB 15 + #define DMA2_DEBUG_DMA_ID_LSB 8 + #define DMA2_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA2_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA2_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA2_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA2_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA2_DEBUG_READ_ERROR_BITS 2:2 + #define DMA2_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA2_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA2_DEBUG_READ_ERROR_MSB 2 + #define DMA2_DEBUG_READ_ERROR_LSB 2 + #define DMA2_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA2_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA2_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA2_DEBUG_FIFO_ERROR_MSB 1 + #define DMA2_DEBUG_FIFO_ERROR_LSB 1 + #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma3.h b/bcm2708_chip/axi_dma3.h new file mode 100755 index 0000000..a2208c0 --- /dev/null +++ b/bcm2708_chip/axi_dma3.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA3_BASE 0x7e007300 +#define DMA3_CS HW_REGISTER_RW( 0x7e007300 ) + #define DMA3_CS_MASK 0xf0ff017f + #define DMA3_CS_WIDTH 32 + #define DMA3_CS_RESET 0000000000 + #define DMA3_CS_RESET_BITS 31:31 + #define DMA3_CS_RESET_SET 0x80000000 + #define DMA3_CS_RESET_CLR 0x7fffffff + #define DMA3_CS_RESET_MSB 31 + #define DMA3_CS_RESET_LSB 31 + #define DMA3_CS_ABORT_BITS 30:30 + #define DMA3_CS_ABORT_SET 0x40000000 + #define DMA3_CS_ABORT_CLR 0xbfffffff + #define DMA3_CS_ABORT_MSB 30 + #define DMA3_CS_ABORT_LSB 30 + #define DMA3_CS_DISDEBUG_BITS 29:29 + #define DMA3_CS_DISDEBUG_SET 0x20000000 + #define DMA3_CS_DISDEBUG_CLR 0xdfffffff + #define DMA3_CS_DISDEBUG_MSB 29 + #define DMA3_CS_DISDEBUG_LSB 29 + #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA3_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA3_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA3_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA3_CS_PANIC_PRIORITY_MSB 23 + #define DMA3_CS_PANIC_PRIORITY_LSB 20 + #define DMA3_CS_PRIORITY_BITS 19:16 + #define DMA3_CS_PRIORITY_SET 0x000f0000 + #define DMA3_CS_PRIORITY_CLR 0xfff0ffff + #define DMA3_CS_PRIORITY_MSB 19 + #define DMA3_CS_PRIORITY_LSB 16 + #define DMA3_CS_ERROR_BITS 8:8 + #define DMA3_CS_ERROR_SET 0x00000100 + #define DMA3_CS_ERROR_CLR 0xfffffeff + #define DMA3_CS_ERROR_MSB 8 + #define DMA3_CS_ERROR_LSB 8 + #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA3_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA3_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA3_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA3_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA3_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA3_CS_PAUSED_BITS 4:4 + #define DMA3_CS_PAUSED_SET 0x00000010 + #define DMA3_CS_PAUSED_CLR 0xffffffef + #define DMA3_CS_PAUSED_MSB 4 + #define DMA3_CS_PAUSED_LSB 4 + #define DMA3_CS_DREQ_BITS 3:3 + #define DMA3_CS_DREQ_SET 0x00000008 + #define DMA3_CS_DREQ_CLR 0xfffffff7 + #define DMA3_CS_DREQ_MSB 3 + #define DMA3_CS_DREQ_LSB 3 + #define DMA3_CS_INT_BITS 2:2 + #define DMA3_CS_INT_SET 0x00000004 + #define DMA3_CS_INT_CLR 0xfffffffb + #define DMA3_CS_INT_MSB 2 + #define DMA3_CS_INT_LSB 2 + #define DMA3_CS_END_BITS 1:1 + #define DMA3_CS_END_SET 0x00000002 + #define DMA3_CS_END_CLR 0xfffffffd + #define DMA3_CS_END_MSB 1 + #define DMA3_CS_END_LSB 1 + #define DMA3_CS_ACTIVE_BITS 0:0 + #define DMA3_CS_ACTIVE_SET 0x00000001 + #define DMA3_CS_ACTIVE_CLR 0xfffffffe + #define DMA3_CS_ACTIVE_MSB 0 + #define DMA3_CS_ACTIVE_LSB 0 +#define DMA3_CONBLK_AD HW_REGISTER_RW( 0x7e007304 ) + #define DMA3_CONBLK_AD_MASK 0xffffffe0 + #define DMA3_CONBLK_AD_WIDTH 32 + #define DMA3_CONBLK_AD_RESET 0000000000 + #define DMA3_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA3_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA3_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA3_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA3_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA3_TI HW_REGISTER_RO( 0x7e007308 ) + #define DMA3_TI_MASK 0x07fffffb + #define DMA3_TI_WIDTH 27 + #define DMA3_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA3_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA3_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA3_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA3_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA3_TI_WAITS_BITS 25:21 + #define DMA3_TI_WAITS_SET 0x03e00000 + #define DMA3_TI_WAITS_CLR 0xfc1fffff + #define DMA3_TI_WAITS_MSB 25 + #define DMA3_TI_WAITS_LSB 21 + #define DMA3_TI_PERMAP_BITS 20:16 + #define DMA3_TI_PERMAP_SET 0x001f0000 + #define DMA3_TI_PERMAP_CLR 0xffe0ffff + #define DMA3_TI_PERMAP_MSB 20 + #define DMA3_TI_PERMAP_LSB 16 + #define DMA3_TI_BURST_LENGTH_BITS 15:12 + #define DMA3_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA3_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA3_TI_BURST_LENGTH_MSB 15 + #define DMA3_TI_BURST_LENGTH_LSB 12 + #define DMA3_TI_SRC_IGNORE_BITS 11:11 + #define DMA3_TI_SRC_IGNORE_SET 0x00000800 + #define DMA3_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA3_TI_SRC_IGNORE_MSB 11 + #define DMA3_TI_SRC_IGNORE_LSB 11 + #define DMA3_TI_SRC_DREQ_BITS 10:10 + #define DMA3_TI_SRC_DREQ_SET 0x00000400 + #define DMA3_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA3_TI_SRC_DREQ_MSB 10 + #define DMA3_TI_SRC_DREQ_LSB 10 + #define DMA3_TI_SRC_WIDTH_BITS 9:9 + #define DMA3_TI_SRC_WIDTH_SET 0x00000200 + #define DMA3_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA3_TI_SRC_WIDTH_MSB 9 + #define DMA3_TI_SRC_WIDTH_LSB 9 + #define DMA3_TI_SRC_INC_BITS 8:8 + #define DMA3_TI_SRC_INC_SET 0x00000100 + #define DMA3_TI_SRC_INC_CLR 0xfffffeff + #define DMA3_TI_SRC_INC_MSB 8 + #define DMA3_TI_SRC_INC_LSB 8 + #define DMA3_TI_DEST_IGNORE_BITS 7:7 + #define DMA3_TI_DEST_IGNORE_SET 0x00000080 + #define DMA3_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA3_TI_DEST_IGNORE_MSB 7 + #define DMA3_TI_DEST_IGNORE_LSB 7 + #define DMA3_TI_DEST_DREQ_BITS 6:6 + #define DMA3_TI_DEST_DREQ_SET 0x00000040 + #define DMA3_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA3_TI_DEST_DREQ_MSB 6 + #define DMA3_TI_DEST_DREQ_LSB 6 + #define DMA3_TI_DEST_WIDTH_BITS 5:5 + #define DMA3_TI_DEST_WIDTH_SET 0x00000020 + #define DMA3_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA3_TI_DEST_WIDTH_MSB 5 + #define DMA3_TI_DEST_WIDTH_LSB 5 + #define DMA3_TI_DEST_INC_BITS 4:4 + #define DMA3_TI_DEST_INC_SET 0x00000010 + #define DMA3_TI_DEST_INC_CLR 0xffffffef + #define DMA3_TI_DEST_INC_MSB 4 + #define DMA3_TI_DEST_INC_LSB 4 + #define DMA3_TI_WAIT_RESP_BITS 3:3 + #define DMA3_TI_WAIT_RESP_SET 0x00000008 + #define DMA3_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA3_TI_WAIT_RESP_MSB 3 + #define DMA3_TI_WAIT_RESP_LSB 3 + #define DMA3_TI_TDMODE_BITS 1:1 + #define DMA3_TI_TDMODE_SET 0x00000002 + #define DMA3_TI_TDMODE_CLR 0xfffffffd + #define DMA3_TI_TDMODE_MSB 1 + #define DMA3_TI_TDMODE_LSB 1 + #define DMA3_TI_INTEN_BITS 0:0 + #define DMA3_TI_INTEN_SET 0x00000001 + #define DMA3_TI_INTEN_CLR 0xfffffffe + #define DMA3_TI_INTEN_MSB 0 + #define DMA3_TI_INTEN_LSB 0 +#define DMA3_SOURCE_AD HW_REGISTER_RO( 0x7e00730c ) + #define DMA3_SOURCE_AD_MASK 0xffffffff + #define DMA3_SOURCE_AD_WIDTH 32 + #define DMA3_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA3_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA3_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA3_SOURCE_AD_S_ADDR_MSB 31 + #define DMA3_SOURCE_AD_S_ADDR_LSB 0 +#define DMA3_DEST_AD HW_REGISTER_RO( 0x7e007310 ) + #define DMA3_DEST_AD_MASK 0xffffffff + #define DMA3_DEST_AD_WIDTH 32 + #define DMA3_DEST_AD_D_ADDR_BITS 31:0 + #define DMA3_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA3_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA3_DEST_AD_D_ADDR_MSB 31 + #define DMA3_DEST_AD_D_ADDR_LSB 0 +#define DMA3_TXFR_LEN HW_REGISTER_RO( 0x7e007314 ) + #define DMA3_TXFR_LEN_MASK 0x3fffffff + #define DMA3_TXFR_LEN_WIDTH 30 + #define DMA3_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA3_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA3_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA3_TXFR_LEN_YLENGTH_MSB 29 + #define DMA3_TXFR_LEN_YLENGTH_LSB 16 + #define DMA3_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA3_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA3_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA3_TXFR_LEN_XLENGTH_MSB 15 + #define DMA3_TXFR_LEN_XLENGTH_LSB 0 +#define DMA3_STRIDE HW_REGISTER_RO( 0x7e007318 ) + #define DMA3_STRIDE_MASK 0xffffffff + #define DMA3_STRIDE_WIDTH 32 + #define DMA3_STRIDE_D_STRIDE_BITS 31:16 + #define DMA3_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA3_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA3_STRIDE_D_STRIDE_MSB 31 + #define DMA3_STRIDE_D_STRIDE_LSB 16 + #define DMA3_STRIDE_S_STRIDE_BITS 15:0 + #define DMA3_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA3_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA3_STRIDE_S_STRIDE_MSB 15 + #define DMA3_STRIDE_S_STRIDE_LSB 0 +#define DMA3_NEXTCONBK HW_REGISTER_RO( 0x7e00731c ) + #define DMA3_NEXTCONBK_MASK 0xffffffe0 + #define DMA3_NEXTCONBK_WIDTH 32 + #define DMA3_NEXTCONBK_ADDR_BITS 31:5 + #define DMA3_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA3_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA3_NEXTCONBK_ADDR_MSB 31 + #define DMA3_NEXTCONBK_ADDR_LSB 5 +#define DMA3_DEBUG HW_REGISTER_RW( 0x7e007320 ) + #define DMA3_DEBUG_MASK 0x1ffffff7 + #define DMA3_DEBUG_WIDTH 29 + #define DMA3_DEBUG_RESET 0000000000 + #define DMA3_DEBUG_LITE_BITS 28:28 + #define DMA3_DEBUG_LITE_SET 0x10000000 + #define DMA3_DEBUG_LITE_CLR 0xefffffff + #define DMA3_DEBUG_LITE_MSB 28 + #define DMA3_DEBUG_LITE_LSB 28 + #define DMA3_DEBUG_VERSION_BITS 27:25 + #define DMA3_DEBUG_VERSION_SET 0x0e000000 + #define DMA3_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA3_DEBUG_VERSION_MSB 27 + #define DMA3_DEBUG_VERSION_LSB 25 + #define DMA3_DEBUG_DMA_STATE_BITS 24:16 + #define DMA3_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA3_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA3_DEBUG_DMA_STATE_MSB 24 + #define DMA3_DEBUG_DMA_STATE_LSB 16 + #define DMA3_DEBUG_DMA_ID_BITS 15:8 + #define DMA3_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA3_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA3_DEBUG_DMA_ID_MSB 15 + #define DMA3_DEBUG_DMA_ID_LSB 8 + #define DMA3_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA3_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA3_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA3_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA3_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA3_DEBUG_READ_ERROR_BITS 2:2 + #define DMA3_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA3_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA3_DEBUG_READ_ERROR_MSB 2 + #define DMA3_DEBUG_READ_ERROR_LSB 2 + #define DMA3_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA3_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA3_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA3_DEBUG_FIFO_ERROR_MSB 1 + #define DMA3_DEBUG_FIFO_ERROR_LSB 1 + #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma4.h b/bcm2708_chip/axi_dma4.h new file mode 100755 index 0000000..1cefda5 --- /dev/null +++ b/bcm2708_chip/axi_dma4.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA4_BASE 0x7e007400 +#define DMA4_CS HW_REGISTER_RW( 0x7e007400 ) + #define DMA4_CS_MASK 0xf0ff017f + #define DMA4_CS_WIDTH 32 + #define DMA4_CS_RESET 0000000000 + #define DMA4_CS_RESET_BITS 31:31 + #define DMA4_CS_RESET_SET 0x80000000 + #define DMA4_CS_RESET_CLR 0x7fffffff + #define DMA4_CS_RESET_MSB 31 + #define DMA4_CS_RESET_LSB 31 + #define DMA4_CS_ABORT_BITS 30:30 + #define DMA4_CS_ABORT_SET 0x40000000 + #define DMA4_CS_ABORT_CLR 0xbfffffff + #define DMA4_CS_ABORT_MSB 30 + #define DMA4_CS_ABORT_LSB 30 + #define DMA4_CS_DISDEBUG_BITS 29:29 + #define DMA4_CS_DISDEBUG_SET 0x20000000 + #define DMA4_CS_DISDEBUG_CLR 0xdfffffff + #define DMA4_CS_DISDEBUG_MSB 29 + #define DMA4_CS_DISDEBUG_LSB 29 + #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA4_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA4_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA4_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA4_CS_PANIC_PRIORITY_MSB 23 + #define DMA4_CS_PANIC_PRIORITY_LSB 20 + #define DMA4_CS_PRIORITY_BITS 19:16 + #define DMA4_CS_PRIORITY_SET 0x000f0000 + #define DMA4_CS_PRIORITY_CLR 0xfff0ffff + #define DMA4_CS_PRIORITY_MSB 19 + #define DMA4_CS_PRIORITY_LSB 16 + #define DMA4_CS_ERROR_BITS 8:8 + #define DMA4_CS_ERROR_SET 0x00000100 + #define DMA4_CS_ERROR_CLR 0xfffffeff + #define DMA4_CS_ERROR_MSB 8 + #define DMA4_CS_ERROR_LSB 8 + #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA4_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA4_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA4_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA4_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA4_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA4_CS_PAUSED_BITS 4:4 + #define DMA4_CS_PAUSED_SET 0x00000010 + #define DMA4_CS_PAUSED_CLR 0xffffffef + #define DMA4_CS_PAUSED_MSB 4 + #define DMA4_CS_PAUSED_LSB 4 + #define DMA4_CS_DREQ_BITS 3:3 + #define DMA4_CS_DREQ_SET 0x00000008 + #define DMA4_CS_DREQ_CLR 0xfffffff7 + #define DMA4_CS_DREQ_MSB 3 + #define DMA4_CS_DREQ_LSB 3 + #define DMA4_CS_INT_BITS 2:2 + #define DMA4_CS_INT_SET 0x00000004 + #define DMA4_CS_INT_CLR 0xfffffffb + #define DMA4_CS_INT_MSB 2 + #define DMA4_CS_INT_LSB 2 + #define DMA4_CS_END_BITS 1:1 + #define DMA4_CS_END_SET 0x00000002 + #define DMA4_CS_END_CLR 0xfffffffd + #define DMA4_CS_END_MSB 1 + #define DMA4_CS_END_LSB 1 + #define DMA4_CS_ACTIVE_BITS 0:0 + #define DMA4_CS_ACTIVE_SET 0x00000001 + #define DMA4_CS_ACTIVE_CLR 0xfffffffe + #define DMA4_CS_ACTIVE_MSB 0 + #define DMA4_CS_ACTIVE_LSB 0 +#define DMA4_CONBLK_AD HW_REGISTER_RW( 0x7e007404 ) + #define DMA4_CONBLK_AD_MASK 0xffffffe0 + #define DMA4_CONBLK_AD_WIDTH 32 + #define DMA4_CONBLK_AD_RESET 0000000000 + #define DMA4_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA4_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA4_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA4_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA4_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA4_TI HW_REGISTER_RO( 0x7e007408 ) + #define DMA4_TI_MASK 0x07fffffb + #define DMA4_TI_WIDTH 27 + #define DMA4_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA4_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA4_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA4_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA4_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA4_TI_WAITS_BITS 25:21 + #define DMA4_TI_WAITS_SET 0x03e00000 + #define DMA4_TI_WAITS_CLR 0xfc1fffff + #define DMA4_TI_WAITS_MSB 25 + #define DMA4_TI_WAITS_LSB 21 + #define DMA4_TI_PERMAP_BITS 20:16 + #define DMA4_TI_PERMAP_SET 0x001f0000 + #define DMA4_TI_PERMAP_CLR 0xffe0ffff + #define DMA4_TI_PERMAP_MSB 20 + #define DMA4_TI_PERMAP_LSB 16 + #define DMA4_TI_BURST_LENGTH_BITS 15:12 + #define DMA4_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA4_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA4_TI_BURST_LENGTH_MSB 15 + #define DMA4_TI_BURST_LENGTH_LSB 12 + #define DMA4_TI_SRC_IGNORE_BITS 11:11 + #define DMA4_TI_SRC_IGNORE_SET 0x00000800 + #define DMA4_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA4_TI_SRC_IGNORE_MSB 11 + #define DMA4_TI_SRC_IGNORE_LSB 11 + #define DMA4_TI_SRC_DREQ_BITS 10:10 + #define DMA4_TI_SRC_DREQ_SET 0x00000400 + #define DMA4_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA4_TI_SRC_DREQ_MSB 10 + #define DMA4_TI_SRC_DREQ_LSB 10 + #define DMA4_TI_SRC_WIDTH_BITS 9:9 + #define DMA4_TI_SRC_WIDTH_SET 0x00000200 + #define DMA4_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA4_TI_SRC_WIDTH_MSB 9 + #define DMA4_TI_SRC_WIDTH_LSB 9 + #define DMA4_TI_SRC_INC_BITS 8:8 + #define DMA4_TI_SRC_INC_SET 0x00000100 + #define DMA4_TI_SRC_INC_CLR 0xfffffeff + #define DMA4_TI_SRC_INC_MSB 8 + #define DMA4_TI_SRC_INC_LSB 8 + #define DMA4_TI_DEST_IGNORE_BITS 7:7 + #define DMA4_TI_DEST_IGNORE_SET 0x00000080 + #define DMA4_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA4_TI_DEST_IGNORE_MSB 7 + #define DMA4_TI_DEST_IGNORE_LSB 7 + #define DMA4_TI_DEST_DREQ_BITS 6:6 + #define DMA4_TI_DEST_DREQ_SET 0x00000040 + #define DMA4_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA4_TI_DEST_DREQ_MSB 6 + #define DMA4_TI_DEST_DREQ_LSB 6 + #define DMA4_TI_DEST_WIDTH_BITS 5:5 + #define DMA4_TI_DEST_WIDTH_SET 0x00000020 + #define DMA4_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA4_TI_DEST_WIDTH_MSB 5 + #define DMA4_TI_DEST_WIDTH_LSB 5 + #define DMA4_TI_DEST_INC_BITS 4:4 + #define DMA4_TI_DEST_INC_SET 0x00000010 + #define DMA4_TI_DEST_INC_CLR 0xffffffef + #define DMA4_TI_DEST_INC_MSB 4 + #define DMA4_TI_DEST_INC_LSB 4 + #define DMA4_TI_WAIT_RESP_BITS 3:3 + #define DMA4_TI_WAIT_RESP_SET 0x00000008 + #define DMA4_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA4_TI_WAIT_RESP_MSB 3 + #define DMA4_TI_WAIT_RESP_LSB 3 + #define DMA4_TI_TDMODE_BITS 1:1 + #define DMA4_TI_TDMODE_SET 0x00000002 + #define DMA4_TI_TDMODE_CLR 0xfffffffd + #define DMA4_TI_TDMODE_MSB 1 + #define DMA4_TI_TDMODE_LSB 1 + #define DMA4_TI_INTEN_BITS 0:0 + #define DMA4_TI_INTEN_SET 0x00000001 + #define DMA4_TI_INTEN_CLR 0xfffffffe + #define DMA4_TI_INTEN_MSB 0 + #define DMA4_TI_INTEN_LSB 0 +#define DMA4_SOURCE_AD HW_REGISTER_RO( 0x7e00740c ) + #define DMA4_SOURCE_AD_MASK 0xffffffff + #define DMA4_SOURCE_AD_WIDTH 32 + #define DMA4_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA4_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA4_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA4_SOURCE_AD_S_ADDR_MSB 31 + #define DMA4_SOURCE_AD_S_ADDR_LSB 0 +#define DMA4_DEST_AD HW_REGISTER_RO( 0x7e007410 ) + #define DMA4_DEST_AD_MASK 0xffffffff + #define DMA4_DEST_AD_WIDTH 32 + #define DMA4_DEST_AD_D_ADDR_BITS 31:0 + #define DMA4_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA4_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA4_DEST_AD_D_ADDR_MSB 31 + #define DMA4_DEST_AD_D_ADDR_LSB 0 +#define DMA4_TXFR_LEN HW_REGISTER_RO( 0x7e007414 ) + #define DMA4_TXFR_LEN_MASK 0x3fffffff + #define DMA4_TXFR_LEN_WIDTH 30 + #define DMA4_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA4_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA4_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA4_TXFR_LEN_YLENGTH_MSB 29 + #define DMA4_TXFR_LEN_YLENGTH_LSB 16 + #define DMA4_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA4_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA4_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA4_TXFR_LEN_XLENGTH_MSB 15 + #define DMA4_TXFR_LEN_XLENGTH_LSB 0 +#define DMA4_STRIDE HW_REGISTER_RO( 0x7e007418 ) + #define DMA4_STRIDE_MASK 0xffffffff + #define DMA4_STRIDE_WIDTH 32 + #define DMA4_STRIDE_D_STRIDE_BITS 31:16 + #define DMA4_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA4_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA4_STRIDE_D_STRIDE_MSB 31 + #define DMA4_STRIDE_D_STRIDE_LSB 16 + #define DMA4_STRIDE_S_STRIDE_BITS 15:0 + #define DMA4_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA4_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA4_STRIDE_S_STRIDE_MSB 15 + #define DMA4_STRIDE_S_STRIDE_LSB 0 +#define DMA4_NEXTCONBK HW_REGISTER_RO( 0x7e00741c ) + #define DMA4_NEXTCONBK_MASK 0xffffffe0 + #define DMA4_NEXTCONBK_WIDTH 32 + #define DMA4_NEXTCONBK_ADDR_BITS 31:5 + #define DMA4_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA4_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA4_NEXTCONBK_ADDR_MSB 31 + #define DMA4_NEXTCONBK_ADDR_LSB 5 +#define DMA4_DEBUG HW_REGISTER_RW( 0x7e007420 ) + #define DMA4_DEBUG_MASK 0x1ffffff7 + #define DMA4_DEBUG_WIDTH 29 + #define DMA4_DEBUG_RESET 0000000000 + #define DMA4_DEBUG_LITE_BITS 28:28 + #define DMA4_DEBUG_LITE_SET 0x10000000 + #define DMA4_DEBUG_LITE_CLR 0xefffffff + #define DMA4_DEBUG_LITE_MSB 28 + #define DMA4_DEBUG_LITE_LSB 28 + #define DMA4_DEBUG_VERSION_BITS 27:25 + #define DMA4_DEBUG_VERSION_SET 0x0e000000 + #define DMA4_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA4_DEBUG_VERSION_MSB 27 + #define DMA4_DEBUG_VERSION_LSB 25 + #define DMA4_DEBUG_DMA_STATE_BITS 24:16 + #define DMA4_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA4_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA4_DEBUG_DMA_STATE_MSB 24 + #define DMA4_DEBUG_DMA_STATE_LSB 16 + #define DMA4_DEBUG_DMA_ID_BITS 15:8 + #define DMA4_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA4_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA4_DEBUG_DMA_ID_MSB 15 + #define DMA4_DEBUG_DMA_ID_LSB 8 + #define DMA4_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA4_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA4_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA4_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA4_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA4_DEBUG_READ_ERROR_BITS 2:2 + #define DMA4_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA4_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA4_DEBUG_READ_ERROR_MSB 2 + #define DMA4_DEBUG_READ_ERROR_LSB 2 + #define DMA4_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA4_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA4_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA4_DEBUG_FIFO_ERROR_MSB 1 + #define DMA4_DEBUG_FIFO_ERROR_LSB 1 + #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma5.h b/bcm2708_chip/axi_dma5.h new file mode 100755 index 0000000..a8f6a1f --- /dev/null +++ b/bcm2708_chip/axi_dma5.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA5_BASE 0x7e007500 +#define DMA5_CS HW_REGISTER_RW( 0x7e007500 ) + #define DMA5_CS_MASK 0xf0ff017f + #define DMA5_CS_WIDTH 32 + #define DMA5_CS_RESET 0000000000 + #define DMA5_CS_RESET_BITS 31:31 + #define DMA5_CS_RESET_SET 0x80000000 + #define DMA5_CS_RESET_CLR 0x7fffffff + #define DMA5_CS_RESET_MSB 31 + #define DMA5_CS_RESET_LSB 31 + #define DMA5_CS_ABORT_BITS 30:30 + #define DMA5_CS_ABORT_SET 0x40000000 + #define DMA5_CS_ABORT_CLR 0xbfffffff + #define DMA5_CS_ABORT_MSB 30 + #define DMA5_CS_ABORT_LSB 30 + #define DMA5_CS_DISDEBUG_BITS 29:29 + #define DMA5_CS_DISDEBUG_SET 0x20000000 + #define DMA5_CS_DISDEBUG_CLR 0xdfffffff + #define DMA5_CS_DISDEBUG_MSB 29 + #define DMA5_CS_DISDEBUG_LSB 29 + #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA5_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA5_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA5_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA5_CS_PANIC_PRIORITY_MSB 23 + #define DMA5_CS_PANIC_PRIORITY_LSB 20 + #define DMA5_CS_PRIORITY_BITS 19:16 + #define DMA5_CS_PRIORITY_SET 0x000f0000 + #define DMA5_CS_PRIORITY_CLR 0xfff0ffff + #define DMA5_CS_PRIORITY_MSB 19 + #define DMA5_CS_PRIORITY_LSB 16 + #define DMA5_CS_ERROR_BITS 8:8 + #define DMA5_CS_ERROR_SET 0x00000100 + #define DMA5_CS_ERROR_CLR 0xfffffeff + #define DMA5_CS_ERROR_MSB 8 + #define DMA5_CS_ERROR_LSB 8 + #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA5_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA5_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA5_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA5_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA5_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA5_CS_PAUSED_BITS 4:4 + #define DMA5_CS_PAUSED_SET 0x00000010 + #define DMA5_CS_PAUSED_CLR 0xffffffef + #define DMA5_CS_PAUSED_MSB 4 + #define DMA5_CS_PAUSED_LSB 4 + #define DMA5_CS_DREQ_BITS 3:3 + #define DMA5_CS_DREQ_SET 0x00000008 + #define DMA5_CS_DREQ_CLR 0xfffffff7 + #define DMA5_CS_DREQ_MSB 3 + #define DMA5_CS_DREQ_LSB 3 + #define DMA5_CS_INT_BITS 2:2 + #define DMA5_CS_INT_SET 0x00000004 + #define DMA5_CS_INT_CLR 0xfffffffb + #define DMA5_CS_INT_MSB 2 + #define DMA5_CS_INT_LSB 2 + #define DMA5_CS_END_BITS 1:1 + #define DMA5_CS_END_SET 0x00000002 + #define DMA5_CS_END_CLR 0xfffffffd + #define DMA5_CS_END_MSB 1 + #define DMA5_CS_END_LSB 1 + #define DMA5_CS_ACTIVE_BITS 0:0 + #define DMA5_CS_ACTIVE_SET 0x00000001 + #define DMA5_CS_ACTIVE_CLR 0xfffffffe + #define DMA5_CS_ACTIVE_MSB 0 + #define DMA5_CS_ACTIVE_LSB 0 +#define DMA5_CONBLK_AD HW_REGISTER_RW( 0x7e007504 ) + #define DMA5_CONBLK_AD_MASK 0xffffffe0 + #define DMA5_CONBLK_AD_WIDTH 32 + #define DMA5_CONBLK_AD_RESET 0000000000 + #define DMA5_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA5_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA5_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA5_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA5_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA5_TI HW_REGISTER_RO( 0x7e007508 ) + #define DMA5_TI_MASK 0x07fffffb + #define DMA5_TI_WIDTH 27 + #define DMA5_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA5_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA5_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA5_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA5_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA5_TI_WAITS_BITS 25:21 + #define DMA5_TI_WAITS_SET 0x03e00000 + #define DMA5_TI_WAITS_CLR 0xfc1fffff + #define DMA5_TI_WAITS_MSB 25 + #define DMA5_TI_WAITS_LSB 21 + #define DMA5_TI_PERMAP_BITS 20:16 + #define DMA5_TI_PERMAP_SET 0x001f0000 + #define DMA5_TI_PERMAP_CLR 0xffe0ffff + #define DMA5_TI_PERMAP_MSB 20 + #define DMA5_TI_PERMAP_LSB 16 + #define DMA5_TI_BURST_LENGTH_BITS 15:12 + #define DMA5_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA5_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA5_TI_BURST_LENGTH_MSB 15 + #define DMA5_TI_BURST_LENGTH_LSB 12 + #define DMA5_TI_SRC_IGNORE_BITS 11:11 + #define DMA5_TI_SRC_IGNORE_SET 0x00000800 + #define DMA5_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA5_TI_SRC_IGNORE_MSB 11 + #define DMA5_TI_SRC_IGNORE_LSB 11 + #define DMA5_TI_SRC_DREQ_BITS 10:10 + #define DMA5_TI_SRC_DREQ_SET 0x00000400 + #define DMA5_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA5_TI_SRC_DREQ_MSB 10 + #define DMA5_TI_SRC_DREQ_LSB 10 + #define DMA5_TI_SRC_WIDTH_BITS 9:9 + #define DMA5_TI_SRC_WIDTH_SET 0x00000200 + #define DMA5_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA5_TI_SRC_WIDTH_MSB 9 + #define DMA5_TI_SRC_WIDTH_LSB 9 + #define DMA5_TI_SRC_INC_BITS 8:8 + #define DMA5_TI_SRC_INC_SET 0x00000100 + #define DMA5_TI_SRC_INC_CLR 0xfffffeff + #define DMA5_TI_SRC_INC_MSB 8 + #define DMA5_TI_SRC_INC_LSB 8 + #define DMA5_TI_DEST_IGNORE_BITS 7:7 + #define DMA5_TI_DEST_IGNORE_SET 0x00000080 + #define DMA5_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA5_TI_DEST_IGNORE_MSB 7 + #define DMA5_TI_DEST_IGNORE_LSB 7 + #define DMA5_TI_DEST_DREQ_BITS 6:6 + #define DMA5_TI_DEST_DREQ_SET 0x00000040 + #define DMA5_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA5_TI_DEST_DREQ_MSB 6 + #define DMA5_TI_DEST_DREQ_LSB 6 + #define DMA5_TI_DEST_WIDTH_BITS 5:5 + #define DMA5_TI_DEST_WIDTH_SET 0x00000020 + #define DMA5_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA5_TI_DEST_WIDTH_MSB 5 + #define DMA5_TI_DEST_WIDTH_LSB 5 + #define DMA5_TI_DEST_INC_BITS 4:4 + #define DMA5_TI_DEST_INC_SET 0x00000010 + #define DMA5_TI_DEST_INC_CLR 0xffffffef + #define DMA5_TI_DEST_INC_MSB 4 + #define DMA5_TI_DEST_INC_LSB 4 + #define DMA5_TI_WAIT_RESP_BITS 3:3 + #define DMA5_TI_WAIT_RESP_SET 0x00000008 + #define DMA5_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA5_TI_WAIT_RESP_MSB 3 + #define DMA5_TI_WAIT_RESP_LSB 3 + #define DMA5_TI_TDMODE_BITS 1:1 + #define DMA5_TI_TDMODE_SET 0x00000002 + #define DMA5_TI_TDMODE_CLR 0xfffffffd + #define DMA5_TI_TDMODE_MSB 1 + #define DMA5_TI_TDMODE_LSB 1 + #define DMA5_TI_INTEN_BITS 0:0 + #define DMA5_TI_INTEN_SET 0x00000001 + #define DMA5_TI_INTEN_CLR 0xfffffffe + #define DMA5_TI_INTEN_MSB 0 + #define DMA5_TI_INTEN_LSB 0 +#define DMA5_SOURCE_AD HW_REGISTER_RO( 0x7e00750c ) + #define DMA5_SOURCE_AD_MASK 0xffffffff + #define DMA5_SOURCE_AD_WIDTH 32 + #define DMA5_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA5_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA5_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA5_SOURCE_AD_S_ADDR_MSB 31 + #define DMA5_SOURCE_AD_S_ADDR_LSB 0 +#define DMA5_DEST_AD HW_REGISTER_RO( 0x7e007510 ) + #define DMA5_DEST_AD_MASK 0xffffffff + #define DMA5_DEST_AD_WIDTH 32 + #define DMA5_DEST_AD_D_ADDR_BITS 31:0 + #define DMA5_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA5_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA5_DEST_AD_D_ADDR_MSB 31 + #define DMA5_DEST_AD_D_ADDR_LSB 0 +#define DMA5_TXFR_LEN HW_REGISTER_RO( 0x7e007514 ) + #define DMA5_TXFR_LEN_MASK 0x3fffffff + #define DMA5_TXFR_LEN_WIDTH 30 + #define DMA5_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA5_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA5_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA5_TXFR_LEN_YLENGTH_MSB 29 + #define DMA5_TXFR_LEN_YLENGTH_LSB 16 + #define DMA5_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA5_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA5_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA5_TXFR_LEN_XLENGTH_MSB 15 + #define DMA5_TXFR_LEN_XLENGTH_LSB 0 +#define DMA5_STRIDE HW_REGISTER_RO( 0x7e007518 ) + #define DMA5_STRIDE_MASK 0xffffffff + #define DMA5_STRIDE_WIDTH 32 + #define DMA5_STRIDE_D_STRIDE_BITS 31:16 + #define DMA5_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA5_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA5_STRIDE_D_STRIDE_MSB 31 + #define DMA5_STRIDE_D_STRIDE_LSB 16 + #define DMA5_STRIDE_S_STRIDE_BITS 15:0 + #define DMA5_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA5_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA5_STRIDE_S_STRIDE_MSB 15 + #define DMA5_STRIDE_S_STRIDE_LSB 0 +#define DMA5_NEXTCONBK HW_REGISTER_RO( 0x7e00751c ) + #define DMA5_NEXTCONBK_MASK 0xffffffe0 + #define DMA5_NEXTCONBK_WIDTH 32 + #define DMA5_NEXTCONBK_ADDR_BITS 31:5 + #define DMA5_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA5_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA5_NEXTCONBK_ADDR_MSB 31 + #define DMA5_NEXTCONBK_ADDR_LSB 5 +#define DMA5_DEBUG HW_REGISTER_RW( 0x7e007520 ) + #define DMA5_DEBUG_MASK 0x1ffffff7 + #define DMA5_DEBUG_WIDTH 29 + #define DMA5_DEBUG_RESET 0000000000 + #define DMA5_DEBUG_LITE_BITS 28:28 + #define DMA5_DEBUG_LITE_SET 0x10000000 + #define DMA5_DEBUG_LITE_CLR 0xefffffff + #define DMA5_DEBUG_LITE_MSB 28 + #define DMA5_DEBUG_LITE_LSB 28 + #define DMA5_DEBUG_VERSION_BITS 27:25 + #define DMA5_DEBUG_VERSION_SET 0x0e000000 + #define DMA5_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA5_DEBUG_VERSION_MSB 27 + #define DMA5_DEBUG_VERSION_LSB 25 + #define DMA5_DEBUG_DMA_STATE_BITS 24:16 + #define DMA5_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA5_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA5_DEBUG_DMA_STATE_MSB 24 + #define DMA5_DEBUG_DMA_STATE_LSB 16 + #define DMA5_DEBUG_DMA_ID_BITS 15:8 + #define DMA5_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA5_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA5_DEBUG_DMA_ID_MSB 15 + #define DMA5_DEBUG_DMA_ID_LSB 8 + #define DMA5_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA5_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA5_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA5_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA5_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA5_DEBUG_READ_ERROR_BITS 2:2 + #define DMA5_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA5_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA5_DEBUG_READ_ERROR_MSB 2 + #define DMA5_DEBUG_READ_ERROR_LSB 2 + #define DMA5_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA5_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA5_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA5_DEBUG_FIFO_ERROR_MSB 1 + #define DMA5_DEBUG_FIFO_ERROR_LSB 1 + #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma6.h b/bcm2708_chip/axi_dma6.h new file mode 100755 index 0000000..988f002 --- /dev/null +++ b/bcm2708_chip/axi_dma6.h @@ -0,0 +1,257 @@ +// This file was generated by the create_regs script +#define DMA6_BASE 0x7e007600 +#define DMA6_CS HW_REGISTER_RW( 0x7e007600 ) + #define DMA6_CS_MASK 0xf0ff017f + #define DMA6_CS_WIDTH 32 + #define DMA6_CS_RESET 0000000000 + #define DMA6_CS_RESET_BITS 31:31 + #define DMA6_CS_RESET_SET 0x80000000 + #define DMA6_CS_RESET_CLR 0x7fffffff + #define DMA6_CS_RESET_MSB 31 + #define DMA6_CS_RESET_LSB 31 + #define DMA6_CS_ABORT_BITS 30:30 + #define DMA6_CS_ABORT_SET 0x40000000 + #define DMA6_CS_ABORT_CLR 0xbfffffff + #define DMA6_CS_ABORT_MSB 30 + #define DMA6_CS_ABORT_LSB 30 + #define DMA6_CS_DISDEBUG_BITS 29:29 + #define DMA6_CS_DISDEBUG_SET 0x20000000 + #define DMA6_CS_DISDEBUG_CLR 0xdfffffff + #define DMA6_CS_DISDEBUG_MSB 29 + #define DMA6_CS_DISDEBUG_LSB 29 + #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA6_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA6_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA6_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA6_CS_PANIC_PRIORITY_MSB 23 + #define DMA6_CS_PANIC_PRIORITY_LSB 20 + #define DMA6_CS_PRIORITY_BITS 19:16 + #define DMA6_CS_PRIORITY_SET 0x000f0000 + #define DMA6_CS_PRIORITY_CLR 0xfff0ffff + #define DMA6_CS_PRIORITY_MSB 19 + #define DMA6_CS_PRIORITY_LSB 16 + #define DMA6_CS_ERROR_BITS 8:8 + #define DMA6_CS_ERROR_SET 0x00000100 + #define DMA6_CS_ERROR_CLR 0xfffffeff + #define DMA6_CS_ERROR_MSB 8 + #define DMA6_CS_ERROR_LSB 8 + #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA6_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA6_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA6_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA6_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA6_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA6_CS_PAUSED_BITS 4:4 + #define DMA6_CS_PAUSED_SET 0x00000010 + #define DMA6_CS_PAUSED_CLR 0xffffffef + #define DMA6_CS_PAUSED_MSB 4 + #define DMA6_CS_PAUSED_LSB 4 + #define DMA6_CS_DREQ_BITS 3:3 + #define DMA6_CS_DREQ_SET 0x00000008 + #define DMA6_CS_DREQ_CLR 0xfffffff7 + #define DMA6_CS_DREQ_MSB 3 + #define DMA6_CS_DREQ_LSB 3 + #define DMA6_CS_INT_BITS 2:2 + #define DMA6_CS_INT_SET 0x00000004 + #define DMA6_CS_INT_CLR 0xfffffffb + #define DMA6_CS_INT_MSB 2 + #define DMA6_CS_INT_LSB 2 + #define DMA6_CS_END_BITS 1:1 + #define DMA6_CS_END_SET 0x00000002 + #define DMA6_CS_END_CLR 0xfffffffd + #define DMA6_CS_END_MSB 1 + #define DMA6_CS_END_LSB 1 + #define DMA6_CS_ACTIVE_BITS 0:0 + #define DMA6_CS_ACTIVE_SET 0x00000001 + #define DMA6_CS_ACTIVE_CLR 0xfffffffe + #define DMA6_CS_ACTIVE_MSB 0 + #define DMA6_CS_ACTIVE_LSB 0 +#define DMA6_CONBLK_AD HW_REGISTER_RW( 0x7e007604 ) + #define DMA6_CONBLK_AD_MASK 0xffffffe0 + #define DMA6_CONBLK_AD_WIDTH 32 + #define DMA6_CONBLK_AD_RESET 0000000000 + #define DMA6_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA6_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA6_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA6_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA6_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA6_TI HW_REGISTER_RO( 0x7e007608 ) + #define DMA6_TI_MASK 0x07fffffb + #define DMA6_TI_WIDTH 27 + #define DMA6_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA6_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA6_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA6_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA6_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA6_TI_WAITS_BITS 25:21 + #define DMA6_TI_WAITS_SET 0x03e00000 + #define DMA6_TI_WAITS_CLR 0xfc1fffff + #define DMA6_TI_WAITS_MSB 25 + #define DMA6_TI_WAITS_LSB 21 + #define DMA6_TI_PERMAP_BITS 20:16 + #define DMA6_TI_PERMAP_SET 0x001f0000 + #define DMA6_TI_PERMAP_CLR 0xffe0ffff + #define DMA6_TI_PERMAP_MSB 20 + #define DMA6_TI_PERMAP_LSB 16 + #define DMA6_TI_BURST_LENGTH_BITS 15:12 + #define DMA6_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA6_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA6_TI_BURST_LENGTH_MSB 15 + #define DMA6_TI_BURST_LENGTH_LSB 12 + #define DMA6_TI_SRC_IGNORE_BITS 11:11 + #define DMA6_TI_SRC_IGNORE_SET 0x00000800 + #define DMA6_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA6_TI_SRC_IGNORE_MSB 11 + #define DMA6_TI_SRC_IGNORE_LSB 11 + #define DMA6_TI_SRC_DREQ_BITS 10:10 + #define DMA6_TI_SRC_DREQ_SET 0x00000400 + #define DMA6_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA6_TI_SRC_DREQ_MSB 10 + #define DMA6_TI_SRC_DREQ_LSB 10 + #define DMA6_TI_SRC_WIDTH_BITS 9:9 + #define DMA6_TI_SRC_WIDTH_SET 0x00000200 + #define DMA6_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA6_TI_SRC_WIDTH_MSB 9 + #define DMA6_TI_SRC_WIDTH_LSB 9 + #define DMA6_TI_SRC_INC_BITS 8:8 + #define DMA6_TI_SRC_INC_SET 0x00000100 + #define DMA6_TI_SRC_INC_CLR 0xfffffeff + #define DMA6_TI_SRC_INC_MSB 8 + #define DMA6_TI_SRC_INC_LSB 8 + #define DMA6_TI_DEST_IGNORE_BITS 7:7 + #define DMA6_TI_DEST_IGNORE_SET 0x00000080 + #define DMA6_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA6_TI_DEST_IGNORE_MSB 7 + #define DMA6_TI_DEST_IGNORE_LSB 7 + #define DMA6_TI_DEST_DREQ_BITS 6:6 + #define DMA6_TI_DEST_DREQ_SET 0x00000040 + #define DMA6_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA6_TI_DEST_DREQ_MSB 6 + #define DMA6_TI_DEST_DREQ_LSB 6 + #define DMA6_TI_DEST_WIDTH_BITS 5:5 + #define DMA6_TI_DEST_WIDTH_SET 0x00000020 + #define DMA6_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA6_TI_DEST_WIDTH_MSB 5 + #define DMA6_TI_DEST_WIDTH_LSB 5 + #define DMA6_TI_DEST_INC_BITS 4:4 + #define DMA6_TI_DEST_INC_SET 0x00000010 + #define DMA6_TI_DEST_INC_CLR 0xffffffef + #define DMA6_TI_DEST_INC_MSB 4 + #define DMA6_TI_DEST_INC_LSB 4 + #define DMA6_TI_WAIT_RESP_BITS 3:3 + #define DMA6_TI_WAIT_RESP_SET 0x00000008 + #define DMA6_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA6_TI_WAIT_RESP_MSB 3 + #define DMA6_TI_WAIT_RESP_LSB 3 + #define DMA6_TI_TDMODE_BITS 1:1 + #define DMA6_TI_TDMODE_SET 0x00000002 + #define DMA6_TI_TDMODE_CLR 0xfffffffd + #define DMA6_TI_TDMODE_MSB 1 + #define DMA6_TI_TDMODE_LSB 1 + #define DMA6_TI_INTEN_BITS 0:0 + #define DMA6_TI_INTEN_SET 0x00000001 + #define DMA6_TI_INTEN_CLR 0xfffffffe + #define DMA6_TI_INTEN_MSB 0 + #define DMA6_TI_INTEN_LSB 0 +#define DMA6_SOURCE_AD HW_REGISTER_RO( 0x7e00760c ) + #define DMA6_SOURCE_AD_MASK 0xffffffff + #define DMA6_SOURCE_AD_WIDTH 32 + #define DMA6_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA6_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA6_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA6_SOURCE_AD_S_ADDR_MSB 31 + #define DMA6_SOURCE_AD_S_ADDR_LSB 0 +#define DMA6_DEST_AD HW_REGISTER_RO( 0x7e007610 ) + #define DMA6_DEST_AD_MASK 0xffffffff + #define DMA6_DEST_AD_WIDTH 32 + #define DMA6_DEST_AD_D_ADDR_BITS 31:0 + #define DMA6_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA6_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA6_DEST_AD_D_ADDR_MSB 31 + #define DMA6_DEST_AD_D_ADDR_LSB 0 +#define DMA6_TXFR_LEN HW_REGISTER_RO( 0x7e007614 ) + #define DMA6_TXFR_LEN_MASK 0x3fffffff + #define DMA6_TXFR_LEN_WIDTH 30 + #define DMA6_TXFR_LEN_YLENGTH_BITS 29:16 + #define DMA6_TXFR_LEN_YLENGTH_SET 0x3fff0000 + #define DMA6_TXFR_LEN_YLENGTH_CLR 0xc000ffff + #define DMA6_TXFR_LEN_YLENGTH_MSB 29 + #define DMA6_TXFR_LEN_YLENGTH_LSB 16 + #define DMA6_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA6_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA6_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA6_TXFR_LEN_XLENGTH_MSB 15 + #define DMA6_TXFR_LEN_XLENGTH_LSB 0 +#define DMA6_STRIDE HW_REGISTER_RO( 0x7e007618 ) + #define DMA6_STRIDE_MASK 0xffffffff + #define DMA6_STRIDE_WIDTH 32 + #define DMA6_STRIDE_D_STRIDE_BITS 31:16 + #define DMA6_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA6_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA6_STRIDE_D_STRIDE_MSB 31 + #define DMA6_STRIDE_D_STRIDE_LSB 16 + #define DMA6_STRIDE_S_STRIDE_BITS 15:0 + #define DMA6_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA6_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA6_STRIDE_S_STRIDE_MSB 15 + #define DMA6_STRIDE_S_STRIDE_LSB 0 +#define DMA6_NEXTCONBK HW_REGISTER_RO( 0x7e00761c ) + #define DMA6_NEXTCONBK_MASK 0xffffffe0 + #define DMA6_NEXTCONBK_WIDTH 32 + #define DMA6_NEXTCONBK_ADDR_BITS 31:5 + #define DMA6_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA6_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA6_NEXTCONBK_ADDR_MSB 31 + #define DMA6_NEXTCONBK_ADDR_LSB 5 +#define DMA6_DEBUG HW_REGISTER_RW( 0x7e007620 ) + #define DMA6_DEBUG_MASK 0x1ffffff7 + #define DMA6_DEBUG_WIDTH 29 + #define DMA6_DEBUG_RESET 0000000000 + #define DMA6_DEBUG_LITE_BITS 28:28 + #define DMA6_DEBUG_LITE_SET 0x10000000 + #define DMA6_DEBUG_LITE_CLR 0xefffffff + #define DMA6_DEBUG_LITE_MSB 28 + #define DMA6_DEBUG_LITE_LSB 28 + #define DMA6_DEBUG_VERSION_BITS 27:25 + #define DMA6_DEBUG_VERSION_SET 0x0e000000 + #define DMA6_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA6_DEBUG_VERSION_MSB 27 + #define DMA6_DEBUG_VERSION_LSB 25 + #define DMA6_DEBUG_DMA_STATE_BITS 24:16 + #define DMA6_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA6_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA6_DEBUG_DMA_STATE_MSB 24 + #define DMA6_DEBUG_DMA_STATE_LSB 16 + #define DMA6_DEBUG_DMA_ID_BITS 15:8 + #define DMA6_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA6_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA6_DEBUG_DMA_ID_MSB 15 + #define DMA6_DEBUG_DMA_ID_LSB 8 + #define DMA6_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA6_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA6_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA6_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA6_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA6_DEBUG_READ_ERROR_BITS 2:2 + #define DMA6_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA6_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA6_DEBUG_READ_ERROR_MSB 2 + #define DMA6_DEBUG_READ_ERROR_LSB 2 + #define DMA6_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA6_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA6_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA6_DEBUG_FIFO_ERROR_MSB 1 + #define DMA6_DEBUG_FIFO_ERROR_LSB 1 + #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma7.h b/bcm2708_chip/axi_dma7.h new file mode 100755 index 0000000..e544821 --- /dev/null +++ b/bcm2708_chip/axi_dma7.h @@ -0,0 +1,247 @@ +// This file was generated by the create_regs script +#define DMA7_BASE 0x7e007700 +#define DMA7_CS HW_REGISTER_RW( 0x7e007700 ) + #define DMA7_CS_MASK 0xf0ff017f + #define DMA7_CS_WIDTH 32 + #define DMA7_CS_RESET 0000000000 + #define DMA7_CS_RESET_BITS 31:31 + #define DMA7_CS_RESET_SET 0x80000000 + #define DMA7_CS_RESET_CLR 0x7fffffff + #define DMA7_CS_RESET_MSB 31 + #define DMA7_CS_RESET_LSB 31 + #define DMA7_CS_ABORT_BITS 30:30 + #define DMA7_CS_ABORT_SET 0x40000000 + #define DMA7_CS_ABORT_CLR 0xbfffffff + #define DMA7_CS_ABORT_MSB 30 + #define DMA7_CS_ABORT_LSB 30 + #define DMA7_CS_DISDEBUG_BITS 29:29 + #define DMA7_CS_DISDEBUG_SET 0x20000000 + #define DMA7_CS_DISDEBUG_CLR 0xdfffffff + #define DMA7_CS_DISDEBUG_MSB 29 + #define DMA7_CS_DISDEBUG_LSB 29 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA7_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA7_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA7_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA7_CS_PANIC_PRIORITY_MSB 23 + #define DMA7_CS_PANIC_PRIORITY_LSB 20 + #define DMA7_CS_PRIORITY_BITS 19:16 + #define DMA7_CS_PRIORITY_SET 0x000f0000 + #define DMA7_CS_PRIORITY_CLR 0xfff0ffff + #define DMA7_CS_PRIORITY_MSB 19 + #define DMA7_CS_PRIORITY_LSB 16 + #define DMA7_CS_ERROR_BITS 8:8 + #define DMA7_CS_ERROR_SET 0x00000100 + #define DMA7_CS_ERROR_CLR 0xfffffeff + #define DMA7_CS_ERROR_MSB 8 + #define DMA7_CS_ERROR_LSB 8 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA7_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA7_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA7_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA7_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA7_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA7_CS_PAUSED_BITS 4:4 + #define DMA7_CS_PAUSED_SET 0x00000010 + #define DMA7_CS_PAUSED_CLR 0xffffffef + #define DMA7_CS_PAUSED_MSB 4 + #define DMA7_CS_PAUSED_LSB 4 + #define DMA7_CS_DREQ_BITS 3:3 + #define DMA7_CS_DREQ_SET 0x00000008 + #define DMA7_CS_DREQ_CLR 0xfffffff7 + #define DMA7_CS_DREQ_MSB 3 + #define DMA7_CS_DREQ_LSB 3 + #define DMA7_CS_INT_BITS 2:2 + #define DMA7_CS_INT_SET 0x00000004 + #define DMA7_CS_INT_CLR 0xfffffffb + #define DMA7_CS_INT_MSB 2 + #define DMA7_CS_INT_LSB 2 + #define DMA7_CS_END_BITS 1:1 + #define DMA7_CS_END_SET 0x00000002 + #define DMA7_CS_END_CLR 0xfffffffd + #define DMA7_CS_END_MSB 1 + #define DMA7_CS_END_LSB 1 + #define DMA7_CS_ACTIVE_BITS 0:0 + #define DMA7_CS_ACTIVE_SET 0x00000001 + #define DMA7_CS_ACTIVE_CLR 0xfffffffe + #define DMA7_CS_ACTIVE_MSB 0 + #define DMA7_CS_ACTIVE_LSB 0 +#define DMA7_CONBLK_AD HW_REGISTER_RW( 0x7e007704 ) + #define DMA7_CONBLK_AD_MASK 0xffffffe0 + #define DMA7_CONBLK_AD_WIDTH 32 + #define DMA7_CONBLK_AD_RESET 0000000000 + #define DMA7_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA7_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA7_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA7_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA7_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA7_TI HW_REGISTER_RO( 0x7e007708 ) + #define DMA7_TI_MASK 0x07fffffb + #define DMA7_TI_WIDTH 27 + #define DMA7_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA7_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA7_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA7_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA7_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA7_TI_WAITS_BITS 25:21 + #define DMA7_TI_WAITS_SET 0x03e00000 + #define DMA7_TI_WAITS_CLR 0xfc1fffff + #define DMA7_TI_WAITS_MSB 25 + #define DMA7_TI_WAITS_LSB 21 + #define DMA7_TI_PERMAP_BITS 20:16 + #define DMA7_TI_PERMAP_SET 0x001f0000 + #define DMA7_TI_PERMAP_CLR 0xffe0ffff + #define DMA7_TI_PERMAP_MSB 20 + #define DMA7_TI_PERMAP_LSB 16 + #define DMA7_TI_BURST_LENGTH_BITS 15:12 + #define DMA7_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA7_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA7_TI_BURST_LENGTH_MSB 15 + #define DMA7_TI_BURST_LENGTH_LSB 12 + #define DMA7_TI_SRC_IGNORE_BITS 11:11 + #define DMA7_TI_SRC_IGNORE_SET 0x00000800 + #define DMA7_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA7_TI_SRC_IGNORE_MSB 11 + #define DMA7_TI_SRC_IGNORE_LSB 11 + #define DMA7_TI_SRC_DREQ_BITS 10:10 + #define DMA7_TI_SRC_DREQ_SET 0x00000400 + #define DMA7_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA7_TI_SRC_DREQ_MSB 10 + #define DMA7_TI_SRC_DREQ_LSB 10 + #define DMA7_TI_SRC_WIDTH_BITS 9:9 + #define DMA7_TI_SRC_WIDTH_SET 0x00000200 + #define DMA7_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA7_TI_SRC_WIDTH_MSB 9 + #define DMA7_TI_SRC_WIDTH_LSB 9 + #define DMA7_TI_SRC_INC_BITS 8:8 + #define DMA7_TI_SRC_INC_SET 0x00000100 + #define DMA7_TI_SRC_INC_CLR 0xfffffeff + #define DMA7_TI_SRC_INC_MSB 8 + #define DMA7_TI_SRC_INC_LSB 8 + #define DMA7_TI_DEST_IGNORE_BITS 7:7 + #define DMA7_TI_DEST_IGNORE_SET 0x00000080 + #define DMA7_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA7_TI_DEST_IGNORE_MSB 7 + #define DMA7_TI_DEST_IGNORE_LSB 7 + #define DMA7_TI_DEST_DREQ_BITS 6:6 + #define DMA7_TI_DEST_DREQ_SET 0x00000040 + #define DMA7_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA7_TI_DEST_DREQ_MSB 6 + #define DMA7_TI_DEST_DREQ_LSB 6 + #define DMA7_TI_DEST_WIDTH_BITS 5:5 + #define DMA7_TI_DEST_WIDTH_SET 0x00000020 + #define DMA7_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA7_TI_DEST_WIDTH_MSB 5 + #define DMA7_TI_DEST_WIDTH_LSB 5 + #define DMA7_TI_DEST_INC_BITS 4:4 + #define DMA7_TI_DEST_INC_SET 0x00000010 + #define DMA7_TI_DEST_INC_CLR 0xffffffef + #define DMA7_TI_DEST_INC_MSB 4 + #define DMA7_TI_DEST_INC_LSB 4 + #define DMA7_TI_WAIT_RESP_BITS 3:3 + #define DMA7_TI_WAIT_RESP_SET 0x00000008 + #define DMA7_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA7_TI_WAIT_RESP_MSB 3 + #define DMA7_TI_WAIT_RESP_LSB 3 + #define DMA7_TI_TDMODE_BITS 1:1 + #define DMA7_TI_TDMODE_SET 0x00000002 + #define DMA7_TI_TDMODE_CLR 0xfffffffd + #define DMA7_TI_TDMODE_MSB 1 + #define DMA7_TI_TDMODE_LSB 1 + #define DMA7_TI_INTEN_BITS 0:0 + #define DMA7_TI_INTEN_SET 0x00000001 + #define DMA7_TI_INTEN_CLR 0xfffffffe + #define DMA7_TI_INTEN_MSB 0 + #define DMA7_TI_INTEN_LSB 0 +#define DMA7_SOURCE_AD HW_REGISTER_RO( 0x7e00770c ) + #define DMA7_SOURCE_AD_MASK 0xffffffff + #define DMA7_SOURCE_AD_WIDTH 32 + #define DMA7_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA7_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA7_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA7_SOURCE_AD_S_ADDR_MSB 31 + #define DMA7_SOURCE_AD_S_ADDR_LSB 0 +#define DMA7_DEST_AD HW_REGISTER_RO( 0x7e007710 ) + #define DMA7_DEST_AD_MASK 0xffffffff + #define DMA7_DEST_AD_WIDTH 32 + #define DMA7_DEST_AD_D_ADDR_BITS 31:0 + #define DMA7_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA7_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA7_DEST_AD_D_ADDR_MSB 31 + #define DMA7_DEST_AD_D_ADDR_LSB 0 +#define DMA7_TXFR_LEN HW_REGISTER_RO( 0x7e007714 ) + #define DMA7_TXFR_LEN_MASK 0x3fffffff + #define DMA7_TXFR_LEN_WIDTH 30 + #define DMA7_TXFR_LEN_ylength_BITS 29:16 + #define DMA7_TXFR_LEN_ylength_SET 0x3fff0000 + #define DMA7_TXFR_LEN_ylength_CLR 0xc000ffff + #define DMA7_TXFR_LEN_ylength_MSB 29 + #define DMA7_TXFR_LEN_ylength_LSB 16 + #define DMA7_TXFR_LEN_xlength_BITS 15:0 + #define DMA7_TXFR_LEN_xlength_SET 0x0000ffff + #define DMA7_TXFR_LEN_xlength_CLR 0xffff0000 + #define DMA7_TXFR_LEN_xlength_MSB 15 + #define DMA7_TXFR_LEN_xlength_LSB 0 +#define DMA7_STRIDE HW_REGISTER_RO( 0x7e007718 ) + #define DMA7_STRIDE_MASK 0xffffffff + #define DMA7_STRIDE_WIDTH 32 + #define DMA7_STRIDE_D_STRIDE_BITS 31:16 + #define DMA7_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA7_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA7_STRIDE_D_STRIDE_MSB 31 + #define DMA7_STRIDE_D_STRIDE_LSB 16 + #define DMA7_STRIDE_S_STRIDE_BITS 15:0 + #define DMA7_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA7_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA7_STRIDE_S_STRIDE_MSB 15 + #define DMA7_STRIDE_S_STRIDE_LSB 0 +#define DMA7_NEXTCONBK HW_REGISTER_RO( 0x7e00771c ) + #define DMA7_NEXTCONBK_MASK 0xffffffe0 + #define DMA7_NEXTCONBK_WIDTH 32 +#define DMA7_DEBUG HW_REGISTER_RW( 0x7e007720 ) + #define DMA7_DEBUG_MASK 0x0ffffff7 + #define DMA7_DEBUG_WIDTH 28 + #define DMA7_DEBUG_RESET 0000000000 + #define DMA7_DEBUG_VERSION_BITS 27:25 + #define DMA7_DEBUG_VERSION_SET 0x0e000000 + #define DMA7_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA7_DEBUG_VERSION_MSB 27 + #define DMA7_DEBUG_VERSION_LSB 25 + #define DMA7_DEBUG_DMA_STATE_BITS 24:16 + #define DMA7_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA7_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA7_DEBUG_DMA_STATE_MSB 24 + #define DMA7_DEBUG_DMA_STATE_LSB 16 + #define DMA7_DEBUG_DMA_ID_BITS 15:8 + #define DMA7_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA7_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA7_DEBUG_DMA_ID_MSB 15 + #define DMA7_DEBUG_DMA_ID_LSB 8 + #define DMA7_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA7_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA7_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA7_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA7_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA7_DEBUG_READ_ERROR_BITS 2:2 + #define DMA7_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA7_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA7_DEBUG_READ_ERROR_MSB 2 + #define DMA7_DEBUG_READ_ERROR_LSB 2 + #define DMA7_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA7_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA7_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA7_DEBUG_FIFO_ERROR_MSB 1 + #define DMA7_DEBUG_FIFO_ERROR_LSB 1 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma8.h b/bcm2708_chip/axi_dma8.h new file mode 100755 index 0000000..62fc62c --- /dev/null +++ b/bcm2708_chip/axi_dma8.h @@ -0,0 +1,247 @@ +// This file was generated by the create_regs script +#define DMA8_BASE 0x7ee05000 +#define DMA8_CS HW_REGISTER_RW( 0x7ee05000 ) + #define DMA8_CS_MASK 0xf0ff017f + #define DMA8_CS_WIDTH 32 + #define DMA8_CS_RESET 0000000000 + #define DMA8_CS_RESET_BITS 31:31 + #define DMA8_CS_RESET_SET 0x80000000 + #define DMA8_CS_RESET_CLR 0x7fffffff + #define DMA8_CS_RESET_MSB 31 + #define DMA8_CS_RESET_LSB 31 + #define DMA8_CS_ABORT_BITS 30:30 + #define DMA8_CS_ABORT_SET 0x40000000 + #define DMA8_CS_ABORT_CLR 0xbfffffff + #define DMA8_CS_ABORT_MSB 30 + #define DMA8_CS_ABORT_LSB 30 + #define DMA8_CS_DISDEBUG_BITS 29:29 + #define DMA8_CS_DISDEBUG_SET 0x20000000 + #define DMA8_CS_DISDEBUG_CLR 0xdfffffff + #define DMA8_CS_DISDEBUG_MSB 29 + #define DMA8_CS_DISDEBUG_LSB 29 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA8_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA8_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA8_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA8_CS_PANIC_PRIORITY_MSB 23 + #define DMA8_CS_PANIC_PRIORITY_LSB 20 + #define DMA8_CS_PRIORITY_BITS 19:16 + #define DMA8_CS_PRIORITY_SET 0x000f0000 + #define DMA8_CS_PRIORITY_CLR 0xfff0ffff + #define DMA8_CS_PRIORITY_MSB 19 + #define DMA8_CS_PRIORITY_LSB 16 + #define DMA8_CS_ERROR_BITS 8:8 + #define DMA8_CS_ERROR_SET 0x00000100 + #define DMA8_CS_ERROR_CLR 0xfffffeff + #define DMA8_CS_ERROR_MSB 8 + #define DMA8_CS_ERROR_LSB 8 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA8_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA8_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA8_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA8_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA8_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA8_CS_PAUSED_BITS 4:4 + #define DMA8_CS_PAUSED_SET 0x00000010 + #define DMA8_CS_PAUSED_CLR 0xffffffef + #define DMA8_CS_PAUSED_MSB 4 + #define DMA8_CS_PAUSED_LSB 4 + #define DMA8_CS_DREQ_BITS 3:3 + #define DMA8_CS_DREQ_SET 0x00000008 + #define DMA8_CS_DREQ_CLR 0xfffffff7 + #define DMA8_CS_DREQ_MSB 3 + #define DMA8_CS_DREQ_LSB 3 + #define DMA8_CS_INT_BITS 2:2 + #define DMA8_CS_INT_SET 0x00000004 + #define DMA8_CS_INT_CLR 0xfffffffb + #define DMA8_CS_INT_MSB 2 + #define DMA8_CS_INT_LSB 2 + #define DMA8_CS_END_BITS 1:1 + #define DMA8_CS_END_SET 0x00000002 + #define DMA8_CS_END_CLR 0xfffffffd + #define DMA8_CS_END_MSB 1 + #define DMA8_CS_END_LSB 1 + #define DMA8_CS_ACTIVE_BITS 0:0 + #define DMA8_CS_ACTIVE_SET 0x00000001 + #define DMA8_CS_ACTIVE_CLR 0xfffffffe + #define DMA8_CS_ACTIVE_MSB 0 + #define DMA8_CS_ACTIVE_LSB 0 +#define DMA8_CONBLK_AD HW_REGISTER_RW( 0x7ee05004 ) + #define DMA8_CONBLK_AD_MASK 0xffffffe0 + #define DMA8_CONBLK_AD_WIDTH 32 + #define DMA8_CONBLK_AD_RESET 0000000000 + #define DMA8_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA8_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA8_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA8_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA8_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA8_TI HW_REGISTER_RO( 0x7ee05008 ) + #define DMA8_TI_MASK 0x07fffffb + #define DMA8_TI_WIDTH 27 + #define DMA8_TI_NO_WIDE_BURSTS_BITS 26:26 + #define DMA8_TI_NO_WIDE_BURSTS_SET 0x04000000 + #define DMA8_TI_NO_WIDE_BURSTS_CLR 0xfbffffff + #define DMA8_TI_NO_WIDE_BURSTS_MSB 26 + #define DMA8_TI_NO_WIDE_BURSTS_LSB 26 + #define DMA8_TI_WAITS_BITS 25:21 + #define DMA8_TI_WAITS_SET 0x03e00000 + #define DMA8_TI_WAITS_CLR 0xfc1fffff + #define DMA8_TI_WAITS_MSB 25 + #define DMA8_TI_WAITS_LSB 21 + #define DMA8_TI_PERMAP_BITS 20:16 + #define DMA8_TI_PERMAP_SET 0x001f0000 + #define DMA8_TI_PERMAP_CLR 0xffe0ffff + #define DMA8_TI_PERMAP_MSB 20 + #define DMA8_TI_PERMAP_LSB 16 + #define DMA8_TI_BURST_LENGTH_BITS 15:12 + #define DMA8_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA8_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA8_TI_BURST_LENGTH_MSB 15 + #define DMA8_TI_BURST_LENGTH_LSB 12 + #define DMA8_TI_SRC_IGNORE_BITS 11:11 + #define DMA8_TI_SRC_IGNORE_SET 0x00000800 + #define DMA8_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA8_TI_SRC_IGNORE_MSB 11 + #define DMA8_TI_SRC_IGNORE_LSB 11 + #define DMA8_TI_SRC_DREQ_BITS 10:10 + #define DMA8_TI_SRC_DREQ_SET 0x00000400 + #define DMA8_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA8_TI_SRC_DREQ_MSB 10 + #define DMA8_TI_SRC_DREQ_LSB 10 + #define DMA8_TI_SRC_WIDTH_BITS 9:9 + #define DMA8_TI_SRC_WIDTH_SET 0x00000200 + #define DMA8_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA8_TI_SRC_WIDTH_MSB 9 + #define DMA8_TI_SRC_WIDTH_LSB 9 + #define DMA8_TI_SRC_INC_BITS 8:8 + #define DMA8_TI_SRC_INC_SET 0x00000100 + #define DMA8_TI_SRC_INC_CLR 0xfffffeff + #define DMA8_TI_SRC_INC_MSB 8 + #define DMA8_TI_SRC_INC_LSB 8 + #define DMA8_TI_DEST_IGNORE_BITS 7:7 + #define DMA8_TI_DEST_IGNORE_SET 0x00000080 + #define DMA8_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA8_TI_DEST_IGNORE_MSB 7 + #define DMA8_TI_DEST_IGNORE_LSB 7 + #define DMA8_TI_DEST_DREQ_BITS 6:6 + #define DMA8_TI_DEST_DREQ_SET 0x00000040 + #define DMA8_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA8_TI_DEST_DREQ_MSB 6 + #define DMA8_TI_DEST_DREQ_LSB 6 + #define DMA8_TI_DEST_WIDTH_BITS 5:5 + #define DMA8_TI_DEST_WIDTH_SET 0x00000020 + #define DMA8_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA8_TI_DEST_WIDTH_MSB 5 + #define DMA8_TI_DEST_WIDTH_LSB 5 + #define DMA8_TI_DEST_INC_BITS 4:4 + #define DMA8_TI_DEST_INC_SET 0x00000010 + #define DMA8_TI_DEST_INC_CLR 0xffffffef + #define DMA8_TI_DEST_INC_MSB 4 + #define DMA8_TI_DEST_INC_LSB 4 + #define DMA8_TI_WAIT_RESP_BITS 3:3 + #define DMA8_TI_WAIT_RESP_SET 0x00000008 + #define DMA8_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA8_TI_WAIT_RESP_MSB 3 + #define DMA8_TI_WAIT_RESP_LSB 3 + #define DMA8_TI_TDMODE_BITS 1:1 + #define DMA8_TI_TDMODE_SET 0x00000002 + #define DMA8_TI_TDMODE_CLR 0xfffffffd + #define DMA8_TI_TDMODE_MSB 1 + #define DMA8_TI_TDMODE_LSB 1 + #define DMA8_TI_INTEN_BITS 0:0 + #define DMA8_TI_INTEN_SET 0x00000001 + #define DMA8_TI_INTEN_CLR 0xfffffffe + #define DMA8_TI_INTEN_MSB 0 + #define DMA8_TI_INTEN_LSB 0 +#define DMA8_SOURCE_AD HW_REGISTER_RO( 0x7ee0500c ) + #define DMA8_SOURCE_AD_MASK 0xffffffff + #define DMA8_SOURCE_AD_WIDTH 32 + #define DMA8_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA8_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA8_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA8_SOURCE_AD_S_ADDR_MSB 31 + #define DMA8_SOURCE_AD_S_ADDR_LSB 0 +#define DMA8_DEST_AD HW_REGISTER_RO( 0x7ee05010 ) + #define DMA8_DEST_AD_MASK 0xffffffff + #define DMA8_DEST_AD_WIDTH 32 + #define DMA8_DEST_AD_D_ADDR_BITS 31:0 + #define DMA8_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA8_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA8_DEST_AD_D_ADDR_MSB 31 + #define DMA8_DEST_AD_D_ADDR_LSB 0 +#define DMA8_TXFR_LEN HW_REGISTER_RO( 0x7ee05014 ) + #define DMA8_TXFR_LEN_MASK 0x3fffffff + #define DMA8_TXFR_LEN_WIDTH 30 + #define DMA8_TXFR_LEN_ylength_BITS 29:16 + #define DMA8_TXFR_LEN_ylength_SET 0x3fff0000 + #define DMA8_TXFR_LEN_ylength_CLR 0xc000ffff + #define DMA8_TXFR_LEN_ylength_MSB 29 + #define DMA8_TXFR_LEN_ylength_LSB 16 + #define DMA8_TXFR_LEN_xlength_BITS 15:0 + #define DMA8_TXFR_LEN_xlength_SET 0x0000ffff + #define DMA8_TXFR_LEN_xlength_CLR 0xffff0000 + #define DMA8_TXFR_LEN_xlength_MSB 15 + #define DMA8_TXFR_LEN_xlength_LSB 0 +#define DMA8_STRIDE HW_REGISTER_RO( 0x7ee05018 ) + #define DMA8_STRIDE_MASK 0xffffffff + #define DMA8_STRIDE_WIDTH 32 + #define DMA8_STRIDE_D_STRIDE_BITS 31:16 + #define DMA8_STRIDE_D_STRIDE_SET 0xffff0000 + #define DMA8_STRIDE_D_STRIDE_CLR 0x0000ffff + #define DMA8_STRIDE_D_STRIDE_MSB 31 + #define DMA8_STRIDE_D_STRIDE_LSB 16 + #define DMA8_STRIDE_S_STRIDE_BITS 15:0 + #define DMA8_STRIDE_S_STRIDE_SET 0x0000ffff + #define DMA8_STRIDE_S_STRIDE_CLR 0xffff0000 + #define DMA8_STRIDE_S_STRIDE_MSB 15 + #define DMA8_STRIDE_S_STRIDE_LSB 0 +#define DMA8_NEXTCONBK HW_REGISTER_RO( 0x7ee0501c ) + #define DMA8_NEXTCONBK_MASK 0xffffffe0 + #define DMA8_NEXTCONBK_WIDTH 32 +#define DMA8_DEBUG HW_REGISTER_RW( 0x7ee05020 ) + #define DMA8_DEBUG_MASK 0x0ffffff7 + #define DMA8_DEBUG_WIDTH 28 + #define DMA8_DEBUG_RESET 0000000000 + #define DMA8_DEBUG_VERSION_BITS 27:25 + #define DMA8_DEBUG_VERSION_SET 0x0e000000 + #define DMA8_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA8_DEBUG_VERSION_MSB 27 + #define DMA8_DEBUG_VERSION_LSB 25 + #define DMA8_DEBUG_DMA_STATE_BITS 24:16 + #define DMA8_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA8_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA8_DEBUG_DMA_STATE_MSB 24 + #define DMA8_DEBUG_DMA_STATE_LSB 16 + #define DMA8_DEBUG_DMA_ID_BITS 15:8 + #define DMA8_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA8_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA8_DEBUG_DMA_ID_MSB 15 + #define DMA8_DEBUG_DMA_ID_LSB 8 + #define DMA8_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA8_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA8_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA8_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA8_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA8_DEBUG_READ_ERROR_BITS 2:2 + #define DMA8_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA8_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA8_DEBUG_READ_ERROR_MSB 2 + #define DMA8_DEBUG_READ_ERROR_LSB 2 + #define DMA8_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA8_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA8_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA8_DEBUG_FIFO_ERROR_MSB 1 + #define DMA8_DEBUG_FIFO_ERROR_LSB 1 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite10.h b/bcm2708_chip/axi_dma_lite10.h new file mode 100755 index 0000000..5460f81 --- /dev/null +++ b/bcm2708_chip/axi_dma_lite10.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA10_BASE 0x7e007a00 +#define DMA10_CS HW_REGISTER_RW( 0x7e007a00 ) + #define DMA10_CS_MASK 0xf0ff017f + #define DMA10_CS_WIDTH 32 + #define DMA10_CS_RESET 0000000000 + #define DMA10_CS_RESET_BITS 31:31 + #define DMA10_CS_RESET_SET 0x80000000 + #define DMA10_CS_RESET_CLR 0x7fffffff + #define DMA10_CS_RESET_MSB 31 + #define DMA10_CS_RESET_LSB 31 + #define DMA10_CS_ABORT_BITS 30:30 + #define DMA10_CS_ABORT_SET 0x40000000 + #define DMA10_CS_ABORT_CLR 0xbfffffff + #define DMA10_CS_ABORT_MSB 30 + #define DMA10_CS_ABORT_LSB 30 + #define DMA10_CS_DISDEBUG_BITS 29:29 + #define DMA10_CS_DISDEBUG_SET 0x20000000 + #define DMA10_CS_DISDEBUG_CLR 0xdfffffff + #define DMA10_CS_DISDEBUG_MSB 29 + #define DMA10_CS_DISDEBUG_LSB 29 + #define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA10_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA10_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA10_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA10_CS_PANIC_PRIORITY_MSB 23 + #define DMA10_CS_PANIC_PRIORITY_LSB 20 + #define DMA10_CS_PRIORITY_BITS 19:16 + #define DMA10_CS_PRIORITY_SET 0x000f0000 + #define DMA10_CS_PRIORITY_CLR 0xfff0ffff + #define DMA10_CS_PRIORITY_MSB 19 + #define DMA10_CS_PRIORITY_LSB 16 + #define DMA10_CS_ERROR_BITS 8:8 + #define DMA10_CS_ERROR_SET 0x00000100 + #define DMA10_CS_ERROR_CLR 0xfffffeff + #define DMA10_CS_ERROR_MSB 8 + #define DMA10_CS_ERROR_LSB 8 + #define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA10_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA10_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA10_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA10_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA10_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA10_CS_PAUSED_BITS 4:4 + #define DMA10_CS_PAUSED_SET 0x00000010 + #define DMA10_CS_PAUSED_CLR 0xffffffef + #define DMA10_CS_PAUSED_MSB 4 + #define DMA10_CS_PAUSED_LSB 4 + #define DMA10_CS_DREQ_BITS 3:3 + #define DMA10_CS_DREQ_SET 0x00000008 + #define DMA10_CS_DREQ_CLR 0xfffffff7 + #define DMA10_CS_DREQ_MSB 3 + #define DMA10_CS_DREQ_LSB 3 + #define DMA10_CS_INT_BITS 2:2 + #define DMA10_CS_INT_SET 0x00000004 + #define DMA10_CS_INT_CLR 0xfffffffb + #define DMA10_CS_INT_MSB 2 + #define DMA10_CS_INT_LSB 2 + #define DMA10_CS_END_BITS 1:1 + #define DMA10_CS_END_SET 0x00000002 + #define DMA10_CS_END_CLR 0xfffffffd + #define DMA10_CS_END_MSB 1 + #define DMA10_CS_END_LSB 1 + #define DMA10_CS_ACTIVE_BITS 0:0 + #define DMA10_CS_ACTIVE_SET 0x00000001 + #define DMA10_CS_ACTIVE_CLR 0xfffffffe + #define DMA10_CS_ACTIVE_MSB 0 + #define DMA10_CS_ACTIVE_LSB 0 +#define DMA10_CONBLK_AD HW_REGISTER_RW( 0x7e007a04 ) + #define DMA10_CONBLK_AD_MASK 0xffffffe0 + #define DMA10_CONBLK_AD_WIDTH 32 + #define DMA10_CONBLK_AD_RESET 0000000000 + #define DMA10_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA10_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA10_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA10_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA10_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA10_TI HW_REGISTER_RO( 0x7e007a08 ) + #define DMA10_TI_MASK 0x03fffff9 + #define DMA10_TI_WIDTH 26 + #define DMA10_TI_WAITS_BITS 25:21 + #define DMA10_TI_WAITS_SET 0x03e00000 + #define DMA10_TI_WAITS_CLR 0xfc1fffff + #define DMA10_TI_WAITS_MSB 25 + #define DMA10_TI_WAITS_LSB 21 + #define DMA10_TI_PERMAP_BITS 20:16 + #define DMA10_TI_PERMAP_SET 0x001f0000 + #define DMA10_TI_PERMAP_CLR 0xffe0ffff + #define DMA10_TI_PERMAP_MSB 20 + #define DMA10_TI_PERMAP_LSB 16 + #define DMA10_TI_BURST_LENGTH_BITS 15:12 + #define DMA10_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA10_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA10_TI_BURST_LENGTH_MSB 15 + #define DMA10_TI_BURST_LENGTH_LSB 12 + #define DMA10_TI_SRC_IGNORE_BITS 11:11 + #define DMA10_TI_SRC_IGNORE_SET 0x00000800 + #define DMA10_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA10_TI_SRC_IGNORE_MSB 11 + #define DMA10_TI_SRC_IGNORE_LSB 11 + #define DMA10_TI_SRC_DREQ_BITS 10:10 + #define DMA10_TI_SRC_DREQ_SET 0x00000400 + #define DMA10_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA10_TI_SRC_DREQ_MSB 10 + #define DMA10_TI_SRC_DREQ_LSB 10 + #define DMA10_TI_SRC_WIDTH_BITS 9:9 + #define DMA10_TI_SRC_WIDTH_SET 0x00000200 + #define DMA10_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA10_TI_SRC_WIDTH_MSB 9 + #define DMA10_TI_SRC_WIDTH_LSB 9 + #define DMA10_TI_SRC_INC_BITS 8:8 + #define DMA10_TI_SRC_INC_SET 0x00000100 + #define DMA10_TI_SRC_INC_CLR 0xfffffeff + #define DMA10_TI_SRC_INC_MSB 8 + #define DMA10_TI_SRC_INC_LSB 8 + #define DMA10_TI_DEST_IGNORE_BITS 7:7 + #define DMA10_TI_DEST_IGNORE_SET 0x00000080 + #define DMA10_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA10_TI_DEST_IGNORE_MSB 7 + #define DMA10_TI_DEST_IGNORE_LSB 7 + #define DMA10_TI_DEST_DREQ_BITS 6:6 + #define DMA10_TI_DEST_DREQ_SET 0x00000040 + #define DMA10_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA10_TI_DEST_DREQ_MSB 6 + #define DMA10_TI_DEST_DREQ_LSB 6 + #define DMA10_TI_DEST_WIDTH_BITS 5:5 + #define DMA10_TI_DEST_WIDTH_SET 0x00000020 + #define DMA10_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA10_TI_DEST_WIDTH_MSB 5 + #define DMA10_TI_DEST_WIDTH_LSB 5 + #define DMA10_TI_DEST_INC_BITS 4:4 + #define DMA10_TI_DEST_INC_SET 0x00000010 + #define DMA10_TI_DEST_INC_CLR 0xffffffef + #define DMA10_TI_DEST_INC_MSB 4 + #define DMA10_TI_DEST_INC_LSB 4 + #define DMA10_TI_WAIT_RESP_BITS 3:3 + #define DMA10_TI_WAIT_RESP_SET 0x00000008 + #define DMA10_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA10_TI_WAIT_RESP_MSB 3 + #define DMA10_TI_WAIT_RESP_LSB 3 + #define DMA10_TI_INTEN_BITS 0:0 + #define DMA10_TI_INTEN_SET 0x00000001 + #define DMA10_TI_INTEN_CLR 0xfffffffe + #define DMA10_TI_INTEN_MSB 0 + #define DMA10_TI_INTEN_LSB 0 +#define DMA10_SOURCE_AD HW_REGISTER_RO( 0x7e007a0c ) + #define DMA10_SOURCE_AD_MASK 0xffffffff + #define DMA10_SOURCE_AD_WIDTH 32 + #define DMA10_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA10_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA10_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA10_SOURCE_AD_S_ADDR_MSB 31 + #define DMA10_SOURCE_AD_S_ADDR_LSB 0 +#define DMA10_DEST_AD HW_REGISTER_RO( 0x7e007a10 ) + #define DMA10_DEST_AD_MASK 0xffffffff + #define DMA10_DEST_AD_WIDTH 32 + #define DMA10_DEST_AD_D_ADDR_BITS 31:0 + #define DMA10_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA10_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA10_DEST_AD_D_ADDR_MSB 31 + #define DMA10_DEST_AD_D_ADDR_LSB 0 +#define DMA10_TXFR_LEN HW_REGISTER_RO( 0x7e007a14 ) + #define DMA10_TXFR_LEN_MASK 0x0000ffff + #define DMA10_TXFR_LEN_WIDTH 16 + #define DMA10_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA10_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA10_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA10_TXFR_LEN_XLENGTH_MSB 15 + #define DMA10_TXFR_LEN_XLENGTH_LSB 0 +#define DMA10_NEXTCONBK HW_REGISTER_RO( 0x7e007a1c ) + #define DMA10_NEXTCONBK_MASK 0xffffffe0 + #define DMA10_NEXTCONBK_WIDTH 32 + #define DMA10_NEXTCONBK_ADDR_BITS 31:5 + #define DMA10_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA10_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA10_NEXTCONBK_ADDR_MSB 31 + #define DMA10_NEXTCONBK_ADDR_LSB 5 +#define DMA10_DEBUG HW_REGISTER_RW( 0x7e007a20 ) + #define DMA10_DEBUG_MASK 0x1ffffff7 + #define DMA10_DEBUG_WIDTH 29 + #define DMA10_DEBUG_RESET 0000000000 + #define DMA10_DEBUG_LITE_BITS 28:28 + #define DMA10_DEBUG_LITE_SET 0x10000000 + #define DMA10_DEBUG_LITE_CLR 0xefffffff + #define DMA10_DEBUG_LITE_MSB 28 + #define DMA10_DEBUG_LITE_LSB 28 + #define DMA10_DEBUG_VERSION_BITS 27:25 + #define DMA10_DEBUG_VERSION_SET 0x0e000000 + #define DMA10_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA10_DEBUG_VERSION_MSB 27 + #define DMA10_DEBUG_VERSION_LSB 25 + #define DMA10_DEBUG_DMA_STATE_BITS 24:16 + #define DMA10_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA10_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA10_DEBUG_DMA_STATE_MSB 24 + #define DMA10_DEBUG_DMA_STATE_LSB 16 + #define DMA10_DEBUG_DMA_ID_BITS 15:8 + #define DMA10_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA10_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA10_DEBUG_DMA_ID_MSB 15 + #define DMA10_DEBUG_DMA_ID_LSB 8 + #define DMA10_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA10_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA10_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA10_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA10_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA10_DEBUG_READ_ERROR_BITS 2:2 + #define DMA10_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA10_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA10_DEBUG_READ_ERROR_MSB 2 + #define DMA10_DEBUG_READ_ERROR_LSB 2 + #define DMA10_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA10_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA10_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA10_DEBUG_FIFO_ERROR_MSB 1 + #define DMA10_DEBUG_FIFO_ERROR_LSB 1 + #define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite11.h b/bcm2708_chip/axi_dma_lite11.h new file mode 100755 index 0000000..66fa4ec --- /dev/null +++ b/bcm2708_chip/axi_dma_lite11.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA11_BASE 0x7e007b00 +#define DMA11_CS HW_REGISTER_RW( 0x7e007b00 ) + #define DMA11_CS_MASK 0xf0ff017f + #define DMA11_CS_WIDTH 32 + #define DMA11_CS_RESET 0000000000 + #define DMA11_CS_RESET_BITS 31:31 + #define DMA11_CS_RESET_SET 0x80000000 + #define DMA11_CS_RESET_CLR 0x7fffffff + #define DMA11_CS_RESET_MSB 31 + #define DMA11_CS_RESET_LSB 31 + #define DMA11_CS_ABORT_BITS 30:30 + #define DMA11_CS_ABORT_SET 0x40000000 + #define DMA11_CS_ABORT_CLR 0xbfffffff + #define DMA11_CS_ABORT_MSB 30 + #define DMA11_CS_ABORT_LSB 30 + #define DMA11_CS_DISDEBUG_BITS 29:29 + #define DMA11_CS_DISDEBUG_SET 0x20000000 + #define DMA11_CS_DISDEBUG_CLR 0xdfffffff + #define DMA11_CS_DISDEBUG_MSB 29 + #define DMA11_CS_DISDEBUG_LSB 29 + #define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA11_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA11_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA11_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA11_CS_PANIC_PRIORITY_MSB 23 + #define DMA11_CS_PANIC_PRIORITY_LSB 20 + #define DMA11_CS_PRIORITY_BITS 19:16 + #define DMA11_CS_PRIORITY_SET 0x000f0000 + #define DMA11_CS_PRIORITY_CLR 0xfff0ffff + #define DMA11_CS_PRIORITY_MSB 19 + #define DMA11_CS_PRIORITY_LSB 16 + #define DMA11_CS_ERROR_BITS 8:8 + #define DMA11_CS_ERROR_SET 0x00000100 + #define DMA11_CS_ERROR_CLR 0xfffffeff + #define DMA11_CS_ERROR_MSB 8 + #define DMA11_CS_ERROR_LSB 8 + #define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA11_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA11_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA11_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA11_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA11_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA11_CS_PAUSED_BITS 4:4 + #define DMA11_CS_PAUSED_SET 0x00000010 + #define DMA11_CS_PAUSED_CLR 0xffffffef + #define DMA11_CS_PAUSED_MSB 4 + #define DMA11_CS_PAUSED_LSB 4 + #define DMA11_CS_DREQ_BITS 3:3 + #define DMA11_CS_DREQ_SET 0x00000008 + #define DMA11_CS_DREQ_CLR 0xfffffff7 + #define DMA11_CS_DREQ_MSB 3 + #define DMA11_CS_DREQ_LSB 3 + #define DMA11_CS_INT_BITS 2:2 + #define DMA11_CS_INT_SET 0x00000004 + #define DMA11_CS_INT_CLR 0xfffffffb + #define DMA11_CS_INT_MSB 2 + #define DMA11_CS_INT_LSB 2 + #define DMA11_CS_END_BITS 1:1 + #define DMA11_CS_END_SET 0x00000002 + #define DMA11_CS_END_CLR 0xfffffffd + #define DMA11_CS_END_MSB 1 + #define DMA11_CS_END_LSB 1 + #define DMA11_CS_ACTIVE_BITS 0:0 + #define DMA11_CS_ACTIVE_SET 0x00000001 + #define DMA11_CS_ACTIVE_CLR 0xfffffffe + #define DMA11_CS_ACTIVE_MSB 0 + #define DMA11_CS_ACTIVE_LSB 0 +#define DMA11_CONBLK_AD HW_REGISTER_RW( 0x7e007b04 ) + #define DMA11_CONBLK_AD_MASK 0xffffffe0 + #define DMA11_CONBLK_AD_WIDTH 32 + #define DMA11_CONBLK_AD_RESET 0000000000 + #define DMA11_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA11_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA11_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA11_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA11_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA11_TI HW_REGISTER_RO( 0x7e007b08 ) + #define DMA11_TI_MASK 0x03fffff9 + #define DMA11_TI_WIDTH 26 + #define DMA11_TI_WAITS_BITS 25:21 + #define DMA11_TI_WAITS_SET 0x03e00000 + #define DMA11_TI_WAITS_CLR 0xfc1fffff + #define DMA11_TI_WAITS_MSB 25 + #define DMA11_TI_WAITS_LSB 21 + #define DMA11_TI_PERMAP_BITS 20:16 + #define DMA11_TI_PERMAP_SET 0x001f0000 + #define DMA11_TI_PERMAP_CLR 0xffe0ffff + #define DMA11_TI_PERMAP_MSB 20 + #define DMA11_TI_PERMAP_LSB 16 + #define DMA11_TI_BURST_LENGTH_BITS 15:12 + #define DMA11_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA11_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA11_TI_BURST_LENGTH_MSB 15 + #define DMA11_TI_BURST_LENGTH_LSB 12 + #define DMA11_TI_SRC_IGNORE_BITS 11:11 + #define DMA11_TI_SRC_IGNORE_SET 0x00000800 + #define DMA11_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA11_TI_SRC_IGNORE_MSB 11 + #define DMA11_TI_SRC_IGNORE_LSB 11 + #define DMA11_TI_SRC_DREQ_BITS 10:10 + #define DMA11_TI_SRC_DREQ_SET 0x00000400 + #define DMA11_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA11_TI_SRC_DREQ_MSB 10 + #define DMA11_TI_SRC_DREQ_LSB 10 + #define DMA11_TI_SRC_WIDTH_BITS 9:9 + #define DMA11_TI_SRC_WIDTH_SET 0x00000200 + #define DMA11_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA11_TI_SRC_WIDTH_MSB 9 + #define DMA11_TI_SRC_WIDTH_LSB 9 + #define DMA11_TI_SRC_INC_BITS 8:8 + #define DMA11_TI_SRC_INC_SET 0x00000100 + #define DMA11_TI_SRC_INC_CLR 0xfffffeff + #define DMA11_TI_SRC_INC_MSB 8 + #define DMA11_TI_SRC_INC_LSB 8 + #define DMA11_TI_DEST_IGNORE_BITS 7:7 + #define DMA11_TI_DEST_IGNORE_SET 0x00000080 + #define DMA11_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA11_TI_DEST_IGNORE_MSB 7 + #define DMA11_TI_DEST_IGNORE_LSB 7 + #define DMA11_TI_DEST_DREQ_BITS 6:6 + #define DMA11_TI_DEST_DREQ_SET 0x00000040 + #define DMA11_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA11_TI_DEST_DREQ_MSB 6 + #define DMA11_TI_DEST_DREQ_LSB 6 + #define DMA11_TI_DEST_WIDTH_BITS 5:5 + #define DMA11_TI_DEST_WIDTH_SET 0x00000020 + #define DMA11_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA11_TI_DEST_WIDTH_MSB 5 + #define DMA11_TI_DEST_WIDTH_LSB 5 + #define DMA11_TI_DEST_INC_BITS 4:4 + #define DMA11_TI_DEST_INC_SET 0x00000010 + #define DMA11_TI_DEST_INC_CLR 0xffffffef + #define DMA11_TI_DEST_INC_MSB 4 + #define DMA11_TI_DEST_INC_LSB 4 + #define DMA11_TI_WAIT_RESP_BITS 3:3 + #define DMA11_TI_WAIT_RESP_SET 0x00000008 + #define DMA11_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA11_TI_WAIT_RESP_MSB 3 + #define DMA11_TI_WAIT_RESP_LSB 3 + #define DMA11_TI_INTEN_BITS 0:0 + #define DMA11_TI_INTEN_SET 0x00000001 + #define DMA11_TI_INTEN_CLR 0xfffffffe + #define DMA11_TI_INTEN_MSB 0 + #define DMA11_TI_INTEN_LSB 0 +#define DMA11_SOURCE_AD HW_REGISTER_RO( 0x7e007b0c ) + #define DMA11_SOURCE_AD_MASK 0xffffffff + #define DMA11_SOURCE_AD_WIDTH 32 + #define DMA11_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA11_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA11_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA11_SOURCE_AD_S_ADDR_MSB 31 + #define DMA11_SOURCE_AD_S_ADDR_LSB 0 +#define DMA11_DEST_AD HW_REGISTER_RO( 0x7e007b10 ) + #define DMA11_DEST_AD_MASK 0xffffffff + #define DMA11_DEST_AD_WIDTH 32 + #define DMA11_DEST_AD_D_ADDR_BITS 31:0 + #define DMA11_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA11_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA11_DEST_AD_D_ADDR_MSB 31 + #define DMA11_DEST_AD_D_ADDR_LSB 0 +#define DMA11_TXFR_LEN HW_REGISTER_RO( 0x7e007b14 ) + #define DMA11_TXFR_LEN_MASK 0x0000ffff + #define DMA11_TXFR_LEN_WIDTH 16 + #define DMA11_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA11_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA11_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA11_TXFR_LEN_XLENGTH_MSB 15 + #define DMA11_TXFR_LEN_XLENGTH_LSB 0 +#define DMA11_NEXTCONBK HW_REGISTER_RO( 0x7e007b1c ) + #define DMA11_NEXTCONBK_MASK 0xffffffe0 + #define DMA11_NEXTCONBK_WIDTH 32 + #define DMA11_NEXTCONBK_ADDR_BITS 31:5 + #define DMA11_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA11_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA11_NEXTCONBK_ADDR_MSB 31 + #define DMA11_NEXTCONBK_ADDR_LSB 5 +#define DMA11_DEBUG HW_REGISTER_RW( 0x7e007b20 ) + #define DMA11_DEBUG_MASK 0x1ffffff7 + #define DMA11_DEBUG_WIDTH 29 + #define DMA11_DEBUG_RESET 0000000000 + #define DMA11_DEBUG_LITE_BITS 28:28 + #define DMA11_DEBUG_LITE_SET 0x10000000 + #define DMA11_DEBUG_LITE_CLR 0xefffffff + #define DMA11_DEBUG_LITE_MSB 28 + #define DMA11_DEBUG_LITE_LSB 28 + #define DMA11_DEBUG_VERSION_BITS 27:25 + #define DMA11_DEBUG_VERSION_SET 0x0e000000 + #define DMA11_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA11_DEBUG_VERSION_MSB 27 + #define DMA11_DEBUG_VERSION_LSB 25 + #define DMA11_DEBUG_DMA_STATE_BITS 24:16 + #define DMA11_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA11_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA11_DEBUG_DMA_STATE_MSB 24 + #define DMA11_DEBUG_DMA_STATE_LSB 16 + #define DMA11_DEBUG_DMA_ID_BITS 15:8 + #define DMA11_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA11_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA11_DEBUG_DMA_ID_MSB 15 + #define DMA11_DEBUG_DMA_ID_LSB 8 + #define DMA11_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA11_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA11_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA11_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA11_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA11_DEBUG_READ_ERROR_BITS 2:2 + #define DMA11_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA11_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA11_DEBUG_READ_ERROR_MSB 2 + #define DMA11_DEBUG_READ_ERROR_LSB 2 + #define DMA11_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA11_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA11_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA11_DEBUG_FIFO_ERROR_MSB 1 + #define DMA11_DEBUG_FIFO_ERROR_LSB 1 + #define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite12.h b/bcm2708_chip/axi_dma_lite12.h new file mode 100755 index 0000000..85aebb2 --- /dev/null +++ b/bcm2708_chip/axi_dma_lite12.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA12_BASE 0x7e007c00 +#define DMA12_CS HW_REGISTER_RW( 0x7e007c00 ) + #define DMA12_CS_MASK 0xf0ff017f + #define DMA12_CS_WIDTH 32 + #define DMA12_CS_RESET 0000000000 + #define DMA12_CS_RESET_BITS 31:31 + #define DMA12_CS_RESET_SET 0x80000000 + #define DMA12_CS_RESET_CLR 0x7fffffff + #define DMA12_CS_RESET_MSB 31 + #define DMA12_CS_RESET_LSB 31 + #define DMA12_CS_ABORT_BITS 30:30 + #define DMA12_CS_ABORT_SET 0x40000000 + #define DMA12_CS_ABORT_CLR 0xbfffffff + #define DMA12_CS_ABORT_MSB 30 + #define DMA12_CS_ABORT_LSB 30 + #define DMA12_CS_DISDEBUG_BITS 29:29 + #define DMA12_CS_DISDEBUG_SET 0x20000000 + #define DMA12_CS_DISDEBUG_CLR 0xdfffffff + #define DMA12_CS_DISDEBUG_MSB 29 + #define DMA12_CS_DISDEBUG_LSB 29 + #define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA12_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA12_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA12_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA12_CS_PANIC_PRIORITY_MSB 23 + #define DMA12_CS_PANIC_PRIORITY_LSB 20 + #define DMA12_CS_PRIORITY_BITS 19:16 + #define DMA12_CS_PRIORITY_SET 0x000f0000 + #define DMA12_CS_PRIORITY_CLR 0xfff0ffff + #define DMA12_CS_PRIORITY_MSB 19 + #define DMA12_CS_PRIORITY_LSB 16 + #define DMA12_CS_ERROR_BITS 8:8 + #define DMA12_CS_ERROR_SET 0x00000100 + #define DMA12_CS_ERROR_CLR 0xfffffeff + #define DMA12_CS_ERROR_MSB 8 + #define DMA12_CS_ERROR_LSB 8 + #define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA12_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA12_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA12_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA12_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA12_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA12_CS_PAUSED_BITS 4:4 + #define DMA12_CS_PAUSED_SET 0x00000010 + #define DMA12_CS_PAUSED_CLR 0xffffffef + #define DMA12_CS_PAUSED_MSB 4 + #define DMA12_CS_PAUSED_LSB 4 + #define DMA12_CS_DREQ_BITS 3:3 + #define DMA12_CS_DREQ_SET 0x00000008 + #define DMA12_CS_DREQ_CLR 0xfffffff7 + #define DMA12_CS_DREQ_MSB 3 + #define DMA12_CS_DREQ_LSB 3 + #define DMA12_CS_INT_BITS 2:2 + #define DMA12_CS_INT_SET 0x00000004 + #define DMA12_CS_INT_CLR 0xfffffffb + #define DMA12_CS_INT_MSB 2 + #define DMA12_CS_INT_LSB 2 + #define DMA12_CS_END_BITS 1:1 + #define DMA12_CS_END_SET 0x00000002 + #define DMA12_CS_END_CLR 0xfffffffd + #define DMA12_CS_END_MSB 1 + #define DMA12_CS_END_LSB 1 + #define DMA12_CS_ACTIVE_BITS 0:0 + #define DMA12_CS_ACTIVE_SET 0x00000001 + #define DMA12_CS_ACTIVE_CLR 0xfffffffe + #define DMA12_CS_ACTIVE_MSB 0 + #define DMA12_CS_ACTIVE_LSB 0 +#define DMA12_CONBLK_AD HW_REGISTER_RW( 0x7e007c04 ) + #define DMA12_CONBLK_AD_MASK 0xffffffe0 + #define DMA12_CONBLK_AD_WIDTH 32 + #define DMA12_CONBLK_AD_RESET 0000000000 + #define DMA12_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA12_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA12_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA12_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA12_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA12_TI HW_REGISTER_RO( 0x7e007c08 ) + #define DMA12_TI_MASK 0x03fffff9 + #define DMA12_TI_WIDTH 26 + #define DMA12_TI_WAITS_BITS 25:21 + #define DMA12_TI_WAITS_SET 0x03e00000 + #define DMA12_TI_WAITS_CLR 0xfc1fffff + #define DMA12_TI_WAITS_MSB 25 + #define DMA12_TI_WAITS_LSB 21 + #define DMA12_TI_PERMAP_BITS 20:16 + #define DMA12_TI_PERMAP_SET 0x001f0000 + #define DMA12_TI_PERMAP_CLR 0xffe0ffff + #define DMA12_TI_PERMAP_MSB 20 + #define DMA12_TI_PERMAP_LSB 16 + #define DMA12_TI_BURST_LENGTH_BITS 15:12 + #define DMA12_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA12_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA12_TI_BURST_LENGTH_MSB 15 + #define DMA12_TI_BURST_LENGTH_LSB 12 + #define DMA12_TI_SRC_IGNORE_BITS 11:11 + #define DMA12_TI_SRC_IGNORE_SET 0x00000800 + #define DMA12_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA12_TI_SRC_IGNORE_MSB 11 + #define DMA12_TI_SRC_IGNORE_LSB 11 + #define DMA12_TI_SRC_DREQ_BITS 10:10 + #define DMA12_TI_SRC_DREQ_SET 0x00000400 + #define DMA12_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA12_TI_SRC_DREQ_MSB 10 + #define DMA12_TI_SRC_DREQ_LSB 10 + #define DMA12_TI_SRC_WIDTH_BITS 9:9 + #define DMA12_TI_SRC_WIDTH_SET 0x00000200 + #define DMA12_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA12_TI_SRC_WIDTH_MSB 9 + #define DMA12_TI_SRC_WIDTH_LSB 9 + #define DMA12_TI_SRC_INC_BITS 8:8 + #define DMA12_TI_SRC_INC_SET 0x00000100 + #define DMA12_TI_SRC_INC_CLR 0xfffffeff + #define DMA12_TI_SRC_INC_MSB 8 + #define DMA12_TI_SRC_INC_LSB 8 + #define DMA12_TI_DEST_IGNORE_BITS 7:7 + #define DMA12_TI_DEST_IGNORE_SET 0x00000080 + #define DMA12_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA12_TI_DEST_IGNORE_MSB 7 + #define DMA12_TI_DEST_IGNORE_LSB 7 + #define DMA12_TI_DEST_DREQ_BITS 6:6 + #define DMA12_TI_DEST_DREQ_SET 0x00000040 + #define DMA12_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA12_TI_DEST_DREQ_MSB 6 + #define DMA12_TI_DEST_DREQ_LSB 6 + #define DMA12_TI_DEST_WIDTH_BITS 5:5 + #define DMA12_TI_DEST_WIDTH_SET 0x00000020 + #define DMA12_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA12_TI_DEST_WIDTH_MSB 5 + #define DMA12_TI_DEST_WIDTH_LSB 5 + #define DMA12_TI_DEST_INC_BITS 4:4 + #define DMA12_TI_DEST_INC_SET 0x00000010 + #define DMA12_TI_DEST_INC_CLR 0xffffffef + #define DMA12_TI_DEST_INC_MSB 4 + #define DMA12_TI_DEST_INC_LSB 4 + #define DMA12_TI_WAIT_RESP_BITS 3:3 + #define DMA12_TI_WAIT_RESP_SET 0x00000008 + #define DMA12_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA12_TI_WAIT_RESP_MSB 3 + #define DMA12_TI_WAIT_RESP_LSB 3 + #define DMA12_TI_INTEN_BITS 0:0 + #define DMA12_TI_INTEN_SET 0x00000001 + #define DMA12_TI_INTEN_CLR 0xfffffffe + #define DMA12_TI_INTEN_MSB 0 + #define DMA12_TI_INTEN_LSB 0 +#define DMA12_SOURCE_AD HW_REGISTER_RO( 0x7e007c0c ) + #define DMA12_SOURCE_AD_MASK 0xffffffff + #define DMA12_SOURCE_AD_WIDTH 32 + #define DMA12_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA12_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA12_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA12_SOURCE_AD_S_ADDR_MSB 31 + #define DMA12_SOURCE_AD_S_ADDR_LSB 0 +#define DMA12_DEST_AD HW_REGISTER_RO( 0x7e007c10 ) + #define DMA12_DEST_AD_MASK 0xffffffff + #define DMA12_DEST_AD_WIDTH 32 + #define DMA12_DEST_AD_D_ADDR_BITS 31:0 + #define DMA12_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA12_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA12_DEST_AD_D_ADDR_MSB 31 + #define DMA12_DEST_AD_D_ADDR_LSB 0 +#define DMA12_TXFR_LEN HW_REGISTER_RO( 0x7e007c14 ) + #define DMA12_TXFR_LEN_MASK 0x0000ffff + #define DMA12_TXFR_LEN_WIDTH 16 + #define DMA12_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA12_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA12_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA12_TXFR_LEN_XLENGTH_MSB 15 + #define DMA12_TXFR_LEN_XLENGTH_LSB 0 +#define DMA12_NEXTCONBK HW_REGISTER_RO( 0x7e007c1c ) + #define DMA12_NEXTCONBK_MASK 0xffffffe0 + #define DMA12_NEXTCONBK_WIDTH 32 + #define DMA12_NEXTCONBK_ADDR_BITS 31:5 + #define DMA12_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA12_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA12_NEXTCONBK_ADDR_MSB 31 + #define DMA12_NEXTCONBK_ADDR_LSB 5 +#define DMA12_DEBUG HW_REGISTER_RW( 0x7e007c20 ) + #define DMA12_DEBUG_MASK 0x1ffffff7 + #define DMA12_DEBUG_WIDTH 29 + #define DMA12_DEBUG_RESET 0000000000 + #define DMA12_DEBUG_LITE_BITS 28:28 + #define DMA12_DEBUG_LITE_SET 0x10000000 + #define DMA12_DEBUG_LITE_CLR 0xefffffff + #define DMA12_DEBUG_LITE_MSB 28 + #define DMA12_DEBUG_LITE_LSB 28 + #define DMA12_DEBUG_VERSION_BITS 27:25 + #define DMA12_DEBUG_VERSION_SET 0x0e000000 + #define DMA12_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA12_DEBUG_VERSION_MSB 27 + #define DMA12_DEBUG_VERSION_LSB 25 + #define DMA12_DEBUG_DMA_STATE_BITS 24:16 + #define DMA12_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA12_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA12_DEBUG_DMA_STATE_MSB 24 + #define DMA12_DEBUG_DMA_STATE_LSB 16 + #define DMA12_DEBUG_DMA_ID_BITS 15:8 + #define DMA12_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA12_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA12_DEBUG_DMA_ID_MSB 15 + #define DMA12_DEBUG_DMA_ID_LSB 8 + #define DMA12_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA12_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA12_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA12_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA12_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA12_DEBUG_READ_ERROR_BITS 2:2 + #define DMA12_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA12_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA12_DEBUG_READ_ERROR_MSB 2 + #define DMA12_DEBUG_READ_ERROR_LSB 2 + #define DMA12_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA12_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA12_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA12_DEBUG_FIFO_ERROR_MSB 1 + #define DMA12_DEBUG_FIFO_ERROR_LSB 1 + #define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite13.h b/bcm2708_chip/axi_dma_lite13.h new file mode 100755 index 0000000..42bf47c --- /dev/null +++ b/bcm2708_chip/axi_dma_lite13.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA13_BASE 0x7e007d00 +#define DMA13_CS HW_REGISTER_RW( 0x7e007d00 ) + #define DMA13_CS_MASK 0xf0ff017f + #define DMA13_CS_WIDTH 32 + #define DMA13_CS_RESET 0000000000 + #define DMA13_CS_RESET_BITS 31:31 + #define DMA13_CS_RESET_SET 0x80000000 + #define DMA13_CS_RESET_CLR 0x7fffffff + #define DMA13_CS_RESET_MSB 31 + #define DMA13_CS_RESET_LSB 31 + #define DMA13_CS_ABORT_BITS 30:30 + #define DMA13_CS_ABORT_SET 0x40000000 + #define DMA13_CS_ABORT_CLR 0xbfffffff + #define DMA13_CS_ABORT_MSB 30 + #define DMA13_CS_ABORT_LSB 30 + #define DMA13_CS_DISDEBUG_BITS 29:29 + #define DMA13_CS_DISDEBUG_SET 0x20000000 + #define DMA13_CS_DISDEBUG_CLR 0xdfffffff + #define DMA13_CS_DISDEBUG_MSB 29 + #define DMA13_CS_DISDEBUG_LSB 29 + #define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA13_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA13_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA13_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA13_CS_PANIC_PRIORITY_MSB 23 + #define DMA13_CS_PANIC_PRIORITY_LSB 20 + #define DMA13_CS_PRIORITY_BITS 19:16 + #define DMA13_CS_PRIORITY_SET 0x000f0000 + #define DMA13_CS_PRIORITY_CLR 0xfff0ffff + #define DMA13_CS_PRIORITY_MSB 19 + #define DMA13_CS_PRIORITY_LSB 16 + #define DMA13_CS_ERROR_BITS 8:8 + #define DMA13_CS_ERROR_SET 0x00000100 + #define DMA13_CS_ERROR_CLR 0xfffffeff + #define DMA13_CS_ERROR_MSB 8 + #define DMA13_CS_ERROR_LSB 8 + #define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA13_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA13_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA13_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA13_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA13_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA13_CS_PAUSED_BITS 4:4 + #define DMA13_CS_PAUSED_SET 0x00000010 + #define DMA13_CS_PAUSED_CLR 0xffffffef + #define DMA13_CS_PAUSED_MSB 4 + #define DMA13_CS_PAUSED_LSB 4 + #define DMA13_CS_DREQ_BITS 3:3 + #define DMA13_CS_DREQ_SET 0x00000008 + #define DMA13_CS_DREQ_CLR 0xfffffff7 + #define DMA13_CS_DREQ_MSB 3 + #define DMA13_CS_DREQ_LSB 3 + #define DMA13_CS_INT_BITS 2:2 + #define DMA13_CS_INT_SET 0x00000004 + #define DMA13_CS_INT_CLR 0xfffffffb + #define DMA13_CS_INT_MSB 2 + #define DMA13_CS_INT_LSB 2 + #define DMA13_CS_END_BITS 1:1 + #define DMA13_CS_END_SET 0x00000002 + #define DMA13_CS_END_CLR 0xfffffffd + #define DMA13_CS_END_MSB 1 + #define DMA13_CS_END_LSB 1 + #define DMA13_CS_ACTIVE_BITS 0:0 + #define DMA13_CS_ACTIVE_SET 0x00000001 + #define DMA13_CS_ACTIVE_CLR 0xfffffffe + #define DMA13_CS_ACTIVE_MSB 0 + #define DMA13_CS_ACTIVE_LSB 0 +#define DMA13_CONBLK_AD HW_REGISTER_RW( 0x7e007d04 ) + #define DMA13_CONBLK_AD_MASK 0xffffffe0 + #define DMA13_CONBLK_AD_WIDTH 32 + #define DMA13_CONBLK_AD_RESET 0000000000 + #define DMA13_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA13_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA13_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA13_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA13_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA13_TI HW_REGISTER_RO( 0x7e007d08 ) + #define DMA13_TI_MASK 0x03fffff9 + #define DMA13_TI_WIDTH 26 + #define DMA13_TI_WAITS_BITS 25:21 + #define DMA13_TI_WAITS_SET 0x03e00000 + #define DMA13_TI_WAITS_CLR 0xfc1fffff + #define DMA13_TI_WAITS_MSB 25 + #define DMA13_TI_WAITS_LSB 21 + #define DMA13_TI_PERMAP_BITS 20:16 + #define DMA13_TI_PERMAP_SET 0x001f0000 + #define DMA13_TI_PERMAP_CLR 0xffe0ffff + #define DMA13_TI_PERMAP_MSB 20 + #define DMA13_TI_PERMAP_LSB 16 + #define DMA13_TI_BURST_LENGTH_BITS 15:12 + #define DMA13_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA13_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA13_TI_BURST_LENGTH_MSB 15 + #define DMA13_TI_BURST_LENGTH_LSB 12 + #define DMA13_TI_SRC_IGNORE_BITS 11:11 + #define DMA13_TI_SRC_IGNORE_SET 0x00000800 + #define DMA13_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA13_TI_SRC_IGNORE_MSB 11 + #define DMA13_TI_SRC_IGNORE_LSB 11 + #define DMA13_TI_SRC_DREQ_BITS 10:10 + #define DMA13_TI_SRC_DREQ_SET 0x00000400 + #define DMA13_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA13_TI_SRC_DREQ_MSB 10 + #define DMA13_TI_SRC_DREQ_LSB 10 + #define DMA13_TI_SRC_WIDTH_BITS 9:9 + #define DMA13_TI_SRC_WIDTH_SET 0x00000200 + #define DMA13_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA13_TI_SRC_WIDTH_MSB 9 + #define DMA13_TI_SRC_WIDTH_LSB 9 + #define DMA13_TI_SRC_INC_BITS 8:8 + #define DMA13_TI_SRC_INC_SET 0x00000100 + #define DMA13_TI_SRC_INC_CLR 0xfffffeff + #define DMA13_TI_SRC_INC_MSB 8 + #define DMA13_TI_SRC_INC_LSB 8 + #define DMA13_TI_DEST_IGNORE_BITS 7:7 + #define DMA13_TI_DEST_IGNORE_SET 0x00000080 + #define DMA13_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA13_TI_DEST_IGNORE_MSB 7 + #define DMA13_TI_DEST_IGNORE_LSB 7 + #define DMA13_TI_DEST_DREQ_BITS 6:6 + #define DMA13_TI_DEST_DREQ_SET 0x00000040 + #define DMA13_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA13_TI_DEST_DREQ_MSB 6 + #define DMA13_TI_DEST_DREQ_LSB 6 + #define DMA13_TI_DEST_WIDTH_BITS 5:5 + #define DMA13_TI_DEST_WIDTH_SET 0x00000020 + #define DMA13_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA13_TI_DEST_WIDTH_MSB 5 + #define DMA13_TI_DEST_WIDTH_LSB 5 + #define DMA13_TI_DEST_INC_BITS 4:4 + #define DMA13_TI_DEST_INC_SET 0x00000010 + #define DMA13_TI_DEST_INC_CLR 0xffffffef + #define DMA13_TI_DEST_INC_MSB 4 + #define DMA13_TI_DEST_INC_LSB 4 + #define DMA13_TI_WAIT_RESP_BITS 3:3 + #define DMA13_TI_WAIT_RESP_SET 0x00000008 + #define DMA13_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA13_TI_WAIT_RESP_MSB 3 + #define DMA13_TI_WAIT_RESP_LSB 3 + #define DMA13_TI_INTEN_BITS 0:0 + #define DMA13_TI_INTEN_SET 0x00000001 + #define DMA13_TI_INTEN_CLR 0xfffffffe + #define DMA13_TI_INTEN_MSB 0 + #define DMA13_TI_INTEN_LSB 0 +#define DMA13_SOURCE_AD HW_REGISTER_RO( 0x7e007d0c ) + #define DMA13_SOURCE_AD_MASK 0xffffffff + #define DMA13_SOURCE_AD_WIDTH 32 + #define DMA13_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA13_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA13_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA13_SOURCE_AD_S_ADDR_MSB 31 + #define DMA13_SOURCE_AD_S_ADDR_LSB 0 +#define DMA13_DEST_AD HW_REGISTER_RO( 0x7e007d10 ) + #define DMA13_DEST_AD_MASK 0xffffffff + #define DMA13_DEST_AD_WIDTH 32 + #define DMA13_DEST_AD_D_ADDR_BITS 31:0 + #define DMA13_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA13_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA13_DEST_AD_D_ADDR_MSB 31 + #define DMA13_DEST_AD_D_ADDR_LSB 0 +#define DMA13_TXFR_LEN HW_REGISTER_RO( 0x7e007d14 ) + #define DMA13_TXFR_LEN_MASK 0x0000ffff + #define DMA13_TXFR_LEN_WIDTH 16 + #define DMA13_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA13_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA13_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA13_TXFR_LEN_XLENGTH_MSB 15 + #define DMA13_TXFR_LEN_XLENGTH_LSB 0 +#define DMA13_NEXTCONBK HW_REGISTER_RO( 0x7e007d1c ) + #define DMA13_NEXTCONBK_MASK 0xffffffe0 + #define DMA13_NEXTCONBK_WIDTH 32 + #define DMA13_NEXTCONBK_ADDR_BITS 31:5 + #define DMA13_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA13_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA13_NEXTCONBK_ADDR_MSB 31 + #define DMA13_NEXTCONBK_ADDR_LSB 5 +#define DMA13_DEBUG HW_REGISTER_RW( 0x7e007d20 ) + #define DMA13_DEBUG_MASK 0x1ffffff7 + #define DMA13_DEBUG_WIDTH 29 + #define DMA13_DEBUG_RESET 0000000000 + #define DMA13_DEBUG_LITE_BITS 28:28 + #define DMA13_DEBUG_LITE_SET 0x10000000 + #define DMA13_DEBUG_LITE_CLR 0xefffffff + #define DMA13_DEBUG_LITE_MSB 28 + #define DMA13_DEBUG_LITE_LSB 28 + #define DMA13_DEBUG_VERSION_BITS 27:25 + #define DMA13_DEBUG_VERSION_SET 0x0e000000 + #define DMA13_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA13_DEBUG_VERSION_MSB 27 + #define DMA13_DEBUG_VERSION_LSB 25 + #define DMA13_DEBUG_DMA_STATE_BITS 24:16 + #define DMA13_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA13_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA13_DEBUG_DMA_STATE_MSB 24 + #define DMA13_DEBUG_DMA_STATE_LSB 16 + #define DMA13_DEBUG_DMA_ID_BITS 15:8 + #define DMA13_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA13_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA13_DEBUG_DMA_ID_MSB 15 + #define DMA13_DEBUG_DMA_ID_LSB 8 + #define DMA13_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA13_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA13_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA13_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA13_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA13_DEBUG_READ_ERROR_BITS 2:2 + #define DMA13_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA13_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA13_DEBUG_READ_ERROR_MSB 2 + #define DMA13_DEBUG_READ_ERROR_LSB 2 + #define DMA13_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA13_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA13_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA13_DEBUG_FIFO_ERROR_MSB 1 + #define DMA13_DEBUG_FIFO_ERROR_LSB 1 + #define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite14.h b/bcm2708_chip/axi_dma_lite14.h new file mode 100755 index 0000000..ad0908d --- /dev/null +++ b/bcm2708_chip/axi_dma_lite14.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA14_BASE 0x7e007e00 +#define DMA14_CS HW_REGISTER_RW( 0x7e007e00 ) + #define DMA14_CS_MASK 0xf0ff017f + #define DMA14_CS_WIDTH 32 + #define DMA14_CS_RESET 0000000000 + #define DMA14_CS_RESET_BITS 31:31 + #define DMA14_CS_RESET_SET 0x80000000 + #define DMA14_CS_RESET_CLR 0x7fffffff + #define DMA14_CS_RESET_MSB 31 + #define DMA14_CS_RESET_LSB 31 + #define DMA14_CS_ABORT_BITS 30:30 + #define DMA14_CS_ABORT_SET 0x40000000 + #define DMA14_CS_ABORT_CLR 0xbfffffff + #define DMA14_CS_ABORT_MSB 30 + #define DMA14_CS_ABORT_LSB 30 + #define DMA14_CS_DISDEBUG_BITS 29:29 + #define DMA14_CS_DISDEBUG_SET 0x20000000 + #define DMA14_CS_DISDEBUG_CLR 0xdfffffff + #define DMA14_CS_DISDEBUG_MSB 29 + #define DMA14_CS_DISDEBUG_LSB 29 + #define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA14_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA14_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA14_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA14_CS_PANIC_PRIORITY_MSB 23 + #define DMA14_CS_PANIC_PRIORITY_LSB 20 + #define DMA14_CS_PRIORITY_BITS 19:16 + #define DMA14_CS_PRIORITY_SET 0x000f0000 + #define DMA14_CS_PRIORITY_CLR 0xfff0ffff + #define DMA14_CS_PRIORITY_MSB 19 + #define DMA14_CS_PRIORITY_LSB 16 + #define DMA14_CS_ERROR_BITS 8:8 + #define DMA14_CS_ERROR_SET 0x00000100 + #define DMA14_CS_ERROR_CLR 0xfffffeff + #define DMA14_CS_ERROR_MSB 8 + #define DMA14_CS_ERROR_LSB 8 + #define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA14_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA14_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA14_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA14_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA14_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA14_CS_PAUSED_BITS 4:4 + #define DMA14_CS_PAUSED_SET 0x00000010 + #define DMA14_CS_PAUSED_CLR 0xffffffef + #define DMA14_CS_PAUSED_MSB 4 + #define DMA14_CS_PAUSED_LSB 4 + #define DMA14_CS_DREQ_BITS 3:3 + #define DMA14_CS_DREQ_SET 0x00000008 + #define DMA14_CS_DREQ_CLR 0xfffffff7 + #define DMA14_CS_DREQ_MSB 3 + #define DMA14_CS_DREQ_LSB 3 + #define DMA14_CS_INT_BITS 2:2 + #define DMA14_CS_INT_SET 0x00000004 + #define DMA14_CS_INT_CLR 0xfffffffb + #define DMA14_CS_INT_MSB 2 + #define DMA14_CS_INT_LSB 2 + #define DMA14_CS_END_BITS 1:1 + #define DMA14_CS_END_SET 0x00000002 + #define DMA14_CS_END_CLR 0xfffffffd + #define DMA14_CS_END_MSB 1 + #define DMA14_CS_END_LSB 1 + #define DMA14_CS_ACTIVE_BITS 0:0 + #define DMA14_CS_ACTIVE_SET 0x00000001 + #define DMA14_CS_ACTIVE_CLR 0xfffffffe + #define DMA14_CS_ACTIVE_MSB 0 + #define DMA14_CS_ACTIVE_LSB 0 +#define DMA14_CONBLK_AD HW_REGISTER_RW( 0x7e007e04 ) + #define DMA14_CONBLK_AD_MASK 0xffffffe0 + #define DMA14_CONBLK_AD_WIDTH 32 + #define DMA14_CONBLK_AD_RESET 0000000000 + #define DMA14_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA14_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA14_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA14_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA14_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA14_TI HW_REGISTER_RO( 0x7e007e08 ) + #define DMA14_TI_MASK 0x03fffff9 + #define DMA14_TI_WIDTH 26 + #define DMA14_TI_WAITS_BITS 25:21 + #define DMA14_TI_WAITS_SET 0x03e00000 + #define DMA14_TI_WAITS_CLR 0xfc1fffff + #define DMA14_TI_WAITS_MSB 25 + #define DMA14_TI_WAITS_LSB 21 + #define DMA14_TI_PERMAP_BITS 20:16 + #define DMA14_TI_PERMAP_SET 0x001f0000 + #define DMA14_TI_PERMAP_CLR 0xffe0ffff + #define DMA14_TI_PERMAP_MSB 20 + #define DMA14_TI_PERMAP_LSB 16 + #define DMA14_TI_BURST_LENGTH_BITS 15:12 + #define DMA14_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA14_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA14_TI_BURST_LENGTH_MSB 15 + #define DMA14_TI_BURST_LENGTH_LSB 12 + #define DMA14_TI_SRC_IGNORE_BITS 11:11 + #define DMA14_TI_SRC_IGNORE_SET 0x00000800 + #define DMA14_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA14_TI_SRC_IGNORE_MSB 11 + #define DMA14_TI_SRC_IGNORE_LSB 11 + #define DMA14_TI_SRC_DREQ_BITS 10:10 + #define DMA14_TI_SRC_DREQ_SET 0x00000400 + #define DMA14_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA14_TI_SRC_DREQ_MSB 10 + #define DMA14_TI_SRC_DREQ_LSB 10 + #define DMA14_TI_SRC_WIDTH_BITS 9:9 + #define DMA14_TI_SRC_WIDTH_SET 0x00000200 + #define DMA14_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA14_TI_SRC_WIDTH_MSB 9 + #define DMA14_TI_SRC_WIDTH_LSB 9 + #define DMA14_TI_SRC_INC_BITS 8:8 + #define DMA14_TI_SRC_INC_SET 0x00000100 + #define DMA14_TI_SRC_INC_CLR 0xfffffeff + #define DMA14_TI_SRC_INC_MSB 8 + #define DMA14_TI_SRC_INC_LSB 8 + #define DMA14_TI_DEST_IGNORE_BITS 7:7 + #define DMA14_TI_DEST_IGNORE_SET 0x00000080 + #define DMA14_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA14_TI_DEST_IGNORE_MSB 7 + #define DMA14_TI_DEST_IGNORE_LSB 7 + #define DMA14_TI_DEST_DREQ_BITS 6:6 + #define DMA14_TI_DEST_DREQ_SET 0x00000040 + #define DMA14_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA14_TI_DEST_DREQ_MSB 6 + #define DMA14_TI_DEST_DREQ_LSB 6 + #define DMA14_TI_DEST_WIDTH_BITS 5:5 + #define DMA14_TI_DEST_WIDTH_SET 0x00000020 + #define DMA14_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA14_TI_DEST_WIDTH_MSB 5 + #define DMA14_TI_DEST_WIDTH_LSB 5 + #define DMA14_TI_DEST_INC_BITS 4:4 + #define DMA14_TI_DEST_INC_SET 0x00000010 + #define DMA14_TI_DEST_INC_CLR 0xffffffef + #define DMA14_TI_DEST_INC_MSB 4 + #define DMA14_TI_DEST_INC_LSB 4 + #define DMA14_TI_WAIT_RESP_BITS 3:3 + #define DMA14_TI_WAIT_RESP_SET 0x00000008 + #define DMA14_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA14_TI_WAIT_RESP_MSB 3 + #define DMA14_TI_WAIT_RESP_LSB 3 + #define DMA14_TI_INTEN_BITS 0:0 + #define DMA14_TI_INTEN_SET 0x00000001 + #define DMA14_TI_INTEN_CLR 0xfffffffe + #define DMA14_TI_INTEN_MSB 0 + #define DMA14_TI_INTEN_LSB 0 +#define DMA14_SOURCE_AD HW_REGISTER_RO( 0x7e007e0c ) + #define DMA14_SOURCE_AD_MASK 0xffffffff + #define DMA14_SOURCE_AD_WIDTH 32 + #define DMA14_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA14_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA14_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA14_SOURCE_AD_S_ADDR_MSB 31 + #define DMA14_SOURCE_AD_S_ADDR_LSB 0 +#define DMA14_DEST_AD HW_REGISTER_RO( 0x7e007e10 ) + #define DMA14_DEST_AD_MASK 0xffffffff + #define DMA14_DEST_AD_WIDTH 32 + #define DMA14_DEST_AD_D_ADDR_BITS 31:0 + #define DMA14_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA14_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA14_DEST_AD_D_ADDR_MSB 31 + #define DMA14_DEST_AD_D_ADDR_LSB 0 +#define DMA14_TXFR_LEN HW_REGISTER_RO( 0x7e007e14 ) + #define DMA14_TXFR_LEN_MASK 0x0000ffff + #define DMA14_TXFR_LEN_WIDTH 16 + #define DMA14_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA14_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA14_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA14_TXFR_LEN_XLENGTH_MSB 15 + #define DMA14_TXFR_LEN_XLENGTH_LSB 0 +#define DMA14_NEXTCONBK HW_REGISTER_RO( 0x7e007e1c ) + #define DMA14_NEXTCONBK_MASK 0xffffffe0 + #define DMA14_NEXTCONBK_WIDTH 32 + #define DMA14_NEXTCONBK_ADDR_BITS 31:5 + #define DMA14_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA14_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA14_NEXTCONBK_ADDR_MSB 31 + #define DMA14_NEXTCONBK_ADDR_LSB 5 +#define DMA14_DEBUG HW_REGISTER_RW( 0x7e007e20 ) + #define DMA14_DEBUG_MASK 0x1ffffff7 + #define DMA14_DEBUG_WIDTH 29 + #define DMA14_DEBUG_RESET 0000000000 + #define DMA14_DEBUG_LITE_BITS 28:28 + #define DMA14_DEBUG_LITE_SET 0x10000000 + #define DMA14_DEBUG_LITE_CLR 0xefffffff + #define DMA14_DEBUG_LITE_MSB 28 + #define DMA14_DEBUG_LITE_LSB 28 + #define DMA14_DEBUG_VERSION_BITS 27:25 + #define DMA14_DEBUG_VERSION_SET 0x0e000000 + #define DMA14_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA14_DEBUG_VERSION_MSB 27 + #define DMA14_DEBUG_VERSION_LSB 25 + #define DMA14_DEBUG_DMA_STATE_BITS 24:16 + #define DMA14_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA14_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA14_DEBUG_DMA_STATE_MSB 24 + #define DMA14_DEBUG_DMA_STATE_LSB 16 + #define DMA14_DEBUG_DMA_ID_BITS 15:8 + #define DMA14_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA14_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA14_DEBUG_DMA_ID_MSB 15 + #define DMA14_DEBUG_DMA_ID_LSB 8 + #define DMA14_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA14_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA14_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA14_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA14_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA14_DEBUG_READ_ERROR_BITS 2:2 + #define DMA14_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA14_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA14_DEBUG_READ_ERROR_MSB 2 + #define DMA14_DEBUG_READ_ERROR_LSB 2 + #define DMA14_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA14_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA14_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA14_DEBUG_FIFO_ERROR_MSB 1 + #define DMA14_DEBUG_FIFO_ERROR_LSB 1 + #define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite7.h b/bcm2708_chip/axi_dma_lite7.h new file mode 100755 index 0000000..ad375cc --- /dev/null +++ b/bcm2708_chip/axi_dma_lite7.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA7_BASE 0x7e007700 +#define DMA7_CS HW_REGISTER_RW( 0x7e007700 ) + #define DMA7_CS_MASK 0xf0ff017f + #define DMA7_CS_WIDTH 32 + #define DMA7_CS_RESET 0000000000 + #define DMA7_CS_RESET_BITS 31:31 + #define DMA7_CS_RESET_SET 0x80000000 + #define DMA7_CS_RESET_CLR 0x7fffffff + #define DMA7_CS_RESET_MSB 31 + #define DMA7_CS_RESET_LSB 31 + #define DMA7_CS_ABORT_BITS 30:30 + #define DMA7_CS_ABORT_SET 0x40000000 + #define DMA7_CS_ABORT_CLR 0xbfffffff + #define DMA7_CS_ABORT_MSB 30 + #define DMA7_CS_ABORT_LSB 30 + #define DMA7_CS_DISDEBUG_BITS 29:29 + #define DMA7_CS_DISDEBUG_SET 0x20000000 + #define DMA7_CS_DISDEBUG_CLR 0xdfffffff + #define DMA7_CS_DISDEBUG_MSB 29 + #define DMA7_CS_DISDEBUG_LSB 29 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA7_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA7_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA7_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA7_CS_PANIC_PRIORITY_MSB 23 + #define DMA7_CS_PANIC_PRIORITY_LSB 20 + #define DMA7_CS_PRIORITY_BITS 19:16 + #define DMA7_CS_PRIORITY_SET 0x000f0000 + #define DMA7_CS_PRIORITY_CLR 0xfff0ffff + #define DMA7_CS_PRIORITY_MSB 19 + #define DMA7_CS_PRIORITY_LSB 16 + #define DMA7_CS_ERROR_BITS 8:8 + #define DMA7_CS_ERROR_SET 0x00000100 + #define DMA7_CS_ERROR_CLR 0xfffffeff + #define DMA7_CS_ERROR_MSB 8 + #define DMA7_CS_ERROR_LSB 8 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA7_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA7_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA7_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA7_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA7_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA7_CS_PAUSED_BITS 4:4 + #define DMA7_CS_PAUSED_SET 0x00000010 + #define DMA7_CS_PAUSED_CLR 0xffffffef + #define DMA7_CS_PAUSED_MSB 4 + #define DMA7_CS_PAUSED_LSB 4 + #define DMA7_CS_DREQ_BITS 3:3 + #define DMA7_CS_DREQ_SET 0x00000008 + #define DMA7_CS_DREQ_CLR 0xfffffff7 + #define DMA7_CS_DREQ_MSB 3 + #define DMA7_CS_DREQ_LSB 3 + #define DMA7_CS_INT_BITS 2:2 + #define DMA7_CS_INT_SET 0x00000004 + #define DMA7_CS_INT_CLR 0xfffffffb + #define DMA7_CS_INT_MSB 2 + #define DMA7_CS_INT_LSB 2 + #define DMA7_CS_END_BITS 1:1 + #define DMA7_CS_END_SET 0x00000002 + #define DMA7_CS_END_CLR 0xfffffffd + #define DMA7_CS_END_MSB 1 + #define DMA7_CS_END_LSB 1 + #define DMA7_CS_ACTIVE_BITS 0:0 + #define DMA7_CS_ACTIVE_SET 0x00000001 + #define DMA7_CS_ACTIVE_CLR 0xfffffffe + #define DMA7_CS_ACTIVE_MSB 0 + #define DMA7_CS_ACTIVE_LSB 0 +#define DMA7_CONBLK_AD HW_REGISTER_RW( 0x7e007704 ) + #define DMA7_CONBLK_AD_MASK 0xffffffe0 + #define DMA7_CONBLK_AD_WIDTH 32 + #define DMA7_CONBLK_AD_RESET 0000000000 + #define DMA7_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA7_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA7_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA7_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA7_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA7_TI HW_REGISTER_RO( 0x7e007708 ) + #define DMA7_TI_MASK 0x03fffff9 + #define DMA7_TI_WIDTH 26 + #define DMA7_TI_WAITS_BITS 25:21 + #define DMA7_TI_WAITS_SET 0x03e00000 + #define DMA7_TI_WAITS_CLR 0xfc1fffff + #define DMA7_TI_WAITS_MSB 25 + #define DMA7_TI_WAITS_LSB 21 + #define DMA7_TI_PERMAP_BITS 20:16 + #define DMA7_TI_PERMAP_SET 0x001f0000 + #define DMA7_TI_PERMAP_CLR 0xffe0ffff + #define DMA7_TI_PERMAP_MSB 20 + #define DMA7_TI_PERMAP_LSB 16 + #define DMA7_TI_BURST_LENGTH_BITS 15:12 + #define DMA7_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA7_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA7_TI_BURST_LENGTH_MSB 15 + #define DMA7_TI_BURST_LENGTH_LSB 12 + #define DMA7_TI_SRC_IGNORE_BITS 11:11 + #define DMA7_TI_SRC_IGNORE_SET 0x00000800 + #define DMA7_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA7_TI_SRC_IGNORE_MSB 11 + #define DMA7_TI_SRC_IGNORE_LSB 11 + #define DMA7_TI_SRC_DREQ_BITS 10:10 + #define DMA7_TI_SRC_DREQ_SET 0x00000400 + #define DMA7_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA7_TI_SRC_DREQ_MSB 10 + #define DMA7_TI_SRC_DREQ_LSB 10 + #define DMA7_TI_SRC_WIDTH_BITS 9:9 + #define DMA7_TI_SRC_WIDTH_SET 0x00000200 + #define DMA7_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA7_TI_SRC_WIDTH_MSB 9 + #define DMA7_TI_SRC_WIDTH_LSB 9 + #define DMA7_TI_SRC_INC_BITS 8:8 + #define DMA7_TI_SRC_INC_SET 0x00000100 + #define DMA7_TI_SRC_INC_CLR 0xfffffeff + #define DMA7_TI_SRC_INC_MSB 8 + #define DMA7_TI_SRC_INC_LSB 8 + #define DMA7_TI_DEST_IGNORE_BITS 7:7 + #define DMA7_TI_DEST_IGNORE_SET 0x00000080 + #define DMA7_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA7_TI_DEST_IGNORE_MSB 7 + #define DMA7_TI_DEST_IGNORE_LSB 7 + #define DMA7_TI_DEST_DREQ_BITS 6:6 + #define DMA7_TI_DEST_DREQ_SET 0x00000040 + #define DMA7_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA7_TI_DEST_DREQ_MSB 6 + #define DMA7_TI_DEST_DREQ_LSB 6 + #define DMA7_TI_DEST_WIDTH_BITS 5:5 + #define DMA7_TI_DEST_WIDTH_SET 0x00000020 + #define DMA7_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA7_TI_DEST_WIDTH_MSB 5 + #define DMA7_TI_DEST_WIDTH_LSB 5 + #define DMA7_TI_DEST_INC_BITS 4:4 + #define DMA7_TI_DEST_INC_SET 0x00000010 + #define DMA7_TI_DEST_INC_CLR 0xffffffef + #define DMA7_TI_DEST_INC_MSB 4 + #define DMA7_TI_DEST_INC_LSB 4 + #define DMA7_TI_WAIT_RESP_BITS 3:3 + #define DMA7_TI_WAIT_RESP_SET 0x00000008 + #define DMA7_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA7_TI_WAIT_RESP_MSB 3 + #define DMA7_TI_WAIT_RESP_LSB 3 + #define DMA7_TI_INTEN_BITS 0:0 + #define DMA7_TI_INTEN_SET 0x00000001 + #define DMA7_TI_INTEN_CLR 0xfffffffe + #define DMA7_TI_INTEN_MSB 0 + #define DMA7_TI_INTEN_LSB 0 +#define DMA7_SOURCE_AD HW_REGISTER_RO( 0x7e00770c ) + #define DMA7_SOURCE_AD_MASK 0xffffffff + #define DMA7_SOURCE_AD_WIDTH 32 + #define DMA7_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA7_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA7_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA7_SOURCE_AD_S_ADDR_MSB 31 + #define DMA7_SOURCE_AD_S_ADDR_LSB 0 +#define DMA7_DEST_AD HW_REGISTER_RO( 0x7e007710 ) + #define DMA7_DEST_AD_MASK 0xffffffff + #define DMA7_DEST_AD_WIDTH 32 + #define DMA7_DEST_AD_D_ADDR_BITS 31:0 + #define DMA7_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA7_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA7_DEST_AD_D_ADDR_MSB 31 + #define DMA7_DEST_AD_D_ADDR_LSB 0 +#define DMA7_TXFR_LEN HW_REGISTER_RO( 0x7e007714 ) + #define DMA7_TXFR_LEN_MASK 0x0000ffff + #define DMA7_TXFR_LEN_WIDTH 16 + #define DMA7_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA7_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA7_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA7_TXFR_LEN_XLENGTH_MSB 15 + #define DMA7_TXFR_LEN_XLENGTH_LSB 0 +#define DMA7_NEXTCONBK HW_REGISTER_RO( 0x7e00771c ) + #define DMA7_NEXTCONBK_MASK 0xffffffe0 + #define DMA7_NEXTCONBK_WIDTH 32 + #define DMA7_NEXTCONBK_ADDR_BITS 31:5 + #define DMA7_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA7_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA7_NEXTCONBK_ADDR_MSB 31 + #define DMA7_NEXTCONBK_ADDR_LSB 5 +#define DMA7_DEBUG HW_REGISTER_RW( 0x7e007720 ) + #define DMA7_DEBUG_MASK 0x1ffffff7 + #define DMA7_DEBUG_WIDTH 29 + #define DMA7_DEBUG_RESET 0000000000 + #define DMA7_DEBUG_LITE_BITS 28:28 + #define DMA7_DEBUG_LITE_SET 0x10000000 + #define DMA7_DEBUG_LITE_CLR 0xefffffff + #define DMA7_DEBUG_LITE_MSB 28 + #define DMA7_DEBUG_LITE_LSB 28 + #define DMA7_DEBUG_VERSION_BITS 27:25 + #define DMA7_DEBUG_VERSION_SET 0x0e000000 + #define DMA7_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA7_DEBUG_VERSION_MSB 27 + #define DMA7_DEBUG_VERSION_LSB 25 + #define DMA7_DEBUG_DMA_STATE_BITS 24:16 + #define DMA7_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA7_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA7_DEBUG_DMA_STATE_MSB 24 + #define DMA7_DEBUG_DMA_STATE_LSB 16 + #define DMA7_DEBUG_DMA_ID_BITS 15:8 + #define DMA7_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA7_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA7_DEBUG_DMA_ID_MSB 15 + #define DMA7_DEBUG_DMA_ID_LSB 8 + #define DMA7_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA7_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA7_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA7_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA7_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA7_DEBUG_READ_ERROR_BITS 2:2 + #define DMA7_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA7_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA7_DEBUG_READ_ERROR_MSB 2 + #define DMA7_DEBUG_READ_ERROR_LSB 2 + #define DMA7_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA7_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA7_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA7_DEBUG_FIFO_ERROR_MSB 1 + #define DMA7_DEBUG_FIFO_ERROR_LSB 1 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite8.h b/bcm2708_chip/axi_dma_lite8.h new file mode 100755 index 0000000..af7d04f --- /dev/null +++ b/bcm2708_chip/axi_dma_lite8.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA8_BASE 0x7e007800 +#define DMA8_CS HW_REGISTER_RW( 0x7e007800 ) + #define DMA8_CS_MASK 0xf0ff017f + #define DMA8_CS_WIDTH 32 + #define DMA8_CS_RESET 0000000000 + #define DMA8_CS_RESET_BITS 31:31 + #define DMA8_CS_RESET_SET 0x80000000 + #define DMA8_CS_RESET_CLR 0x7fffffff + #define DMA8_CS_RESET_MSB 31 + #define DMA8_CS_RESET_LSB 31 + #define DMA8_CS_ABORT_BITS 30:30 + #define DMA8_CS_ABORT_SET 0x40000000 + #define DMA8_CS_ABORT_CLR 0xbfffffff + #define DMA8_CS_ABORT_MSB 30 + #define DMA8_CS_ABORT_LSB 30 + #define DMA8_CS_DISDEBUG_BITS 29:29 + #define DMA8_CS_DISDEBUG_SET 0x20000000 + #define DMA8_CS_DISDEBUG_CLR 0xdfffffff + #define DMA8_CS_DISDEBUG_MSB 29 + #define DMA8_CS_DISDEBUG_LSB 29 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA8_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA8_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA8_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA8_CS_PANIC_PRIORITY_MSB 23 + #define DMA8_CS_PANIC_PRIORITY_LSB 20 + #define DMA8_CS_PRIORITY_BITS 19:16 + #define DMA8_CS_PRIORITY_SET 0x000f0000 + #define DMA8_CS_PRIORITY_CLR 0xfff0ffff + #define DMA8_CS_PRIORITY_MSB 19 + #define DMA8_CS_PRIORITY_LSB 16 + #define DMA8_CS_ERROR_BITS 8:8 + #define DMA8_CS_ERROR_SET 0x00000100 + #define DMA8_CS_ERROR_CLR 0xfffffeff + #define DMA8_CS_ERROR_MSB 8 + #define DMA8_CS_ERROR_LSB 8 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA8_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA8_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA8_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA8_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA8_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA8_CS_PAUSED_BITS 4:4 + #define DMA8_CS_PAUSED_SET 0x00000010 + #define DMA8_CS_PAUSED_CLR 0xffffffef + #define DMA8_CS_PAUSED_MSB 4 + #define DMA8_CS_PAUSED_LSB 4 + #define DMA8_CS_DREQ_BITS 3:3 + #define DMA8_CS_DREQ_SET 0x00000008 + #define DMA8_CS_DREQ_CLR 0xfffffff7 + #define DMA8_CS_DREQ_MSB 3 + #define DMA8_CS_DREQ_LSB 3 + #define DMA8_CS_INT_BITS 2:2 + #define DMA8_CS_INT_SET 0x00000004 + #define DMA8_CS_INT_CLR 0xfffffffb + #define DMA8_CS_INT_MSB 2 + #define DMA8_CS_INT_LSB 2 + #define DMA8_CS_END_BITS 1:1 + #define DMA8_CS_END_SET 0x00000002 + #define DMA8_CS_END_CLR 0xfffffffd + #define DMA8_CS_END_MSB 1 + #define DMA8_CS_END_LSB 1 + #define DMA8_CS_ACTIVE_BITS 0:0 + #define DMA8_CS_ACTIVE_SET 0x00000001 + #define DMA8_CS_ACTIVE_CLR 0xfffffffe + #define DMA8_CS_ACTIVE_MSB 0 + #define DMA8_CS_ACTIVE_LSB 0 +#define DMA8_CONBLK_AD HW_REGISTER_RW( 0x7e007804 ) + #define DMA8_CONBLK_AD_MASK 0xffffffe0 + #define DMA8_CONBLK_AD_WIDTH 32 + #define DMA8_CONBLK_AD_RESET 0000000000 + #define DMA8_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA8_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA8_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA8_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA8_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA8_TI HW_REGISTER_RO( 0x7e007808 ) + #define DMA8_TI_MASK 0x03fffff9 + #define DMA8_TI_WIDTH 26 + #define DMA8_TI_WAITS_BITS 25:21 + #define DMA8_TI_WAITS_SET 0x03e00000 + #define DMA8_TI_WAITS_CLR 0xfc1fffff + #define DMA8_TI_WAITS_MSB 25 + #define DMA8_TI_WAITS_LSB 21 + #define DMA8_TI_PERMAP_BITS 20:16 + #define DMA8_TI_PERMAP_SET 0x001f0000 + #define DMA8_TI_PERMAP_CLR 0xffe0ffff + #define DMA8_TI_PERMAP_MSB 20 + #define DMA8_TI_PERMAP_LSB 16 + #define DMA8_TI_BURST_LENGTH_BITS 15:12 + #define DMA8_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA8_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA8_TI_BURST_LENGTH_MSB 15 + #define DMA8_TI_BURST_LENGTH_LSB 12 + #define DMA8_TI_SRC_IGNORE_BITS 11:11 + #define DMA8_TI_SRC_IGNORE_SET 0x00000800 + #define DMA8_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA8_TI_SRC_IGNORE_MSB 11 + #define DMA8_TI_SRC_IGNORE_LSB 11 + #define DMA8_TI_SRC_DREQ_BITS 10:10 + #define DMA8_TI_SRC_DREQ_SET 0x00000400 + #define DMA8_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA8_TI_SRC_DREQ_MSB 10 + #define DMA8_TI_SRC_DREQ_LSB 10 + #define DMA8_TI_SRC_WIDTH_BITS 9:9 + #define DMA8_TI_SRC_WIDTH_SET 0x00000200 + #define DMA8_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA8_TI_SRC_WIDTH_MSB 9 + #define DMA8_TI_SRC_WIDTH_LSB 9 + #define DMA8_TI_SRC_INC_BITS 8:8 + #define DMA8_TI_SRC_INC_SET 0x00000100 + #define DMA8_TI_SRC_INC_CLR 0xfffffeff + #define DMA8_TI_SRC_INC_MSB 8 + #define DMA8_TI_SRC_INC_LSB 8 + #define DMA8_TI_DEST_IGNORE_BITS 7:7 + #define DMA8_TI_DEST_IGNORE_SET 0x00000080 + #define DMA8_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA8_TI_DEST_IGNORE_MSB 7 + #define DMA8_TI_DEST_IGNORE_LSB 7 + #define DMA8_TI_DEST_DREQ_BITS 6:6 + #define DMA8_TI_DEST_DREQ_SET 0x00000040 + #define DMA8_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA8_TI_DEST_DREQ_MSB 6 + #define DMA8_TI_DEST_DREQ_LSB 6 + #define DMA8_TI_DEST_WIDTH_BITS 5:5 + #define DMA8_TI_DEST_WIDTH_SET 0x00000020 + #define DMA8_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA8_TI_DEST_WIDTH_MSB 5 + #define DMA8_TI_DEST_WIDTH_LSB 5 + #define DMA8_TI_DEST_INC_BITS 4:4 + #define DMA8_TI_DEST_INC_SET 0x00000010 + #define DMA8_TI_DEST_INC_CLR 0xffffffef + #define DMA8_TI_DEST_INC_MSB 4 + #define DMA8_TI_DEST_INC_LSB 4 + #define DMA8_TI_WAIT_RESP_BITS 3:3 + #define DMA8_TI_WAIT_RESP_SET 0x00000008 + #define DMA8_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA8_TI_WAIT_RESP_MSB 3 + #define DMA8_TI_WAIT_RESP_LSB 3 + #define DMA8_TI_INTEN_BITS 0:0 + #define DMA8_TI_INTEN_SET 0x00000001 + #define DMA8_TI_INTEN_CLR 0xfffffffe + #define DMA8_TI_INTEN_MSB 0 + #define DMA8_TI_INTEN_LSB 0 +#define DMA8_SOURCE_AD HW_REGISTER_RO( 0x7e00780c ) + #define DMA8_SOURCE_AD_MASK 0xffffffff + #define DMA8_SOURCE_AD_WIDTH 32 + #define DMA8_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA8_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA8_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA8_SOURCE_AD_S_ADDR_MSB 31 + #define DMA8_SOURCE_AD_S_ADDR_LSB 0 +#define DMA8_DEST_AD HW_REGISTER_RO( 0x7e007810 ) + #define DMA8_DEST_AD_MASK 0xffffffff + #define DMA8_DEST_AD_WIDTH 32 + #define DMA8_DEST_AD_D_ADDR_BITS 31:0 + #define DMA8_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA8_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA8_DEST_AD_D_ADDR_MSB 31 + #define DMA8_DEST_AD_D_ADDR_LSB 0 +#define DMA8_TXFR_LEN HW_REGISTER_RO( 0x7e007814 ) + #define DMA8_TXFR_LEN_MASK 0x0000ffff + #define DMA8_TXFR_LEN_WIDTH 16 + #define DMA8_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA8_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA8_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA8_TXFR_LEN_XLENGTH_MSB 15 + #define DMA8_TXFR_LEN_XLENGTH_LSB 0 +#define DMA8_NEXTCONBK HW_REGISTER_RO( 0x7e00781c ) + #define DMA8_NEXTCONBK_MASK 0xffffffe0 + #define DMA8_NEXTCONBK_WIDTH 32 + #define DMA8_NEXTCONBK_ADDR_BITS 31:5 + #define DMA8_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA8_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA8_NEXTCONBK_ADDR_MSB 31 + #define DMA8_NEXTCONBK_ADDR_LSB 5 +#define DMA8_DEBUG HW_REGISTER_RW( 0x7e007820 ) + #define DMA8_DEBUG_MASK 0x1ffffff7 + #define DMA8_DEBUG_WIDTH 29 + #define DMA8_DEBUG_RESET 0000000000 + #define DMA8_DEBUG_LITE_BITS 28:28 + #define DMA8_DEBUG_LITE_SET 0x10000000 + #define DMA8_DEBUG_LITE_CLR 0xefffffff + #define DMA8_DEBUG_LITE_MSB 28 + #define DMA8_DEBUG_LITE_LSB 28 + #define DMA8_DEBUG_VERSION_BITS 27:25 + #define DMA8_DEBUG_VERSION_SET 0x0e000000 + #define DMA8_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA8_DEBUG_VERSION_MSB 27 + #define DMA8_DEBUG_VERSION_LSB 25 + #define DMA8_DEBUG_DMA_STATE_BITS 24:16 + #define DMA8_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA8_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA8_DEBUG_DMA_STATE_MSB 24 + #define DMA8_DEBUG_DMA_STATE_LSB 16 + #define DMA8_DEBUG_DMA_ID_BITS 15:8 + #define DMA8_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA8_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA8_DEBUG_DMA_ID_MSB 15 + #define DMA8_DEBUG_DMA_ID_LSB 8 + #define DMA8_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA8_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA8_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA8_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA8_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA8_DEBUG_READ_ERROR_BITS 2:2 + #define DMA8_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA8_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA8_DEBUG_READ_ERROR_MSB 2 + #define DMA8_DEBUG_READ_ERROR_LSB 2 + #define DMA8_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA8_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA8_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA8_DEBUG_FIFO_ERROR_MSB 1 + #define DMA8_DEBUG_FIFO_ERROR_LSB 1 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_lite9.h b/bcm2708_chip/axi_dma_lite9.h new file mode 100755 index 0000000..8d6f246 --- /dev/null +++ b/bcm2708_chip/axi_dma_lite9.h @@ -0,0 +1,229 @@ +// This file was generated by the create_regs script +#define DMA9_BASE 0x7e007900 +#define DMA9_CS HW_REGISTER_RW( 0x7e007900 ) + #define DMA9_CS_MASK 0xf0ff017f + #define DMA9_CS_WIDTH 32 + #define DMA9_CS_RESET 0000000000 + #define DMA9_CS_RESET_BITS 31:31 + #define DMA9_CS_RESET_SET 0x80000000 + #define DMA9_CS_RESET_CLR 0x7fffffff + #define DMA9_CS_RESET_MSB 31 + #define DMA9_CS_RESET_LSB 31 + #define DMA9_CS_ABORT_BITS 30:30 + #define DMA9_CS_ABORT_SET 0x40000000 + #define DMA9_CS_ABORT_CLR 0xbfffffff + #define DMA9_CS_ABORT_MSB 30 + #define DMA9_CS_ABORT_LSB 30 + #define DMA9_CS_DISDEBUG_BITS 29:29 + #define DMA9_CS_DISDEBUG_SET 0x20000000 + #define DMA9_CS_DISDEBUG_CLR 0xdfffffff + #define DMA9_CS_DISDEBUG_MSB 29 + #define DMA9_CS_DISDEBUG_LSB 29 + #define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28 + #define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000 + #define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff + #define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28 + #define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28 + #define DMA9_CS_PANIC_PRIORITY_BITS 23:20 + #define DMA9_CS_PANIC_PRIORITY_SET 0x00f00000 + #define DMA9_CS_PANIC_PRIORITY_CLR 0xff0fffff + #define DMA9_CS_PANIC_PRIORITY_MSB 23 + #define DMA9_CS_PANIC_PRIORITY_LSB 20 + #define DMA9_CS_PRIORITY_BITS 19:16 + #define DMA9_CS_PRIORITY_SET 0x000f0000 + #define DMA9_CS_PRIORITY_CLR 0xfff0ffff + #define DMA9_CS_PRIORITY_MSB 19 + #define DMA9_CS_PRIORITY_LSB 16 + #define DMA9_CS_ERROR_BITS 8:8 + #define DMA9_CS_ERROR_SET 0x00000100 + #define DMA9_CS_ERROR_CLR 0xfffffeff + #define DMA9_CS_ERROR_MSB 8 + #define DMA9_CS_ERROR_LSB 8 + #define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6 + #define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040 + #define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf + #define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6 + #define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6 + #define DMA9_CS_DREQ_STOPS_DMA_BITS 5:5 + #define DMA9_CS_DREQ_STOPS_DMA_SET 0x00000020 + #define DMA9_CS_DREQ_STOPS_DMA_CLR 0xffffffdf + #define DMA9_CS_DREQ_STOPS_DMA_MSB 5 + #define DMA9_CS_DREQ_STOPS_DMA_LSB 5 + #define DMA9_CS_PAUSED_BITS 4:4 + #define DMA9_CS_PAUSED_SET 0x00000010 + #define DMA9_CS_PAUSED_CLR 0xffffffef + #define DMA9_CS_PAUSED_MSB 4 + #define DMA9_CS_PAUSED_LSB 4 + #define DMA9_CS_DREQ_BITS 3:3 + #define DMA9_CS_DREQ_SET 0x00000008 + #define DMA9_CS_DREQ_CLR 0xfffffff7 + #define DMA9_CS_DREQ_MSB 3 + #define DMA9_CS_DREQ_LSB 3 + #define DMA9_CS_INT_BITS 2:2 + #define DMA9_CS_INT_SET 0x00000004 + #define DMA9_CS_INT_CLR 0xfffffffb + #define DMA9_CS_INT_MSB 2 + #define DMA9_CS_INT_LSB 2 + #define DMA9_CS_END_BITS 1:1 + #define DMA9_CS_END_SET 0x00000002 + #define DMA9_CS_END_CLR 0xfffffffd + #define DMA9_CS_END_MSB 1 + #define DMA9_CS_END_LSB 1 + #define DMA9_CS_ACTIVE_BITS 0:0 + #define DMA9_CS_ACTIVE_SET 0x00000001 + #define DMA9_CS_ACTIVE_CLR 0xfffffffe + #define DMA9_CS_ACTIVE_MSB 0 + #define DMA9_CS_ACTIVE_LSB 0 +#define DMA9_CONBLK_AD HW_REGISTER_RW( 0x7e007904 ) + #define DMA9_CONBLK_AD_MASK 0xffffffe0 + #define DMA9_CONBLK_AD_WIDTH 32 + #define DMA9_CONBLK_AD_RESET 0000000000 + #define DMA9_CONBLK_AD_SCB_ADDR_BITS 31:5 + #define DMA9_CONBLK_AD_SCB_ADDR_SET 0xffffffe0 + #define DMA9_CONBLK_AD_SCB_ADDR_CLR 0x0000001f + #define DMA9_CONBLK_AD_SCB_ADDR_MSB 31 + #define DMA9_CONBLK_AD_SCB_ADDR_LSB 5 +#define DMA9_TI HW_REGISTER_RO( 0x7e007908 ) + #define DMA9_TI_MASK 0x03fffff9 + #define DMA9_TI_WIDTH 26 + #define DMA9_TI_WAITS_BITS 25:21 + #define DMA9_TI_WAITS_SET 0x03e00000 + #define DMA9_TI_WAITS_CLR 0xfc1fffff + #define DMA9_TI_WAITS_MSB 25 + #define DMA9_TI_WAITS_LSB 21 + #define DMA9_TI_PERMAP_BITS 20:16 + #define DMA9_TI_PERMAP_SET 0x001f0000 + #define DMA9_TI_PERMAP_CLR 0xffe0ffff + #define DMA9_TI_PERMAP_MSB 20 + #define DMA9_TI_PERMAP_LSB 16 + #define DMA9_TI_BURST_LENGTH_BITS 15:12 + #define DMA9_TI_BURST_LENGTH_SET 0x0000f000 + #define DMA9_TI_BURST_LENGTH_CLR 0xffff0fff + #define DMA9_TI_BURST_LENGTH_MSB 15 + #define DMA9_TI_BURST_LENGTH_LSB 12 + #define DMA9_TI_SRC_IGNORE_BITS 11:11 + #define DMA9_TI_SRC_IGNORE_SET 0x00000800 + #define DMA9_TI_SRC_IGNORE_CLR 0xfffff7ff + #define DMA9_TI_SRC_IGNORE_MSB 11 + #define DMA9_TI_SRC_IGNORE_LSB 11 + #define DMA9_TI_SRC_DREQ_BITS 10:10 + #define DMA9_TI_SRC_DREQ_SET 0x00000400 + #define DMA9_TI_SRC_DREQ_CLR 0xfffffbff + #define DMA9_TI_SRC_DREQ_MSB 10 + #define DMA9_TI_SRC_DREQ_LSB 10 + #define DMA9_TI_SRC_WIDTH_BITS 9:9 + #define DMA9_TI_SRC_WIDTH_SET 0x00000200 + #define DMA9_TI_SRC_WIDTH_CLR 0xfffffdff + #define DMA9_TI_SRC_WIDTH_MSB 9 + #define DMA9_TI_SRC_WIDTH_LSB 9 + #define DMA9_TI_SRC_INC_BITS 8:8 + #define DMA9_TI_SRC_INC_SET 0x00000100 + #define DMA9_TI_SRC_INC_CLR 0xfffffeff + #define DMA9_TI_SRC_INC_MSB 8 + #define DMA9_TI_SRC_INC_LSB 8 + #define DMA9_TI_DEST_IGNORE_BITS 7:7 + #define DMA9_TI_DEST_IGNORE_SET 0x00000080 + #define DMA9_TI_DEST_IGNORE_CLR 0xffffff7f + #define DMA9_TI_DEST_IGNORE_MSB 7 + #define DMA9_TI_DEST_IGNORE_LSB 7 + #define DMA9_TI_DEST_DREQ_BITS 6:6 + #define DMA9_TI_DEST_DREQ_SET 0x00000040 + #define DMA9_TI_DEST_DREQ_CLR 0xffffffbf + #define DMA9_TI_DEST_DREQ_MSB 6 + #define DMA9_TI_DEST_DREQ_LSB 6 + #define DMA9_TI_DEST_WIDTH_BITS 5:5 + #define DMA9_TI_DEST_WIDTH_SET 0x00000020 + #define DMA9_TI_DEST_WIDTH_CLR 0xffffffdf + #define DMA9_TI_DEST_WIDTH_MSB 5 + #define DMA9_TI_DEST_WIDTH_LSB 5 + #define DMA9_TI_DEST_INC_BITS 4:4 + #define DMA9_TI_DEST_INC_SET 0x00000010 + #define DMA9_TI_DEST_INC_CLR 0xffffffef + #define DMA9_TI_DEST_INC_MSB 4 + #define DMA9_TI_DEST_INC_LSB 4 + #define DMA9_TI_WAIT_RESP_BITS 3:3 + #define DMA9_TI_WAIT_RESP_SET 0x00000008 + #define DMA9_TI_WAIT_RESP_CLR 0xfffffff7 + #define DMA9_TI_WAIT_RESP_MSB 3 + #define DMA9_TI_WAIT_RESP_LSB 3 + #define DMA9_TI_INTEN_BITS 0:0 + #define DMA9_TI_INTEN_SET 0x00000001 + #define DMA9_TI_INTEN_CLR 0xfffffffe + #define DMA9_TI_INTEN_MSB 0 + #define DMA9_TI_INTEN_LSB 0 +#define DMA9_SOURCE_AD HW_REGISTER_RO( 0x7e00790c ) + #define DMA9_SOURCE_AD_MASK 0xffffffff + #define DMA9_SOURCE_AD_WIDTH 32 + #define DMA9_SOURCE_AD_S_ADDR_BITS 31:0 + #define DMA9_SOURCE_AD_S_ADDR_SET 0xffffffff + #define DMA9_SOURCE_AD_S_ADDR_CLR 0x00000000 + #define DMA9_SOURCE_AD_S_ADDR_MSB 31 + #define DMA9_SOURCE_AD_S_ADDR_LSB 0 +#define DMA9_DEST_AD HW_REGISTER_RO( 0x7e007910 ) + #define DMA9_DEST_AD_MASK 0xffffffff + #define DMA9_DEST_AD_WIDTH 32 + #define DMA9_DEST_AD_D_ADDR_BITS 31:0 + #define DMA9_DEST_AD_D_ADDR_SET 0xffffffff + #define DMA9_DEST_AD_D_ADDR_CLR 0x00000000 + #define DMA9_DEST_AD_D_ADDR_MSB 31 + #define DMA9_DEST_AD_D_ADDR_LSB 0 +#define DMA9_TXFR_LEN HW_REGISTER_RO( 0x7e007914 ) + #define DMA9_TXFR_LEN_MASK 0x0000ffff + #define DMA9_TXFR_LEN_WIDTH 16 + #define DMA9_TXFR_LEN_XLENGTH_BITS 15:0 + #define DMA9_TXFR_LEN_XLENGTH_SET 0x0000ffff + #define DMA9_TXFR_LEN_XLENGTH_CLR 0xffff0000 + #define DMA9_TXFR_LEN_XLENGTH_MSB 15 + #define DMA9_TXFR_LEN_XLENGTH_LSB 0 +#define DMA9_NEXTCONBK HW_REGISTER_RO( 0x7e00791c ) + #define DMA9_NEXTCONBK_MASK 0xffffffe0 + #define DMA9_NEXTCONBK_WIDTH 32 + #define DMA9_NEXTCONBK_ADDR_BITS 31:5 + #define DMA9_NEXTCONBK_ADDR_SET 0xffffffe0 + #define DMA9_NEXTCONBK_ADDR_CLR 0x0000001f + #define DMA9_NEXTCONBK_ADDR_MSB 31 + #define DMA9_NEXTCONBK_ADDR_LSB 5 +#define DMA9_DEBUG HW_REGISTER_RW( 0x7e007920 ) + #define DMA9_DEBUG_MASK 0x1ffffff7 + #define DMA9_DEBUG_WIDTH 29 + #define DMA9_DEBUG_RESET 0000000000 + #define DMA9_DEBUG_LITE_BITS 28:28 + #define DMA9_DEBUG_LITE_SET 0x10000000 + #define DMA9_DEBUG_LITE_CLR 0xefffffff + #define DMA9_DEBUG_LITE_MSB 28 + #define DMA9_DEBUG_LITE_LSB 28 + #define DMA9_DEBUG_VERSION_BITS 27:25 + #define DMA9_DEBUG_VERSION_SET 0x0e000000 + #define DMA9_DEBUG_VERSION_CLR 0xf1ffffff + #define DMA9_DEBUG_VERSION_MSB 27 + #define DMA9_DEBUG_VERSION_LSB 25 + #define DMA9_DEBUG_DMA_STATE_BITS 24:16 + #define DMA9_DEBUG_DMA_STATE_SET 0x01ff0000 + #define DMA9_DEBUG_DMA_STATE_CLR 0xfe00ffff + #define DMA9_DEBUG_DMA_STATE_MSB 24 + #define DMA9_DEBUG_DMA_STATE_LSB 16 + #define DMA9_DEBUG_DMA_ID_BITS 15:8 + #define DMA9_DEBUG_DMA_ID_SET 0x0000ff00 + #define DMA9_DEBUG_DMA_ID_CLR 0xffff00ff + #define DMA9_DEBUG_DMA_ID_MSB 15 + #define DMA9_DEBUG_DMA_ID_LSB 8 + #define DMA9_DEBUG_OUTSTANDING_WRITES_BITS 7:4 + #define DMA9_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0 + #define DMA9_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f + #define DMA9_DEBUG_OUTSTANDING_WRITES_MSB 7 + #define DMA9_DEBUG_OUTSTANDING_WRITES_LSB 4 + #define DMA9_DEBUG_READ_ERROR_BITS 2:2 + #define DMA9_DEBUG_READ_ERROR_SET 0x00000004 + #define DMA9_DEBUG_READ_ERROR_CLR 0xfffffffb + #define DMA9_DEBUG_READ_ERROR_MSB 2 + #define DMA9_DEBUG_READ_ERROR_LSB 2 + #define DMA9_DEBUG_FIFO_ERROR_BITS 1:1 + #define DMA9_DEBUG_FIFO_ERROR_SET 0x00000002 + #define DMA9_DEBUG_FIFO_ERROR_CLR 0xfffffffd + #define DMA9_DEBUG_FIFO_ERROR_MSB 1 + #define DMA9_DEBUG_FIFO_ERROR_LSB 1 + #define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0 + #define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001 + #define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe + #define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0 + #define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0 diff --git a/bcm2708_chip/axi_dma_top.h b/bcm2708_chip/axi_dma_top.h new file mode 100755 index 0000000..39b8670 --- /dev/null +++ b/bcm2708_chip/axi_dma_top.h @@ -0,0 +1,165 @@ +// This file was generated by the create_regs script +#define DMA_BASE 0x7e007fe0 +#define DMA_INT_STATUS HW_REGISTER_RO( 0x7e007fe0 ) + #define DMA_INT_STATUS_MASK 0x0000ffff + #define DMA_INT_STATUS_WIDTH 16 + #define DMA_INT_STATUS_RESET 0000000000 + #define DMA_INT_STATUS_INT0_BITS 0:0 + #define DMA_INT_STATUS_INT0_SET 0x00000001 + #define DMA_INT_STATUS_INT0_CLR 0xfffffffe + #define DMA_INT_STATUS_INT0_MSB 0 + #define DMA_INT_STATUS_INT0_LSB 0 + #define DMA_INT_STATUS_INT1_BITS 1:1 + #define DMA_INT_STATUS_INT1_SET 0x00000002 + #define DMA_INT_STATUS_INT1_CLR 0xfffffffd + #define DMA_INT_STATUS_INT1_MSB 1 + #define DMA_INT_STATUS_INT1_LSB 1 + #define DMA_INT_STATUS_INT2_BITS 2:2 + #define DMA_INT_STATUS_INT2_SET 0x00000004 + #define DMA_INT_STATUS_INT2_CLR 0xfffffffb + #define DMA_INT_STATUS_INT2_MSB 2 + #define DMA_INT_STATUS_INT2_LSB 2 + #define DMA_INT_STATUS_INT3_BITS 3:3 + #define DMA_INT_STATUS_INT3_SET 0x00000008 + #define DMA_INT_STATUS_INT3_CLR 0xfffffff7 + #define DMA_INT_STATUS_INT3_MSB 3 + #define DMA_INT_STATUS_INT3_LSB 3 + #define DMA_INT_STATUS_INT4_BITS 4:4 + #define DMA_INT_STATUS_INT4_SET 0x00000010 + #define DMA_INT_STATUS_INT4_CLR 0xffffffef + #define DMA_INT_STATUS_INT4_MSB 4 + #define DMA_INT_STATUS_INT4_LSB 4 + #define DMA_INT_STATUS_INT5_BITS 5:5 + #define DMA_INT_STATUS_INT5_SET 0x00000020 + #define DMA_INT_STATUS_INT5_CLR 0xffffffdf + #define DMA_INT_STATUS_INT5_MSB 5 + #define DMA_INT_STATUS_INT5_LSB 5 + #define DMA_INT_STATUS_INT6_BITS 6:6 + #define DMA_INT_STATUS_INT6_SET 0x00000040 + #define DMA_INT_STATUS_INT6_CLR 0xffffffbf + #define DMA_INT_STATUS_INT6_MSB 6 + #define DMA_INT_STATUS_INT6_LSB 6 + #define DMA_INT_STATUS_INT7_BITS 7:7 + #define DMA_INT_STATUS_INT7_SET 0x00000080 + #define DMA_INT_STATUS_INT7_CLR 0xffffff7f + #define DMA_INT_STATUS_INT7_MSB 7 + #define DMA_INT_STATUS_INT7_LSB 7 + #define DMA_INT_STATUS_INT8_BITS 8:8 + #define DMA_INT_STATUS_INT8_SET 0x00000100 + #define DMA_INT_STATUS_INT8_CLR 0xfffffeff + #define DMA_INT_STATUS_INT8_MSB 8 + #define DMA_INT_STATUS_INT8_LSB 8 + #define DMA_INT_STATUS_INT9_BITS 9:9 + #define DMA_INT_STATUS_INT9_SET 0x00000200 + #define DMA_INT_STATUS_INT9_CLR 0xfffffdff + #define DMA_INT_STATUS_INT9_MSB 9 + #define DMA_INT_STATUS_INT9_LSB 9 + #define DMA_INT_STATUS_INT10_BITS 10:10 + #define DMA_INT_STATUS_INT10_SET 0x00000400 + #define DMA_INT_STATUS_INT10_CLR 0xfffffbff + #define DMA_INT_STATUS_INT10_MSB 10 + #define DMA_INT_STATUS_INT10_LSB 10 + #define DMA_INT_STATUS_INT11_BITS 11:11 + #define DMA_INT_STATUS_INT11_SET 0x00000800 + #define DMA_INT_STATUS_INT11_CLR 0xfffff7ff + #define DMA_INT_STATUS_INT11_MSB 11 + #define DMA_INT_STATUS_INT11_LSB 11 + #define DMA_INT_STATUS_INT12_BITS 12:12 + #define DMA_INT_STATUS_INT12_SET 0x00001000 + #define DMA_INT_STATUS_INT12_CLR 0xffffefff + #define DMA_INT_STATUS_INT12_MSB 12 + #define DMA_INT_STATUS_INT12_LSB 12 + #define DMA_INT_STATUS_INT13_BITS 13:13 + #define DMA_INT_STATUS_INT13_SET 0x00002000 + #define DMA_INT_STATUS_INT13_CLR 0xffffdfff + #define DMA_INT_STATUS_INT13_MSB 13 + #define DMA_INT_STATUS_INT13_LSB 13 + #define DMA_INT_STATUS_INT14_BITS 14:14 + #define DMA_INT_STATUS_INT14_SET 0x00004000 + #define DMA_INT_STATUS_INT14_CLR 0xffffbfff + #define DMA_INT_STATUS_INT14_MSB 14 + #define DMA_INT_STATUS_INT14_LSB 14 + #define DMA_INT_STATUS_INT15_BITS 15:15 + #define DMA_INT_STATUS_INT15_SET 0x00008000 + #define DMA_INT_STATUS_INT15_CLR 0xffff7fff + #define DMA_INT_STATUS_INT15_MSB 15 + #define DMA_INT_STATUS_INT15_LSB 15 +#define DMA_ENABLE HW_REGISTER_RW( 0x7e007ff0 ) + #define DMA_ENABLE_MASK 0x00007fff + #define DMA_ENABLE_WIDTH 15 + #define DMA_ENABLE_RESET 0x00007fff + #define DMA_ENABLE_EN0_BITS 0:0 + #define DMA_ENABLE_EN0_SET 0x00000001 + #define DMA_ENABLE_EN0_CLR 0xfffffffe + #define DMA_ENABLE_EN0_MSB 0 + #define DMA_ENABLE_EN0_LSB 0 + #define DMA_ENABLE_EN1_BITS 1:1 + #define DMA_ENABLE_EN1_SET 0x00000002 + #define DMA_ENABLE_EN1_CLR 0xfffffffd + #define DMA_ENABLE_EN1_MSB 1 + #define DMA_ENABLE_EN1_LSB 1 + #define DMA_ENABLE_EN2_BITS 2:2 + #define DMA_ENABLE_EN2_SET 0x00000004 + #define DMA_ENABLE_EN2_CLR 0xfffffffb + #define DMA_ENABLE_EN2_MSB 2 + #define DMA_ENABLE_EN2_LSB 2 + #define DMA_ENABLE_EN3_BITS 3:3 + #define DMA_ENABLE_EN3_SET 0x00000008 + #define DMA_ENABLE_EN3_CLR 0xfffffff7 + #define DMA_ENABLE_EN3_MSB 3 + #define DMA_ENABLE_EN3_LSB 3 + #define DMA_ENABLE_EN4_BITS 4:4 + #define DMA_ENABLE_EN4_SET 0x00000010 + #define DMA_ENABLE_EN4_CLR 0xffffffef + #define DMA_ENABLE_EN4_MSB 4 + #define DMA_ENABLE_EN4_LSB 4 + #define DMA_ENABLE_EN5_BITS 5:5 + #define DMA_ENABLE_EN5_SET 0x00000020 + #define DMA_ENABLE_EN5_CLR 0xffffffdf + #define DMA_ENABLE_EN5_MSB 5 + #define DMA_ENABLE_EN5_LSB 5 + #define DMA_ENABLE_EN6_BITS 6:6 + #define DMA_ENABLE_EN6_SET 0x00000040 + #define DMA_ENABLE_EN6_CLR 0xffffffbf + #define DMA_ENABLE_EN6_MSB 6 + #define DMA_ENABLE_EN6_LSB 6 + #define DMA_ENABLE_EN7_BITS 7:7 + #define DMA_ENABLE_EN7_SET 0x00000080 + #define DMA_ENABLE_EN7_CLR 0xffffff7f + #define DMA_ENABLE_EN7_MSB 7 + #define DMA_ENABLE_EN7_LSB 7 + #define DMA_ENABLE_EN8_BITS 8:8 + #define DMA_ENABLE_EN8_SET 0x00000100 + #define DMA_ENABLE_EN8_CLR 0xfffffeff + #define DMA_ENABLE_EN8_MSB 8 + #define DMA_ENABLE_EN8_LSB 8 + #define DMA_ENABLE_EN9_BITS 9:9 + #define DMA_ENABLE_EN9_SET 0x00000200 + #define DMA_ENABLE_EN9_CLR 0xfffffdff + #define DMA_ENABLE_EN9_MSB 9 + #define DMA_ENABLE_EN9_LSB 9 + #define DMA_ENABLE_EN10_BITS 10:10 + #define DMA_ENABLE_EN10_SET 0x00000400 + #define DMA_ENABLE_EN10_CLR 0xfffffbff + #define DMA_ENABLE_EN10_MSB 10 + #define DMA_ENABLE_EN10_LSB 10 + #define DMA_ENABLE_EN11_BITS 11:11 + #define DMA_ENABLE_EN11_SET 0x00000800 + #define DMA_ENABLE_EN11_CLR 0xfffff7ff + #define DMA_ENABLE_EN11_MSB 11 + #define DMA_ENABLE_EN11_LSB 11 + #define DMA_ENABLE_EN12_BITS 12:12 + #define DMA_ENABLE_EN12_SET 0x00001000 + #define DMA_ENABLE_EN12_CLR 0xffffefff + #define DMA_ENABLE_EN12_MSB 12 + #define DMA_ENABLE_EN12_LSB 12 + #define DMA_ENABLE_EN13_BITS 13:13 + #define DMA_ENABLE_EN13_SET 0x00002000 + #define DMA_ENABLE_EN13_CLR 0xffffdfff + #define DMA_ENABLE_EN13_MSB 13 + #define DMA_ENABLE_EN13_LSB 13 + #define DMA_ENABLE_EN14_BITS 14:14 + #define DMA_ENABLE_EN14_SET 0x00004000 + #define DMA_ENABLE_EN14_CLR 0xffffbfff + #define DMA_ENABLE_EN14_MSB 14 + #define DMA_ENABLE_EN14_LSB 14 diff --git a/bcm2708_chip/axi_performance0.h b/bcm2708_chip/axi_performance0.h new file mode 100755 index 0000000..080282b --- /dev/null +++ b/bcm2708_chip/axi_performance0.h @@ -0,0 +1,259 @@ +// This file was generated by the create_regs script +#define APERF0_BASE 0x7e009800 +#define APERF0_APB_ID 0x41584950 +#define APERF0_GEN_CTRL HW_REGISTER_RW( 0x7e009800 ) + #define APERF0_GEN_CTRL_MASK 0x00000003 + #define APERF0_GEN_CTRL_WIDTH 2 + #define APERF0_GEN_CTRL_RESET 0000000000 + #define APERF0_GEN_CTRL_ENABLE_BITS 0:0 + #define APERF0_GEN_CTRL_ENABLE_SET 0x00000001 + #define APERF0_GEN_CTRL_ENABLE_CLR 0xfffffffe + #define APERF0_GEN_CTRL_ENABLE_MSB 0 + #define APERF0_GEN_CTRL_ENABLE_LSB 0 + #define APERF0_GEN_CTRL_ENABLE_RESET 0x0 + #define APERF0_GEN_CTRL_RESET_BITS 1:1 + #define APERF0_GEN_CTRL_RESET_SET 0x00000002 + #define APERF0_GEN_CTRL_RESET_CLR 0xfffffffd + #define APERF0_GEN_CTRL_RESET_MSB 1 + #define APERF0_GEN_CTRL_RESET_LSB 1 + #define APERF0_GEN_CTRL_RESET_RESET 0x0 +#define APERF0_BW0_CTRL HW_REGISTER_RW( 0x7e009840 ) + #define APERF0_BW0_CTRL_MASK 0xf0001f1f + #define APERF0_BW0_CTRL_WIDTH 32 + #define APERF0_BW0_CTRL_RESET 0000000000 + #define APERF0_BW0_CTRL_BUS_BITS 4:0 + #define APERF0_BW0_CTRL_BUS_SET 0x0000001f + #define APERF0_BW0_CTRL_BUS_CLR 0xffffffe0 + #define APERF0_BW0_CTRL_BUS_MSB 4 + #define APERF0_BW0_CTRL_BUS_LSB 0 + #define APERF0_BW0_CTRL_BUS_RESET 0x0 + #define APERF0_BW0_CTRL_ID_BITS 12:8 + #define APERF0_BW0_CTRL_ID_SET 0x00001f00 + #define APERF0_BW0_CTRL_ID_CLR 0xffffe0ff + #define APERF0_BW0_CTRL_ID_MSB 12 + #define APERF0_BW0_CTRL_ID_LSB 8 + #define APERF0_BW0_CTRL_ID_RESET 0x0 + #define APERF0_BW0_CTRL_LATHALT_BITS 28:28 + #define APERF0_BW0_CTRL_LATHALT_SET 0x10000000 + #define APERF0_BW0_CTRL_LATHALT_CLR 0xefffffff + #define APERF0_BW0_CTRL_LATHALT_MSB 28 + #define APERF0_BW0_CTRL_LATHALT_LSB 28 + #define APERF0_BW0_CTRL_LATHALT_RESET 0x0 + #define APERF0_BW0_CTRL_ID_EN_BITS 29:29 + #define APERF0_BW0_CTRL_ID_EN_SET 0x20000000 + #define APERF0_BW0_CTRL_ID_EN_CLR 0xdfffffff + #define APERF0_BW0_CTRL_ID_EN_MSB 29 + #define APERF0_BW0_CTRL_ID_EN_LSB 29 + #define APERF0_BW0_CTRL_ID_EN_RESET 0x0 + #define APERF0_BW0_CTRL_EN_BITS 30:30 + #define APERF0_BW0_CTRL_EN_SET 0x40000000 + #define APERF0_BW0_CTRL_EN_CLR 0xbfffffff + #define APERF0_BW0_CTRL_EN_MSB 30 + #define APERF0_BW0_CTRL_EN_LSB 30 + #define APERF0_BW0_CTRL_EN_RESET 0x0 + #define APERF0_BW0_CTRL_RESET_BITS 31:31 + #define APERF0_BW0_CTRL_RESET_SET 0x80000000 + #define APERF0_BW0_CTRL_RESET_CLR 0x7fffffff + #define APERF0_BW0_CTRL_RESET_MSB 31 + #define APERF0_BW0_CTRL_RESET_LSB 31 + #define APERF0_BW0_CTRL_RESET_RESET 0x0 +#define APERF0_BW0_ATRANS HW_REGISTER_RO( 0x7e009844 ) + #define APERF0_BW0_ATRANS_MASK 0xffffffff + #define APERF0_BW0_ATRANS_WIDTH 32 + #define APERF0_BW0_ATRANS_RESET 0000000000 +#define APERF0_BW0_ATWAIT HW_REGISTER_RO( 0x7e009848 ) + #define APERF0_BW0_ATWAIT_MASK 0xffffffff + #define APERF0_BW0_ATWAIT_WIDTH 32 + #define APERF0_BW0_ATWAIT_RESET 0000000000 +#define APERF0_BW0_AMAX HW_REGISTER_RO( 0x7e00984c ) + #define APERF0_BW0_AMAX_MASK 0x00ffffff + #define APERF0_BW0_AMAX_WIDTH 24 + #define APERF0_BW0_AMAX_RESET 0000000000 +#define APERF0_BW0_WTRANS HW_REGISTER_RO( 0x7e009850 ) + #define APERF0_BW0_WTRANS_MASK 0xffffffff + #define APERF0_BW0_WTRANS_WIDTH 32 + #define APERF0_BW0_WTRANS_RESET 0000000000 +#define APERF0_BW0_WTWAIT HW_REGISTER_RO( 0x7e009854 ) + #define APERF0_BW0_WTWAIT_MASK 0xffffffff + #define APERF0_BW0_WTWAIT_WIDTH 32 + #define APERF0_BW0_WTWAIT_RESET 0000000000 +#define APERF0_BW0_WMAX HW_REGISTER_RO( 0x7e009858 ) + #define APERF0_BW0_WMAX_MASK 0x00ffffff + #define APERF0_BW0_WMAX_WIDTH 24 + #define APERF0_BW0_WMAX_RESET 0000000000 +#define APERF0_BW0_RTRANS HW_REGISTER_RO( 0x7e00985c ) + #define APERF0_BW0_RTRANS_MASK 0xffffffff + #define APERF0_BW0_RTRANS_WIDTH 32 + #define APERF0_BW0_RTRANS_RESET 0000000000 +#define APERF0_BW0_RTWAIT HW_REGISTER_RO( 0x7e009860 ) + #define APERF0_BW0_RTWAIT_MASK 0xffffffff + #define APERF0_BW0_RTWAIT_WIDTH 32 + #define APERF0_BW0_RTWAIT_RESET 0000000000 +#define APERF0_BW0_RMAX HW_REGISTER_RO( 0x7e009864 ) + #define APERF0_BW0_RMAX_MASK 0x00ffffff + #define APERF0_BW0_RMAX_WIDTH 24 + #define APERF0_BW0_RMAX_RESET 0000000000 +#define APERF0_BW0_RPEND HW_REGISTER_RO( 0x7e009868 ) + #define APERF0_BW0_RPEND_MASK 0x000000ff + #define APERF0_BW0_RPEND_WIDTH 8 + #define APERF0_BW0_RPEND_RESET 0000000000 +#define APERF0_BW1_CTRL HW_REGISTER_RW( 0x7e009880 ) + #define APERF0_BW1_CTRL_MASK 0xf0001f1f + #define APERF0_BW1_CTRL_WIDTH 32 + #define APERF0_BW1_CTRL_RESET 0000000000 + #define APERF0_BW1_CTRL_BUS_BITS 4:0 + #define APERF0_BW1_CTRL_BUS_SET 0x0000001f + #define APERF0_BW1_CTRL_BUS_CLR 0xffffffe0 + #define APERF0_BW1_CTRL_BUS_MSB 4 + #define APERF0_BW1_CTRL_BUS_LSB 0 + #define APERF0_BW1_CTRL_BUS_RESET 0x0 + #define APERF0_BW1_CTRL_ID_BITS 12:8 + #define APERF0_BW1_CTRL_ID_SET 0x00001f00 + #define APERF0_BW1_CTRL_ID_CLR 0xffffe0ff + #define APERF0_BW1_CTRL_ID_MSB 12 + #define APERF0_BW1_CTRL_ID_LSB 8 + #define APERF0_BW1_CTRL_ID_RESET 0x0 + #define APERF0_BW1_CTRL_LATHALT_BITS 28:28 + #define APERF0_BW1_CTRL_LATHALT_SET 0x10000000 + #define APERF0_BW1_CTRL_LATHALT_CLR 0xefffffff + #define APERF0_BW1_CTRL_LATHALT_MSB 28 + #define APERF0_BW1_CTRL_LATHALT_LSB 28 + #define APERF0_BW1_CTRL_LATHALT_RESET 0x0 + #define APERF0_BW1_CTRL_ID_EN_BITS 29:29 + #define APERF0_BW1_CTRL_ID_EN_SET 0x20000000 + #define APERF0_BW1_CTRL_ID_EN_CLR 0xdfffffff + #define APERF0_BW1_CTRL_ID_EN_MSB 29 + #define APERF0_BW1_CTRL_ID_EN_LSB 29 + #define APERF0_BW1_CTRL_ID_EN_RESET 0x0 + #define APERF0_BW1_CTRL_EN_BITS 30:30 + #define APERF0_BW1_CTRL_EN_SET 0x40000000 + #define APERF0_BW1_CTRL_EN_CLR 0xbfffffff + #define APERF0_BW1_CTRL_EN_MSB 30 + #define APERF0_BW1_CTRL_EN_LSB 30 + #define APERF0_BW1_CTRL_EN_RESET 0x0 + #define APERF0_BW1_CTRL_RESET_BITS 31:31 + #define APERF0_BW1_CTRL_RESET_SET 0x80000000 + #define APERF0_BW1_CTRL_RESET_CLR 0x7fffffff + #define APERF0_BW1_CTRL_RESET_MSB 31 + #define APERF0_BW1_CTRL_RESET_LSB 31 + #define APERF0_BW1_CTRL_RESET_RESET 0x0 +#define APERF0_BW1_ATRANS HW_REGISTER_RO( 0x7e009884 ) + #define APERF0_BW1_ATRANS_MASK 0xffffffff + #define APERF0_BW1_ATRANS_WIDTH 32 + #define APERF0_BW1_ATRANS_RESET 0000000000 +#define APERF0_BW1_ATWAIT HW_REGISTER_RO( 0x7e009888 ) + #define APERF0_BW1_ATWAIT_MASK 0xffffffff + #define APERF0_BW1_ATWAIT_WIDTH 32 + #define APERF0_BW1_ATWAIT_RESET 0000000000 +#define APERF0_BW1_AMAX HW_REGISTER_RO( 0x7e00988c ) + #define APERF0_BW1_AMAX_MASK 0x00ffffff + #define APERF0_BW1_AMAX_WIDTH 24 + #define APERF0_BW1_AMAX_RESET 0000000000 +#define APERF0_BW1_WTRANS HW_REGISTER_RO( 0x7e009890 ) + #define APERF0_BW1_WTRANS_MASK 0xffffffff + #define APERF0_BW1_WTRANS_WIDTH 32 + #define APERF0_BW1_WTRANS_RESET 0000000000 +#define APERF0_BW1_WTWAIT HW_REGISTER_RO( 0x7e009894 ) + #define APERF0_BW1_WTWAIT_MASK 0xffffffff + #define APERF0_BW1_WTWAIT_WIDTH 32 + #define APERF0_BW1_WTWAIT_RESET 0000000000 +#define APERF0_BW1_WMAX HW_REGISTER_RO( 0x7e009898 ) + #define APERF0_BW1_WMAX_MASK 0x0000ffff + #define APERF0_BW1_WMAX_WIDTH 16 + #define APERF0_BW1_WMAX_RESET 0000000000 +#define APERF0_BW1_RTRANS HW_REGISTER_RO( 0x7e00989c ) + #define APERF0_BW1_RTRANS_MASK 0xffffffff + #define APERF0_BW1_RTRANS_WIDTH 32 + #define APERF0_BW1_RTRANS_RESET 0000000000 +#define APERF0_BW1_RTWAIT HW_REGISTER_RO( 0x7e0098a0 ) + #define APERF0_BW1_RTWAIT_MASK 0xffffffff + #define APERF0_BW1_RTWAIT_WIDTH 32 + #define APERF0_BW1_RTWAIT_RESET 0000000000 +#define APERF0_BW1_RMAX HW_REGISTER_RO( 0x7e0098a4 ) + #define APERF0_BW1_RMAX_MASK 0x00ffffff + #define APERF0_BW1_RMAX_WIDTH 24 + #define APERF0_BW1_RMAX_RESET 0000000000 +#define APERF0_BW1_RPEND HW_REGISTER_RO( 0x7e009868 ) + #define APERF0_BW1_RPEND_MASK 0x000000ff + #define APERF0_BW1_RPEND_WIDTH 8 + #define APERF0_BW1_RPEND_RESET 0000000000 +#define APERF0_BW2_CTRL HW_REGISTER_RW( 0x7e0098c0 ) + #define APERF0_BW2_CTRL_MASK 0xf0001f1f + #define APERF0_BW2_CTRL_WIDTH 32 + #define APERF0_BW2_CTRL_RESET 0000000000 + #define APERF0_BW2_CTRL_BUS_BITS 4:0 + #define APERF0_BW2_CTRL_BUS_SET 0x0000001f + #define APERF0_BW2_CTRL_BUS_CLR 0xffffffe0 + #define APERF0_BW2_CTRL_BUS_MSB 4 + #define APERF0_BW2_CTRL_BUS_LSB 0 + #define APERF0_BW2_CTRL_BUS_RESET 0x0 + #define APERF0_BW2_CTRL_ID_BITS 12:8 + #define APERF0_BW2_CTRL_ID_SET 0x00001f00 + #define APERF0_BW2_CTRL_ID_CLR 0xffffe0ff + #define APERF0_BW2_CTRL_ID_MSB 12 + #define APERF0_BW2_CTRL_ID_LSB 8 + #define APERF0_BW2_CTRL_ID_RESET 0x0 + #define APERF0_BW2_CTRL_LATHALT_BITS 28:28 + #define APERF0_BW2_CTRL_LATHALT_SET 0x10000000 + #define APERF0_BW2_CTRL_LATHALT_CLR 0xefffffff + #define APERF0_BW2_CTRL_LATHALT_MSB 28 + #define APERF0_BW2_CTRL_LATHALT_LSB 28 + #define APERF0_BW2_CTRL_LATHALT_RESET 0x0 + #define APERF0_BW2_CTRL_ID_EN_BITS 29:29 + #define APERF0_BW2_CTRL_ID_EN_SET 0x20000000 + #define APERF0_BW2_CTRL_ID_EN_CLR 0xdfffffff + #define APERF0_BW2_CTRL_ID_EN_MSB 29 + #define APERF0_BW2_CTRL_ID_EN_LSB 29 + #define APERF0_BW2_CTRL_ID_EN_RESET 0x0 + #define APERF0_BW2_CTRL_EN_BITS 30:30 + #define APERF0_BW2_CTRL_EN_SET 0x40000000 + #define APERF0_BW2_CTRL_EN_CLR 0xbfffffff + #define APERF0_BW2_CTRL_EN_MSB 30 + #define APERF0_BW2_CTRL_EN_LSB 30 + #define APERF0_BW2_CTRL_EN_RESET 0x0 + #define APERF0_BW2_CTRL_RESET_BITS 31:31 + #define APERF0_BW2_CTRL_RESET_SET 0x80000000 + #define APERF0_BW2_CTRL_RESET_CLR 0x7fffffff + #define APERF0_BW2_CTRL_RESET_MSB 31 + #define APERF0_BW2_CTRL_RESET_LSB 31 + #define APERF0_BW2_CTRL_RESET_RESET 0x0 +#define APERF0_BW2_ATRANS HW_REGISTER_RO( 0x7e0098c4 ) + #define APERF0_BW2_ATRANS_MASK 0xffffffff + #define APERF0_BW2_ATRANS_WIDTH 32 + #define APERF0_BW2_ATRANS_RESET 0000000000 +#define APERF0_BW2_ATWAIT HW_REGISTER_RO( 0x7e0098c8 ) + #define APERF0_BW2_ATWAIT_MASK 0xffffffff + #define APERF0_BW2_ATWAIT_WIDTH 32 + #define APERF0_BW2_ATWAIT_RESET 0000000000 +#define APERF0_BW2_AMAX HW_REGISTER_RO( 0x7e0098cc ) + #define APERF0_BW2_AMAX_MASK 0x00ffffff + #define APERF0_BW2_AMAX_WIDTH 24 + #define APERF0_BW2_AMAX_RESET 0000000000 +#define APERF0_BW2_WTRANS HW_REGISTER_RO( 0x7e0098d0 ) + #define APERF0_BW2_WTRANS_MASK 0xffffffff + #define APERF0_BW2_WTRANS_WIDTH 32 + #define APERF0_BW2_WTRANS_RESET 0000000000 +#define APERF0_BW2_WTWAIT HW_REGISTER_RO( 0x7e0098d4 ) + #define APERF0_BW2_WTWAIT_MASK 0xffffffff + #define APERF0_BW2_WTWAIT_WIDTH 32 + #define APERF0_BW2_WTWAIT_RESET 0000000000 +#define APERF0_BW2_WMAX HW_REGISTER_RO( 0x7e0098d8 ) + #define APERF0_BW2_WMAX_MASK 0x0ff0ffff + #define APERF0_BW2_WMAX_WIDTH 28 + #define APERF0_BW2_WMAX_RESET 0000000000 +#define APERF0_BW2_RTRANS HW_REGISTER_RO( 0x7e0098dc ) + #define APERF0_BW2_RTRANS_MASK 0xffffffff + #define APERF0_BW2_RTRANS_WIDTH 32 + #define APERF0_BW2_RTRANS_RESET 0000000000 +#define APERF0_BW2_RTWAIT HW_REGISTER_RO( 0x7e0098e0 ) + #define APERF0_BW2_RTWAIT_MASK 0xffffffff + #define APERF0_BW2_RTWAIT_WIDTH 32 + #define APERF0_BW2_RTWAIT_RESET 0000000000 +#define APERF0_BW2_RMAX HW_REGISTER_RO( 0x7e0098e4 ) + #define APERF0_BW2_RMAX_MASK 0x00ffffff + #define APERF0_BW2_RMAX_WIDTH 24 + #define APERF0_BW2_RMAX_RESET 0000000000 +#define APERF0_BW2_RPEND HW_REGISTER_RO( 0x7e009868 ) + #define APERF0_BW2_RPEND_MASK 0x000000ff + #define APERF0_BW2_RPEND_WIDTH 8 + #define APERF0_BW2_RPEND_RESET 0000000000 diff --git a/bcm2708_chip/axi_performance1.h b/bcm2708_chip/axi_performance1.h new file mode 100755 index 0000000..9457b8e --- /dev/null +++ b/bcm2708_chip/axi_performance1.h @@ -0,0 +1,259 @@ +// This file was generated by the create_regs script +#define APERF1_BASE 0x7ee08000 +#define APERF1_APB_ID 0x41584950 +#define APERF1_GEN_CTRL HW_REGISTER_RW( 0x7ee08000 ) + #define APERF1_GEN_CTRL_MASK 0x00000003 + #define APERF1_GEN_CTRL_WIDTH 2 + #define APERF1_GEN_CTRL_RESET 0000000000 + #define APERF1_GEN_CTRL_ENABLE_BITS 0:0 + #define APERF1_GEN_CTRL_ENABLE_SET 0x00000001 + #define APERF1_GEN_CTRL_ENABLE_CLR 0xfffffffe + #define APERF1_GEN_CTRL_ENABLE_MSB 0 + #define APERF1_GEN_CTRL_ENABLE_LSB 0 + #define APERF1_GEN_CTRL_ENABLE_RESET 0x0 + #define APERF1_GEN_CTRL_RESET_BITS 1:1 + #define APERF1_GEN_CTRL_RESET_SET 0x00000002 + #define APERF1_GEN_CTRL_RESET_CLR 0xfffffffd + #define APERF1_GEN_CTRL_RESET_MSB 1 + #define APERF1_GEN_CTRL_RESET_LSB 1 + #define APERF1_GEN_CTRL_RESET_RESET 0x0 +#define APERF1_BW0_CTRL HW_REGISTER_RW( 0x7ee08040 ) + #define APERF1_BW0_CTRL_MASK 0xf0001f1f + #define APERF1_BW0_CTRL_WIDTH 32 + #define APERF1_BW0_CTRL_RESET 0000000000 + #define APERF1_BW0_CTRL_BUS_BITS 4:0 + #define APERF1_BW0_CTRL_BUS_SET 0x0000001f + #define APERF1_BW0_CTRL_BUS_CLR 0xffffffe0 + #define APERF1_BW0_CTRL_BUS_MSB 4 + #define APERF1_BW0_CTRL_BUS_LSB 0 + #define APERF1_BW0_CTRL_BUS_RESET 0x0 + #define APERF1_BW0_CTRL_ID_BITS 12:8 + #define APERF1_BW0_CTRL_ID_SET 0x00001f00 + #define APERF1_BW0_CTRL_ID_CLR 0xffffe0ff + #define APERF1_BW0_CTRL_ID_MSB 12 + #define APERF1_BW0_CTRL_ID_LSB 8 + #define APERF1_BW0_CTRL_ID_RESET 0x0 + #define APERF1_BW0_CTRL_LATHALT_BITS 28:28 + #define APERF1_BW0_CTRL_LATHALT_SET 0x10000000 + #define APERF1_BW0_CTRL_LATHALT_CLR 0xefffffff + #define APERF1_BW0_CTRL_LATHALT_MSB 28 + #define APERF1_BW0_CTRL_LATHALT_LSB 28 + #define APERF1_BW0_CTRL_LATHALT_RESET 0x0 + #define APERF1_BW0_CTRL_ID_EN_BITS 29:29 + #define APERF1_BW0_CTRL_ID_EN_SET 0x20000000 + #define APERF1_BW0_CTRL_ID_EN_CLR 0xdfffffff + #define APERF1_BW0_CTRL_ID_EN_MSB 29 + #define APERF1_BW0_CTRL_ID_EN_LSB 29 + #define APERF1_BW0_CTRL_ID_EN_RESET 0x0 + #define APERF1_BW0_CTRL_EN_BITS 30:30 + #define APERF1_BW0_CTRL_EN_SET 0x40000000 + #define APERF1_BW0_CTRL_EN_CLR 0xbfffffff + #define APERF1_BW0_CTRL_EN_MSB 30 + #define APERF1_BW0_CTRL_EN_LSB 30 + #define APERF1_BW0_CTRL_EN_RESET 0x0 + #define APERF1_BW0_CTRL_RESET_BITS 31:31 + #define APERF1_BW0_CTRL_RESET_SET 0x80000000 + #define APERF1_BW0_CTRL_RESET_CLR 0x7fffffff + #define APERF1_BW0_CTRL_RESET_MSB 31 + #define APERF1_BW0_CTRL_RESET_LSB 31 + #define APERF1_BW0_CTRL_RESET_RESET 0x0 +#define APERF1_BW0_ATRANS HW_REGISTER_RO( 0x7ee08044 ) + #define APERF1_BW0_ATRANS_MASK 0xffffffff + #define APERF1_BW0_ATRANS_WIDTH 32 + #define APERF1_BW0_ATRANS_RESET 0000000000 +#define APERF1_BW0_ATWAIT HW_REGISTER_RO( 0x7ee08048 ) + #define APERF1_BW0_ATWAIT_MASK 0xffffffff + #define APERF1_BW0_ATWAIT_WIDTH 32 + #define APERF1_BW0_ATWAIT_RESET 0000000000 +#define APERF1_BW0_AMAX HW_REGISTER_RO( 0x7ee0804c ) + #define APERF1_BW0_AMAX_MASK 0x00ffffff + #define APERF1_BW0_AMAX_WIDTH 24 + #define APERF1_BW0_AMAX_RESET 0000000000 +#define APERF1_BW0_WTRANS HW_REGISTER_RO( 0x7ee08050 ) + #define APERF1_BW0_WTRANS_MASK 0xffffffff + #define APERF1_BW0_WTRANS_WIDTH 32 + #define APERF1_BW0_WTRANS_RESET 0000000000 +#define APERF1_BW0_WTWAIT HW_REGISTER_RO( 0x7ee08054 ) + #define APERF1_BW0_WTWAIT_MASK 0xffffffff + #define APERF1_BW0_WTWAIT_WIDTH 32 + #define APERF1_BW0_WTWAIT_RESET 0000000000 +#define APERF1_BW0_WMAX HW_REGISTER_RO( 0x7ee08058 ) + #define APERF1_BW0_WMAX_MASK 0x00ffffff + #define APERF1_BW0_WMAX_WIDTH 24 + #define APERF1_BW0_WMAX_RESET 0000000000 +#define APERF1_BW0_RTRANS HW_REGISTER_RO( 0x7ee0805c ) + #define APERF1_BW0_RTRANS_MASK 0xffffffff + #define APERF1_BW0_RTRANS_WIDTH 32 + #define APERF1_BW0_RTRANS_RESET 0000000000 +#define APERF1_BW0_RTWAIT HW_REGISTER_RO( 0x7ee08060 ) + #define APERF1_BW0_RTWAIT_MASK 0xffffffff + #define APERF1_BW0_RTWAIT_WIDTH 32 + #define APERF1_BW0_RTWAIT_RESET 0000000000 +#define APERF1_BW0_RMAX HW_REGISTER_RO( 0x7ee08064 ) + #define APERF1_BW0_RMAX_MASK 0x00ffffff + #define APERF1_BW0_RMAX_WIDTH 24 + #define APERF1_BW0_RMAX_RESET 0000000000 +#define APERF1_BW0_RPEND HW_REGISTER_RO( 0x7ee08068 ) + #define APERF1_BW0_RPEND_MASK 0x000000ff + #define APERF1_BW0_RPEND_WIDTH 8 + #define APERF1_BW0_RPEND_RESET 0000000000 +#define APERF1_BW1_CTRL HW_REGISTER_RW( 0x7ee08080 ) + #define APERF1_BW1_CTRL_MASK 0xf0001f1f + #define APERF1_BW1_CTRL_WIDTH 32 + #define APERF1_BW1_CTRL_RESET 0000000000 + #define APERF1_BW1_CTRL_BUS_BITS 4:0 + #define APERF1_BW1_CTRL_BUS_SET 0x0000001f + #define APERF1_BW1_CTRL_BUS_CLR 0xffffffe0 + #define APERF1_BW1_CTRL_BUS_MSB 4 + #define APERF1_BW1_CTRL_BUS_LSB 0 + #define APERF1_BW1_CTRL_BUS_RESET 0x0 + #define APERF1_BW1_CTRL_ID_BITS 12:8 + #define APERF1_BW1_CTRL_ID_SET 0x00001f00 + #define APERF1_BW1_CTRL_ID_CLR 0xffffe0ff + #define APERF1_BW1_CTRL_ID_MSB 12 + #define APERF1_BW1_CTRL_ID_LSB 8 + #define APERF1_BW1_CTRL_ID_RESET 0x0 + #define APERF1_BW1_CTRL_LATHALT_BITS 28:28 + #define APERF1_BW1_CTRL_LATHALT_SET 0x10000000 + #define APERF1_BW1_CTRL_LATHALT_CLR 0xefffffff + #define APERF1_BW1_CTRL_LATHALT_MSB 28 + #define APERF1_BW1_CTRL_LATHALT_LSB 28 + #define APERF1_BW1_CTRL_LATHALT_RESET 0x0 + #define APERF1_BW1_CTRL_ID_EN_BITS 29:29 + #define APERF1_BW1_CTRL_ID_EN_SET 0x20000000 + #define APERF1_BW1_CTRL_ID_EN_CLR 0xdfffffff + #define APERF1_BW1_CTRL_ID_EN_MSB 29 + #define APERF1_BW1_CTRL_ID_EN_LSB 29 + #define APERF1_BW1_CTRL_ID_EN_RESET 0x0 + #define APERF1_BW1_CTRL_EN_BITS 30:30 + #define APERF1_BW1_CTRL_EN_SET 0x40000000 + #define APERF1_BW1_CTRL_EN_CLR 0xbfffffff + #define APERF1_BW1_CTRL_EN_MSB 30 + #define APERF1_BW1_CTRL_EN_LSB 30 + #define APERF1_BW1_CTRL_EN_RESET 0x0 + #define APERF1_BW1_CTRL_RESET_BITS 31:31 + #define APERF1_BW1_CTRL_RESET_SET 0x80000000 + #define APERF1_BW1_CTRL_RESET_CLR 0x7fffffff + #define APERF1_BW1_CTRL_RESET_MSB 31 + #define APERF1_BW1_CTRL_RESET_LSB 31 + #define APERF1_BW1_CTRL_RESET_RESET 0x0 +#define APERF1_BW1_ATRANS HW_REGISTER_RO( 0x7ee08084 ) + #define APERF1_BW1_ATRANS_MASK 0xffffffff + #define APERF1_BW1_ATRANS_WIDTH 32 + #define APERF1_BW1_ATRANS_RESET 0000000000 +#define APERF1_BW1_ATWAIT HW_REGISTER_RO( 0x7ee08088 ) + #define APERF1_BW1_ATWAIT_MASK 0xffffffff + #define APERF1_BW1_ATWAIT_WIDTH 32 + #define APERF1_BW1_ATWAIT_RESET 0000000000 +#define APERF1_BW1_AMAX HW_REGISTER_RO( 0x7ee0808c ) + #define APERF1_BW1_AMAX_MASK 0x00ffffff + #define APERF1_BW1_AMAX_WIDTH 24 + #define APERF1_BW1_AMAX_RESET 0000000000 +#define APERF1_BW1_WTRANS HW_REGISTER_RO( 0x7ee08090 ) + #define APERF1_BW1_WTRANS_MASK 0xffffffff + #define APERF1_BW1_WTRANS_WIDTH 32 + #define APERF1_BW1_WTRANS_RESET 0000000000 +#define APERF1_BW1_WTWAIT HW_REGISTER_RO( 0x7ee08094 ) + #define APERF1_BW1_WTWAIT_MASK 0xffffffff + #define APERF1_BW1_WTWAIT_WIDTH 32 + #define APERF1_BW1_WTWAIT_RESET 0000000000 +#define APERF1_BW1_WMAX HW_REGISTER_RO( 0x7ee08098 ) + #define APERF1_BW1_WMAX_MASK 0x0000ffff + #define APERF1_BW1_WMAX_WIDTH 16 + #define APERF1_BW1_WMAX_RESET 0000000000 +#define APERF1_BW1_RTRANS HW_REGISTER_RO( 0x7ee0809c ) + #define APERF1_BW1_RTRANS_MASK 0xffffffff + #define APERF1_BW1_RTRANS_WIDTH 32 + #define APERF1_BW1_RTRANS_RESET 0000000000 +#define APERF1_BW1_RTWAIT HW_REGISTER_RO( 0x7ee080a0 ) + #define APERF1_BW1_RTWAIT_MASK 0xffffffff + #define APERF1_BW1_RTWAIT_WIDTH 32 + #define APERF1_BW1_RTWAIT_RESET 0000000000 +#define APERF1_BW1_RMAX HW_REGISTER_RO( 0x7ee080a4 ) + #define APERF1_BW1_RMAX_MASK 0x00ffffff + #define APERF1_BW1_RMAX_WIDTH 24 + #define APERF1_BW1_RMAX_RESET 0000000000 +#define APERF1_BW1_RPEND HW_REGISTER_RO( 0x7ee08068 ) + #define APERF1_BW1_RPEND_MASK 0x000000ff + #define APERF1_BW1_RPEND_WIDTH 8 + #define APERF1_BW1_RPEND_RESET 0000000000 +#define APERF1_BW2_CTRL HW_REGISTER_RW( 0x7ee080c0 ) + #define APERF1_BW2_CTRL_MASK 0xf0001f1f + #define APERF1_BW2_CTRL_WIDTH 32 + #define APERF1_BW2_CTRL_RESET 0000000000 + #define APERF1_BW2_CTRL_BUS_BITS 4:0 + #define APERF1_BW2_CTRL_BUS_SET 0x0000001f + #define APERF1_BW2_CTRL_BUS_CLR 0xffffffe0 + #define APERF1_BW2_CTRL_BUS_MSB 4 + #define APERF1_BW2_CTRL_BUS_LSB 0 + #define APERF1_BW2_CTRL_BUS_RESET 0x0 + #define APERF1_BW2_CTRL_ID_BITS 12:8 + #define APERF1_BW2_CTRL_ID_SET 0x00001f00 + #define APERF1_BW2_CTRL_ID_CLR 0xffffe0ff + #define APERF1_BW2_CTRL_ID_MSB 12 + #define APERF1_BW2_CTRL_ID_LSB 8 + #define APERF1_BW2_CTRL_ID_RESET 0x0 + #define APERF1_BW2_CTRL_LATHALT_BITS 28:28 + #define APERF1_BW2_CTRL_LATHALT_SET 0x10000000 + #define APERF1_BW2_CTRL_LATHALT_CLR 0xefffffff + #define APERF1_BW2_CTRL_LATHALT_MSB 28 + #define APERF1_BW2_CTRL_LATHALT_LSB 28 + #define APERF1_BW2_CTRL_LATHALT_RESET 0x0 + #define APERF1_BW2_CTRL_ID_EN_BITS 29:29 + #define APERF1_BW2_CTRL_ID_EN_SET 0x20000000 + #define APERF1_BW2_CTRL_ID_EN_CLR 0xdfffffff + #define APERF1_BW2_CTRL_ID_EN_MSB 29 + #define APERF1_BW2_CTRL_ID_EN_LSB 29 + #define APERF1_BW2_CTRL_ID_EN_RESET 0x0 + #define APERF1_BW2_CTRL_EN_BITS 30:30 + #define APERF1_BW2_CTRL_EN_SET 0x40000000 + #define APERF1_BW2_CTRL_EN_CLR 0xbfffffff + #define APERF1_BW2_CTRL_EN_MSB 30 + #define APERF1_BW2_CTRL_EN_LSB 30 + #define APERF1_BW2_CTRL_EN_RESET 0x0 + #define APERF1_BW2_CTRL_RESET_BITS 31:31 + #define APERF1_BW2_CTRL_RESET_SET 0x80000000 + #define APERF1_BW2_CTRL_RESET_CLR 0x7fffffff + #define APERF1_BW2_CTRL_RESET_MSB 31 + #define APERF1_BW2_CTRL_RESET_LSB 31 + #define APERF1_BW2_CTRL_RESET_RESET 0x0 +#define APERF1_BW2_ATRANS HW_REGISTER_RO( 0x7ee080c4 ) + #define APERF1_BW2_ATRANS_MASK 0xffffffff + #define APERF1_BW2_ATRANS_WIDTH 32 + #define APERF1_BW2_ATRANS_RESET 0000000000 +#define APERF1_BW2_ATWAIT HW_REGISTER_RO( 0x7ee080c8 ) + #define APERF1_BW2_ATWAIT_MASK 0xffffffff + #define APERF1_BW2_ATWAIT_WIDTH 32 + #define APERF1_BW2_ATWAIT_RESET 0000000000 +#define APERF1_BW2_AMAX HW_REGISTER_RO( 0x7ee080cc ) + #define APERF1_BW2_AMAX_MASK 0x00ffffff + #define APERF1_BW2_AMAX_WIDTH 24 + #define APERF1_BW2_AMAX_RESET 0000000000 +#define APERF1_BW2_WTRANS HW_REGISTER_RO( 0x7ee080d0 ) + #define APERF1_BW2_WTRANS_MASK 0xffffffff + #define APERF1_BW2_WTRANS_WIDTH 32 + #define APERF1_BW2_WTRANS_RESET 0000000000 +#define APERF1_BW2_WTWAIT HW_REGISTER_RO( 0x7ee080d4 ) + #define APERF1_BW2_WTWAIT_MASK 0xffffffff + #define APERF1_BW2_WTWAIT_WIDTH 32 + #define APERF1_BW2_WTWAIT_RESET 0000000000 +#define APERF1_BW2_WMAX HW_REGISTER_RO( 0x7ee080d8 ) + #define APERF1_BW2_WMAX_MASK 0x0ff0ffff + #define APERF1_BW2_WMAX_WIDTH 28 + #define APERF1_BW2_WMAX_RESET 0000000000 +#define APERF1_BW2_RTRANS HW_REGISTER_RO( 0x7ee080dc ) + #define APERF1_BW2_RTRANS_MASK 0xffffffff + #define APERF1_BW2_RTRANS_WIDTH 32 + #define APERF1_BW2_RTRANS_RESET 0000000000 +#define APERF1_BW2_RTWAIT HW_REGISTER_RO( 0x7ee080e0 ) + #define APERF1_BW2_RTWAIT_MASK 0xffffffff + #define APERF1_BW2_RTWAIT_WIDTH 32 + #define APERF1_BW2_RTWAIT_RESET 0000000000 +#define APERF1_BW2_RMAX HW_REGISTER_RO( 0x7ee080e4 ) + #define APERF1_BW2_RMAX_MASK 0x00ffffff + #define APERF1_BW2_RMAX_WIDTH 24 + #define APERF1_BW2_RMAX_RESET 0000000000 +#define APERF1_BW2_RPEND HW_REGISTER_RO( 0x7ee08068 ) + #define APERF1_BW2_RPEND_MASK 0x000000ff + #define APERF1_BW2_RPEND_WIDTH 8 + #define APERF1_BW2_RPEND_RESET 0000000000 diff --git a/bcm2708_chip/cam0.h b/bcm2708_chip/cam0.h new file mode 100755 index 0000000..1236d8e --- /dev/null +++ b/bcm2708_chip/cam0.h @@ -0,0 +1,199 @@ +// This file was generated by the create_regs script +#define CAM0_BASE 0x7e800000 +#define CAM0_APB_ID 0x7563616d +#define CAM0_CAMCTL HW_REGISTER_RW( 0x7e800000 ) + #define CAM0_CAMCTL_MASK 0xffffffff + #define CAM0_CAMCTL_WIDTH 32 + #define CAM0_CAMCTL_RESET 0000000000 +#define CAM0_CAMSTA HW_REGISTER_RW( 0x7e800004 ) + #define CAM0_CAMSTA_MASK 0xffffffff + #define CAM0_CAMSTA_WIDTH 32 + #define CAM0_CAMSTA_RESET 0000000000 +#define CAM0_CAMANA HW_REGISTER_RW( 0x7e800008 ) + #define CAM0_CAMANA_MASK 0xffffffff + #define CAM0_CAMANA_WIDTH 32 + #define CAM0_CAMANA_RESET 0x00000777 +#define CAM0_CAMPRI HW_REGISTER_RW( 0x7e80000c ) + #define CAM0_CAMPRI_MASK 0xffffffff + #define CAM0_CAMPRI_WIDTH 32 + #define CAM0_CAMPRI_RESET 0000000000 +#define CAM0_CAMCLK HW_REGISTER_RW( 0x7e800010 ) + #define CAM0_CAMCLK_MASK 0xffffffff + #define CAM0_CAMCLK_WIDTH 32 + #define CAM0_CAMCLK_RESET 0x00000002 +#define CAM0_CAMCLT HW_REGISTER_RW( 0x7e800014 ) + #define CAM0_CAMCLT_MASK 0xffffffff + #define CAM0_CAMCLT_WIDTH 32 + #define CAM0_CAMCLT_RESET 0000000000 +#define CAM0_CAMDAT0 HW_REGISTER_RW( 0x7e800018 ) + #define CAM0_CAMDAT0_MASK 0xffffffff + #define CAM0_CAMDAT0_WIDTH 32 + #define CAM0_CAMDAT0_RESET 0x00000002 +#define CAM0_CAMDAT1 HW_REGISTER_RW( 0x7e80001c ) + #define CAM0_CAMDAT1_MASK 0xffffffff + #define CAM0_CAMDAT1_WIDTH 32 + #define CAM0_CAMDAT1_RESET 0x00000002 +#define CAM0_CAMDAT2 HW_REGISTER_RW( 0x7e800020 ) + #define CAM0_CAMDAT2_MASK 0xffffffff + #define CAM0_CAMDAT2_WIDTH 32 + #define CAM0_CAMDAT2_RESET 0x00000002 +#define CAM0_CAMDAT3 HW_REGISTER_RW( 0x7e800024 ) + #define CAM0_CAMDAT3_MASK 0xffffffff + #define CAM0_CAMDAT3_WIDTH 32 + #define CAM0_CAMDAT3_RESET 0x00000002 +#define CAM0_CAMDLT HW_REGISTER_RW( 0x7e800028 ) + #define CAM0_CAMDLT_MASK 0xffffffff + #define CAM0_CAMDLT_WIDTH 32 + #define CAM0_CAMDLT_RESET 0000000000 +#define CAM0_CAMCMP0 HW_REGISTER_RW( 0x7e80002c ) + #define CAM0_CAMCMP0_MASK 0xffffffff + #define CAM0_CAMCMP0_WIDTH 32 + #define CAM0_CAMCMP0_RESET 0000000000 +#define CAM0_CAMCMP1 HW_REGISTER_RW( 0x7e800030 ) + #define CAM0_CAMCMP1_MASK 0xffffffff + #define CAM0_CAMCMP1_WIDTH 32 + #define CAM0_CAMCMP1_RESET 0000000000 +#define CAM0_CAMCAP0 HW_REGISTER_RW( 0x7e800034 ) + #define CAM0_CAMCAP0_MASK 0xffffffff + #define CAM0_CAMCAP0_WIDTH 32 + #define CAM0_CAMCAP0_RESET 0000000000 +#define CAM0_CAMCAP1 HW_REGISTER_RW( 0x7e800038 ) + #define CAM0_CAMCAP1_MASK 0xffffffff + #define CAM0_CAMCAP1_WIDTH 32 + #define CAM0_CAMCAP1_RESET 0000000000 +#define CAM0_CAMDBG0 HW_REGISTER_RW( 0x7e8000f0 ) + #define CAM0_CAMDBG0_MASK 0xffffffff + #define CAM0_CAMDBG0_WIDTH 32 + #define CAM0_CAMDBG0_RESET 0000000000 +#define CAM0_CAMDBG1 HW_REGISTER_RW( 0x7e8000f4 ) + #define CAM0_CAMDBG1_MASK 0xffffffff + #define CAM0_CAMDBG1_WIDTH 32 + #define CAM0_CAMDBG1_RESET 0000000000 +#define CAM0_CAMDBG2 HW_REGISTER_RW( 0x7e8000f8 ) + #define CAM0_CAMDBG2_MASK 0xffffffff + #define CAM0_CAMDBG2_WIDTH 32 + #define CAM0_CAMDBG2_RESET 0000000000 +#define CAM0_CAMDBG3 HW_REGISTER_RW( 0x7e8000fc ) + #define CAM0_CAMDBG3_MASK 0xffffffff + #define CAM0_CAMDBG3_WIDTH 32 + #define CAM0_CAMDBG3_RESET 0000000000 +#define CAM0_CAMICTL HW_REGISTER_RW( 0x7e800100 ) + #define CAM0_CAMICTL_MASK 0xffffffff + #define CAM0_CAMICTL_WIDTH 32 + #define CAM0_CAMICTL_RESET 0000000000 +#define CAM0_CAMISTA HW_REGISTER_RW( 0x7e800104 ) + #define CAM0_CAMISTA_MASK 0xffffffff + #define CAM0_CAMISTA_WIDTH 32 + #define CAM0_CAMISTA_RESET 0000000000 +#define CAM0_CAMIDI0 HW_REGISTER_RW( 0x7e800108 ) + #define CAM0_CAMIDI0_MASK 0xffffffff + #define CAM0_CAMIDI0_WIDTH 32 + #define CAM0_CAMIDI0_RESET 0000000000 +#define CAM0_CAMIPIPE HW_REGISTER_RW( 0x7e80010c ) + #define CAM0_CAMIPIPE_MASK 0xffffffff + #define CAM0_CAMIPIPE_WIDTH 32 + #define CAM0_CAMIPIPE_RESET 0000000000 +#define CAM0_CAMIBSA0 HW_REGISTER_RW( 0x7e800110 ) + #define CAM0_CAMIBSA0_MASK 0xffffffff + #define CAM0_CAMIBSA0_WIDTH 32 + #define CAM0_CAMIBSA0_RESET 0000000000 +#define CAM0_CAMIBEA0 HW_REGISTER_RW( 0x7e800114 ) + #define CAM0_CAMIBEA0_MASK 0xffffffff + #define CAM0_CAMIBEA0_WIDTH 32 + #define CAM0_CAMIBEA0_RESET 0000000000 +#define CAM0_CAMIBLS HW_REGISTER_RW( 0x7e800118 ) + #define CAM0_CAMIBLS_MASK 0xffffffff + #define CAM0_CAMIBLS_WIDTH 32 + #define CAM0_CAMIBLS_RESET 0000000000 +#define CAM0_CAMIBWP HW_REGISTER_RW( 0x7e80011c ) + #define CAM0_CAMIBWP_MASK 0xffffffff + #define CAM0_CAMIBWP_WIDTH 32 + #define CAM0_CAMIBWP_RESET 0000000000 +#define CAM0_CAMIHWIN HW_REGISTER_RW( 0x7e800120 ) + #define CAM0_CAMIHWIN_MASK 0xffffffff + #define CAM0_CAMIHWIN_WIDTH 32 + #define CAM0_CAMIHWIN_RESET 0000000000 +#define CAM0_CAMIHSTA HW_REGISTER_RW( 0x7e800124 ) + #define CAM0_CAMIHSTA_MASK 0xffffffff + #define CAM0_CAMIHSTA_WIDTH 32 + #define CAM0_CAMIHSTA_RESET 0000000000 +#define CAM0_CAMIVWIN HW_REGISTER_RW( 0x7e800128 ) + #define CAM0_CAMIVWIN_MASK 0xffffffff + #define CAM0_CAMIVWIN_WIDTH 32 + #define CAM0_CAMIVWIN_RESET 0000000000 +#define CAM0_CAMIVSTA HW_REGISTER_RW( 0x7e80012c ) + #define CAM0_CAMIVSTA_MASK 0xffffffff + #define CAM0_CAMIVSTA_WIDTH 32 + #define CAM0_CAMIVSTA_RESET 0000000000 +#define CAM0_CAMICC HW_REGISTER_RW( 0x7e800130 ) + #define CAM0_CAMICC_MASK 0xffffffff + #define CAM0_CAMICC_WIDTH 32 + #define CAM0_CAMICC_RESET 0000000000 +#define CAM0_CAMICS HW_REGISTER_RW( 0x7e800134 ) + #define CAM0_CAMICS_MASK 0xffffffff + #define CAM0_CAMICS_WIDTH 32 + #define CAM0_CAMICS_RESET 0000000000 +#define CAM0_CAMIDC HW_REGISTER_RW( 0x7e800138 ) + #define CAM0_CAMIDC_MASK 0xffffffff + #define CAM0_CAMIDC_WIDTH 32 + #define CAM0_CAMIDC_RESET 0000000000 +#define CAM0_CAMIDPO HW_REGISTER_RW( 0x7e80013c ) + #define CAM0_CAMIDPO_MASK 0xffffffff + #define CAM0_CAMIDPO_WIDTH 32 + #define CAM0_CAMIDPO_RESET 0000000000 +#define CAM0_CAMIDCA HW_REGISTER_RW( 0x7e800140 ) + #define CAM0_CAMIDCA_MASK 0xffffffff + #define CAM0_CAMIDCA_WIDTH 32 + #define CAM0_CAMIDCA_RESET 0000000000 +#define CAM0_CAMIDCD HW_REGISTER_RW( 0x7e800144 ) + #define CAM0_CAMIDCD_MASK 0xffffffff + #define CAM0_CAMIDCD_WIDTH 32 + #define CAM0_CAMIDCD_RESET 0000000000 +#define CAM0_CAMIDS HW_REGISTER_RW( 0x7e800148 ) + #define CAM0_CAMIDS_MASK 0xffffffff + #define CAM0_CAMIDS_WIDTH 32 + #define CAM0_CAMIDS_RESET 0000000000 +#define CAM0_CAMDCS HW_REGISTER_RW( 0x7e800200 ) + #define CAM0_CAMDCS_MASK 0xffffffff + #define CAM0_CAMDCS_WIDTH 32 + #define CAM0_CAMDCS_RESET 0000000000 +#define CAM0_CAMDBSA0 HW_REGISTER_RW( 0x7e800204 ) + #define CAM0_CAMDBSA0_MASK 0xffffffff + #define CAM0_CAMDBSA0_WIDTH 32 + #define CAM0_CAMDBSA0_RESET 0000000000 +#define CAM0_CAMDBEA0 HW_REGISTER_RW( 0x7e800208 ) + #define CAM0_CAMDBEA0_MASK 0xffffffff + #define CAM0_CAMDBEA0_WIDTH 32 + #define CAM0_CAMDBEA0_RESET 0000000000 +#define CAM0_CAMDBWP HW_REGISTER_RW( 0x7e80020c ) + #define CAM0_CAMDBWP_MASK 0xffffffff + #define CAM0_CAMDBWP_WIDTH 32 + #define CAM0_CAMDBWP_RESET 0000000000 +#define CAM0_CAMDBCTL HW_REGISTER_RW( 0x7e800300 ) + #define CAM0_CAMDBCTL_MASK 0xffffffff + #define CAM0_CAMDBCTL_WIDTH 32 + #define CAM0_CAMDBCTL_RESET 0000000000 +#define CAM0_CAMIBSA1 HW_REGISTER_RW( 0x7e800304 ) + #define CAM0_CAMIBSA1_MASK 0xffffffff + #define CAM0_CAMIBSA1_WIDTH 32 + #define CAM0_CAMIBSA1_RESET 0000000000 +#define CAM0_CAMIBEA1 HW_REGISTER_RW( 0x7e800308 ) + #define CAM0_CAMIBEA1_MASK 0xffffffff + #define CAM0_CAMIBEA1_WIDTH 32 + #define CAM0_CAMIBEA1_RESET 0000000000 +#define CAM0_CAMIDI1 HW_REGISTER_RW( 0x7e80030c ) + #define CAM0_CAMIDI1_MASK 0xffffffff + #define CAM0_CAMIDI1_WIDTH 32 + #define CAM0_CAMIDI1_RESET 0000000000 +#define CAM0_CAMDBSA1 HW_REGISTER_RW( 0x7e800310 ) + #define CAM0_CAMDBSA1_MASK 0xffffffff + #define CAM0_CAMDBSA1_WIDTH 32 + #define CAM0_CAMDBSA1_RESET 0000000000 +#define CAM0_CAMDBEA1 HW_REGISTER_RW( 0x7e800314 ) + #define CAM0_CAMDBEA1_MASK 0xffffffff + #define CAM0_CAMDBEA1_WIDTH 32 + #define CAM0_CAMDBEA1_RESET 0000000000 +#define CAM0_CAMMISC HW_REGISTER_RW( 0x7e800400 ) + #define CAM0_CAMMISC_MASK 0xffffffff + #define CAM0_CAMMISC_WIDTH 32 + #define CAM0_CAMMISC_RESET 0000000000 diff --git a/bcm2708_chip/cam0_a0.h b/bcm2708_chip/cam0_a0.h new file mode 100755 index 0000000..c6d1126 --- /dev/null +++ b/bcm2708_chip/cam0_a0.h @@ -0,0 +1,131 @@ +// This file was generated by the create_regs script +#define CAM0_BASE 0x7e800000 +#define CAM0_APB_ID 0x7563616d +#define CAM0_CTL HW_REGISTER_RW( 0x7e800000 ) + #define CAM0_CTL_MASK 0xffffffff + #define CAM0_CTL_WIDTH 32 + #define CAM0_CTL_RESET 0000000000 +#define CAM0_STA HW_REGISTER_RW( 0x7e800004 ) + #define CAM0_STA_MASK 0xffffffff + #define CAM0_STA_WIDTH 32 + #define CAM0_STA_RESET 0000000000 +#define CAM0_ANA HW_REGISTER_RW( 0x7e800008 ) + #define CAM0_ANA_MASK 0xffffffff + #define CAM0_ANA_WIDTH 32 + #define CAM0_ANA_RESET 0000000000 +#define CAM0_PRI HW_REGISTER_RW( 0x7e80000c ) + #define CAM0_PRI_MASK 0xffffffff + #define CAM0_PRI_WIDTH 32 + #define CAM0_PRI_RESET 0000000000 +#define CAM0_CLK HW_REGISTER_RW( 0x7e800010 ) + #define CAM0_CLK_MASK 0xffffffff + #define CAM0_CLK_WIDTH 32 + #define CAM0_CLK_RESET 0000000000 +#define CAM0_DAT0 HW_REGISTER_RW( 0x7e800014 ) + #define CAM0_DAT0_MASK 0xffffffff + #define CAM0_DAT0_WIDTH 32 + #define CAM0_DAT0_RESET 0000000000 +#define CAM0_DAT1 HW_REGISTER_RW( 0x7e800018 ) + #define CAM0_DAT1_MASK 0xffffffff + #define CAM0_DAT1_WIDTH 32 + #define CAM0_DAT1_RESET 0000000000 +#define CAM0_DAT2 HW_REGISTER_RW( 0x7e80001c ) + #define CAM0_DAT2_MASK 0xffffffff + #define CAM0_DAT2_WIDTH 32 + #define CAM0_DAT2_RESET 0000000000 +#define CAM0_DAT3 HW_REGISTER_RW( 0x7e800020 ) + #define CAM0_DAT3_MASK 0xffffffff + #define CAM0_DAT3_WIDTH 32 + #define CAM0_DAT3_RESET 0000000000 +#define CAM0_CMP0 HW_REGISTER_RW( 0x7e800024 ) + #define CAM0_CMP0_MASK 0xffffffff + #define CAM0_CMP0_WIDTH 32 + #define CAM0_CMP0_RESET 0000000000 +#define CAM0_CMP1 HW_REGISTER_RW( 0x7e800028 ) + #define CAM0_CMP1_MASK 0xffffffff + #define CAM0_CMP1_WIDTH 32 + #define CAM0_CMP1_RESET 0000000000 +#define CAM0_CAP0 HW_REGISTER_RW( 0x7e80002c ) + #define CAM0_CAP0_MASK 0xffffffff + #define CAM0_CAP0_WIDTH 32 + #define CAM0_CAP0_RESET 0000000000 +#define CAM0_CAP1 HW_REGISTER_RW( 0x7e800030 ) + #define CAM0_CAP1_MASK 0xffffffff + #define CAM0_CAP1_WIDTH 32 + #define CAM0_CAP1_RESET 0000000000 +#define CAM0_DBG0 HW_REGISTER_RW( 0x7e8000f0 ) + #define CAM0_DBG0_MASK 0xffffffff + #define CAM0_DBG0_WIDTH 32 + #define CAM0_DBG0_RESET 0000000000 +#define CAM0_DBG1 HW_REGISTER_RW( 0x7e8000f4 ) + #define CAM0_DBG1_MASK 0xffffffff + #define CAM0_DBG1_WIDTH 32 + #define CAM0_DBG1_RESET 0000000000 +#define CAM0_DBG2 HW_REGISTER_RW( 0x7e8000f8 ) + #define CAM0_DBG2_MASK 0xffffffff + #define CAM0_DBG2_WIDTH 32 + #define CAM0_DBG2_RESET 0000000000 +#define CAM0_ICTL HW_REGISTER_RW( 0x7e800100 ) + #define CAM0_ICTL_MASK 0xffffffff + #define CAM0_ICTL_WIDTH 32 + #define CAM0_ICTL_RESET 0000000000 +#define CAM0_ISTA HW_REGISTER_RW( 0x7e800104 ) + #define CAM0_ISTA_MASK 0xffffffff + #define CAM0_ISTA_WIDTH 32 + #define CAM0_ISTA_RESET 0000000000 +#define CAM0_IDI HW_REGISTER_RW( 0x7e800108 ) + #define CAM0_IDI_MASK 0xffffffff + #define CAM0_IDI_WIDTH 32 + #define CAM0_IDI_RESET 0000000000 +#define CAM0_IPIPE HW_REGISTER_RW( 0x7e80010c ) + #define CAM0_IPIPE_MASK 0xffffffff + #define CAM0_IPIPE_WIDTH 32 + #define CAM0_IPIPE_RESET 0000000000 +#define CAM0_IBSA HW_REGISTER_RW( 0x7e800110 ) + #define CAM0_IBSA_MASK 0xffffffff + #define CAM0_IBSA_WIDTH 32 + #define CAM0_IBSA_RESET 0000000000 +#define CAM0_IBEA HW_REGISTER_RW( 0x7e800114 ) + #define CAM0_IBEA_MASK 0xffffffff + #define CAM0_IBEA_WIDTH 32 + #define CAM0_IBEA_RESET 0000000000 +#define CAM0_IBLS HW_REGISTER_RW( 0x7e800118 ) + #define CAM0_IBLS_MASK 0xffffffff + #define CAM0_IBLS_WIDTH 32 + #define CAM0_IBLS_RESET 0000000000 +#define CAM0_IBWP HW_REGISTER_RW( 0x7e80011c ) + #define CAM0_IBWP_MASK 0xffffffff + #define CAM0_IBWP_WIDTH 32 + #define CAM0_IBWP_RESET 0000000000 +#define CAM0_IHWIN HW_REGISTER_RW( 0x7e800120 ) + #define CAM0_IHWIN_MASK 0xffffffff + #define CAM0_IHWIN_WIDTH 32 + #define CAM0_IHWIN_RESET 0000000000 +#define CAM0_IHSTA HW_REGISTER_RW( 0x7e800124 ) + #define CAM0_IHSTA_MASK 0xffffffff + #define CAM0_IHSTA_WIDTH 32 + #define CAM0_IHSTA_RESET 0000000000 +#define CAM0_IVWIN HW_REGISTER_RW( 0x7e800128 ) + #define CAM0_IVWIN_MASK 0xffffffff + #define CAM0_IVWIN_WIDTH 32 + #define CAM0_IVWIN_RESET 0000000000 +#define CAM0_IVSTA HW_REGISTER_RW( 0x7e80012c ) + #define CAM0_IVSTA_MASK 0xffffffff + #define CAM0_IVSTA_WIDTH 32 + #define CAM0_IVSTA_RESET 0000000000 +#define CAM0_DCS HW_REGISTER_RW( 0x7e800200 ) + #define CAM0_DCS_MASK 0xffffffff + #define CAM0_DCS_WIDTH 32 + #define CAM0_DCS_RESET 0000000000 +#define CAM0_DBSA HW_REGISTER_RW( 0x7e800204 ) + #define CAM0_DBSA_MASK 0xffffffff + #define CAM0_DBSA_WIDTH 32 + #define CAM0_DBSA_RESET 0000000000 +#define CAM0_DBEA HW_REGISTER_RW( 0x7e800208 ) + #define CAM0_DBEA_MASK 0xffffffff + #define CAM0_DBEA_WIDTH 32 + #define CAM0_DBEA_RESET 0000000000 +#define CAM0_DBWP HW_REGISTER_RW( 0x7e800208 ) + #define CAM0_DBWP_MASK 0xffffffff + #define CAM0_DBWP_WIDTH 32 + #define CAM0_DBWP_RESET 0000000000 diff --git a/bcm2708_chip/cam1.h b/bcm2708_chip/cam1.h new file mode 100755 index 0000000..c7c0504 --- /dev/null +++ b/bcm2708_chip/cam1.h @@ -0,0 +1,199 @@ +// This file was generated by the create_regs script +#define CAM1_BASE 0x7e801000 +#define CAM1_APB_ID 0x7563616d +#define CAM1_CAMCTL HW_REGISTER_RW( 0x7e801000 ) + #define CAM1_CAMCTL_MASK 0xffffffff + #define CAM1_CAMCTL_WIDTH 32 + #define CAM1_CAMCTL_RESET 0000000000 +#define CAM1_CAMSTA HW_REGISTER_RW( 0x7e801004 ) + #define CAM1_CAMSTA_MASK 0xffffffff + #define CAM1_CAMSTA_WIDTH 32 + #define CAM1_CAMSTA_RESET 0000000000 +#define CAM1_CAMANA HW_REGISTER_RW( 0x7e801008 ) + #define CAM1_CAMANA_MASK 0xffffffff + #define CAM1_CAMANA_WIDTH 32 + #define CAM1_CAMANA_RESET 0x00000777 +#define CAM1_CAMPRI HW_REGISTER_RW( 0x7e80100c ) + #define CAM1_CAMPRI_MASK 0xffffffff + #define CAM1_CAMPRI_WIDTH 32 + #define CAM1_CAMPRI_RESET 0000000000 +#define CAM1_CAMCLK HW_REGISTER_RW( 0x7e801010 ) + #define CAM1_CAMCLK_MASK 0xffffffff + #define CAM1_CAMCLK_WIDTH 32 + #define CAM1_CAMCLK_RESET 0x00000002 +#define CAM1_CAMCLT HW_REGISTER_RW( 0x7e801014 ) + #define CAM1_CAMCLT_MASK 0xffffffff + #define CAM1_CAMCLT_WIDTH 32 + #define CAM1_CAMCLT_RESET 0000000000 +#define CAM1_CAMDAT0 HW_REGISTER_RW( 0x7e801018 ) + #define CAM1_CAMDAT0_MASK 0xffffffff + #define CAM1_CAMDAT0_WIDTH 32 + #define CAM1_CAMDAT0_RESET 0x00000002 +#define CAM1_CAMDAT1 HW_REGISTER_RW( 0x7e80101c ) + #define CAM1_CAMDAT1_MASK 0xffffffff + #define CAM1_CAMDAT1_WIDTH 32 + #define CAM1_CAMDAT1_RESET 0x00000002 +#define CAM1_CAMDAT2 HW_REGISTER_RW( 0x7e801020 ) + #define CAM1_CAMDAT2_MASK 0xffffffff + #define CAM1_CAMDAT2_WIDTH 32 + #define CAM1_CAMDAT2_RESET 0x00000002 +#define CAM1_CAMDAT3 HW_REGISTER_RW( 0x7e801024 ) + #define CAM1_CAMDAT3_MASK 0xffffffff + #define CAM1_CAMDAT3_WIDTH 32 + #define CAM1_CAMDAT3_RESET 0x00000002 +#define CAM1_CAMDLT HW_REGISTER_RW( 0x7e801028 ) + #define CAM1_CAMDLT_MASK 0xffffffff + #define CAM1_CAMDLT_WIDTH 32 + #define CAM1_CAMDLT_RESET 0000000000 +#define CAM1_CAMCMP0 HW_REGISTER_RW( 0x7e80102c ) + #define CAM1_CAMCMP0_MASK 0xffffffff + #define CAM1_CAMCMP0_WIDTH 32 + #define CAM1_CAMCMP0_RESET 0000000000 +#define CAM1_CAMCMP1 HW_REGISTER_RW( 0x7e801030 ) + #define CAM1_CAMCMP1_MASK 0xffffffff + #define CAM1_CAMCMP1_WIDTH 32 + #define CAM1_CAMCMP1_RESET 0000000000 +#define CAM1_CAMCAP0 HW_REGISTER_RW( 0x7e801034 ) + #define CAM1_CAMCAP0_MASK 0xffffffff + #define CAM1_CAMCAP0_WIDTH 32 + #define CAM1_CAMCAP0_RESET 0000000000 +#define CAM1_CAMCAP1 HW_REGISTER_RW( 0x7e801038 ) + #define CAM1_CAMCAP1_MASK 0xffffffff + #define CAM1_CAMCAP1_WIDTH 32 + #define CAM1_CAMCAP1_RESET 0000000000 +#define CAM1_CAMDBG0 HW_REGISTER_RW( 0x7e8010f0 ) + #define CAM1_CAMDBG0_MASK 0xffffffff + #define CAM1_CAMDBG0_WIDTH 32 + #define CAM1_CAMDBG0_RESET 0000000000 +#define CAM1_CAMDBG1 HW_REGISTER_RW( 0x7e8010f4 ) + #define CAM1_CAMDBG1_MASK 0xffffffff + #define CAM1_CAMDBG1_WIDTH 32 + #define CAM1_CAMDBG1_RESET 0000000000 +#define CAM1_CAMDBG2 HW_REGISTER_RW( 0x7e8010f8 ) + #define CAM1_CAMDBG2_MASK 0xffffffff + #define CAM1_CAMDBG2_WIDTH 32 + #define CAM1_CAMDBG2_RESET 0000000000 +#define CAM1_CAMDBG3 HW_REGISTER_RW( 0x7e8010fc ) + #define CAM1_CAMDBG3_MASK 0xffffffff + #define CAM1_CAMDBG3_WIDTH 32 + #define CAM1_CAMDBG3_RESET 0000000000 +#define CAM1_CAMICTL HW_REGISTER_RW( 0x7e801100 ) + #define CAM1_CAMICTL_MASK 0xffffffff + #define CAM1_CAMICTL_WIDTH 32 + #define CAM1_CAMICTL_RESET 0000000000 +#define CAM1_CAMISTA HW_REGISTER_RW( 0x7e801104 ) + #define CAM1_CAMISTA_MASK 0xffffffff + #define CAM1_CAMISTA_WIDTH 32 + #define CAM1_CAMISTA_RESET 0000000000 +#define CAM1_CAMIDI0 HW_REGISTER_RW( 0x7e801108 ) + #define CAM1_CAMIDI0_MASK 0xffffffff + #define CAM1_CAMIDI0_WIDTH 32 + #define CAM1_CAMIDI0_RESET 0000000000 +#define CAM1_CAMIPIPE HW_REGISTER_RW( 0x7e80110c ) + #define CAM1_CAMIPIPE_MASK 0xffffffff + #define CAM1_CAMIPIPE_WIDTH 32 + #define CAM1_CAMIPIPE_RESET 0000000000 +#define CAM1_CAMIBSA0 HW_REGISTER_RW( 0x7e801110 ) + #define CAM1_CAMIBSA0_MASK 0xffffffff + #define CAM1_CAMIBSA0_WIDTH 32 + #define CAM1_CAMIBSA0_RESET 0000000000 +#define CAM1_CAMIBEA0 HW_REGISTER_RW( 0x7e801114 ) + #define CAM1_CAMIBEA0_MASK 0xffffffff + #define CAM1_CAMIBEA0_WIDTH 32 + #define CAM1_CAMIBEA0_RESET 0000000000 +#define CAM1_CAMIBLS HW_REGISTER_RW( 0x7e801118 ) + #define CAM1_CAMIBLS_MASK 0xffffffff + #define CAM1_CAMIBLS_WIDTH 32 + #define CAM1_CAMIBLS_RESET 0000000000 +#define CAM1_CAMIBWP HW_REGISTER_RW( 0x7e80111c ) + #define CAM1_CAMIBWP_MASK 0xffffffff + #define CAM1_CAMIBWP_WIDTH 32 + #define CAM1_CAMIBWP_RESET 0000000000 +#define CAM1_CAMIHWIN HW_REGISTER_RW( 0x7e801120 ) + #define CAM1_CAMIHWIN_MASK 0xffffffff + #define CAM1_CAMIHWIN_WIDTH 32 + #define CAM1_CAMIHWIN_RESET 0000000000 +#define CAM1_CAMIHSTA HW_REGISTER_RW( 0x7e801124 ) + #define CAM1_CAMIHSTA_MASK 0xffffffff + #define CAM1_CAMIHSTA_WIDTH 32 + #define CAM1_CAMIHSTA_RESET 0000000000 +#define CAM1_CAMIVWIN HW_REGISTER_RW( 0x7e801128 ) + #define CAM1_CAMIVWIN_MASK 0xffffffff + #define CAM1_CAMIVWIN_WIDTH 32 + #define CAM1_CAMIVWIN_RESET 0000000000 +#define CAM1_CAMIVSTA HW_REGISTER_RW( 0x7e80112c ) + #define CAM1_CAMIVSTA_MASK 0xffffffff + #define CAM1_CAMIVSTA_WIDTH 32 + #define CAM1_CAMIVSTA_RESET 0000000000 +#define CAM1_CAMICC HW_REGISTER_RW( 0x7e801130 ) + #define CAM1_CAMICC_MASK 0xffffffff + #define CAM1_CAMICC_WIDTH 32 + #define CAM1_CAMICC_RESET 0000000000 +#define CAM1_CAMICS HW_REGISTER_RW( 0x7e801134 ) + #define CAM1_CAMICS_MASK 0xffffffff + #define CAM1_CAMICS_WIDTH 32 + #define CAM1_CAMICS_RESET 0000000000 +#define CAM1_CAMIDC HW_REGISTER_RW( 0x7e801138 ) + #define CAM1_CAMIDC_MASK 0xffffffff + #define CAM1_CAMIDC_WIDTH 32 + #define CAM1_CAMIDC_RESET 0000000000 +#define CAM1_CAMIDPO HW_REGISTER_RW( 0x7e80113c ) + #define CAM1_CAMIDPO_MASK 0xffffffff + #define CAM1_CAMIDPO_WIDTH 32 + #define CAM1_CAMIDPO_RESET 0000000000 +#define CAM1_CAMIDCA HW_REGISTER_RW( 0x7e801140 ) + #define CAM1_CAMIDCA_MASK 0xffffffff + #define CAM1_CAMIDCA_WIDTH 32 + #define CAM1_CAMIDCA_RESET 0000000000 +#define CAM1_CAMIDCD HW_REGISTER_RW( 0x7e801144 ) + #define CAM1_CAMIDCD_MASK 0xffffffff + #define CAM1_CAMIDCD_WIDTH 32 + #define CAM1_CAMIDCD_RESET 0000000000 +#define CAM1_CAMIDS HW_REGISTER_RW( 0x7e801148 ) + #define CAM1_CAMIDS_MASK 0xffffffff + #define CAM1_CAMIDS_WIDTH 32 + #define CAM1_CAMIDS_RESET 0000000000 +#define CAM1_CAMDCS HW_REGISTER_RW( 0x7e801200 ) + #define CAM1_CAMDCS_MASK 0xffffffff + #define CAM1_CAMDCS_WIDTH 32 + #define CAM1_CAMDCS_RESET 0000000000 +#define CAM1_CAMDBSA0 HW_REGISTER_RW( 0x7e801204 ) + #define CAM1_CAMDBSA0_MASK 0xffffffff + #define CAM1_CAMDBSA0_WIDTH 32 + #define CAM1_CAMDBSA0_RESET 0000000000 +#define CAM1_CAMDBEA0 HW_REGISTER_RW( 0x7e801208 ) + #define CAM1_CAMDBEA0_MASK 0xffffffff + #define CAM1_CAMDBEA0_WIDTH 32 + #define CAM1_CAMDBEA0_RESET 0000000000 +#define CAM1_CAMDBWP HW_REGISTER_RW( 0x7e80120c ) + #define CAM1_CAMDBWP_MASK 0xffffffff + #define CAM1_CAMDBWP_WIDTH 32 + #define CAM1_CAMDBWP_RESET 0000000000 +#define CAM1_CAMDBCTL HW_REGISTER_RW( 0x7e801300 ) + #define CAM1_CAMDBCTL_MASK 0xffffffff + #define CAM1_CAMDBCTL_WIDTH 32 + #define CAM1_CAMDBCTL_RESET 0000000000 +#define CAM1_CAMIBSA1 HW_REGISTER_RW( 0x7e801304 ) + #define CAM1_CAMIBSA1_MASK 0xffffffff + #define CAM1_CAMIBSA1_WIDTH 32 + #define CAM1_CAMIBSA1_RESET 0000000000 +#define CAM1_CAMIBEA1 HW_REGISTER_RW( 0x7e801308 ) + #define CAM1_CAMIBEA1_MASK 0xffffffff + #define CAM1_CAMIBEA1_WIDTH 32 + #define CAM1_CAMIBEA1_RESET 0000000000 +#define CAM1_CAMIDI1 HW_REGISTER_RW( 0x7e80130c ) + #define CAM1_CAMIDI1_MASK 0xffffffff + #define CAM1_CAMIDI1_WIDTH 32 + #define CAM1_CAMIDI1_RESET 0000000000 +#define CAM1_CAMDBSA1 HW_REGISTER_RW( 0x7e801310 ) + #define CAM1_CAMDBSA1_MASK 0xffffffff + #define CAM1_CAMDBSA1_WIDTH 32 + #define CAM1_CAMDBSA1_RESET 0000000000 +#define CAM1_CAMDBEA1 HW_REGISTER_RW( 0x7e801314 ) + #define CAM1_CAMDBEA1_MASK 0xffffffff + #define CAM1_CAMDBEA1_WIDTH 32 + #define CAM1_CAMDBEA1_RESET 0000000000 +#define CAM1_CAMMISC HW_REGISTER_RW( 0x7e801400 ) + #define CAM1_CAMMISC_MASK 0xffffffff + #define CAM1_CAMMISC_WIDTH 32 + #define CAM1_CAMMISC_RESET 0000000000 diff --git a/bcm2708_chip/cam1_a0.h b/bcm2708_chip/cam1_a0.h new file mode 100755 index 0000000..e70460e --- /dev/null +++ b/bcm2708_chip/cam1_a0.h @@ -0,0 +1,131 @@ +// This file was generated by the create_regs script +#define CAM1_BASE 0x7e801000 +#define CAM1_APB_ID 0x7563616d +#define CAM1_CTL HW_REGISTER_RW( 0x7e801000 ) + #define CAM1_CTL_MASK 0xffffffff + #define CAM1_CTL_WIDTH 32 + #define CAM1_CTL_RESET 0000000000 +#define CAM1_STA HW_REGISTER_RW( 0x7e801004 ) + #define CAM1_STA_MASK 0xffffffff + #define CAM1_STA_WIDTH 32 + #define CAM1_STA_RESET 0000000000 +#define CAM1_ANA HW_REGISTER_RW( 0x7e801008 ) + #define CAM1_ANA_MASK 0xffffffff + #define CAM1_ANA_WIDTH 32 + #define CAM1_ANA_RESET 0000000000 +#define CAM1_PRI HW_REGISTER_RW( 0x7e80100c ) + #define CAM1_PRI_MASK 0xffffffff + #define CAM1_PRI_WIDTH 32 + #define CAM1_PRI_RESET 0000000000 +#define CAM1_CLK HW_REGISTER_RW( 0x7e801010 ) + #define CAM1_CLK_MASK 0xffffffff + #define CAM1_CLK_WIDTH 32 + #define CAM1_CLK_RESET 0000000000 +#define CAM1_DAT0 HW_REGISTER_RW( 0x7e801014 ) + #define CAM1_DAT0_MASK 0xffffffff + #define CAM1_DAT0_WIDTH 32 + #define CAM1_DAT0_RESET 0000000000 +#define CAM1_DAT1 HW_REGISTER_RW( 0x7e801018 ) + #define CAM1_DAT1_MASK 0xffffffff + #define CAM1_DAT1_WIDTH 32 + #define CAM1_DAT1_RESET 0000000000 +#define CAM1_DAT2 HW_REGISTER_RW( 0x7e80101c ) + #define CAM1_DAT2_MASK 0xffffffff + #define CAM1_DAT2_WIDTH 32 + #define CAM1_DAT2_RESET 0000000000 +#define CAM1_DAT3 HW_REGISTER_RW( 0x7e801020 ) + #define CAM1_DAT3_MASK 0xffffffff + #define CAM1_DAT3_WIDTH 32 + #define CAM1_DAT3_RESET 0000000000 +#define CAM1_CMP0 HW_REGISTER_RW( 0x7e801024 ) + #define CAM1_CMP0_MASK 0xffffffff + #define CAM1_CMP0_WIDTH 32 + #define CAM1_CMP0_RESET 0000000000 +#define CAM1_CMP1 HW_REGISTER_RW( 0x7e801028 ) + #define CAM1_CMP1_MASK 0xffffffff + #define CAM1_CMP1_WIDTH 32 + #define CAM1_CMP1_RESET 0000000000 +#define CAM1_CAP0 HW_REGISTER_RW( 0x7e80102c ) + #define CAM1_CAP0_MASK 0xffffffff + #define CAM1_CAP0_WIDTH 32 + #define CAM1_CAP0_RESET 0000000000 +#define CAM1_CAP1 HW_REGISTER_RW( 0x7e801030 ) + #define CAM1_CAP1_MASK 0xffffffff + #define CAM1_CAP1_WIDTH 32 + #define CAM1_CAP1_RESET 0000000000 +#define CAM1_DBG0 HW_REGISTER_RW( 0x7e8010f0 ) + #define CAM1_DBG0_MASK 0xffffffff + #define CAM1_DBG0_WIDTH 32 + #define CAM1_DBG0_RESET 0000000000 +#define CAM1_DBG1 HW_REGISTER_RW( 0x7e8010f4 ) + #define CAM1_DBG1_MASK 0xffffffff + #define CAM1_DBG1_WIDTH 32 + #define CAM1_DBG1_RESET 0000000000 +#define CAM1_DBG2 HW_REGISTER_RW( 0x7e8010f8 ) + #define CAM1_DBG2_MASK 0xffffffff + #define CAM1_DBG2_WIDTH 32 + #define CAM1_DBG2_RESET 0000000000 +#define CAM1_ICTL HW_REGISTER_RW( 0x7e801100 ) + #define CAM1_ICTL_MASK 0xffffffff + #define CAM1_ICTL_WIDTH 32 + #define CAM1_ICTL_RESET 0000000000 +#define CAM1_ISTA HW_REGISTER_RW( 0x7e801104 ) + #define CAM1_ISTA_MASK 0xffffffff + #define CAM1_ISTA_WIDTH 32 + #define CAM1_ISTA_RESET 0000000000 +#define CAM1_IDI HW_REGISTER_RW( 0x7e801108 ) + #define CAM1_IDI_MASK 0xffffffff + #define CAM1_IDI_WIDTH 32 + #define CAM1_IDI_RESET 0000000000 +#define CAM1_IPIPE HW_REGISTER_RW( 0x7e80110c ) + #define CAM1_IPIPE_MASK 0xffffffff + #define CAM1_IPIPE_WIDTH 32 + #define CAM1_IPIPE_RESET 0000000000 +#define CAM1_IBSA HW_REGISTER_RW( 0x7e801110 ) + #define CAM1_IBSA_MASK 0xffffffff + #define CAM1_IBSA_WIDTH 32 + #define CAM1_IBSA_RESET 0000000000 +#define CAM1_IBEA HW_REGISTER_RW( 0x7e801114 ) + #define CAM1_IBEA_MASK 0xffffffff + #define CAM1_IBEA_WIDTH 32 + #define CAM1_IBEA_RESET 0000000000 +#define CAM1_IBLS HW_REGISTER_RW( 0x7e801118 ) + #define CAM1_IBLS_MASK 0xffffffff + #define CAM1_IBLS_WIDTH 32 + #define CAM1_IBLS_RESET 0000000000 +#define CAM1_IBWP HW_REGISTER_RW( 0x7e80111c ) + #define CAM1_IBWP_MASK 0xffffffff + #define CAM1_IBWP_WIDTH 32 + #define CAM1_IBWP_RESET 0000000000 +#define CAM1_IHWIN HW_REGISTER_RW( 0x7e801120 ) + #define CAM1_IHWIN_MASK 0xffffffff + #define CAM1_IHWIN_WIDTH 32 + #define CAM1_IHWIN_RESET 0000000000 +#define CAM1_IHSTA HW_REGISTER_RW( 0x7e801124 ) + #define CAM1_IHSTA_MASK 0xffffffff + #define CAM1_IHSTA_WIDTH 32 + #define CAM1_IHSTA_RESET 0000000000 +#define CAM1_IVWIN HW_REGISTER_RW( 0x7e801128 ) + #define CAM1_IVWIN_MASK 0xffffffff + #define CAM1_IVWIN_WIDTH 32 + #define CAM1_IVWIN_RESET 0000000000 +#define CAM1_IVSTA HW_REGISTER_RW( 0x7e80112c ) + #define CAM1_IVSTA_MASK 0xffffffff + #define CAM1_IVSTA_WIDTH 32 + #define CAM1_IVSTA_RESET 0000000000 +#define CAM1_DCS HW_REGISTER_RW( 0x7e801200 ) + #define CAM1_DCS_MASK 0xffffffff + #define CAM1_DCS_WIDTH 32 + #define CAM1_DCS_RESET 0000000000 +#define CAM1_DBSA HW_REGISTER_RW( 0x7e801204 ) + #define CAM1_DBSA_MASK 0xffffffff + #define CAM1_DBSA_WIDTH 32 + #define CAM1_DBSA_RESET 0000000000 +#define CAM1_DBEA HW_REGISTER_RW( 0x7e801208 ) + #define CAM1_DBEA_MASK 0xffffffff + #define CAM1_DBEA_WIDTH 32 + #define CAM1_DBEA_RESET 0000000000 +#define CAM1_DBWP HW_REGISTER_RW( 0x7e801208 ) + #define CAM1_DBWP_MASK 0xffffffff + #define CAM1_DBWP_WIDTH 32 + #define CAM1_DBWP_RESET 0000000000 diff --git a/bcm2708_chip/camccp.h b/bcm2708_chip/camccp.h new file mode 100755 index 0000000..14cc35d --- /dev/null +++ b/bcm2708_chip/camccp.h @@ -0,0 +1,138 @@ +// This file was generated by the create_regs script +#define CCP_BASE 0x7e801000 +#define CCP_APB_ID 0x63637032 +#define CCP_RC HW_REGISTER_RW( 0x7e801000 ) + #define CCP_RC_MASK 0xffffffff + #define CCP_RC_WIDTH 32 + #define CCP_RC__MSB 31 + #define CCP_RC__LSB 0 +#define CCP_RS HW_REGISTER_RW( 0x7e801004 ) + #define CCP_RS_MASK 0xffffffff + #define CCP_RS_WIDTH 32 + #define CCP_RS__MSB 31 + #define CCP_RS__LSB 0 +#define CCP_RDR1 HW_REGISTER_RW( 0x7e801080 ) + #define CCP_RDR1_MASK 0xffffffff + #define CCP_RDR1_WIDTH 32 + #define CCP_RDR1__MSB 31 + #define CCP_RDR1__LSB 0 +#define CCP_RDR2 HW_REGISTER_RW( 0x7e801084 ) + #define CCP_RDR2_MASK 0xffffffff + #define CCP_RDR2_WIDTH 32 + #define CCP_RDR2__MSB 31 + #define CCP_RDR2__LSB 0 +#define CCP_RDR3 HW_REGISTER_RW( 0x7e801088 ) + #define CCP_RDR3_MASK 0xffffffff + #define CCP_RDR3_WIDTH 32 + #define CCP_RDR3__MSB 31 + #define CCP_RDR3__LSB 0 +#define CCP_RC0 HW_REGISTER_RW( 0x7e801100 ) + #define CCP_RC0_MASK 0xffffffff + #define CCP_RC0_WIDTH 32 + #define CCP_RC0__MSB 31 + #define CCP_RC0__LSB 0 +#define CCP_RPC0 HW_REGISTER_RW( 0x7e801104 ) + #define CCP_RPC0_MASK 0xffffffff + #define CCP_RPC0_WIDTH 32 + #define CCP_RPC0__MSB 31 + #define CCP_RPC0__LSB 0 +#define CCP_RS0 HW_REGISTER_RW( 0x7e801108 ) + #define CCP_RS0_MASK 0xffffffff + #define CCP_RS0_WIDTH 32 + #define CCP_RS0__MSB 31 + #define CCP_RS0__LSB 0 +#define CCP_RSA0 HW_REGISTER_RW( 0x7e80110c ) + #define CCP_RSA0_MASK 0xffffffff + #define CCP_RSA0_WIDTH 32 + #define CCP_RSA0__MSB 31 + #define CCP_RSA0__LSB 0 +#define CCP_REA0 HW_REGISTER_RW( 0x7e801110 ) + #define CCP_REA0_MASK 0xffffffff + #define CCP_REA0_WIDTH 32 + #define CCP_REA0__MSB 31 + #define CCP_REA0__LSB 0 +#define CCP_RWP0 HW_REGISTER_RW( 0x7e801114 ) + #define CCP_RWP0_MASK 0xffffffff + #define CCP_RWP0_WIDTH 32 + #define CCP_RWP0__MSB 31 + #define CCP_RWP0__LSB 0 +#define CCP_RBC0 HW_REGISTER_RW( 0x7e801118 ) + #define CCP_RBC0_MASK 0xffffffff + #define CCP_RBC0_WIDTH 32 + #define CCP_RBC0__MSB 31 + #define CCP_RBC0__LSB 0 +#define CCP_RLS0 HW_REGISTER_RW( 0x7e80111c ) + #define CCP_RLS0_MASK 0xffffffff + #define CCP_RLS0_WIDTH 32 + #define CCP_RLS0__MSB 31 + #define CCP_RLS0__LSB 0 +#define CCP_RDSA0 HW_REGISTER_RW( 0x7e801120 ) + #define CCP_RDSA0_MASK 0xffffffff + #define CCP_RDSA0_WIDTH 32 + #define CCP_RDSA0__MSB 31 + #define CCP_RDSA0__LSB 0 +#define CCP_RDEA0 HW_REGISTER_RW( 0x7e801124 ) + #define CCP_RDEA0_MASK 0xffffffff + #define CCP_RDEA0_WIDTH 32 + #define CCP_RDEA0__MSB 31 + #define CCP_RDEA0__LSB 0 +#define CCP_RDS0 HW_REGISTER_RW( 0x7e801128 ) + #define CCP_RDS0_MASK 0xffffffff + #define CCP_RDS0_WIDTH 32 + #define CCP_RDS0__MSB 31 + #define CCP_RDS0__LSB 0 +#define CCP_RC1 HW_REGISTER_RW( 0x7e801200 ) + #define CCP_RC1_MASK 0xffffffff + #define CCP_RC1_WIDTH 32 + #define CCP_RC1__MSB 31 + #define CCP_RC1__LSB 0 +#define CCP_RPC1 HW_REGISTER_RW( 0x7e801204 ) + #define CCP_RPC1_MASK 0xffffffff + #define CCP_RPC1_WIDTH 32 + #define CCP_RPC1__MSB 31 + #define CCP_RPC1__LSB 0 +#define CCP_RS1 HW_REGISTER_RW( 0x7e801208 ) + #define CCP_RS1_MASK 0xffffffff + #define CCP_RS1_WIDTH 32 + #define CCP_RS1__MSB 31 + #define CCP_RS1__LSB 0 +#define CCP_RSA1 HW_REGISTER_RW( 0x7e80120c ) + #define CCP_RSA1_MASK 0xffffffff + #define CCP_RSA1_WIDTH 32 + #define CCP_RSA1__MSB 31 + #define CCP_RSA1__LSB 0 +#define CCP_REA1 HW_REGISTER_RW( 0x7e801210 ) + #define CCP_REA1_MASK 0xffffffff + #define CCP_REA1_WIDTH 32 + #define CCP_REA1__MSB 31 + #define CCP_REA1__LSB 0 +#define CCP_RWP1 HW_REGISTER_RW( 0x7e801214 ) + #define CCP_RWP1_MASK 0xffffffff + #define CCP_RWP1_WIDTH 32 + #define CCP_RWP1__MSB 31 + #define CCP_RWP1__LSB 0 +#define CCP_RBC1 HW_REGISTER_RW( 0x7e801218 ) + #define CCP_RBC1_MASK 0xffffffff + #define CCP_RBC1_WIDTH 32 + #define CCP_RBC1__MSB 31 + #define CCP_RBC1__LSB 0 +#define CCP_RLS1 HW_REGISTER_RW( 0x7e80121c ) + #define CCP_RLS1_MASK 0xffffffff + #define CCP_RLS1_WIDTH 32 + #define CCP_RLS1__MSB 31 + #define CCP_RLS1__LSB 0 +#define CCP_RDSA1 HW_REGISTER_RW( 0x7e801220 ) + #define CCP_RDSA1_MASK 0xffffffff + #define CCP_RDSA1_WIDTH 32 + #define CCP_RDSA1__MSB 31 + #define CCP_RDSA1__LSB 0 +#define CCP_RDEA1 HW_REGISTER_RW( 0x7e801224 ) + #define CCP_RDEA1_MASK 0xffffffff + #define CCP_RDEA1_WIDTH 32 + #define CCP_RDEA1__MSB 31 + #define CCP_RDEA1__LSB 0 +#define CCP_RDS1 HW_REGISTER_RW( 0x7e801228 ) + #define CCP_RDS1_MASK 0xffffffff + #define CCP_RDS1_WIDTH 32 + #define CCP_RDS1__MSB 31 + #define CCP_RDS1__LSB 0 diff --git a/bcm2708_chip/ccp2tx.h b/bcm2708_chip/ccp2tx.h new file mode 100755 index 0000000..19b3f77 --- /dev/null +++ b/bcm2708_chip/ccp2tx.h @@ -0,0 +1,260 @@ +// This file was generated by the create_regs script +#define CCP2TX_BASE 0x7e001000 +#define CCP2TX_APB_ID 0x63637032 +#define CCP2TX_TC HW_REGISTER_RW( 0x7e001000 ) + #define CCP2TX_TC_MASK 0x8000ff07 + #define CCP2TX_TC_WIDTH 32 + #define CCP2TX_TC_RESET 0x0000ff00 + #define CCP2TX_TC_SWR_BITS 31:31 + #define CCP2TX_TC_SWR_SET 0x80000000 + #define CCP2TX_TC_SWR_CLR 0x7fffffff + #define CCP2TX_TC_SWR_MSB 31 + #define CCP2TX_TC_SWR_LSB 31 + #define CCP2TX_TC_TIP_BITS 15:8 + #define CCP2TX_TC_TIP_SET 0x0000ff00 + #define CCP2TX_TC_TIP_CLR 0xffff00ff + #define CCP2TX_TC_TIP_MSB 15 + #define CCP2TX_TC_TIP_LSB 8 + #define CCP2TX_TC_CLKM_BITS 2:2 + #define CCP2TX_TC_CLKM_SET 0x00000004 + #define CCP2TX_TC_CLKM_CLR 0xfffffffb + #define CCP2TX_TC_CLKM_MSB 2 + #define CCP2TX_TC_CLKM_LSB 2 + #define CCP2TX_TC_MEN_BITS 1:1 + #define CCP2TX_TC_MEN_SET 0x00000002 + #define CCP2TX_TC_MEN_CLR 0xfffffffd + #define CCP2TX_TC_MEN_MSB 1 + #define CCP2TX_TC_MEN_LSB 1 + #define CCP2TX_TC_TEN_BITS 0:0 + #define CCP2TX_TC_TEN_SET 0x00000001 + #define CCP2TX_TC_TEN_CLR 0xfffffffe + #define CCP2TX_TC_TEN_MSB 0 + #define CCP2TX_TC_TEN_LSB 0 +#define CCP2TX_TS HW_REGISTER_RW( 0x7e001004 ) + #define CCP2TX_TS_MASK 0x000f1f7f + #define CCP2TX_TS_WIDTH 20 + #define CCP2TX_TS_RESET 0000000000 + #define CCP2TX_TS_TQI_BITS 19:19 + #define CCP2TX_TS_TQI_SET 0x00080000 + #define CCP2TX_TS_TQI_CLR 0xfff7ffff + #define CCP2TX_TS_TQI_MSB 19 + #define CCP2TX_TS_TQI_LSB 19 + #define CCP2TX_TS_TEI_BITS 18:18 + #define CCP2TX_TS_TEI_SET 0x00040000 + #define CCP2TX_TS_TEI_CLR 0xfffbffff + #define CCP2TX_TS_TEI_MSB 18 + #define CCP2TX_TS_TEI_LSB 18 + #define CCP2TX_TS_TII_BITS 17:17 + #define CCP2TX_TS_TII_SET 0x00020000 + #define CCP2TX_TS_TII_CLR 0xfffdffff + #define CCP2TX_TS_TII_MSB 17 + #define CCP2TX_TS_TII_LSB 17 + #define CCP2TX_TS_IS_BITS 16:16 + #define CCP2TX_TS_IS_SET 0x00010000 + #define CCP2TX_TS_IS_CLR 0xfffeffff + #define CCP2TX_TS_IS_MSB 16 + #define CCP2TX_TS_IS_LSB 16 + #define CCP2TX_TS_TQL_BITS 12:8 + #define CCP2TX_TS_TQL_SET 0x00001f00 + #define CCP2TX_TS_TQL_CLR 0xffffe0ff + #define CCP2TX_TS_TQL_MSB 12 + #define CCP2TX_TS_TQL_LSB 8 + #define CCP2TX_TS_TFP_BITS 6:6 + #define CCP2TX_TS_TFP_SET 0x00000040 + #define CCP2TX_TS_TFP_CLR 0xffffffbf + #define CCP2TX_TS_TFP_MSB 6 + #define CCP2TX_TS_TFP_LSB 6 + #define CCP2TX_TS_TFF_BITS 5:5 + #define CCP2TX_TS_TFF_SET 0x00000020 + #define CCP2TX_TS_TFF_CLR 0xffffffdf + #define CCP2TX_TS_TFF_MSB 5 + #define CCP2TX_TS_TFF_LSB 5 + #define CCP2TX_TS_TFE_BITS 4:4 + #define CCP2TX_TS_TFE_SET 0x00000010 + #define CCP2TX_TS_TFE_CLR 0xffffffef + #define CCP2TX_TS_TFE_MSB 4 + #define CCP2TX_TS_TFE_LSB 4 + #define CCP2TX_TS_TUE_BITS 3:3 + #define CCP2TX_TS_TUE_SET 0x00000008 + #define CCP2TX_TS_TUE_CLR 0xfffffff7 + #define CCP2TX_TS_TUE_MSB 3 + #define CCP2TX_TS_TUE_LSB 3 + #define CCP2TX_TS_ARE_BITS 2:2 + #define CCP2TX_TS_ARE_SET 0x00000004 + #define CCP2TX_TS_ARE_CLR 0xfffffffb + #define CCP2TX_TS_ARE_MSB 2 + #define CCP2TX_TS_ARE_LSB 2 + #define CCP2TX_TS_IEB_BITS 1:1 + #define CCP2TX_TS_IEB_SET 0x00000002 + #define CCP2TX_TS_IEB_CLR 0xfffffffd + #define CCP2TX_TS_IEB_MSB 1 + #define CCP2TX_TS_IEB_LSB 1 + #define CCP2TX_TS_TXB_BITS 0:0 + #define CCP2TX_TS_TXB_SET 0x00000001 + #define CCP2TX_TS_TXB_CLR 0xfffffffe + #define CCP2TX_TS_TXB_MSB 0 + #define CCP2TX_TS_TXB_LSB 0 +#define CCP2TX_TAC HW_REGISTER_RW( 0x7e001008 ) + #define CCP2TX_TAC_MASK 0xffffff0f + #define CCP2TX_TAC_WIDTH 32 + #define CCP2TX_TAC_RESET 0x77434307 + #define CCP2TX_TAC_CTATADJ_BITS 31:28 + #define CCP2TX_TAC_CTATADJ_SET 0xf0000000 + #define CCP2TX_TAC_CTATADJ_CLR 0x0fffffff + #define CCP2TX_TAC_CTATADJ_MSB 31 + #define CCP2TX_TAC_CTATADJ_LSB 28 + #define CCP2TX_TAC_PTATADJ_BITS 27:24 + #define CCP2TX_TAC_PTATADJ_SET 0x0f000000 + #define CCP2TX_TAC_PTATADJ_CLR 0xf0ffffff + #define CCP2TX_TAC_PTATADJ_MSB 27 + #define CCP2TX_TAC_PTATADJ_LSB 24 + #define CCP2TX_TAC_CLAC_BITS 23:16 + #define CCP2TX_TAC_CLAC_SET 0x00ff0000 + #define CCP2TX_TAC_CLAC_CLR 0xff00ffff + #define CCP2TX_TAC_CLAC_MSB 23 + #define CCP2TX_TAC_CLAC_LSB 16 + #define CCP2TX_TAC_DLAC_BITS 15:8 + #define CCP2TX_TAC_DLAC_SET 0x0000ff00 + #define CCP2TX_TAC_DLAC_CLR 0xffff00ff + #define CCP2TX_TAC_DLAC_MSB 15 + #define CCP2TX_TAC_DLAC_LSB 8 + #define CCP2TX_TAC_TPC_BITS 3:3 + #define CCP2TX_TAC_TPC_SET 0x00000008 + #define CCP2TX_TAC_TPC_CLR 0xfffffff7 + #define CCP2TX_TAC_TPC_MSB 3 + #define CCP2TX_TAC_TPC_LSB 3 + #define CCP2TX_TAC_BPD_BITS 2:2 + #define CCP2TX_TAC_BPD_SET 0x00000004 + #define CCP2TX_TAC_BPD_CLR 0xfffffffb + #define CCP2TX_TAC_BPD_MSB 2 + #define CCP2TX_TAC_BPD_LSB 2 + #define CCP2TX_TAC_APD_BITS 1:1 + #define CCP2TX_TAC_APD_SET 0x00000002 + #define CCP2TX_TAC_APD_CLR 0xfffffffd + #define CCP2TX_TAC_APD_MSB 1 + #define CCP2TX_TAC_APD_LSB 1 + #define CCP2TX_TAC_ARST_BITS 0:0 + #define CCP2TX_TAC_ARST_SET 0x00000001 + #define CCP2TX_TAC_ARST_CLR 0xfffffffe + #define CCP2TX_TAC_ARST_MSB 0 + #define CCP2TX_TAC_ARST_LSB 0 +#define CCP2TX_TPC HW_REGISTER_RW( 0x7e00100c ) + #define CCP2TX_TPC_MASK 0x0000ffff + #define CCP2TX_TPC_WIDTH 16 + #define CCP2TX_TPC_RESET 0000000000 + #define CCP2TX_TPC_TPT_BITS 15:8 + #define CCP2TX_TPC_TPT_SET 0x0000ff00 + #define CCP2TX_TPC_TPT_CLR 0xffff00ff + #define CCP2TX_TPC_TPT_MSB 15 + #define CCP2TX_TPC_TPT_LSB 8 + #define CCP2TX_TPC_TPP_BITS 7:4 + #define CCP2TX_TPC_TPP_SET 0x000000f0 + #define CCP2TX_TPC_TPP_CLR 0xffffff0f + #define CCP2TX_TPC_TPP_MSB 7 + #define CCP2TX_TPC_TPP_LSB 4 + #define CCP2TX_TPC_TNP_BITS 3:0 + #define CCP2TX_TPC_TNP_SET 0x0000000f + #define CCP2TX_TPC_TNP_CLR 0xfffffff0 + #define CCP2TX_TPC_TNP_MSB 3 + #define CCP2TX_TPC_TNP_LSB 0 +#define CCP2TX_TSC HW_REGISTER_RW( 0x7e001010 ) + #define CCP2TX_TSC_MASK 0x0000000f + #define CCP2TX_TSC_WIDTH 4 + #define CCP2TX_TSC_RESET 0x00000002 + #define CCP2TX_TSC_TSM_BITS 3:0 + #define CCP2TX_TSC_TSM_SET 0x0000000f + #define CCP2TX_TSC_TSM_CLR 0xfffffff0 + #define CCP2TX_TSC_TSM_MSB 3 + #define CCP2TX_TSC_TSM_LSB 0 +#define CCP2TX_TIC HW_REGISTER_RW( 0x7e001014 ) + #define CCP2TX_TIC_MASK 0x000000f7 + #define CCP2TX_TIC_WIDTH 8 + #define CCP2TX_TIC_RESET 0000000000 + #define CCP2TX_TIC_TQIT_BITS 7:4 + #define CCP2TX_TIC_TQIT_SET 0x000000f0 + #define CCP2TX_TIC_TQIT_CLR 0xffffff0f + #define CCP2TX_TIC_TQIT_MSB 7 + #define CCP2TX_TIC_TQIT_LSB 4 + #define CCP2TX_TIC_TQIE_BITS 2:2 + #define CCP2TX_TIC_TQIE_SET 0x00000004 + #define CCP2TX_TIC_TQIE_CLR 0xfffffffb + #define CCP2TX_TIC_TQIE_MSB 2 + #define CCP2TX_TIC_TQIE_LSB 2 + #define CCP2TX_TIC_TEIE_BITS 1:1 + #define CCP2TX_TIC_TEIE_SET 0x00000002 + #define CCP2TX_TIC_TEIE_CLR 0xfffffffd + #define CCP2TX_TIC_TEIE_MSB 1 + #define CCP2TX_TIC_TEIE_LSB 1 + #define CCP2TX_TIC_TIIE_BITS 0:0 + #define CCP2TX_TIC_TIIE_SET 0x00000001 + #define CCP2TX_TIC_TIIE_CLR 0xfffffffe + #define CCP2TX_TIC_TIIE_MSB 0 + #define CCP2TX_TIC_TIIE_LSB 0 +#define CCP2TX_TTC HW_REGISTER_RW( 0x7e001018 ) + #define CCP2TX_TTC_MASK 0x80ff1fff + #define CCP2TX_TTC_WIDTH 32 + #define CCP2TX_TTC_RESET 0x00000100 + #define CCP2TX_TTC_ATX_BITS 31:31 + #define CCP2TX_TTC_ATX_SET 0x80000000 + #define CCP2TX_TTC_ATX_CLR 0x7fffffff + #define CCP2TX_TTC_ATX_MSB 31 + #define CCP2TX_TTC_ATX_LSB 31 + #define CCP2TX_TTC_BI_BITS 23:16 + #define CCP2TX_TTC_BI_SET 0x00ff0000 + #define CCP2TX_TTC_BI_CLR 0xff00ffff + #define CCP2TX_TTC_BI_MSB 23 + #define CCP2TX_TTC_BI_LSB 16 + #define CCP2TX_TTC_FSP_BITS 12:12 + #define CCP2TX_TTC_FSP_SET 0x00001000 + #define CCP2TX_TTC_FSP_CLR 0xffffefff + #define CCP2TX_TTC_FSP_MSB 12 + #define CCP2TX_TTC_FSP_LSB 12 + #define CCP2TX_TTC_LEC_BITS 11:8 + #define CCP2TX_TTC_LEC_SET 0x00000f00 + #define CCP2TX_TTC_LEC_CLR 0xfffff0ff + #define CCP2TX_TTC_LEC_MSB 11 + #define CCP2TX_TTC_LEC_LSB 8 + #define CCP2TX_TTC_LSC_BITS 7:4 + #define CCP2TX_TTC_LSC_SET 0x000000f0 + #define CCP2TX_TTC_LSC_CLR 0xffffff0f + #define CCP2TX_TTC_LSC_MSB 7 + #define CCP2TX_TTC_LSC_LSB 4 + #define CCP2TX_TTC_LCN_BITS 3:0 + #define CCP2TX_TTC_LCN_SET 0x0000000f + #define CCP2TX_TTC_LCN_CLR 0xfffffff0 + #define CCP2TX_TTC_LCN_MSB 3 + #define CCP2TX_TTC_LCN_LSB 0 +#define CCP2TX_TBA HW_REGISTER_RW( 0x7e00101c ) + #define CCP2TX_TBA_MASK 0x3fffffff + #define CCP2TX_TBA_WIDTH 30 + #define CCP2TX_TBA_RESET 0000000000 + #define CCP2TX_TBA_ADDR_BITS 29:0 + #define CCP2TX_TBA_ADDR_SET 0x3fffffff + #define CCP2TX_TBA_ADDR_CLR 0xc0000000 + #define CCP2TX_TBA_ADDR_MSB 29 + #define CCP2TX_TBA_ADDR_LSB 0 +#define CCP2TX_TDL HW_REGISTER_RW( 0x7e001020 ) + #define CCP2TX_TDL_MASK 0x3fffffff + #define CCP2TX_TDL_WIDTH 30 + #define CCP2TX_TDL_RESET 0000000000 + #define CCP2TX_TDL_LEN_BITS 29:0 + #define CCP2TX_TDL_LEN_SET 0x3fffffff + #define CCP2TX_TDL_LEN_CLR 0xc0000000 + #define CCP2TX_TDL_LEN_MSB 29 + #define CCP2TX_TDL_LEN_LSB 0 +#define CCP2TX_TD HW_REGISTER_RW( 0x7e001024 ) + #define CCP2TX_TD_MASK 0x000000ff + #define CCP2TX_TD_WIDTH 8 + #define CCP2TX_TD_IES_BITS 6:5 + #define CCP2TX_TD_IES_SET 0x00000060 + #define CCP2TX_TD_IES_CLR 0xffffff9f + #define CCP2TX_TD_IES_MSB 6 + #define CCP2TX_TD_IES_LSB 5 + #define CCP2TX_TD_TCS_BITS 4:0 + #define CCP2TX_TD_TCS_SET 0x0000001f + #define CCP2TX_TD_TCS_CLR 0xffffffe0 + #define CCP2TX_TD_TCS_MSB 4 + #define CCP2TX_TD_TCS_LSB 0 +#define CCP2TX_TSPARE HW_REGISTER_RW( 0x7e001028 ) + #define CCP2TX_TSPARE_MASK 0xffffffff + #define CCP2TX_TSPARE_WIDTH 32 diff --git a/bcm2708_chip/ccp2tx_a0.h b/bcm2708_chip/ccp2tx_a0.h new file mode 100755 index 0000000..3a9828a --- /dev/null +++ b/bcm2708_chip/ccp2tx_a0.h @@ -0,0 +1,30 @@ +// This file was generated by the create_regs script +#define CCP2TX_BASE 0x7e001000 +#define CCP2TX_APB_ID 0x63637032 +#define CCP2TX_TC HW_REGISTER_RW( 0x7e001000 ) + #define CCP2TX_TC_MASK 0xffffffff + #define CCP2TX_TC_WIDTH 32 +#define CCP2TX_TS HW_REGISTER_RW( 0x7e001004 ) + #define CCP2TX_TS_MASK 0xffffffff + #define CCP2TX_TS_WIDTH 32 +#define CCP2TX_TPC HW_REGISTER_RW( 0x7e001008 ) + #define CCP2TX_TPC_MASK 0xffffffff + #define CCP2TX_TPC_WIDTH 32 +#define CCP2TX_TSC HW_REGISTER_RW( 0x7e00100c ) + #define CCP2TX_TSC_MASK 0xffffffff + #define CCP2TX_TSC_WIDTH 32 +#define CCP2TX_TIC HW_REGISTER_RW( 0x7e001010 ) + #define CCP2TX_TIC_MASK 0xffffffff + #define CCP2TX_TIC_WIDTH 32 +#define CCP2TX_TTC HW_REGISTER_RW( 0x7e001014 ) + #define CCP2TX_TTC_MASK 0xffffffff + #define CCP2TX_TTC_WIDTH 32 +#define CCP2TX_TBA HW_REGISTER_RW( 0x7e001018 ) + #define CCP2TX_TBA_MASK 0xffffffff + #define CCP2TX_TBA_WIDTH 32 +#define CCP2TX_TDL HW_REGISTER_RW( 0x7e00101c ) + #define CCP2TX_TDL_MASK 0xffffffff + #define CCP2TX_TDL_WIDTH 32 +#define CCP2TX_TD HW_REGISTER_RW( 0x7e001020 ) + #define CCP2TX_TD_MASK 0xffffffff + #define CCP2TX_TD_WIDTH 32 diff --git a/bcm2708_chip/cdp.h b/bcm2708_chip/cdp.h new file mode 100755 index 0000000..967311e --- /dev/null +++ b/bcm2708_chip/cdp.h @@ -0,0 +1,19 @@ +// This file was generated by the create_regs script +#define CD_BASE 0x1820b000 +#define CD_APB_ID 0x43445000 +#define CD_CS HW_REGISTER_RW( 0x1820b000 ) + #define CD_CS__MASK 0xffffffff + #define CD_CS__WIDTH 32 + #define CD_CS__RESET 0000000000 + #define CD_CS__MSB 31 + #define CD_CS__LSB 0 +#define CD_PHYADJ HW_REGISTER_RW( 0x1820b004 ) + #define CD_PHYADJ__MASK 0x0000ffff + #define CD_PHYADJ__WIDTH 16 + #define CD_PHYADJ__MSB 15 + #define CD_PHYADJ__LSB 0 +#define CD_PHYDAT HW_REGISTER_RO( 0x1820b008 ) + #define CD_PHYDAT__MASK 0xffffffff + #define CD_PHYDAT__WIDTH 32 + #define CD_PHYDAT__MSB 31 + #define CD_PHYDAT__LSB 0 diff --git a/bcm2708_chip/clkman_image.h b/bcm2708_chip/clkman_image.h new file mode 100755 index 0000000..55c2824 --- /dev/null +++ b/bcm2708_chip/clkman_image.h @@ -0,0 +1,75 @@ +// This file was generated by the create_regs script +#define CMI_PASSWORD 0x5a000000 +#define CMI_BASE 0x7e802000 +#define CMI_APB_ID 0x00636d69 +#define CMI_CAM0 HW_REGISTER_RW( 0x7e802000 ) + #define CMI_CAM0_MASK 0x0000003f + #define CMI_CAM0_WIDTH 6 + #define CMI_CAM0_RESET 0000000000 + #define CMI_CAM0_RX1SRC_BITS 5:4 + #define CMI_CAM0_RX1SRC_SET 0x00000030 + #define CMI_CAM0_RX1SRC_CLR 0xffffffcf + #define CMI_CAM0_RX1SRC_MSB 5 + #define CMI_CAM0_RX1SRC_LSB 4 + #define CMI_CAM0_RX0SRC_BITS 3:2 + #define CMI_CAM0_RX0SRC_SET 0x0000000c + #define CMI_CAM0_RX0SRC_CLR 0xfffffff3 + #define CMI_CAM0_RX0SRC_MSB 3 + #define CMI_CAM0_RX0SRC_LSB 2 + #define CMI_CAM0_HSSRC_BITS 1:0 + #define CMI_CAM0_HSSRC_SET 0x00000003 + #define CMI_CAM0_HSSRC_CLR 0xfffffffc + #define CMI_CAM0_HSSRC_MSB 1 + #define CMI_CAM0_HSSRC_LSB 0 +#define CMI_CAM1 HW_REGISTER_RW( 0x7e802004 ) + #define CMI_CAM1_MASK 0x000003ff + #define CMI_CAM1_WIDTH 10 + #define CMI_CAM1_RESET 0000000000 + #define CMI_CAM1_RX3SRC_BITS 9:8 + #define CMI_CAM1_RX3SRC_SET 0x00000300 + #define CMI_CAM1_RX3SRC_CLR 0xfffffcff + #define CMI_CAM1_RX3SRC_MSB 9 + #define CMI_CAM1_RX3SRC_LSB 8 + #define CMI_CAM1_RX2SRC_BITS 7:6 + #define CMI_CAM1_RX2SRC_SET 0x000000c0 + #define CMI_CAM1_RX2SRC_CLR 0xffffff3f + #define CMI_CAM1_RX2SRC_MSB 7 + #define CMI_CAM1_RX2SRC_LSB 6 + #define CMI_CAM1_RX1SRC_BITS 5:4 + #define CMI_CAM1_RX1SRC_SET 0x00000030 + #define CMI_CAM1_RX1SRC_CLR 0xffffffcf + #define CMI_CAM1_RX1SRC_MSB 5 + #define CMI_CAM1_RX1SRC_LSB 4 + #define CMI_CAM1_RX0SRC_BITS 3:2 + #define CMI_CAM1_RX0SRC_SET 0x0000000c + #define CMI_CAM1_RX0SRC_CLR 0xfffffff3 + #define CMI_CAM1_RX0SRC_MSB 3 + #define CMI_CAM1_RX0SRC_LSB 2 + #define CMI_CAM1_HSSRC_BITS 1:0 + #define CMI_CAM1_HSSRC_SET 0x00000003 + #define CMI_CAM1_HSSRC_CLR 0xfffffffc + #define CMI_CAM1_HSSRC_MSB 1 + #define CMI_CAM1_HSSRC_LSB 0 +#define CMI_CAMTEST HW_REGISTER_RW( 0x7e802008 ) + #define CMI_CAMTEST_MASK 0x0000001f + #define CMI_CAMTEST_WIDTH 5 + #define CMI_CAMTEST_RESET 0000000000 + #define CMI_CAMTEST_ENAB_BITS 4:4 + #define CMI_CAMTEST_ENAB_SET 0x00000010 + #define CMI_CAMTEST_ENAB_CLR 0xffffffef + #define CMI_CAMTEST_ENAB_MSB 4 + #define CMI_CAMTEST_ENAB_LSB 4 + #define CMI_CAMTEST_SRC_BITS 3:0 + #define CMI_CAMTEST_SRC_SET 0x0000000f + #define CMI_CAMTEST_SRC_CLR 0xfffffff0 + #define CMI_CAMTEST_SRC_MSB 3 + #define CMI_CAMTEST_SRC_LSB 0 +#define CMI_USBCTL HW_REGISTER_RW( 0x7e802010 ) + #define CMI_USBCTL_MASK 0x00000040 + #define CMI_USBCTL_WIDTH 7 + #define CMI_USBCTL_RESET 0x00000040 + #define CMI_USBCTL_GATE_BITS 6:6 + #define CMI_USBCTL_GATE_SET 0x00000040 + #define CMI_USBCTL_GATE_CLR 0xffffffbf + #define CMI_USBCTL_GATE_MSB 6 + #define CMI_USBCTL_GATE_LSB 6 diff --git a/bcm2708_chip/cpg.h b/bcm2708_chip/cpg.h new file mode 100755 index 0000000..364bbf5 --- /dev/null +++ b/bcm2708_chip/cpg.h @@ -0,0 +1,36 @@ +// This file was generated by the create_regs script +#define CPG_BASE 0x7e211000 +#define CPG_APB_ID 0x67706320 +#define CPG_Config HW_REGISTER_RW( 0x7e211000 ) + #define CPG_Config_MASK 0xffffffff + #define CPG_Config_WIDTH 32 +#define CPG_IntStatus HW_REGISTER_RW( 0x7e211004 ) + #define CPG_IntStatus_MASK 0xffffffff + #define CPG_IntStatus_WIDTH 32 +#define CPG_Trigger HW_REGISTER_RW( 0x7e211008 ) + #define CPG_Trigger_MASK 0x00000003 + #define CPG_Trigger_WIDTH 2 +#define CPG_Param0 HW_REGISTER_RW( 0x7e211010 ) + #define CPG_Param0_MASK 0xffffffff + #define CPG_Param0_WIDTH 32 +#define CPG_Param1 HW_REGISTER_RW( 0x7e211014 ) + #define CPG_Param1_MASK 0xffffffff + #define CPG_Param1_WIDTH 32 +#define CPG_Param2 HW_REGISTER_RW( 0x7e211018 ) + #define CPG_Param2_MASK 0xffffffff + #define CPG_Param2_WIDTH 32 +#define CPG_Param3 HW_REGISTER_RW( 0x7e21101c ) + #define CPG_Param3_MASK 0xffffffff + #define CPG_Param3_WIDTH 32 +#define CPG_Debug0 HW_REGISTER_RW( 0x7e211040 ) + #define CPG_Debug0_MASK 0xffffffff + #define CPG_Debug0_WIDTH 32 +#define CPG_Debug1 HW_REGISTER_RW( 0x7e211044 ) + #define CPG_Debug1_MASK 0xffffffff + #define CPG_Debug1_WIDTH 32 +#define CPG_Debug2 HW_REGISTER_RW( 0x7e211048 ) + #define CPG_Debug2_MASK 0xffffffff + #define CPG_Debug2_WIDTH 32 +#define CPG_Debug3 HW_REGISTER_RW( 0x7e21104c ) + #define CPG_Debug3_MASK 0xffffffff + #define CPG_Debug3_WIDTH 32 diff --git a/bcm2708_chip/cpi.h b/bcm2708_chip/cpi.h new file mode 100755 index 0000000..643a59a --- /dev/null +++ b/bcm2708_chip/cpi.h @@ -0,0 +1,48 @@ +// This file was generated by the create_regs script +#define CPI_BASE 0x7e800000 +#define CPI_APB_ID 0x20637069 +#define CPI_CPIS HW_REGISTER_RW( 0x7e800000 ) + #define CPI_CPIS_MASK 0xc0000007 + #define CPI_CPIS_WIDTH 32 + #define CPI_CPIS__MSB 31 + #define CPI_CPIS__LSB 0 +#define CPI_CPIR HW_REGISTER_RW( 0x7e800004 ) + #define CPI_CPIR_MASK 0xffffffff + #define CPI_CPIR_WIDTH 32 + #define CPI_CPIR__MSB 31 + #define CPI_CPIR__LSB 0 +#define CPI_CPIF HW_REGISTER_RW( 0x7e800008 ) + #define CPI_CPIF_MASK 0xffffffff + #define CPI_CPIF_WIDTH 32 + #define CPI_CPIF__MSB 31 + #define CPI_CPIF__LSB 0 +#define CPI_CPIW HW_REGISTER_RW( 0x7e80000c ) + #define CPI_CPIW_MASK 0xffffffff + #define CPI_CPIW_WIDTH 32 + #define CPI_CPIW__MSB 31 + #define CPI_CPIW__LSB 0 +#define CPI_CPIWVC HW_REGISTER_RW( 0x7e800010 ) + #define CPI_CPIWVC_MASK 0xffffffff + #define CPI_CPIWVC_WIDTH 32 + #define CPI_CPIWVC__MSB 31 + #define CPI_CPIWVC__LSB 0 +#define CPI_CPIWVS HW_REGISTER_RW( 0x7e800014 ) + #define CPI_CPIWVS_MASK 0xffffffff + #define CPI_CPIWVS_WIDTH 32 + #define CPI_CPIWVS__MSB 31 + #define CPI_CPIWVS__LSB 0 +#define CPI_CPIWHC HW_REGISTER_RW( 0x7e800018 ) + #define CPI_CPIWHC_MASK 0xffffffff + #define CPI_CPIWHC_WIDTH 32 + #define CPI_CPIWHC__MSB 31 + #define CPI_CPIWHC__LSB 0 +#define CPI_CPIWHS HW_REGISTER_RW( 0x7e80001c ) + #define CPI_CPIWHS_MASK 0xffffffff + #define CPI_CPIWHS_WIDTH 32 + #define CPI_CPIWHS__MSB 31 + #define CPI_CPIWHS__LSB 0 +#define CPI_CPIB HW_REGISTER_RW( 0x7e800020 ) + #define CPI_CPIB_MASK 0xffffffff + #define CPI_CPIB_WIDTH 32 + #define CPI_CPIB__MSB 31 + #define CPI_CPIB__LSB 0 diff --git a/bcm2708_chip/cpr_apb2wtap.h b/bcm2708_chip/cpr_apb2wtap.h new file mode 100755 index 0000000..154bcf6 --- /dev/null +++ b/bcm2708_chip/cpr_apb2wtap.h @@ -0,0 +1,2037 @@ +// This file was generated by the create_regs script +#define A2W_PASSWORD 0x5a000000 +#define A2W_BASE 0x7e102000 +#define A2W_APB_ID 0x00613277 +#define A2W_PLLA_DIG0 HW_REGISTER_RW( 0x7e102000 ) + #define A2W_PLLA_DIG0_MASK 0x00ffffff + #define A2W_PLLA_DIG0_WIDTH 24 + #define A2W_PLLA_DIG0_RESET 0000000000 +#define A2W_PLLA_DIG1 HW_REGISTER_RW( 0x7e102004 ) + #define A2W_PLLA_DIG1_MASK 0x00ffffff + #define A2W_PLLA_DIG1_WIDTH 24 + #define A2W_PLLA_DIG1_RESET 0x00004000 +#define A2W_PLLA_DIG2 HW_REGISTER_RW( 0x7e102008 ) + #define A2W_PLLA_DIG2_MASK 0x00ffffff + #define A2W_PLLA_DIG2_WIDTH 24 + #define A2W_PLLA_DIG2_RESET 0x00100401 +#define A2W_PLLA_DIG3 HW_REGISTER_RW( 0x7e10200c ) + #define A2W_PLLA_DIG3_MASK 0x00ffffff + #define A2W_PLLA_DIG3_WIDTH 24 + #define A2W_PLLA_DIG3_RESET 0x00000004 +#define A2W_PLLA_ANA0 HW_REGISTER_RW( 0x7e102010 ) + #define A2W_PLLA_ANA0_MASK 0x00ffffff + #define A2W_PLLA_ANA0_WIDTH 24 + #define A2W_PLLA_ANA0_RESET 0000000000 +#define A2W_PLLA_ANA1 HW_REGISTER_RW( 0x7e102014 ) + #define A2W_PLLA_ANA1_MASK 0x00ffffff + #define A2W_PLLA_ANA1_WIDTH 24 + #define A2W_PLLA_ANA1_RESET 0x001d0000 +#define A2W_PLLA_ANA2 HW_REGISTER_RW( 0x7e102018 ) + #define A2W_PLLA_ANA2_MASK 0x00ffffff + #define A2W_PLLA_ANA2_WIDTH 24 + #define A2W_PLLA_ANA2_RESET 0000000000 +#define A2W_PLLA_ANA3 HW_REGISTER_RW( 0x7e10201c ) + #define A2W_PLLA_ANA3_MASK 0x00ffffff + #define A2W_PLLA_ANA3_WIDTH 24 + #define A2W_PLLA_ANA3_RESET 0x00000180 +#define A2W_PLLB_DIG0 HW_REGISTER_RW( 0x7e1020e0 ) + #define A2W_PLLB_DIG0_MASK 0x00ffffff + #define A2W_PLLB_DIG0_WIDTH 24 + #define A2W_PLLB_DIG0_RESET 0000000000 +#define A2W_PLLB_DIG1 HW_REGISTER_RW( 0x7e1020e4 ) + #define A2W_PLLB_DIG1_MASK 0x00ffffff + #define A2W_PLLB_DIG1_WIDTH 24 + #define A2W_PLLB_DIG1_RESET 0x00004000 +#define A2W_PLLB_DIG2 HW_REGISTER_RW( 0x7e1020e8 ) + #define A2W_PLLB_DIG2_MASK 0x00ffffff + #define A2W_PLLB_DIG2_WIDTH 24 + #define A2W_PLLB_DIG2_RESET 0x00100401 +#define A2W_PLLB_DIG3 HW_REGISTER_RW( 0x7e1020ec ) + #define A2W_PLLB_DIG3_MASK 0x00ffffff + #define A2W_PLLB_DIG3_WIDTH 24 + #define A2W_PLLB_DIG3_RESET 0x00000004 +#define A2W_PLLB_ANA0 HW_REGISTER_RW( 0x7e1020f0 ) + #define A2W_PLLB_ANA0_MASK 0x00ffffff + #define A2W_PLLB_ANA0_WIDTH 24 + #define A2W_PLLB_ANA0_RESET 0000000000 +#define A2W_PLLB_ANA1 HW_REGISTER_RW( 0x7e1020f4 ) + #define A2W_PLLB_ANA1_MASK 0x00ffffff + #define A2W_PLLB_ANA1_WIDTH 24 + #define A2W_PLLB_ANA1_RESET 0x001d0000 +#define A2W_PLLB_ANA2 HW_REGISTER_RW( 0x7e1020f8 ) + #define A2W_PLLB_ANA2_MASK 0x00ffffff + #define A2W_PLLB_ANA2_WIDTH 24 + #define A2W_PLLB_ANA2_RESET 0000000000 +#define A2W_PLLB_ANA3 HW_REGISTER_RW( 0x7e1020fc ) + #define A2W_PLLB_ANA3_MASK 0x00ffffff + #define A2W_PLLB_ANA3_WIDTH 24 + #define A2W_PLLB_ANA3_RESET 0x00000180 +#define A2W_PLLC_DIG0 HW_REGISTER_RW( 0x7e102020 ) + #define A2W_PLLC_DIG0_MASK 0x00ffffff + #define A2W_PLLC_DIG0_WIDTH 24 + #define A2W_PLLC_DIG0_RESET 0000000000 +#define A2W_PLLC_DIG1 HW_REGISTER_RW( 0x7e102024 ) + #define A2W_PLLC_DIG1_MASK 0x00ffffff + #define A2W_PLLC_DIG1_WIDTH 24 + #define A2W_PLLC_DIG1_RESET 0x00004000 +#define A2W_PLLC_DIG2 HW_REGISTER_RW( 0x7e102028 ) + #define A2W_PLLC_DIG2_MASK 0x00ffffff + #define A2W_PLLC_DIG2_WIDTH 24 + #define A2W_PLLC_DIG2_RESET 0x00100401 +#define A2W_PLLC_DIG3 HW_REGISTER_RW( 0x7e10202c ) + #define A2W_PLLC_DIG3_MASK 0x00ffffff + #define A2W_PLLC_DIG3_WIDTH 24 + #define A2W_PLLC_DIG3_RESET 0x00000004 +#define A2W_PLLC_ANA0 HW_REGISTER_RW( 0x7e102030 ) + #define A2W_PLLC_ANA0_MASK 0x00ffffff + #define A2W_PLLC_ANA0_WIDTH 24 + #define A2W_PLLC_ANA0_RESET 0000000000 +#define A2W_PLLC_ANA1 HW_REGISTER_RW( 0x7e102034 ) + #define A2W_PLLC_ANA1_MASK 0x00ffffff + #define A2W_PLLC_ANA1_WIDTH 24 + #define A2W_PLLC_ANA1_RESET 0x001d0000 +#define A2W_PLLC_ANA2 HW_REGISTER_RW( 0x7e102038 ) + #define A2W_PLLC_ANA2_MASK 0x00ffffff + #define A2W_PLLC_ANA2_WIDTH 24 + #define A2W_PLLC_ANA2_RESET 0000000000 +#define A2W_PLLC_ANA3 HW_REGISTER_RW( 0x7e10203c ) + #define A2W_PLLC_ANA3_MASK 0x00ffffff + #define A2W_PLLC_ANA3_WIDTH 24 + #define A2W_PLLC_ANA3_RESET 0x00000180 +#define A2W_PLLD_DIG0 HW_REGISTER_RW( 0x7e102040 ) + #define A2W_PLLD_DIG0_MASK 0x00ffffff + #define A2W_PLLD_DIG0_WIDTH 24 + #define A2W_PLLD_DIG0_RESET 0000000000 +#define A2W_PLLD_DIG1 HW_REGISTER_RW( 0x7e102044 ) + #define A2W_PLLD_DIG1_MASK 0x00ffffff + #define A2W_PLLD_DIG1_WIDTH 24 + #define A2W_PLLD_DIG1_RESET 0x00004000 +#define A2W_PLLD_DIG2 HW_REGISTER_RW( 0x7e102048 ) + #define A2W_PLLD_DIG2_MASK 0x00ffffff + #define A2W_PLLD_DIG2_WIDTH 24 + #define A2W_PLLD_DIG2_RESET 0x00100401 +#define A2W_PLLD_DIG3 HW_REGISTER_RW( 0x7e10204c ) + #define A2W_PLLD_DIG3_MASK 0x00ffffff + #define A2W_PLLD_DIG3_WIDTH 24 + #define A2W_PLLD_DIG3_RESET 0x00000004 +#define A2W_PLLD_ANA0 HW_REGISTER_RW( 0x7e102050 ) + #define A2W_PLLD_ANA0_MASK 0x00ffffff + #define A2W_PLLD_ANA0_WIDTH 24 + #define A2W_PLLD_ANA0_RESET 0000000000 +#define A2W_PLLD_ANA1 HW_REGISTER_RW( 0x7e102054 ) + #define A2W_PLLD_ANA1_MASK 0x00ffffff + #define A2W_PLLD_ANA1_WIDTH 24 + #define A2W_PLLD_ANA1_RESET 0x001d0000 +#define A2W_PLLD_ANA2 HW_REGISTER_RW( 0x7e102058 ) + #define A2W_PLLD_ANA2_MASK 0x00ffffff + #define A2W_PLLD_ANA2_WIDTH 24 + #define A2W_PLLD_ANA2_RESET 0000000000 +#define A2W_PLLD_ANA3 HW_REGISTER_RW( 0x7e10205c ) + #define A2W_PLLD_ANA3_MASK 0x00ffffff + #define A2W_PLLD_ANA3_WIDTH 24 + #define A2W_PLLD_ANA3_RESET 0x00000180 +#define A2W_PLLH_DIG0 HW_REGISTER_RW( 0x7e102060 ) + #define A2W_PLLH_DIG0_MASK 0x00ffffff + #define A2W_PLLH_DIG0_WIDTH 24 + #define A2W_PLLH_DIG0_RESET 0000000000 +#define A2W_PLLH_DIG1 HW_REGISTER_RW( 0x7e102064 ) + #define A2W_PLLH_DIG1_MASK 0x00ffffff + #define A2W_PLLH_DIG1_WIDTH 24 + #define A2W_PLLH_DIG1_RESET 0000000000 +#define A2W_PLLH_DIG2 HW_REGISTER_RW( 0x7e102068 ) + #define A2W_PLLH_DIG2_MASK 0x00ffffff + #define A2W_PLLH_DIG2_WIDTH 24 + #define A2W_PLLH_DIG2_RESET 0x000000aa +#define A2W_PLLH_DIG3 HW_REGISTER_RW( 0x7e10206c ) + #define A2W_PLLH_DIG3_MASK 0x00ffffff + #define A2W_PLLH_DIG3_WIDTH 24 + #define A2W_PLLH_DIG3_RESET 0000000000 +#define A2W_PLLH_ANA0 HW_REGISTER_RW( 0x7e102070 ) + #define A2W_PLLH_ANA0_MASK 0x00ffffff + #define A2W_PLLH_ANA0_WIDTH 24 + #define A2W_PLLH_ANA0_RESET 0x00d80000 +#define A2W_PLLH_ANA1 HW_REGISTER_RW( 0x7e102074 ) + #define A2W_PLLH_ANA1_MASK 0x00ffffff + #define A2W_PLLH_ANA1_WIDTH 24 + #define A2W_PLLH_ANA1_RESET 0x00000014 +#define A2W_PLLH_ANA2 HW_REGISTER_RW( 0x7e102078 ) + #define A2W_PLLH_ANA2_MASK 0x00ffffff + #define A2W_PLLH_ANA2_WIDTH 24 + #define A2W_PLLH_ANA2_RESET 0000000000 +#define A2W_PLLH_ANA3 HW_REGISTER_RW( 0x7e10207c ) + #define A2W_PLLH_ANA3_MASK 0x00ffffff + #define A2W_PLLH_ANA3_WIDTH 24 + #define A2W_PLLH_ANA3_RESET 0000000000 +#define A2W_HDMI_CTL0 HW_REGISTER_RW( 0x7e102080 ) + #define A2W_HDMI_CTL0_MASK 0x00ffffff + #define A2W_HDMI_CTL0_WIDTH 24 + #define A2W_HDMI_CTL0_RESET 0x00470238 +#define A2W_HDMI_CTL1 HW_REGISTER_RW( 0x7e102084 ) + #define A2W_HDMI_CTL1_MASK 0x00ffffff + #define A2W_HDMI_CTL1_WIDTH 24 + #define A2W_HDMI_CTL1_RESET 0x00011c00 +#define A2W_HDMI_CTL2 HW_REGISTER_RW( 0x7e102088 ) + #define A2W_HDMI_CTL2_MASK 0x00ffffff + #define A2W_HDMI_CTL2_WIDTH 24 + #define A2W_HDMI_CTL2_RESET 0x0018048e +#define A2W_HDMI_CTL3 HW_REGISTER_RW( 0x7e10208c ) + #define A2W_HDMI_CTL3_MASK 0x00ffffff + #define A2W_HDMI_CTL3_WIDTH 24 + #define A2W_HDMI_CTL3_RESET 0x00000040 +#define A2W_XOSC0 HW_REGISTER_RW( 0x7e102090 ) + #define A2W_XOSC0_MASK 0x00ffffff + #define A2W_XOSC0_WIDTH 24 + #define A2W_XOSC0_RESET 0x00820080 +#define A2W_XOSC1 HW_REGISTER_RW( 0x7e102094 ) + #define A2W_XOSC1_MASK 0x00ffffff + #define A2W_XOSC1_WIDTH 24 + #define A2W_XOSC1_RESET 0x00000006 +#define A2W_SMPS_CTLA0 HW_REGISTER_RW( 0x7e1020a0 ) + #define A2W_SMPS_CTLA0_MASK 0x00ffffff + #define A2W_SMPS_CTLA0_WIDTH 24 + #define A2W_SMPS_CTLA0_RESET 0000000000 +#define A2W_SMPS_CTLA1 HW_REGISTER_RW( 0x7e1020a4 ) + #define A2W_SMPS_CTLA1_MASK 0x00ffffff + #define A2W_SMPS_CTLA1_WIDTH 24 + #define A2W_SMPS_CTLA1_RESET 0000000000 +#define A2W_SMPS_CTLA2 HW_REGISTER_RW( 0x7e1020a8 ) + #define A2W_SMPS_CTLA2_MASK 0x00ffffff + #define A2W_SMPS_CTLA2_WIDTH 24 + #define A2W_SMPS_CTLA2_RESET 0000000000 +#define A2W_SMPS_CTLB0 HW_REGISTER_RW( 0x7e1020b0 ) + #define A2W_SMPS_CTLB0_MASK 0x00ffffff + #define A2W_SMPS_CTLB0_WIDTH 24 + #define A2W_SMPS_CTLB0_RESET 0000000000 +#define A2W_SMPS_CTLB1 HW_REGISTER_RW( 0x7e1020b4 ) + #define A2W_SMPS_CTLB1_MASK 0x00ffffff + #define A2W_SMPS_CTLB1_WIDTH 24 + #define A2W_SMPS_CTLB1_RESET 0000000000 +#define A2W_SMPS_CTLB2 HW_REGISTER_RW( 0x7e1020b8 ) + #define A2W_SMPS_CTLB2_MASK 0x00ffffff + #define A2W_SMPS_CTLB2_WIDTH 24 + #define A2W_SMPS_CTLB2_RESET 0000000000 +#define A2W_SMPS_CTLC0 HW_REGISTER_RW( 0x7e1020c0 ) + #define A2W_SMPS_CTLC0_MASK 0x00ffffff + #define A2W_SMPS_CTLC0_WIDTH 24 + #define A2W_SMPS_CTLC0_RESET 0000000000 +#define A2W_SMPS_CTLC1 HW_REGISTER_RW( 0x7e1020c4 ) + #define A2W_SMPS_CTLC1_MASK 0x00ffffff + #define A2W_SMPS_CTLC1_WIDTH 24 + #define A2W_SMPS_CTLC1_RESET 0000000000 +#define A2W_SMPS_CTLC2 HW_REGISTER_RW( 0x7e1020c8 ) + #define A2W_SMPS_CTLC2_MASK 0x00ffffff + #define A2W_SMPS_CTLC2_WIDTH 24 + #define A2W_SMPS_CTLC2_RESET 0000000000 +#define A2W_SMPS_CTLC3 HW_REGISTER_RW( 0x7e1020cc ) + #define A2W_SMPS_CTLC3_MASK 0x00ffffff + #define A2W_SMPS_CTLC3_WIDTH 24 + #define A2W_SMPS_CTLC3_RESET 0000000000 +#define A2W_SMPS_LDO0 HW_REGISTER_RW( 0x7e1020d0 ) + #define A2W_SMPS_LDO0_MASK 0x00ffffff + #define A2W_SMPS_LDO0_WIDTH 24 + #define A2W_SMPS_LDO0_RESET 0000000000 +#define A2W_SMPS_LDO1 HW_REGISTER_RW( 0x7e1020d4 ) + #define A2W_SMPS_LDO1_MASK 0x00ffffff + #define A2W_SMPS_LDO1_WIDTH 24 + #define A2W_SMPS_LDO1_RESET 0000000000 +#define A2W_PLLA_CTRL HW_REGISTER_RW( 0x7e102100 ) + #define A2W_PLLA_CTRL_MASK 0x000373ff + #define A2W_PLLA_CTRL_WIDTH 18 + #define A2W_PLLA_CTRL_RESET 0x00010000 + #define A2W_PLLA_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLA_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLA_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLA_CTRL_PRSTN_MSB 17 + #define A2W_PLLA_CTRL_PRSTN_LSB 17 + #define A2W_PLLA_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLA_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLA_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLA_CTRL_PWRDN_MSB 16 + #define A2W_PLLA_CTRL_PWRDN_LSB 16 + #define A2W_PLLA_CTRL_PDIV_BITS 14:12 + #define A2W_PLLA_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLA_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLA_CTRL_PDIV_MSB 14 + #define A2W_PLLA_CTRL_PDIV_LSB 12 + #define A2W_PLLA_CTRL_NDIV_BITS 9:0 + #define A2W_PLLA_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLA_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLA_CTRL_NDIV_MSB 9 + #define A2W_PLLA_CTRL_NDIV_LSB 0 +#define A2W_PLLA_FRAC HW_REGISTER_RW( 0x7e102200 ) + #define A2W_PLLA_FRAC_MASK 0x000fffff + #define A2W_PLLA_FRAC_WIDTH 20 + #define A2W_PLLA_FRAC_RESET 0000000000 + #define A2W_PLLA_FRAC_FRAC_BITS 19:0 + #define A2W_PLLA_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLA_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLA_FRAC_FRAC_MSB 19 + #define A2W_PLLA_FRAC_FRAC_LSB 0 +#define A2W_PLLA_DSI0 HW_REGISTER_RW( 0x7e102300 ) + #define A2W_PLLA_DSI0_MASK 0x000003ff + #define A2W_PLLA_DSI0_WIDTH 10 + #define A2W_PLLA_DSI0_RESET 0x00000100 + #define A2W_PLLA_DSI0_BYPEN_BITS 9:9 + #define A2W_PLLA_DSI0_BYPEN_SET 0x00000200 + #define A2W_PLLA_DSI0_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_DSI0_BYPEN_MSB 9 + #define A2W_PLLA_DSI0_BYPEN_LSB 9 + #define A2W_PLLA_DSI0_CHENB_BITS 8:8 + #define A2W_PLLA_DSI0_CHENB_SET 0x00000100 + #define A2W_PLLA_DSI0_CHENB_CLR 0xfffffeff + #define A2W_PLLA_DSI0_CHENB_MSB 8 + #define A2W_PLLA_DSI0_CHENB_LSB 8 + #define A2W_PLLA_DSI0_DIV_BITS 7:0 + #define A2W_PLLA_DSI0_DIV_SET 0x000000ff + #define A2W_PLLA_DSI0_DIV_CLR 0xffffff00 + #define A2W_PLLA_DSI0_DIV_MSB 7 + #define A2W_PLLA_DSI0_DIV_LSB 0 +#define A2W_PLLA_CORE HW_REGISTER_RW( 0x7e102400 ) + #define A2W_PLLA_CORE_MASK 0x000003ff + #define A2W_PLLA_CORE_WIDTH 10 + #define A2W_PLLA_CORE_RESET 0x00000100 + #define A2W_PLLA_CORE_BYPEN_BITS 9:9 + #define A2W_PLLA_CORE_BYPEN_SET 0x00000200 + #define A2W_PLLA_CORE_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_CORE_BYPEN_MSB 9 + #define A2W_PLLA_CORE_BYPEN_LSB 9 + #define A2W_PLLA_CORE_CHENB_BITS 8:8 + #define A2W_PLLA_CORE_CHENB_SET 0x00000100 + #define A2W_PLLA_CORE_CHENB_CLR 0xfffffeff + #define A2W_PLLA_CORE_CHENB_MSB 8 + #define A2W_PLLA_CORE_CHENB_LSB 8 + #define A2W_PLLA_CORE_DIV_BITS 7:0 + #define A2W_PLLA_CORE_DIV_SET 0x000000ff + #define A2W_PLLA_CORE_DIV_CLR 0xffffff00 + #define A2W_PLLA_CORE_DIV_MSB 7 + #define A2W_PLLA_CORE_DIV_LSB 0 +#define A2W_PLLA_PER HW_REGISTER_RW( 0x7e102500 ) + #define A2W_PLLA_PER_MASK 0x000003ff + #define A2W_PLLA_PER_WIDTH 10 + #define A2W_PLLA_PER_RESET 0x00000100 + #define A2W_PLLA_PER_BYPEN_BITS 9:9 + #define A2W_PLLA_PER_BYPEN_SET 0x00000200 + #define A2W_PLLA_PER_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_PER_BYPEN_MSB 9 + #define A2W_PLLA_PER_BYPEN_LSB 9 + #define A2W_PLLA_PER_CHENB_BITS 8:8 + #define A2W_PLLA_PER_CHENB_SET 0x00000100 + #define A2W_PLLA_PER_CHENB_CLR 0xfffffeff + #define A2W_PLLA_PER_CHENB_MSB 8 + #define A2W_PLLA_PER_CHENB_LSB 8 + #define A2W_PLLA_PER_DIV_BITS 7:0 + #define A2W_PLLA_PER_DIV_SET 0x000000ff + #define A2W_PLLA_PER_DIV_CLR 0xffffff00 + #define A2W_PLLA_PER_DIV_MSB 7 + #define A2W_PLLA_PER_DIV_LSB 0 +#define A2W_PLLA_CCP2 HW_REGISTER_RW( 0x7e102600 ) + #define A2W_PLLA_CCP2_MASK 0x000003ff + #define A2W_PLLA_CCP2_WIDTH 10 + #define A2W_PLLA_CCP2_RESET 0x00000100 + #define A2W_PLLA_CCP2_BYPEN_BITS 9:9 + #define A2W_PLLA_CCP2_BYPEN_SET 0x00000200 + #define A2W_PLLA_CCP2_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_CCP2_BYPEN_MSB 9 + #define A2W_PLLA_CCP2_BYPEN_LSB 9 + #define A2W_PLLA_CCP2_CHENB_BITS 8:8 + #define A2W_PLLA_CCP2_CHENB_SET 0x00000100 + #define A2W_PLLA_CCP2_CHENB_CLR 0xfffffeff + #define A2W_PLLA_CCP2_CHENB_MSB 8 + #define A2W_PLLA_CCP2_CHENB_LSB 8 + #define A2W_PLLA_CCP2_DIV_BITS 7:0 + #define A2W_PLLA_CCP2_DIV_SET 0x000000ff + #define A2W_PLLA_CCP2_DIV_CLR 0xffffff00 + #define A2W_PLLA_CCP2_DIV_MSB 7 + #define A2W_PLLA_CCP2_DIV_LSB 0 +#define A2W_PLLB_CTRL HW_REGISTER_RW( 0x7e1021e0 ) + #define A2W_PLLB_CTRL_MASK 0x000373ff + #define A2W_PLLB_CTRL_WIDTH 18 + #define A2W_PLLB_CTRL_RESET 0x00010000 + #define A2W_PLLB_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLB_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLB_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLB_CTRL_PRSTN_MSB 17 + #define A2W_PLLB_CTRL_PRSTN_LSB 17 + #define A2W_PLLB_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLB_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLB_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLB_CTRL_PWRDN_MSB 16 + #define A2W_PLLB_CTRL_PWRDN_LSB 16 + #define A2W_PLLB_CTRL_PDIV_BITS 14:12 + #define A2W_PLLB_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLB_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLB_CTRL_PDIV_MSB 14 + #define A2W_PLLB_CTRL_PDIV_LSB 12 + #define A2W_PLLB_CTRL_NDIV_BITS 9:0 + #define A2W_PLLB_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLB_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLB_CTRL_NDIV_MSB 9 + #define A2W_PLLB_CTRL_NDIV_LSB 0 +#define A2W_PLLB_FRAC HW_REGISTER_RW( 0x7e1022e0 ) + #define A2W_PLLB_FRAC_MASK 0x000fffff + #define A2W_PLLB_FRAC_WIDTH 20 + #define A2W_PLLB_FRAC_RESET 0000000000 + #define A2W_PLLB_FRAC_FRAC_BITS 19:0 + #define A2W_PLLB_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLB_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLB_FRAC_FRAC_MSB 19 + #define A2W_PLLB_FRAC_FRAC_LSB 0 +#define A2W_PLLB_ARM HW_REGISTER_RW( 0x7e1023e0 ) + #define A2W_PLLB_ARM_MASK 0x000003ff + #define A2W_PLLB_ARM_WIDTH 10 + #define A2W_PLLB_ARM_RESET 0x00000100 + #define A2W_PLLB_ARM_BYPEN_BITS 9:9 + #define A2W_PLLB_ARM_BYPEN_SET 0x00000200 + #define A2W_PLLB_ARM_BYPEN_CLR 0xfffffdff + #define A2W_PLLB_ARM_BYPEN_MSB 9 + #define A2W_PLLB_ARM_BYPEN_LSB 9 + #define A2W_PLLB_ARM_CHENB_BITS 8:8 + #define A2W_PLLB_ARM_CHENB_SET 0x00000100 + #define A2W_PLLB_ARM_CHENB_CLR 0xfffffeff + #define A2W_PLLB_ARM_CHENB_MSB 8 + #define A2W_PLLB_ARM_CHENB_LSB 8 + #define A2W_PLLB_ARM_DIV_BITS 7:0 + #define A2W_PLLB_ARM_DIV_SET 0x000000ff + #define A2W_PLLB_ARM_DIV_CLR 0xffffff00 + #define A2W_PLLB_ARM_DIV_MSB 7 + #define A2W_PLLB_ARM_DIV_LSB 0 +#define A2W_PLLB_SP0 HW_REGISTER_RW( 0x7e1024e0 ) + #define A2W_PLLB_SP0_MASK 0x000003ff + #define A2W_PLLB_SP0_WIDTH 10 + #define A2W_PLLB_SP0_RESET 0x00000100 + #define A2W_PLLB_SP0_BYPEN_BITS 9:9 + #define A2W_PLLB_SP0_BYPEN_SET 0x00000200 + #define A2W_PLLB_SP0_BYPEN_CLR 0xfffffdff + #define A2W_PLLB_SP0_BYPEN_MSB 9 + #define A2W_PLLB_SP0_BYPEN_LSB 9 + #define A2W_PLLB_SP0_CHENB_BITS 8:8 + #define A2W_PLLB_SP0_CHENB_SET 0x00000100 + #define A2W_PLLB_SP0_CHENB_CLR 0xfffffeff + #define A2W_PLLB_SP0_CHENB_MSB 8 + #define A2W_PLLB_SP0_CHENB_LSB 8 + #define A2W_PLLB_SP0_DIV_BITS 7:0 + #define A2W_PLLB_SP0_DIV_SET 0x000000ff + #define A2W_PLLB_SP0_DIV_CLR 0xffffff00 + #define A2W_PLLB_SP0_DIV_MSB 7 + #define A2W_PLLB_SP0_DIV_LSB 0 +#define A2W_PLLB_SP1 HW_REGISTER_RW( 0x7e1025e0 ) + #define A2W_PLLB_SP1_MASK 0x000003ff + #define A2W_PLLB_SP1_WIDTH 10 + #define A2W_PLLB_SP1_RESET 0x00000100 + #define A2W_PLLB_SP1_BYPEN_BITS 9:9 + #define A2W_PLLB_SP1_BYPEN_SET 0x00000200 + #define A2W_PLLB_SP1_BYPEN_CLR 0xfffffdff + #define A2W_PLLB_SP1_BYPEN_MSB 9 + #define A2W_PLLB_SP1_BYPEN_LSB 9 + #define A2W_PLLB_SP1_CHENB_BITS 8:8 + #define A2W_PLLB_SP1_CHENB_SET 0x00000100 + #define A2W_PLLB_SP1_CHENB_CLR 0xfffffeff + #define A2W_PLLB_SP1_CHENB_MSB 8 + #define A2W_PLLB_SP1_CHENB_LSB 8 + #define A2W_PLLB_SP1_DIV_BITS 7:0 + #define A2W_PLLB_SP1_DIV_SET 0x000000ff + #define A2W_PLLB_SP1_DIV_CLR 0xffffff00 + #define A2W_PLLB_SP1_DIV_MSB 7 + #define A2W_PLLB_SP1_DIV_LSB 0 +#define A2W_PLLB_SP2 HW_REGISTER_RW( 0x7e1026e0 ) + #define A2W_PLLB_SP2_MASK 0x000003ff + #define A2W_PLLB_SP2_WIDTH 10 + #define A2W_PLLB_SP2_RESET 0x00000100 + #define A2W_PLLB_SP2_BYPEN_BITS 9:9 + #define A2W_PLLB_SP2_BYPEN_SET 0x00000200 + #define A2W_PLLB_SP2_BYPEN_CLR 0xfffffdff + #define A2W_PLLB_SP2_BYPEN_MSB 9 + #define A2W_PLLB_SP2_BYPEN_LSB 9 + #define A2W_PLLB_SP2_CHENB_BITS 8:8 + #define A2W_PLLB_SP2_CHENB_SET 0x00000100 + #define A2W_PLLB_SP2_CHENB_CLR 0xfffffeff + #define A2W_PLLB_SP2_CHENB_MSB 8 + #define A2W_PLLB_SP2_CHENB_LSB 8 + #define A2W_PLLB_SP2_DIV_BITS 7:0 + #define A2W_PLLB_SP2_DIV_SET 0x000000ff + #define A2W_PLLB_SP2_DIV_CLR 0xffffff00 + #define A2W_PLLB_SP2_DIV_MSB 7 + #define A2W_PLLB_SP2_DIV_LSB 0 +#define A2W_PLLC_CTRL HW_REGISTER_RW( 0x7e102120 ) + #define A2W_PLLC_CTRL_MASK 0x000373ff + #define A2W_PLLC_CTRL_WIDTH 18 + #define A2W_PLLC_CTRL_RESET 0x00010000 + #define A2W_PLLC_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLC_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLC_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLC_CTRL_PRSTN_MSB 17 + #define A2W_PLLC_CTRL_PRSTN_LSB 17 + #define A2W_PLLC_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLC_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLC_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLC_CTRL_PWRDN_MSB 16 + #define A2W_PLLC_CTRL_PWRDN_LSB 16 + #define A2W_PLLC_CTRL_PDIV_BITS 14:12 + #define A2W_PLLC_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLC_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLC_CTRL_PDIV_MSB 14 + #define A2W_PLLC_CTRL_PDIV_LSB 12 + #define A2W_PLLC_CTRL_NDIV_BITS 9:0 + #define A2W_PLLC_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLC_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLC_CTRL_NDIV_MSB 9 + #define A2W_PLLC_CTRL_NDIV_LSB 0 +#define A2W_PLLC_FRAC HW_REGISTER_RW( 0x7e102220 ) + #define A2W_PLLC_FRAC_MASK 0x000fffff + #define A2W_PLLC_FRAC_WIDTH 20 + #define A2W_PLLC_FRAC_RESET 0000000000 + #define A2W_PLLC_FRAC_FRAC_BITS 19:0 + #define A2W_PLLC_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLC_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLC_FRAC_FRAC_MSB 19 + #define A2W_PLLC_FRAC_FRAC_LSB 0 +#define A2W_PLLC_CORE2 HW_REGISTER_RW( 0x7e102320 ) + #define A2W_PLLC_CORE2_MASK 0x000003ff + #define A2W_PLLC_CORE2_WIDTH 10 + #define A2W_PLLC_CORE2_RESET 0x00000100 + #define A2W_PLLC_CORE2_BYPEN_BITS 9:9 + #define A2W_PLLC_CORE2_BYPEN_SET 0x00000200 + #define A2W_PLLC_CORE2_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_CORE2_BYPEN_MSB 9 + #define A2W_PLLC_CORE2_BYPEN_LSB 9 + #define A2W_PLLC_CORE2_CHENB_BITS 8:8 + #define A2W_PLLC_CORE2_CHENB_SET 0x00000100 + #define A2W_PLLC_CORE2_CHENB_CLR 0xfffffeff + #define A2W_PLLC_CORE2_CHENB_MSB 8 + #define A2W_PLLC_CORE2_CHENB_LSB 8 + #define A2W_PLLC_CORE2_DIV_BITS 7:0 + #define A2W_PLLC_CORE2_DIV_SET 0x000000ff + #define A2W_PLLC_CORE2_DIV_CLR 0xffffff00 + #define A2W_PLLC_CORE2_DIV_MSB 7 + #define A2W_PLLC_CORE2_DIV_LSB 0 +#define A2W_PLLC_CORE1 HW_REGISTER_RW( 0x7e102420 ) + #define A2W_PLLC_CORE1_MASK 0x000003ff + #define A2W_PLLC_CORE1_WIDTH 10 + #define A2W_PLLC_CORE1_RESET 0x00000100 + #define A2W_PLLC_CORE1_BYPEN_BITS 9:9 + #define A2W_PLLC_CORE1_BYPEN_SET 0x00000200 + #define A2W_PLLC_CORE1_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_CORE1_BYPEN_MSB 9 + #define A2W_PLLC_CORE1_BYPEN_LSB 9 + #define A2W_PLLC_CORE1_CHENB_BITS 8:8 + #define A2W_PLLC_CORE1_CHENB_SET 0x00000100 + #define A2W_PLLC_CORE1_CHENB_CLR 0xfffffeff + #define A2W_PLLC_CORE1_CHENB_MSB 8 + #define A2W_PLLC_CORE1_CHENB_LSB 8 + #define A2W_PLLC_CORE1_DIV_BITS 7:0 + #define A2W_PLLC_CORE1_DIV_SET 0x000000ff + #define A2W_PLLC_CORE1_DIV_CLR 0xffffff00 + #define A2W_PLLC_CORE1_DIV_MSB 7 + #define A2W_PLLC_CORE1_DIV_LSB 0 +#define A2W_PLLC_PER HW_REGISTER_RW( 0x7e102520 ) + #define A2W_PLLC_PER_MASK 0x000003ff + #define A2W_PLLC_PER_WIDTH 10 + #define A2W_PLLC_PER_RESET 0x00000100 + #define A2W_PLLC_PER_BYPEN_BITS 9:9 + #define A2W_PLLC_PER_BYPEN_SET 0x00000200 + #define A2W_PLLC_PER_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_PER_BYPEN_MSB 9 + #define A2W_PLLC_PER_BYPEN_LSB 9 + #define A2W_PLLC_PER_CHENB_BITS 8:8 + #define A2W_PLLC_PER_CHENB_SET 0x00000100 + #define A2W_PLLC_PER_CHENB_CLR 0xfffffeff + #define A2W_PLLC_PER_CHENB_MSB 8 + #define A2W_PLLC_PER_CHENB_LSB 8 + #define A2W_PLLC_PER_DIV_BITS 7:0 + #define A2W_PLLC_PER_DIV_SET 0x000000ff + #define A2W_PLLC_PER_DIV_CLR 0xffffff00 + #define A2W_PLLC_PER_DIV_MSB 7 + #define A2W_PLLC_PER_DIV_LSB 0 +#define A2W_PLLC_CORE0 HW_REGISTER_RW( 0x7e102620 ) + #define A2W_PLLC_CORE0_MASK 0x000003ff + #define A2W_PLLC_CORE0_WIDTH 10 + #define A2W_PLLC_CORE0_RESET 0x00000100 + #define A2W_PLLC_CORE0_BYPEN_BITS 9:9 + #define A2W_PLLC_CORE0_BYPEN_SET 0x00000200 + #define A2W_PLLC_CORE0_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_CORE0_BYPEN_MSB 9 + #define A2W_PLLC_CORE0_BYPEN_LSB 9 + #define A2W_PLLC_CORE0_CHENB_BITS 8:8 + #define A2W_PLLC_CORE0_CHENB_SET 0x00000100 + #define A2W_PLLC_CORE0_CHENB_CLR 0xfffffeff + #define A2W_PLLC_CORE0_CHENB_MSB 8 + #define A2W_PLLC_CORE0_CHENB_LSB 8 + #define A2W_PLLC_CORE0_DIV_BITS 7:0 + #define A2W_PLLC_CORE0_DIV_SET 0x000000ff + #define A2W_PLLC_CORE0_DIV_CLR 0xffffff00 + #define A2W_PLLC_CORE0_DIV_MSB 7 + #define A2W_PLLC_CORE0_DIV_LSB 0 +#define A2W_PLLD_CTRL HW_REGISTER_RW( 0x7e102140 ) + #define A2W_PLLD_CTRL_MASK 0x000373ff + #define A2W_PLLD_CTRL_WIDTH 18 + #define A2W_PLLD_CTRL_RESET 0x00010000 + #define A2W_PLLD_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLD_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLD_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLD_CTRL_PRSTN_MSB 17 + #define A2W_PLLD_CTRL_PRSTN_LSB 17 + #define A2W_PLLD_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLD_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLD_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLD_CTRL_PWRDN_MSB 16 + #define A2W_PLLD_CTRL_PWRDN_LSB 16 + #define A2W_PLLD_CTRL_PDIV_BITS 14:12 + #define A2W_PLLD_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLD_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLD_CTRL_PDIV_MSB 14 + #define A2W_PLLD_CTRL_PDIV_LSB 12 + #define A2W_PLLD_CTRL_NDIV_BITS 9:0 + #define A2W_PLLD_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLD_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLD_CTRL_NDIV_MSB 9 + #define A2W_PLLD_CTRL_NDIV_LSB 0 +#define A2W_PLLD_FRAC HW_REGISTER_RW( 0x7e102240 ) + #define A2W_PLLD_FRAC_MASK 0x000fffff + #define A2W_PLLD_FRAC_WIDTH 20 + #define A2W_PLLD_FRAC_RESET 0000000000 + #define A2W_PLLD_FRAC_FRAC_BITS 19:0 + #define A2W_PLLD_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLD_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLD_FRAC_FRAC_MSB 19 + #define A2W_PLLD_FRAC_FRAC_LSB 0 +#define A2W_PLLD_DSI0 HW_REGISTER_RW( 0x7e102340 ) + #define A2W_PLLD_DSI0_MASK 0x000003ff + #define A2W_PLLD_DSI0_WIDTH 10 + #define A2W_PLLD_DSI0_RESET 0x00000100 + #define A2W_PLLD_DSI0_BYPEN_BITS 9:9 + #define A2W_PLLD_DSI0_BYPEN_SET 0x00000200 + #define A2W_PLLD_DSI0_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_DSI0_BYPEN_MSB 9 + #define A2W_PLLD_DSI0_BYPEN_LSB 9 + #define A2W_PLLD_DSI0_CHENB_BITS 8:8 + #define A2W_PLLD_DSI0_CHENB_SET 0x00000100 + #define A2W_PLLD_DSI0_CHENB_CLR 0xfffffeff + #define A2W_PLLD_DSI0_CHENB_MSB 8 + #define A2W_PLLD_DSI0_CHENB_LSB 8 + #define A2W_PLLD_DSI0_DIV_BITS 7:0 + #define A2W_PLLD_DSI0_DIV_SET 0x000000ff + #define A2W_PLLD_DSI0_DIV_CLR 0xffffff00 + #define A2W_PLLD_DSI0_DIV_MSB 7 + #define A2W_PLLD_DSI0_DIV_LSB 0 +#define A2W_PLLD_CORE HW_REGISTER_RW( 0x7e102440 ) + #define A2W_PLLD_CORE_MASK 0x000003ff + #define A2W_PLLD_CORE_WIDTH 10 + #define A2W_PLLD_CORE_RESET 0x00000100 + #define A2W_PLLD_CORE_BYPEN_BITS 9:9 + #define A2W_PLLD_CORE_BYPEN_SET 0x00000200 + #define A2W_PLLD_CORE_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_CORE_BYPEN_MSB 9 + #define A2W_PLLD_CORE_BYPEN_LSB 9 + #define A2W_PLLD_CORE_CHENB_BITS 8:8 + #define A2W_PLLD_CORE_CHENB_SET 0x00000100 + #define A2W_PLLD_CORE_CHENB_CLR 0xfffffeff + #define A2W_PLLD_CORE_CHENB_MSB 8 + #define A2W_PLLD_CORE_CHENB_LSB 8 + #define A2W_PLLD_CORE_DIV_BITS 7:0 + #define A2W_PLLD_CORE_DIV_SET 0x000000ff + #define A2W_PLLD_CORE_DIV_CLR 0xffffff00 + #define A2W_PLLD_CORE_DIV_MSB 7 + #define A2W_PLLD_CORE_DIV_LSB 0 +#define A2W_PLLD_PER HW_REGISTER_RW( 0x7e102540 ) + #define A2W_PLLD_PER_MASK 0x000003ff + #define A2W_PLLD_PER_WIDTH 10 + #define A2W_PLLD_PER_RESET 0x00000100 + #define A2W_PLLD_PER_BYPEN_BITS 9:9 + #define A2W_PLLD_PER_BYPEN_SET 0x00000200 + #define A2W_PLLD_PER_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_PER_BYPEN_MSB 9 + #define A2W_PLLD_PER_BYPEN_LSB 9 + #define A2W_PLLD_PER_CHENB_BITS 8:8 + #define A2W_PLLD_PER_CHENB_SET 0x00000100 + #define A2W_PLLD_PER_CHENB_CLR 0xfffffeff + #define A2W_PLLD_PER_CHENB_MSB 8 + #define A2W_PLLD_PER_CHENB_LSB 8 + #define A2W_PLLD_PER_DIV_BITS 7:0 + #define A2W_PLLD_PER_DIV_SET 0x000000ff + #define A2W_PLLD_PER_DIV_CLR 0xffffff00 + #define A2W_PLLD_PER_DIV_MSB 7 + #define A2W_PLLD_PER_DIV_LSB 0 +#define A2W_PLLD_DSI1 HW_REGISTER_RW( 0x7e102640 ) + #define A2W_PLLD_DSI1_MASK 0x000003ff + #define A2W_PLLD_DSI1_WIDTH 10 + #define A2W_PLLD_DSI1_RESET 0x00000100 + #define A2W_PLLD_DSI1_BYPEN_BITS 9:9 + #define A2W_PLLD_DSI1_BYPEN_SET 0x00000200 + #define A2W_PLLD_DSI1_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_DSI1_BYPEN_MSB 9 + #define A2W_PLLD_DSI1_BYPEN_LSB 9 + #define A2W_PLLD_DSI1_CHENB_BITS 8:8 + #define A2W_PLLD_DSI1_CHENB_SET 0x00000100 + #define A2W_PLLD_DSI1_CHENB_CLR 0xfffffeff + #define A2W_PLLD_DSI1_CHENB_MSB 8 + #define A2W_PLLD_DSI1_CHENB_LSB 8 + #define A2W_PLLD_DSI1_DIV_BITS 7:0 + #define A2W_PLLD_DSI1_DIV_SET 0x000000ff + #define A2W_PLLD_DSI1_DIV_CLR 0xffffff00 + #define A2W_PLLD_DSI1_DIV_MSB 7 + #define A2W_PLLD_DSI1_DIV_LSB 0 +#define A2W_PLLH_CTRL HW_REGISTER_RW( 0x7e102160 ) + #define A2W_PLLH_CTRL_MASK 0x000370ff + #define A2W_PLLH_CTRL_WIDTH 18 + #define A2W_PLLH_CTRL_RESET 0x00010000 + #define A2W_PLLH_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLH_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLH_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLH_CTRL_PRSTN_MSB 17 + #define A2W_PLLH_CTRL_PRSTN_LSB 17 + #define A2W_PLLH_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLH_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLH_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLH_CTRL_PWRDN_MSB 16 + #define A2W_PLLH_CTRL_PWRDN_LSB 16 + #define A2W_PLLH_CTRL_PDIV_BITS 14:12 + #define A2W_PLLH_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLH_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLH_CTRL_PDIV_MSB 14 + #define A2W_PLLH_CTRL_PDIV_LSB 12 + #define A2W_PLLH_CTRL_NDIV_BITS 7:0 + #define A2W_PLLH_CTRL_NDIV_SET 0x000000ff + #define A2W_PLLH_CTRL_NDIV_CLR 0xffffff00 + #define A2W_PLLH_CTRL_NDIV_MSB 7 + #define A2W_PLLH_CTRL_NDIV_LSB 0 +#define A2W_PLLH_FRAC HW_REGISTER_RW( 0x7e102260 ) + #define A2W_PLLH_FRAC_MASK 0x000fffff + #define A2W_PLLH_FRAC_WIDTH 20 + #define A2W_PLLH_FRAC_RESET 0000000000 + #define A2W_PLLH_FRAC_FRAC_BITS 19:0 + #define A2W_PLLH_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLH_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLH_FRAC_FRAC_MSB 19 + #define A2W_PLLH_FRAC_FRAC_LSB 0 +#define A2W_PLLH_AUX HW_REGISTER_RW( 0x7e102360 ) + #define A2W_PLLH_AUX_MASK 0x000003ff + #define A2W_PLLH_AUX_WIDTH 10 + #define A2W_PLLH_AUX_RESET 0x00000100 + #define A2W_PLLH_AUX_BYPEN_BITS 9:9 + #define A2W_PLLH_AUX_BYPEN_SET 0x00000200 + #define A2W_PLLH_AUX_BYPEN_CLR 0xfffffdff + #define A2W_PLLH_AUX_BYPEN_MSB 9 + #define A2W_PLLH_AUX_BYPEN_LSB 9 + #define A2W_PLLH_AUX_CHENB_BITS 8:8 + #define A2W_PLLH_AUX_CHENB_SET 0x00000100 + #define A2W_PLLH_AUX_CHENB_CLR 0xfffffeff + #define A2W_PLLH_AUX_CHENB_MSB 8 + #define A2W_PLLH_AUX_CHENB_LSB 8 + #define A2W_PLLH_AUX_DIV_BITS 7:0 + #define A2W_PLLH_AUX_DIV_SET 0x000000ff + #define A2W_PLLH_AUX_DIV_CLR 0xffffff00 + #define A2W_PLLH_AUX_DIV_MSB 7 + #define A2W_PLLH_AUX_DIV_LSB 0 +#define A2W_PLLH_RCAL HW_REGISTER_RW( 0x7e102460 ) + #define A2W_PLLH_RCAL_MASK 0x000003ff + #define A2W_PLLH_RCAL_WIDTH 10 + #define A2W_PLLH_RCAL_RESET 0x00000100 + #define A2W_PLLH_RCAL_BYPEN_BITS 9:9 + #define A2W_PLLH_RCAL_BYPEN_SET 0x00000200 + #define A2W_PLLH_RCAL_BYPEN_CLR 0xfffffdff + #define A2W_PLLH_RCAL_BYPEN_MSB 9 + #define A2W_PLLH_RCAL_BYPEN_LSB 9 + #define A2W_PLLH_RCAL_CHENB_BITS 8:8 + #define A2W_PLLH_RCAL_CHENB_SET 0x00000100 + #define A2W_PLLH_RCAL_CHENB_CLR 0xfffffeff + #define A2W_PLLH_RCAL_CHENB_MSB 8 + #define A2W_PLLH_RCAL_CHENB_LSB 8 + #define A2W_PLLH_RCAL_DIV_BITS 7:0 + #define A2W_PLLH_RCAL_DIV_SET 0x000000ff + #define A2W_PLLH_RCAL_DIV_CLR 0xffffff00 + #define A2W_PLLH_RCAL_DIV_MSB 7 + #define A2W_PLLH_RCAL_DIV_LSB 0 +#define A2W_PLLH_PIX HW_REGISTER_RW( 0x7e102560 ) + #define A2W_PLLH_PIX_MASK 0x000003ff + #define A2W_PLLH_PIX_WIDTH 10 + #define A2W_PLLH_PIX_RESET 0x00000100 + #define A2W_PLLH_PIX_BYPEN_BITS 9:9 + #define A2W_PLLH_PIX_BYPEN_SET 0x00000200 + #define A2W_PLLH_PIX_BYPEN_CLR 0xfffffdff + #define A2W_PLLH_PIX_BYPEN_MSB 9 + #define A2W_PLLH_PIX_BYPEN_LSB 9 + #define A2W_PLLH_PIX_CHENB_BITS 8:8 + #define A2W_PLLH_PIX_CHENB_SET 0x00000100 + #define A2W_PLLH_PIX_CHENB_CLR 0xfffffeff + #define A2W_PLLH_PIX_CHENB_MSB 8 + #define A2W_PLLH_PIX_CHENB_LSB 8 + #define A2W_PLLH_PIX_DIV_BITS 7:0 + #define A2W_PLLH_PIX_DIV_SET 0x000000ff + #define A2W_PLLH_PIX_DIV_CLR 0xffffff00 + #define A2W_PLLH_PIX_DIV_MSB 7 + #define A2W_PLLH_PIX_DIV_LSB 0 +#define A2W_SMPS_A_MODE HW_REGISTER_RW( 0x7e1021a0 ) + #define A2W_SMPS_A_MODE_MASK 0x00000001 + #define A2W_SMPS_A_MODE_WIDTH 1 + #define A2W_SMPS_A_MODE_RESET 0000000000 + #define A2W_SMPS_A_MODE_BSTPWMB_BITS 0:0 + #define A2W_SMPS_A_MODE_BSTPWMB_SET 0x00000001 + #define A2W_SMPS_A_MODE_BSTPWMB_CLR 0xfffffffe + #define A2W_SMPS_A_MODE_BSTPWMB_MSB 0 + #define A2W_SMPS_A_MODE_BSTPWMB_LSB 0 +#define A2W_SMPS_A_VOLTS HW_REGISTER_RW( 0x7e1022a0 ) + #define A2W_SMPS_A_VOLTS_MASK 0x0000001f + #define A2W_SMPS_A_VOLTS_WIDTH 5 + #define A2W_SMPS_A_VOLTS_RESET 0000000000 + #define A2W_SMPS_A_VOLTS_VOLTS_BITS 4:0 + #define A2W_SMPS_A_VOLTS_VOLTS_SET 0x0000001f + #define A2W_SMPS_A_VOLTS_VOLTS_CLR 0xffffffe0 + #define A2W_SMPS_A_VOLTS_VOLTS_MSB 4 + #define A2W_SMPS_A_VOLTS_VOLTS_LSB 0 +#define A2W_SMPS_A_GAIN HW_REGISTER_RW( 0x7e1023a0 ) + #define A2W_SMPS_A_GAIN_MASK 0x00000007 + #define A2W_SMPS_A_GAIN_WIDTH 3 + #define A2W_SMPS_A_GAIN_RESET 0000000000 + #define A2W_SMPS_A_GAIN_DIGGAIN_BITS 2:0 + #define A2W_SMPS_A_GAIN_DIGGAIN_SET 0x00000007 + #define A2W_SMPS_A_GAIN_DIGGAIN_CLR 0xfffffff8 + #define A2W_SMPS_A_GAIN_DIGGAIN_MSB 2 + #define A2W_SMPS_A_GAIN_DIGGAIN_LSB 0 +#define A2W_SMPS_B_STAT HW_REGISTER_RW( 0x7e1021b0 ) + #define A2W_SMPS_B_STAT_MASK 0x0000111f + #define A2W_SMPS_B_STAT_WIDTH 13 + #define A2W_SMPS_B_STAT_RESET 0000000000 + #define A2W_SMPS_B_STAT_POK_BITS 12:12 + #define A2W_SMPS_B_STAT_POK_SET 0x00001000 + #define A2W_SMPS_B_STAT_POK_CLR 0xffffefff + #define A2W_SMPS_B_STAT_POK_MSB 12 + #define A2W_SMPS_B_STAT_POK_LSB 12 + #define A2W_SMPS_B_STAT_BSTPWMB_BITS 8:8 + #define A2W_SMPS_B_STAT_BSTPWMB_SET 0x00000100 + #define A2W_SMPS_B_STAT_BSTPWMB_CLR 0xfffffeff + #define A2W_SMPS_B_STAT_BSTPWMB_MSB 8 + #define A2W_SMPS_B_STAT_BSTPWMB_LSB 8 + #define A2W_SMPS_B_STAT_VOLTS_BITS 4:0 + #define A2W_SMPS_B_STAT_VOLTS_SET 0x0000001f + #define A2W_SMPS_B_STAT_VOLTS_CLR 0xffffffe0 + #define A2W_SMPS_B_STAT_VOLTS_MSB 4 + #define A2W_SMPS_B_STAT_VOLTS_LSB 0 +#define A2W_SMPS_C_CLK HW_REGISTER_RW( 0x7e1021c0 ) + #define A2W_SMPS_C_CLK_MASK 0x0000000f + #define A2W_SMPS_C_CLK_WIDTH 4 + #define A2W_SMPS_C_CLK_RESET 0000000000 + #define A2W_SMPS_C_CLK_TDEN_BITS 3:3 + #define A2W_SMPS_C_CLK_TDEN_SET 0x00000008 + #define A2W_SMPS_C_CLK_TDEN_CLR 0xfffffff7 + #define A2W_SMPS_C_CLK_TDEN_MSB 3 + #define A2W_SMPS_C_CLK_TDEN_LSB 3 + #define A2W_SMPS_C_CLK_USEOSC_BITS 2:2 + #define A2W_SMPS_C_CLK_USEOSC_SET 0x00000004 + #define A2W_SMPS_C_CLK_USEOSC_CLR 0xfffffffb + #define A2W_SMPS_C_CLK_USEOSC_MSB 2 + #define A2W_SMPS_C_CLK_USEOSC_LSB 2 + #define A2W_SMPS_C_CLK_OSCDIV_BITS 1:0 + #define A2W_SMPS_C_CLK_OSCDIV_SET 0x00000003 + #define A2W_SMPS_C_CLK_OSCDIV_CLR 0xfffffffc + #define A2W_SMPS_C_CLK_OSCDIV_MSB 1 + #define A2W_SMPS_C_CLK_OSCDIV_LSB 0 +#define A2W_SMPS_C_CTL HW_REGISTER_RW( 0x7e1022c0 ) + #define A2W_SMPS_C_CTL_MASK 0x00000003 + #define A2W_SMPS_C_CTL_WIDTH 2 + #define A2W_SMPS_C_CTL_RESET 0000000000 + #define A2W_SMPS_C_CTL_UPEN_BITS 1:1 + #define A2W_SMPS_C_CTL_UPEN_SET 0x00000002 + #define A2W_SMPS_C_CTL_UPEN_CLR 0xfffffffd + #define A2W_SMPS_C_CTL_UPEN_MSB 1 + #define A2W_SMPS_C_CTL_UPEN_LSB 1 + #define A2W_SMPS_C_CTL_CTRLEN_BITS 0:0 + #define A2W_SMPS_C_CTL_CTRLEN_SET 0x00000001 + #define A2W_SMPS_C_CTL_CTRLEN_CLR 0xfffffffe + #define A2W_SMPS_C_CTL_CTRLEN_MSB 0 + #define A2W_SMPS_C_CTL_CTRLEN_LSB 0 +#define A2W_SMPS_L_SPV HW_REGISTER_RW( 0x7e1021d0 ) + #define A2W_SMPS_L_SPV_MASK 0x0000001f + #define A2W_SMPS_L_SPV_WIDTH 5 + #define A2W_SMPS_L_SPV_RESET 0000000000 + #define A2W_SMPS_L_SPV_VOLTS_BITS 4:0 + #define A2W_SMPS_L_SPV_VOLTS_SET 0x0000001f + #define A2W_SMPS_L_SPV_VOLTS_CLR 0xffffffe0 + #define A2W_SMPS_L_SPV_VOLTS_MSB 4 + #define A2W_SMPS_L_SPV_VOLTS_LSB 0 +#define A2W_SMPS_L_SPA HW_REGISTER_RW( 0x7e1022d0 ) + #define A2W_SMPS_L_SPA_MASK 0x000003ff + #define A2W_SMPS_L_SPA_WIDTH 10 + #define A2W_SMPS_L_SPA_RESET 0000000000 + #define A2W_SMPS_L_SPA_ANA_BITS 9:0 + #define A2W_SMPS_L_SPA_ANA_SET 0x000003ff + #define A2W_SMPS_L_SPA_ANA_CLR 0xfffffc00 + #define A2W_SMPS_L_SPA_ANA_MSB 9 + #define A2W_SMPS_L_SPA_ANA_LSB 0 +#define A2W_SMPS_L_SCV HW_REGISTER_RW( 0x7e1023d0 ) + #define A2W_SMPS_L_SCV_MASK 0x0000001f + #define A2W_SMPS_L_SCV_WIDTH 5 + #define A2W_SMPS_L_SCV_RESET 0000000000 + #define A2W_SMPS_L_SCV_VOLTS_BITS 4:0 + #define A2W_SMPS_L_SCV_VOLTS_SET 0x0000001f + #define A2W_SMPS_L_SCV_VOLTS_CLR 0xffffffe0 + #define A2W_SMPS_L_SCV_VOLTS_MSB 4 + #define A2W_SMPS_L_SCV_VOLTS_LSB 0 +#define A2W_SMPS_L_SCA HW_REGISTER_RW( 0x7e1024d0 ) + #define A2W_SMPS_L_SCA_MASK 0x00000fff + #define A2W_SMPS_L_SCA_WIDTH 12 + #define A2W_SMPS_L_SCA_RESET 0000000000 + #define A2W_SMPS_L_SCA_ANA_BITS 11:0 + #define A2W_SMPS_L_SCA_ANA_SET 0x00000fff + #define A2W_SMPS_L_SCA_ANA_CLR 0xfffff000 + #define A2W_SMPS_L_SCA_ANA_MSB 11 + #define A2W_SMPS_L_SCA_ANA_LSB 0 +#define A2W_SMPS_L_SIV HW_REGISTER_RW( 0x7e1025d0 ) + #define A2W_SMPS_L_SIV_MASK 0x0000001f + #define A2W_SMPS_L_SIV_WIDTH 5 + #define A2W_SMPS_L_SIV_RESET 0000000000 + #define A2W_SMPS_L_SIV_VOLTS_BITS 4:0 + #define A2W_SMPS_L_SIV_VOLTS_SET 0x0000001f + #define A2W_SMPS_L_SIV_VOLTS_CLR 0xffffffe0 + #define A2W_SMPS_L_SIV_VOLTS_MSB 4 + #define A2W_SMPS_L_SIV_VOLTS_LSB 0 +#define A2W_SMPS_L_SIA HW_REGISTER_RW( 0x7e1026d0 ) + #define A2W_SMPS_L_SIA_MASK 0x000003ff + #define A2W_SMPS_L_SIA_WIDTH 10 + #define A2W_SMPS_L_SIA_RESET 0000000000 + #define A2W_SMPS_L_SIA_ANA_BITS 9:0 + #define A2W_SMPS_L_SIA_ANA_SET 0x000003ff + #define A2W_SMPS_L_SIA_ANA_CLR 0xfffffc00 + #define A2W_SMPS_L_SIA_ANA_MSB 9 + #define A2W_SMPS_L_SIA_ANA_LSB 0 +#define A2W_XOSC_CTRL HW_REGISTER_RW( 0x7e102190 ) + #define A2W_XOSC_CTRL_MASK 0x000ff0ff + #define A2W_XOSC_CTRL_WIDTH 20 + #define A2W_XOSC_CTRL_RESET 0000000000 + #define A2W_XOSC_CTRL_PLLBOK_BITS 19:19 + #define A2W_XOSC_CTRL_PLLBOK_SET 0x00080000 + #define A2W_XOSC_CTRL_PLLBOK_CLR 0xfff7ffff + #define A2W_XOSC_CTRL_PLLBOK_MSB 19 + #define A2W_XOSC_CTRL_PLLBOK_LSB 19 + #define A2W_XOSC_CTRL_PLLAOK_BITS 18:18 + #define A2W_XOSC_CTRL_PLLAOK_SET 0x00040000 + #define A2W_XOSC_CTRL_PLLAOK_CLR 0xfffbffff + #define A2W_XOSC_CTRL_PLLAOK_MSB 18 + #define A2W_XOSC_CTRL_PLLAOK_LSB 18 + #define A2W_XOSC_CTRL_PLLDOK_BITS 17:17 + #define A2W_XOSC_CTRL_PLLDOK_SET 0x00020000 + #define A2W_XOSC_CTRL_PLLDOK_CLR 0xfffdffff + #define A2W_XOSC_CTRL_PLLDOK_MSB 17 + #define A2W_XOSC_CTRL_PLLDOK_LSB 17 + #define A2W_XOSC_CTRL_DDROK_BITS 16:16 + #define A2W_XOSC_CTRL_DDROK_SET 0x00010000 + #define A2W_XOSC_CTRL_DDROK_CLR 0xfffeffff + #define A2W_XOSC_CTRL_DDROK_MSB 16 + #define A2W_XOSC_CTRL_DDROK_LSB 16 + #define A2W_XOSC_CTRL_SMPSOK_BITS 15:15 + #define A2W_XOSC_CTRL_SMPSOK_SET 0x00008000 + #define A2W_XOSC_CTRL_SMPSOK_CLR 0xffff7fff + #define A2W_XOSC_CTRL_SMPSOK_MSB 15 + #define A2W_XOSC_CTRL_SMPSOK_LSB 15 + #define A2W_XOSC_CTRL_USBOK_BITS 14:14 + #define A2W_XOSC_CTRL_USBOK_SET 0x00004000 + #define A2W_XOSC_CTRL_USBOK_CLR 0xffffbfff + #define A2W_XOSC_CTRL_USBOK_MSB 14 + #define A2W_XOSC_CTRL_USBOK_LSB 14 + #define A2W_XOSC_CTRL_HDMIOK_BITS 13:13 + #define A2W_XOSC_CTRL_HDMIOK_SET 0x00002000 + #define A2W_XOSC_CTRL_HDMIOK_CLR 0xffffdfff + #define A2W_XOSC_CTRL_HDMIOK_MSB 13 + #define A2W_XOSC_CTRL_HDMIOK_LSB 13 + #define A2W_XOSC_CTRL_PLLCOK_BITS 12:12 + #define A2W_XOSC_CTRL_PLLCOK_SET 0x00001000 + #define A2W_XOSC_CTRL_PLLCOK_CLR 0xffffefff + #define A2W_XOSC_CTRL_PLLCOK_MSB 12 + #define A2W_XOSC_CTRL_PLLCOK_LSB 12 + #define A2W_XOSC_CTRL_PLLBEN_BITS 7:7 + #define A2W_XOSC_CTRL_PLLBEN_SET 0x00000080 + #define A2W_XOSC_CTRL_PLLBEN_CLR 0xffffff7f + #define A2W_XOSC_CTRL_PLLBEN_MSB 7 + #define A2W_XOSC_CTRL_PLLBEN_LSB 7 + #define A2W_XOSC_CTRL_PLLAEN_BITS 6:6 + #define A2W_XOSC_CTRL_PLLAEN_SET 0x00000040 + #define A2W_XOSC_CTRL_PLLAEN_CLR 0xffffffbf + #define A2W_XOSC_CTRL_PLLAEN_MSB 6 + #define A2W_XOSC_CTRL_PLLAEN_LSB 6 + #define A2W_XOSC_CTRL_PLLDEN_BITS 5:5 + #define A2W_XOSC_CTRL_PLLDEN_SET 0x00000020 + #define A2W_XOSC_CTRL_PLLDEN_CLR 0xffffffdf + #define A2W_XOSC_CTRL_PLLDEN_MSB 5 + #define A2W_XOSC_CTRL_PLLDEN_LSB 5 + #define A2W_XOSC_CTRL_DDREN_BITS 4:4 + #define A2W_XOSC_CTRL_DDREN_SET 0x00000010 + #define A2W_XOSC_CTRL_DDREN_CLR 0xffffffef + #define A2W_XOSC_CTRL_DDREN_MSB 4 + #define A2W_XOSC_CTRL_DDREN_LSB 4 + #define A2W_XOSC_CTRL_SMPSEN_BITS 3:3 + #define A2W_XOSC_CTRL_SMPSEN_SET 0x00000008 + #define A2W_XOSC_CTRL_SMPSEN_CLR 0xfffffff7 + #define A2W_XOSC_CTRL_SMPSEN_MSB 3 + #define A2W_XOSC_CTRL_SMPSEN_LSB 3 + #define A2W_XOSC_CTRL_USBEN_BITS 2:2 + #define A2W_XOSC_CTRL_USBEN_SET 0x00000004 + #define A2W_XOSC_CTRL_USBEN_CLR 0xfffffffb + #define A2W_XOSC_CTRL_USBEN_MSB 2 + #define A2W_XOSC_CTRL_USBEN_LSB 2 + #define A2W_XOSC_CTRL_HDMIEN_BITS 1:1 + #define A2W_XOSC_CTRL_HDMIEN_SET 0x00000002 + #define A2W_XOSC_CTRL_HDMIEN_CLR 0xfffffffd + #define A2W_XOSC_CTRL_HDMIEN_MSB 1 + #define A2W_XOSC_CTRL_HDMIEN_LSB 1 + #define A2W_XOSC_CTRL_PLLCEN_BITS 0:0 + #define A2W_XOSC_CTRL_PLLCEN_SET 0x00000001 + #define A2W_XOSC_CTRL_PLLCEN_CLR 0xfffffffe + #define A2W_XOSC_CTRL_PLLCEN_MSB 0 + #define A2W_XOSC_CTRL_PLLCEN_LSB 0 +#define A2W_XOSC_CPR HW_REGISTER_RW( 0x7e102290 ) + #define A2W_XOSC_CPR_MASK 0x00000013 + #define A2W_XOSC_CPR_WIDTH 5 + #define A2W_XOSC_CPR_RESET 0000000000 + #define A2W_XOSC_CPR_CPR1_BITS 4:4 + #define A2W_XOSC_CPR_CPR1_SET 0x00000010 + #define A2W_XOSC_CPR_CPR1_CLR 0xffffffef + #define A2W_XOSC_CPR_CPR1_MSB 4 + #define A2W_XOSC_CPR_CPR1_LSB 4 + #define A2W_XOSC_CPR_DIV_BITS 1:0 + #define A2W_XOSC_CPR_DIV_SET 0x00000003 + #define A2W_XOSC_CPR_DIV_CLR 0xfffffffc + #define A2W_XOSC_CPR_DIV_MSB 1 + #define A2W_XOSC_CPR_DIV_LSB 0 +#define A2W_XOSC_BIAS HW_REGISTER_RW( 0x7e102390 ) + #define A2W_XOSC_BIAS_MASK 0x0000001f + #define A2W_XOSC_BIAS_WIDTH 5 + #define A2W_XOSC_BIAS_RESET 0x00000018 + #define A2W_XOSC_BIAS_HIGHP_BITS 4:4 + #define A2W_XOSC_BIAS_HIGHP_SET 0x00000010 + #define A2W_XOSC_BIAS_HIGHP_CLR 0xffffffef + #define A2W_XOSC_BIAS_HIGHP_MSB 4 + #define A2W_XOSC_BIAS_HIGHP_LSB 4 + #define A2W_XOSC_BIAS_BIAS_BITS 3:0 + #define A2W_XOSC_BIAS_BIAS_SET 0x0000000f + #define A2W_XOSC_BIAS_BIAS_CLR 0xfffffff0 + #define A2W_XOSC_BIAS_BIAS_MSB 3 + #define A2W_XOSC_BIAS_BIAS_LSB 0 +#define A2W_XOSC_PWR HW_REGISTER_RW( 0x7e102490 ) + #define A2W_XOSC_PWR_MASK 0x00000007 + #define A2W_XOSC_PWR_WIDTH 3 + #define A2W_XOSC_PWR_RESET 0x00000004 + #define A2W_XOSC_PWR_RSTB_BITS 2:2 + #define A2W_XOSC_PWR_RSTB_SET 0x00000004 + #define A2W_XOSC_PWR_RSTB_CLR 0xfffffffb + #define A2W_XOSC_PWR_RSTB_MSB 2 + #define A2W_XOSC_PWR_RSTB_LSB 2 + #define A2W_XOSC_PWR_PWRDN_BITS 1:1 + #define A2W_XOSC_PWR_PWRDN_SET 0x00000002 + #define A2W_XOSC_PWR_PWRDN_CLR 0xfffffffd + #define A2W_XOSC_PWR_PWRDN_MSB 1 + #define A2W_XOSC_PWR_PWRDN_LSB 1 + #define A2W_XOSC_PWR_BYPASS_BITS 0:0 + #define A2W_XOSC_PWR_BYPASS_SET 0x00000001 + #define A2W_XOSC_PWR_BYPASS_CLR 0xfffffffe + #define A2W_XOSC_PWR_BYPASS_MSB 0 + #define A2W_XOSC_PWR_BYPASS_LSB 0 +#define A2W_PLLA_ANA_SSCS HW_REGISTER_RW( 0x7e102110 ) + #define A2W_PLLA_ANA_SSCS_MASK 0x0001ffff + #define A2W_PLLA_ANA_SSCS_WIDTH 17 + #define A2W_PLLA_ANA_SSCS_RESET 0000000000 + #define A2W_PLLA_ANA_SSCS_MODE_BITS 16:16 + #define A2W_PLLA_ANA_SSCS_MODE_SET 0x00010000 + #define A2W_PLLA_ANA_SSCS_MODE_CLR 0xfffeffff + #define A2W_PLLA_ANA_SSCS_MODE_MSB 16 + #define A2W_PLLA_ANA_SSCS_MODE_LSB 16 + #define A2W_PLLA_ANA_SSCS_STEP_BITS 15:0 + #define A2W_PLLA_ANA_SSCS_STEP_SET 0x0000ffff + #define A2W_PLLA_ANA_SSCS_STEP_CLR 0xffff0000 + #define A2W_PLLA_ANA_SSCS_STEP_MSB 15 + #define A2W_PLLA_ANA_SSCS_STEP_LSB 0 +#define A2W_PLLA_ANA_SSCL HW_REGISTER_RW( 0x7e102210 ) + #define A2W_PLLA_ANA_SSCL_MASK 0x003fffff + #define A2W_PLLA_ANA_SSCL_WIDTH 22 + #define A2W_PLLA_ANA_SSCL_RESET 0000000000 + #define A2W_PLLA_ANA_SSCL_LIMIT_BITS 21:0 + #define A2W_PLLA_ANA_SSCL_LIMIT_SET 0x003fffff + #define A2W_PLLA_ANA_SSCL_LIMIT_CLR 0xffc00000 + #define A2W_PLLA_ANA_SSCL_LIMIT_MSB 21 + #define A2W_PLLA_ANA_SSCL_LIMIT_LSB 0 +#define A2W_PLLA_ANA_KAIP HW_REGISTER_RW( 0x7e102310 ) + #define A2W_PLLA_ANA_KAIP_MASK 0x0000077f + #define A2W_PLLA_ANA_KAIP_WIDTH 11 + #define A2W_PLLA_ANA_KAIP_RESET 0x0000033a + #define A2W_PLLA_ANA_KAIP_KA_BITS 10:8 + #define A2W_PLLA_ANA_KAIP_KA_SET 0x00000700 + #define A2W_PLLA_ANA_KAIP_KA_CLR 0xfffff8ff + #define A2W_PLLA_ANA_KAIP_KA_MSB 10 + #define A2W_PLLA_ANA_KAIP_KA_LSB 8 + #define A2W_PLLA_ANA_KAIP_KI_BITS 6:4 + #define A2W_PLLA_ANA_KAIP_KI_SET 0x00000070 + #define A2W_PLLA_ANA_KAIP_KI_CLR 0xffffff8f + #define A2W_PLLA_ANA_KAIP_KI_MSB 6 + #define A2W_PLLA_ANA_KAIP_KI_LSB 4 + #define A2W_PLLA_ANA_KAIP_KP_BITS 3:0 + #define A2W_PLLA_ANA_KAIP_KP_SET 0x0000000f + #define A2W_PLLA_ANA_KAIP_KP_CLR 0xfffffff0 + #define A2W_PLLA_ANA_KAIP_KP_MSB 3 + #define A2W_PLLA_ANA_KAIP_KP_LSB 0 +#define A2W_PLLA_ANA_STAT HW_REGISTER_RW( 0x7e102410 ) + #define A2W_PLLA_ANA_STAT_MASK 0x00000fff + #define A2W_PLLA_ANA_STAT_WIDTH 12 + #define A2W_PLLA_ANA_STAT_RESET 0000000000 + #define A2W_PLLA_ANA_STAT_DATA_BITS 11:0 + #define A2W_PLLA_ANA_STAT_DATA_SET 0x00000fff + #define A2W_PLLA_ANA_STAT_DATA_CLR 0xfffff000 + #define A2W_PLLA_ANA_STAT_DATA_MSB 11 + #define A2W_PLLA_ANA_STAT_DATA_LSB 0 +#define A2W_PLLA_ANA_SCTL HW_REGISTER_RW( 0x7e102510 ) + #define A2W_PLLA_ANA_SCTL_MASK 0x0000001f + #define A2W_PLLA_ANA_SCTL_WIDTH 5 + #define A2W_PLLA_ANA_SCTL_RESET 0000000000 + #define A2W_PLLA_ANA_SCTL_RESET_BITS 4:4 + #define A2W_PLLA_ANA_SCTL_RESET_SET 0x00000010 + #define A2W_PLLA_ANA_SCTL_RESET_CLR 0xffffffef + #define A2W_PLLA_ANA_SCTL_RESET_MSB 4 + #define A2W_PLLA_ANA_SCTL_RESET_LSB 4 + #define A2W_PLLA_ANA_SCTL_UPDATE_BITS 3:3 + #define A2W_PLLA_ANA_SCTL_UPDATE_SET 0x00000008 + #define A2W_PLLA_ANA_SCTL_UPDATE_CLR 0xfffffff7 + #define A2W_PLLA_ANA_SCTL_UPDATE_MSB 3 + #define A2W_PLLA_ANA_SCTL_UPDATE_LSB 3 + #define A2W_PLLA_ANA_SCTL_SEL_BITS 2:0 + #define A2W_PLLA_ANA_SCTL_SEL_SET 0x00000007 + #define A2W_PLLA_ANA_SCTL_SEL_CLR 0xfffffff8 + #define A2W_PLLA_ANA_SCTL_SEL_MSB 2 + #define A2W_PLLA_ANA_SCTL_SEL_LSB 0 +#define A2W_PLLA_ANA_VCO HW_REGISTER_RW( 0x7e102610 ) + #define A2W_PLLA_ANA_VCO_MASK 0x00000001 + #define A2W_PLLA_ANA_VCO_WIDTH 1 + #define A2W_PLLA_ANA_VCO_RESET 0000000000 + #define A2W_PLLA_ANA_VCO_RANGE_BITS 0:0 + #define A2W_PLLA_ANA_VCO_RANGE_SET 0x00000001 + #define A2W_PLLA_ANA_VCO_RANGE_CLR 0xfffffffe + #define A2W_PLLA_ANA_VCO_RANGE_MSB 0 + #define A2W_PLLA_ANA_VCO_RANGE_LSB 0 +#define A2W_PLLB_ANA_SSCS HW_REGISTER_RW( 0x7e1021f0 ) + #define A2W_PLLB_ANA_SSCS_MASK 0x0001ffff + #define A2W_PLLB_ANA_SSCS_WIDTH 17 + #define A2W_PLLB_ANA_SSCS_RESET 0000000000 + #define A2W_PLLB_ANA_SSCS_MODE_BITS 16:16 + #define A2W_PLLB_ANA_SSCS_MODE_SET 0x00010000 + #define A2W_PLLB_ANA_SSCS_MODE_CLR 0xfffeffff + #define A2W_PLLB_ANA_SSCS_MODE_MSB 16 + #define A2W_PLLB_ANA_SSCS_MODE_LSB 16 + #define A2W_PLLB_ANA_SSCS_STEP_BITS 15:0 + #define A2W_PLLB_ANA_SSCS_STEP_SET 0x0000ffff + #define A2W_PLLB_ANA_SSCS_STEP_CLR 0xffff0000 + #define A2W_PLLB_ANA_SSCS_STEP_MSB 15 + #define A2W_PLLB_ANA_SSCS_STEP_LSB 0 +#define A2W_PLLB_ANA_SSCL HW_REGISTER_RW( 0x7e1022f0 ) + #define A2W_PLLB_ANA_SSCL_MASK 0x003fffff + #define A2W_PLLB_ANA_SSCL_WIDTH 22 + #define A2W_PLLB_ANA_SSCL_RESET 0000000000 + #define A2W_PLLB_ANA_SSCL_LIMIT_BITS 21:0 + #define A2W_PLLB_ANA_SSCL_LIMIT_SET 0x003fffff + #define A2W_PLLB_ANA_SSCL_LIMIT_CLR 0xffc00000 + #define A2W_PLLB_ANA_SSCL_LIMIT_MSB 21 + #define A2W_PLLB_ANA_SSCL_LIMIT_LSB 0 +#define A2W_PLLB_ANA_KAIP HW_REGISTER_RW( 0x7e1023f0 ) + #define A2W_PLLB_ANA_KAIP_MASK 0x0000077f + #define A2W_PLLB_ANA_KAIP_WIDTH 11 + #define A2W_PLLB_ANA_KAIP_RESET 0x0000033a + #define A2W_PLLB_ANA_KAIP_KA_BITS 10:8 + #define A2W_PLLB_ANA_KAIP_KA_SET 0x00000700 + #define A2W_PLLB_ANA_KAIP_KA_CLR 0xfffff8ff + #define A2W_PLLB_ANA_KAIP_KA_MSB 10 + #define A2W_PLLB_ANA_KAIP_KA_LSB 8 + #define A2W_PLLB_ANA_KAIP_KI_BITS 6:4 + #define A2W_PLLB_ANA_KAIP_KI_SET 0x00000070 + #define A2W_PLLB_ANA_KAIP_KI_CLR 0xffffff8f + #define A2W_PLLB_ANA_KAIP_KI_MSB 6 + #define A2W_PLLB_ANA_KAIP_KI_LSB 4 + #define A2W_PLLB_ANA_KAIP_KP_BITS 3:0 + #define A2W_PLLB_ANA_KAIP_KP_SET 0x0000000f + #define A2W_PLLB_ANA_KAIP_KP_CLR 0xfffffff0 + #define A2W_PLLB_ANA_KAIP_KP_MSB 3 + #define A2W_PLLB_ANA_KAIP_KP_LSB 0 +#define A2W_PLLB_ANA_STAT HW_REGISTER_RW( 0x7e1024f0 ) + #define A2W_PLLB_ANA_STAT_MASK 0x00000fff + #define A2W_PLLB_ANA_STAT_WIDTH 12 + #define A2W_PLLB_ANA_STAT_RESET 0000000000 + #define A2W_PLLB_ANA_STAT_DATA_BITS 11:0 + #define A2W_PLLB_ANA_STAT_DATA_SET 0x00000fff + #define A2W_PLLB_ANA_STAT_DATA_CLR 0xfffff000 + #define A2W_PLLB_ANA_STAT_DATA_MSB 11 + #define A2W_PLLB_ANA_STAT_DATA_LSB 0 +#define A2W_PLLB_ANA_SCTL HW_REGISTER_RW( 0x7e1025f0 ) + #define A2W_PLLB_ANA_SCTL_MASK 0x0000001f + #define A2W_PLLB_ANA_SCTL_WIDTH 5 + #define A2W_PLLB_ANA_SCTL_RESET 0000000000 + #define A2W_PLLB_ANA_SCTL_RESET_BITS 4:4 + #define A2W_PLLB_ANA_SCTL_RESET_SET 0x00000010 + #define A2W_PLLB_ANA_SCTL_RESET_CLR 0xffffffef + #define A2W_PLLB_ANA_SCTL_RESET_MSB 4 + #define A2W_PLLB_ANA_SCTL_RESET_LSB 4 + #define A2W_PLLB_ANA_SCTL_UPDATE_BITS 3:3 + #define A2W_PLLB_ANA_SCTL_UPDATE_SET 0x00000008 + #define A2W_PLLB_ANA_SCTL_UPDATE_CLR 0xfffffff7 + #define A2W_PLLB_ANA_SCTL_UPDATE_MSB 3 + #define A2W_PLLB_ANA_SCTL_UPDATE_LSB 3 + #define A2W_PLLB_ANA_SCTL_SEL_BITS 2:0 + #define A2W_PLLB_ANA_SCTL_SEL_SET 0x00000007 + #define A2W_PLLB_ANA_SCTL_SEL_CLR 0xfffffff8 + #define A2W_PLLB_ANA_SCTL_SEL_MSB 2 + #define A2W_PLLB_ANA_SCTL_SEL_LSB 0 +#define A2W_PLLB_ANA_VCO HW_REGISTER_RW( 0x7e1026f0 ) + #define A2W_PLLB_ANA_VCO_MASK 0x00000001 + #define A2W_PLLB_ANA_VCO_WIDTH 1 + #define A2W_PLLB_ANA_VCO_RESET 0000000000 + #define A2W_PLLB_ANA_VCO_RANGE_BITS 0:0 + #define A2W_PLLB_ANA_VCO_RANGE_SET 0x00000001 + #define A2W_PLLB_ANA_VCO_RANGE_CLR 0xfffffffe + #define A2W_PLLB_ANA_VCO_RANGE_MSB 0 + #define A2W_PLLB_ANA_VCO_RANGE_LSB 0 +#define A2W_PLLC_ANA_SSCS HW_REGISTER_RW( 0x7e102130 ) + #define A2W_PLLC_ANA_SSCS_MASK 0x0001ffff + #define A2W_PLLC_ANA_SSCS_WIDTH 17 + #define A2W_PLLC_ANA_SSCS_RESET 0000000000 + #define A2W_PLLC_ANA_SSCS_MODE_BITS 16:16 + #define A2W_PLLC_ANA_SSCS_MODE_SET 0x00010000 + #define A2W_PLLC_ANA_SSCS_MODE_CLR 0xfffeffff + #define A2W_PLLC_ANA_SSCS_MODE_MSB 16 + #define A2W_PLLC_ANA_SSCS_MODE_LSB 16 + #define A2W_PLLC_ANA_SSCS_STEP_BITS 15:0 + #define A2W_PLLC_ANA_SSCS_STEP_SET 0x0000ffff + #define A2W_PLLC_ANA_SSCS_STEP_CLR 0xffff0000 + #define A2W_PLLC_ANA_SSCS_STEP_MSB 15 + #define A2W_PLLC_ANA_SSCS_STEP_LSB 0 +#define A2W_PLLC_ANA_SSCL HW_REGISTER_RW( 0x7e102230 ) + #define A2W_PLLC_ANA_SSCL_MASK 0x003fffff + #define A2W_PLLC_ANA_SSCL_WIDTH 22 + #define A2W_PLLC_ANA_SSCL_RESET 0000000000 +#define A2W_PLLC_ANA_KAIP HW_REGISTER_RW( 0x7e102330 ) + #define A2W_PLLC_ANA_KAIP_MASK 0x0000077f + #define A2W_PLLC_ANA_KAIP_WIDTH 11 + #define A2W_PLLC_ANA_KAIP_RESET 0x0000033a + #define A2W_PLLC_ANA_KAIP_KA_BITS 10:8 + #define A2W_PLLC_ANA_KAIP_KA_SET 0x00000700 + #define A2W_PLLC_ANA_KAIP_KA_CLR 0xfffff8ff + #define A2W_PLLC_ANA_KAIP_KA_MSB 10 + #define A2W_PLLC_ANA_KAIP_KA_LSB 8 + #define A2W_PLLC_ANA_KAIP_KI_BITS 6:4 + #define A2W_PLLC_ANA_KAIP_KI_SET 0x00000070 + #define A2W_PLLC_ANA_KAIP_KI_CLR 0xffffff8f + #define A2W_PLLC_ANA_KAIP_KI_MSB 6 + #define A2W_PLLC_ANA_KAIP_KI_LSB 4 + #define A2W_PLLC_ANA_KAIP_KP_BITS 3:0 + #define A2W_PLLC_ANA_KAIP_KP_SET 0x0000000f + #define A2W_PLLC_ANA_KAIP_KP_CLR 0xfffffff0 + #define A2W_PLLC_ANA_KAIP_KP_MSB 3 + #define A2W_PLLC_ANA_KAIP_KP_LSB 0 +#define A2W_PLLC_ANA_STAT HW_REGISTER_RW( 0x7e102430 ) + #define A2W_PLLC_ANA_STAT_MASK 0x00000fff + #define A2W_PLLC_ANA_STAT_WIDTH 12 + #define A2W_PLLC_ANA_STAT_RESET 0000000000 + #define A2W_PLLC_ANA_STAT_DATA_BITS 11:0 + #define A2W_PLLC_ANA_STAT_DATA_SET 0x00000fff + #define A2W_PLLC_ANA_STAT_DATA_CLR 0xfffff000 + #define A2W_PLLC_ANA_STAT_DATA_MSB 11 + #define A2W_PLLC_ANA_STAT_DATA_LSB 0 +#define A2W_PLLC_ANA_SCTL HW_REGISTER_RW( 0x7e102530 ) + #define A2W_PLLC_ANA_SCTL_MASK 0x0000001f + #define A2W_PLLC_ANA_SCTL_WIDTH 5 + #define A2W_PLLC_ANA_SCTL_RESET 0000000000 + #define A2W_PLLC_ANA_SCTL_RESET_BITS 4:4 + #define A2W_PLLC_ANA_SCTL_RESET_SET 0x00000010 + #define A2W_PLLC_ANA_SCTL_RESET_CLR 0xffffffef + #define A2W_PLLC_ANA_SCTL_RESET_MSB 4 + #define A2W_PLLC_ANA_SCTL_RESET_LSB 4 + #define A2W_PLLC_ANA_SCTL_UPDATE_BITS 3:3 + #define A2W_PLLC_ANA_SCTL_UPDATE_SET 0x00000008 + #define A2W_PLLC_ANA_SCTL_UPDATE_CLR 0xfffffff7 + #define A2W_PLLC_ANA_SCTL_UPDATE_MSB 3 + #define A2W_PLLC_ANA_SCTL_UPDATE_LSB 3 + #define A2W_PLLC_ANA_SCTL_SEL_BITS 2:0 + #define A2W_PLLC_ANA_SCTL_SEL_SET 0x00000007 + #define A2W_PLLC_ANA_SCTL_SEL_CLR 0xfffffff8 + #define A2W_PLLC_ANA_SCTL_SEL_MSB 2 + #define A2W_PLLC_ANA_SCTL_SEL_LSB 0 +#define A2W_PLLC_ANA_VCO HW_REGISTER_RW( 0x7e102630 ) + #define A2W_PLLC_ANA_VCO_MASK 0x00000001 + #define A2W_PLLC_ANA_VCO_WIDTH 1 + #define A2W_PLLC_ANA_VCO_RESET 0000000000 + #define A2W_PLLC_ANA_VCO_RANGE_BITS 0:0 + #define A2W_PLLC_ANA_VCO_RANGE_SET 0x00000001 + #define A2W_PLLC_ANA_VCO_RANGE_CLR 0xfffffffe + #define A2W_PLLC_ANA_VCO_RANGE_MSB 0 + #define A2W_PLLC_ANA_VCO_RANGE_LSB 0 +#define A2W_PLLD_ANA_SSCS HW_REGISTER_RW( 0x7e102150 ) + #define A2W_PLLD_ANA_SSCS_MASK 0x0001ffff + #define A2W_PLLD_ANA_SSCS_WIDTH 17 + #define A2W_PLLD_ANA_SSCS_RESET 0000000000 + #define A2W_PLLD_ANA_SSCS_MODE_BITS 16:16 + #define A2W_PLLD_ANA_SSCS_MODE_SET 0x00010000 + #define A2W_PLLD_ANA_SSCS_MODE_CLR 0xfffeffff + #define A2W_PLLD_ANA_SSCS_MODE_MSB 16 + #define A2W_PLLD_ANA_SSCS_MODE_LSB 16 + #define A2W_PLLD_ANA_SSCS_STEP_BITS 15:0 + #define A2W_PLLD_ANA_SSCS_STEP_SET 0x0000ffff + #define A2W_PLLD_ANA_SSCS_STEP_CLR 0xffff0000 + #define A2W_PLLD_ANA_SSCS_STEP_MSB 15 + #define A2W_PLLD_ANA_SSCS_STEP_LSB 0 +#define A2W_PLLD_ANA_SSCL HW_REGISTER_RW( 0x7e102250 ) + #define A2W_PLLD_ANA_SSCL_MASK 0x003fffff + #define A2W_PLLD_ANA_SSCL_WIDTH 22 + #define A2W_PLLD_ANA_SSCL_RESET 0000000000 +#define A2W_PLLD_ANA_KAIP HW_REGISTER_RW( 0x7e102350 ) + #define A2W_PLLD_ANA_KAIP_MASK 0x0000077f + #define A2W_PLLD_ANA_KAIP_WIDTH 11 + #define A2W_PLLD_ANA_KAIP_RESET 0x0000033a + #define A2W_PLLD_ANA_KAIP_KA_BITS 10:8 + #define A2W_PLLD_ANA_KAIP_KA_SET 0x00000700 + #define A2W_PLLD_ANA_KAIP_KA_CLR 0xfffff8ff + #define A2W_PLLD_ANA_KAIP_KA_MSB 10 + #define A2W_PLLD_ANA_KAIP_KA_LSB 8 + #define A2W_PLLD_ANA_KAIP_KI_BITS 6:4 + #define A2W_PLLD_ANA_KAIP_KI_SET 0x00000070 + #define A2W_PLLD_ANA_KAIP_KI_CLR 0xffffff8f + #define A2W_PLLD_ANA_KAIP_KI_MSB 6 + #define A2W_PLLD_ANA_KAIP_KI_LSB 4 + #define A2W_PLLD_ANA_KAIP_KP_BITS 3:0 + #define A2W_PLLD_ANA_KAIP_KP_SET 0x0000000f + #define A2W_PLLD_ANA_KAIP_KP_CLR 0xfffffff0 + #define A2W_PLLD_ANA_KAIP_KP_MSB 3 + #define A2W_PLLD_ANA_KAIP_KP_LSB 0 +#define A2W_PLLD_ANA_STAT HW_REGISTER_RW( 0x7e102450 ) + #define A2W_PLLD_ANA_STAT_MASK 0x00000fff + #define A2W_PLLD_ANA_STAT_WIDTH 12 + #define A2W_PLLD_ANA_STAT_RESET 0000000000 + #define A2W_PLLD_ANA_STAT_DATA_BITS 11:0 + #define A2W_PLLD_ANA_STAT_DATA_SET 0x00000fff + #define A2W_PLLD_ANA_STAT_DATA_CLR 0xfffff000 + #define A2W_PLLD_ANA_STAT_DATA_MSB 11 + #define A2W_PLLD_ANA_STAT_DATA_LSB 0 +#define A2W_PLLD_ANA_SCTL HW_REGISTER_RW( 0x7e102550 ) + #define A2W_PLLD_ANA_SCTL_MASK 0x0000001f + #define A2W_PLLD_ANA_SCTL_WIDTH 5 + #define A2W_PLLD_ANA_SCTL_RESET 0000000000 + #define A2W_PLLD_ANA_SCTL_RESET_BITS 4:4 + #define A2W_PLLD_ANA_SCTL_RESET_SET 0x00000010 + #define A2W_PLLD_ANA_SCTL_RESET_CLR 0xffffffef + #define A2W_PLLD_ANA_SCTL_RESET_MSB 4 + #define A2W_PLLD_ANA_SCTL_RESET_LSB 4 + #define A2W_PLLD_ANA_SCTL_UPDATE_BITS 3:3 + #define A2W_PLLD_ANA_SCTL_UPDATE_SET 0x00000008 + #define A2W_PLLD_ANA_SCTL_UPDATE_CLR 0xfffffff7 + #define A2W_PLLD_ANA_SCTL_UPDATE_MSB 3 + #define A2W_PLLD_ANA_SCTL_UPDATE_LSB 3 + #define A2W_PLLD_ANA_SCTL_SEL_BITS 2:0 + #define A2W_PLLD_ANA_SCTL_SEL_SET 0x00000007 + #define A2W_PLLD_ANA_SCTL_SEL_CLR 0xfffffff8 + #define A2W_PLLD_ANA_SCTL_SEL_MSB 2 + #define A2W_PLLD_ANA_SCTL_SEL_LSB 0 +#define A2W_PLLD_ANA_VCO HW_REGISTER_RW( 0x7e102650 ) + #define A2W_PLLD_ANA_VCO_MASK 0x00000001 + #define A2W_PLLD_ANA_VCO_WIDTH 1 + #define A2W_PLLD_ANA_VCO_RESET 0000000000 + #define A2W_PLLD_ANA_VCO_RANGE_BITS 0:0 + #define A2W_PLLD_ANA_VCO_RANGE_SET 0x00000001 + #define A2W_PLLD_ANA_VCO_RANGE_CLR 0xfffffffe + #define A2W_PLLD_ANA_VCO_RANGE_MSB 0 + #define A2W_PLLD_ANA_VCO_RANGE_LSB 0 +#define A2W_PLLH_ANA_KAIP HW_REGISTER_RW( 0x7e102370 ) + #define A2W_PLLH_ANA_KAIP_MASK 0x0000077f + #define A2W_PLLH_ANA_KAIP_WIDTH 11 + #define A2W_PLLH_ANA_KAIP_RESET 0x0000033a + #define A2W_PLLH_ANA_KAIP_KA_BITS 10:8 + #define A2W_PLLH_ANA_KAIP_KA_SET 0x00000700 + #define A2W_PLLH_ANA_KAIP_KA_CLR 0xfffff8ff + #define A2W_PLLH_ANA_KAIP_KA_MSB 10 + #define A2W_PLLH_ANA_KAIP_KA_LSB 8 + #define A2W_PLLH_ANA_KAIP_KI_BITS 6:4 + #define A2W_PLLH_ANA_KAIP_KI_SET 0x00000070 + #define A2W_PLLH_ANA_KAIP_KI_CLR 0xffffff8f + #define A2W_PLLH_ANA_KAIP_KI_MSB 6 + #define A2W_PLLH_ANA_KAIP_KI_LSB 4 + #define A2W_PLLH_ANA_KAIP_KP_BITS 3:0 + #define A2W_PLLH_ANA_KAIP_KP_SET 0x0000000f + #define A2W_PLLH_ANA_KAIP_KP_CLR 0xfffffff0 + #define A2W_PLLH_ANA_KAIP_KP_MSB 3 + #define A2W_PLLH_ANA_KAIP_KP_LSB 0 +#define A2W_PLLH_ANA_STAT HW_REGISTER_RW( 0x7e102660 ) + #define A2W_PLLH_ANA_STAT_MASK 0x001f1fff + #define A2W_PLLH_ANA_STAT_WIDTH 21 + #define A2W_PLLH_ANA_STAT_RESET 0000000000 + #define A2W_PLLH_ANA_STAT_CNTLENB_BITS 20:20 + #define A2W_PLLH_ANA_STAT_CNTLENB_SET 0x00100000 + #define A2W_PLLH_ANA_STAT_CNTLENB_CLR 0xffefffff + #define A2W_PLLH_ANA_STAT_CNTLENB_MSB 20 + #define A2W_PLLH_ANA_STAT_CNTLENB_LSB 20 + #define A2W_PLLH_ANA_STAT_RCALCODE_BITS 19:16 + #define A2W_PLLH_ANA_STAT_RCALCODE_SET 0x000f0000 + #define A2W_PLLH_ANA_STAT_RCALCODE_CLR 0xfff0ffff + #define A2W_PLLH_ANA_STAT_RCALCODE_MSB 19 + #define A2W_PLLH_ANA_STAT_RCALCODE_LSB 16 + #define A2W_PLLH_ANA_STAT_RCALDONE_BITS 12:12 + #define A2W_PLLH_ANA_STAT_RCALDONE_SET 0x00001000 + #define A2W_PLLH_ANA_STAT_RCALDONE_CLR 0xffffefff + #define A2W_PLLH_ANA_STAT_RCALDONE_MSB 12 + #define A2W_PLLH_ANA_STAT_RCALDONE_LSB 12 + #define A2W_PLLH_ANA_STAT_DATA_BITS 11:0 + #define A2W_PLLH_ANA_STAT_DATA_SET 0x00000fff + #define A2W_PLLH_ANA_STAT_DATA_CLR 0xfffff000 + #define A2W_PLLH_ANA_STAT_DATA_MSB 11 + #define A2W_PLLH_ANA_STAT_DATA_LSB 0 +#define A2W_PLLH_ANA_SCTL HW_REGISTER_RW( 0x7e102570 ) + #define A2W_PLLH_ANA_SCTL_MASK 0x0000001f + #define A2W_PLLH_ANA_SCTL_WIDTH 5 + #define A2W_PLLH_ANA_SCTL_RESET 0000000000 + #define A2W_PLLH_ANA_SCTL_RESET_BITS 4:4 + #define A2W_PLLH_ANA_SCTL_RESET_SET 0x00000010 + #define A2W_PLLH_ANA_SCTL_RESET_CLR 0xffffffef + #define A2W_PLLH_ANA_SCTL_RESET_MSB 4 + #define A2W_PLLH_ANA_SCTL_RESET_LSB 4 + #define A2W_PLLH_ANA_SCTL_UPDATE_BITS 3:3 + #define A2W_PLLH_ANA_SCTL_UPDATE_SET 0x00000008 + #define A2W_PLLH_ANA_SCTL_UPDATE_CLR 0xfffffff7 + #define A2W_PLLH_ANA_SCTL_UPDATE_MSB 3 + #define A2W_PLLH_ANA_SCTL_UPDATE_LSB 3 + #define A2W_PLLH_ANA_SCTL_SEL_BITS 2:0 + #define A2W_PLLH_ANA_SCTL_SEL_SET 0x00000007 + #define A2W_PLLH_ANA_SCTL_SEL_CLR 0xfffffff8 + #define A2W_PLLH_ANA_SCTL_SEL_MSB 2 + #define A2W_PLLH_ANA_SCTL_SEL_LSB 0 +#define A2W_PLLH_ANA_VCO HW_REGISTER_RW( 0x7e102670 ) + #define A2W_PLLH_ANA_VCO_MASK 0x00000001 + #define A2W_PLLH_ANA_VCO_WIDTH 1 + #define A2W_PLLH_ANA_VCO_RESET 0000000000 + #define A2W_PLLH_ANA_VCO_RANGE_BITS 0:0 + #define A2W_PLLH_ANA_VCO_RANGE_SET 0x00000001 + #define A2W_PLLH_ANA_VCO_RANGE_CLR 0xfffffffe + #define A2W_PLLH_ANA_VCO_RANGE_MSB 0 + #define A2W_PLLH_ANA_VCO_RANGE_LSB 0 +#define A2W_HDMI_CTL_RCAL HW_REGISTER_RW( 0x7e102180 ) + #define A2W_HDMI_CTL_RCAL_MASK 0x00011f33 + #define A2W_HDMI_CTL_RCAL_WIDTH 17 + #define A2W_HDMI_CTL_RCAL_RESET 0x00010000 + #define A2W_HDMI_CTL_RCAL_RSTB_BITS 16:16 + #define A2W_HDMI_CTL_RCAL_RSTB_SET 0x00010000 + #define A2W_HDMI_CTL_RCAL_RSTB_CLR 0xfffeffff + #define A2W_HDMI_CTL_RCAL_RSTB_MSB 16 + #define A2W_HDMI_CTL_RCAL_RSTB_LSB 16 + #define A2W_HDMI_CTL_RCAL_MANREN_BITS 12:12 + #define A2W_HDMI_CTL_RCAL_MANREN_SET 0x00001000 + #define A2W_HDMI_CTL_RCAL_MANREN_CLR 0xffffefff + #define A2W_HDMI_CTL_RCAL_MANREN_MSB 12 + #define A2W_HDMI_CTL_RCAL_MANREN_LSB 12 + #define A2W_HDMI_CTL_RCAL_MANR_BITS 11:8 + #define A2W_HDMI_CTL_RCAL_MANR_SET 0x00000f00 + #define A2W_HDMI_CTL_RCAL_MANR_CLR 0xfffff0ff + #define A2W_HDMI_CTL_RCAL_MANR_MSB 11 + #define A2W_HDMI_CTL_RCAL_MANR_LSB 8 + #define A2W_HDMI_CTL_RCAL_SELDIV_BITS 5:4 + #define A2W_HDMI_CTL_RCAL_SELDIV_SET 0x00000030 + #define A2W_HDMI_CTL_RCAL_SELDIV_CLR 0xffffffcf + #define A2W_HDMI_CTL_RCAL_SELDIV_MSB 5 + #define A2W_HDMI_CTL_RCAL_SELDIV_LSB 4 + #define A2W_HDMI_CTL_RCAL_SELAVG_BITS 1:0 + #define A2W_HDMI_CTL_RCAL_SELAVG_SET 0x00000003 + #define A2W_HDMI_CTL_RCAL_SELAVG_CLR 0xfffffffc + #define A2W_HDMI_CTL_RCAL_SELAVG_MSB 1 + #define A2W_HDMI_CTL_RCAL_SELAVG_LSB 0 +#define A2W_HDMI_CTL_HFEN HW_REGISTER_RW( 0x7e102280 ) + #define A2W_HDMI_CTL_HFEN_MASK 0x00000001 + #define A2W_HDMI_CTL_HFEN_WIDTH 1 + #define A2W_HDMI_CTL_HFEN_RESET 0000000000 + #define A2W_HDMI_CTL_HFEN_HFEN_BITS 0:0 + #define A2W_HDMI_CTL_HFEN_HFEN_SET 0x00000001 + #define A2W_HDMI_CTL_HFEN_HFEN_CLR 0xfffffffe + #define A2W_HDMI_CTL_HFEN_HFEN_MSB 0 + #define A2W_HDMI_CTL_HFEN_HFEN_LSB 0 +#define A2W_PLLA_DIG0R HW_REGISTER_RW( 0x7e102800 ) + #define A2W_PLLA_DIG0R_MASK 0x00ffffff + #define A2W_PLLA_DIG0R_WIDTH 24 + #define A2W_PLLA_DIG0R_RESET 0000000000 +#define A2W_PLLA_DIG1R HW_REGISTER_RW( 0x7e102804 ) + #define A2W_PLLA_DIG1R_MASK 0x00ffffff + #define A2W_PLLA_DIG1R_WIDTH 24 + #define A2W_PLLA_DIG1R_RESET 0x00004000 +#define A2W_PLLA_DIG2R HW_REGISTER_RW( 0x7e102808 ) + #define A2W_PLLA_DIG2R_MASK 0x00ffffff + #define A2W_PLLA_DIG2R_WIDTH 24 + #define A2W_PLLA_DIG2R_RESET 0x00100401 +#define A2W_PLLA_DIG3R HW_REGISTER_RW( 0x7e10280c ) + #define A2W_PLLA_DIG3R_MASK 0x00ffffff + #define A2W_PLLA_DIG3R_WIDTH 24 + #define A2W_PLLA_DIG3R_RESET 0x00000004 +#define A2W_PLLA_ANA0R HW_REGISTER_RW( 0x7e102810 ) + #define A2W_PLLA_ANA0R_MASK 0x00ffffff + #define A2W_PLLA_ANA0R_WIDTH 24 + #define A2W_PLLA_ANA0R_RESET 0000000000 +#define A2W_PLLA_ANA1R HW_REGISTER_RW( 0x7e102814 ) + #define A2W_PLLA_ANA1R_MASK 0x00ffffff + #define A2W_PLLA_ANA1R_WIDTH 24 + #define A2W_PLLA_ANA1R_RESET 0x001d0000 +#define A2W_PLLA_ANA2R HW_REGISTER_RW( 0x7e102818 ) + #define A2W_PLLA_ANA2R_MASK 0x00ffffff + #define A2W_PLLA_ANA2R_WIDTH 24 + #define A2W_PLLA_ANA2R_RESET 0000000000 +#define A2W_PLLA_ANA3R HW_REGISTER_RW( 0x7e10281c ) + #define A2W_PLLA_ANA3R_MASK 0x00ffffff + #define A2W_PLLA_ANA3R_WIDTH 24 + #define A2W_PLLA_ANA3R_RESET 0x00000180 +#define A2W_PLLB_DIG0R HW_REGISTER_RW( 0x7e1028e0 ) + #define A2W_PLLB_DIG0R_MASK 0x00ffffff + #define A2W_PLLB_DIG0R_WIDTH 24 + #define A2W_PLLB_DIG0R_RESET 0000000000 +#define A2W_PLLB_DIG1R HW_REGISTER_RW( 0x7e1028e4 ) + #define A2W_PLLB_DIG1R_MASK 0x00ffffff + #define A2W_PLLB_DIG1R_WIDTH 24 + #define A2W_PLLB_DIG1R_RESET 0x00004000 +#define A2W_PLLB_DIG2R HW_REGISTER_RW( 0x7e1028e8 ) + #define A2W_PLLB_DIG2R_MASK 0x00ffffff + #define A2W_PLLB_DIG2R_WIDTH 24 + #define A2W_PLLB_DIG2R_RESET 0x00100401 +#define A2W_PLLB_DIG3R HW_REGISTER_RW( 0x7e1028ec ) + #define A2W_PLLB_DIG3R_MASK 0x00ffffff + #define A2W_PLLB_DIG3R_WIDTH 24 + #define A2W_PLLB_DIG3R_RESET 0x00000004 +#define A2W_PLLB_ANA0R HW_REGISTER_RW( 0x7e1028f0 ) + #define A2W_PLLB_ANA0R_MASK 0x00ffffff + #define A2W_PLLB_ANA0R_WIDTH 24 + #define A2W_PLLB_ANA0R_RESET 0000000000 +#define A2W_PLLB_ANA1R HW_REGISTER_RW( 0x7e1028f4 ) + #define A2W_PLLB_ANA1R_MASK 0x00ffffff + #define A2W_PLLB_ANA1R_WIDTH 24 + #define A2W_PLLB_ANA1R_RESET 0x001d0000 +#define A2W_PLLB_ANA2R HW_REGISTER_RW( 0x7e1028f8 ) + #define A2W_PLLB_ANA2R_MASK 0x00ffffff + #define A2W_PLLB_ANA2R_WIDTH 24 + #define A2W_PLLB_ANA2R_RESET 0000000000 +#define A2W_PLLB_ANA3R HW_REGISTER_RW( 0x7e1028fc ) + #define A2W_PLLB_ANA3R_MASK 0x00ffffff + #define A2W_PLLB_ANA3R_WIDTH 24 + #define A2W_PLLB_ANA3R_RESET 0x00000180 +#define A2W_PLLC_DIG0R HW_REGISTER_RW( 0x7e102820 ) + #define A2W_PLLC_DIG0R_MASK 0x00ffffff + #define A2W_PLLC_DIG0R_WIDTH 24 + #define A2W_PLLC_DIG0R_RESET 0000000000 +#define A2W_PLLC_DIG1R HW_REGISTER_RW( 0x7e102824 ) + #define A2W_PLLC_DIG1R_MASK 0x00ffffff + #define A2W_PLLC_DIG1R_WIDTH 24 + #define A2W_PLLC_DIG1R_RESET 0x00004000 +#define A2W_PLLC_DIG2R HW_REGISTER_RW( 0x7e102828 ) + #define A2W_PLLC_DIG2R_MASK 0x00ffffff + #define A2W_PLLC_DIG2R_WIDTH 24 + #define A2W_PLLC_DIG2R_RESET 0x00100401 +#define A2W_PLLC_DIG3R HW_REGISTER_RW( 0x7e10282c ) + #define A2W_PLLC_DIG3R_MASK 0x00ffffff + #define A2W_PLLC_DIG3R_WIDTH 24 + #define A2W_PLLC_DIG3R_RESET 0x00000004 +#define A2W_PLLC_ANA0R HW_REGISTER_RW( 0x7e102830 ) + #define A2W_PLLC_ANA0R_MASK 0x00ffffff + #define A2W_PLLC_ANA0R_WIDTH 24 + #define A2W_PLLC_ANA0R_RESET 0000000000 +#define A2W_PLLC_ANA1R HW_REGISTER_RW( 0x7e102834 ) + #define A2W_PLLC_ANA1R_MASK 0x00ffffff + #define A2W_PLLC_ANA1R_WIDTH 24 + #define A2W_PLLC_ANA1R_RESET 0x001d0000 +#define A2W_PLLC_ANA2R HW_REGISTER_RW( 0x7e102838 ) + #define A2W_PLLC_ANA2R_MASK 0x00ffffff + #define A2W_PLLC_ANA2R_WIDTH 24 + #define A2W_PLLC_ANA2R_RESET 0000000000 +#define A2W_PLLC_ANA3R HW_REGISTER_RW( 0x7e10283c ) + #define A2W_PLLC_ANA3R_MASK 0x00ffffff + #define A2W_PLLC_ANA3R_WIDTH 24 + #define A2W_PLLC_ANA3R_RESET 0x00000180 +#define A2W_PLLD_DIG0R HW_REGISTER_RW( 0x7e102840 ) + #define A2W_PLLD_DIG0R_MASK 0x00ffffff + #define A2W_PLLD_DIG0R_WIDTH 24 + #define A2W_PLLD_DIG0R_RESET 0000000000 +#define A2W_PLLD_DIG1R HW_REGISTER_RW( 0x7e102844 ) + #define A2W_PLLD_DIG1R_MASK 0x00ffffff + #define A2W_PLLD_DIG1R_WIDTH 24 + #define A2W_PLLD_DIG1R_RESET 0x00004000 +#define A2W_PLLD_DIG2R HW_REGISTER_RW( 0x7e102848 ) + #define A2W_PLLD_DIG2R_MASK 0x00ffffff + #define A2W_PLLD_DIG2R_WIDTH 24 + #define A2W_PLLD_DIG2R_RESET 0x00100401 +#define A2W_PLLD_DIG3R HW_REGISTER_RW( 0x7e10284c ) + #define A2W_PLLD_DIG3R_MASK 0x00ffffff + #define A2W_PLLD_DIG3R_WIDTH 24 + #define A2W_PLLD_DIG3R_RESET 0x00000004 +#define A2W_PLLD_ANA0R HW_REGISTER_RW( 0x7e102850 ) + #define A2W_PLLD_ANA0R_MASK 0x00ffffff + #define A2W_PLLD_ANA0R_WIDTH 24 + #define A2W_PLLD_ANA0R_RESET 0000000000 +#define A2W_PLLD_ANA1R HW_REGISTER_RW( 0x7e102854 ) + #define A2W_PLLD_ANA1R_MASK 0x00ffffff + #define A2W_PLLD_ANA1R_WIDTH 24 + #define A2W_PLLD_ANA1R_RESET 0x001d0000 +#define A2W_PLLD_ANA2R HW_REGISTER_RW( 0x7e102858 ) + #define A2W_PLLD_ANA2R_MASK 0x00ffffff + #define A2W_PLLD_ANA2R_WIDTH 24 + #define A2W_PLLD_ANA2R_RESET 0000000000 +#define A2W_PLLD_ANA3R HW_REGISTER_RW( 0x7e10285c ) + #define A2W_PLLD_ANA3R_MASK 0x00ffffff + #define A2W_PLLD_ANA3R_WIDTH 24 + #define A2W_PLLD_ANA3R_RESET 0x00000180 +#define A2W_PLLH_DIG0R HW_REGISTER_RW( 0x7e102860 ) + #define A2W_PLLH_DIG0R_MASK 0x00ffffff + #define A2W_PLLH_DIG0R_WIDTH 24 + #define A2W_PLLH_DIG0R_RESET 0000000000 +#define A2W_PLLH_DIG1R HW_REGISTER_RW( 0x7e102864 ) + #define A2W_PLLH_DIG1R_MASK 0x00ffffff + #define A2W_PLLH_DIG1R_WIDTH 24 + #define A2W_PLLH_DIG1R_RESET 0000000000 +#define A2W_PLLH_DIG2R HW_REGISTER_RW( 0x7e102868 ) + #define A2W_PLLH_DIG2R_MASK 0x00ffffff + #define A2W_PLLH_DIG2R_WIDTH 24 + #define A2W_PLLH_DIG2R_RESET 0x000000aa +#define A2W_PLLH_DIG3R HW_REGISTER_RW( 0x7e10286c ) + #define A2W_PLLH_DIG3R_MASK 0x00ffffff + #define A2W_PLLH_DIG3R_WIDTH 24 + #define A2W_PLLH_DIG3R_RESET 0000000000 +#define A2W_PLLH_ANA0R HW_REGISTER_RW( 0x7e102870 ) + #define A2W_PLLH_ANA0R_MASK 0x00ffffff + #define A2W_PLLH_ANA0R_WIDTH 24 + #define A2W_PLLH_ANA0R_RESET 0x00d80000 +#define A2W_PLLH_ANA1R HW_REGISTER_RW( 0x7e102874 ) + #define A2W_PLLH_ANA1R_MASK 0x00ffffff + #define A2W_PLLH_ANA1R_WIDTH 24 + #define A2W_PLLH_ANA1R_RESET 0x00000014 +#define A2W_PLLH_ANA2R HW_REGISTER_RW( 0x7e102878 ) + #define A2W_PLLH_ANA2R_MASK 0x00ffffff + #define A2W_PLLH_ANA2R_WIDTH 24 + #define A2W_PLLH_ANA2R_RESET 0000000000 +#define A2W_PLLH_ANA3R HW_REGISTER_RW( 0x7e10287c ) + #define A2W_PLLH_ANA3R_MASK 0x00ffffff + #define A2W_PLLH_ANA3R_WIDTH 24 + #define A2W_PLLH_ANA3R_RESET 0000000000 +#define A2W_HDMI_CTL0R HW_REGISTER_RW( 0x7e102880 ) + #define A2W_HDMI_CTL0R_MASK 0x00ffffff + #define A2W_HDMI_CTL0R_WIDTH 24 + #define A2W_HDMI_CTL0R_RESET 0x00470238 +#define A2W_HDMI_CTL1R HW_REGISTER_RW( 0x7e102884 ) + #define A2W_HDMI_CTL1R_MASK 0x00ffffff + #define A2W_HDMI_CTL1R_WIDTH 24 + #define A2W_HDMI_CTL1R_RESET 0x00011c00 +#define A2W_HDMI_CTL2R HW_REGISTER_RW( 0x7e102888 ) + #define A2W_HDMI_CTL2R_MASK 0x00ffffff + #define A2W_HDMI_CTL2R_WIDTH 24 + #define A2W_HDMI_CTL2R_RESET 0x0018048e +#define A2W_HDMI_CTL3R HW_REGISTER_RW( 0x7e10288c ) + #define A2W_HDMI_CTL3R_MASK 0x00ffffff + #define A2W_HDMI_CTL3R_WIDTH 24 + #define A2W_HDMI_CTL3R_RESET 0x00000040 +#define A2W_XOSC0R HW_REGISTER_RW( 0x7e102890 ) + #define A2W_XOSC0R_MASK 0x00ffffff + #define A2W_XOSC0R_WIDTH 24 + #define A2W_XOSC0R_RESET 0x00820080 +#define A2W_XOSC1R HW_REGISTER_RW( 0x7e102894 ) + #define A2W_XOSC1R_MASK 0x00ffffff + #define A2W_XOSC1R_WIDTH 24 + #define A2W_XOSC1R_RESET 0x00000006 +#define A2W_SMPS_CTLA0R HW_REGISTER_RW( 0x7e1028a0 ) + #define A2W_SMPS_CTLA0R_MASK 0x00ffffff + #define A2W_SMPS_CTLA0R_WIDTH 24 + #define A2W_SMPS_CTLA0R_RESET 0000000000 +#define A2W_SMPS_CTLA1R HW_REGISTER_RW( 0x7e1028a4 ) + #define A2W_SMPS_CTLA1R_MASK 0x00ffffff + #define A2W_SMPS_CTLA1R_WIDTH 24 + #define A2W_SMPS_CTLA1R_RESET 0000000000 +#define A2W_SMPS_CTLA2R HW_REGISTER_RW( 0x7e1028a8 ) + #define A2W_SMPS_CTLA2R_MASK 0x00ffffff + #define A2W_SMPS_CTLA2R_WIDTH 24 + #define A2W_SMPS_CTLA2R_RESET 0000000000 +#define A2W_SMPS_CTLB0R HW_REGISTER_RW( 0x7e1028b0 ) + #define A2W_SMPS_CTLB0R_MASK 0x00ffffff + #define A2W_SMPS_CTLB0R_WIDTH 24 + #define A2W_SMPS_CTLB0R_RESET 0000000000 +#define A2W_SMPS_CTLB1R HW_REGISTER_RW( 0x7e1028b4 ) + #define A2W_SMPS_CTLB1R_MASK 0x00ffffff + #define A2W_SMPS_CTLB1R_WIDTH 24 + #define A2W_SMPS_CTLB1R_RESET 0000000000 +#define A2W_SMPS_CTLB2R HW_REGISTER_RW( 0x7e1028b8 ) + #define A2W_SMPS_CTLB2R_MASK 0x00ffffff + #define A2W_SMPS_CTLB2R_WIDTH 24 + #define A2W_SMPS_CTLB2R_RESET 0000000000 +#define A2W_SMPS_CTLC0R HW_REGISTER_RW( 0x7e1028c0 ) + #define A2W_SMPS_CTLC0R_MASK 0x00ffffff + #define A2W_SMPS_CTLC0R_WIDTH 24 + #define A2W_SMPS_CTLC0R_RESET 0000000000 +#define A2W_SMPS_CTLC1R HW_REGISTER_RW( 0x7e1028c4 ) + #define A2W_SMPS_CTLC1R_MASK 0x00ffffff + #define A2W_SMPS_CTLC1R_WIDTH 24 + #define A2W_SMPS_CTLC1R_RESET 0000000000 +#define A2W_SMPS_CTLC2R HW_REGISTER_RW( 0x7e1028c8 ) + #define A2W_SMPS_CTLC2R_MASK 0x00ffffff + #define A2W_SMPS_CTLC2R_WIDTH 24 + #define A2W_SMPS_CTLC2R_RESET 0000000000 +#define A2W_SMPS_CTLC3R HW_REGISTER_RW( 0x7e1028cc ) + #define A2W_SMPS_CTLC3R_MASK 0x00ffffff + #define A2W_SMPS_CTLC3R_WIDTH 24 + #define A2W_SMPS_CTLC3R_RESET 0000000000 +#define A2W_SMPS_LDO0R HW_REGISTER_RW( 0x7e1028d0 ) + #define A2W_SMPS_LDO0R_MASK 0x00ffffff + #define A2W_SMPS_LDO0R_WIDTH 24 + #define A2W_SMPS_LDO0R_RESET 0000000000 +#define A2W_SMPS_LDO1R HW_REGISTER_RW( 0x7e1028d4 ) + #define A2W_SMPS_LDO1R_MASK 0x00ffffff + #define A2W_SMPS_LDO1R_WIDTH 24 + #define A2W_SMPS_LDO1R_RESET 0000000000 +#define A2W_PLLA_CTRLR HW_REGISTER_RW( 0x7e102900 ) + #define A2W_PLLA_CTRLR_MASK 0x000373ff + #define A2W_PLLA_CTRLR_WIDTH 18 + #define A2W_PLLA_CTRLR_RESET 0x00010000 +#define A2W_PLLA_FRACR HW_REGISTER_RW( 0x7e102a00 ) + #define A2W_PLLA_FRACR_MASK 0x000fffff + #define A2W_PLLA_FRACR_WIDTH 20 + #define A2W_PLLA_FRACR_RESET 0000000000 +#define A2W_PLLA_DSI0R HW_REGISTER_RW( 0x7e102b00 ) + #define A2W_PLLA_DSI0R_MASK 0x000003ff + #define A2W_PLLA_DSI0R_WIDTH 10 + #define A2W_PLLA_DSI0R_RESET 0x00000100 +#define A2W_PLLA_CORER HW_REGISTER_RW( 0x7e102c00 ) + #define A2W_PLLA_CORER_MASK 0x000003ff + #define A2W_PLLA_CORER_WIDTH 10 + #define A2W_PLLA_CORER_RESET 0x00000100 +#define A2W_PLLA_PERR HW_REGISTER_RW( 0x7e102d00 ) + #define A2W_PLLA_PERR_MASK 0x000003ff + #define A2W_PLLA_PERR_WIDTH 10 + #define A2W_PLLA_PERR_RESET 0x00000100 +#define A2W_PLLA_CCP2R HW_REGISTER_RW( 0x7e102e00 ) + #define A2W_PLLA_CCP2R_MASK 0x000003ff + #define A2W_PLLA_CCP2R_WIDTH 10 + #define A2W_PLLA_CCP2R_RESET 0x00000100 +#define A2W_PLLA_MULTI HW_REGISTER_RW( 0x7e102f00 ) + #define A2W_PLLA_MULTI_MASK 0000000000 + #define A2W_PLLA_MULTI_WIDTH 0 + #define A2W_PLLA_MULTI_RESET 0000000000 +#define A2W_PLLB_CTRLR HW_REGISTER_RW( 0x7e1029e0 ) + #define A2W_PLLB_CTRLR_MASK 0x000373ff + #define A2W_PLLB_CTRLR_WIDTH 18 + #define A2W_PLLB_CTRLR_RESET 0x00010000 +#define A2W_PLLB_FRACR HW_REGISTER_RW( 0x7e102ae0 ) + #define A2W_PLLB_FRACR_MASK 0x000fffff + #define A2W_PLLB_FRACR_WIDTH 20 + #define A2W_PLLB_FRACR_RESET 0000000000 +#define A2W_PLLB_ARMR HW_REGISTER_RW( 0x7e102be0 ) + #define A2W_PLLB_ARMR_MASK 0x000003ff + #define A2W_PLLB_ARMR_WIDTH 10 + #define A2W_PLLB_ARMR_RESET 0x00000100 +#define A2W_PLLB_SP0R HW_REGISTER_RW( 0x7e102ce0 ) + #define A2W_PLLB_SP0R_MASK 0x000003ff + #define A2W_PLLB_SP0R_WIDTH 10 + #define A2W_PLLB_SP0R_RESET 0x00000100 +#define A2W_PLLB_SP1R HW_REGISTER_RW( 0x7e102de0 ) + #define A2W_PLLB_SP1R_MASK 0x000003ff + #define A2W_PLLB_SP1R_WIDTH 10 + #define A2W_PLLB_SP1R_RESET 0x00000100 +#define A2W_PLLB_SP2R HW_REGISTER_RW( 0x7e102ee0 ) + #define A2W_PLLB_SP2R_MASK 0x000003ff + #define A2W_PLLB_SP2R_WIDTH 10 + #define A2W_PLLB_SP2R_RESET 0x00000100 +#define A2W_PLLB_MULTI HW_REGISTER_RW( 0x7e102fe0 ) + #define A2W_PLLB_MULTI_MASK 0000000000 + #define A2W_PLLB_MULTI_WIDTH 0 + #define A2W_PLLB_MULTI_RESET 0000000000 +#define A2W_PLLC_CTRLR HW_REGISTER_RW( 0x7e102920 ) + #define A2W_PLLC_CTRLR_MASK 0x000373ff + #define A2W_PLLC_CTRLR_WIDTH 18 + #define A2W_PLLC_CTRLR_RESET 0x00010000 +#define A2W_PLLC_FRACR HW_REGISTER_RW( 0x7e102a20 ) + #define A2W_PLLC_FRACR_MASK 0x000fffff + #define A2W_PLLC_FRACR_WIDTH 20 + #define A2W_PLLC_FRACR_RESET 0000000000 +#define A2W_PLLC_CORE2R HW_REGISTER_RW( 0x7e102b20 ) + #define A2W_PLLC_CORE2R_MASK 0x000003ff + #define A2W_PLLC_CORE2R_WIDTH 10 + #define A2W_PLLC_CORE2R_RESET 0x00000100 +#define A2W_PLLC_CORE1R HW_REGISTER_RW( 0x7e102c20 ) + #define A2W_PLLC_CORE1R_MASK 0x000003ff + #define A2W_PLLC_CORE1R_WIDTH 10 + #define A2W_PLLC_CORE1R_RESET 0x00000100 +#define A2W_PLLC_PERR HW_REGISTER_RW( 0x7e102d20 ) + #define A2W_PLLC_PERR_MASK 0x000003ff + #define A2W_PLLC_PERR_WIDTH 10 + #define A2W_PLLC_PERR_RESET 0x00000100 +#define A2W_PLLC_CORE0R HW_REGISTER_RW( 0x7e102e20 ) + #define A2W_PLLC_CORE0R_MASK 0x000003ff + #define A2W_PLLC_CORE0R_WIDTH 10 + #define A2W_PLLC_CORE0R_RESET 0x00000100 +#define A2W_PLLC_MULTI HW_REGISTER_RW( 0x7e102f20 ) + #define A2W_PLLC_MULTI_MASK 0000000000 + #define A2W_PLLC_MULTI_WIDTH 0 + #define A2W_PLLC_MULTI_RESET 0000000000 +#define A2W_PLLD_CTRLR HW_REGISTER_RW( 0x7e102940 ) + #define A2W_PLLD_CTRLR_MASK 0x000373ff + #define A2W_PLLD_CTRLR_WIDTH 18 + #define A2W_PLLD_CTRLR_RESET 0x00010000 +#define A2W_PLLD_FRACR HW_REGISTER_RW( 0x7e102a40 ) + #define A2W_PLLD_FRACR_MASK 0x000fffff + #define A2W_PLLD_FRACR_WIDTH 20 + #define A2W_PLLD_FRACR_RESET 0000000000 +#define A2W_PLLD_DSI0R HW_REGISTER_RW( 0x7e102b40 ) + #define A2W_PLLD_DSI0R_MASK 0x000003ff + #define A2W_PLLD_DSI0R_WIDTH 10 + #define A2W_PLLD_DSI0R_RESET 0x00000100 +#define A2W_PLLD_CORER HW_REGISTER_RW( 0x7e102c40 ) + #define A2W_PLLD_CORER_MASK 0x000003ff + #define A2W_PLLD_CORER_WIDTH 10 + #define A2W_PLLD_CORER_RESET 0x00000100 +#define A2W_PLLD_PERR HW_REGISTER_RW( 0x7e102d40 ) + #define A2W_PLLD_PERR_MASK 0x000003ff + #define A2W_PLLD_PERR_WIDTH 10 + #define A2W_PLLD_PERR_RESET 0x00000100 +#define A2W_PLLD_DSI1R HW_REGISTER_RW( 0x7e102e40 ) + #define A2W_PLLD_DSI1R_MASK 0x000003ff + #define A2W_PLLD_DSI1R_WIDTH 10 + #define A2W_PLLD_DSI1R_RESET 0x00000100 +#define A2W_PLLD_MULTI HW_REGISTER_RW( 0x7e102f40 ) + #define A2W_PLLD_MULTI_MASK 0000000000 + #define A2W_PLLD_MULTI_WIDTH 0 + #define A2W_PLLD_MULTI_RESET 0000000000 +#define A2W_PLLH_CTRLR HW_REGISTER_RW( 0x7e102960 ) + #define A2W_PLLH_CTRLR_MASK 0x000370ff + #define A2W_PLLH_CTRLR_WIDTH 18 + #define A2W_PLLH_CTRLR_RESET 0x00010000 +#define A2W_PLLH_FRACR HW_REGISTER_RW( 0x7e102a60 ) + #define A2W_PLLH_FRACR_MASK 0x000fffff + #define A2W_PLLH_FRACR_WIDTH 20 + #define A2W_PLLH_FRACR_RESET 0000000000 +#define A2W_PLLH_AUXR HW_REGISTER_RW( 0x7e102b60 ) + #define A2W_PLLH_AUXR_MASK 0x000003ff + #define A2W_PLLH_AUXR_WIDTH 10 + #define A2W_PLLH_AUXR_RESET 0x00000100 +#define A2W_PLLH_RCALR HW_REGISTER_RW( 0x7e102c60 ) + #define A2W_PLLH_RCALR_MASK 0x000003ff + #define A2W_PLLH_RCALR_WIDTH 10 + #define A2W_PLLH_RCALR_RESET 0x00000100 +#define A2W_PLLH_PIXR HW_REGISTER_RW( 0x7e102d60 ) + #define A2W_PLLH_PIXR_MASK 0x000003ff + #define A2W_PLLH_PIXR_WIDTH 10 + #define A2W_PLLH_PIXR_RESET 0x00000100 +#define A2W_PLLH_MULTI HW_REGISTER_RW( 0x7e102f60 ) + #define A2W_PLLH_MULTI_MASK 0000000000 + #define A2W_PLLH_MULTI_WIDTH 0 + #define A2W_PLLH_MULTI_RESET 0000000000 +#define A2W_SMPS_A_MODER HW_REGISTER_RW( 0x7e1029a0 ) + #define A2W_SMPS_A_MODER_MASK 0x00000001 + #define A2W_SMPS_A_MODER_WIDTH 1 + #define A2W_SMPS_A_MODER_RESET 0000000000 +#define A2W_SMPS_A_VOLTSR HW_REGISTER_RW( 0x7e102aa0 ) + #define A2W_SMPS_A_VOLTSR_MASK 0x0000001f + #define A2W_SMPS_A_VOLTSR_WIDTH 5 + #define A2W_SMPS_A_VOLTSR_RESET 0000000000 +#define A2W_SMPS_A_GAINR HW_REGISTER_RW( 0x7e102ba0 ) + #define A2W_SMPS_A_GAINR_MASK 0x00000007 + #define A2W_SMPS_A_GAINR_WIDTH 3 + #define A2W_SMPS_A_GAINR_RESET 0000000000 +#define A2W_SMPS_A_MULTI HW_REGISTER_RW( 0x7e102fa0 ) + #define A2W_SMPS_A_MULTI_MASK 0000000000 + #define A2W_SMPS_A_MULTI_WIDTH 0 + #define A2W_SMPS_A_MULTI_RESET 0000000000 +#define A2W_SMPS_B_STATR HW_REGISTER_RW( 0x7e1029b0 ) + #define A2W_SMPS_B_STATR_MASK 0x0000111f + #define A2W_SMPS_B_STATR_WIDTH 13 + #define A2W_SMPS_B_STATR_RESET 0000000000 +#define A2W_SMPS_B_MULTI HW_REGISTER_RW( 0x7e102fb0 ) + #define A2W_SMPS_B_MULTI_MASK 0000000000 + #define A2W_SMPS_B_MULTI_WIDTH 0 + #define A2W_SMPS_B_MULTI_RESET 0000000000 +#define A2W_SMPS_C_CLKR HW_REGISTER_RW( 0x7e1029c0 ) + #define A2W_SMPS_C_CLKR_MASK 0x0000000f + #define A2W_SMPS_C_CLKR_WIDTH 4 + #define A2W_SMPS_C_CLKR_RESET 0000000000 +#define A2W_SMPS_C_CTLR HW_REGISTER_RW( 0x7e102ac0 ) + #define A2W_SMPS_C_CTLR_MASK 0x00000003 + #define A2W_SMPS_C_CTLR_WIDTH 2 + #define A2W_SMPS_C_CTLR_RESET 0000000000 +#define A2W_SMPS_C_MULTI HW_REGISTER_RW( 0x7e102fc0 ) + #define A2W_SMPS_C_MULTI_MASK 0000000000 + #define A2W_SMPS_C_MULTI_WIDTH 0 + #define A2W_SMPS_C_MULTI_RESET 0000000000 +#define A2W_SMPS_L_SPVR HW_REGISTER_RW( 0x7e1029d0 ) + #define A2W_SMPS_L_SPVR_MASK 0x0000001f + #define A2W_SMPS_L_SPVR_WIDTH 5 + #define A2W_SMPS_L_SPVR_RESET 0000000000 +#define A2W_SMPS_L_SPAR HW_REGISTER_RW( 0x7e102ad0 ) + #define A2W_SMPS_L_SPAR_MASK 0x000003ff + #define A2W_SMPS_L_SPAR_WIDTH 10 + #define A2W_SMPS_L_SPAR_RESET 0000000000 +#define A2W_SMPS_L_SCVR HW_REGISTER_RW( 0x7e102bd0 ) + #define A2W_SMPS_L_SCVR_MASK 0x0000001f + #define A2W_SMPS_L_SCVR_WIDTH 5 + #define A2W_SMPS_L_SCVR_RESET 0000000000 +#define A2W_SMPS_L_SCAR HW_REGISTER_RW( 0x7e102cd0 ) + #define A2W_SMPS_L_SCAR_MASK 0x00000fff + #define A2W_SMPS_L_SCAR_WIDTH 12 + #define A2W_SMPS_L_SCAR_RESET 0000000000 +#define A2W_SMPS_L_SIVR HW_REGISTER_RW( 0x7e102dd0 ) + #define A2W_SMPS_L_SIVR_MASK 0x0000001f + #define A2W_SMPS_L_SIVR_WIDTH 5 + #define A2W_SMPS_L_SIVR_RESET 0000000000 +#define A2W_SMPS_L_SIAR HW_REGISTER_RW( 0x7e102ed0 ) + #define A2W_SMPS_L_SIAR_MASK 0x000003ff + #define A2W_SMPS_L_SIAR_WIDTH 10 + #define A2W_SMPS_L_SIAR_RESET 0000000000 +#define A2W_SMPS_L_MULTI HW_REGISTER_RW( 0x7e102fd0 ) + #define A2W_SMPS_L_MULTI_MASK 0000000000 + #define A2W_SMPS_L_MULTI_WIDTH 0 + #define A2W_SMPS_L_MULTI_RESET 0000000000 +#define A2W_XOSC_CTRLR HW_REGISTER_RW( 0x7e102990 ) + #define A2W_XOSC_CTRLR_MASK 0x000000ff + #define A2W_XOSC_CTRLR_WIDTH 8 + #define A2W_XOSC_CTRLR_RESET 0000000000 +#define A2W_XOSC_CPRR HW_REGISTER_RW( 0x7e102a90 ) + #define A2W_XOSC_CPRR_MASK 0x00000013 + #define A2W_XOSC_CPRR_WIDTH 5 + #define A2W_XOSC_CPRR_RESET 0000000000 +#define A2W_XOSC_BIASR HW_REGISTER_RW( 0x7e102b90 ) + #define A2W_XOSC_BIASR_MASK 0x0000001f + #define A2W_XOSC_BIASR_WIDTH 5 + #define A2W_XOSC_BIASR_RESET 0x00000018 +#define A2W_XOSC_PWRR HW_REGISTER_RW( 0x7e102c90 ) + #define A2W_XOSC_PWRR_MASK 0x00000007 + #define A2W_XOSC_PWRR_WIDTH 3 + #define A2W_XOSC_PWRR_RESET 0x00000004 +#define A2W_XOSC_MULTI HW_REGISTER_RW( 0x7e102f90 ) + #define A2W_XOSC_MULTI_MASK 0000000000 + #define A2W_XOSC_MULTI_WIDTH 0 + #define A2W_XOSC_MULTI_RESET 0000000000 +#define A2W_PLLA_ANA_SSCSR HW_REGISTER_RW( 0x7e102910 ) + #define A2W_PLLA_ANA_SSCSR_MASK 0x0001ffff + #define A2W_PLLA_ANA_SSCSR_WIDTH 17 + #define A2W_PLLA_ANA_SSCSR_RESET 0000000000 +#define A2W_PLLA_ANA_SSCLR HW_REGISTER_RW( 0x7e102a10 ) + #define A2W_PLLA_ANA_SSCLR_MASK 0x0001ffff + #define A2W_PLLA_ANA_SSCLR_WIDTH 17 + #define A2W_PLLA_ANA_SSCLR_RESET 0000000000 +#define A2W_PLLA_ANA_KAIPR HW_REGISTER_RW( 0x7e102b10 ) + #define A2W_PLLA_ANA_KAIPR_MASK 0x0000077f + #define A2W_PLLA_ANA_KAIPR_WIDTH 11 + #define A2W_PLLA_ANA_KAIPR_RESET 0x0000033a +#define A2W_PLLA_ANA_STATR HW_REGISTER_RW( 0x7e102c10 ) + #define A2W_PLLA_ANA_STATR_MASK 0x00000fff + #define A2W_PLLA_ANA_STATR_WIDTH 12 + #define A2W_PLLA_ANA_STATR_RESET 0000000000 +#define A2W_PLLA_ANA_SCTLR HW_REGISTER_RW( 0x7e102d10 ) + #define A2W_PLLA_ANA_SCTLR_MASK 0x0000001f + #define A2W_PLLA_ANA_SCTLR_WIDTH 5 + #define A2W_PLLA_ANA_SCTLR_RESET 0000000000 +#define A2W_PLLA_ANA_VCOR HW_REGISTER_RW( 0x7e102e10 ) + #define A2W_PLLA_ANA_VCOR_MASK 0x00000001 + #define A2W_PLLA_ANA_VCOR_WIDTH 1 + #define A2W_PLLA_ANA_VCOR_RESET 0000000000 +#define A2W_PLLA_ANA_MULTI HW_REGISTER_RW( 0x7e102f10 ) + #define A2W_PLLA_ANA_MULTI_MASK 0000000000 + #define A2W_PLLA_ANA_MULTI_WIDTH 0 + #define A2W_PLLA_ANA_MULTI_RESET 0000000000 +#define A2W_PLLB_ANA_SSCSR HW_REGISTER_RW( 0x7e1029f0 ) + #define A2W_PLLB_ANA_SSCSR_MASK 0x0001ffff + #define A2W_PLLB_ANA_SSCSR_WIDTH 17 + #define A2W_PLLB_ANA_SSCSR_RESET 0000000000 +#define A2W_PLLB_ANA_SSCLR HW_REGISTER_RW( 0x7e102af0 ) + #define A2W_PLLB_ANA_SSCLR_MASK 0x0001ffff + #define A2W_PLLB_ANA_SSCLR_WIDTH 17 + #define A2W_PLLB_ANA_SSCLR_RESET 0000000000 +#define A2W_PLLB_ANA_KAIPR HW_REGISTER_RW( 0x7e102bf0 ) + #define A2W_PLLB_ANA_KAIPR_MASK 0x0000077f + #define A2W_PLLB_ANA_KAIPR_WIDTH 11 + #define A2W_PLLB_ANA_KAIPR_RESET 0x0000033a +#define A2W_PLLB_ANA_STATR HW_REGISTER_RW( 0x7e102cf0 ) + #define A2W_PLLB_ANA_STATR_MASK 0x00000fff + #define A2W_PLLB_ANA_STATR_WIDTH 12 + #define A2W_PLLB_ANA_STATR_RESET 0000000000 +#define A2W_PLLB_ANA_SCTLR HW_REGISTER_RW( 0x7e102df0 ) + #define A2W_PLLB_ANA_SCTLR_MASK 0x0000001f + #define A2W_PLLB_ANA_SCTLR_WIDTH 5 + #define A2W_PLLB_ANA_SCTLR_RESET 0000000000 +#define A2W_PLLB_ANA_VCOR HW_REGISTER_RW( 0x7e102ef0 ) + #define A2W_PLLB_ANA_VCOR_MASK 0x00000001 + #define A2W_PLLB_ANA_VCOR_WIDTH 1 + #define A2W_PLLB_ANA_VCOR_RESET 0000000000 +#define A2W_PLLB_ANA_MULTI HW_REGISTER_RW( 0x7e102ff0 ) + #define A2W_PLLB_ANA_MULTI_MASK 0000000000 + #define A2W_PLLB_ANA_MULTI_WIDTH 0 + #define A2W_PLLB_ANA_MULTI_RESET 0000000000 +#define A2W_PLLC_ANA_SSCSR HW_REGISTER_RW( 0x7e102930 ) + #define A2W_PLLC_ANA_SSCSR_MASK 0x0001ffff + #define A2W_PLLC_ANA_SSCSR_WIDTH 17 + #define A2W_PLLC_ANA_SSCSR_RESET 0000000000 +#define A2W_PLLC_ANA_SSCLR HW_REGISTER_RW( 0x7e102a30 ) + #define A2W_PLLC_ANA_SSCLR_MASK 0x0001ffff + #define A2W_PLLC_ANA_SSCLR_WIDTH 17 + #define A2W_PLLC_ANA_SSCLR_RESET 0000000000 +#define A2W_PLLC_ANA_KAIPR HW_REGISTER_RW( 0x7e102b30 ) + #define A2W_PLLC_ANA_KAIPR_MASK 0x0000077f + #define A2W_PLLC_ANA_KAIPR_WIDTH 11 + #define A2W_PLLC_ANA_KAIPR_RESET 0x0000033a +#define A2W_PLLC_ANA_STATR HW_REGISTER_RW( 0x7e102c30 ) + #define A2W_PLLC_ANA_STATR_MASK 0x00000fff + #define A2W_PLLC_ANA_STATR_WIDTH 12 + #define A2W_PLLC_ANA_STATR_RESET 0000000000 +#define A2W_PLLC_ANA_SCTLR HW_REGISTER_RW( 0x7e102d30 ) + #define A2W_PLLC_ANA_SCTLR_MASK 0x0000001f + #define A2W_PLLC_ANA_SCTLR_WIDTH 5 + #define A2W_PLLC_ANA_SCTLR_RESET 0000000000 +#define A2W_PLLC_ANA_VCOR HW_REGISTER_RW( 0x7e102e30 ) + #define A2W_PLLC_ANA_VCOR_MASK 0x00000001 + #define A2W_PLLC_ANA_VCOR_WIDTH 1 + #define A2W_PLLC_ANA_VCOR_RESET 0000000000 +#define A2W_PLLC_ANA_MULTI HW_REGISTER_RW( 0x7e102f30 ) + #define A2W_PLLC_ANA_MULTI_MASK 0000000000 + #define A2W_PLLC_ANA_MULTI_WIDTH 0 + #define A2W_PLLC_ANA_MULTI_RESET 0000000000 +#define A2W_PLLD_ANA_SSCSR HW_REGISTER_RW( 0x7e102950 ) + #define A2W_PLLD_ANA_SSCSR_MASK 0x0001ffff + #define A2W_PLLD_ANA_SSCSR_WIDTH 17 + #define A2W_PLLD_ANA_SSCSR_RESET 0000000000 +#define A2W_PLLD_ANA_SSCLR HW_REGISTER_RW( 0x7e102a50 ) + #define A2W_PLLD_ANA_SSCLR_MASK 0x0001ffff + #define A2W_PLLD_ANA_SSCLR_WIDTH 17 + #define A2W_PLLD_ANA_SSCLR_RESET 0000000000 +#define A2W_PLLD_ANA_KAIPR HW_REGISTER_RW( 0x7e102b50 ) + #define A2W_PLLD_ANA_KAIPR_MASK 0x0000077f + #define A2W_PLLD_ANA_KAIPR_WIDTH 11 + #define A2W_PLLD_ANA_KAIPR_RESET 0x0000033a +#define A2W_PLLD_ANA_STATR HW_REGISTER_RW( 0x7e102c50 ) + #define A2W_PLLD_ANA_STATR_MASK 0x00000fff + #define A2W_PLLD_ANA_STATR_WIDTH 12 + #define A2W_PLLD_ANA_STATR_RESET 0000000000 +#define A2W_PLLD_ANA_SCTLR HW_REGISTER_RW( 0x7e102d50 ) + #define A2W_PLLD_ANA_SCTLR_MASK 0x0000001f + #define A2W_PLLD_ANA_SCTLR_WIDTH 5 + #define A2W_PLLD_ANA_SCTLR_RESET 0000000000 +#define A2W_PLLD_ANA_VCOR HW_REGISTER_RW( 0x7e102e50 ) + #define A2W_PLLD_ANA_VCOR_MASK 0x00000001 + #define A2W_PLLD_ANA_VCOR_WIDTH 1 + #define A2W_PLLD_ANA_VCOR_RESET 0000000000 +#define A2W_PLLD_ANA_MULTI HW_REGISTER_RW( 0x7e102f50 ) + #define A2W_PLLD_ANA_MULTI_MASK 0000000000 + #define A2W_PLLD_ANA_MULTI_WIDTH 0 + #define A2W_PLLD_ANA_MULTI_RESET 0000000000 +#define A2W_PLLH_ANA_KAIPR HW_REGISTER_RW( 0x7e102b70 ) + #define A2W_PLLH_ANA_KAIPR_MASK 0x0000077f + #define A2W_PLLH_ANA_KAIPR_WIDTH 11 + #define A2W_PLLH_ANA_KAIPR_RESET 0x0000033a +#define A2W_PLLH_ANA_STATR HW_REGISTER_RW( 0x7e102e60 ) + #define A2W_PLLH_ANA_STATR_MASK 0x001f1fff + #define A2W_PLLH_ANA_STATR_WIDTH 21 + #define A2W_PLLH_ANA_STATR_RESET 0000000000 +#define A2W_PLLH_ANA_SCTLR HW_REGISTER_RW( 0x7e102d70 ) + #define A2W_PLLH_ANA_SCTLR_MASK 0x0000001f + #define A2W_PLLH_ANA_SCTLR_WIDTH 5 + #define A2W_PLLH_ANA_SCTLR_RESET 0000000000 +#define A2W_PLLH_ANA_VCOR HW_REGISTER_RW( 0x7e102e70 ) + #define A2W_PLLH_ANA_VCOR_MASK 0x00000001 + #define A2W_PLLH_ANA_VCOR_WIDTH 1 + #define A2W_PLLH_ANA_VCOR_RESET 0000000000 +#define A2W_PLLH_ANA_MULTI HW_REGISTER_RW( 0x7e102f70 ) + #define A2W_PLLH_ANA_MULTI_MASK 0000000000 + #define A2W_PLLH_ANA_MULTI_WIDTH 0 + #define A2W_PLLH_ANA_MULTI_RESET 0000000000 +#define A2W_HDMI_CTL_RCALR HW_REGISTER_RW( 0x7e102980 ) + #define A2W_HDMI_CTL_RCALR_MASK 0x00011f33 + #define A2W_HDMI_CTL_RCALR_WIDTH 17 + #define A2W_HDMI_CTL_RCALR_RESET 0x00010000 +#define A2W_HDMI_CTL_HFENR HW_REGISTER_RW( 0x7e102a80 ) + #define A2W_HDMI_CTL_HFENR_MASK 0x00000001 + #define A2W_HDMI_CTL_HFENR_WIDTH 1 + #define A2W_HDMI_CTL_HFENR_RESET 0000000000 +#define A2W_HDMI_CTL_MULTI HW_REGISTER_RW( 0x7e102f80 ) + #define A2W_HDMI_CTL_MULTI_MASK 0000000000 + #define A2W_HDMI_CTL_MULTI_WIDTH 0 + #define A2W_HDMI_CTL_MULTI_RESET 0000000000 diff --git a/bcm2708_chip/cpr_apb2wtap_a0.h b/bcm2708_chip/cpr_apb2wtap_a0.h new file mode 100755 index 0000000..9d53b00 --- /dev/null +++ b/bcm2708_chip/cpr_apb2wtap_a0.h @@ -0,0 +1,985 @@ +// This file was generated by the create_regs script +#define A2W_PASSWORD 0x5a000000 +#define A2W_BASE 0x7e102000 +#define A2W_APB_ID 0x00613277 +#define A2W_PLLA_DIG0 HW_REGISTER_RW( 0x7e102000 ) + #define A2W_PLLA_DIG0_MASK 0x00ffffff + #define A2W_PLLA_DIG0_WIDTH 24 + #define A2W_PLLA_DIG0_RESET 0000000000 +#define A2W_PLLA_DIG1 HW_REGISTER_RW( 0x7e102004 ) + #define A2W_PLLA_DIG1_MASK 0x00ffffff + #define A2W_PLLA_DIG1_WIDTH 24 + #define A2W_PLLA_DIG1_RESET 0000000000 +#define A2W_PLLA_DIG2 HW_REGISTER_RW( 0x7e102008 ) + #define A2W_PLLA_DIG2_MASK 0x00ffffff + #define A2W_PLLA_DIG2_WIDTH 24 + #define A2W_PLLA_DIG2_RESET 0000000000 +#define A2W_PLLA_DIG3 HW_REGISTER_RW( 0x7e10200c ) + #define A2W_PLLA_DIG3_MASK 0x00ffffff + #define A2W_PLLA_DIG3_WIDTH 24 + #define A2W_PLLA_DIG3_RESET 0000000000 +#define A2W_PLLA_ANA0 HW_REGISTER_RW( 0x7e102010 ) + #define A2W_PLLA_ANA0_MASK 0x00ffffff + #define A2W_PLLA_ANA0_WIDTH 24 + #define A2W_PLLA_ANA0_RESET 0000000000 +#define A2W_PLLA_ANA1 HW_REGISTER_RW( 0x7e102014 ) + #define A2W_PLLA_ANA1_MASK 0x00ffffff + #define A2W_PLLA_ANA1_WIDTH 24 + #define A2W_PLLA_ANA1_RESET 0000000000 +#define A2W_PLLA_ANA2 HW_REGISTER_RW( 0x7e102018 ) + #define A2W_PLLA_ANA2_MASK 0x00ffffff + #define A2W_PLLA_ANA2_WIDTH 24 + #define A2W_PLLA_ANA2_RESET 0000000000 +#define A2W_PLLA_ANA3 HW_REGISTER_RW( 0x7e10201c ) + #define A2W_PLLA_ANA3_MASK 0x00ffffff + #define A2W_PLLA_ANA3_WIDTH 24 + #define A2W_PLLA_ANA3_RESET 0000000000 +#define A2W_PLLC_DIG0 HW_REGISTER_RW( 0x7e102020 ) + #define A2W_PLLC_DIG0_MASK 0x00ffffff + #define A2W_PLLC_DIG0_WIDTH 24 + #define A2W_PLLC_DIG0_RESET 0000000000 +#define A2W_PLLC_DIG1 HW_REGISTER_RW( 0x7e102024 ) + #define A2W_PLLC_DIG1_MASK 0x00ffffff + #define A2W_PLLC_DIG1_WIDTH 24 + #define A2W_PLLC_DIG1_RESET 0000000000 +#define A2W_PLLC_DIG2 HW_REGISTER_RW( 0x7e102028 ) + #define A2W_PLLC_DIG2_MASK 0x00ffffff + #define A2W_PLLC_DIG2_WIDTH 24 + #define A2W_PLLC_DIG2_RESET 0000000000 +#define A2W_PLLC_DIG3 HW_REGISTER_RW( 0x7e10202c ) + #define A2W_PLLC_DIG3_MASK 0x00ffffff + #define A2W_PLLC_DIG3_WIDTH 24 + #define A2W_PLLC_DIG3_RESET 0000000000 +#define A2W_PLLC_ANA0 HW_REGISTER_RW( 0x7e102030 ) + #define A2W_PLLC_ANA0_MASK 0x00ffffff + #define A2W_PLLC_ANA0_WIDTH 24 + #define A2W_PLLC_ANA0_RESET 0000000000 +#define A2W_PLLC_ANA1 HW_REGISTER_RW( 0x7e102034 ) + #define A2W_PLLC_ANA1_MASK 0x00ffffff + #define A2W_PLLC_ANA1_WIDTH 24 + #define A2W_PLLC_ANA1_RESET 0000000000 +#define A2W_PLLC_ANA2 HW_REGISTER_RW( 0x7e102038 ) + #define A2W_PLLC_ANA2_MASK 0x00ffffff + #define A2W_PLLC_ANA2_WIDTH 24 + #define A2W_PLLC_ANA2_RESET 0000000000 +#define A2W_PLLC_ANA3 HW_REGISTER_RW( 0x7e10203c ) + #define A2W_PLLC_ANA3_MASK 0x00ffffff + #define A2W_PLLC_ANA3_WIDTH 24 + #define A2W_PLLC_ANA3_RESET 0000000000 +#define A2W_PLLD_DIG0 HW_REGISTER_RW( 0x7e102040 ) + #define A2W_PLLD_DIG0_MASK 0x00ffffff + #define A2W_PLLD_DIG0_WIDTH 24 + #define A2W_PLLD_DIG0_RESET 0000000000 +#define A2W_PLLD_DIG1 HW_REGISTER_RW( 0x7e102044 ) + #define A2W_PLLD_DIG1_MASK 0x00ffffff + #define A2W_PLLD_DIG1_WIDTH 24 + #define A2W_PLLD_DIG1_RESET 0000000000 +#define A2W_PLLD_DIG2 HW_REGISTER_RW( 0x7e102048 ) + #define A2W_PLLD_DIG2_MASK 0x00ffffff + #define A2W_PLLD_DIG2_WIDTH 24 + #define A2W_PLLD_DIG2_RESET 0000000000 +#define A2W_PLLD_DIG3 HW_REGISTER_RW( 0x7e10204c ) + #define A2W_PLLD_DIG3_MASK 0x00ffffff + #define A2W_PLLD_DIG3_WIDTH 24 + #define A2W_PLLD_DIG3_RESET 0000000000 +#define A2W_PLLD_ANA0 HW_REGISTER_RW( 0x7e102050 ) + #define A2W_PLLD_ANA0_MASK 0x00ffffff + #define A2W_PLLD_ANA0_WIDTH 24 + #define A2W_PLLD_ANA0_RESET 0000000000 +#define A2W_PLLD_ANA1 HW_REGISTER_RW( 0x7e102054 ) + #define A2W_PLLD_ANA1_MASK 0x00ffffff + #define A2W_PLLD_ANA1_WIDTH 24 + #define A2W_PLLD_ANA1_RESET 0000000000 +#define A2W_PLLD_ANA2 HW_REGISTER_RW( 0x7e102058 ) + #define A2W_PLLD_ANA2_MASK 0x00ffffff + #define A2W_PLLD_ANA2_WIDTH 24 + #define A2W_PLLD_ANA2_RESET 0000000000 +#define A2W_PLLD_ANA3 HW_REGISTER_RW( 0x7e10205c ) + #define A2W_PLLD_ANA3_MASK 0x00ffffff + #define A2W_PLLD_ANA3_WIDTH 24 + #define A2W_PLLD_ANA3_RESET 0000000000 +#define A2W_PLLH_DIG0 HW_REGISTER_RW( 0x7e102060 ) + #define A2W_PLLH_DIG0_MASK 0x00ffffff + #define A2W_PLLH_DIG0_WIDTH 24 + #define A2W_PLLH_DIG0_RESET 0000000000 +#define A2W_PLLH_DIG1 HW_REGISTER_RW( 0x7e102064 ) + #define A2W_PLLH_DIG1_MASK 0x00ffffff + #define A2W_PLLH_DIG1_WIDTH 24 + #define A2W_PLLH_DIG1_RESET 0000000000 +#define A2W_PLLH_DIG2 HW_REGISTER_RW( 0x7e102068 ) + #define A2W_PLLH_DIG2_MASK 0x00ffffff + #define A2W_PLLH_DIG2_WIDTH 24 + #define A2W_PLLH_DIG2_RESET 0000000000 +#define A2W_PLLH_DIG3 HW_REGISTER_RW( 0x7e10206c ) + #define A2W_PLLH_DIG3_MASK 0x00ffffff + #define A2W_PLLH_DIG3_WIDTH 24 + #define A2W_PLLH_DIG3_RESET 0000000000 +#define A2W_PLLH_ANA0 HW_REGISTER_RW( 0x7e102070 ) + #define A2W_PLLH_ANA0_MASK 0x00ffffff + #define A2W_PLLH_ANA0_WIDTH 24 + #define A2W_PLLH_ANA0_RESET 0000000000 +#define A2W_PLLH_ANA1 HW_REGISTER_RW( 0x7e102074 ) + #define A2W_PLLH_ANA1_MASK 0x00ffffff + #define A2W_PLLH_ANA1_WIDTH 24 + #define A2W_PLLH_ANA1_RESET 0000000000 +#define A2W_PLLH_ANA2 HW_REGISTER_RW( 0x7e102078 ) + #define A2W_PLLH_ANA2_MASK 0x00ffffff + #define A2W_PLLH_ANA2_WIDTH 24 + #define A2W_PLLH_ANA2_RESET 0000000000 +#define A2W_PLLH_ANA3 HW_REGISTER_RW( 0x7e10207c ) + #define A2W_PLLH_ANA3_MASK 0x00ffffff + #define A2W_PLLH_ANA3_WIDTH 24 + #define A2W_PLLH_ANA3_RESET 0000000000 +#define A2W_HDMI_CTL0 HW_REGISTER_RW( 0x7e102080 ) + #define A2W_HDMI_CTL0_MASK 0x00ffffff + #define A2W_HDMI_CTL0_WIDTH 24 + #define A2W_HDMI_CTL0_RESET 0000000000 +#define A2W_HDMI_CTL1 HW_REGISTER_RW( 0x7e102084 ) + #define A2W_HDMI_CTL1_MASK 0x00ffffff + #define A2W_HDMI_CTL1_WIDTH 24 + #define A2W_HDMI_CTL1_RESET 0000000000 +#define A2W_HDMI_CTL2 HW_REGISTER_RW( 0x7e102088 ) + #define A2W_HDMI_CTL2_MASK 0x00ffffff + #define A2W_HDMI_CTL2_WIDTH 24 + #define A2W_HDMI_CTL2_RESET 0000000000 +#define A2W_HDMI_CTL3 HW_REGISTER_RW( 0x7e10208c ) + #define A2W_HDMI_CTL3_MASK 0x00ffffff + #define A2W_HDMI_CTL3_WIDTH 24 + #define A2W_HDMI_CTL3_RESET 0000000000 +#define A2W_XOSC0 HW_REGISTER_RW( 0x7e102090 ) + #define A2W_XOSC0_MASK 0x00ffffff + #define A2W_XOSC0_WIDTH 24 + #define A2W_XOSC0_RESET 0000000000 +#define A2W_XOSC1 HW_REGISTER_RW( 0x7e102094 ) + #define A2W_XOSC1_MASK 0x00ffffff + #define A2W_XOSC1_WIDTH 24 + #define A2W_XOSC1_RESET 0000000000 +#define A2W_SMPS_CTLA0 HW_REGISTER_RW( 0x7e1020a0 ) + #define A2W_SMPS_CTLA0_MASK 0x00ffffff + #define A2W_SMPS_CTLA0_WIDTH 24 + #define A2W_SMPS_CTLA0_RESET 0000000000 +#define A2W_SMPS_CTLA1 HW_REGISTER_RW( 0x7e1020a4 ) + #define A2W_SMPS_CTLA1_MASK 0x00ffffff + #define A2W_SMPS_CTLA1_WIDTH 24 + #define A2W_SMPS_CTLA1_RESET 0000000000 +#define A2W_SMPS_CTLA2 HW_REGISTER_RW( 0x7e1020a8 ) + #define A2W_SMPS_CTLA2_MASK 0x00ffffff + #define A2W_SMPS_CTLA2_WIDTH 24 + #define A2W_SMPS_CTLA2_RESET 0000000000 +#define A2W_SMPS_CTLB0 HW_REGISTER_RW( 0x7e1020b0 ) + #define A2W_SMPS_CTLB0_MASK 0x00ffffff + #define A2W_SMPS_CTLB0_WIDTH 24 + #define A2W_SMPS_CTLB0_RESET 0000000000 +#define A2W_SMPS_CTLB1 HW_REGISTER_RW( 0x7e1020b4 ) + #define A2W_SMPS_CTLB1_MASK 0x00ffffff + #define A2W_SMPS_CTLB1_WIDTH 24 + #define A2W_SMPS_CTLB1_RESET 0000000000 +#define A2W_SMPS_CTLB2 HW_REGISTER_RW( 0x7e1020b8 ) + #define A2W_SMPS_CTLB2_MASK 0x00ffffff + #define A2W_SMPS_CTLB2_WIDTH 24 + #define A2W_SMPS_CTLB2_RESET 0000000000 +#define A2W_SMPS_CTLC0 HW_REGISTER_RW( 0x7e1020c0 ) + #define A2W_SMPS_CTLC0_MASK 0x00ffffff + #define A2W_SMPS_CTLC0_WIDTH 24 + #define A2W_SMPS_CTLC0_RESET 0000000000 +#define A2W_SMPS_CTLC1 HW_REGISTER_RW( 0x7e1020c4 ) + #define A2W_SMPS_CTLC1_MASK 0x00ffffff + #define A2W_SMPS_CTLC1_WIDTH 24 + #define A2W_SMPS_CTLC1_RESET 0000000000 +#define A2W_SMPS_CTLC2 HW_REGISTER_RW( 0x7e1020c8 ) + #define A2W_SMPS_CTLC2_MASK 0x00ffffff + #define A2W_SMPS_CTLC2_WIDTH 24 + #define A2W_SMPS_CTLC2_RESET 0000000000 +#define A2W_SMPS_CTLC3 HW_REGISTER_RW( 0x7e1020cc ) + #define A2W_SMPS_CTLC3_MASK 0x00ffffff + #define A2W_SMPS_CTLC3_WIDTH 24 + #define A2W_SMPS_CTLC3_RESET 0000000000 +#define A2W_SMPS_LDO0 HW_REGISTER_RW( 0x7e1020d0 ) + #define A2W_SMPS_LDO0_MASK 0x00ffffff + #define A2W_SMPS_LDO0_WIDTH 24 + #define A2W_SMPS_LDO0_RESET 0000000000 +#define A2W_SMPS_LDO1 HW_REGISTER_RW( 0x7e1020d4 ) + #define A2W_SMPS_LDO1_MASK 0x00ffffff + #define A2W_SMPS_LDO1_WIDTH 24 + #define A2W_SMPS_LDO1_RESET 0000000000 +#define A2W_PLLA_CTRL HW_REGISTER_RW( 0x7e102100 ) + #define A2W_PLLA_CTRL_MASK 0x000373ff + #define A2W_PLLA_CTRL_WIDTH 18 + #define A2W_PLLA_CTRL_RESET 0000000000 + #define A2W_PLLA_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLA_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLA_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLA_CTRL_PRSTN_MSB 17 + #define A2W_PLLA_CTRL_PRSTN_LSB 17 + #define A2W_PLLA_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLA_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLA_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLA_CTRL_PWRDN_MSB 16 + #define A2W_PLLA_CTRL_PWRDN_LSB 16 + #define A2W_PLLA_CTRL_PDIV_BITS 14:12 + #define A2W_PLLA_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLA_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLA_CTRL_PDIV_MSB 14 + #define A2W_PLLA_CTRL_PDIV_LSB 12 + #define A2W_PLLA_CTRL_NDIV_BITS 9:0 + #define A2W_PLLA_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLA_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLA_CTRL_NDIV_MSB 9 + #define A2W_PLLA_CTRL_NDIV_LSB 0 +#define A2W_PLLA_FRAC HW_REGISTER_RW( 0x7e102200 ) + #define A2W_PLLA_FRAC_MASK 0x000fffff + #define A2W_PLLA_FRAC_WIDTH 20 + #define A2W_PLLA_FRAC_RESET 0000000000 + #define A2W_PLLA_FRAC_FRAC_BITS 19:0 + #define A2W_PLLA_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLA_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLA_FRAC_FRAC_MSB 19 + #define A2W_PLLA_FRAC_FRAC_LSB 0 +#define A2W_PLLA_DSI0 HW_REGISTER_RW( 0x7e102300 ) + #define A2W_PLLA_DSI0_MASK 0x000003ff + #define A2W_PLLA_DSI0_WIDTH 10 + #define A2W_PLLA_DSI0_RESET 0000000000 + #define A2W_PLLA_DSI0_BYPEN_BITS 9:9 + #define A2W_PLLA_DSI0_BYPEN_SET 0x00000200 + #define A2W_PLLA_DSI0_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_DSI0_BYPEN_MSB 9 + #define A2W_PLLA_DSI0_BYPEN_LSB 9 + #define A2W_PLLA_DSI0_CHENB_BITS 8:8 + #define A2W_PLLA_DSI0_CHENB_SET 0x00000100 + #define A2W_PLLA_DSI0_CHENB_CLR 0xfffffeff + #define A2W_PLLA_DSI0_CHENB_MSB 8 + #define A2W_PLLA_DSI0_CHENB_LSB 8 + #define A2W_PLLA_DSI0_DIV_BITS 7:0 + #define A2W_PLLA_DSI0_DIV_SET 0x000000ff + #define A2W_PLLA_DSI0_DIV_CLR 0xffffff00 + #define A2W_PLLA_DSI0_DIV_MSB 7 + #define A2W_PLLA_DSI0_DIV_LSB 0 +#define A2W_PLLA_CORE HW_REGISTER_RW( 0x7e102400 ) + #define A2W_PLLA_CORE_MASK 0x000003ff + #define A2W_PLLA_CORE_WIDTH 10 + #define A2W_PLLA_CORE_RESET 0000000000 + #define A2W_PLLA_CORE_BYPEN_BITS 9:9 + #define A2W_PLLA_CORE_BYPEN_SET 0x00000200 + #define A2W_PLLA_CORE_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_CORE_BYPEN_MSB 9 + #define A2W_PLLA_CORE_BYPEN_LSB 9 + #define A2W_PLLA_CORE_CHENB_BITS 8:8 + #define A2W_PLLA_CORE_CHENB_SET 0x00000100 + #define A2W_PLLA_CORE_CHENB_CLR 0xfffffeff + #define A2W_PLLA_CORE_CHENB_MSB 8 + #define A2W_PLLA_CORE_CHENB_LSB 8 + #define A2W_PLLA_CORE_DIV_BITS 7:0 + #define A2W_PLLA_CORE_DIV_SET 0x000000ff + #define A2W_PLLA_CORE_DIV_CLR 0xffffff00 + #define A2W_PLLA_CORE_DIV_MSB 7 + #define A2W_PLLA_CORE_DIV_LSB 0 +#define A2W_PLLA_PER HW_REGISTER_RW( 0x7e102500 ) + #define A2W_PLLA_PER_MASK 0x000003ff + #define A2W_PLLA_PER_WIDTH 10 + #define A2W_PLLA_PER_RESET 0000000000 + #define A2W_PLLA_PER_BYPEN_BITS 9:9 + #define A2W_PLLA_PER_BYPEN_SET 0x00000200 + #define A2W_PLLA_PER_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_PER_BYPEN_MSB 9 + #define A2W_PLLA_PER_BYPEN_LSB 9 + #define A2W_PLLA_PER_CHENB_BITS 8:8 + #define A2W_PLLA_PER_CHENB_SET 0x00000100 + #define A2W_PLLA_PER_CHENB_CLR 0xfffffeff + #define A2W_PLLA_PER_CHENB_MSB 8 + #define A2W_PLLA_PER_CHENB_LSB 8 + #define A2W_PLLA_PER_DIV_BITS 7:0 + #define A2W_PLLA_PER_DIV_SET 0x000000ff + #define A2W_PLLA_PER_DIV_CLR 0xffffff00 + #define A2W_PLLA_PER_DIV_MSB 7 + #define A2W_PLLA_PER_DIV_LSB 0 +#define A2W_PLLA_CCP2 HW_REGISTER_RW( 0x7e102600 ) + #define A2W_PLLA_CCP2_MASK 0x000003ff + #define A2W_PLLA_CCP2_WIDTH 10 + #define A2W_PLLA_CCP2_RESET 0000000000 + #define A2W_PLLA_CCP2_BYPEN_BITS 9:9 + #define A2W_PLLA_CCP2_BYPEN_SET 0x00000200 + #define A2W_PLLA_CCP2_BYPEN_CLR 0xfffffdff + #define A2W_PLLA_CCP2_BYPEN_MSB 9 + #define A2W_PLLA_CCP2_BYPEN_LSB 9 + #define A2W_PLLA_CCP2_CHENB_BITS 8:8 + #define A2W_PLLA_CCP2_CHENB_SET 0x00000100 + #define A2W_PLLA_CCP2_CHENB_CLR 0xfffffeff + #define A2W_PLLA_CCP2_CHENB_MSB 8 + #define A2W_PLLA_CCP2_CHENB_LSB 8 + #define A2W_PLLA_CCP2_DIV_BITS 7:0 + #define A2W_PLLA_CCP2_DIV_SET 0x000000ff + #define A2W_PLLA_CCP2_DIV_CLR 0xffffff00 + #define A2W_PLLA_CCP2_DIV_MSB 7 + #define A2W_PLLA_CCP2_DIV_LSB 0 +#define A2W_PLLC_CTRL HW_REGISTER_RW( 0x7e102120 ) + #define A2W_PLLC_CTRL_MASK 0x000373ff + #define A2W_PLLC_CTRL_WIDTH 18 + #define A2W_PLLC_CTRL_RESET 0000000000 + #define A2W_PLLC_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLC_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLC_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLC_CTRL_PRSTN_MSB 17 + #define A2W_PLLC_CTRL_PRSTN_LSB 17 + #define A2W_PLLC_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLC_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLC_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLC_CTRL_PWRDN_MSB 16 + #define A2W_PLLC_CTRL_PWRDN_LSB 16 + #define A2W_PLLC_CTRL_PDIV_BITS 14:12 + #define A2W_PLLC_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLC_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLC_CTRL_PDIV_MSB 14 + #define A2W_PLLC_CTRL_PDIV_LSB 12 + #define A2W_PLLC_CTRL_NDIV_BITS 9:0 + #define A2W_PLLC_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLC_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLC_CTRL_NDIV_MSB 9 + #define A2W_PLLC_CTRL_NDIV_LSB 0 +#define A2W_PLLC_FRAC HW_REGISTER_RW( 0x7e102220 ) + #define A2W_PLLC_FRAC_MASK 0x000fffff + #define A2W_PLLC_FRAC_WIDTH 20 + #define A2W_PLLC_FRAC_RESET 0000000000 + #define A2W_PLLC_FRAC_FRAC_BITS 19:0 + #define A2W_PLLC_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLC_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLC_FRAC_FRAC_MSB 19 + #define A2W_PLLC_FRAC_FRAC_LSB 0 +#define A2W_PLLC_CORE2 HW_REGISTER_RW( 0x7e102320 ) + #define A2W_PLLC_CORE2_MASK 0x000003ff + #define A2W_PLLC_CORE2_WIDTH 10 + #define A2W_PLLC_CORE2_RESET 0000000000 + #define A2W_PLLC_CORE2_BYPEN_BITS 9:9 + #define A2W_PLLC_CORE2_BYPEN_SET 0x00000200 + #define A2W_PLLC_CORE2_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_CORE2_BYPEN_MSB 9 + #define A2W_PLLC_CORE2_BYPEN_LSB 9 + #define A2W_PLLC_CORE2_CHENB_BITS 8:8 + #define A2W_PLLC_CORE2_CHENB_SET 0x00000100 + #define A2W_PLLC_CORE2_CHENB_CLR 0xfffffeff + #define A2W_PLLC_CORE2_CHENB_MSB 8 + #define A2W_PLLC_CORE2_CHENB_LSB 8 + #define A2W_PLLC_CORE2_DIV_BITS 7:0 + #define A2W_PLLC_CORE2_DIV_SET 0x000000ff + #define A2W_PLLC_CORE2_DIV_CLR 0xffffff00 + #define A2W_PLLC_CORE2_DIV_MSB 7 + #define A2W_PLLC_CORE2_DIV_LSB 0 +#define A2W_PLLC_CORE1 HW_REGISTER_RW( 0x7e102420 ) + #define A2W_PLLC_CORE1_MASK 0x000003ff + #define A2W_PLLC_CORE1_WIDTH 10 + #define A2W_PLLC_CORE1_RESET 0000000000 + #define A2W_PLLC_CORE1_BYPEN_BITS 9:9 + #define A2W_PLLC_CORE1_BYPEN_SET 0x00000200 + #define A2W_PLLC_CORE1_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_CORE1_BYPEN_MSB 9 + #define A2W_PLLC_CORE1_BYPEN_LSB 9 + #define A2W_PLLC_CORE1_CHENB_BITS 8:8 + #define A2W_PLLC_CORE1_CHENB_SET 0x00000100 + #define A2W_PLLC_CORE1_CHENB_CLR 0xfffffeff + #define A2W_PLLC_CORE1_CHENB_MSB 8 + #define A2W_PLLC_CORE1_CHENB_LSB 8 + #define A2W_PLLC_CORE1_DIV_BITS 7:0 + #define A2W_PLLC_CORE1_DIV_SET 0x000000ff + #define A2W_PLLC_CORE1_DIV_CLR 0xffffff00 + #define A2W_PLLC_CORE1_DIV_MSB 7 + #define A2W_PLLC_CORE1_DIV_LSB 0 +#define A2W_PLLC_PER HW_REGISTER_RW( 0x7e102520 ) + #define A2W_PLLC_PER_MASK 0x000003ff + #define A2W_PLLC_PER_WIDTH 10 + #define A2W_PLLC_PER_RESET 0000000000 + #define A2W_PLLC_PER_BYPEN_BITS 9:9 + #define A2W_PLLC_PER_BYPEN_SET 0x00000200 + #define A2W_PLLC_PER_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_PER_BYPEN_MSB 9 + #define A2W_PLLC_PER_BYPEN_LSB 9 + #define A2W_PLLC_PER_CHENB_BITS 8:8 + #define A2W_PLLC_PER_CHENB_SET 0x00000100 + #define A2W_PLLC_PER_CHENB_CLR 0xfffffeff + #define A2W_PLLC_PER_CHENB_MSB 8 + #define A2W_PLLC_PER_CHENB_LSB 8 + #define A2W_PLLC_PER_DIV_BITS 7:0 + #define A2W_PLLC_PER_DIV_SET 0x000000ff + #define A2W_PLLC_PER_DIV_CLR 0xffffff00 + #define A2W_PLLC_PER_DIV_MSB 7 + #define A2W_PLLC_PER_DIV_LSB 0 +#define A2W_PLLC_CORE0 HW_REGISTER_RW( 0x7e102620 ) + #define A2W_PLLC_CORE0_MASK 0x000003ff + #define A2W_PLLC_CORE0_WIDTH 10 + #define A2W_PLLC_CORE0_RESET 0000000000 + #define A2W_PLLC_CORE0_BYPEN_BITS 9:9 + #define A2W_PLLC_CORE0_BYPEN_SET 0x00000200 + #define A2W_PLLC_CORE0_BYPEN_CLR 0xfffffdff + #define A2W_PLLC_CORE0_BYPEN_MSB 9 + #define A2W_PLLC_CORE0_BYPEN_LSB 9 + #define A2W_PLLC_CORE0_CHENB_BITS 8:8 + #define A2W_PLLC_CORE0_CHENB_SET 0x00000100 + #define A2W_PLLC_CORE0_CHENB_CLR 0xfffffeff + #define A2W_PLLC_CORE0_CHENB_MSB 8 + #define A2W_PLLC_CORE0_CHENB_LSB 8 + #define A2W_PLLC_CORE0_DIV_BITS 7:0 + #define A2W_PLLC_CORE0_DIV_SET 0x000000ff + #define A2W_PLLC_CORE0_DIV_CLR 0xffffff00 + #define A2W_PLLC_CORE0_DIV_MSB 7 + #define A2W_PLLC_CORE0_DIV_LSB 0 +#define A2W_PLLD_CTRL HW_REGISTER_RW( 0x7e102140 ) + #define A2W_PLLD_CTRL_MASK 0x000373ff + #define A2W_PLLD_CTRL_WIDTH 18 + #define A2W_PLLD_CTRL_RESET 0000000000 + #define A2W_PLLD_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLD_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLD_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLD_CTRL_PRSTN_MSB 17 + #define A2W_PLLD_CTRL_PRSTN_LSB 17 + #define A2W_PLLD_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLD_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLD_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLD_CTRL_PWRDN_MSB 16 + #define A2W_PLLD_CTRL_PWRDN_LSB 16 + #define A2W_PLLD_CTRL_PDIV_BITS 14:12 + #define A2W_PLLD_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLD_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLD_CTRL_PDIV_MSB 14 + #define A2W_PLLD_CTRL_PDIV_LSB 12 + #define A2W_PLLD_CTRL_NDIV_BITS 9:0 + #define A2W_PLLD_CTRL_NDIV_SET 0x000003ff + #define A2W_PLLD_CTRL_NDIV_CLR 0xfffffc00 + #define A2W_PLLD_CTRL_NDIV_MSB 9 + #define A2W_PLLD_CTRL_NDIV_LSB 0 +#define A2W_PLLD_FRAC HW_REGISTER_RW( 0x7e102240 ) + #define A2W_PLLD_FRAC_MASK 0x000fffff + #define A2W_PLLD_FRAC_WIDTH 20 + #define A2W_PLLD_FRAC_RESET 0000000000 + #define A2W_PLLD_FRAC_FRAC_BITS 19:0 + #define A2W_PLLD_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLD_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLD_FRAC_FRAC_MSB 19 + #define A2W_PLLD_FRAC_FRAC_LSB 0 +#define A2W_PLLD_DSI0 HW_REGISTER_RW( 0x7e102340 ) + #define A2W_PLLD_DSI0_MASK 0x000003ff + #define A2W_PLLD_DSI0_WIDTH 10 + #define A2W_PLLD_DSI0_RESET 0000000000 + #define A2W_PLLD_DSI0_BYPEN_BITS 9:9 + #define A2W_PLLD_DSI0_BYPEN_SET 0x00000200 + #define A2W_PLLD_DSI0_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_DSI0_BYPEN_MSB 9 + #define A2W_PLLD_DSI0_BYPEN_LSB 9 + #define A2W_PLLD_DSI0_CHENB_BITS 8:8 + #define A2W_PLLD_DSI0_CHENB_SET 0x00000100 + #define A2W_PLLD_DSI0_CHENB_CLR 0xfffffeff + #define A2W_PLLD_DSI0_CHENB_MSB 8 + #define A2W_PLLD_DSI0_CHENB_LSB 8 + #define A2W_PLLD_DSI0_DIV_BITS 7:0 + #define A2W_PLLD_DSI0_DIV_SET 0x000000ff + #define A2W_PLLD_DSI0_DIV_CLR 0xffffff00 + #define A2W_PLLD_DSI0_DIV_MSB 7 + #define A2W_PLLD_DSI0_DIV_LSB 0 +#define A2W_PLLD_CORE HW_REGISTER_RW( 0x7e102440 ) + #define A2W_PLLD_CORE_MASK 0x000003ff + #define A2W_PLLD_CORE_WIDTH 10 + #define A2W_PLLD_CORE_RESET 0000000000 + #define A2W_PLLD_CORE_BYPEN_BITS 9:9 + #define A2W_PLLD_CORE_BYPEN_SET 0x00000200 + #define A2W_PLLD_CORE_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_CORE_BYPEN_MSB 9 + #define A2W_PLLD_CORE_BYPEN_LSB 9 + #define A2W_PLLD_CORE_CHENB_BITS 8:8 + #define A2W_PLLD_CORE_CHENB_SET 0x00000100 + #define A2W_PLLD_CORE_CHENB_CLR 0xfffffeff + #define A2W_PLLD_CORE_CHENB_MSB 8 + #define A2W_PLLD_CORE_CHENB_LSB 8 + #define A2W_PLLD_CORE_DIV_BITS 7:0 + #define A2W_PLLD_CORE_DIV_SET 0x000000ff + #define A2W_PLLD_CORE_DIV_CLR 0xffffff00 + #define A2W_PLLD_CORE_DIV_MSB 7 + #define A2W_PLLD_CORE_DIV_LSB 0 +#define A2W_PLLD_PER HW_REGISTER_RW( 0x7e102540 ) + #define A2W_PLLD_PER_MASK 0x000003ff + #define A2W_PLLD_PER_WIDTH 10 + #define A2W_PLLD_PER_RESET 0000000000 + #define A2W_PLLD_PER_BYPEN_BITS 9:9 + #define A2W_PLLD_PER_BYPEN_SET 0x00000200 + #define A2W_PLLD_PER_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_PER_BYPEN_MSB 9 + #define A2W_PLLD_PER_BYPEN_LSB 9 + #define A2W_PLLD_PER_CHENB_BITS 8:8 + #define A2W_PLLD_PER_CHENB_SET 0x00000100 + #define A2W_PLLD_PER_CHENB_CLR 0xfffffeff + #define A2W_PLLD_PER_CHENB_MSB 8 + #define A2W_PLLD_PER_CHENB_LSB 8 + #define A2W_PLLD_PER_DIV_BITS 7:0 + #define A2W_PLLD_PER_DIV_SET 0x000000ff + #define A2W_PLLD_PER_DIV_CLR 0xffffff00 + #define A2W_PLLD_PER_DIV_MSB 7 + #define A2W_PLLD_PER_DIV_LSB 0 +#define A2W_PLLD_DSI1 HW_REGISTER_RW( 0x7e102640 ) + #define A2W_PLLD_DSI1_MASK 0x000003ff + #define A2W_PLLD_DSI1_WIDTH 10 + #define A2W_PLLD_DSI1_RESET 0000000000 + #define A2W_PLLD_DSI1_BYPEN_BITS 9:9 + #define A2W_PLLD_DSI1_BYPEN_SET 0x00000200 + #define A2W_PLLD_DSI1_BYPEN_CLR 0xfffffdff + #define A2W_PLLD_DSI1_BYPEN_MSB 9 + #define A2W_PLLD_DSI1_BYPEN_LSB 9 + #define A2W_PLLD_DSI1_CHENB_BITS 8:8 + #define A2W_PLLD_DSI1_CHENB_SET 0x00000100 + #define A2W_PLLD_DSI1_CHENB_CLR 0xfffffeff + #define A2W_PLLD_DSI1_CHENB_MSB 8 + #define A2W_PLLD_DSI1_CHENB_LSB 8 + #define A2W_PLLD_DSI1_DIV_BITS 7:0 + #define A2W_PLLD_DSI1_DIV_SET 0x000000ff + #define A2W_PLLD_DSI1_DIV_CLR 0xffffff00 + #define A2W_PLLD_DSI1_DIV_MSB 7 + #define A2W_PLLD_DSI1_DIV_LSB 0 +#define A2W_PLLH_CTRL HW_REGISTER_RW( 0x7e102160 ) + #define A2W_PLLH_CTRL_MASK 0x000370ff + #define A2W_PLLH_CTRL_WIDTH 18 + #define A2W_PLLH_CTRL_RESET 0000000000 + #define A2W_PLLH_CTRL_PRSTN_BITS 17:17 + #define A2W_PLLH_CTRL_PRSTN_SET 0x00020000 + #define A2W_PLLH_CTRL_PRSTN_CLR 0xfffdffff + #define A2W_PLLH_CTRL_PRSTN_MSB 17 + #define A2W_PLLH_CTRL_PRSTN_LSB 17 + #define A2W_PLLH_CTRL_PWRDN_BITS 16:16 + #define A2W_PLLH_CTRL_PWRDN_SET 0x00010000 + #define A2W_PLLH_CTRL_PWRDN_CLR 0xfffeffff + #define A2W_PLLH_CTRL_PWRDN_MSB 16 + #define A2W_PLLH_CTRL_PWRDN_LSB 16 + #define A2W_PLLH_CTRL_PDIV_BITS 14:12 + #define A2W_PLLH_CTRL_PDIV_SET 0x00007000 + #define A2W_PLLH_CTRL_PDIV_CLR 0xffff8fff + #define A2W_PLLH_CTRL_PDIV_MSB 14 + #define A2W_PLLH_CTRL_PDIV_LSB 12 + #define A2W_PLLH_CTRL_NDIV_BITS 7:0 + #define A2W_PLLH_CTRL_NDIV_SET 0x000000ff + #define A2W_PLLH_CTRL_NDIV_CLR 0xffffff00 + #define A2W_PLLH_CTRL_NDIV_MSB 7 + #define A2W_PLLH_CTRL_NDIV_LSB 0 +#define A2W_PLLH_FRAC HW_REGISTER_RW( 0x7e102260 ) + #define A2W_PLLH_FRAC_MASK 0x000fffff + #define A2W_PLLH_FRAC_WIDTH 20 + #define A2W_PLLH_FRAC_RESET 0000000000 + #define A2W_PLLH_FRAC_FRAC_BITS 19:0 + #define A2W_PLLH_FRAC_FRAC_SET 0x000fffff + #define A2W_PLLH_FRAC_FRAC_CLR 0xfff00000 + #define A2W_PLLH_FRAC_FRAC_MSB 19 + #define A2W_PLLH_FRAC_FRAC_LSB 0 +#define A2W_PLLH_AUX HW_REGISTER_RW( 0x7e102360 ) + #define A2W_PLLH_AUX_MASK 0x000003ff + #define A2W_PLLH_AUX_WIDTH 10 + #define A2W_PLLH_AUX_RESET 0000000000 + #define A2W_PLLH_AUX_BYPEN_BITS 9:9 + #define A2W_PLLH_AUX_BYPEN_SET 0x00000200 + #define A2W_PLLH_AUX_BYPEN_CLR 0xfffffdff + #define A2W_PLLH_AUX_BYPEN_MSB 9 + #define A2W_PLLH_AUX_BYPEN_LSB 9 + #define A2W_PLLH_AUX_CHENB_BITS 8:8 + #define A2W_PLLH_AUX_CHENB_SET 0x00000100 + #define A2W_PLLH_AUX_CHENB_CLR 0xfffffeff + #define A2W_PLLH_AUX_CHENB_MSB 8 + #define A2W_PLLH_AUX_CHENB_LSB 8 + #define A2W_PLLH_AUX_DIV_BITS 7:0 + #define A2W_PLLH_AUX_DIV_SET 0x000000ff + #define A2W_PLLH_AUX_DIV_CLR 0xffffff00 + #define A2W_PLLH_AUX_DIV_MSB 7 + #define A2W_PLLH_AUX_DIV_LSB 0 +#define A2W_PLLH_RCAL HW_REGISTER_RW( 0x7e102460 ) + #define A2W_PLLH_RCAL_MASK 0x000003ff + #define A2W_PLLH_RCAL_WIDTH 10 + #define A2W_PLLH_RCAL_RESET 0000000000 + #define A2W_PLLH_RCAL_BYPEN_BITS 9:9 + #define A2W_PLLH_RCAL_BYPEN_SET 0x00000200 + #define A2W_PLLH_RCAL_BYPEN_CLR 0xfffffdff + #define A2W_PLLH_RCAL_BYPEN_MSB 9 + #define A2W_PLLH_RCAL_BYPEN_LSB 9 + #define A2W_PLLH_RCAL_CHENB_BITS 8:8 + #define A2W_PLLH_RCAL_CHENB_SET 0x00000100 + #define A2W_PLLH_RCAL_CHENB_CLR 0xfffffeff + #define A2W_PLLH_RCAL_CHENB_MSB 8 + #define A2W_PLLH_RCAL_CHENB_LSB 8 + #define A2W_PLLH_RCAL_DIV_BITS 7:0 + #define A2W_PLLH_RCAL_DIV_SET 0x000000ff + #define A2W_PLLH_RCAL_DIV_CLR 0xffffff00 + #define A2W_PLLH_RCAL_DIV_MSB 7 + #define A2W_PLLH_RCAL_DIV_LSB 0 +#define A2W_PLLH_PIX HW_REGISTER_RW( 0x7e102560 ) + #define A2W_PLLH_PIX_MASK 0x000003ff + #define A2W_PLLH_PIX_WIDTH 10 + #define A2W_PLLH_PIX_RESET 0000000000 + #define A2W_PLLH_PIX_BYPEN_BITS 9:9 + #define A2W_PLLH_PIX_BYPEN_SET 0x00000200 + #define A2W_PLLH_PIX_BYPEN_CLR 0xfffffdff + #define A2W_PLLH_PIX_BYPEN_MSB 9 + #define A2W_PLLH_PIX_BYPEN_LSB 9 + #define A2W_PLLH_PIX_CHENB_BITS 8:8 + #define A2W_PLLH_PIX_CHENB_SET 0x00000100 + #define A2W_PLLH_PIX_CHENB_CLR 0xfffffeff + #define A2W_PLLH_PIX_CHENB_MSB 8 + #define A2W_PLLH_PIX_CHENB_LSB 8 + #define A2W_PLLH_PIX_DIV_BITS 7:0 + #define A2W_PLLH_PIX_DIV_SET 0x000000ff + #define A2W_PLLH_PIX_DIV_CLR 0xffffff00 + #define A2W_PLLH_PIX_DIV_MSB 7 + #define A2W_PLLH_PIX_DIV_LSB 0 +#define A2W_PLLH_STS HW_REGISTER_RW( 0x7e102660 ) + #define A2W_PLLH_STS_MASK 0xffffffff + #define A2W_PLLH_STS_WIDTH 32 + #define A2W_PLLH_STS_RESET 0000000000 +#define A2W_XOSC_CTRL HW_REGISTER_RW( 0x7e102190 ) + #define A2W_XOSC_CTRL_MASK 0x0000037f + #define A2W_XOSC_CTRL_WIDTH 10 + #define A2W_XOSC_CTRL_RESET 0000000000 + #define A2W_XOSC_CTRL_DIV_BITS 9:8 + #define A2W_XOSC_CTRL_DIV_SET 0x00000300 + #define A2W_XOSC_CTRL_DIV_CLR 0xfffffcff + #define A2W_XOSC_CTRL_DIV_MSB 9 + #define A2W_XOSC_CTRL_DIV_LSB 8 + #define A2W_XOSC_CTRL_PLLAEN_BITS 6:6 + #define A2W_XOSC_CTRL_PLLAEN_SET 0x00000040 + #define A2W_XOSC_CTRL_PLLAEN_CLR 0xffffffbf + #define A2W_XOSC_CTRL_PLLAEN_MSB 6 + #define A2W_XOSC_CTRL_PLLAEN_LSB 6 + #define A2W_XOSC_CTRL_PLLDEN_BITS 5:5 + #define A2W_XOSC_CTRL_PLLDEN_SET 0x00000020 + #define A2W_XOSC_CTRL_PLLDEN_CLR 0xffffffdf + #define A2W_XOSC_CTRL_PLLDEN_MSB 5 + #define A2W_XOSC_CTRL_PLLDEN_LSB 5 + #define A2W_XOSC_CTRL_DDREN_BITS 4:4 + #define A2W_XOSC_CTRL_DDREN_SET 0x00000010 + #define A2W_XOSC_CTRL_DDREN_CLR 0xffffffef + #define A2W_XOSC_CTRL_DDREN_MSB 4 + #define A2W_XOSC_CTRL_DDREN_LSB 4 + #define A2W_XOSC_CTRL_CPR1EN_BITS 3:3 + #define A2W_XOSC_CTRL_CPR1EN_SET 0x00000008 + #define A2W_XOSC_CTRL_CPR1EN_CLR 0xfffffff7 + #define A2W_XOSC_CTRL_CPR1EN_MSB 3 + #define A2W_XOSC_CTRL_CPR1EN_LSB 3 + #define A2W_XOSC_CTRL_USBEN_BITS 2:2 + #define A2W_XOSC_CTRL_USBEN_SET 0x00000004 + #define A2W_XOSC_CTRL_USBEN_CLR 0xfffffffb + #define A2W_XOSC_CTRL_USBEN_MSB 2 + #define A2W_XOSC_CTRL_USBEN_LSB 2 + #define A2W_XOSC_CTRL_HDMIEN_BITS 1:1 + #define A2W_XOSC_CTRL_HDMIEN_SET 0x00000002 + #define A2W_XOSC_CTRL_HDMIEN_CLR 0xfffffffd + #define A2W_XOSC_CTRL_HDMIEN_MSB 1 + #define A2W_XOSC_CTRL_HDMIEN_LSB 1 + #define A2W_XOSC_CTRL_PLLCEN_BITS 0:0 + #define A2W_XOSC_CTRL_PLLCEN_SET 0x00000001 + #define A2W_XOSC_CTRL_PLLCEN_CLR 0xfffffffe + #define A2W_XOSC_CTRL_PLLCEN_MSB 0 + #define A2W_XOSC_CTRL_PLLCEN_LSB 0 +#define A2W_PLLA_DIG0R HW_REGISTER_RW( 0x7e102800 ) + #define A2W_PLLA_DIG0R_MASK 0x00ffffff + #define A2W_PLLA_DIG0R_WIDTH 24 + #define A2W_PLLA_DIG0R_RESET 0000000000 +#define A2W_PLLA_DIG1R HW_REGISTER_RW( 0x7e102804 ) + #define A2W_PLLA_DIG1R_MASK 0x00ffffff + #define A2W_PLLA_DIG1R_WIDTH 24 + #define A2W_PLLA_DIG1R_RESET 0000000000 +#define A2W_PLLA_DIG2R HW_REGISTER_RW( 0x7e102808 ) + #define A2W_PLLA_DIG2R_MASK 0x00ffffff + #define A2W_PLLA_DIG2R_WIDTH 24 + #define A2W_PLLA_DIG2R_RESET 0000000000 +#define A2W_PLLA_DIG3R HW_REGISTER_RW( 0x7e10280c ) + #define A2W_PLLA_DIG3R_MASK 0x00ffffff + #define A2W_PLLA_DIG3R_WIDTH 24 + #define A2W_PLLA_DIG3R_RESET 0000000000 +#define A2W_PLLA_ANA0R HW_REGISTER_RW( 0x7e102810 ) + #define A2W_PLLA_ANA0R_MASK 0x00ffffff + #define A2W_PLLA_ANA0R_WIDTH 24 + #define A2W_PLLA_ANA0R_RESET 0000000000 +#define A2W_PLLA_ANA1R HW_REGISTER_RW( 0x7e102814 ) + #define A2W_PLLA_ANA1R_MASK 0x00ffffff + #define A2W_PLLA_ANA1R_WIDTH 24 + #define A2W_PLLA_ANA1R_RESET 0000000000 +#define A2W_PLLA_ANA2R HW_REGISTER_RW( 0x7e102818 ) + #define A2W_PLLA_ANA2R_MASK 0x00ffffff + #define A2W_PLLA_ANA2R_WIDTH 24 + #define A2W_PLLA_ANA2R_RESET 0000000000 +#define A2W_PLLA_ANA3R HW_REGISTER_RW( 0x7e10281c ) + #define A2W_PLLA_ANA3R_MASK 0x00ffffff + #define A2W_PLLA_ANA3R_WIDTH 24 + #define A2W_PLLA_ANA3R_RESET 0000000000 +#define A2W_PLLC_DIG0R HW_REGISTER_RW( 0x7e102820 ) + #define A2W_PLLC_DIG0R_MASK 0x00ffffff + #define A2W_PLLC_DIG0R_WIDTH 24 + #define A2W_PLLC_DIG0R_RESET 0000000000 +#define A2W_PLLC_DIG1R HW_REGISTER_RW( 0x7e102824 ) + #define A2W_PLLC_DIG1R_MASK 0x00ffffff + #define A2W_PLLC_DIG1R_WIDTH 24 + #define A2W_PLLC_DIG1R_RESET 0000000000 +#define A2W_PLLC_DIG2R HW_REGISTER_RW( 0x7e102828 ) + #define A2W_PLLC_DIG2R_MASK 0x00ffffff + #define A2W_PLLC_DIG2R_WIDTH 24 + #define A2W_PLLC_DIG2R_RESET 0000000000 +#define A2W_PLLC_DIG3R HW_REGISTER_RW( 0x7e10282c ) + #define A2W_PLLC_DIG3R_MASK 0x00ffffff + #define A2W_PLLC_DIG3R_WIDTH 24 + #define A2W_PLLC_DIG3R_RESET 0000000000 +#define A2W_PLLC_ANA0R HW_REGISTER_RW( 0x7e102830 ) + #define A2W_PLLC_ANA0R_MASK 0x00ffffff + #define A2W_PLLC_ANA0R_WIDTH 24 + #define A2W_PLLC_ANA0R_RESET 0000000000 +#define A2W_PLLC_ANA1R HW_REGISTER_RW( 0x7e102834 ) + #define A2W_PLLC_ANA1R_MASK 0x00ffffff + #define A2W_PLLC_ANA1R_WIDTH 24 + #define A2W_PLLC_ANA1R_RESET 0000000000 +#define A2W_PLLC_ANA2R HW_REGISTER_RW( 0x7e102838 ) + #define A2W_PLLC_ANA2R_MASK 0x00ffffff + #define A2W_PLLC_ANA2R_WIDTH 24 + #define A2W_PLLC_ANA2R_RESET 0000000000 +#define A2W_PLLC_ANA3R HW_REGISTER_RW( 0x7e10283c ) + #define A2W_PLLC_ANA3R_MASK 0x00ffffff + #define A2W_PLLC_ANA3R_WIDTH 24 + #define A2W_PLLC_ANA3R_RESET 0000000000 +#define A2W_PLLD_DIG0R HW_REGISTER_RW( 0x7e102840 ) + #define A2W_PLLD_DIG0R_MASK 0x00ffffff + #define A2W_PLLD_DIG0R_WIDTH 24 + #define A2W_PLLD_DIG0R_RESET 0000000000 +#define A2W_PLLD_DIG1R HW_REGISTER_RW( 0x7e102844 ) + #define A2W_PLLD_DIG1R_MASK 0x00ffffff + #define A2W_PLLD_DIG1R_WIDTH 24 + #define A2W_PLLD_DIG1R_RESET 0000000000 +#define A2W_PLLD_DIG2R HW_REGISTER_RW( 0x7e102848 ) + #define A2W_PLLD_DIG2R_MASK 0x00ffffff + #define A2W_PLLD_DIG2R_WIDTH 24 + #define A2W_PLLD_DIG2R_RESET 0000000000 +#define A2W_PLLD_DIG3R HW_REGISTER_RW( 0x7e10284c ) + #define A2W_PLLD_DIG3R_MASK 0x00ffffff + #define A2W_PLLD_DIG3R_WIDTH 24 + #define A2W_PLLD_DIG3R_RESET 0000000000 +#define A2W_PLLD_ANA0R HW_REGISTER_RW( 0x7e102850 ) + #define A2W_PLLD_ANA0R_MASK 0x00ffffff + #define A2W_PLLD_ANA0R_WIDTH 24 + #define A2W_PLLD_ANA0R_RESET 0000000000 +#define A2W_PLLD_ANA1R HW_REGISTER_RW( 0x7e102854 ) + #define A2W_PLLD_ANA1R_MASK 0x00ffffff + #define A2W_PLLD_ANA1R_WIDTH 24 + #define A2W_PLLD_ANA1R_RESET 0000000000 +#define A2W_PLLD_ANA2R HW_REGISTER_RW( 0x7e102858 ) + #define A2W_PLLD_ANA2R_MASK 0x00ffffff + #define A2W_PLLD_ANA2R_WIDTH 24 + #define A2W_PLLD_ANA2R_RESET 0000000000 +#define A2W_PLLD_ANA3R HW_REGISTER_RW( 0x7e10285c ) + #define A2W_PLLD_ANA3R_MASK 0x00ffffff + #define A2W_PLLD_ANA3R_WIDTH 24 + #define A2W_PLLD_ANA3R_RESET 0000000000 +#define A2W_PLLH_DIG0R HW_REGISTER_RW( 0x7e102860 ) + #define A2W_PLLH_DIG0R_MASK 0x00ffffff + #define A2W_PLLH_DIG0R_WIDTH 24 + #define A2W_PLLH_DIG0R_RESET 0000000000 +#define A2W_PLLH_DIG1R HW_REGISTER_RW( 0x7e102864 ) + #define A2W_PLLH_DIG1R_MASK 0x00ffffff + #define A2W_PLLH_DIG1R_WIDTH 24 + #define A2W_PLLH_DIG1R_RESET 0000000000 +#define A2W_PLLH_DIG2R HW_REGISTER_RW( 0x7e102868 ) + #define A2W_PLLH_DIG2R_MASK 0x00ffffff + #define A2W_PLLH_DIG2R_WIDTH 24 + #define A2W_PLLH_DIG2R_RESET 0000000000 +#define A2W_PLLH_DIG3R HW_REGISTER_RW( 0x7e10286c ) + #define A2W_PLLH_DIG3R_MASK 0x00ffffff + #define A2W_PLLH_DIG3R_WIDTH 24 + #define A2W_PLLH_DIG3R_RESET 0000000000 +#define A2W_PLLH_ANA0R HW_REGISTER_RW( 0x7e102870 ) + #define A2W_PLLH_ANA0R_MASK 0x00ffffff + #define A2W_PLLH_ANA0R_WIDTH 24 + #define A2W_PLLH_ANA0R_RESET 0000000000 +#define A2W_PLLH_ANA1R HW_REGISTER_RW( 0x7e102874 ) + #define A2W_PLLH_ANA1R_MASK 0x00ffffff + #define A2W_PLLH_ANA1R_WIDTH 24 + #define A2W_PLLH_ANA1R_RESET 0000000000 +#define A2W_PLLH_ANA2R HW_REGISTER_RW( 0x7e102878 ) + #define A2W_PLLH_ANA2R_MASK 0x00ffffff + #define A2W_PLLH_ANA2R_WIDTH 24 + #define A2W_PLLH_ANA2R_RESET 0000000000 +#define A2W_PLLH_ANA3R HW_REGISTER_RW( 0x7e10287c ) + #define A2W_PLLH_ANA3R_MASK 0x00ffffff + #define A2W_PLLH_ANA3R_WIDTH 24 + #define A2W_PLLH_ANA3R_RESET 0000000000 +#define A2W_HDMI_CTL0R HW_REGISTER_RW( 0x7e102880 ) + #define A2W_HDMI_CTL0R_MASK 0x00ffffff + #define A2W_HDMI_CTL0R_WIDTH 24 + #define A2W_HDMI_CTL0R_RESET 0000000000 +#define A2W_HDMI_CTL1R HW_REGISTER_RW( 0x7e102884 ) + #define A2W_HDMI_CTL1R_MASK 0x00ffffff + #define A2W_HDMI_CTL1R_WIDTH 24 + #define A2W_HDMI_CTL1R_RESET 0000000000 +#define A2W_HDMI_CTL2R HW_REGISTER_RW( 0x7e102888 ) + #define A2W_HDMI_CTL2R_MASK 0x00ffffff + #define A2W_HDMI_CTL2R_WIDTH 24 + #define A2W_HDMI_CTL2R_RESET 0000000000 +#define A2W_HDMI_CTL3R HW_REGISTER_RW( 0x7e10288c ) + #define A2W_HDMI_CTL3R_MASK 0x00ffffff + #define A2W_HDMI_CTL3R_WIDTH 24 + #define A2W_HDMI_CTL3R_RESET 0000000000 +#define A2W_XOSC0R HW_REGISTER_RW( 0x7e102890 ) + #define A2W_XOSC0R_MASK 0x00ffffff + #define A2W_XOSC0R_WIDTH 24 + #define A2W_XOSC0R_RESET 0000000000 +#define A2W_XOSC1R HW_REGISTER_RW( 0x7e102894 ) + #define A2W_XOSC1R_MASK 0x00ffffff + #define A2W_XOSC1R_WIDTH 24 + #define A2W_XOSC1R_RESET 0000000000 +#define A2W_SMPS_CTLA0R HW_REGISTER_RW( 0x7e1028a0 ) + #define A2W_SMPS_CTLA0R_MASK 0x00ffffff + #define A2W_SMPS_CTLA0R_WIDTH 24 + #define A2W_SMPS_CTLA0R_RESET 0000000000 +#define A2W_SMPS_CTLA1R HW_REGISTER_RW( 0x7e1028a4 ) + #define A2W_SMPS_CTLA1R_MASK 0x00ffffff + #define A2W_SMPS_CTLA1R_WIDTH 24 + #define A2W_SMPS_CTLA1R_RESET 0000000000 +#define A2W_SMPS_CTLA2R HW_REGISTER_RW( 0x7e1028a8 ) + #define A2W_SMPS_CTLA2R_MASK 0x00ffffff + #define A2W_SMPS_CTLA2R_WIDTH 24 + #define A2W_SMPS_CTLA2R_RESET 0000000000 +#define A2W_SMPS_CTLB0R HW_REGISTER_RW( 0x7e1028b0 ) + #define A2W_SMPS_CTLB0R_MASK 0x00ffffff + #define A2W_SMPS_CTLB0R_WIDTH 24 + #define A2W_SMPS_CTLB0R_RESET 0000000000 +#define A2W_SMPS_CTLB1R HW_REGISTER_RW( 0x7e1028b4 ) + #define A2W_SMPS_CTLB1R_MASK 0x00ffffff + #define A2W_SMPS_CTLB1R_WIDTH 24 + #define A2W_SMPS_CTLB1R_RESET 0000000000 +#define A2W_SMPS_CTLB2R HW_REGISTER_RW( 0x7e1028b8 ) + #define A2W_SMPS_CTLB2R_MASK 0x00ffffff + #define A2W_SMPS_CTLB2R_WIDTH 24 + #define A2W_SMPS_CTLB2R_RESET 0000000000 +#define A2W_SMPS_CTLC0R HW_REGISTER_RW( 0x7e1028c0 ) + #define A2W_SMPS_CTLC0R_MASK 0x00ffffff + #define A2W_SMPS_CTLC0R_WIDTH 24 + #define A2W_SMPS_CTLC0R_RESET 0000000000 +#define A2W_SMPS_CTLC1R HW_REGISTER_RW( 0x7e1028c4 ) + #define A2W_SMPS_CTLC1R_MASK 0x00ffffff + #define A2W_SMPS_CTLC1R_WIDTH 24 + #define A2W_SMPS_CTLC1R_RESET 0000000000 +#define A2W_SMPS_CTLC2R HW_REGISTER_RW( 0x7e1028c8 ) + #define A2W_SMPS_CTLC2R_MASK 0x00ffffff + #define A2W_SMPS_CTLC2R_WIDTH 24 + #define A2W_SMPS_CTLC2R_RESET 0000000000 +#define A2W_SMPS_CTLC3R HW_REGISTER_RW( 0x7e1028cc ) + #define A2W_SMPS_CTLC3R_MASK 0x00ffffff + #define A2W_SMPS_CTLC3R_WIDTH 24 + #define A2W_SMPS_CTLC3R_RESET 0000000000 +#define A2W_SMPS_LDO0R HW_REGISTER_RW( 0x7e1028d0 ) + #define A2W_SMPS_LDO0R_MASK 0x00ffffff + #define A2W_SMPS_LDO0R_WIDTH 24 + #define A2W_SMPS_LDO0R_RESET 0000000000 +#define A2W_SMPS_LDO1R HW_REGISTER_RW( 0x7e1028d4 ) + #define A2W_SMPS_LDO1R_MASK 0x00ffffff + #define A2W_SMPS_LDO1R_WIDTH 24 + #define A2W_SMPS_LDO1R_RESET 0000000000 +#define A2W_PLLA_CTRLR HW_REGISTER_RW( 0x7e102900 ) + #define A2W_PLLA_CTRLR_MASK 0x000373ff + #define A2W_PLLA_CTRLR_WIDTH 18 + #define A2W_PLLA_CTRLR_RESET 0000000000 +#define A2W_PLLA_FRACR HW_REGISTER_RW( 0x7e102a00 ) + #define A2W_PLLA_FRACR_MASK 0x000fffff + #define A2W_PLLA_FRACR_WIDTH 20 + #define A2W_PLLA_FRACR_RESET 0000000000 +#define A2W_PLLA_DSI0R HW_REGISTER_RW( 0x7e102b00 ) + #define A2W_PLLA_DSI0R_MASK 0x000003ff + #define A2W_PLLA_DSI0R_WIDTH 10 + #define A2W_PLLA_DSI0R_RESET 0000000000 +#define A2W_PLLA_CORER HW_REGISTER_RW( 0x7e102c00 ) + #define A2W_PLLA_CORER_MASK 0x000003ff + #define A2W_PLLA_CORER_WIDTH 10 + #define A2W_PLLA_CORER_RESET 0000000000 +#define A2W_PLLA_PERR HW_REGISTER_RW( 0x7e102d00 ) + #define A2W_PLLA_PERR_MASK 0x000003ff + #define A2W_PLLA_PERR_WIDTH 10 + #define A2W_PLLA_PERR_RESET 0000000000 +#define A2W_PLLA_CCP2R HW_REGISTER_RW( 0x7e102e00 ) + #define A2W_PLLA_CCP2R_MASK 0x000003ff + #define A2W_PLLA_CCP2R_WIDTH 10 + #define A2W_PLLA_CCP2R_RESET 0000000000 +#define A2W_PLLA_MULTI HW_REGISTER_RW( 0x7e102f00 ) + #define A2W_PLLA_MULTI_MASK 0000000000 + #define A2W_PLLA_MULTI_WIDTH 0 + #define A2W_PLLA_MULTI_RESET 0000000000 +#define A2W_PLLC_CTRLR HW_REGISTER_RW( 0x7e102920 ) + #define A2W_PLLC_CTRLR_MASK 0x000373ff + #define A2W_PLLC_CTRLR_WIDTH 18 + #define A2W_PLLC_CTRLR_RESET 0000000000 +#define A2W_PLLC_FRACR HW_REGISTER_RW( 0x7e102a20 ) + #define A2W_PLLC_FRACR_MASK 0x000fffff + #define A2W_PLLC_FRACR_WIDTH 20 + #define A2W_PLLC_FRACR_RESET 0000000000 +#define A2W_PLLC_CORE2R HW_REGISTER_RW( 0x7e102b20 ) + #define A2W_PLLC_CORE2R_MASK 0x000003ff + #define A2W_PLLC_CORE2R_WIDTH 10 + #define A2W_PLLC_CORE2R_RESET 0000000000 +#define A2W_PLLC_CORE1R HW_REGISTER_RW( 0x7e102c20 ) + #define A2W_PLLC_CORE1R_MASK 0x000003ff + #define A2W_PLLC_CORE1R_WIDTH 10 + #define A2W_PLLC_CORE1R_RESET 0000000000 +#define A2W_PLLC_PERR HW_REGISTER_RW( 0x7e102d20 ) + #define A2W_PLLC_PERR_MASK 0x000003ff + #define A2W_PLLC_PERR_WIDTH 10 + #define A2W_PLLC_PERR_RESET 0000000000 +#define A2W_PLLC_CORE0R HW_REGISTER_RW( 0x7e102e20 ) + #define A2W_PLLC_CORE0R_MASK 0x000003ff + #define A2W_PLLC_CORE0R_WIDTH 10 + #define A2W_PLLC_CORE0R_RESET 0000000000 +#define A2W_PLLC_MULTI HW_REGISTER_RW( 0x7e102f20 ) + #define A2W_PLLC_MULTI_MASK 0000000000 + #define A2W_PLLC_MULTI_WIDTH 0 + #define A2W_PLLC_MULTI_RESET 0000000000 +#define A2W_PLLD_CTRLR HW_REGISTER_RW( 0x7e102940 ) + #define A2W_PLLD_CTRLR_MASK 0x000373ff + #define A2W_PLLD_CTRLR_WIDTH 18 + #define A2W_PLLD_CTRLR_RESET 0000000000 +#define A2W_PLLD_FRACR HW_REGISTER_RW( 0x7e102a40 ) + #define A2W_PLLD_FRACR_MASK 0x000fffff + #define A2W_PLLD_FRACR_WIDTH 20 + #define A2W_PLLD_FRACR_RESET 0000000000 +#define A2W_PLLD_DSI0R HW_REGISTER_RW( 0x7e102b40 ) + #define A2W_PLLD_DSI0R_MASK 0x000003ff + #define A2W_PLLD_DSI0R_WIDTH 10 + #define A2W_PLLD_DSI0R_RESET 0000000000 +#define A2W_PLLD_CORER HW_REGISTER_RW( 0x7e102c40 ) + #define A2W_PLLD_CORER_MASK 0x000003ff + #define A2W_PLLD_CORER_WIDTH 10 + #define A2W_PLLD_CORER_RESET 0000000000 +#define A2W_PLLD_PERR HW_REGISTER_RW( 0x7e102d40 ) + #define A2W_PLLD_PERR_MASK 0x000003ff + #define A2W_PLLD_PERR_WIDTH 10 + #define A2W_PLLD_PERR_RESET 0000000000 +#define A2W_PLLD_DSI1R HW_REGISTER_RW( 0x7e102e40 ) + #define A2W_PLLD_DSI1R_MASK 0x000003ff + #define A2W_PLLD_DSI1R_WIDTH 10 + #define A2W_PLLD_DSI1R_RESET 0000000000 +#define A2W_PLLD_MULTI HW_REGISTER_RW( 0x7e102f40 ) + #define A2W_PLLD_MULTI_MASK 0000000000 + #define A2W_PLLD_MULTI_WIDTH 0 + #define A2W_PLLD_MULTI_RESET 0000000000 +#define A2W_PLLH_CTRLR HW_REGISTER_RW( 0x7e102960 ) + #define A2W_PLLH_CTRLR_MASK 0x000370ff + #define A2W_PLLH_CTRLR_WIDTH 18 + #define A2W_PLLH_CTRLR_RESET 0000000000 +#define A2W_PLLH_FRACR HW_REGISTER_RW( 0x7e102a60 ) + #define A2W_PLLH_FRACR_MASK 0x000fffff + #define A2W_PLLH_FRACR_WIDTH 20 + #define A2W_PLLH_FRACR_RESET 0000000000 +#define A2W_PLLH_AUXR HW_REGISTER_RW( 0x7e102b60 ) + #define A2W_PLLH_AUXR_MASK 0x000003ff + #define A2W_PLLH_AUXR_WIDTH 10 + #define A2W_PLLH_AUXR_RESET 0000000000 +#define A2W_PLLH_RCALR HW_REGISTER_RW( 0x7e102c60 ) + #define A2W_PLLH_RCALR_MASK 0x000003ff + #define A2W_PLLH_RCALR_WIDTH 10 + #define A2W_PLLH_RCALR_RESET 0000000000 +#define A2W_PLLH_PIXR HW_REGISTER_RW( 0x7e102d60 ) + #define A2W_PLLH_PIXR_MASK 0x000003ff + #define A2W_PLLH_PIXR_WIDTH 10 + #define A2W_PLLH_PIXR_RESET 0000000000 +#define A2W_PLLH_STSR HW_REGISTER_RW( 0x7e102e60 ) + #define A2W_PLLH_STSR_MASK 0xffffffff + #define A2W_PLLH_STSR_WIDTH 32 + #define A2W_PLLH_STSR_RESET 0000000000 +#define A2W_XOSC_CTRLR HW_REGISTER_RW( 0x7e102990 ) + #define A2W_XOSC_CTRLR_MASK 0x0000037f + #define A2W_XOSC_CTRLR_WIDTH 10 + #define A2W_XOSC_CTRLR_RESET 0000000000 +#define A2W_PLLH_MULTI HW_REGISTER_RW( 0x7e102f60 ) + #define A2W_PLLH_MULTI_MASK 0000000000 + #define A2W_PLLH_MULTI_WIDTH 0 + #define A2W_PLLH_MULTI_RESET 0000000000 diff --git a/bcm2708_chip/cpr_clkman.h b/bcm2708_chip/cpr_clkman.h new file mode 100755 index 0000000..3e41465 --- /dev/null +++ b/bcm2708_chip/cpr_clkman.h @@ -0,0 +1,2400 @@ +// This file was generated by the create_regs script +#define CM_PASSWORD 0x5a000000 +#define CM_BASE 0x7e101000 +#define CM_APB_ID 0x0000636d +#define CM_GNRICCTL HW_REGISTER_RW( 0x7e101000 ) + #define CM_GNRICCTL_MASK 0x000fffff + #define CM_GNRICCTL_WIDTH 20 + #define CM_GNRICCTL_RESET 0000000000 + #define CM_GNRICCTL_FLIP_BITS 11:11 + #define CM_GNRICCTL_FLIP_SET 0x00000800 + #define CM_GNRICCTL_FLIP_CLR 0xfffff7ff + #define CM_GNRICCTL_FLIP_MSB 11 + #define CM_GNRICCTL_FLIP_LSB 11 + #define CM_GNRICCTL_MASH_BITS 10:9 + #define CM_GNRICCTL_MASH_SET 0x00000600 + #define CM_GNRICCTL_MASH_CLR 0xfffff9ff + #define CM_GNRICCTL_MASH_MSB 10 + #define CM_GNRICCTL_MASH_LSB 9 + #define CM_GNRICCTL_BUSYD_BITS 8:8 + #define CM_GNRICCTL_BUSYD_SET 0x00000100 + #define CM_GNRICCTL_BUSYD_CLR 0xfffffeff + #define CM_GNRICCTL_BUSYD_MSB 8 + #define CM_GNRICCTL_BUSYD_LSB 8 + #define CM_GNRICCTL_BUSY_BITS 7:7 + #define CM_GNRICCTL_BUSY_SET 0x00000080 + #define CM_GNRICCTL_BUSY_CLR 0xffffff7f + #define CM_GNRICCTL_BUSY_MSB 7 + #define CM_GNRICCTL_BUSY_LSB 7 + #define CM_GNRICCTL_GATE_BITS 6:6 + #define CM_GNRICCTL_GATE_SET 0x00000040 + #define CM_GNRICCTL_GATE_CLR 0xffffffbf + #define CM_GNRICCTL_GATE_MSB 6 + #define CM_GNRICCTL_GATE_LSB 6 + #define CM_GNRICCTL_KILL_BITS 5:5 + #define CM_GNRICCTL_KILL_SET 0x00000020 + #define CM_GNRICCTL_KILL_CLR 0xffffffdf + #define CM_GNRICCTL_KILL_MSB 5 + #define CM_GNRICCTL_KILL_LSB 5 + #define CM_GNRICCTL_ENAB_BITS 4:4 + #define CM_GNRICCTL_ENAB_SET 0x00000010 + #define CM_GNRICCTL_ENAB_CLR 0xffffffef + #define CM_GNRICCTL_ENAB_MSB 4 + #define CM_GNRICCTL_ENAB_LSB 4 + #define CM_GNRICCTL_SRC_BITS 3:0 + #define CM_GNRICCTL_SRC_SET 0x0000000f + #define CM_GNRICCTL_SRC_CLR 0xfffffff0 + #define CM_GNRICCTL_SRC_MSB 3 + #define CM_GNRICCTL_SRC_LSB 0 +#define CM_GNRICDIV HW_REGISTER_RW( 0x7e101004 ) + #define CM_GNRICDIV_MASK 0x00ffffff + #define CM_GNRICDIV_WIDTH 24 + #define CM_GNRICDIV_RESET 0000000000 + #define CM_GNRICDIV_DIV_BITS 23:0 + #define CM_GNRICDIV_DIV_SET 0x00ffffff + #define CM_GNRICDIV_DIV_CLR 0xff000000 + #define CM_GNRICDIV_DIV_MSB 23 + #define CM_GNRICDIV_DIV_LSB 0 +#define CM_VPUCTL HW_REGISTER_RW( 0x7e101008 ) + #define CM_VPUCTL_MASK 0x000003cf + #define CM_VPUCTL_WIDTH 10 + #define CM_VPUCTL_RESET 0x00000041 + #define CM_VPUCTL_FRAC_BITS 9:9 + #define CM_VPUCTL_FRAC_SET 0x00000200 + #define CM_VPUCTL_FRAC_CLR 0xfffffdff + #define CM_VPUCTL_FRAC_MSB 9 + #define CM_VPUCTL_FRAC_LSB 9 + #define CM_VPUCTL_BUSYD_BITS 8:8 + #define CM_VPUCTL_BUSYD_SET 0x00000100 + #define CM_VPUCTL_BUSYD_CLR 0xfffffeff + #define CM_VPUCTL_BUSYD_MSB 8 + #define CM_VPUCTL_BUSYD_LSB 8 + #define CM_VPUCTL_BUSY_BITS 7:7 + #define CM_VPUCTL_BUSY_SET 0x00000080 + #define CM_VPUCTL_BUSY_CLR 0xffffff7f + #define CM_VPUCTL_BUSY_MSB 7 + #define CM_VPUCTL_BUSY_LSB 7 + #define CM_VPUCTL_GATE_BITS 6:6 + #define CM_VPUCTL_GATE_SET 0x00000040 + #define CM_VPUCTL_GATE_CLR 0xffffffbf + #define CM_VPUCTL_GATE_MSB 6 + #define CM_VPUCTL_GATE_LSB 6 + #define CM_VPUCTL_SRC_BITS 3:0 + #define CM_VPUCTL_SRC_SET 0x0000000f + #define CM_VPUCTL_SRC_CLR 0xfffffff0 + #define CM_VPUCTL_SRC_MSB 3 + #define CM_VPUCTL_SRC_LSB 0 +#define CM_VPUDIV HW_REGISTER_RW( 0x7e10100c ) + #define CM_VPUDIV_MASK 0x00fffff0 + #define CM_VPUDIV_WIDTH 24 + #define CM_VPUDIV_RESET 0x00001000 + #define CM_VPUDIV_DIV_BITS 23:4 + #define CM_VPUDIV_DIV_SET 0x00fffff0 + #define CM_VPUDIV_DIV_CLR 0xff00000f + #define CM_VPUDIV_DIV_MSB 23 + #define CM_VPUDIV_DIV_LSB 4 +#define CM_SYSCTL HW_REGISTER_RW( 0x7e101010 ) + #define CM_SYSCTL_MASK 0x00000040 + #define CM_SYSCTL_WIDTH 7 + #define CM_SYSCTL_RESET 0x00000040 + #define CM_SYSCTL_GATE_BITS 6:6 + #define CM_SYSCTL_GATE_SET 0x00000040 + #define CM_SYSCTL_GATE_CLR 0xffffffbf + #define CM_SYSCTL_GATE_MSB 6 + #define CM_SYSCTL_GATE_LSB 6 +#define CM_SYSDIV HW_REGISTER_RO( 0x7e101014 ) + #define CM_SYSDIV_MASK 0x00001000 + #define CM_SYSDIV_WIDTH 13 + #define CM_SYSDIV_RESET 0x00001000 + #define CM_SYSDIV_DIV_BITS 12:12 + #define CM_SYSDIV_DIV_SET 0x00001000 + #define CM_SYSDIV_DIV_CLR 0xffffefff + #define CM_SYSDIV_DIV_MSB 12 + #define CM_SYSDIV_DIV_LSB 12 +#define CM_PERIACTL HW_REGISTER_RW( 0x7e101018 ) + #define CM_PERIACTL_MASK 0x00000040 + #define CM_PERIACTL_WIDTH 7 + #define CM_PERIACTL_RESET 0x00000040 + #define CM_PERIACTL_GATE_BITS 6:6 + #define CM_PERIACTL_GATE_SET 0x00000040 + #define CM_PERIACTL_GATE_CLR 0xffffffbf + #define CM_PERIACTL_GATE_MSB 6 + #define CM_PERIACTL_GATE_LSB 6 +#define CM_PERIADIV HW_REGISTER_RO( 0x7e10101c ) + #define CM_PERIADIV_MASK 0x00001000 + #define CM_PERIADIV_WIDTH 13 + #define CM_PERIADIV_RESET 0x00001000 + #define CM_PERIADIV_DIV_BITS 12:12 + #define CM_PERIADIV_DIV_SET 0x00001000 + #define CM_PERIADIV_DIV_CLR 0xffffefff + #define CM_PERIADIV_DIV_MSB 12 + #define CM_PERIADIV_DIV_LSB 12 +#define CM_PERIICTL HW_REGISTER_RW( 0x7e101020 ) + #define CM_PERIICTL_MASK 0x00000040 + #define CM_PERIICTL_WIDTH 7 + #define CM_PERIICTL_RESET 0000000000 + #define CM_PERIICTL_GATE_BITS 6:6 + #define CM_PERIICTL_GATE_SET 0x00000040 + #define CM_PERIICTL_GATE_CLR 0xffffffbf + #define CM_PERIICTL_GATE_MSB 6 + #define CM_PERIICTL_GATE_LSB 6 +#define CM_PERIIDIV HW_REGISTER_RO( 0x7e101024 ) + #define CM_PERIIDIV_MASK 0x00001000 + #define CM_PERIIDIV_WIDTH 13 + #define CM_PERIIDIV_RESET 0x00001000 + #define CM_PERIIDIV_DIV_BITS 12:12 + #define CM_PERIIDIV_DIV_SET 0x00001000 + #define CM_PERIIDIV_DIV_CLR 0xffffefff + #define CM_PERIIDIV_DIV_MSB 12 + #define CM_PERIIDIV_DIV_LSB 12 +#define CM_H264CTL HW_REGISTER_RW( 0x7e101028 ) + #define CM_H264CTL_MASK 0x000003ff + #define CM_H264CTL_WIDTH 10 + #define CM_H264CTL_RESET 0x00000040 + #define CM_H264CTL_FRAC_BITS 9:9 + #define CM_H264CTL_FRAC_SET 0x00000200 + #define CM_H264CTL_FRAC_CLR 0xfffffdff + #define CM_H264CTL_FRAC_MSB 9 + #define CM_H264CTL_FRAC_LSB 9 + #define CM_H264CTL_BUSYD_BITS 8:8 + #define CM_H264CTL_BUSYD_SET 0x00000100 + #define CM_H264CTL_BUSYD_CLR 0xfffffeff + #define CM_H264CTL_BUSYD_MSB 8 + #define CM_H264CTL_BUSYD_LSB 8 + #define CM_H264CTL_BUSY_BITS 7:7 + #define CM_H264CTL_BUSY_SET 0x00000080 + #define CM_H264CTL_BUSY_CLR 0xffffff7f + #define CM_H264CTL_BUSY_MSB 7 + #define CM_H264CTL_BUSY_LSB 7 + #define CM_H264CTL_GATE_BITS 6:6 + #define CM_H264CTL_GATE_SET 0x00000040 + #define CM_H264CTL_GATE_CLR 0xffffffbf + #define CM_H264CTL_GATE_MSB 6 + #define CM_H264CTL_GATE_LSB 6 + #define CM_H264CTL_KILL_BITS 5:5 + #define CM_H264CTL_KILL_SET 0x00000020 + #define CM_H264CTL_KILL_CLR 0xffffffdf + #define CM_H264CTL_KILL_MSB 5 + #define CM_H264CTL_KILL_LSB 5 + #define CM_H264CTL_ENAB_BITS 4:4 + #define CM_H264CTL_ENAB_SET 0x00000010 + #define CM_H264CTL_ENAB_CLR 0xffffffef + #define CM_H264CTL_ENAB_MSB 4 + #define CM_H264CTL_ENAB_LSB 4 + #define CM_H264CTL_SRC_BITS 3:0 + #define CM_H264CTL_SRC_SET 0x0000000f + #define CM_H264CTL_SRC_CLR 0xfffffff0 + #define CM_H264CTL_SRC_MSB 3 + #define CM_H264CTL_SRC_LSB 0 +#define CM_H264DIV HW_REGISTER_RW( 0x7e10102c ) + #define CM_H264DIV_MASK 0x0000fff0 + #define CM_H264DIV_WIDTH 16 + #define CM_H264DIV_RESET 0000000000 + #define CM_H264DIV_DIV_BITS 15:4 + #define CM_H264DIV_DIV_SET 0x0000fff0 + #define CM_H264DIV_DIV_CLR 0xffff000f + #define CM_H264DIV_DIV_MSB 15 + #define CM_H264DIV_DIV_LSB 4 +#define CM_ISPCTL HW_REGISTER_RW( 0x7e101030 ) + #define CM_ISPCTL_MASK 0x000003ff + #define CM_ISPCTL_WIDTH 10 + #define CM_ISPCTL_RESET 0x00000040 + #define CM_ISPCTL_FRAC_BITS 9:9 + #define CM_ISPCTL_FRAC_SET 0x00000200 + #define CM_ISPCTL_FRAC_CLR 0xfffffdff + #define CM_ISPCTL_FRAC_MSB 9 + #define CM_ISPCTL_FRAC_LSB 9 + #define CM_ISPCTL_BUSYD_BITS 8:8 + #define CM_ISPCTL_BUSYD_SET 0x00000100 + #define CM_ISPCTL_BUSYD_CLR 0xfffffeff + #define CM_ISPCTL_BUSYD_MSB 8 + #define CM_ISPCTL_BUSYD_LSB 8 + #define CM_ISPCTL_BUSY_BITS 7:7 + #define CM_ISPCTL_BUSY_SET 0x00000080 + #define CM_ISPCTL_BUSY_CLR 0xffffff7f + #define CM_ISPCTL_BUSY_MSB 7 + #define CM_ISPCTL_BUSY_LSB 7 + #define CM_ISPCTL_GATE_BITS 6:6 + #define CM_ISPCTL_GATE_SET 0x00000040 + #define CM_ISPCTL_GATE_CLR 0xffffffbf + #define CM_ISPCTL_GATE_MSB 6 + #define CM_ISPCTL_GATE_LSB 6 + #define CM_ISPCTL_KILL_BITS 5:5 + #define CM_ISPCTL_KILL_SET 0x00000020 + #define CM_ISPCTL_KILL_CLR 0xffffffdf + #define CM_ISPCTL_KILL_MSB 5 + #define CM_ISPCTL_KILL_LSB 5 + #define CM_ISPCTL_ENAB_BITS 4:4 + #define CM_ISPCTL_ENAB_SET 0x00000010 + #define CM_ISPCTL_ENAB_CLR 0xffffffef + #define CM_ISPCTL_ENAB_MSB 4 + #define CM_ISPCTL_ENAB_LSB 4 + #define CM_ISPCTL_SRC_BITS 3:0 + #define CM_ISPCTL_SRC_SET 0x0000000f + #define CM_ISPCTL_SRC_CLR 0xfffffff0 + #define CM_ISPCTL_SRC_MSB 3 + #define CM_ISPCTL_SRC_LSB 0 +#define CM_ISPDIV HW_REGISTER_RW( 0x7e101034 ) + #define CM_ISPDIV_MASK 0x0000fff0 + #define CM_ISPDIV_WIDTH 16 + #define CM_ISPDIV_RESET 0000000000 + #define CM_ISPDIV_DIV_BITS 15:4 + #define CM_ISPDIV_DIV_SET 0x0000fff0 + #define CM_ISPDIV_DIV_CLR 0xffff000f + #define CM_ISPDIV_DIV_MSB 15 + #define CM_ISPDIV_DIV_LSB 4 +#define CM_ARMCTL HW_REGISTER_RW( 0x7e1011b0 ) + #define CM_ARMCTL_MASK 0x000013bf + #define CM_ARMCTL_WIDTH 13 + #define CM_ARMCTL_RESET 0x00000004 + #define CM_ARMCTL_AXIHALF_BITS 12:12 + #define CM_ARMCTL_AXIHALF_SET 0x00001000 + #define CM_ARMCTL_AXIHALF_CLR 0xffffefff + #define CM_ARMCTL_AXIHALF_MSB 12 + #define CM_ARMCTL_AXIHALF_LSB 12 + #define CM_ARMCTL_FRAC_BITS 9:9 + #define CM_ARMCTL_FRAC_SET 0x00000200 + #define CM_ARMCTL_FRAC_CLR 0xfffffdff + #define CM_ARMCTL_FRAC_MSB 9 + #define CM_ARMCTL_FRAC_LSB 9 + #define CM_ARMCTL_BUSYD_BITS 8:8 + #define CM_ARMCTL_BUSYD_SET 0x00000100 + #define CM_ARMCTL_BUSYD_CLR 0xfffffeff + #define CM_ARMCTL_BUSYD_MSB 8 + #define CM_ARMCTL_BUSYD_LSB 8 + #define CM_ARMCTL_BUSY_BITS 7:7 + #define CM_ARMCTL_BUSY_SET 0x00000080 + #define CM_ARMCTL_BUSY_CLR 0xffffff7f + #define CM_ARMCTL_BUSY_MSB 7 + #define CM_ARMCTL_BUSY_LSB 7 + #define CM_ARMCTL_KILL_BITS 5:5 + #define CM_ARMCTL_KILL_SET 0x00000020 + #define CM_ARMCTL_KILL_CLR 0xffffffdf + #define CM_ARMCTL_KILL_MSB 5 + #define CM_ARMCTL_KILL_LSB 5 + #define CM_ARMCTL_ENAB_BITS 4:4 + #define CM_ARMCTL_ENAB_SET 0x00000010 + #define CM_ARMCTL_ENAB_CLR 0xffffffef + #define CM_ARMCTL_ENAB_MSB 4 + #define CM_ARMCTL_ENAB_LSB 4 + #define CM_ARMCTL_SRC_BITS 3:0 + #define CM_ARMCTL_SRC_SET 0x0000000f + #define CM_ARMCTL_SRC_CLR 0xfffffff0 + #define CM_ARMCTL_SRC_MSB 3 + #define CM_ARMCTL_SRC_LSB 0 +#define CM_ARMDIV HW_REGISTER_RO( 0x7e1011b4 ) + #define CM_ARMDIV_MASK 0x00001000 + #define CM_ARMDIV_WIDTH 13 + #define CM_ARMDIV_RESET 0x00001000 + #define CM_ARMDIV_DIV_BITS 12:12 + #define CM_ARMDIV_DIV_SET 0x00001000 + #define CM_ARMDIV_DIV_CLR 0xffffefff + #define CM_ARMDIV_DIV_MSB 12 + #define CM_ARMDIV_DIV_LSB 12 +#define CM_SDCCTL HW_REGISTER_RW( 0x7e1011a8 ) + #define CM_SDCCTL_MASK 0x0003f3bf + #define CM_SDCCTL_WIDTH 18 + #define CM_SDCCTL_RESET 0x00004000 + #define CM_SDCCTL_UPDATE_BITS 17:17 + #define CM_SDCCTL_UPDATE_SET 0x00020000 + #define CM_SDCCTL_UPDATE_CLR 0xfffdffff + #define CM_SDCCTL_UPDATE_MSB 17 + #define CM_SDCCTL_UPDATE_LSB 17 + #define CM_SDCCTL_ACCPT_BITS 16:16 + #define CM_SDCCTL_ACCPT_SET 0x00010000 + #define CM_SDCCTL_ACCPT_CLR 0xfffeffff + #define CM_SDCCTL_ACCPT_MSB 16 + #define CM_SDCCTL_ACCPT_LSB 16 + #define CM_SDCCTL_CTRL_BITS 15:12 + #define CM_SDCCTL_CTRL_SET 0x0000f000 + #define CM_SDCCTL_CTRL_CLR 0xffff0fff + #define CM_SDCCTL_CTRL_MSB 15 + #define CM_SDCCTL_CTRL_LSB 12 + #define CM_SDCCTL_FRAC_BITS 9:9 + #define CM_SDCCTL_FRAC_SET 0x00000200 + #define CM_SDCCTL_FRAC_CLR 0xfffffdff + #define CM_SDCCTL_FRAC_MSB 9 + #define CM_SDCCTL_FRAC_LSB 9 + #define CM_SDCCTL_BUSYD_BITS 8:8 + #define CM_SDCCTL_BUSYD_SET 0x00000100 + #define CM_SDCCTL_BUSYD_CLR 0xfffffeff + #define CM_SDCCTL_BUSYD_MSB 8 + #define CM_SDCCTL_BUSYD_LSB 8 + #define CM_SDCCTL_BUSY_BITS 7:7 + #define CM_SDCCTL_BUSY_SET 0x00000080 + #define CM_SDCCTL_BUSY_CLR 0xffffff7f + #define CM_SDCCTL_BUSY_MSB 7 + #define CM_SDCCTL_BUSY_LSB 7 + #define CM_SDCCTL_KILL_BITS 5:5 + #define CM_SDCCTL_KILL_SET 0x00000020 + #define CM_SDCCTL_KILL_CLR 0xffffffdf + #define CM_SDCCTL_KILL_MSB 5 + #define CM_SDCCTL_KILL_LSB 5 + #define CM_SDCCTL_ENAB_BITS 4:4 + #define CM_SDCCTL_ENAB_SET 0x00000010 + #define CM_SDCCTL_ENAB_CLR 0xffffffef + #define CM_SDCCTL_ENAB_MSB 4 + #define CM_SDCCTL_ENAB_LSB 4 + #define CM_SDCCTL_SRC_BITS 3:0 + #define CM_SDCCTL_SRC_SET 0x0000000f + #define CM_SDCCTL_SRC_CLR 0xfffffff0 + #define CM_SDCCTL_SRC_MSB 3 + #define CM_SDCCTL_SRC_LSB 0 +#define CM_SDCDIV HW_REGISTER_RW( 0x7e1011ac ) + #define CM_SDCDIV_MASK 0x0003f000 + #define CM_SDCDIV_WIDTH 18 + #define CM_SDCDIV_RESET 0000000000 + #define CM_SDCDIV_DIV_BITS 17:12 + #define CM_SDCDIV_DIV_SET 0x0003f000 + #define CM_SDCDIV_DIV_CLR 0xfffc0fff + #define CM_SDCDIV_DIV_MSB 17 + #define CM_SDCDIV_DIV_LSB 12 +#define CM_V3DCTL HW_REGISTER_RW( 0x7e101038 ) + #define CM_V3DCTL_MASK 0x000003ff + #define CM_V3DCTL_WIDTH 10 + #define CM_V3DCTL_RESET 0x00000040 + #define CM_V3DCTL_FRAC_BITS 9:9 + #define CM_V3DCTL_FRAC_SET 0x00000200 + #define CM_V3DCTL_FRAC_CLR 0xfffffdff + #define CM_V3DCTL_FRAC_MSB 9 + #define CM_V3DCTL_FRAC_LSB 9 + #define CM_V3DCTL_BUSYD_BITS 8:8 + #define CM_V3DCTL_BUSYD_SET 0x00000100 + #define CM_V3DCTL_BUSYD_CLR 0xfffffeff + #define CM_V3DCTL_BUSYD_MSB 8 + #define CM_V3DCTL_BUSYD_LSB 8 + #define CM_V3DCTL_BUSY_BITS 7:7 + #define CM_V3DCTL_BUSY_SET 0x00000080 + #define CM_V3DCTL_BUSY_CLR 0xffffff7f + #define CM_V3DCTL_BUSY_MSB 7 + #define CM_V3DCTL_BUSY_LSB 7 + #define CM_V3DCTL_GATE_BITS 6:6 + #define CM_V3DCTL_GATE_SET 0x00000040 + #define CM_V3DCTL_GATE_CLR 0xffffffbf + #define CM_V3DCTL_GATE_MSB 6 + #define CM_V3DCTL_GATE_LSB 6 + #define CM_V3DCTL_KILL_BITS 5:5 + #define CM_V3DCTL_KILL_SET 0x00000020 + #define CM_V3DCTL_KILL_CLR 0xffffffdf + #define CM_V3DCTL_KILL_MSB 5 + #define CM_V3DCTL_KILL_LSB 5 + #define CM_V3DCTL_ENAB_BITS 4:4 + #define CM_V3DCTL_ENAB_SET 0x00000010 + #define CM_V3DCTL_ENAB_CLR 0xffffffef + #define CM_V3DCTL_ENAB_MSB 4 + #define CM_V3DCTL_ENAB_LSB 4 + #define CM_V3DCTL_SRC_BITS 3:0 + #define CM_V3DCTL_SRC_SET 0x0000000f + #define CM_V3DCTL_SRC_CLR 0xfffffff0 + #define CM_V3DCTL_SRC_MSB 3 + #define CM_V3DCTL_SRC_LSB 0 +#define CM_V3DDIV HW_REGISTER_RW( 0x7e10103c ) + #define CM_V3DDIV_MASK 0x0000fff0 + #define CM_V3DDIV_WIDTH 16 + #define CM_V3DDIV_RESET 0000000000 + #define CM_V3DDIV_DIV_BITS 15:4 + #define CM_V3DDIV_DIV_SET 0x0000fff0 + #define CM_V3DDIV_DIV_CLR 0xffff000f + #define CM_V3DDIV_DIV_MSB 15 + #define CM_V3DDIV_DIV_LSB 4 +#define CM_CAM0CTL HW_REGISTER_RW( 0x7e101040 ) + #define CM_CAM0CTL_MASK 0x000003bf + #define CM_CAM0CTL_WIDTH 10 + #define CM_CAM0CTL_RESET 0000000000 + #define CM_CAM0CTL_FRAC_BITS 9:9 + #define CM_CAM0CTL_FRAC_SET 0x00000200 + #define CM_CAM0CTL_FRAC_CLR 0xfffffdff + #define CM_CAM0CTL_FRAC_MSB 9 + #define CM_CAM0CTL_FRAC_LSB 9 + #define CM_CAM0CTL_BUSYD_BITS 8:8 + #define CM_CAM0CTL_BUSYD_SET 0x00000100 + #define CM_CAM0CTL_BUSYD_CLR 0xfffffeff + #define CM_CAM0CTL_BUSYD_MSB 8 + #define CM_CAM0CTL_BUSYD_LSB 8 + #define CM_CAM0CTL_BUSY_BITS 7:7 + #define CM_CAM0CTL_BUSY_SET 0x00000080 + #define CM_CAM0CTL_BUSY_CLR 0xffffff7f + #define CM_CAM0CTL_BUSY_MSB 7 + #define CM_CAM0CTL_BUSY_LSB 7 + #define CM_CAM0CTL_KILL_BITS 5:5 + #define CM_CAM0CTL_KILL_SET 0x00000020 + #define CM_CAM0CTL_KILL_CLR 0xffffffdf + #define CM_CAM0CTL_KILL_MSB 5 + #define CM_CAM0CTL_KILL_LSB 5 + #define CM_CAM0CTL_ENAB_BITS 4:4 + #define CM_CAM0CTL_ENAB_SET 0x00000010 + #define CM_CAM0CTL_ENAB_CLR 0xffffffef + #define CM_CAM0CTL_ENAB_MSB 4 + #define CM_CAM0CTL_ENAB_LSB 4 + #define CM_CAM0CTL_SRC_BITS 3:0 + #define CM_CAM0CTL_SRC_SET 0x0000000f + #define CM_CAM0CTL_SRC_CLR 0xfffffff0 + #define CM_CAM0CTL_SRC_MSB 3 + #define CM_CAM0CTL_SRC_LSB 0 +#define CM_CAM0DIV HW_REGISTER_RW( 0x7e101044 ) + #define CM_CAM0DIV_MASK 0x0000fff0 + #define CM_CAM0DIV_WIDTH 16 + #define CM_CAM0DIV_RESET 0000000000 + #define CM_CAM0DIV_DIV_BITS 15:4 + #define CM_CAM0DIV_DIV_SET 0x0000fff0 + #define CM_CAM0DIV_DIV_CLR 0xffff000f + #define CM_CAM0DIV_DIV_MSB 15 + #define CM_CAM0DIV_DIV_LSB 4 +#define CM_CAM1CTL HW_REGISTER_RW( 0x7e101048 ) + #define CM_CAM1CTL_MASK 0x000003bf + #define CM_CAM1CTL_WIDTH 10 + #define CM_CAM1CTL_RESET 0000000000 + #define CM_CAM1CTL_FRAC_BITS 9:9 + #define CM_CAM1CTL_FRAC_SET 0x00000200 + #define CM_CAM1CTL_FRAC_CLR 0xfffffdff + #define CM_CAM1CTL_FRAC_MSB 9 + #define CM_CAM1CTL_FRAC_LSB 9 + #define CM_CAM1CTL_BUSYD_BITS 8:8 + #define CM_CAM1CTL_BUSYD_SET 0x00000100 + #define CM_CAM1CTL_BUSYD_CLR 0xfffffeff + #define CM_CAM1CTL_BUSYD_MSB 8 + #define CM_CAM1CTL_BUSYD_LSB 8 + #define CM_CAM1CTL_BUSY_BITS 7:7 + #define CM_CAM1CTL_BUSY_SET 0x00000080 + #define CM_CAM1CTL_BUSY_CLR 0xffffff7f + #define CM_CAM1CTL_BUSY_MSB 7 + #define CM_CAM1CTL_BUSY_LSB 7 + #define CM_CAM1CTL_KILL_BITS 5:5 + #define CM_CAM1CTL_KILL_SET 0x00000020 + #define CM_CAM1CTL_KILL_CLR 0xffffffdf + #define CM_CAM1CTL_KILL_MSB 5 + #define CM_CAM1CTL_KILL_LSB 5 + #define CM_CAM1CTL_ENAB_BITS 4:4 + #define CM_CAM1CTL_ENAB_SET 0x00000010 + #define CM_CAM1CTL_ENAB_CLR 0xffffffef + #define CM_CAM1CTL_ENAB_MSB 4 + #define CM_CAM1CTL_ENAB_LSB 4 + #define CM_CAM1CTL_SRC_BITS 3:0 + #define CM_CAM1CTL_SRC_SET 0x0000000f + #define CM_CAM1CTL_SRC_CLR 0xfffffff0 + #define CM_CAM1CTL_SRC_MSB 3 + #define CM_CAM1CTL_SRC_LSB 0 +#define CM_CAM1DIV HW_REGISTER_RW( 0x7e10104c ) + #define CM_CAM1DIV_MASK 0x0000fff0 + #define CM_CAM1DIV_WIDTH 16 + #define CM_CAM1DIV_RESET 0000000000 + #define CM_CAM1DIV_DIV_BITS 15:4 + #define CM_CAM1DIV_DIV_SET 0x0000fff0 + #define CM_CAM1DIV_DIV_CLR 0xffff000f + #define CM_CAM1DIV_DIV_MSB 15 + #define CM_CAM1DIV_DIV_LSB 4 +#define CM_CCP2CTL HW_REGISTER_RW( 0x7e101050 ) + #define CM_CCP2CTL_MASK 0x00000397 + #define CM_CCP2CTL_WIDTH 10 + #define CM_CCP2CTL_RESET 0000000000 + #define CM_CCP2CTL_FRAC_BITS 9:9 + #define CM_CCP2CTL_FRAC_SET 0x00000200 + #define CM_CCP2CTL_FRAC_CLR 0xfffffdff + #define CM_CCP2CTL_FRAC_MSB 9 + #define CM_CCP2CTL_FRAC_LSB 9 + #define CM_CCP2CTL_BUSYD_BITS 8:8 + #define CM_CCP2CTL_BUSYD_SET 0x00000100 + #define CM_CCP2CTL_BUSYD_CLR 0xfffffeff + #define CM_CCP2CTL_BUSYD_MSB 8 + #define CM_CCP2CTL_BUSYD_LSB 8 + #define CM_CCP2CTL_BUSY_BITS 7:7 + #define CM_CCP2CTL_BUSY_SET 0x00000080 + #define CM_CCP2CTL_BUSY_CLR 0xffffff7f + #define CM_CCP2CTL_BUSY_MSB 7 + #define CM_CCP2CTL_BUSY_LSB 7 + #define CM_CCP2CTL_ENAB_BITS 4:4 + #define CM_CCP2CTL_ENAB_SET 0x00000010 + #define CM_CCP2CTL_ENAB_CLR 0xffffffef + #define CM_CCP2CTL_ENAB_MSB 4 + #define CM_CCP2CTL_ENAB_LSB 4 + #define CM_CCP2CTL_SRC_BITS 2:0 + #define CM_CCP2CTL_SRC_SET 0x00000007 + #define CM_CCP2CTL_SRC_CLR 0xfffffff8 + #define CM_CCP2CTL_SRC_MSB 2 + #define CM_CCP2CTL_SRC_LSB 0 +#define CM_CCP2DIV HW_REGISTER_RO( 0x7e101054 ) + #define CM_CCP2DIV_MASK 0x00001000 + #define CM_CCP2DIV_WIDTH 13 + #define CM_CCP2DIV_RESET 0x00001000 + #define CM_CCP2DIV_DIV_BITS 12:12 + #define CM_CCP2DIV_DIV_SET 0x00001000 + #define CM_CCP2DIV_DIV_CLR 0xffffefff + #define CM_CCP2DIV_DIV_MSB 12 + #define CM_CCP2DIV_DIV_LSB 12 +#define CM_DSI0ECTL HW_REGISTER_RW( 0x7e101058 ) + #define CM_DSI0ECTL_MASK 0x000003bf + #define CM_DSI0ECTL_WIDTH 10 + #define CM_DSI0ECTL_RESET 0000000000 + #define CM_DSI0ECTL_FRAC_BITS 9:9 + #define CM_DSI0ECTL_FRAC_SET 0x00000200 + #define CM_DSI0ECTL_FRAC_CLR 0xfffffdff + #define CM_DSI0ECTL_FRAC_MSB 9 + #define CM_DSI0ECTL_FRAC_LSB 9 + #define CM_DSI0ECTL_BUSYD_BITS 8:8 + #define CM_DSI0ECTL_BUSYD_SET 0x00000100 + #define CM_DSI0ECTL_BUSYD_CLR 0xfffffeff + #define CM_DSI0ECTL_BUSYD_MSB 8 + #define CM_DSI0ECTL_BUSYD_LSB 8 + #define CM_DSI0ECTL_BUSY_BITS 7:7 + #define CM_DSI0ECTL_BUSY_SET 0x00000080 + #define CM_DSI0ECTL_BUSY_CLR 0xffffff7f + #define CM_DSI0ECTL_BUSY_MSB 7 + #define CM_DSI0ECTL_BUSY_LSB 7 + #define CM_DSI0ECTL_KILL_BITS 5:5 + #define CM_DSI0ECTL_KILL_SET 0x00000020 + #define CM_DSI0ECTL_KILL_CLR 0xffffffdf + #define CM_DSI0ECTL_KILL_MSB 5 + #define CM_DSI0ECTL_KILL_LSB 5 + #define CM_DSI0ECTL_ENAB_BITS 4:4 + #define CM_DSI0ECTL_ENAB_SET 0x00000010 + #define CM_DSI0ECTL_ENAB_CLR 0xffffffef + #define CM_DSI0ECTL_ENAB_MSB 4 + #define CM_DSI0ECTL_ENAB_LSB 4 + #define CM_DSI0ECTL_SRC_BITS 3:0 + #define CM_DSI0ECTL_SRC_SET 0x0000000f + #define CM_DSI0ECTL_SRC_CLR 0xfffffff0 + #define CM_DSI0ECTL_SRC_MSB 3 + #define CM_DSI0ECTL_SRC_LSB 0 +#define CM_DSI0EDIV HW_REGISTER_RW( 0x7e10105c ) + #define CM_DSI0EDIV_MASK 0x0000fff0 + #define CM_DSI0EDIV_WIDTH 16 + #define CM_DSI0EDIV_RESET 0000000000 + #define CM_DSI0EDIV_DIV_BITS 15:4 + #define CM_DSI0EDIV_DIV_SET 0x0000fff0 + #define CM_DSI0EDIV_DIV_CLR 0xffff000f + #define CM_DSI0EDIV_DIV_MSB 15 + #define CM_DSI0EDIV_DIV_LSB 4 +#define CM_DSI0PCTL HW_REGISTER_RW( 0x7e101060 ) + #define CM_DSI0PCTL_MASK 0x0000039f + #define CM_DSI0PCTL_WIDTH 10 + #define CM_DSI0PCTL_RESET 0000000000 + #define CM_DSI0PCTL_FRAC_BITS 9:9 + #define CM_DSI0PCTL_FRAC_SET 0x00000200 + #define CM_DSI0PCTL_FRAC_CLR 0xfffffdff + #define CM_DSI0PCTL_FRAC_MSB 9 + #define CM_DSI0PCTL_FRAC_LSB 9 + #define CM_DSI0PCTL_BUSYD_BITS 8:8 + #define CM_DSI0PCTL_BUSYD_SET 0x00000100 + #define CM_DSI0PCTL_BUSYD_CLR 0xfffffeff + #define CM_DSI0PCTL_BUSYD_MSB 8 + #define CM_DSI0PCTL_BUSYD_LSB 8 + #define CM_DSI0PCTL_BUSY_BITS 7:7 + #define CM_DSI0PCTL_BUSY_SET 0x00000080 + #define CM_DSI0PCTL_BUSY_CLR 0xffffff7f + #define CM_DSI0PCTL_BUSY_MSB 7 + #define CM_DSI0PCTL_BUSY_LSB 7 + #define CM_DSI0PCTL_ENAB_BITS 4:4 + #define CM_DSI0PCTL_ENAB_SET 0x00000010 + #define CM_DSI0PCTL_ENAB_CLR 0xffffffef + #define CM_DSI0PCTL_ENAB_MSB 4 + #define CM_DSI0PCTL_ENAB_LSB 4 + #define CM_DSI0PCTL_SRC_BITS 3:0 + #define CM_DSI0PCTL_SRC_SET 0x0000000f + #define CM_DSI0PCTL_SRC_CLR 0xfffffff0 + #define CM_DSI0PCTL_SRC_MSB 3 + #define CM_DSI0PCTL_SRC_LSB 0 +#define CM_DSI0PDIV HW_REGISTER_RO( 0x7e101064 ) + #define CM_DSI0PDIV_MASK 0x00001000 + #define CM_DSI0PDIV_WIDTH 13 + #define CM_DSI0PDIV_RESET 0x00001000 + #define CM_DSI0PDIV_DIV_BITS 12:12 + #define CM_DSI0PDIV_DIV_SET 0x00001000 + #define CM_DSI0PDIV_DIV_CLR 0xffffefff + #define CM_DSI0PDIV_DIV_MSB 12 + #define CM_DSI0PDIV_DIV_LSB 12 +#define CM_DSI1ECTL HW_REGISTER_RW( 0x7e101158 ) + #define CM_DSI1ECTL_MASK 0x000003bf + #define CM_DSI1ECTL_WIDTH 10 + #define CM_DSI1ECTL_RESET 0000000000 + #define CM_DSI1ECTL_FRAC_BITS 9:9 + #define CM_DSI1ECTL_FRAC_SET 0x00000200 + #define CM_DSI1ECTL_FRAC_CLR 0xfffffdff + #define CM_DSI1ECTL_FRAC_MSB 9 + #define CM_DSI1ECTL_FRAC_LSB 9 + #define CM_DSI1ECTL_BUSYD_BITS 8:8 + #define CM_DSI1ECTL_BUSYD_SET 0x00000100 + #define CM_DSI1ECTL_BUSYD_CLR 0xfffffeff + #define CM_DSI1ECTL_BUSYD_MSB 8 + #define CM_DSI1ECTL_BUSYD_LSB 8 + #define CM_DSI1ECTL_BUSY_BITS 7:7 + #define CM_DSI1ECTL_BUSY_SET 0x00000080 + #define CM_DSI1ECTL_BUSY_CLR 0xffffff7f + #define CM_DSI1ECTL_BUSY_MSB 7 + #define CM_DSI1ECTL_BUSY_LSB 7 + #define CM_DSI1ECTL_KILL_BITS 5:5 + #define CM_DSI1ECTL_KILL_SET 0x00000020 + #define CM_DSI1ECTL_KILL_CLR 0xffffffdf + #define CM_DSI1ECTL_KILL_MSB 5 + #define CM_DSI1ECTL_KILL_LSB 5 + #define CM_DSI1ECTL_ENAB_BITS 4:4 + #define CM_DSI1ECTL_ENAB_SET 0x00000010 + #define CM_DSI1ECTL_ENAB_CLR 0xffffffef + #define CM_DSI1ECTL_ENAB_MSB 4 + #define CM_DSI1ECTL_ENAB_LSB 4 + #define CM_DSI1ECTL_SRC_BITS 3:0 + #define CM_DSI1ECTL_SRC_SET 0x0000000f + #define CM_DSI1ECTL_SRC_CLR 0xfffffff0 + #define CM_DSI1ECTL_SRC_MSB 3 + #define CM_DSI1ECTL_SRC_LSB 0 +#define CM_DSI1EDIV HW_REGISTER_RW( 0x7e10115c ) + #define CM_DSI1EDIV_MASK 0x0000fff0 + #define CM_DSI1EDIV_WIDTH 16 + #define CM_DSI1EDIV_RESET 0000000000 + #define CM_DSI1EDIV_DIV_BITS 15:4 + #define CM_DSI1EDIV_DIV_SET 0x0000fff0 + #define CM_DSI1EDIV_DIV_CLR 0xffff000f + #define CM_DSI1EDIV_DIV_MSB 15 + #define CM_DSI1EDIV_DIV_LSB 4 +#define CM_DSI1PCTL HW_REGISTER_RW( 0x7e101160 ) + #define CM_DSI1PCTL_MASK 0x0000039f + #define CM_DSI1PCTL_WIDTH 10 + #define CM_DSI1PCTL_RESET 0000000000 + #define CM_DSI1PCTL_FRAC_BITS 9:9 + #define CM_DSI1PCTL_FRAC_SET 0x00000200 + #define CM_DSI1PCTL_FRAC_CLR 0xfffffdff + #define CM_DSI1PCTL_FRAC_MSB 9 + #define CM_DSI1PCTL_FRAC_LSB 9 + #define CM_DSI1PCTL_BUSYD_BITS 8:8 + #define CM_DSI1PCTL_BUSYD_SET 0x00000100 + #define CM_DSI1PCTL_BUSYD_CLR 0xfffffeff + #define CM_DSI1PCTL_BUSYD_MSB 8 + #define CM_DSI1PCTL_BUSYD_LSB 8 + #define CM_DSI1PCTL_BUSY_BITS 7:7 + #define CM_DSI1PCTL_BUSY_SET 0x00000080 + #define CM_DSI1PCTL_BUSY_CLR 0xffffff7f + #define CM_DSI1PCTL_BUSY_MSB 7 + #define CM_DSI1PCTL_BUSY_LSB 7 + #define CM_DSI1PCTL_ENAB_BITS 4:4 + #define CM_DSI1PCTL_ENAB_SET 0x00000010 + #define CM_DSI1PCTL_ENAB_CLR 0xffffffef + #define CM_DSI1PCTL_ENAB_MSB 4 + #define CM_DSI1PCTL_ENAB_LSB 4 + #define CM_DSI1PCTL_SRC_BITS 3:0 + #define CM_DSI1PCTL_SRC_SET 0x0000000f + #define CM_DSI1PCTL_SRC_CLR 0xfffffff0 + #define CM_DSI1PCTL_SRC_MSB 3 + #define CM_DSI1PCTL_SRC_LSB 0 +#define CM_DSI1PDIV HW_REGISTER_RO( 0x7e101164 ) + #define CM_DSI1PDIV_MASK 0x00001000 + #define CM_DSI1PDIV_WIDTH 13 + #define CM_DSI1PDIV_RESET 0x00001000 + #define CM_DSI1PDIV_DIV_BITS 12:12 + #define CM_DSI1PDIV_DIV_SET 0x00001000 + #define CM_DSI1PDIV_DIV_CLR 0xffffefff + #define CM_DSI1PDIV_DIV_MSB 12 + #define CM_DSI1PDIV_DIV_LSB 12 +#define CM_DPICTL HW_REGISTER_RW( 0x7e101068 ) + #define CM_DPICTL_MASK 0x000003bf + #define CM_DPICTL_WIDTH 10 + #define CM_DPICTL_RESET 0000000000 + #define CM_DPICTL_FRAC_BITS 9:9 + #define CM_DPICTL_FRAC_SET 0x00000200 + #define CM_DPICTL_FRAC_CLR 0xfffffdff + #define CM_DPICTL_FRAC_MSB 9 + #define CM_DPICTL_FRAC_LSB 9 + #define CM_DPICTL_BUSYD_BITS 8:8 + #define CM_DPICTL_BUSYD_SET 0x00000100 + #define CM_DPICTL_BUSYD_CLR 0xfffffeff + #define CM_DPICTL_BUSYD_MSB 8 + #define CM_DPICTL_BUSYD_LSB 8 + #define CM_DPICTL_BUSY_BITS 7:7 + #define CM_DPICTL_BUSY_SET 0x00000080 + #define CM_DPICTL_BUSY_CLR 0xffffff7f + #define CM_DPICTL_BUSY_MSB 7 + #define CM_DPICTL_BUSY_LSB 7 + #define CM_DPICTL_KILL_BITS 5:5 + #define CM_DPICTL_KILL_SET 0x00000020 + #define CM_DPICTL_KILL_CLR 0xffffffdf + #define CM_DPICTL_KILL_MSB 5 + #define CM_DPICTL_KILL_LSB 5 + #define CM_DPICTL_ENAB_BITS 4:4 + #define CM_DPICTL_ENAB_SET 0x00000010 + #define CM_DPICTL_ENAB_CLR 0xffffffef + #define CM_DPICTL_ENAB_MSB 4 + #define CM_DPICTL_ENAB_LSB 4 + #define CM_DPICTL_SRC_BITS 3:0 + #define CM_DPICTL_SRC_SET 0x0000000f + #define CM_DPICTL_SRC_CLR 0xfffffff0 + #define CM_DPICTL_SRC_MSB 3 + #define CM_DPICTL_SRC_LSB 0 +#define CM_DPIDIV HW_REGISTER_RW( 0x7e10106c ) + #define CM_DPIDIV_MASK 0x0000fff0 + #define CM_DPIDIV_WIDTH 16 + #define CM_DPIDIV_RESET 0000000000 + #define CM_DPIDIV_DIV_BITS 15:4 + #define CM_DPIDIV_DIV_SET 0x0000fff0 + #define CM_DPIDIV_DIV_CLR 0xffff000f + #define CM_DPIDIV_DIV_MSB 15 + #define CM_DPIDIV_DIV_LSB 4 +#define CM_DFTCTL HW_REGISTER_RW( 0x7e101168 ) + #define CM_DFTCTL_MASK 0x000003bf + #define CM_DFTCTL_WIDTH 10 + #define CM_DFTCTL_RESET 0000000000 + #define CM_DFTCTL_FRAC_BITS 9:9 + #define CM_DFTCTL_FRAC_SET 0x00000200 + #define CM_DFTCTL_FRAC_CLR 0xfffffdff + #define CM_DFTCTL_FRAC_MSB 9 + #define CM_DFTCTL_FRAC_LSB 9 + #define CM_DFTCTL_BUSYD_BITS 8:8 + #define CM_DFTCTL_BUSYD_SET 0x00000100 + #define CM_DFTCTL_BUSYD_CLR 0xfffffeff + #define CM_DFTCTL_BUSYD_MSB 8 + #define CM_DFTCTL_BUSYD_LSB 8 + #define CM_DFTCTL_BUSY_BITS 7:7 + #define CM_DFTCTL_BUSY_SET 0x00000080 + #define CM_DFTCTL_BUSY_CLR 0xffffff7f + #define CM_DFTCTL_BUSY_MSB 7 + #define CM_DFTCTL_BUSY_LSB 7 + #define CM_DFTCTL_KILL_BITS 5:5 + #define CM_DFTCTL_KILL_SET 0x00000020 + #define CM_DFTCTL_KILL_CLR 0xffffffdf + #define CM_DFTCTL_KILL_MSB 5 + #define CM_DFTCTL_KILL_LSB 5 + #define CM_DFTCTL_ENAB_BITS 4:4 + #define CM_DFTCTL_ENAB_SET 0x00000010 + #define CM_DFTCTL_ENAB_CLR 0xffffffef + #define CM_DFTCTL_ENAB_MSB 4 + #define CM_DFTCTL_ENAB_LSB 4 + #define CM_DFTCTL_SRC_BITS 3:0 + #define CM_DFTCTL_SRC_SET 0x0000000f + #define CM_DFTCTL_SRC_CLR 0xfffffff0 + #define CM_DFTCTL_SRC_MSB 3 + #define CM_DFTCTL_SRC_LSB 0 +#define CM_DFTDIV HW_REGISTER_RW( 0x7e10116c ) + #define CM_DFTDIV_MASK 0x0001f000 + #define CM_DFTDIV_WIDTH 17 + #define CM_DFTDIV_RESET 0000000000 + #define CM_DFTDIV_DIV_BITS 16:12 + #define CM_DFTDIV_DIV_SET 0x0001f000 + #define CM_DFTDIV_DIV_CLR 0xfffe0fff + #define CM_DFTDIV_DIV_MSB 16 + #define CM_DFTDIV_DIV_LSB 12 +#define CM_GP0CTL HW_REGISTER_RW( 0x7e101070 ) + #define CM_GP0CTL_MASK 0x000007bf + #define CM_GP0CTL_WIDTH 11 + #define CM_GP0CTL_RESET 0x00000200 + #define CM_GP0CTL_MASH_BITS 10:9 + #define CM_GP0CTL_MASH_SET 0x00000600 + #define CM_GP0CTL_MASH_CLR 0xfffff9ff + #define CM_GP0CTL_MASH_MSB 10 + #define CM_GP0CTL_MASH_LSB 9 + #define CM_GP0CTL_BUSYD_BITS 8:8 + #define CM_GP0CTL_BUSYD_SET 0x00000100 + #define CM_GP0CTL_BUSYD_CLR 0xfffffeff + #define CM_GP0CTL_BUSYD_MSB 8 + #define CM_GP0CTL_BUSYD_LSB 8 + #define CM_GP0CTL_BUSY_BITS 7:7 + #define CM_GP0CTL_BUSY_SET 0x00000080 + #define CM_GP0CTL_BUSY_CLR 0xffffff7f + #define CM_GP0CTL_BUSY_MSB 7 + #define CM_GP0CTL_BUSY_LSB 7 + #define CM_GP0CTL_KILL_BITS 5:5 + #define CM_GP0CTL_KILL_SET 0x00000020 + #define CM_GP0CTL_KILL_CLR 0xffffffdf + #define CM_GP0CTL_KILL_MSB 5 + #define CM_GP0CTL_KILL_LSB 5 + #define CM_GP0CTL_ENAB_BITS 4:4 + #define CM_GP0CTL_ENAB_SET 0x00000010 + #define CM_GP0CTL_ENAB_CLR 0xffffffef + #define CM_GP0CTL_ENAB_MSB 4 + #define CM_GP0CTL_ENAB_LSB 4 + #define CM_GP0CTL_SRC_BITS 3:0 + #define CM_GP0CTL_SRC_SET 0x0000000f + #define CM_GP0CTL_SRC_CLR 0xfffffff0 + #define CM_GP0CTL_SRC_MSB 3 + #define CM_GP0CTL_SRC_LSB 0 +#define CM_GP0DIV HW_REGISTER_RW( 0x7e101074 ) + #define CM_GP0DIV_MASK 0x00ffffff + #define CM_GP0DIV_WIDTH 24 + #define CM_GP0DIV_RESET 0000000000 + #define CM_GP0DIV_DIV_BITS 23:0 + #define CM_GP0DIV_DIV_SET 0x00ffffff + #define CM_GP0DIV_DIV_CLR 0xff000000 + #define CM_GP0DIV_DIV_MSB 23 + #define CM_GP0DIV_DIV_LSB 0 +#define CM_GP1CTL HW_REGISTER_RW( 0x7e101078 ) + #define CM_GP1CTL_MASK 0x000007bf + #define CM_GP1CTL_WIDTH 11 + #define CM_GP1CTL_RESET 0x00000200 + #define CM_GP1CTL_MASH_BITS 10:9 + #define CM_GP1CTL_MASH_SET 0x00000600 + #define CM_GP1CTL_MASH_CLR 0xfffff9ff + #define CM_GP1CTL_MASH_MSB 10 + #define CM_GP1CTL_MASH_LSB 9 + #define CM_GP1CTL_BUSYD_BITS 8:8 + #define CM_GP1CTL_BUSYD_SET 0x00000100 + #define CM_GP1CTL_BUSYD_CLR 0xfffffeff + #define CM_GP1CTL_BUSYD_MSB 8 + #define CM_GP1CTL_BUSYD_LSB 8 + #define CM_GP1CTL_BUSY_BITS 7:7 + #define CM_GP1CTL_BUSY_SET 0x00000080 + #define CM_GP1CTL_BUSY_CLR 0xffffff7f + #define CM_GP1CTL_BUSY_MSB 7 + #define CM_GP1CTL_BUSY_LSB 7 + #define CM_GP1CTL_KILL_BITS 5:5 + #define CM_GP1CTL_KILL_SET 0x00000020 + #define CM_GP1CTL_KILL_CLR 0xffffffdf + #define CM_GP1CTL_KILL_MSB 5 + #define CM_GP1CTL_KILL_LSB 5 + #define CM_GP1CTL_ENAB_BITS 4:4 + #define CM_GP1CTL_ENAB_SET 0x00000010 + #define CM_GP1CTL_ENAB_CLR 0xffffffef + #define CM_GP1CTL_ENAB_MSB 4 + #define CM_GP1CTL_ENAB_LSB 4 + #define CM_GP1CTL_SRC_BITS 3:0 + #define CM_GP1CTL_SRC_SET 0x0000000f + #define CM_GP1CTL_SRC_CLR 0xfffffff0 + #define CM_GP1CTL_SRC_MSB 3 + #define CM_GP1CTL_SRC_LSB 0 +#define CM_GP1DIV HW_REGISTER_RW( 0x7e10107c ) + #define CM_GP1DIV_MASK 0x00ffffff + #define CM_GP1DIV_WIDTH 24 + #define CM_GP1DIV_RESET 0000000000 + #define CM_GP1DIV_DIV_BITS 23:0 + #define CM_GP1DIV_DIV_SET 0x00ffffff + #define CM_GP1DIV_DIV_CLR 0xff000000 + #define CM_GP1DIV_DIV_MSB 23 + #define CM_GP1DIV_DIV_LSB 0 +#define CM_GP2CTL HW_REGISTER_RW( 0x7e101080 ) + #define CM_GP2CTL_MASK 0x000003bf + #define CM_GP2CTL_WIDTH 10 + #define CM_GP2CTL_RESET 0000000000 + #define CM_GP2CTL_FRAC_BITS 9:9 + #define CM_GP2CTL_FRAC_SET 0x00000200 + #define CM_GP2CTL_FRAC_CLR 0xfffffdff + #define CM_GP2CTL_FRAC_MSB 9 + #define CM_GP2CTL_FRAC_LSB 9 + #define CM_GP2CTL_BUSYD_BITS 8:8 + #define CM_GP2CTL_BUSYD_SET 0x00000100 + #define CM_GP2CTL_BUSYD_CLR 0xfffffeff + #define CM_GP2CTL_BUSYD_MSB 8 + #define CM_GP2CTL_BUSYD_LSB 8 + #define CM_GP2CTL_BUSY_BITS 7:7 + #define CM_GP2CTL_BUSY_SET 0x00000080 + #define CM_GP2CTL_BUSY_CLR 0xffffff7f + #define CM_GP2CTL_BUSY_MSB 7 + #define CM_GP2CTL_BUSY_LSB 7 + #define CM_GP2CTL_KILL_BITS 5:5 + #define CM_GP2CTL_KILL_SET 0x00000020 + #define CM_GP2CTL_KILL_CLR 0xffffffdf + #define CM_GP2CTL_KILL_MSB 5 + #define CM_GP2CTL_KILL_LSB 5 + #define CM_GP2CTL_ENAB_BITS 4:4 + #define CM_GP2CTL_ENAB_SET 0x00000010 + #define CM_GP2CTL_ENAB_CLR 0xffffffef + #define CM_GP2CTL_ENAB_MSB 4 + #define CM_GP2CTL_ENAB_LSB 4 + #define CM_GP2CTL_SRC_BITS 3:0 + #define CM_GP2CTL_SRC_SET 0x0000000f + #define CM_GP2CTL_SRC_CLR 0xfffffff0 + #define CM_GP2CTL_SRC_MSB 3 + #define CM_GP2CTL_SRC_LSB 0 +#define CM_GP2DIV HW_REGISTER_RW( 0x7e101084 ) + #define CM_GP2DIV_MASK 0x00ffffff + #define CM_GP2DIV_WIDTH 24 + #define CM_GP2DIV_RESET 0000000000 + #define CM_GP2DIV_DIV_BITS 23:0 + #define CM_GP2DIV_DIV_SET 0x00ffffff + #define CM_GP2DIV_DIV_CLR 0xff000000 + #define CM_GP2DIV_DIV_MSB 23 + #define CM_GP2DIV_DIV_LSB 0 +#define CM_HSMCTL HW_REGISTER_RW( 0x7e101088 ) + #define CM_HSMCTL_MASK 0x000003ff + #define CM_HSMCTL_WIDTH 10 + #define CM_HSMCTL_RESET 0000000000 + #define CM_HSMCTL_FRAC_BITS 9:9 + #define CM_HSMCTL_FRAC_SET 0x00000200 + #define CM_HSMCTL_FRAC_CLR 0xfffffdff + #define CM_HSMCTL_FRAC_MSB 9 + #define CM_HSMCTL_FRAC_LSB 9 + #define CM_HSMCTL_BUSYD_BITS 8:8 + #define CM_HSMCTL_BUSYD_SET 0x00000100 + #define CM_HSMCTL_BUSYD_CLR 0xfffffeff + #define CM_HSMCTL_BUSYD_MSB 8 + #define CM_HSMCTL_BUSYD_LSB 8 + #define CM_HSMCTL_BUSY_BITS 7:7 + #define CM_HSMCTL_BUSY_SET 0x00000080 + #define CM_HSMCTL_BUSY_CLR 0xffffff7f + #define CM_HSMCTL_BUSY_MSB 7 + #define CM_HSMCTL_BUSY_LSB 7 + #define CM_HSMCTL_GATE_BITS 6:6 + #define CM_HSMCTL_GATE_SET 0x00000040 + #define CM_HSMCTL_GATE_CLR 0xffffffbf + #define CM_HSMCTL_GATE_MSB 6 + #define CM_HSMCTL_GATE_LSB 6 + #define CM_HSMCTL_KILL_BITS 5:5 + #define CM_HSMCTL_KILL_SET 0x00000020 + #define CM_HSMCTL_KILL_CLR 0xffffffdf + #define CM_HSMCTL_KILL_MSB 5 + #define CM_HSMCTL_KILL_LSB 5 + #define CM_HSMCTL_ENAB_BITS 4:4 + #define CM_HSMCTL_ENAB_SET 0x00000010 + #define CM_HSMCTL_ENAB_CLR 0xffffffef + #define CM_HSMCTL_ENAB_MSB 4 + #define CM_HSMCTL_ENAB_LSB 4 + #define CM_HSMCTL_SRC_BITS 3:0 + #define CM_HSMCTL_SRC_SET 0x0000000f + #define CM_HSMCTL_SRC_CLR 0xfffffff0 + #define CM_HSMCTL_SRC_MSB 3 + #define CM_HSMCTL_SRC_LSB 0 +#define CM_HSMDIV HW_REGISTER_RW( 0x7e10108c ) + #define CM_HSMDIV_MASK 0x0000fff0 + #define CM_HSMDIV_WIDTH 16 + #define CM_HSMDIV_RESET 0000000000 + #define CM_HSMDIV_DIV_BITS 15:4 + #define CM_HSMDIV_DIV_SET 0x0000fff0 + #define CM_HSMDIV_DIV_CLR 0xffff000f + #define CM_HSMDIV_DIV_MSB 15 + #define CM_HSMDIV_DIV_LSB 4 +#define CM_OTPCTL HW_REGISTER_RW( 0x7e101090 ) + #define CM_OTPCTL_MASK 0x000003b3 + #define CM_OTPCTL_WIDTH 10 + #define CM_OTPCTL_RESET 0x00000011 + #define CM_OTPCTL_FRAC_BITS 9:9 + #define CM_OTPCTL_FRAC_SET 0x00000200 + #define CM_OTPCTL_FRAC_CLR 0xfffffdff + #define CM_OTPCTL_FRAC_MSB 9 + #define CM_OTPCTL_FRAC_LSB 9 + #define CM_OTPCTL_BUSYD_BITS 8:8 + #define CM_OTPCTL_BUSYD_SET 0x00000100 + #define CM_OTPCTL_BUSYD_CLR 0xfffffeff + #define CM_OTPCTL_BUSYD_MSB 8 + #define CM_OTPCTL_BUSYD_LSB 8 + #define CM_OTPCTL_BUSY_BITS 7:7 + #define CM_OTPCTL_BUSY_SET 0x00000080 + #define CM_OTPCTL_BUSY_CLR 0xffffff7f + #define CM_OTPCTL_BUSY_MSB 7 + #define CM_OTPCTL_BUSY_LSB 7 + #define CM_OTPCTL_KILL_BITS 5:5 + #define CM_OTPCTL_KILL_SET 0x00000020 + #define CM_OTPCTL_KILL_CLR 0xffffffdf + #define CM_OTPCTL_KILL_MSB 5 + #define CM_OTPCTL_KILL_LSB 5 + #define CM_OTPCTL_ENAB_BITS 4:4 + #define CM_OTPCTL_ENAB_SET 0x00000010 + #define CM_OTPCTL_ENAB_CLR 0xffffffef + #define CM_OTPCTL_ENAB_MSB 4 + #define CM_OTPCTL_ENAB_LSB 4 + #define CM_OTPCTL_SRC_BITS 1:0 + #define CM_OTPCTL_SRC_SET 0x00000003 + #define CM_OTPCTL_SRC_CLR 0xfffffffc + #define CM_OTPCTL_SRC_MSB 1 + #define CM_OTPCTL_SRC_LSB 0 +#define CM_OTPDIV HW_REGISTER_RW( 0x7e101094 ) + #define CM_OTPDIV_MASK 0x0001f000 + #define CM_OTPDIV_WIDTH 17 + #define CM_OTPDIV_RESET 0x00004000 + #define CM_OTPDIV_DIV_BITS 16:12 + #define CM_OTPDIV_DIV_SET 0x0001f000 + #define CM_OTPDIV_DIV_CLR 0xfffe0fff + #define CM_OTPDIV_DIV_MSB 16 + #define CM_OTPDIV_DIV_LSB 12 +#define CM_PULSECTL HW_REGISTER_RW( 0x7e101190 ) + #define CM_PULSECTL_MASK 0x000003b3 + #define CM_PULSECTL_WIDTH 10 + #define CM_PULSECTL_RESET 0x00000011 + #define CM_PULSECTL_FRAC_BITS 9:9 + #define CM_PULSECTL_FRAC_SET 0x00000200 + #define CM_PULSECTL_FRAC_CLR 0xfffffdff + #define CM_PULSECTL_FRAC_MSB 9 + #define CM_PULSECTL_FRAC_LSB 9 + #define CM_PULSECTL_BUSYD_BITS 8:8 + #define CM_PULSECTL_BUSYD_SET 0x00000100 + #define CM_PULSECTL_BUSYD_CLR 0xfffffeff + #define CM_PULSECTL_BUSYD_MSB 8 + #define CM_PULSECTL_BUSYD_LSB 8 + #define CM_PULSECTL_BUSY_BITS 7:7 + #define CM_PULSECTL_BUSY_SET 0x00000080 + #define CM_PULSECTL_BUSY_CLR 0xffffff7f + #define CM_PULSECTL_BUSY_MSB 7 + #define CM_PULSECTL_BUSY_LSB 7 + #define CM_PULSECTL_KILL_BITS 5:5 + #define CM_PULSECTL_KILL_SET 0x00000020 + #define CM_PULSECTL_KILL_CLR 0xffffffdf + #define CM_PULSECTL_KILL_MSB 5 + #define CM_PULSECTL_KILL_LSB 5 + #define CM_PULSECTL_ENAB_BITS 4:4 + #define CM_PULSECTL_ENAB_SET 0x00000010 + #define CM_PULSECTL_ENAB_CLR 0xffffffef + #define CM_PULSECTL_ENAB_MSB 4 + #define CM_PULSECTL_ENAB_LSB 4 + #define CM_PULSECTL_SRC_BITS 1:0 + #define CM_PULSECTL_SRC_SET 0x00000003 + #define CM_PULSECTL_SRC_CLR 0xfffffffc + #define CM_PULSECTL_SRC_MSB 1 + #define CM_PULSECTL_SRC_LSB 0 +#define CM_PULSEDIV HW_REGISTER_RW( 0x7e101194 ) + #define CM_PULSEDIV_MASK 0x00fff000 + #define CM_PULSEDIV_WIDTH 24 + #define CM_PULSEDIV_RESET 0x0001b000 + #define CM_PULSEDIV_DIV_BITS 23:12 + #define CM_PULSEDIV_DIV_SET 0x00fff000 + #define CM_PULSEDIV_DIV_CLR 0xff000fff + #define CM_PULSEDIV_DIV_MSB 23 + #define CM_PULSEDIV_DIV_LSB 12 +#define CM_PCMCTL HW_REGISTER_RW( 0x7e101098 ) + #define CM_PCMCTL_MASK 0x000007bf + #define CM_PCMCTL_WIDTH 11 + #define CM_PCMCTL_RESET 0x00000200 + #define CM_PCMCTL_MASH_BITS 10:9 + #define CM_PCMCTL_MASH_SET 0x00000600 + #define CM_PCMCTL_MASH_CLR 0xfffff9ff + #define CM_PCMCTL_MASH_MSB 10 + #define CM_PCMCTL_MASH_LSB 9 + #define CM_PCMCTL_BUSYD_BITS 8:8 + #define CM_PCMCTL_BUSYD_SET 0x00000100 + #define CM_PCMCTL_BUSYD_CLR 0xfffffeff + #define CM_PCMCTL_BUSYD_MSB 8 + #define CM_PCMCTL_BUSYD_LSB 8 + #define CM_PCMCTL_BUSY_BITS 7:7 + #define CM_PCMCTL_BUSY_SET 0x00000080 + #define CM_PCMCTL_BUSY_CLR 0xffffff7f + #define CM_PCMCTL_BUSY_MSB 7 + #define CM_PCMCTL_BUSY_LSB 7 + #define CM_PCMCTL_KILL_BITS 5:5 + #define CM_PCMCTL_KILL_SET 0x00000020 + #define CM_PCMCTL_KILL_CLR 0xffffffdf + #define CM_PCMCTL_KILL_MSB 5 + #define CM_PCMCTL_KILL_LSB 5 + #define CM_PCMCTL_ENAB_BITS 4:4 + #define CM_PCMCTL_ENAB_SET 0x00000010 + #define CM_PCMCTL_ENAB_CLR 0xffffffef + #define CM_PCMCTL_ENAB_MSB 4 + #define CM_PCMCTL_ENAB_LSB 4 + #define CM_PCMCTL_SRC_BITS 3:0 + #define CM_PCMCTL_SRC_SET 0x0000000f + #define CM_PCMCTL_SRC_CLR 0xfffffff0 + #define CM_PCMCTL_SRC_MSB 3 + #define CM_PCMCTL_SRC_LSB 0 +#define CM_PCMDIV HW_REGISTER_RW( 0x7e10109c ) + #define CM_PCMDIV_MASK 0x00ffffff + #define CM_PCMDIV_WIDTH 24 + #define CM_PCMDIV_RESET 0000000000 + #define CM_PCMDIV_DIV_BITS 23:0 + #define CM_PCMDIV_DIV_SET 0x00ffffff + #define CM_PCMDIV_DIV_CLR 0xff000000 + #define CM_PCMDIV_DIV_MSB 23 + #define CM_PCMDIV_DIV_LSB 0 +#define CM_PWMCTL HW_REGISTER_RW( 0x7e1010a0 ) + #define CM_PWMCTL_MASK 0x000007bf + #define CM_PWMCTL_WIDTH 11 + #define CM_PWMCTL_RESET 0x00000200 + #define CM_PWMCTL_MASH_BITS 10:9 + #define CM_PWMCTL_MASH_SET 0x00000600 + #define CM_PWMCTL_MASH_CLR 0xfffff9ff + #define CM_PWMCTL_MASH_MSB 10 + #define CM_PWMCTL_MASH_LSB 9 + #define CM_PWMCTL_BUSYD_BITS 8:8 + #define CM_PWMCTL_BUSYD_SET 0x00000100 + #define CM_PWMCTL_BUSYD_CLR 0xfffffeff + #define CM_PWMCTL_BUSYD_MSB 8 + #define CM_PWMCTL_BUSYD_LSB 8 + #define CM_PWMCTL_BUSY_BITS 7:7 + #define CM_PWMCTL_BUSY_SET 0x00000080 + #define CM_PWMCTL_BUSY_CLR 0xffffff7f + #define CM_PWMCTL_BUSY_MSB 7 + #define CM_PWMCTL_BUSY_LSB 7 + #define CM_PWMCTL_KILL_BITS 5:5 + #define CM_PWMCTL_KILL_SET 0x00000020 + #define CM_PWMCTL_KILL_CLR 0xffffffdf + #define CM_PWMCTL_KILL_MSB 5 + #define CM_PWMCTL_KILL_LSB 5 + #define CM_PWMCTL_ENAB_BITS 4:4 + #define CM_PWMCTL_ENAB_SET 0x00000010 + #define CM_PWMCTL_ENAB_CLR 0xffffffef + #define CM_PWMCTL_ENAB_MSB 4 + #define CM_PWMCTL_ENAB_LSB 4 + #define CM_PWMCTL_SRC_BITS 3:0 + #define CM_PWMCTL_SRC_SET 0x0000000f + #define CM_PWMCTL_SRC_CLR 0xfffffff0 + #define CM_PWMCTL_SRC_MSB 3 + #define CM_PWMCTL_SRC_LSB 0 +#define CM_PWMDIV HW_REGISTER_RW( 0x7e1010a4 ) + #define CM_PWMDIV_MASK 0x00ffffff + #define CM_PWMDIV_WIDTH 24 + #define CM_PWMDIV_RESET 0000000000 + #define CM_PWMDIV_DIV_BITS 23:0 + #define CM_PWMDIV_DIV_SET 0x00ffffff + #define CM_PWMDIV_DIV_CLR 0xff000000 + #define CM_PWMDIV_DIV_MSB 23 + #define CM_PWMDIV_DIV_LSB 0 +#define CM_SLIMCTL HW_REGISTER_RW( 0x7e1010a8 ) + #define CM_SLIMCTL_MASK 0x000007bf + #define CM_SLIMCTL_WIDTH 11 + #define CM_SLIMCTL_RESET 0x00000200 + #define CM_SLIMCTL_MASH_BITS 10:9 + #define CM_SLIMCTL_MASH_SET 0x00000600 + #define CM_SLIMCTL_MASH_CLR 0xfffff9ff + #define CM_SLIMCTL_MASH_MSB 10 + #define CM_SLIMCTL_MASH_LSB 9 + #define CM_SLIMCTL_BUSYD_BITS 8:8 + #define CM_SLIMCTL_BUSYD_SET 0x00000100 + #define CM_SLIMCTL_BUSYD_CLR 0xfffffeff + #define CM_SLIMCTL_BUSYD_MSB 8 + #define CM_SLIMCTL_BUSYD_LSB 8 + #define CM_SLIMCTL_BUSY_BITS 7:7 + #define CM_SLIMCTL_BUSY_SET 0x00000080 + #define CM_SLIMCTL_BUSY_CLR 0xffffff7f + #define CM_SLIMCTL_BUSY_MSB 7 + #define CM_SLIMCTL_BUSY_LSB 7 + #define CM_SLIMCTL_KILL_BITS 5:5 + #define CM_SLIMCTL_KILL_SET 0x00000020 + #define CM_SLIMCTL_KILL_CLR 0xffffffdf + #define CM_SLIMCTL_KILL_MSB 5 + #define CM_SLIMCTL_KILL_LSB 5 + #define CM_SLIMCTL_ENAB_BITS 4:4 + #define CM_SLIMCTL_ENAB_SET 0x00000010 + #define CM_SLIMCTL_ENAB_CLR 0xffffffef + #define CM_SLIMCTL_ENAB_MSB 4 + #define CM_SLIMCTL_ENAB_LSB 4 + #define CM_SLIMCTL_SRC_BITS 3:0 + #define CM_SLIMCTL_SRC_SET 0x0000000f + #define CM_SLIMCTL_SRC_CLR 0xfffffff0 + #define CM_SLIMCTL_SRC_MSB 3 + #define CM_SLIMCTL_SRC_LSB 0 +#define CM_SLIMDIV HW_REGISTER_RW( 0x7e1010ac ) + #define CM_SLIMDIV_MASK 0x00ffffff + #define CM_SLIMDIV_WIDTH 24 + #define CM_SLIMDIV_RESET 0000000000 + #define CM_SLIMDIV_DIV_BITS 23:0 + #define CM_SLIMDIV_DIV_SET 0x00ffffff + #define CM_SLIMDIV_DIV_CLR 0xff000000 + #define CM_SLIMDIV_DIV_MSB 23 + #define CM_SLIMDIV_DIV_LSB 0 +#define CM_SMICTL HW_REGISTER_RW( 0x7e1010b0 ) + #define CM_SMICTL_MASK 0x000003bf + #define CM_SMICTL_WIDTH 10 + #define CM_SMICTL_RESET 0000000000 + #define CM_SMICTL_FRAC_BITS 9:9 + #define CM_SMICTL_FRAC_SET 0x00000200 + #define CM_SMICTL_FRAC_CLR 0xfffffdff + #define CM_SMICTL_FRAC_MSB 9 + #define CM_SMICTL_FRAC_LSB 9 + #define CM_SMICTL_BUSYD_BITS 8:8 + #define CM_SMICTL_BUSYD_SET 0x00000100 + #define CM_SMICTL_BUSYD_CLR 0xfffffeff + #define CM_SMICTL_BUSYD_MSB 8 + #define CM_SMICTL_BUSYD_LSB 8 + #define CM_SMICTL_BUSY_BITS 7:7 + #define CM_SMICTL_BUSY_SET 0x00000080 + #define CM_SMICTL_BUSY_CLR 0xffffff7f + #define CM_SMICTL_BUSY_MSB 7 + #define CM_SMICTL_BUSY_LSB 7 + #define CM_SMICTL_KILL_BITS 5:5 + #define CM_SMICTL_KILL_SET 0x00000020 + #define CM_SMICTL_KILL_CLR 0xffffffdf + #define CM_SMICTL_KILL_MSB 5 + #define CM_SMICTL_KILL_LSB 5 + #define CM_SMICTL_ENAB_BITS 4:4 + #define CM_SMICTL_ENAB_SET 0x00000010 + #define CM_SMICTL_ENAB_CLR 0xffffffef + #define CM_SMICTL_ENAB_MSB 4 + #define CM_SMICTL_ENAB_LSB 4 + #define CM_SMICTL_SRC_BITS 3:0 + #define CM_SMICTL_SRC_SET 0x0000000f + #define CM_SMICTL_SRC_CLR 0xfffffff0 + #define CM_SMICTL_SRC_MSB 3 + #define CM_SMICTL_SRC_LSB 0 +#define CM_SMIDIV HW_REGISTER_RW( 0x7e1010b4 ) + #define CM_SMIDIV_MASK 0x0000fff0 + #define CM_SMIDIV_WIDTH 16 + #define CM_SMIDIV_RESET 0000000000 + #define CM_SMIDIV_DIV_BITS 15:4 + #define CM_SMIDIV_DIV_SET 0x0000fff0 + #define CM_SMIDIV_DIV_CLR 0xffff000f + #define CM_SMIDIV_DIV_MSB 15 + #define CM_SMIDIV_DIV_LSB 4 +#define CM_TCNTCTL HW_REGISTER_RW( 0x7e1010c0 ) + #define CM_TCNTCTL_MASK 0x000030cf + #define CM_TCNTCTL_WIDTH 14 + #define CM_TCNTCTL_RESET 0000000000 + #define CM_TCNTCTL_SRC1_BITS 13:12 + #define CM_TCNTCTL_SRC1_SET 0x00003000 + #define CM_TCNTCTL_SRC1_CLR 0xffffcfff + #define CM_TCNTCTL_SRC1_MSB 13 + #define CM_TCNTCTL_SRC1_LSB 12 + #define CM_TCNTCTL_BUSY_BITS 7:7 + #define CM_TCNTCTL_BUSY_SET 0x00000080 + #define CM_TCNTCTL_BUSY_CLR 0xffffff7f + #define CM_TCNTCTL_BUSY_MSB 7 + #define CM_TCNTCTL_BUSY_LSB 7 + #define CM_TCNTCTL_KILL_BITS 6:6 + #define CM_TCNTCTL_KILL_SET 0x00000040 + #define CM_TCNTCTL_KILL_CLR 0xffffffbf + #define CM_TCNTCTL_KILL_MSB 6 + #define CM_TCNTCTL_KILL_LSB 6 + #define CM_TCNTCTL_SRC0_BITS 3:0 + #define CM_TCNTCTL_SRC0_SET 0x0000000f + #define CM_TCNTCTL_SRC0_CLR 0xfffffff0 + #define CM_TCNTCTL_SRC0_MSB 3 + #define CM_TCNTCTL_SRC0_LSB 0 +#define CM_TCNTCNT HW_REGISTER_RW( 0x7e1010c4 ) + #define CM_TCNTCNT_MASK 0x00ffffff + #define CM_TCNTCNT_WIDTH 24 + #define CM_TCNTCNT_RESET 0000000000 + #define CM_TCNTCNT_CNT_BITS 23:0 + #define CM_TCNTCNT_CNT_SET 0x00ffffff + #define CM_TCNTCNT_CNT_CLR 0xff000000 + #define CM_TCNTCNT_CNT_MSB 23 + #define CM_TCNTCNT_CNT_LSB 0 +#define CM_TECCTL HW_REGISTER_RW( 0x7e1010c8 ) + #define CM_TECCTL_MASK 0x000003b3 + #define CM_TECCTL_WIDTH 10 + #define CM_TECCTL_RESET 0000000000 + #define CM_TECCTL_FRAC_BITS 9:9 + #define CM_TECCTL_FRAC_SET 0x00000200 + #define CM_TECCTL_FRAC_CLR 0xfffffdff + #define CM_TECCTL_FRAC_MSB 9 + #define CM_TECCTL_FRAC_LSB 9 + #define CM_TECCTL_BUSYD_BITS 8:8 + #define CM_TECCTL_BUSYD_SET 0x00000100 + #define CM_TECCTL_BUSYD_CLR 0xfffffeff + #define CM_TECCTL_BUSYD_MSB 8 + #define CM_TECCTL_BUSYD_LSB 8 + #define CM_TECCTL_BUSY_BITS 7:7 + #define CM_TECCTL_BUSY_SET 0x00000080 + #define CM_TECCTL_BUSY_CLR 0xffffff7f + #define CM_TECCTL_BUSY_MSB 7 + #define CM_TECCTL_BUSY_LSB 7 + #define CM_TECCTL_KILL_BITS 5:5 + #define CM_TECCTL_KILL_SET 0x00000020 + #define CM_TECCTL_KILL_CLR 0xffffffdf + #define CM_TECCTL_KILL_MSB 5 + #define CM_TECCTL_KILL_LSB 5 + #define CM_TECCTL_ENAB_BITS 4:4 + #define CM_TECCTL_ENAB_SET 0x00000010 + #define CM_TECCTL_ENAB_CLR 0xffffffef + #define CM_TECCTL_ENAB_MSB 4 + #define CM_TECCTL_ENAB_LSB 4 + #define CM_TECCTL_SRC_BITS 1:0 + #define CM_TECCTL_SRC_SET 0x00000003 + #define CM_TECCTL_SRC_CLR 0xfffffffc + #define CM_TECCTL_SRC_MSB 1 + #define CM_TECCTL_SRC_LSB 0 +#define CM_TECDIV HW_REGISTER_RW( 0x7e1010cc ) + #define CM_TECDIV_MASK 0x0003f000 + #define CM_TECDIV_WIDTH 18 + #define CM_TECDIV_RESET 0000000000 + #define CM_TECDIV_DIV_BITS 17:12 + #define CM_TECDIV_DIV_SET 0x0003f000 + #define CM_TECDIV_DIV_CLR 0xfffc0fff + #define CM_TECDIV_DIV_MSB 17 + #define CM_TECDIV_DIV_LSB 12 +#define CM_TD0CTL HW_REGISTER_RW( 0x7e1010d0 ) + #define CM_TD0CTL_MASK 0x00001bff + #define CM_TD0CTL_WIDTH 13 + #define CM_TD0CTL_RESET 0000000000 + #define CM_TD0CTL_STEP_BITS 12:12 + #define CM_TD0CTL_STEP_SET 0x00001000 + #define CM_TD0CTL_STEP_CLR 0xffffefff + #define CM_TD0CTL_STEP_MSB 12 + #define CM_TD0CTL_STEP_LSB 12 + #define CM_TD0CTL_FLIP_BITS 11:11 + #define CM_TD0CTL_FLIP_SET 0x00000800 + #define CM_TD0CTL_FLIP_CLR 0xfffff7ff + #define CM_TD0CTL_FLIP_MSB 11 + #define CM_TD0CTL_FLIP_LSB 11 + #define CM_TD0CTL_FRAC_BITS 9:9 + #define CM_TD0CTL_FRAC_SET 0x00000200 + #define CM_TD0CTL_FRAC_CLR 0xfffffdff + #define CM_TD0CTL_FRAC_MSB 9 + #define CM_TD0CTL_FRAC_LSB 9 + #define CM_TD0CTL_BUSYD_BITS 8:8 + #define CM_TD0CTL_BUSYD_SET 0x00000100 + #define CM_TD0CTL_BUSYD_CLR 0xfffffeff + #define CM_TD0CTL_BUSYD_MSB 8 + #define CM_TD0CTL_BUSYD_LSB 8 + #define CM_TD0CTL_BUSY_BITS 7:7 + #define CM_TD0CTL_BUSY_SET 0x00000080 + #define CM_TD0CTL_BUSY_CLR 0xffffff7f + #define CM_TD0CTL_BUSY_MSB 7 + #define CM_TD0CTL_BUSY_LSB 7 + #define CM_TD0CTL_GATE_BITS 6:6 + #define CM_TD0CTL_GATE_SET 0x00000040 + #define CM_TD0CTL_GATE_CLR 0xffffffbf + #define CM_TD0CTL_GATE_MSB 6 + #define CM_TD0CTL_GATE_LSB 6 + #define CM_TD0CTL_KILL_BITS 5:5 + #define CM_TD0CTL_KILL_SET 0x00000020 + #define CM_TD0CTL_KILL_CLR 0xffffffdf + #define CM_TD0CTL_KILL_MSB 5 + #define CM_TD0CTL_KILL_LSB 5 + #define CM_TD0CTL_ENAB_BITS 4:4 + #define CM_TD0CTL_ENAB_SET 0x00000010 + #define CM_TD0CTL_ENAB_CLR 0xffffffef + #define CM_TD0CTL_ENAB_MSB 4 + #define CM_TD0CTL_ENAB_LSB 4 + #define CM_TD0CTL_SRC_BITS 3:0 + #define CM_TD0CTL_SRC_SET 0x0000000f + #define CM_TD0CTL_SRC_CLR 0xfffffff0 + #define CM_TD0CTL_SRC_MSB 3 + #define CM_TD0CTL_SRC_LSB 0 +#define CM_TD0DIV HW_REGISTER_RW( 0x7e1010d4 ) + #define CM_TD0DIV_MASK 0x00ffffff + #define CM_TD0DIV_WIDTH 24 + #define CM_TD0DIV_RESET 0000000000 + #define CM_TD0DIV_DIV_BITS 23:0 + #define CM_TD0DIV_DIV_SET 0x00ffffff + #define CM_TD0DIV_DIV_CLR 0xff000000 + #define CM_TD0DIV_DIV_MSB 23 + #define CM_TD0DIV_DIV_LSB 0 +#define CM_TD1CTL HW_REGISTER_RW( 0x7e1010d8 ) + #define CM_TD1CTL_MASK 0x00001bff + #define CM_TD1CTL_WIDTH 13 + #define CM_TD1CTL_RESET 0000000000 + #define CM_TD1CTL_STEP_BITS 12:12 + #define CM_TD1CTL_STEP_SET 0x00001000 + #define CM_TD1CTL_STEP_CLR 0xffffefff + #define CM_TD1CTL_STEP_MSB 12 + #define CM_TD1CTL_STEP_LSB 12 + #define CM_TD1CTL_FLIP_BITS 11:11 + #define CM_TD1CTL_FLIP_SET 0x00000800 + #define CM_TD1CTL_FLIP_CLR 0xfffff7ff + #define CM_TD1CTL_FLIP_MSB 11 + #define CM_TD1CTL_FLIP_LSB 11 + #define CM_TD1CTL_FRAC_BITS 9:9 + #define CM_TD1CTL_FRAC_SET 0x00000200 + #define CM_TD1CTL_FRAC_CLR 0xfffffdff + #define CM_TD1CTL_FRAC_MSB 9 + #define CM_TD1CTL_FRAC_LSB 9 + #define CM_TD1CTL_BUSYD_BITS 8:8 + #define CM_TD1CTL_BUSYD_SET 0x00000100 + #define CM_TD1CTL_BUSYD_CLR 0xfffffeff + #define CM_TD1CTL_BUSYD_MSB 8 + #define CM_TD1CTL_BUSYD_LSB 8 + #define CM_TD1CTL_BUSY_BITS 7:7 + #define CM_TD1CTL_BUSY_SET 0x00000080 + #define CM_TD1CTL_BUSY_CLR 0xffffff7f + #define CM_TD1CTL_BUSY_MSB 7 + #define CM_TD1CTL_BUSY_LSB 7 + #define CM_TD1CTL_GATE_BITS 6:6 + #define CM_TD1CTL_GATE_SET 0x00000040 + #define CM_TD1CTL_GATE_CLR 0xffffffbf + #define CM_TD1CTL_GATE_MSB 6 + #define CM_TD1CTL_GATE_LSB 6 + #define CM_TD1CTL_KILL_BITS 5:5 + #define CM_TD1CTL_KILL_SET 0x00000020 + #define CM_TD1CTL_KILL_CLR 0xffffffdf + #define CM_TD1CTL_KILL_MSB 5 + #define CM_TD1CTL_KILL_LSB 5 + #define CM_TD1CTL_ENAB_BITS 4:4 + #define CM_TD1CTL_ENAB_SET 0x00000010 + #define CM_TD1CTL_ENAB_CLR 0xffffffef + #define CM_TD1CTL_ENAB_MSB 4 + #define CM_TD1CTL_ENAB_LSB 4 + #define CM_TD1CTL_SRC_BITS 3:0 + #define CM_TD1CTL_SRC_SET 0x0000000f + #define CM_TD1CTL_SRC_CLR 0xfffffff0 + #define CM_TD1CTL_SRC_MSB 3 + #define CM_TD1CTL_SRC_LSB 0 +#define CM_TD1DIV HW_REGISTER_RW( 0x7e1010dc ) + #define CM_TD1DIV_MASK 0x00ffffff + #define CM_TD1DIV_WIDTH 24 + #define CM_TD1DIV_RESET 0000000000 + #define CM_TD1DIV_DIV_BITS 23:0 + #define CM_TD1DIV_DIV_SET 0x00ffffff + #define CM_TD1DIV_DIV_CLR 0xff000000 + #define CM_TD1DIV_DIV_MSB 23 + #define CM_TD1DIV_DIV_LSB 0 +#define CM_TSENSCTL HW_REGISTER_RW( 0x7e1010e0 ) + #define CM_TSENSCTL_MASK 0x000003b3 + #define CM_TSENSCTL_WIDTH 10 + #define CM_TSENSCTL_RESET 0000000000 + #define CM_TSENSCTL_FRAC_BITS 9:9 + #define CM_TSENSCTL_FRAC_SET 0x00000200 + #define CM_TSENSCTL_FRAC_CLR 0xfffffdff + #define CM_TSENSCTL_FRAC_MSB 9 + #define CM_TSENSCTL_FRAC_LSB 9 + #define CM_TSENSCTL_BUSYD_BITS 8:8 + #define CM_TSENSCTL_BUSYD_SET 0x00000100 + #define CM_TSENSCTL_BUSYD_CLR 0xfffffeff + #define CM_TSENSCTL_BUSYD_MSB 8 + #define CM_TSENSCTL_BUSYD_LSB 8 + #define CM_TSENSCTL_BUSY_BITS 7:7 + #define CM_TSENSCTL_BUSY_SET 0x00000080 + #define CM_TSENSCTL_BUSY_CLR 0xffffff7f + #define CM_TSENSCTL_BUSY_MSB 7 + #define CM_TSENSCTL_BUSY_LSB 7 + #define CM_TSENSCTL_KILL_BITS 5:5 + #define CM_TSENSCTL_KILL_SET 0x00000020 + #define CM_TSENSCTL_KILL_CLR 0xffffffdf + #define CM_TSENSCTL_KILL_MSB 5 + #define CM_TSENSCTL_KILL_LSB 5 + #define CM_TSENSCTL_ENAB_BITS 4:4 + #define CM_TSENSCTL_ENAB_SET 0x00000010 + #define CM_TSENSCTL_ENAB_CLR 0xffffffef + #define CM_TSENSCTL_ENAB_MSB 4 + #define CM_TSENSCTL_ENAB_LSB 4 + #define CM_TSENSCTL_SRC_BITS 1:0 + #define CM_TSENSCTL_SRC_SET 0x00000003 + #define CM_TSENSCTL_SRC_CLR 0xfffffffc + #define CM_TSENSCTL_SRC_MSB 1 + #define CM_TSENSCTL_SRC_LSB 0 +#define CM_TSENSDIV HW_REGISTER_RW( 0x7e1010e4 ) + #define CM_TSENSDIV_MASK 0x0001f000 + #define CM_TSENSDIV_WIDTH 17 + #define CM_TSENSDIV_RESET 0000000000 + #define CM_TSENSDIV_DIV_BITS 16:12 + #define CM_TSENSDIV_DIV_SET 0x0001f000 + #define CM_TSENSDIV_DIV_CLR 0xfffe0fff + #define CM_TSENSDIV_DIV_MSB 16 + #define CM_TSENSDIV_DIV_LSB 12 +#define CM_TIMERCTL HW_REGISTER_RW( 0x7e1010e8 ) + #define CM_TIMERCTL_MASK 0x000003b3 + #define CM_TIMERCTL_WIDTH 10 + #define CM_TIMERCTL_RESET 0000000000 + #define CM_TIMERCTL_FRAC_BITS 9:9 + #define CM_TIMERCTL_FRAC_SET 0x00000200 + #define CM_TIMERCTL_FRAC_CLR 0xfffffdff + #define CM_TIMERCTL_FRAC_MSB 9 + #define CM_TIMERCTL_FRAC_LSB 9 + #define CM_TIMERCTL_BUSYD_BITS 8:8 + #define CM_TIMERCTL_BUSYD_SET 0x00000100 + #define CM_TIMERCTL_BUSYD_CLR 0xfffffeff + #define CM_TIMERCTL_BUSYD_MSB 8 + #define CM_TIMERCTL_BUSYD_LSB 8 + #define CM_TIMERCTL_BUSY_BITS 7:7 + #define CM_TIMERCTL_BUSY_SET 0x00000080 + #define CM_TIMERCTL_BUSY_CLR 0xffffff7f + #define CM_TIMERCTL_BUSY_MSB 7 + #define CM_TIMERCTL_BUSY_LSB 7 + #define CM_TIMERCTL_KILL_BITS 5:5 + #define CM_TIMERCTL_KILL_SET 0x00000020 + #define CM_TIMERCTL_KILL_CLR 0xffffffdf + #define CM_TIMERCTL_KILL_MSB 5 + #define CM_TIMERCTL_KILL_LSB 5 + #define CM_TIMERCTL_ENAB_BITS 4:4 + #define CM_TIMERCTL_ENAB_SET 0x00000010 + #define CM_TIMERCTL_ENAB_CLR 0xffffffef + #define CM_TIMERCTL_ENAB_MSB 4 + #define CM_TIMERCTL_ENAB_LSB 4 + #define CM_TIMERCTL_SRC_BITS 1:0 + #define CM_TIMERCTL_SRC_SET 0x00000003 + #define CM_TIMERCTL_SRC_CLR 0xfffffffc + #define CM_TIMERCTL_SRC_MSB 1 + #define CM_TIMERCTL_SRC_LSB 0 +#define CM_TIMERDIV HW_REGISTER_RW( 0x7e1010ec ) + #define CM_TIMERDIV_MASK 0x0003ffff + #define CM_TIMERDIV_WIDTH 18 + #define CM_TIMERDIV_RESET 0000000000 + #define CM_TIMERDIV_DIV_BITS 17:0 + #define CM_TIMERDIV_DIV_SET 0x0003ffff + #define CM_TIMERDIV_DIV_CLR 0xfffc0000 + #define CM_TIMERDIV_DIV_MSB 17 + #define CM_TIMERDIV_DIV_LSB 0 +#define CM_UARTCTL HW_REGISTER_RW( 0x7e1010f0 ) + #define CM_UARTCTL_MASK 0x000003bf + #define CM_UARTCTL_WIDTH 10 + #define CM_UARTCTL_RESET 0000000000 + #define CM_UARTCTL_FRAC_BITS 9:9 + #define CM_UARTCTL_FRAC_SET 0x00000200 + #define CM_UARTCTL_FRAC_CLR 0xfffffdff + #define CM_UARTCTL_FRAC_MSB 9 + #define CM_UARTCTL_FRAC_LSB 9 + #define CM_UARTCTL_BUSYD_BITS 8:8 + #define CM_UARTCTL_BUSYD_SET 0x00000100 + #define CM_UARTCTL_BUSYD_CLR 0xfffffeff + #define CM_UARTCTL_BUSYD_MSB 8 + #define CM_UARTCTL_BUSYD_LSB 8 + #define CM_UARTCTL_BUSY_BITS 7:7 + #define CM_UARTCTL_BUSY_SET 0x00000080 + #define CM_UARTCTL_BUSY_CLR 0xffffff7f + #define CM_UARTCTL_BUSY_MSB 7 + #define CM_UARTCTL_BUSY_LSB 7 + #define CM_UARTCTL_KILL_BITS 5:5 + #define CM_UARTCTL_KILL_SET 0x00000020 + #define CM_UARTCTL_KILL_CLR 0xffffffdf + #define CM_UARTCTL_KILL_MSB 5 + #define CM_UARTCTL_KILL_LSB 5 + #define CM_UARTCTL_ENAB_BITS 4:4 + #define CM_UARTCTL_ENAB_SET 0x00000010 + #define CM_UARTCTL_ENAB_CLR 0xffffffef + #define CM_UARTCTL_ENAB_MSB 4 + #define CM_UARTCTL_ENAB_LSB 4 + #define CM_UARTCTL_SRC_BITS 3:0 + #define CM_UARTCTL_SRC_SET 0x0000000f + #define CM_UARTCTL_SRC_CLR 0xfffffff0 + #define CM_UARTCTL_SRC_MSB 3 + #define CM_UARTCTL_SRC_LSB 0 +#define CM_UARTDIV HW_REGISTER_RW( 0x7e1010f4 ) + #define CM_UARTDIV_MASK 0x003fffff + #define CM_UARTDIV_WIDTH 22 + #define CM_UARTDIV_RESET 0000000000 + #define CM_UARTDIV_DIV_BITS 21:0 + #define CM_UARTDIV_DIV_SET 0x003fffff + #define CM_UARTDIV_DIV_CLR 0xffc00000 + #define CM_UARTDIV_DIV_MSB 21 + #define CM_UARTDIV_DIV_LSB 0 +#define CM_VECCTL HW_REGISTER_RW( 0x7e1010f8 ) + #define CM_VECCTL_MASK 0x000003bf + #define CM_VECCTL_WIDTH 10 + #define CM_VECCTL_RESET 0000000000 + #define CM_VECCTL_FRAC_BITS 9:9 + #define CM_VECCTL_FRAC_SET 0x00000200 + #define CM_VECCTL_FRAC_CLR 0xfffffdff + #define CM_VECCTL_FRAC_MSB 9 + #define CM_VECCTL_FRAC_LSB 9 + #define CM_VECCTL_BUSYD_BITS 8:8 + #define CM_VECCTL_BUSYD_SET 0x00000100 + #define CM_VECCTL_BUSYD_CLR 0xfffffeff + #define CM_VECCTL_BUSYD_MSB 8 + #define CM_VECCTL_BUSYD_LSB 8 + #define CM_VECCTL_BUSY_BITS 7:7 + #define CM_VECCTL_BUSY_SET 0x00000080 + #define CM_VECCTL_BUSY_CLR 0xffffff7f + #define CM_VECCTL_BUSY_MSB 7 + #define CM_VECCTL_BUSY_LSB 7 + #define CM_VECCTL_KILL_BITS 5:5 + #define CM_VECCTL_KILL_SET 0x00000020 + #define CM_VECCTL_KILL_CLR 0xffffffdf + #define CM_VECCTL_KILL_MSB 5 + #define CM_VECCTL_KILL_LSB 5 + #define CM_VECCTL_ENAB_BITS 4:4 + #define CM_VECCTL_ENAB_SET 0x00000010 + #define CM_VECCTL_ENAB_CLR 0xffffffef + #define CM_VECCTL_ENAB_MSB 4 + #define CM_VECCTL_ENAB_LSB 4 + #define CM_VECCTL_SRC_BITS 3:0 + #define CM_VECCTL_SRC_SET 0x0000000f + #define CM_VECCTL_SRC_CLR 0xfffffff0 + #define CM_VECCTL_SRC_MSB 3 + #define CM_VECCTL_SRC_LSB 0 +#define CM_VECDIV HW_REGISTER_RW( 0x7e1010fc ) + #define CM_VECDIV_MASK 0x0000f000 + #define CM_VECDIV_WIDTH 16 + #define CM_VECDIV_RESET 0000000000 + #define CM_VECDIV_DIV_BITS 15:12 + #define CM_VECDIV_DIV_SET 0x0000f000 + #define CM_VECDIV_DIV_CLR 0xffff0fff + #define CM_VECDIV_DIV_MSB 15 + #define CM_VECDIV_DIV_LSB 12 +#define CM_AVEOCTL HW_REGISTER_RW( 0x7e1011b8 ) + #define CM_AVEOCTL_MASK 0x000003bf + #define CM_AVEOCTL_WIDTH 10 + #define CM_AVEOCTL_RESET 0000000000 + #define CM_AVEOCTL_FRAC_BITS 9:9 + #define CM_AVEOCTL_FRAC_SET 0x00000200 + #define CM_AVEOCTL_FRAC_CLR 0xfffffdff + #define CM_AVEOCTL_FRAC_MSB 9 + #define CM_AVEOCTL_FRAC_LSB 9 + #define CM_AVEOCTL_BUSYD_BITS 8:8 + #define CM_AVEOCTL_BUSYD_SET 0x00000100 + #define CM_AVEOCTL_BUSYD_CLR 0xfffffeff + #define CM_AVEOCTL_BUSYD_MSB 8 + #define CM_AVEOCTL_BUSYD_LSB 8 + #define CM_AVEOCTL_BUSY_BITS 7:7 + #define CM_AVEOCTL_BUSY_SET 0x00000080 + #define CM_AVEOCTL_BUSY_CLR 0xffffff7f + #define CM_AVEOCTL_BUSY_MSB 7 + #define CM_AVEOCTL_BUSY_LSB 7 + #define CM_AVEOCTL_KILL_BITS 5:5 + #define CM_AVEOCTL_KILL_SET 0x00000020 + #define CM_AVEOCTL_KILL_CLR 0xffffffdf + #define CM_AVEOCTL_KILL_MSB 5 + #define CM_AVEOCTL_KILL_LSB 5 + #define CM_AVEOCTL_ENAB_BITS 4:4 + #define CM_AVEOCTL_ENAB_SET 0x00000010 + #define CM_AVEOCTL_ENAB_CLR 0xffffffef + #define CM_AVEOCTL_ENAB_MSB 4 + #define CM_AVEOCTL_ENAB_LSB 4 + #define CM_AVEOCTL_SRC_BITS 3:0 + #define CM_AVEOCTL_SRC_SET 0x0000000f + #define CM_AVEOCTL_SRC_CLR 0xfffffff0 + #define CM_AVEOCTL_SRC_MSB 3 + #define CM_AVEOCTL_SRC_LSB 0 +#define CM_AVEODIV HW_REGISTER_RW( 0x7e1011bc ) + #define CM_AVEODIV_MASK 0x0000f000 + #define CM_AVEODIV_WIDTH 16 + #define CM_AVEODIV_RESET 0000000000 + #define CM_AVEODIV_DIV_BITS 15:12 + #define CM_AVEODIV_DIV_SET 0x0000f000 + #define CM_AVEODIV_DIV_CLR 0xffff0fff + #define CM_AVEODIV_DIV_MSB 15 + #define CM_AVEODIV_DIV_LSB 12 +#define CM_EMMCCTL HW_REGISTER_RW( 0x7e1011c0 ) + #define CM_EMMCCTL_MASK 0x000003bf + #define CM_EMMCCTL_WIDTH 10 + #define CM_EMMCCTL_RESET 0000000000 + #define CM_EMMCCTL_FRAC_BITS 9:9 + #define CM_EMMCCTL_FRAC_SET 0x00000200 + #define CM_EMMCCTL_FRAC_CLR 0xfffffdff + #define CM_EMMCCTL_FRAC_MSB 9 + #define CM_EMMCCTL_FRAC_LSB 9 + #define CM_EMMCCTL_BUSYD_BITS 8:8 + #define CM_EMMCCTL_BUSYD_SET 0x00000100 + #define CM_EMMCCTL_BUSYD_CLR 0xfffffeff + #define CM_EMMCCTL_BUSYD_MSB 8 + #define CM_EMMCCTL_BUSYD_LSB 8 + #define CM_EMMCCTL_BUSY_BITS 7:7 + #define CM_EMMCCTL_BUSY_SET 0x00000080 + #define CM_EMMCCTL_BUSY_CLR 0xffffff7f + #define CM_EMMCCTL_BUSY_MSB 7 + #define CM_EMMCCTL_BUSY_LSB 7 + #define CM_EMMCCTL_KILL_BITS 5:5 + #define CM_EMMCCTL_KILL_SET 0x00000020 + #define CM_EMMCCTL_KILL_CLR 0xffffffdf + #define CM_EMMCCTL_KILL_MSB 5 + #define CM_EMMCCTL_KILL_LSB 5 + #define CM_EMMCCTL_ENAB_BITS 4:4 + #define CM_EMMCCTL_ENAB_SET 0x00000010 + #define CM_EMMCCTL_ENAB_CLR 0xffffffef + #define CM_EMMCCTL_ENAB_MSB 4 + #define CM_EMMCCTL_ENAB_LSB 4 + #define CM_EMMCCTL_SRC_BITS 3:0 + #define CM_EMMCCTL_SRC_SET 0x0000000f + #define CM_EMMCCTL_SRC_CLR 0xfffffff0 + #define CM_EMMCCTL_SRC_MSB 3 + #define CM_EMMCCTL_SRC_LSB 0 +#define CM_EMMCDIV HW_REGISTER_RW( 0x7e1011c4 ) + #define CM_EMMCDIV_MASK 0x0000fff0 + #define CM_EMMCDIV_WIDTH 16 + #define CM_EMMCDIV_RESET 0000000000 + #define CM_EMMCDIV_DIV_BITS 15:4 + #define CM_EMMCDIV_DIV_SET 0x0000fff0 + #define CM_EMMCDIV_DIV_CLR 0xffff000f + #define CM_EMMCDIV_DIV_MSB 15 + #define CM_EMMCDIV_DIV_LSB 4 +#define CM_OSCCOUNT HW_REGISTER_RW( 0x7e101100 ) + #define CM_OSCCOUNT_MASK 0x00ffffff + #define CM_OSCCOUNT_WIDTH 24 + #define CM_OSCCOUNT_RESET 0000000000 + #define CM_OSCCOUNT_NUM_BITS 23:0 + #define CM_OSCCOUNT_NUM_SET 0x00ffffff + #define CM_OSCCOUNT_NUM_CLR 0xff000000 + #define CM_OSCCOUNT_NUM_MSB 23 + #define CM_OSCCOUNT_NUM_LSB 0 +#define CM_PLLA HW_REGISTER_RW( 0x7e101104 ) + #define CM_PLLA_MASK 0x000003ff + #define CM_PLLA_WIDTH 10 + #define CM_PLLA_RESET 0x00000300 + #define CM_PLLA_DIGRST_BITS 9:9 + #define CM_PLLA_DIGRST_SET 0x00000200 + #define CM_PLLA_DIGRST_CLR 0xfffffdff + #define CM_PLLA_DIGRST_MSB 9 + #define CM_PLLA_DIGRST_LSB 9 + #define CM_PLLA_ANARST_BITS 8:8 + #define CM_PLLA_ANARST_SET 0x00000100 + #define CM_PLLA_ANARST_CLR 0xfffffeff + #define CM_PLLA_ANARST_MSB 8 + #define CM_PLLA_ANARST_LSB 8 + #define CM_PLLA_HOLDPER_BITS 7:7 + #define CM_PLLA_HOLDPER_SET 0x00000080 + #define CM_PLLA_HOLDPER_CLR 0xffffff7f + #define CM_PLLA_HOLDPER_MSB 7 + #define CM_PLLA_HOLDPER_LSB 7 + #define CM_PLLA_LOADPER_BITS 6:6 + #define CM_PLLA_LOADPER_SET 0x00000040 + #define CM_PLLA_LOADPER_CLR 0xffffffbf + #define CM_PLLA_LOADPER_MSB 6 + #define CM_PLLA_LOADPER_LSB 6 + #define CM_PLLA_HOLDCORE_BITS 5:5 + #define CM_PLLA_HOLDCORE_SET 0x00000020 + #define CM_PLLA_HOLDCORE_CLR 0xffffffdf + #define CM_PLLA_HOLDCORE_MSB 5 + #define CM_PLLA_HOLDCORE_LSB 5 + #define CM_PLLA_LOADCORE_BITS 4:4 + #define CM_PLLA_LOADCORE_SET 0x00000010 + #define CM_PLLA_LOADCORE_CLR 0xffffffef + #define CM_PLLA_LOADCORE_MSB 4 + #define CM_PLLA_LOADCORE_LSB 4 + #define CM_PLLA_HOLDCCP2_BITS 3:3 + #define CM_PLLA_HOLDCCP2_SET 0x00000008 + #define CM_PLLA_HOLDCCP2_CLR 0xfffffff7 + #define CM_PLLA_HOLDCCP2_MSB 3 + #define CM_PLLA_HOLDCCP2_LSB 3 + #define CM_PLLA_LOADCCP2_BITS 2:2 + #define CM_PLLA_LOADCCP2_SET 0x00000004 + #define CM_PLLA_LOADCCP2_CLR 0xfffffffb + #define CM_PLLA_LOADCCP2_MSB 2 + #define CM_PLLA_LOADCCP2_LSB 2 + #define CM_PLLA_HOLDDSI0_BITS 1:1 + #define CM_PLLA_HOLDDSI0_SET 0x00000002 + #define CM_PLLA_HOLDDSI0_CLR 0xfffffffd + #define CM_PLLA_HOLDDSI0_MSB 1 + #define CM_PLLA_HOLDDSI0_LSB 1 + #define CM_PLLA_LOADDSI0_BITS 0:0 + #define CM_PLLA_LOADDSI0_SET 0x00000001 + #define CM_PLLA_LOADDSI0_CLR 0xfffffffe + #define CM_PLLA_LOADDSI0_MSB 0 + #define CM_PLLA_LOADDSI0_LSB 0 +#define CM_PLLB HW_REGISTER_RW( 0x7e101170 ) + #define CM_PLLB_MASK 0x00000303 + #define CM_PLLB_WIDTH 10 + #define CM_PLLB_RESET 0x00000300 + #define CM_PLLB_DIGRST_BITS 9:9 + #define CM_PLLB_DIGRST_SET 0x00000200 + #define CM_PLLB_DIGRST_CLR 0xfffffdff + #define CM_PLLB_DIGRST_MSB 9 + #define CM_PLLB_DIGRST_LSB 9 + #define CM_PLLB_ANARST_BITS 8:8 + #define CM_PLLB_ANARST_SET 0x00000100 + #define CM_PLLB_ANARST_CLR 0xfffffeff + #define CM_PLLB_ANARST_MSB 8 + #define CM_PLLB_ANARST_LSB 8 + #define CM_PLLB_HOLDARM_BITS 1:1 + #define CM_PLLB_HOLDARM_SET 0x00000002 + #define CM_PLLB_HOLDARM_CLR 0xfffffffd + #define CM_PLLB_HOLDARM_MSB 1 + #define CM_PLLB_HOLDARM_LSB 1 + #define CM_PLLB_LOADARM_BITS 0:0 + #define CM_PLLB_LOADARM_SET 0x00000001 + #define CM_PLLB_LOADARM_CLR 0xfffffffe + #define CM_PLLB_LOADARM_MSB 0 + #define CM_PLLB_LOADARM_LSB 0 +#define CM_PLLC HW_REGISTER_RW( 0x7e101108 ) + #define CM_PLLC_MASK 0x000003ff + #define CM_PLLC_WIDTH 10 + #define CM_PLLC_RESET 0x00000300 + #define CM_PLLC_DIGRST_BITS 9:9 + #define CM_PLLC_DIGRST_SET 0x00000200 + #define CM_PLLC_DIGRST_CLR 0xfffffdff + #define CM_PLLC_DIGRST_MSB 9 + #define CM_PLLC_DIGRST_LSB 9 + #define CM_PLLC_ANARST_BITS 8:8 + #define CM_PLLC_ANARST_SET 0x00000100 + #define CM_PLLC_ANARST_CLR 0xfffffeff + #define CM_PLLC_ANARST_MSB 8 + #define CM_PLLC_ANARST_LSB 8 + #define CM_PLLC_HOLDPER_BITS 7:7 + #define CM_PLLC_HOLDPER_SET 0x00000080 + #define CM_PLLC_HOLDPER_CLR 0xffffff7f + #define CM_PLLC_HOLDPER_MSB 7 + #define CM_PLLC_HOLDPER_LSB 7 + #define CM_PLLC_LOADPER_BITS 6:6 + #define CM_PLLC_LOADPER_SET 0x00000040 + #define CM_PLLC_LOADPER_CLR 0xffffffbf + #define CM_PLLC_LOADPER_MSB 6 + #define CM_PLLC_LOADPER_LSB 6 + #define CM_PLLC_HOLDCORE2_BITS 5:5 + #define CM_PLLC_HOLDCORE2_SET 0x00000020 + #define CM_PLLC_HOLDCORE2_CLR 0xffffffdf + #define CM_PLLC_HOLDCORE2_MSB 5 + #define CM_PLLC_HOLDCORE2_LSB 5 + #define CM_PLLC_LOADCORE2_BITS 4:4 + #define CM_PLLC_LOADCORE2_SET 0x00000010 + #define CM_PLLC_LOADCORE2_CLR 0xffffffef + #define CM_PLLC_LOADCORE2_MSB 4 + #define CM_PLLC_LOADCORE2_LSB 4 + #define CM_PLLC_HOLDCORE1_BITS 3:3 + #define CM_PLLC_HOLDCORE1_SET 0x00000008 + #define CM_PLLC_HOLDCORE1_CLR 0xfffffff7 + #define CM_PLLC_HOLDCORE1_MSB 3 + #define CM_PLLC_HOLDCORE1_LSB 3 + #define CM_PLLC_LOADCORE1_BITS 2:2 + #define CM_PLLC_LOADCORE1_SET 0x00000004 + #define CM_PLLC_LOADCORE1_CLR 0xfffffffb + #define CM_PLLC_LOADCORE1_MSB 2 + #define CM_PLLC_LOADCORE1_LSB 2 + #define CM_PLLC_HOLDCORE0_BITS 1:1 + #define CM_PLLC_HOLDCORE0_SET 0x00000002 + #define CM_PLLC_HOLDCORE0_CLR 0xfffffffd + #define CM_PLLC_HOLDCORE0_MSB 1 + #define CM_PLLC_HOLDCORE0_LSB 1 + #define CM_PLLC_LOADCORE0_BITS 0:0 + #define CM_PLLC_LOADCORE0_SET 0x00000001 + #define CM_PLLC_LOADCORE0_CLR 0xfffffffe + #define CM_PLLC_LOADCORE0_MSB 0 + #define CM_PLLC_LOADCORE0_LSB 0 +#define CM_PLLD HW_REGISTER_RW( 0x7e10110c ) + #define CM_PLLD_MASK 0x000003ff + #define CM_PLLD_WIDTH 10 + #define CM_PLLD_RESET 0x00000300 + #define CM_PLLD_DIGRST_BITS 9:9 + #define CM_PLLD_DIGRST_SET 0x00000200 + #define CM_PLLD_DIGRST_CLR 0xfffffdff + #define CM_PLLD_DIGRST_MSB 9 + #define CM_PLLD_DIGRST_LSB 9 + #define CM_PLLD_ANARST_BITS 8:8 + #define CM_PLLD_ANARST_SET 0x00000100 + #define CM_PLLD_ANARST_CLR 0xfffffeff + #define CM_PLLD_ANARST_MSB 8 + #define CM_PLLD_ANARST_LSB 8 + #define CM_PLLD_HOLDPER_BITS 7:7 + #define CM_PLLD_HOLDPER_SET 0x00000080 + #define CM_PLLD_HOLDPER_CLR 0xffffff7f + #define CM_PLLD_HOLDPER_MSB 7 + #define CM_PLLD_HOLDPER_LSB 7 + #define CM_PLLD_LOADPER_BITS 6:6 + #define CM_PLLD_LOADPER_SET 0x00000040 + #define CM_PLLD_LOADPER_CLR 0xffffffbf + #define CM_PLLD_LOADPER_MSB 6 + #define CM_PLLD_LOADPER_LSB 6 + #define CM_PLLD_HOLDCORE_BITS 5:5 + #define CM_PLLD_HOLDCORE_SET 0x00000020 + #define CM_PLLD_HOLDCORE_CLR 0xffffffdf + #define CM_PLLD_HOLDCORE_MSB 5 + #define CM_PLLD_HOLDCORE_LSB 5 + #define CM_PLLD_LOADCORE_BITS 4:4 + #define CM_PLLD_LOADCORE_SET 0x00000010 + #define CM_PLLD_LOADCORE_CLR 0xffffffef + #define CM_PLLD_LOADCORE_MSB 4 + #define CM_PLLD_LOADCORE_LSB 4 + #define CM_PLLD_HOLDDSI1_BITS 3:3 + #define CM_PLLD_HOLDDSI1_SET 0x00000008 + #define CM_PLLD_HOLDDSI1_CLR 0xfffffff7 + #define CM_PLLD_HOLDDSI1_MSB 3 + #define CM_PLLD_HOLDDSI1_LSB 3 + #define CM_PLLD_LOADDSI1_BITS 2:2 + #define CM_PLLD_LOADDSI1_SET 0x00000004 + #define CM_PLLD_LOADDSI1_CLR 0xfffffffb + #define CM_PLLD_LOADDSI1_MSB 2 + #define CM_PLLD_LOADDSI1_LSB 2 + #define CM_PLLD_HOLDDSI0_BITS 1:1 + #define CM_PLLD_HOLDDSI0_SET 0x00000002 + #define CM_PLLD_HOLDDSI0_CLR 0xfffffffd + #define CM_PLLD_HOLDDSI0_MSB 1 + #define CM_PLLD_HOLDDSI0_LSB 1 + #define CM_PLLD_LOADDSI0_BITS 0:0 + #define CM_PLLD_LOADDSI0_SET 0x00000001 + #define CM_PLLD_LOADDSI0_CLR 0xfffffffe + #define CM_PLLD_LOADDSI0_MSB 0 + #define CM_PLLD_LOADDSI0_LSB 0 +#define CM_PLLH HW_REGISTER_RW( 0x7e101110 ) + #define CM_PLLH_MASK 0x00000307 + #define CM_PLLH_WIDTH 10 + #define CM_PLLH_RESET 0x00000300 + #define CM_PLLH_DIGRST_BITS 9:9 + #define CM_PLLH_DIGRST_SET 0x00000200 + #define CM_PLLH_DIGRST_CLR 0xfffffdff + #define CM_PLLH_DIGRST_MSB 9 + #define CM_PLLH_DIGRST_LSB 9 + #define CM_PLLH_ANARST_BITS 8:8 + #define CM_PLLH_ANARST_SET 0x00000100 + #define CM_PLLH_ANARST_CLR 0xfffffeff + #define CM_PLLH_ANARST_MSB 8 + #define CM_PLLH_ANARST_LSB 8 + #define CM_PLLH_LOADRCAL_BITS 2:2 + #define CM_PLLH_LOADRCAL_SET 0x00000004 + #define CM_PLLH_LOADRCAL_CLR 0xfffffffb + #define CM_PLLH_LOADRCAL_MSB 2 + #define CM_PLLH_LOADRCAL_LSB 2 + #define CM_PLLH_LOADAUX_BITS 1:1 + #define CM_PLLH_LOADAUX_SET 0x00000002 + #define CM_PLLH_LOADAUX_CLR 0xfffffffd + #define CM_PLLH_LOADAUX_MSB 1 + #define CM_PLLH_LOADAUX_LSB 1 + #define CM_PLLH_LOADPIX_BITS 0:0 + #define CM_PLLH_LOADPIX_SET 0x00000001 + #define CM_PLLH_LOADPIX_CLR 0xfffffffe + #define CM_PLLH_LOADPIX_MSB 0 + #define CM_PLLH_LOADPIX_LSB 0 +#define CM_LOCK HW_REGISTER_RW( 0x7e101114 ) + #define CM_LOCK_MASK 0x00001f1f + #define CM_LOCK_WIDTH 13 + #define CM_LOCK_RESET 0000000000 + #define CM_LOCK_FLOCKH_BITS 12:12 + #define CM_LOCK_FLOCKH_SET 0x00001000 + #define CM_LOCK_FLOCKH_CLR 0xffffefff + #define CM_LOCK_FLOCKH_MSB 12 + #define CM_LOCK_FLOCKH_LSB 12 + #define CM_LOCK_FLOCKD_BITS 11:11 + #define CM_LOCK_FLOCKD_SET 0x00000800 + #define CM_LOCK_FLOCKD_CLR 0xfffff7ff + #define CM_LOCK_FLOCKD_MSB 11 + #define CM_LOCK_FLOCKD_LSB 11 + #define CM_LOCK_FLOCKC_BITS 10:10 + #define CM_LOCK_FLOCKC_SET 0x00000400 + #define CM_LOCK_FLOCKC_CLR 0xfffffbff + #define CM_LOCK_FLOCKC_MSB 10 + #define CM_LOCK_FLOCKC_LSB 10 + #define CM_LOCK_FLOCKB_BITS 9:9 + #define CM_LOCK_FLOCKB_SET 0x00000200 + #define CM_LOCK_FLOCKB_CLR 0xfffffdff + #define CM_LOCK_FLOCKB_MSB 9 + #define CM_LOCK_FLOCKB_LSB 9 + #define CM_LOCK_FLOCKA_BITS 8:8 + #define CM_LOCK_FLOCKA_SET 0x00000100 + #define CM_LOCK_FLOCKA_CLR 0xfffffeff + #define CM_LOCK_FLOCKA_MSB 8 + #define CM_LOCK_FLOCKA_LSB 8 + #define CM_LOCK_LOCKH_BITS 4:4 + #define CM_LOCK_LOCKH_SET 0x00000010 + #define CM_LOCK_LOCKH_CLR 0xffffffef + #define CM_LOCK_LOCKH_MSB 4 + #define CM_LOCK_LOCKH_LSB 4 + #define CM_LOCK_LOCKD_BITS 3:3 + #define CM_LOCK_LOCKD_SET 0x00000008 + #define CM_LOCK_LOCKD_CLR 0xfffffff7 + #define CM_LOCK_LOCKD_MSB 3 + #define CM_LOCK_LOCKD_LSB 3 + #define CM_LOCK_LOCKC_BITS 2:2 + #define CM_LOCK_LOCKC_SET 0x00000004 + #define CM_LOCK_LOCKC_CLR 0xfffffffb + #define CM_LOCK_LOCKC_MSB 2 + #define CM_LOCK_LOCKC_LSB 2 + #define CM_LOCK_LOCKB_BITS 1:1 + #define CM_LOCK_LOCKB_SET 0x00000002 + #define CM_LOCK_LOCKB_CLR 0xfffffffd + #define CM_LOCK_LOCKB_MSB 1 + #define CM_LOCK_LOCKB_LSB 1 + #define CM_LOCK_LOCKA_BITS 0:0 + #define CM_LOCK_LOCKA_SET 0x00000001 + #define CM_LOCK_LOCKA_CLR 0xfffffffe + #define CM_LOCK_LOCKA_MSB 0 + #define CM_LOCK_LOCKA_LSB 0 +#define CM_EVENT HW_REGISTER_RW( 0x7e101118 ) + #define CM_EVENT_MASK 0x00ffffff + #define CM_EVENT_WIDTH 24 + #define CM_EVENT_RESET 0000000000 + #define CM_EVENT_BURSTDONE_BITS 23:23 + #define CM_EVENT_BURSTDONE_SET 0x00800000 + #define CM_EVENT_BURSTDONE_CLR 0xff7fffff + #define CM_EVENT_BURSTDONE_MSB 23 + #define CM_EVENT_BURSTDONE_LSB 23 + #define CM_EVENT_RESUS_BITS 22:22 + #define CM_EVENT_RESUS_SET 0x00400000 + #define CM_EVENT_RESUS_CLR 0xffbfffff + #define CM_EVENT_RESUS_MSB 22 + #define CM_EVENT_RESUS_LSB 22 + #define CM_EVENT_OCDONE_BITS 21:21 + #define CM_EVENT_OCDONE_SET 0x00200000 + #define CM_EVENT_OCDONE_CLR 0xffdfffff + #define CM_EVENT_OCDONE_MSB 21 + #define CM_EVENT_OCDONE_LSB 21 + #define CM_EVENT_A2WDONE_BITS 20:20 + #define CM_EVENT_A2WDONE_SET 0x00100000 + #define CM_EVENT_A2WDONE_CLR 0xffefffff + #define CM_EVENT_A2WDONE_MSB 20 + #define CM_EVENT_A2WDONE_LSB 20 + #define CM_EVENT_WRFAIL_BITS 19:19 + #define CM_EVENT_WRFAIL_SET 0x00080000 + #define CM_EVENT_WRFAIL_CLR 0xfff7ffff + #define CM_EVENT_WRFAIL_MSB 19 + #define CM_EVENT_WRFAIL_LSB 19 + #define CM_EVENT_BADPASS_BITS 18:18 + #define CM_EVENT_BADPASS_SET 0x00040000 + #define CM_EVENT_BADPASS_CLR 0xfffbffff + #define CM_EVENT_BADPASS_MSB 18 + #define CM_EVENT_BADPASS_LSB 18 + #define CM_EVENT_FLOSSD_BITS 17:17 + #define CM_EVENT_FLOSSD_SET 0x00020000 + #define CM_EVENT_FLOSSD_CLR 0xfffdffff + #define CM_EVENT_FLOSSD_MSB 17 + #define CM_EVENT_FLOSSD_LSB 17 + #define CM_EVENT_FLOSSC_BITS 16:16 + #define CM_EVENT_FLOSSC_SET 0x00010000 + #define CM_EVENT_FLOSSC_CLR 0xfffeffff + #define CM_EVENT_FLOSSC_MSB 16 + #define CM_EVENT_FLOSSC_LSB 16 + #define CM_EVENT_FLOSSB_BITS 15:15 + #define CM_EVENT_FLOSSB_SET 0x00008000 + #define CM_EVENT_FLOSSB_CLR 0xffff7fff + #define CM_EVENT_FLOSSB_MSB 15 + #define CM_EVENT_FLOSSB_LSB 15 + #define CM_EVENT_FLOSSA_BITS 14:14 + #define CM_EVENT_FLOSSA_SET 0x00004000 + #define CM_EVENT_FLOSSA_CLR 0xffffbfff + #define CM_EVENT_FLOSSA_MSB 14 + #define CM_EVENT_FLOSSA_LSB 14 + #define CM_EVENT_FGAIND_BITS 13:13 + #define CM_EVENT_FGAIND_SET 0x00002000 + #define CM_EVENT_FGAIND_CLR 0xffffdfff + #define CM_EVENT_FGAIND_MSB 13 + #define CM_EVENT_FGAIND_LSB 13 + #define CM_EVENT_FGAINC_BITS 12:12 + #define CM_EVENT_FGAINC_SET 0x00001000 + #define CM_EVENT_FGAINC_CLR 0xffffefff + #define CM_EVENT_FGAINC_MSB 12 + #define CM_EVENT_FGAINC_LSB 12 + #define CM_EVENT_FGAINB_BITS 11:11 + #define CM_EVENT_FGAINB_SET 0x00000800 + #define CM_EVENT_FGAINB_CLR 0xfffff7ff + #define CM_EVENT_FGAINB_MSB 11 + #define CM_EVENT_FGAINB_LSB 11 + #define CM_EVENT_FGAINA_BITS 10:10 + #define CM_EVENT_FGAINA_SET 0x00000400 + #define CM_EVENT_FGAINA_CLR 0xfffffbff + #define CM_EVENT_FGAINA_MSB 10 + #define CM_EVENT_FGAINA_LSB 10 + #define CM_EVENT_LOSSH_BITS 9:9 + #define CM_EVENT_LOSSH_SET 0x00000200 + #define CM_EVENT_LOSSH_CLR 0xfffffdff + #define CM_EVENT_LOSSH_MSB 9 + #define CM_EVENT_LOSSH_LSB 9 + #define CM_EVENT_LOSSD_BITS 8:8 + #define CM_EVENT_LOSSD_SET 0x00000100 + #define CM_EVENT_LOSSD_CLR 0xfffffeff + #define CM_EVENT_LOSSD_MSB 8 + #define CM_EVENT_LOSSD_LSB 8 + #define CM_EVENT_LOSSC_BITS 7:7 + #define CM_EVENT_LOSSC_SET 0x00000080 + #define CM_EVENT_LOSSC_CLR 0xffffff7f + #define CM_EVENT_LOSSC_MSB 7 + #define CM_EVENT_LOSSC_LSB 7 + #define CM_EVENT_LOSSB_BITS 6:6 + #define CM_EVENT_LOSSB_SET 0x00000040 + #define CM_EVENT_LOSSB_CLR 0xffffffbf + #define CM_EVENT_LOSSB_MSB 6 + #define CM_EVENT_LOSSB_LSB 6 + #define CM_EVENT_LOSSA_BITS 5:5 + #define CM_EVENT_LOSSA_SET 0x00000020 + #define CM_EVENT_LOSSA_CLR 0xffffffdf + #define CM_EVENT_LOSSA_MSB 5 + #define CM_EVENT_LOSSA_LSB 5 + #define CM_EVENT_GAINH_BITS 4:4 + #define CM_EVENT_GAINH_SET 0x00000010 + #define CM_EVENT_GAINH_CLR 0xffffffef + #define CM_EVENT_GAINH_MSB 4 + #define CM_EVENT_GAINH_LSB 4 + #define CM_EVENT_GAIND_BITS 3:3 + #define CM_EVENT_GAIND_SET 0x00000008 + #define CM_EVENT_GAIND_CLR 0xfffffff7 + #define CM_EVENT_GAIND_MSB 3 + #define CM_EVENT_GAIND_LSB 3 + #define CM_EVENT_GAINC_BITS 2:2 + #define CM_EVENT_GAINC_SET 0x00000004 + #define CM_EVENT_GAINC_CLR 0xfffffffb + #define CM_EVENT_GAINC_MSB 2 + #define CM_EVENT_GAINC_LSB 2 + #define CM_EVENT_GAINB_BITS 1:1 + #define CM_EVENT_GAINB_SET 0x00000002 + #define CM_EVENT_GAINB_CLR 0xfffffffd + #define CM_EVENT_GAINB_MSB 1 + #define CM_EVENT_GAINB_LSB 1 + #define CM_EVENT_GAINA_BITS 0:0 + #define CM_EVENT_GAINA_SET 0x00000001 + #define CM_EVENT_GAINA_CLR 0xfffffffe + #define CM_EVENT_GAINA_MSB 0 + #define CM_EVENT_GAINA_LSB 0 +#define CM_INTEN HW_REGISTER_RW( 0x7e10111c ) + #define CM_INTEN_MASK 0x00ffffff + #define CM_INTEN_WIDTH 24 + #define CM_INTEN_RESET 0000000000 + #define CM_INTEN_BURSTDONE_BITS 23:23 + #define CM_INTEN_BURSTDONE_SET 0x00800000 + #define CM_INTEN_BURSTDONE_CLR 0xff7fffff + #define CM_INTEN_BURSTDONE_MSB 23 + #define CM_INTEN_BURSTDONE_LSB 23 + #define CM_INTEN_RESUS_BITS 22:22 + #define CM_INTEN_RESUS_SET 0x00400000 + #define CM_INTEN_RESUS_CLR 0xffbfffff + #define CM_INTEN_RESUS_MSB 22 + #define CM_INTEN_RESUS_LSB 22 + #define CM_INTEN_OCDONE_BITS 21:21 + #define CM_INTEN_OCDONE_SET 0x00200000 + #define CM_INTEN_OCDONE_CLR 0xffdfffff + #define CM_INTEN_OCDONE_MSB 21 + #define CM_INTEN_OCDONE_LSB 21 + #define CM_INTEN_A2WDONE_BITS 20:20 + #define CM_INTEN_A2WDONE_SET 0x00100000 + #define CM_INTEN_A2WDONE_CLR 0xffefffff + #define CM_INTEN_A2WDONE_MSB 20 + #define CM_INTEN_A2WDONE_LSB 20 + #define CM_INTEN_WRFAIL_BITS 19:19 + #define CM_INTEN_WRFAIL_SET 0x00080000 + #define CM_INTEN_WRFAIL_CLR 0xfff7ffff + #define CM_INTEN_WRFAIL_MSB 19 + #define CM_INTEN_WRFAIL_LSB 19 + #define CM_INTEN_BADPASS_BITS 18:18 + #define CM_INTEN_BADPASS_SET 0x00040000 + #define CM_INTEN_BADPASS_CLR 0xfffbffff + #define CM_INTEN_BADPASS_MSB 18 + #define CM_INTEN_BADPASS_LSB 18 + #define CM_INTEN_FLOSSD_BITS 17:17 + #define CM_INTEN_FLOSSD_SET 0x00020000 + #define CM_INTEN_FLOSSD_CLR 0xfffdffff + #define CM_INTEN_FLOSSD_MSB 17 + #define CM_INTEN_FLOSSD_LSB 17 + #define CM_INTEN_FLOSSC_BITS 16:16 + #define CM_INTEN_FLOSSC_SET 0x00010000 + #define CM_INTEN_FLOSSC_CLR 0xfffeffff + #define CM_INTEN_FLOSSC_MSB 16 + #define CM_INTEN_FLOSSC_LSB 16 + #define CM_INTEN_FLOSSB_BITS 15:15 + #define CM_INTEN_FLOSSB_SET 0x00008000 + #define CM_INTEN_FLOSSB_CLR 0xffff7fff + #define CM_INTEN_FLOSSB_MSB 15 + #define CM_INTEN_FLOSSB_LSB 15 + #define CM_INTEN_FLOSSA_BITS 14:14 + #define CM_INTEN_FLOSSA_SET 0x00004000 + #define CM_INTEN_FLOSSA_CLR 0xffffbfff + #define CM_INTEN_FLOSSA_MSB 14 + #define CM_INTEN_FLOSSA_LSB 14 + #define CM_INTEN_FGAIND_BITS 13:13 + #define CM_INTEN_FGAIND_SET 0x00002000 + #define CM_INTEN_FGAIND_CLR 0xffffdfff + #define CM_INTEN_FGAIND_MSB 13 + #define CM_INTEN_FGAIND_LSB 13 + #define CM_INTEN_FGAINC_BITS 12:12 + #define CM_INTEN_FGAINC_SET 0x00001000 + #define CM_INTEN_FGAINC_CLR 0xffffefff + #define CM_INTEN_FGAINC_MSB 12 + #define CM_INTEN_FGAINC_LSB 12 + #define CM_INTEN_FGAINB_BITS 11:11 + #define CM_INTEN_FGAINB_SET 0x00000800 + #define CM_INTEN_FGAINB_CLR 0xfffff7ff + #define CM_INTEN_FGAINB_MSB 11 + #define CM_INTEN_FGAINB_LSB 11 + #define CM_INTEN_FGAINA_BITS 10:10 + #define CM_INTEN_FGAINA_SET 0x00000400 + #define CM_INTEN_FGAINA_CLR 0xfffffbff + #define CM_INTEN_FGAINA_MSB 10 + #define CM_INTEN_FGAINA_LSB 10 + #define CM_INTEN_LOSSH_BITS 9:9 + #define CM_INTEN_LOSSH_SET 0x00000200 + #define CM_INTEN_LOSSH_CLR 0xfffffdff + #define CM_INTEN_LOSSH_MSB 9 + #define CM_INTEN_LOSSH_LSB 9 + #define CM_INTEN_LOSSD_BITS 8:8 + #define CM_INTEN_LOSSD_SET 0x00000100 + #define CM_INTEN_LOSSD_CLR 0xfffffeff + #define CM_INTEN_LOSSD_MSB 8 + #define CM_INTEN_LOSSD_LSB 8 + #define CM_INTEN_LOSSC_BITS 7:7 + #define CM_INTEN_LOSSC_SET 0x00000080 + #define CM_INTEN_LOSSC_CLR 0xffffff7f + #define CM_INTEN_LOSSC_MSB 7 + #define CM_INTEN_LOSSC_LSB 7 + #define CM_INTEN_LOSSB_BITS 6:6 + #define CM_INTEN_LOSSB_SET 0x00000040 + #define CM_INTEN_LOSSB_CLR 0xffffffbf + #define CM_INTEN_LOSSB_MSB 6 + #define CM_INTEN_LOSSB_LSB 6 + #define CM_INTEN_LOSSA_BITS 5:5 + #define CM_INTEN_LOSSA_SET 0x00000020 + #define CM_INTEN_LOSSA_CLR 0xffffffdf + #define CM_INTEN_LOSSA_MSB 5 + #define CM_INTEN_LOSSA_LSB 5 + #define CM_INTEN_GAINH_BITS 4:4 + #define CM_INTEN_GAINH_SET 0x00000010 + #define CM_INTEN_GAINH_CLR 0xffffffef + #define CM_INTEN_GAINH_MSB 4 + #define CM_INTEN_GAINH_LSB 4 + #define CM_INTEN_GAIND_BITS 3:3 + #define CM_INTEN_GAIND_SET 0x00000008 + #define CM_INTEN_GAIND_CLR 0xfffffff7 + #define CM_INTEN_GAIND_MSB 3 + #define CM_INTEN_GAIND_LSB 3 + #define CM_INTEN_GAINC_BITS 2:2 + #define CM_INTEN_GAINC_SET 0x00000004 + #define CM_INTEN_GAINC_CLR 0xfffffffb + #define CM_INTEN_GAINC_MSB 2 + #define CM_INTEN_GAINC_LSB 2 + #define CM_INTEN_GAINB_BITS 1:1 + #define CM_INTEN_GAINB_SET 0x00000002 + #define CM_INTEN_GAINB_CLR 0xfffffffd + #define CM_INTEN_GAINB_MSB 1 + #define CM_INTEN_GAINB_LSB 1 + #define CM_INTEN_GAINA_BITS 0:0 + #define CM_INTEN_GAINA_SET 0x00000001 + #define CM_INTEN_GAINA_CLR 0xfffffffe + #define CM_INTEN_GAINA_MSB 0 + #define CM_INTEN_GAINA_LSB 0 +#define CM_DSI0HSCK HW_REGISTER_RW( 0x7e101120 ) + #define CM_DSI0HSCK_MASK 0x00000001 + #define CM_DSI0HSCK_WIDTH 1 + #define CM_DSI0HSCK_RESET 0000000000 + #define CM_DSI0HSCK_SELPLLD_BITS 0:0 + #define CM_DSI0HSCK_SELPLLD_SET 0x00000001 + #define CM_DSI0HSCK_SELPLLD_CLR 0xfffffffe + #define CM_DSI0HSCK_SELPLLD_MSB 0 + #define CM_DSI0HSCK_SELPLLD_LSB 0 +#define CM_CKSM HW_REGISTER_RW( 0x7e101124 ) + #define CM_CKSM_MASK 0x003fffff + #define CM_CKSM_WIDTH 22 + #define CM_CKSM_RESET 0000000000 + #define CM_CKSM_STEP_BITS 21:21 + #define CM_CKSM_STEP_SET 0x00200000 + #define CM_CKSM_STEP_CLR 0xffdfffff + #define CM_CKSM_STEP_MSB 21 + #define CM_CKSM_STEP_LSB 21 + #define CM_CKSM_AUTO_BITS 20:20 + #define CM_CKSM_AUTO_SET 0x00100000 + #define CM_CKSM_AUTO_CLR 0xffefffff + #define CM_CKSM_AUTO_MSB 20 + #define CM_CKSM_AUTO_LSB 20 + #define CM_CKSM_OSC_BITS 19:18 + #define CM_CKSM_OSC_SET 0x000c0000 + #define CM_CKSM_OSC_CLR 0xfff3ffff + #define CM_CKSM_OSC_MSB 19 + #define CM_CKSM_OSC_LSB 18 + #define CM_CKSM_CFG_BITS 17:16 + #define CM_CKSM_CFG_SET 0x00030000 + #define CM_CKSM_CFG_CLR 0xfffcffff + #define CM_CKSM_CFG_MSB 17 + #define CM_CKSM_CFG_LSB 16 + #define CM_CKSM_FRCE_BITS 15:8 + #define CM_CKSM_FRCE_SET 0x0000ff00 + #define CM_CKSM_FRCE_CLR 0xffff00ff + #define CM_CKSM_FRCE_MSB 15 + #define CM_CKSM_FRCE_LSB 8 + #define CM_CKSM_STATE_BITS 7:0 + #define CM_CKSM_STATE_SET 0x000000ff + #define CM_CKSM_STATE_CLR 0xffffff00 + #define CM_CKSM_STATE_MSB 7 + #define CM_CKSM_STATE_LSB 0 +#define CM_OSCFREQI HW_REGISTER_RW( 0x7e101128 ) + #define CM_OSCFREQI_MASK 0x000000ff + #define CM_OSCFREQI_WIDTH 8 + #define CM_OSCFREQI_RESET 0000000000 + #define CM_OSCFREQI_INT_BITS 7:0 + #define CM_OSCFREQI_INT_SET 0x000000ff + #define CM_OSCFREQI_INT_CLR 0xffffff00 + #define CM_OSCFREQI_INT_MSB 7 + #define CM_OSCFREQI_INT_LSB 0 +#define CM_OSCFREQF HW_REGISTER_RW( 0x7e10112c ) + #define CM_OSCFREQF_MASK 0x000fffff + #define CM_OSCFREQF_WIDTH 20 + #define CM_OSCFREQF_RESET 0000000000 + #define CM_OSCFREQF_FRAC_BITS 19:0 + #define CM_OSCFREQF_FRAC_SET 0x000fffff + #define CM_OSCFREQF_FRAC_CLR 0xfff00000 + #define CM_OSCFREQF_FRAC_MSB 19 + #define CM_OSCFREQF_FRAC_LSB 0 +#define CM_PLLTCTL HW_REGISTER_RW( 0x7e101130 ) + #define CM_PLLTCTL_MASK 0x000000a7 + #define CM_PLLTCTL_WIDTH 8 + #define CM_PLLTCTL_RESET 0000000000 + #define CM_PLLTCTL_BUSY_BITS 7:7 + #define CM_PLLTCTL_BUSY_SET 0x00000080 + #define CM_PLLTCTL_BUSY_CLR 0xffffff7f + #define CM_PLLTCTL_BUSY_MSB 7 + #define CM_PLLTCTL_BUSY_LSB 7 + #define CM_PLLTCTL_KILL_BITS 5:5 + #define CM_PLLTCTL_KILL_SET 0x00000020 + #define CM_PLLTCTL_KILL_CLR 0xffffffdf + #define CM_PLLTCTL_KILL_MSB 5 + #define CM_PLLTCTL_KILL_LSB 5 + #define CM_PLLTCTL_SRC_BITS 2:0 + #define CM_PLLTCTL_SRC_SET 0x00000007 + #define CM_PLLTCTL_SRC_CLR 0xfffffff8 + #define CM_PLLTCTL_SRC_MSB 2 + #define CM_PLLTCTL_SRC_LSB 0 +#define CM_PLLTCNT0 HW_REGISTER_RW( 0x7e101134 ) + #define CM_PLLTCNT0_MASK 0x00ffffff + #define CM_PLLTCNT0_WIDTH 24 + #define CM_PLLTCNT0_RESET 0000000000 + #define CM_PLLTCNT0_CNT_BITS 23:0 + #define CM_PLLTCNT0_CNT_SET 0x00ffffff + #define CM_PLLTCNT0_CNT_CLR 0xff000000 + #define CM_PLLTCNT0_CNT_MSB 23 + #define CM_PLLTCNT0_CNT_LSB 0 +#define CM_PLLTCNT1 HW_REGISTER_RW( 0x7e101138 ) + #define CM_PLLTCNT1_MASK 0x00ffffff + #define CM_PLLTCNT1_WIDTH 24 + #define CM_PLLTCNT1_RESET 0000000000 + #define CM_PLLTCNT1_CNT_BITS 23:0 + #define CM_PLLTCNT1_CNT_SET 0x00ffffff + #define CM_PLLTCNT1_CNT_CLR 0xff000000 + #define CM_PLLTCNT1_CNT_MSB 23 + #define CM_PLLTCNT1_CNT_LSB 0 +#define CM_PLLTCNT2 HW_REGISTER_RW( 0x7e10113c ) + #define CM_PLLTCNT2_MASK 0x00ffffff + #define CM_PLLTCNT2_WIDTH 24 + #define CM_PLLTCNT2_RESET 0000000000 + #define CM_PLLTCNT2_CNT_BITS 23:0 + #define CM_PLLTCNT2_CNT_SET 0x00ffffff + #define CM_PLLTCNT2_CNT_CLR 0xff000000 + #define CM_PLLTCNT2_CNT_MSB 23 + #define CM_PLLTCNT2_CNT_LSB 0 +#define CM_PLLTCNT3 HW_REGISTER_RW( 0x7e101140 ) + #define CM_PLLTCNT3_MASK 0x00ffffff + #define CM_PLLTCNT3_WIDTH 24 + #define CM_PLLTCNT3_RESET 0000000000 + #define CM_PLLTCNT3_CNT_BITS 23:0 + #define CM_PLLTCNT3_CNT_SET 0x00ffffff + #define CM_PLLTCNT3_CNT_CLR 0xff000000 + #define CM_PLLTCNT3_CNT_MSB 23 + #define CM_PLLTCNT3_CNT_LSB 0 +#define CM_TDCLKEN HW_REGISTER_RW( 0x7e101144 ) + #define CM_TDCLKEN_MASK 0x00003fff + #define CM_TDCLKEN_WIDTH 14 + #define CM_TDCLKEN_RESET 0000000000 + #define CM_TDCLKEN_IMAGETD_BITS 13:13 + #define CM_TDCLKEN_IMAGETD_SET 0x00002000 + #define CM_TDCLKEN_IMAGETD_CLR 0xffffdfff + #define CM_TDCLKEN_IMAGETD_MSB 13 + #define CM_TDCLKEN_IMAGETD_LSB 13 + #define CM_TDCLKEN_SLIMDFT_BITS 12:12 + #define CM_TDCLKEN_SLIMDFT_SET 0x00001000 + #define CM_TDCLKEN_SLIMDFT_CLR 0xffffefff + #define CM_TDCLKEN_SLIMDFT_MSB 12 + #define CM_TDCLKEN_SLIMDFT_LSB 12 + #define CM_TDCLKEN_USBDFT_BITS 11:11 + #define CM_TDCLKEN_USBDFT_SET 0x00000800 + #define CM_TDCLKEN_USBDFT_CLR 0xfffff7ff + #define CM_TDCLKEN_USBDFT_MSB 11 + #define CM_TDCLKEN_USBDFT_LSB 11 + #define CM_TDCLKEN_MPHIRDFT_BITS 10:10 + #define CM_TDCLKEN_MPHIRDFT_SET 0x00000400 + #define CM_TDCLKEN_MPHIRDFT_CLR 0xfffffbff + #define CM_TDCLKEN_MPHIRDFT_MSB 10 + #define CM_TDCLKEN_MPHIRDFT_LSB 10 + #define CM_TDCLKEN_MPHIWDFT_BITS 9:9 + #define CM_TDCLKEN_MPHIWDFT_SET 0x00000200 + #define CM_TDCLKEN_MPHIWDFT_CLR 0xfffffdff + #define CM_TDCLKEN_MPHIWDFT_MSB 9 + #define CM_TDCLKEN_MPHIWDFT_LSB 9 + #define CM_TDCLKEN_HDMIBYP_BITS 8:8 + #define CM_TDCLKEN_HDMIBYP_SET 0x00000100 + #define CM_TDCLKEN_HDMIBYP_CLR 0xfffffeff + #define CM_TDCLKEN_HDMIBYP_MSB 8 + #define CM_TDCLKEN_HDMIBYP_LSB 8 + #define CM_TDCLKEN_PLLDDIV2_BITS 7:7 + #define CM_TDCLKEN_PLLDDIV2_SET 0x00000080 + #define CM_TDCLKEN_PLLDDIV2_CLR 0xffffff7f + #define CM_TDCLKEN_PLLDDIV2_MSB 7 + #define CM_TDCLKEN_PLLDDIV2_LSB 7 + #define CM_TDCLKEN_PLLCDIV2_BITS 6:6 + #define CM_TDCLKEN_PLLCDIV2_SET 0x00000040 + #define CM_TDCLKEN_PLLCDIV2_CLR 0xffffffbf + #define CM_TDCLKEN_PLLCDIV2_MSB 6 + #define CM_TDCLKEN_PLLCDIV2_LSB 6 + #define CM_TDCLKEN_PLLBDIV2_BITS 5:5 + #define CM_TDCLKEN_PLLBDIV2_SET 0x00000020 + #define CM_TDCLKEN_PLLBDIV2_CLR 0xffffffdf + #define CM_TDCLKEN_PLLBDIV2_MSB 5 + #define CM_TDCLKEN_PLLBDIV2_LSB 5 + #define CM_TDCLKEN_PLLADIV2_BITS 4:4 + #define CM_TDCLKEN_PLLADIV2_SET 0x00000010 + #define CM_TDCLKEN_PLLADIV2_CLR 0xffffffef + #define CM_TDCLKEN_PLLADIV2_MSB 4 + #define CM_TDCLKEN_PLLADIV2_LSB 4 + #define CM_TDCLKEN_PLLDBYP_BITS 3:3 + #define CM_TDCLKEN_PLLDBYP_SET 0x00000008 + #define CM_TDCLKEN_PLLDBYP_CLR 0xfffffff7 + #define CM_TDCLKEN_PLLDBYP_MSB 3 + #define CM_TDCLKEN_PLLDBYP_LSB 3 + #define CM_TDCLKEN_PLLCBYP_BITS 2:2 + #define CM_TDCLKEN_PLLCBYP_SET 0x00000004 + #define CM_TDCLKEN_PLLCBYP_CLR 0xfffffffb + #define CM_TDCLKEN_PLLCBYP_MSB 2 + #define CM_TDCLKEN_PLLCBYP_LSB 2 + #define CM_TDCLKEN_PLLBBYP_BITS 1:1 + #define CM_TDCLKEN_PLLBBYP_SET 0x00000002 + #define CM_TDCLKEN_PLLBBYP_CLR 0xfffffffd + #define CM_TDCLKEN_PLLBBYP_MSB 1 + #define CM_TDCLKEN_PLLBBYP_LSB 1 + #define CM_TDCLKEN_PLLABYP_BITS 0:0 + #define CM_TDCLKEN_PLLABYP_SET 0x00000001 + #define CM_TDCLKEN_PLLABYP_CLR 0xfffffffe + #define CM_TDCLKEN_PLLABYP_MSB 0 + #define CM_TDCLKEN_PLLABYP_LSB 0 +#define CM_BURSTCTL HW_REGISTER_RW( 0x7e101148 ) + #define CM_BURSTCTL_MASK 0x000000b0 + #define CM_BURSTCTL_WIDTH 8 + #define CM_BURSTCTL_RESET 0000000000 + #define CM_BURSTCTL_BUSY_BITS 7:7 + #define CM_BURSTCTL_BUSY_SET 0x00000080 + #define CM_BURSTCTL_BUSY_CLR 0xffffff7f + #define CM_BURSTCTL_BUSY_MSB 7 + #define CM_BURSTCTL_BUSY_LSB 7 + #define CM_BURSTCTL_KILL_BITS 5:5 + #define CM_BURSTCTL_KILL_SET 0x00000020 + #define CM_BURSTCTL_KILL_CLR 0xffffffdf + #define CM_BURSTCTL_KILL_MSB 5 + #define CM_BURSTCTL_KILL_LSB 5 + #define CM_BURSTCTL_ENAB_BITS 4:4 + #define CM_BURSTCTL_ENAB_SET 0x00000010 + #define CM_BURSTCTL_ENAB_CLR 0xffffffef + #define CM_BURSTCTL_ENAB_MSB 4 + #define CM_BURSTCTL_ENAB_LSB 4 +#define CM_BURSTCNT HW_REGISTER_RW( 0x7e10114c ) + #define CM_BURSTCNT_MASK 0x00ffffff + #define CM_BURSTCNT_WIDTH 24 + #define CM_BURSTCNT_RESET 0000000000 + #define CM_BURSTCNT_CNT_BITS 23:0 + #define CM_BURSTCNT_CNT_SET 0x00ffffff + #define CM_BURSTCNT_CNT_CLR 0xff000000 + #define CM_BURSTCNT_CNT_MSB 23 + #define CM_BURSTCNT_CNT_LSB 0 diff --git a/bcm2708_chip/cpr_clkman_a0.h b/bcm2708_chip/cpr_clkman_a0.h new file mode 100755 index 0000000..f6ffc46 --- /dev/null +++ b/bcm2708_chip/cpr_clkman_a0.h @@ -0,0 +1,4299 @@ +#ifndef __BCM2708A0__ + + +#define CM_SMPSCTL HW_REGISTER_RW( 0x7e1010b8 ) + #define CM_SMPSCTL_MASK 0x000000f3 + #define CM_SMPSCTL_WIDTH 8 + #define CM_SMPSCTL_RESET 0000000000 + #define CM_SMPSCTL_BUSY_BITS 7:7 + #define CM_SMPSCTL_BUSY_SET 0x00000080 + #define CM_SMPSCTL_BUSY_CLR 0xffffff7f + #define CM_SMPSCTL_BUSY_MSB 7 + #define CM_SMPSCTL_BUSY_LSB 7 + #define CM_SMPSCTL_GATE_BITS 6:6 + #define CM_SMPSCTL_GATE_SET 0x00000040 + #define CM_SMPSCTL_GATE_CLR 0xffffffbf + #define CM_SMPSCTL_GATE_MSB 6 + #define CM_SMPSCTL_GATE_LSB 6 + #define CM_SMPSCTL_KILL_BITS 5:5 + #define CM_SMPSCTL_KILL_SET 0x00000020 + #define CM_SMPSCTL_KILL_CLR 0xffffffdf + #define CM_SMPSCTL_KILL_MSB 5 + #define CM_SMPSCTL_KILL_LSB 5 + #define CM_SMPSCTL_ENAB_BITS 4:4 + #define CM_SMPSCTL_ENAB_SET 0x00000010 + #define CM_SMPSCTL_ENAB_CLR 0xffffffef + #define CM_SMPSCTL_ENAB_MSB 4 + #define CM_SMPSCTL_ENAB_LSB 4 + #define CM_SMPSCTL_SRC_BITS 1:0 + #define CM_SMPSCTL_SRC_SET 0x00000003 + #define CM_SMPSCTL_SRC_CLR 0xfffffffc + #define CM_SMPSCTL_SRC_MSB 1 + #define CM_SMPSCTL_SRC_LSB 0 +#define CM_SMPSDIV HW_REGISTER_RW( 0x7e1010bc ) + #define CM_SMPSDIV_MASK 0x00007000 + #define CM_SMPSDIV_WIDTH 15 + #define CM_SMPSDIV_RESET 0000000000 + #define CM_SMPSDIV_DIV_BITS 14:12 + #define CM_SMPSDIV_DIV_SET 0x00007000 + #define CM_SMPSDIV_DIV_CLR 0xffff8fff + #define CM_SMPSDIV_DIV_MSB 14 + #define CM_SMPSDIV_DIV_LSB 12 + + +// This file was generated by the create_regs script +#define CM_PASSWORD 0x5a000000 +#define CM_BASE 0x7e101000 +#define CM_APB_ID 0x0000636d +#define CM_GNRICCTL HW_REGISTER_RW( 0x7e101000 ) + #define CM_GNRICCTL_MASK 0x000fffff + #define CM_GNRICCTL_WIDTH 20 + #define CM_GNRICCTL_RESET 0000000000 + #define CM_GNRICCTL_FLIP_BITS 11:11 + #define CM_GNRICCTL_FLIP_SET 0x00000800 + #define CM_GNRICCTL_FLIP_CLR 0xfffff7ff + #define CM_GNRICCTL_FLIP_MSB 11 + #define CM_GNRICCTL_FLIP_LSB 11 + #define CM_GNRICCTL_MASH_BITS 10:9 + #define CM_GNRICCTL_MASH_SET 0x00000600 + #define CM_GNRICCTL_MASH_CLR 0xfffff9ff + #define CM_GNRICCTL_MASH_MSB 10 + #define CM_GNRICCTL_MASH_LSB 9 + #define CM_GNRICCTL_BUSYD_BITS 8:8 + #define CM_GNRICCTL_BUSYD_SET 0x00000100 + #define CM_GNRICCTL_BUSYD_CLR 0xfffffeff + #define CM_GNRICCTL_BUSYD_MSB 8 + #define CM_GNRICCTL_BUSYD_LSB 8 + #define CM_GNRICCTL_BUSY_BITS 7:7 + #define CM_GNRICCTL_BUSY_SET 0x00000080 + #define CM_GNRICCTL_BUSY_CLR 0xffffff7f + #define CM_GNRICCTL_BUSY_MSB 7 + #define CM_GNRICCTL_BUSY_LSB 7 + #define CM_GNRICCTL_GATE_BITS 6:6 + #define CM_GNRICCTL_GATE_SET 0x00000040 + #define CM_GNRICCTL_GATE_CLR 0xffffffbf + #define CM_GNRICCTL_GATE_MSB 6 + #define CM_GNRICCTL_GATE_LSB 6 + #define CM_GNRICCTL_KILL_BITS 5:5 + #define CM_GNRICCTL_KILL_SET 0x00000020 + #define CM_GNRICCTL_KILL_CLR 0xffffffdf + #define CM_GNRICCTL_KILL_MSB 5 + #define CM_GNRICCTL_KILL_LSB 5 + #define CM_GNRICCTL_ENAB_BITS 4:4 + #define CM_GNRICCTL_ENAB_SET 0x00000010 + #define CM_GNRICCTL_ENAB_CLR 0xffffffef + #define CM_GNRICCTL_ENAB_MSB 4 + #define CM_GNRICCTL_ENAB_LSB 4 + #define CM_GNRICCTL_SRC_BITS 3:0 + #define CM_GNRICCTL_SRC_SET 0x0000000f + #define CM_GNRICCTL_SRC_CLR 0xfffffff0 + #define CM_GNRICCTL_SRC_MSB 3 + #define CM_GNRICCTL_SRC_LSB 0 +#define CM_GNRICDIV HW_REGISTER_RW( 0x7e101004 ) + #define CM_GNRICDIV_MASK 0x00ffffff + #define CM_GNRICDIV_WIDTH 24 + #define CM_GNRICDIV_RESET 0000000000 + #define CM_GNRICDIV_DIV_BITS 23:0 + #define CM_GNRICDIV_DIV_SET 0x00ffffff + #define CM_GNRICDIV_DIV_CLR 0xff000000 + #define CM_GNRICDIV_DIV_MSB 23 + #define CM_GNRICDIV_DIV_LSB 0 +#define CM_VPUCTL HW_REGISTER_RW( 0x7e101008 ) + #define CM_VPUCTL_MASK 0x000003cf + #define CM_VPUCTL_WIDTH 10 + #define CM_VPUCTL_RESET 0x00000041 + #define CM_VPUCTL_FRAC_BITS 9:9 + #define CM_VPUCTL_FRAC_SET 0x00000200 + #define CM_VPUCTL_FRAC_CLR 0xfffffdff + #define CM_VPUCTL_FRAC_MSB 9 + #define CM_VPUCTL_FRAC_LSB 9 + #define CM_VPUCTL_BUSYD_BITS 8:8 + #define CM_VPUCTL_BUSYD_SET 0x00000100 + #define CM_VPUCTL_BUSYD_CLR 0xfffffeff + #define CM_VPUCTL_BUSYD_MSB 8 + #define CM_VPUCTL_BUSYD_LSB 8 + #define CM_VPUCTL_BUSY_BITS 7:7 + #define CM_VPUCTL_BUSY_SET 0x00000080 + #define CM_VPUCTL_BUSY_CLR 0xffffff7f + #define CM_VPUCTL_BUSY_MSB 7 + #define CM_VPUCTL_BUSY_LSB 7 + #define CM_VPUCTL_GATE_BITS 6:6 + #define CM_VPUCTL_GATE_SET 0x00000040 + #define CM_VPUCTL_GATE_CLR 0xffffffbf + #define CM_VPUCTL_GATE_MSB 6 + #define CM_VPUCTL_GATE_LSB 6 + #define CM_VPUCTL_SRC_BITS 3:0 + #define CM_VPUCTL_SRC_SET 0x0000000f + #define CM_VPUCTL_SRC_CLR 0xfffffff0 + #define CM_VPUCTL_SRC_MSB 3 + #define CM_VPUCTL_SRC_LSB 0 +#define CM_VPUDIV HW_REGISTER_RW( 0x7e10100c ) + #define CM_VPUDIV_MASK 0x00fffff0 + #define CM_VPUDIV_WIDTH 24 + #define CM_VPUDIV_RESET 0x00001000 + #define CM_VPUDIV_DIV_BITS 23:4 + #define CM_VPUDIV_DIV_SET 0x00fffff0 + #define CM_VPUDIV_DIV_CLR 0xff00000f + #define CM_VPUDIV_DIV_MSB 23 + #define CM_VPUDIV_DIV_LSB 4 +#define CM_SYSCTL HW_REGISTER_RW( 0x7e101010 ) + #define CM_SYSCTL_MASK 0x00000040 + #define CM_SYSCTL_WIDTH 7 + #define CM_SYSCTL_RESET 0x00000040 + #define CM_SYSCTL_GATE_BITS 6:6 + #define CM_SYSCTL_GATE_SET 0x00000040 + #define CM_SYSCTL_GATE_CLR 0xffffffbf + #define CM_SYSCTL_GATE_MSB 6 + #define CM_SYSCTL_GATE_LSB 6 +#define CM_SYSDIV HW_REGISTER_RO( 0x7e101014 ) + #define CM_SYSDIV_MASK 0x00001000 + #define CM_SYSDIV_WIDTH 13 + #define CM_SYSDIV_RESET 0x00001000 + #define CM_SYSDIV_DIV_BITS 12:12 + #define CM_SYSDIV_DIV_SET 0x00001000 + #define CM_SYSDIV_DIV_CLR 0xffffefff + #define CM_SYSDIV_DIV_MSB 12 + #define CM_SYSDIV_DIV_LSB 12 +#define CM_PERIACTL HW_REGISTER_RW( 0x7e101018 ) + #define CM_PERIACTL_MASK 0x00000040 + #define CM_PERIACTL_WIDTH 7 + #define CM_PERIACTL_RESET 0x00000040 + #define CM_PERIACTL_GATE_BITS 6:6 + #define CM_PERIACTL_GATE_SET 0x00000040 + #define CM_PERIACTL_GATE_CLR 0xffffffbf + #define CM_PERIACTL_GATE_MSB 6 + #define CM_PERIACTL_GATE_LSB 6 +#define CM_PERIADIV HW_REGISTER_RO( 0x7e10101c ) + #define CM_PERIADIV_MASK 0x00001000 + #define CM_PERIADIV_WIDTH 13 + #define CM_PERIADIV_RESET 0x00001000 + #define CM_PERIADIV_DIV_BITS 12:12 + #define CM_PERIADIV_DIV_SET 0x00001000 + #define CM_PERIADIV_DIV_CLR 0xffffefff + #define CM_PERIADIV_DIV_MSB 12 + #define CM_PERIADIV_DIV_LSB 12 +#define CM_PERIICTL HW_REGISTER_RW( 0x7e101020 ) + #define CM_PERIICTL_MASK 0x00000040 + #define CM_PERIICTL_WIDTH 7 + #define CM_PERIICTL_RESET 0000000000 + #define CM_PERIICTL_GATE_BITS 6:6 + #define CM_PERIICTL_GATE_SET 0x00000040 + #define CM_PERIICTL_GATE_CLR 0xffffffbf + #define CM_PERIICTL_GATE_MSB 6 + #define CM_PERIICTL_GATE_LSB 6 +#define CM_PERIIDIV HW_REGISTER_RO( 0x7e101024 ) + #define CM_PERIIDIV_MASK 0x00001000 + #define CM_PERIIDIV_WIDTH 13 + #define CM_PERIIDIV_RESET 0x00001000 + #define CM_PERIIDIV_DIV_BITS 12:12 + #define CM_PERIIDIV_DIV_SET 0x00001000 + #define CM_PERIIDIV_DIV_CLR 0xffffefff + #define CM_PERIIDIV_DIV_MSB 12 + #define CM_PERIIDIV_DIV_LSB 12 +#define CM_H264CTL HW_REGISTER_RW( 0x7e101028 ) + #define CM_H264CTL_MASK 0x000003ff + #define CM_H264CTL_WIDTH 10 + #define CM_H264CTL_RESET 0x00000040 + #define CM_H264CTL_FRAC_BITS 9:9 + #define CM_H264CTL_FRAC_SET 0x00000200 + #define CM_H264CTL_FRAC_CLR 0xfffffdff + #define CM_H264CTL_FRAC_MSB 9 + #define CM_H264CTL_FRAC_LSB 9 + #define CM_H264CTL_BUSYD_BITS 8:8 + #define CM_H264CTL_BUSYD_SET 0x00000100 + #define CM_H264CTL_BUSYD_CLR 0xfffffeff + #define CM_H264CTL_BUSYD_MSB 8 + #define CM_H264CTL_BUSYD_LSB 8 + #define CM_H264CTL_BUSY_BITS 7:7 + #define CM_H264CTL_BUSY_SET 0x00000080 + #define CM_H264CTL_BUSY_CLR 0xffffff7f + #define CM_H264CTL_BUSY_MSB 7 + #define CM_H264CTL_BUSY_LSB 7 + #define CM_H264CTL_GATE_BITS 6:6 + #define CM_H264CTL_GATE_SET 0x00000040 + #define CM_H264CTL_GATE_CLR 0xffffffbf + #define CM_H264CTL_GATE_MSB 6 + #define CM_H264CTL_GATE_LSB 6 + #define CM_H264CTL_KILL_BITS 5:5 + #define CM_H264CTL_KILL_SET 0x00000020 + #define CM_H264CTL_KILL_CLR 0xffffffdf + #define CM_H264CTL_KILL_MSB 5 + #define CM_H264CTL_KILL_LSB 5 + #define CM_H264CTL_ENAB_BITS 4:4 + #define CM_H264CTL_ENAB_SET 0x00000010 + #define CM_H264CTL_ENAB_CLR 0xffffffef + #define CM_H264CTL_ENAB_MSB 4 + #define CM_H264CTL_ENAB_LSB 4 + #define CM_H264CTL_SRC_BITS 3:0 + #define CM_H264CTL_SRC_SET 0x0000000f + #define CM_H264CTL_SRC_CLR 0xfffffff0 + #define CM_H264CTL_SRC_MSB 3 + #define CM_H264CTL_SRC_LSB 0 +#define CM_H264DIV HW_REGISTER_RW( 0x7e10102c ) + #define CM_H264DIV_MASK 0x0000fff0 + #define CM_H264DIV_WIDTH 16 + #define CM_H264DIV_RESET 0000000000 + #define CM_H264DIV_DIV_BITS 15:4 + #define CM_H264DIV_DIV_SET 0x0000fff0 + #define CM_H264DIV_DIV_CLR 0xffff000f + #define CM_H264DIV_DIV_MSB 15 + #define CM_H264DIV_DIV_LSB 4 +#define CM_ISPCTL HW_REGISTER_RW( 0x7e101030 ) + #define CM_ISPCTL_MASK 0x000003ff + #define CM_ISPCTL_WIDTH 10 + #define CM_ISPCTL_RESET 0x00000040 + #define CM_ISPCTL_FRAC_BITS 9:9 + #define CM_ISPCTL_FRAC_SET 0x00000200 + #define CM_ISPCTL_FRAC_CLR 0xfffffdff + #define CM_ISPCTL_FRAC_MSB 9 + #define CM_ISPCTL_FRAC_LSB 9 + #define CM_ISPCTL_BUSYD_BITS 8:8 + #define CM_ISPCTL_BUSYD_SET 0x00000100 + #define CM_ISPCTL_BUSYD_CLR 0xfffffeff + #define CM_ISPCTL_BUSYD_MSB 8 + #define CM_ISPCTL_BUSYD_LSB 8 + #define CM_ISPCTL_BUSY_BITS 7:7 + #define CM_ISPCTL_BUSY_SET 0x00000080 + #define CM_ISPCTL_BUSY_CLR 0xffffff7f + #define CM_ISPCTL_BUSY_MSB 7 + #define CM_ISPCTL_BUSY_LSB 7 + #define CM_ISPCTL_GATE_BITS 6:6 + #define CM_ISPCTL_GATE_SET 0x00000040 + #define CM_ISPCTL_GATE_CLR 0xffffffbf + #define CM_ISPCTL_GATE_MSB 6 + #define CM_ISPCTL_GATE_LSB 6 + #define CM_ISPCTL_KILL_BITS 5:5 + #define CM_ISPCTL_KILL_SET 0x00000020 + #define CM_ISPCTL_KILL_CLR 0xffffffdf + #define CM_ISPCTL_KILL_MSB 5 + #define CM_ISPCTL_KILL_LSB 5 + #define CM_ISPCTL_ENAB_BITS 4:4 + #define CM_ISPCTL_ENAB_SET 0x00000010 + #define CM_ISPCTL_ENAB_CLR 0xffffffef + #define CM_ISPCTL_ENAB_MSB 4 + #define CM_ISPCTL_ENAB_LSB 4 + #define CM_ISPCTL_SRC_BITS 3:0 + #define CM_ISPCTL_SRC_SET 0x0000000f + #define CM_ISPCTL_SRC_CLR 0xfffffff0 + #define CM_ISPCTL_SRC_MSB 3 + #define CM_ISPCTL_SRC_LSB 0 +#define CM_ISPDIV HW_REGISTER_RW( 0x7e101034 ) + #define CM_ISPDIV_MASK 0x0000fff0 + #define CM_ISPDIV_WIDTH 16 + #define CM_ISPDIV_RESET 0000000000 + #define CM_ISPDIV_DIV_BITS 15:4 + #define CM_ISPDIV_DIV_SET 0x0000fff0 + #define CM_ISPDIV_DIV_CLR 0xffff000f + #define CM_ISPDIV_DIV_MSB 15 + #define CM_ISPDIV_DIV_LSB 4 +#define CM_ARMCTL HW_REGISTER_RW( 0x7e1011b0 ) + #define CM_ARMCTL_MASK 0x000013bf + #define CM_ARMCTL_WIDTH 13 + #define CM_ARMCTL_RESET 0x00000004 + #define CM_ARMCTL_AXIHALF_BITS 12:12 + #define CM_ARMCTL_AXIHALF_SET 0x00001000 + #define CM_ARMCTL_AXIHALF_CLR 0xffffefff + #define CM_ARMCTL_AXIHALF_MSB 12 + #define CM_ARMCTL_AXIHALF_LSB 12 + #define CM_ARMCTL_FRAC_BITS 9:9 + #define CM_ARMCTL_FRAC_SET 0x00000200 + #define CM_ARMCTL_FRAC_CLR 0xfffffdff + #define CM_ARMCTL_FRAC_MSB 9 + #define CM_ARMCTL_FRAC_LSB 9 + #define CM_ARMCTL_BUSYD_BITS 8:8 + #define CM_ARMCTL_BUSYD_SET 0x00000100 + #define CM_ARMCTL_BUSYD_CLR 0xfffffeff + #define CM_ARMCTL_BUSYD_MSB 8 + #define CM_ARMCTL_BUSYD_LSB 8 + #define CM_ARMCTL_BUSY_BITS 7:7 + #define CM_ARMCTL_BUSY_SET 0x00000080 + #define CM_ARMCTL_BUSY_CLR 0xffffff7f + #define CM_ARMCTL_BUSY_MSB 7 + #define CM_ARMCTL_BUSY_LSB 7 + #define CM_ARMCTL_KILL_BITS 5:5 + #define CM_ARMCTL_KILL_SET 0x00000020 + #define CM_ARMCTL_KILL_CLR 0xffffffdf + #define CM_ARMCTL_KILL_MSB 5 + #define CM_ARMCTL_KILL_LSB 5 + #define CM_ARMCTL_ENAB_BITS 4:4 + #define CM_ARMCTL_ENAB_SET 0x00000010 + #define CM_ARMCTL_ENAB_CLR 0xffffffef + #define CM_ARMCTL_ENAB_MSB 4 + #define CM_ARMCTL_ENAB_LSB 4 + #define CM_ARMCTL_SRC_BITS 3:0 + #define CM_ARMCTL_SRC_SET 0x0000000f + #define CM_ARMCTL_SRC_CLR 0xfffffff0 + #define CM_ARMCTL_SRC_MSB 3 + #define CM_ARMCTL_SRC_LSB 0 +#define CM_ARMDIV HW_REGISTER_RO( 0x7e1011b4 ) + #define CM_ARMDIV_MASK 0x00001000 + #define CM_ARMDIV_WIDTH 13 + #define CM_ARMDIV_RESET 0x00001000 + #define CM_ARMDIV_DIV_BITS 12:12 + #define CM_ARMDIV_DIV_SET 0x00001000 + #define CM_ARMDIV_DIV_CLR 0xffffefff + #define CM_ARMDIV_DIV_MSB 12 + #define CM_ARMDIV_DIV_LSB 12 +#define CM_SDCCTL HW_REGISTER_RW( 0x7e1011a8 ) + #define CM_SDCCTL_MASK 0x0003f3bf + #define CM_SDCCTL_WIDTH 18 + #define CM_SDCCTL_RESET 0x00004000 + #define CM_SDCCTL_UPDATE_BITS 17:17 + #define CM_SDCCTL_UPDATE_SET 0x00020000 + #define CM_SDCCTL_UPDATE_CLR 0xfffdffff + #define CM_SDCCTL_UPDATE_MSB 17 + #define CM_SDCCTL_UPDATE_LSB 17 + #define CM_SDCCTL_ACCPT_BITS 16:16 + #define CM_SDCCTL_ACCPT_SET 0x00010000 + #define CM_SDCCTL_ACCPT_CLR 0xfffeffff + #define CM_SDCCTL_ACCPT_MSB 16 + #define CM_SDCCTL_ACCPT_LSB 16 + #define CM_SDCCTL_CTRL_BITS 15:12 + #define CM_SDCCTL_CTRL_SET 0x0000f000 + #define CM_SDCCTL_CTRL_CLR 0xffff0fff + #define CM_SDCCTL_CTRL_MSB 15 + #define CM_SDCCTL_CTRL_LSB 12 + #define CM_SDCCTL_FRAC_BITS 9:9 + #define CM_SDCCTL_FRAC_SET 0x00000200 + #define CM_SDCCTL_FRAC_CLR 0xfffffdff + #define CM_SDCCTL_FRAC_MSB 9 + #define CM_SDCCTL_FRAC_LSB 9 + #define CM_SDCCTL_BUSYD_BITS 8:8 + #define CM_SDCCTL_BUSYD_SET 0x00000100 + #define CM_SDCCTL_BUSYD_CLR 0xfffffeff + #define CM_SDCCTL_BUSYD_MSB 8 + #define CM_SDCCTL_BUSYD_LSB 8 + #define CM_SDCCTL_BUSY_BITS 7:7 + #define CM_SDCCTL_BUSY_SET 0x00000080 + #define CM_SDCCTL_BUSY_CLR 0xffffff7f + #define CM_SDCCTL_BUSY_MSB 7 + #define CM_SDCCTL_BUSY_LSB 7 + #define CM_SDCCTL_KILL_BITS 5:5 + #define CM_SDCCTL_KILL_SET 0x00000020 + #define CM_SDCCTL_KILL_CLR 0xffffffdf + #define CM_SDCCTL_KILL_MSB 5 + #define CM_SDCCTL_KILL_LSB 5 + #define CM_SDCCTL_ENAB_BITS 4:4 + #define CM_SDCCTL_ENAB_SET 0x00000010 + #define CM_SDCCTL_ENAB_CLR 0xffffffef + #define CM_SDCCTL_ENAB_MSB 4 + #define CM_SDCCTL_ENAB_LSB 4 + #define CM_SDCCTL_SRC_BITS 3:0 + #define CM_SDCCTL_SRC_SET 0x0000000f + #define CM_SDCCTL_SRC_CLR 0xfffffff0 + #define CM_SDCCTL_SRC_MSB 3 + #define CM_SDCCTL_SRC_LSB 0 +#define CM_SDCDIV HW_REGISTER_RW( 0x7e1011ac ) + #define CM_SDCDIV_MASK 0x0003f000 + #define CM_SDCDIV_WIDTH 18 + #define CM_SDCDIV_RESET 0000000000 + #define CM_SDCDIV_DIV_BITS 17:12 + #define CM_SDCDIV_DIV_SET 0x0003f000 + #define CM_SDCDIV_DIV_CLR 0xfffc0fff + #define CM_SDCDIV_DIV_MSB 17 + #define CM_SDCDIV_DIV_LSB 12 +#define CM_V3DCTL HW_REGISTER_RW( 0x7e101038 ) + #define CM_V3DCTL_MASK 0x000003ff + #define CM_V3DCTL_WIDTH 10 + #define CM_V3DCTL_RESET 0x00000040 + #define CM_V3DCTL_FRAC_BITS 9:9 + #define CM_V3DCTL_FRAC_SET 0x00000200 + #define CM_V3DCTL_FRAC_CLR 0xfffffdff + #define CM_V3DCTL_FRAC_MSB 9 + #define CM_V3DCTL_FRAC_LSB 9 + #define CM_V3DCTL_BUSYD_BITS 8:8 + #define CM_V3DCTL_BUSYD_SET 0x00000100 + #define CM_V3DCTL_BUSYD_CLR 0xfffffeff + #define CM_V3DCTL_BUSYD_MSB 8 + #define CM_V3DCTL_BUSYD_LSB 8 + #define CM_V3DCTL_BUSY_BITS 7:7 + #define CM_V3DCTL_BUSY_SET 0x00000080 + #define CM_V3DCTL_BUSY_CLR 0xffffff7f + #define CM_V3DCTL_BUSY_MSB 7 + #define CM_V3DCTL_BUSY_LSB 7 + #define CM_V3DCTL_GATE_BITS 6:6 + #define CM_V3DCTL_GATE_SET 0x00000040 + #define CM_V3DCTL_GATE_CLR 0xffffffbf + #define CM_V3DCTL_GATE_MSB 6 + #define CM_V3DCTL_GATE_LSB 6 + #define CM_V3DCTL_KILL_BITS 5:5 + #define CM_V3DCTL_KILL_SET 0x00000020 + #define CM_V3DCTL_KILL_CLR 0xffffffdf + #define CM_V3DCTL_KILL_MSB 5 + #define CM_V3DCTL_KILL_LSB 5 + #define CM_V3DCTL_ENAB_BITS 4:4 + #define CM_V3DCTL_ENAB_SET 0x00000010 + #define CM_V3DCTL_ENAB_CLR 0xffffffef + #define CM_V3DCTL_ENAB_MSB 4 + #define CM_V3DCTL_ENAB_LSB 4 + #define CM_V3DCTL_SRC_BITS 3:0 + #define CM_V3DCTL_SRC_SET 0x0000000f + #define CM_V3DCTL_SRC_CLR 0xfffffff0 + #define CM_V3DCTL_SRC_MSB 3 + #define CM_V3DCTL_SRC_LSB 0 +#define CM_V3DDIV HW_REGISTER_RW( 0x7e10103c ) + #define CM_V3DDIV_MASK 0x0000fff0 + #define CM_V3DDIV_WIDTH 16 + #define CM_V3DDIV_RESET 0000000000 + #define CM_V3DDIV_DIV_BITS 15:4 + #define CM_V3DDIV_DIV_SET 0x0000fff0 + #define CM_V3DDIV_DIV_CLR 0xffff000f + #define CM_V3DDIV_DIV_MSB 15 + #define CM_V3DDIV_DIV_LSB 4 +#define CM_CAM0CTL HW_REGISTER_RW( 0x7e101040 ) + #define CM_CAM0CTL_MASK 0x000003bf + #define CM_CAM0CTL_WIDTH 10 + #define CM_CAM0CTL_RESET 0000000000 + #define CM_CAM0CTL_FRAC_BITS 9:9 + #define CM_CAM0CTL_FRAC_SET 0x00000200 + #define CM_CAM0CTL_FRAC_CLR 0xfffffdff + #define CM_CAM0CTL_FRAC_MSB 9 + #define CM_CAM0CTL_FRAC_LSB 9 + #define CM_CAM0CTL_BUSYD_BITS 8:8 + #define CM_CAM0CTL_BUSYD_SET 0x00000100 + #define CM_CAM0CTL_BUSYD_CLR 0xfffffeff + #define CM_CAM0CTL_BUSYD_MSB 8 + #define CM_CAM0CTL_BUSYD_LSB 8 + #define CM_CAM0CTL_BUSY_BITS 7:7 + #define CM_CAM0CTL_BUSY_SET 0x00000080 + #define CM_CAM0CTL_BUSY_CLR 0xffffff7f + #define CM_CAM0CTL_BUSY_MSB 7 + #define CM_CAM0CTL_BUSY_LSB 7 + #define CM_CAM0CTL_KILL_BITS 5:5 + #define CM_CAM0CTL_KILL_SET 0x00000020 + #define CM_CAM0CTL_KILL_CLR 0xffffffdf + #define CM_CAM0CTL_KILL_MSB 5 + #define CM_CAM0CTL_KILL_LSB 5 + #define CM_CAM0CTL_ENAB_BITS 4:4 + #define CM_CAM0CTL_ENAB_SET 0x00000010 + #define CM_CAM0CTL_ENAB_CLR 0xffffffef + #define CM_CAM0CTL_ENAB_MSB 4 + #define CM_CAM0CTL_ENAB_LSB 4 + #define CM_CAM0CTL_SRC_BITS 3:0 + #define CM_CAM0CTL_SRC_SET 0x0000000f + #define CM_CAM0CTL_SRC_CLR 0xfffffff0 + #define CM_CAM0CTL_SRC_MSB 3 + #define CM_CAM0CTL_SRC_LSB 0 +#define CM_CAM0DIV HW_REGISTER_RW( 0x7e101044 ) + #define CM_CAM0DIV_MASK 0x0000fff0 + #define CM_CAM0DIV_WIDTH 16 + #define CM_CAM0DIV_RESET 0000000000 + #define CM_CAM0DIV_DIV_BITS 15:4 + #define CM_CAM0DIV_DIV_SET 0x0000fff0 + #define CM_CAM0DIV_DIV_CLR 0xffff000f + #define CM_CAM0DIV_DIV_MSB 15 + #define CM_CAM0DIV_DIV_LSB 4 +#define CM_CAM1CTL HW_REGISTER_RW( 0x7e101048 ) + #define CM_CAM1CTL_MASK 0x000003bf + #define CM_CAM1CTL_WIDTH 10 + #define CM_CAM1CTL_RESET 0000000000 + #define CM_CAM1CTL_FRAC_BITS 9:9 + #define CM_CAM1CTL_FRAC_SET 0x00000200 + #define CM_CAM1CTL_FRAC_CLR 0xfffffdff + #define CM_CAM1CTL_FRAC_MSB 9 + #define CM_CAM1CTL_FRAC_LSB 9 + #define CM_CAM1CTL_BUSYD_BITS 8:8 + #define CM_CAM1CTL_BUSYD_SET 0x00000100 + #define CM_CAM1CTL_BUSYD_CLR 0xfffffeff + #define CM_CAM1CTL_BUSYD_MSB 8 + #define CM_CAM1CTL_BUSYD_LSB 8 + #define CM_CAM1CTL_BUSY_BITS 7:7 + #define CM_CAM1CTL_BUSY_SET 0x00000080 + #define CM_CAM1CTL_BUSY_CLR 0xffffff7f + #define CM_CAM1CTL_BUSY_MSB 7 + #define CM_CAM1CTL_BUSY_LSB 7 + #define CM_CAM1CTL_KILL_BITS 5:5 + #define CM_CAM1CTL_KILL_SET 0x00000020 + #define CM_CAM1CTL_KILL_CLR 0xffffffdf + #define CM_CAM1CTL_KILL_MSB 5 + #define CM_CAM1CTL_KILL_LSB 5 + #define CM_CAM1CTL_ENAB_BITS 4:4 + #define CM_CAM1CTL_ENAB_SET 0x00000010 + #define CM_CAM1CTL_ENAB_CLR 0xffffffef + #define CM_CAM1CTL_ENAB_MSB 4 + #define CM_CAM1CTL_ENAB_LSB 4 + #define CM_CAM1CTL_SRC_BITS 3:0 + #define CM_CAM1CTL_SRC_SET 0x0000000f + #define CM_CAM1CTL_SRC_CLR 0xfffffff0 + #define CM_CAM1CTL_SRC_MSB 3 + #define CM_CAM1CTL_SRC_LSB 0 +#define CM_CAM1DIV HW_REGISTER_RW( 0x7e10104c ) + #define CM_CAM1DIV_MASK 0x0000fff0 + #define CM_CAM1DIV_WIDTH 16 + #define CM_CAM1DIV_RESET 0000000000 + #define CM_CAM1DIV_DIV_BITS 15:4 + #define CM_CAM1DIV_DIV_SET 0x0000fff0 + #define CM_CAM1DIV_DIV_CLR 0xffff000f + #define CM_CAM1DIV_DIV_MSB 15 + #define CM_CAM1DIV_DIV_LSB 4 +#define CM_CCP2CTL HW_REGISTER_RW( 0x7e101050 ) + #define CM_CCP2CTL_MASK 0x00000397 + #define CM_CCP2CTL_WIDTH 10 + #define CM_CCP2CTL_RESET 0000000000 + #define CM_CCP2CTL_FRAC_BITS 9:9 + #define CM_CCP2CTL_FRAC_SET 0x00000200 + #define CM_CCP2CTL_FRAC_CLR 0xfffffdff + #define CM_CCP2CTL_FRAC_MSB 9 + #define CM_CCP2CTL_FRAC_LSB 9 + #define CM_CCP2CTL_BUSYD_BITS 8:8 + #define CM_CCP2CTL_BUSYD_SET 0x00000100 + #define CM_CCP2CTL_BUSYD_CLR 0xfffffeff + #define CM_CCP2CTL_BUSYD_MSB 8 + #define CM_CCP2CTL_BUSYD_LSB 8 + #define CM_CCP2CTL_BUSY_BITS 7:7 + #define CM_CCP2CTL_BUSY_SET 0x00000080 + #define CM_CCP2CTL_BUSY_CLR 0xffffff7f + #define CM_CCP2CTL_BUSY_MSB 7 + #define CM_CCP2CTL_BUSY_LSB 7 + #define CM_CCP2CTL_ENAB_BITS 4:4 + #define CM_CCP2CTL_ENAB_SET 0x00000010 + #define CM_CCP2CTL_ENAB_CLR 0xffffffef + #define CM_CCP2CTL_ENAB_MSB 4 + #define CM_CCP2CTL_ENAB_LSB 4 + #define CM_CCP2CTL_SRC_BITS 2:0 + #define CM_CCP2CTL_SRC_SET 0x00000007 + #define CM_CCP2CTL_SRC_CLR 0xfffffff8 + #define CM_CCP2CTL_SRC_MSB 2 + #define CM_CCP2CTL_SRC_LSB 0 +#define CM_CCP2DIV HW_REGISTER_RO( 0x7e101054 ) + #define CM_CCP2DIV_MASK 0x00001000 + #define CM_CCP2DIV_WIDTH 13 + #define CM_CCP2DIV_RESET 0x00001000 + #define CM_CCP2DIV_DIV_BITS 12:12 + #define CM_CCP2DIV_DIV_SET 0x00001000 + #define CM_CCP2DIV_DIV_CLR 0xffffefff + #define CM_CCP2DIV_DIV_MSB 12 + #define CM_CCP2DIV_DIV_LSB 12 +#define CM_DSI0ECTL HW_REGISTER_RW( 0x7e101058 ) + #define CM_DSI0ECTL_MASK 0x000003bf + #define CM_DSI0ECTL_WIDTH 10 + #define CM_DSI0ECTL_RESET 0000000000 + #define CM_DSI0ECTL_FRAC_BITS 9:9 + #define CM_DSI0ECTL_FRAC_SET 0x00000200 + #define CM_DSI0ECTL_FRAC_CLR 0xfffffdff + #define CM_DSI0ECTL_FRAC_MSB 9 + #define CM_DSI0ECTL_FRAC_LSB 9 + #define CM_DSI0ECTL_BUSYD_BITS 8:8 + #define CM_DSI0ECTL_BUSYD_SET 0x00000100 + #define CM_DSI0ECTL_BUSYD_CLR 0xfffffeff + #define CM_DSI0ECTL_BUSYD_MSB 8 + #define CM_DSI0ECTL_BUSYD_LSB 8 + #define CM_DSI0ECTL_BUSY_BITS 7:7 + #define CM_DSI0ECTL_BUSY_SET 0x00000080 + #define CM_DSI0ECTL_BUSY_CLR 0xffffff7f + #define CM_DSI0ECTL_BUSY_MSB 7 + #define CM_DSI0ECTL_BUSY_LSB 7 + #define CM_DSI0ECTL_KILL_BITS 5:5 + #define CM_DSI0ECTL_KILL_SET 0x00000020 + #define CM_DSI0ECTL_KILL_CLR 0xffffffdf + #define CM_DSI0ECTL_KILL_MSB 5 + #define CM_DSI0ECTL_KILL_LSB 5 + #define CM_DSI0ECTL_ENAB_BITS 4:4 + #define CM_DSI0ECTL_ENAB_SET 0x00000010 + #define CM_DSI0ECTL_ENAB_CLR 0xffffffef + #define CM_DSI0ECTL_ENAB_MSB 4 + #define CM_DSI0ECTL_ENAB_LSB 4 + #define CM_DSI0ECTL_SRC_BITS 3:0 + #define CM_DSI0ECTL_SRC_SET 0x0000000f + #define CM_DSI0ECTL_SRC_CLR 0xfffffff0 + #define CM_DSI0ECTL_SRC_MSB 3 + #define CM_DSI0ECTL_SRC_LSB 0 +#define CM_DSI0EDIV HW_REGISTER_RW( 0x7e10105c ) + #define CM_DSI0EDIV_MASK 0x0000fff0 + #define CM_DSI0EDIV_WIDTH 16 + #define CM_DSI0EDIV_RESET 0000000000 + #define CM_DSI0EDIV_DIV_BITS 15:4 + #define CM_DSI0EDIV_DIV_SET 0x0000fff0 + #define CM_DSI0EDIV_DIV_CLR 0xffff000f + #define CM_DSI0EDIV_DIV_MSB 15 + #define CM_DSI0EDIV_DIV_LSB 4 +#define CM_DSI0PCTL HW_REGISTER_RW( 0x7e101060 ) + #define CM_DSI0PCTL_MASK 0x0000039f + #define CM_DSI0PCTL_WIDTH 10 + #define CM_DSI0PCTL_RESET 0000000000 + #define CM_DSI0PCTL_FRAC_BITS 9:9 + #define CM_DSI0PCTL_FRAC_SET 0x00000200 + #define CM_DSI0PCTL_FRAC_CLR 0xfffffdff + #define CM_DSI0PCTL_FRAC_MSB 9 + #define CM_DSI0PCTL_FRAC_LSB 9 + #define CM_DSI0PCTL_BUSYD_BITS 8:8 + #define CM_DSI0PCTL_BUSYD_SET 0x00000100 + #define CM_DSI0PCTL_BUSYD_CLR 0xfffffeff + #define CM_DSI0PCTL_BUSYD_MSB 8 + #define CM_DSI0PCTL_BUSYD_LSB 8 + #define CM_DSI0PCTL_BUSY_BITS 7:7 + #define CM_DSI0PCTL_BUSY_SET 0x00000080 + #define CM_DSI0PCTL_BUSY_CLR 0xffffff7f + #define CM_DSI0PCTL_BUSY_MSB 7 + #define CM_DSI0PCTL_BUSY_LSB 7 + #define CM_DSI0PCTL_ENAB_BITS 4:4 + #define CM_DSI0PCTL_ENAB_SET 0x00000010 + #define CM_DSI0PCTL_ENAB_CLR 0xffffffef + #define CM_DSI0PCTL_ENAB_MSB 4 + #define CM_DSI0PCTL_ENAB_LSB 4 + #define CM_DSI0PCTL_SRC_BITS 3:0 + #define CM_DSI0PCTL_SRC_SET 0x0000000f + #define CM_DSI0PCTL_SRC_CLR 0xfffffff0 + #define CM_DSI0PCTL_SRC_MSB 3 + #define CM_DSI0PCTL_SRC_LSB 0 +#define CM_DSI0PDIV HW_REGISTER_RO( 0x7e101064 ) + #define CM_DSI0PDIV_MASK 0x00001000 + #define CM_DSI0PDIV_WIDTH 13 + #define CM_DSI0PDIV_RESET 0x00001000 + #define CM_DSI0PDIV_DIV_BITS 12:12 + #define CM_DSI0PDIV_DIV_SET 0x00001000 + #define CM_DSI0PDIV_DIV_CLR 0xffffefff + #define CM_DSI0PDIV_DIV_MSB 12 + #define CM_DSI0PDIV_DIV_LSB 12 +#define CM_DSI1ECTL HW_REGISTER_RW( 0x7e101158 ) + #define CM_DSI1ECTL_MASK 0x000003bf + #define CM_DSI1ECTL_WIDTH 10 + #define CM_DSI1ECTL_RESET 0000000000 + #define CM_DSI1ECTL_FRAC_BITS 9:9 + #define CM_DSI1ECTL_FRAC_SET 0x00000200 + #define CM_DSI1ECTL_FRAC_CLR 0xfffffdff + #define CM_DSI1ECTL_FRAC_MSB 9 + #define CM_DSI1ECTL_FRAC_LSB 9 + #define CM_DSI1ECTL_BUSYD_BITS 8:8 + #define CM_DSI1ECTL_BUSYD_SET 0x00000100 + #define CM_DSI1ECTL_BUSYD_CLR 0xfffffeff + #define CM_DSI1ECTL_BUSYD_MSB 8 + #define CM_DSI1ECTL_BUSYD_LSB 8 + #define CM_DSI1ECTL_BUSY_BITS 7:7 + #define CM_DSI1ECTL_BUSY_SET 0x00000080 + #define CM_DSI1ECTL_BUSY_CLR 0xffffff7f + #define CM_DSI1ECTL_BUSY_MSB 7 + #define CM_DSI1ECTL_BUSY_LSB 7 + #define CM_DSI1ECTL_KILL_BITS 5:5 + #define CM_DSI1ECTL_KILL_SET 0x00000020 + #define CM_DSI1ECTL_KILL_CLR 0xffffffdf + #define CM_DSI1ECTL_KILL_MSB 5 + #define CM_DSI1ECTL_KILL_LSB 5 + #define CM_DSI1ECTL_ENAB_BITS 4:4 + #define CM_DSI1ECTL_ENAB_SET 0x00000010 + #define CM_DSI1ECTL_ENAB_CLR 0xffffffef + #define CM_DSI1ECTL_ENAB_MSB 4 + #define CM_DSI1ECTL_ENAB_LSB 4 + #define CM_DSI1ECTL_SRC_BITS 3:0 + #define CM_DSI1ECTL_SRC_SET 0x0000000f + #define CM_DSI1ECTL_SRC_CLR 0xfffffff0 + #define CM_DSI1ECTL_SRC_MSB 3 + #define CM_DSI1ECTL_SRC_LSB 0 +#define CM_DSI1EDIV HW_REGISTER_RW( 0x7e10115c ) + #define CM_DSI1EDIV_MASK 0x0000fff0 + #define CM_DSI1EDIV_WIDTH 16 + #define CM_DSI1EDIV_RESET 0000000000 + #define CM_DSI1EDIV_DIV_BITS 15:4 + #define CM_DSI1EDIV_DIV_SET 0x0000fff0 + #define CM_DSI1EDIV_DIV_CLR 0xffff000f + #define CM_DSI1EDIV_DIV_MSB 15 + #define CM_DSI1EDIV_DIV_LSB 4 +#define CM_DSI1PCTL HW_REGISTER_RW( 0x7e101160 ) + #define CM_DSI1PCTL_MASK 0x0000039f + #define CM_DSI1PCTL_WIDTH 10 + #define CM_DSI1PCTL_RESET 0000000000 + #define CM_DSI1PCTL_FRAC_BITS 9:9 + #define CM_DSI1PCTL_FRAC_SET 0x00000200 + #define CM_DSI1PCTL_FRAC_CLR 0xfffffdff + #define CM_DSI1PCTL_FRAC_MSB 9 + #define CM_DSI1PCTL_FRAC_LSB 9 + #define CM_DSI1PCTL_BUSYD_BITS 8:8 + #define CM_DSI1PCTL_BUSYD_SET 0x00000100 + #define CM_DSI1PCTL_BUSYD_CLR 0xfffffeff + #define CM_DSI1PCTL_BUSYD_MSB 8 + #define CM_DSI1PCTL_BUSYD_LSB 8 + #define CM_DSI1PCTL_BUSY_BITS 7:7 + #define CM_DSI1PCTL_BUSY_SET 0x00000080 + #define CM_DSI1PCTL_BUSY_CLR 0xffffff7f + #define CM_DSI1PCTL_BUSY_MSB 7 + #define CM_DSI1PCTL_BUSY_LSB 7 + #define CM_DSI1PCTL_ENAB_BITS 4:4 + #define CM_DSI1PCTL_ENAB_SET 0x00000010 + #define CM_DSI1PCTL_ENAB_CLR 0xffffffef + #define CM_DSI1PCTL_ENAB_MSB 4 + #define CM_DSI1PCTL_ENAB_LSB 4 + #define CM_DSI1PCTL_SRC_BITS 3:0 + #define CM_DSI1PCTL_SRC_SET 0x0000000f + #define CM_DSI1PCTL_SRC_CLR 0xfffffff0 + #define CM_DSI1PCTL_SRC_MSB 3 + #define CM_DSI1PCTL_SRC_LSB 0 +#define CM_DSI1PDIV HW_REGISTER_RO( 0x7e101164 ) + #define CM_DSI1PDIV_MASK 0x00001000 + #define CM_DSI1PDIV_WIDTH 13 + #define CM_DSI1PDIV_RESET 0x00001000 + #define CM_DSI1PDIV_DIV_BITS 12:12 + #define CM_DSI1PDIV_DIV_SET 0x00001000 + #define CM_DSI1PDIV_DIV_CLR 0xffffefff + #define CM_DSI1PDIV_DIV_MSB 12 + #define CM_DSI1PDIV_DIV_LSB 12 +#define CM_DPICTL HW_REGISTER_RW( 0x7e101068 ) + #define CM_DPICTL_MASK 0x000003bf + #define CM_DPICTL_WIDTH 10 + #define CM_DPICTL_RESET 0000000000 + #define CM_DPICTL_FRAC_BITS 9:9 + #define CM_DPICTL_FRAC_SET 0x00000200 + #define CM_DPICTL_FRAC_CLR 0xfffffdff + #define CM_DPICTL_FRAC_MSB 9 + #define CM_DPICTL_FRAC_LSB 9 + #define CM_DPICTL_BUSYD_BITS 8:8 + #define CM_DPICTL_BUSYD_SET 0x00000100 + #define CM_DPICTL_BUSYD_CLR 0xfffffeff + #define CM_DPICTL_BUSYD_MSB 8 + #define CM_DPICTL_BUSYD_LSB 8 + #define CM_DPICTL_BUSY_BITS 7:7 + #define CM_DPICTL_BUSY_SET 0x00000080 + #define CM_DPICTL_BUSY_CLR 0xffffff7f + #define CM_DPICTL_BUSY_MSB 7 + #define CM_DPICTL_BUSY_LSB 7 + #define CM_DPICTL_KILL_BITS 5:5 + #define CM_DPICTL_KILL_SET 0x00000020 + #define CM_DPICTL_KILL_CLR 0xffffffdf + #define CM_DPICTL_KILL_MSB 5 + #define CM_DPICTL_KILL_LSB 5 + #define CM_DPICTL_ENAB_BITS 4:4 + #define CM_DPICTL_ENAB_SET 0x00000010 + #define CM_DPICTL_ENAB_CLR 0xffffffef + #define CM_DPICTL_ENAB_MSB 4 + #define CM_DPICTL_ENAB_LSB 4 + #define CM_DPICTL_SRC_BITS 3:0 + #define CM_DPICTL_SRC_SET 0x0000000f + #define CM_DPICTL_SRC_CLR 0xfffffff0 + #define CM_DPICTL_SRC_MSB 3 + #define CM_DPICTL_SRC_LSB 0 +#define CM_DPIDIV HW_REGISTER_RW( 0x7e10106c ) + #define CM_DPIDIV_MASK 0x0000fff0 + #define CM_DPIDIV_WIDTH 16 + #define CM_DPIDIV_RESET 0000000000 + #define CM_DPIDIV_DIV_BITS 15:4 + #define CM_DPIDIV_DIV_SET 0x0000fff0 + #define CM_DPIDIV_DIV_CLR 0xffff000f + #define CM_DPIDIV_DIV_MSB 15 + #define CM_DPIDIV_DIV_LSB 4 +#define CM_DFTCTL HW_REGISTER_RW( 0x7e101168 ) + #define CM_DFTCTL_MASK 0x000003bf + #define CM_DFTCTL_WIDTH 10 + #define CM_DFTCTL_RESET 0000000000 + #define CM_DFTCTL_FRAC_BITS 9:9 + #define CM_DFTCTL_FRAC_SET 0x00000200 + #define CM_DFTCTL_FRAC_CLR 0xfffffdff + #define CM_DFTCTL_FRAC_MSB 9 + #define CM_DFTCTL_FRAC_LSB 9 + #define CM_DFTCTL_BUSYD_BITS 8:8 + #define CM_DFTCTL_BUSYD_SET 0x00000100 + #define CM_DFTCTL_BUSYD_CLR 0xfffffeff + #define CM_DFTCTL_BUSYD_MSB 8 + #define CM_DFTCTL_BUSYD_LSB 8 + #define CM_DFTCTL_BUSY_BITS 7:7 + #define CM_DFTCTL_BUSY_SET 0x00000080 + #define CM_DFTCTL_BUSY_CLR 0xffffff7f + #define CM_DFTCTL_BUSY_MSB 7 + #define CM_DFTCTL_BUSY_LSB 7 + #define CM_DFTCTL_KILL_BITS 5:5 + #define CM_DFTCTL_KILL_SET 0x00000020 + #define CM_DFTCTL_KILL_CLR 0xffffffdf + #define CM_DFTCTL_KILL_MSB 5 + #define CM_DFTCTL_KILL_LSB 5 + #define CM_DFTCTL_ENAB_BITS 4:4 + #define CM_DFTCTL_ENAB_SET 0x00000010 + #define CM_DFTCTL_ENAB_CLR 0xffffffef + #define CM_DFTCTL_ENAB_MSB 4 + #define CM_DFTCTL_ENAB_LSB 4 + #define CM_DFTCTL_SRC_BITS 3:0 + #define CM_DFTCTL_SRC_SET 0x0000000f + #define CM_DFTCTL_SRC_CLR 0xfffffff0 + #define CM_DFTCTL_SRC_MSB 3 + #define CM_DFTCTL_SRC_LSB 0 +#define CM_DFTDIV HW_REGISTER_RW( 0x7e10116c ) + #define CM_DFTDIV_MASK 0x0001f000 + #define CM_DFTDIV_WIDTH 17 + #define CM_DFTDIV_RESET 0000000000 + #define CM_DFTDIV_DIV_BITS 16:12 + #define CM_DFTDIV_DIV_SET 0x0001f000 + #define CM_DFTDIV_DIV_CLR 0xfffe0fff + #define CM_DFTDIV_DIV_MSB 16 + #define CM_DFTDIV_DIV_LSB 12 +#define CM_GP0CTL HW_REGISTER_RW( 0x7e101070 ) + #define CM_GP0CTL_MASK 0x000007bf + #define CM_GP0CTL_WIDTH 11 + #define CM_GP0CTL_RESET 0x00000200 + #define CM_GP0CTL_MASH_BITS 10:9 + #define CM_GP0CTL_MASH_SET 0x00000600 + #define CM_GP0CTL_MASH_CLR 0xfffff9ff + #define CM_GP0CTL_MASH_MSB 10 + #define CM_GP0CTL_MASH_LSB 9 + #define CM_GP0CTL_BUSYD_BITS 8:8 + #define CM_GP0CTL_BUSYD_SET 0x00000100 + #define CM_GP0CTL_BUSYD_CLR 0xfffffeff + #define CM_GP0CTL_BUSYD_MSB 8 + #define CM_GP0CTL_BUSYD_LSB 8 + #define CM_GP0CTL_BUSY_BITS 7:7 + #define CM_GP0CTL_BUSY_SET 0x00000080 + #define CM_GP0CTL_BUSY_CLR 0xffffff7f + #define CM_GP0CTL_BUSY_MSB 7 + #define CM_GP0CTL_BUSY_LSB 7 + #define CM_GP0CTL_KILL_BITS 5:5 + #define CM_GP0CTL_KILL_SET 0x00000020 + #define CM_GP0CTL_KILL_CLR 0xffffffdf + #define CM_GP0CTL_KILL_MSB 5 + #define CM_GP0CTL_KILL_LSB 5 + #define CM_GP0CTL_ENAB_BITS 4:4 + #define CM_GP0CTL_ENAB_SET 0x00000010 + #define CM_GP0CTL_ENAB_CLR 0xffffffef + #define CM_GP0CTL_ENAB_MSB 4 + #define CM_GP0CTL_ENAB_LSB 4 + #define CM_GP0CTL_SRC_BITS 3:0 + #define CM_GP0CTL_SRC_SET 0x0000000f + #define CM_GP0CTL_SRC_CLR 0xfffffff0 + #define CM_GP0CTL_SRC_MSB 3 + #define CM_GP0CTL_SRC_LSB 0 +#define CM_GP0DIV HW_REGISTER_RW( 0x7e101074 ) + #define CM_GP0DIV_MASK 0x00ffffff + #define CM_GP0DIV_WIDTH 24 + #define CM_GP0DIV_RESET 0000000000 + #define CM_GP0DIV_DIV_BITS 23:0 + #define CM_GP0DIV_DIV_SET 0x00ffffff + #define CM_GP0DIV_DIV_CLR 0xff000000 + #define CM_GP0DIV_DIV_MSB 23 + #define CM_GP0DIV_DIV_LSB 0 +#define CM_GP1CTL HW_REGISTER_RW( 0x7e101078 ) + #define CM_GP1CTL_MASK 0x000007bf + #define CM_GP1CTL_WIDTH 11 + #define CM_GP1CTL_RESET 0x00000200 + #define CM_GP1CTL_MASH_BITS 10:9 + #define CM_GP1CTL_MASH_SET 0x00000600 + #define CM_GP1CTL_MASH_CLR 0xfffff9ff + #define CM_GP1CTL_MASH_MSB 10 + #define CM_GP1CTL_MASH_LSB 9 + #define CM_GP1CTL_BUSYD_BITS 8:8 + #define CM_GP1CTL_BUSYD_SET 0x00000100 + #define CM_GP1CTL_BUSYD_CLR 0xfffffeff + #define CM_GP1CTL_BUSYD_MSB 8 + #define CM_GP1CTL_BUSYD_LSB 8 + #define CM_GP1CTL_BUSY_BITS 7:7 + #define CM_GP1CTL_BUSY_SET 0x00000080 + #define CM_GP1CTL_BUSY_CLR 0xffffff7f + #define CM_GP1CTL_BUSY_MSB 7 + #define CM_GP1CTL_BUSY_LSB 7 + #define CM_GP1CTL_KILL_BITS 5:5 + #define CM_GP1CTL_KILL_SET 0x00000020 + #define CM_GP1CTL_KILL_CLR 0xffffffdf + #define CM_GP1CTL_KILL_MSB 5 + #define CM_GP1CTL_KILL_LSB 5 + #define CM_GP1CTL_ENAB_BITS 4:4 + #define CM_GP1CTL_ENAB_SET 0x00000010 + #define CM_GP1CTL_ENAB_CLR 0xffffffef + #define CM_GP1CTL_ENAB_MSB 4 + #define CM_GP1CTL_ENAB_LSB 4 + #define CM_GP1CTL_SRC_BITS 3:0 + #define CM_GP1CTL_SRC_SET 0x0000000f + #define CM_GP1CTL_SRC_CLR 0xfffffff0 + #define CM_GP1CTL_SRC_MSB 3 + #define CM_GP1CTL_SRC_LSB 0 +#define CM_GP1DIV HW_REGISTER_RW( 0x7e10107c ) + #define CM_GP1DIV_MASK 0x00ffffff + #define CM_GP1DIV_WIDTH 24 + #define CM_GP1DIV_RESET 0000000000 + #define CM_GP1DIV_DIV_BITS 23:0 + #define CM_GP1DIV_DIV_SET 0x00ffffff + #define CM_GP1DIV_DIV_CLR 0xff000000 + #define CM_GP1DIV_DIV_MSB 23 + #define CM_GP1DIV_DIV_LSB 0 +#define CM_GP2CTL HW_REGISTER_RW( 0x7e101080 ) + #define CM_GP2CTL_MASK 0x000003bf + #define CM_GP2CTL_WIDTH 10 + #define CM_GP2CTL_RESET 0000000000 + #define CM_GP2CTL_FRAC_BITS 9:9 + #define CM_GP2CTL_FRAC_SET 0x00000200 + #define CM_GP2CTL_FRAC_CLR 0xfffffdff + #define CM_GP2CTL_FRAC_MSB 9 + #define CM_GP2CTL_FRAC_LSB 9 + #define CM_GP2CTL_BUSYD_BITS 8:8 + #define CM_GP2CTL_BUSYD_SET 0x00000100 + #define CM_GP2CTL_BUSYD_CLR 0xfffffeff + #define CM_GP2CTL_BUSYD_MSB 8 + #define CM_GP2CTL_BUSYD_LSB 8 + #define CM_GP2CTL_BUSY_BITS 7:7 + #define CM_GP2CTL_BUSY_SET 0x00000080 + #define CM_GP2CTL_BUSY_CLR 0xffffff7f + #define CM_GP2CTL_BUSY_MSB 7 + #define CM_GP2CTL_BUSY_LSB 7 + #define CM_GP2CTL_KILL_BITS 5:5 + #define CM_GP2CTL_KILL_SET 0x00000020 + #define CM_GP2CTL_KILL_CLR 0xffffffdf + #define CM_GP2CTL_KILL_MSB 5 + #define CM_GP2CTL_KILL_LSB 5 + #define CM_GP2CTL_ENAB_BITS 4:4 + #define CM_GP2CTL_ENAB_SET 0x00000010 + #define CM_GP2CTL_ENAB_CLR 0xffffffef + #define CM_GP2CTL_ENAB_MSB 4 + #define CM_GP2CTL_ENAB_LSB 4 + #define CM_GP2CTL_SRC_BITS 3:0 + #define CM_GP2CTL_SRC_SET 0x0000000f + #define CM_GP2CTL_SRC_CLR 0xfffffff0 + #define CM_GP2CTL_SRC_MSB 3 + #define CM_GP2CTL_SRC_LSB 0 +#define CM_GP2DIV HW_REGISTER_RW( 0x7e101084 ) + #define CM_GP2DIV_MASK 0x00ffffff + #define CM_GP2DIV_WIDTH 24 + #define CM_GP2DIV_RESET 0000000000 + #define CM_GP2DIV_DIV_BITS 23:0 + #define CM_GP2DIV_DIV_SET 0x00ffffff + #define CM_GP2DIV_DIV_CLR 0xff000000 + #define CM_GP2DIV_DIV_MSB 23 + #define CM_GP2DIV_DIV_LSB 0 +#define CM_HSMCTL HW_REGISTER_RW( 0x7e101088 ) + #define CM_HSMCTL_MASK 0x000003ff + #define CM_HSMCTL_WIDTH 10 + #define CM_HSMCTL_RESET 0000000000 + #define CM_HSMCTL_FRAC_BITS 9:9 + #define CM_HSMCTL_FRAC_SET 0x00000200 + #define CM_HSMCTL_FRAC_CLR 0xfffffdff + #define CM_HSMCTL_FRAC_MSB 9 + #define CM_HSMCTL_FRAC_LSB 9 + #define CM_HSMCTL_BUSYD_BITS 8:8 + #define CM_HSMCTL_BUSYD_SET 0x00000100 + #define CM_HSMCTL_BUSYD_CLR 0xfffffeff + #define CM_HSMCTL_BUSYD_MSB 8 + #define CM_HSMCTL_BUSYD_LSB 8 + #define CM_HSMCTL_BUSY_BITS 7:7 + #define CM_HSMCTL_BUSY_SET 0x00000080 + #define CM_HSMCTL_BUSY_CLR 0xffffff7f + #define CM_HSMCTL_BUSY_MSB 7 + #define CM_HSMCTL_BUSY_LSB 7 + #define CM_HSMCTL_GATE_BITS 6:6 + #define CM_HSMCTL_GATE_SET 0x00000040 + #define CM_HSMCTL_GATE_CLR 0xffffffbf + #define CM_HSMCTL_GATE_MSB 6 + #define CM_HSMCTL_GATE_LSB 6 + #define CM_HSMCTL_KILL_BITS 5:5 + #define CM_HSMCTL_KILL_SET 0x00000020 + #define CM_HSMCTL_KILL_CLR 0xffffffdf + #define CM_HSMCTL_KILL_MSB 5 + #define CM_HSMCTL_KILL_LSB 5 + #define CM_HSMCTL_ENAB_BITS 4:4 + #define CM_HSMCTL_ENAB_SET 0x00000010 + #define CM_HSMCTL_ENAB_CLR 0xffffffef + #define CM_HSMCTL_ENAB_MSB 4 + #define CM_HSMCTL_ENAB_LSB 4 + #define CM_HSMCTL_SRC_BITS 3:0 + #define CM_HSMCTL_SRC_SET 0x0000000f + #define CM_HSMCTL_SRC_CLR 0xfffffff0 + #define CM_HSMCTL_SRC_MSB 3 + #define CM_HSMCTL_SRC_LSB 0 +#define CM_HSMDIV HW_REGISTER_RW( 0x7e10108c ) + #define CM_HSMDIV_MASK 0x0000fff0 + #define CM_HSMDIV_WIDTH 16 + #define CM_HSMDIV_RESET 0000000000 + #define CM_HSMDIV_DIV_BITS 15:4 + #define CM_HSMDIV_DIV_SET 0x0000fff0 + #define CM_HSMDIV_DIV_CLR 0xffff000f + #define CM_HSMDIV_DIV_MSB 15 + #define CM_HSMDIV_DIV_LSB 4 +#define CM_OTPCTL HW_REGISTER_RW( 0x7e101090 ) + #define CM_OTPCTL_MASK 0x000003b3 + #define CM_OTPCTL_WIDTH 10 + #define CM_OTPCTL_RESET 0x00000011 + #define CM_OTPCTL_FRAC_BITS 9:9 + #define CM_OTPCTL_FRAC_SET 0x00000200 + #define CM_OTPCTL_FRAC_CLR 0xfffffdff + #define CM_OTPCTL_FRAC_MSB 9 + #define CM_OTPCTL_FRAC_LSB 9 + #define CM_OTPCTL_BUSYD_BITS 8:8 + #define CM_OTPCTL_BUSYD_SET 0x00000100 + #define CM_OTPCTL_BUSYD_CLR 0xfffffeff + #define CM_OTPCTL_BUSYD_MSB 8 + #define CM_OTPCTL_BUSYD_LSB 8 + #define CM_OTPCTL_BUSY_BITS 7:7 + #define CM_OTPCTL_BUSY_SET 0x00000080 + #define CM_OTPCTL_BUSY_CLR 0xffffff7f + #define CM_OTPCTL_BUSY_MSB 7 + #define CM_OTPCTL_BUSY_LSB 7 + #define CM_OTPCTL_KILL_BITS 5:5 + #define CM_OTPCTL_KILL_SET 0x00000020 + #define CM_OTPCTL_KILL_CLR 0xffffffdf + #define CM_OTPCTL_KILL_MSB 5 + #define CM_OTPCTL_KILL_LSB 5 + #define CM_OTPCTL_ENAB_BITS 4:4 + #define CM_OTPCTL_ENAB_SET 0x00000010 + #define CM_OTPCTL_ENAB_CLR 0xffffffef + #define CM_OTPCTL_ENAB_MSB 4 + #define CM_OTPCTL_ENAB_LSB 4 + #define CM_OTPCTL_SRC_BITS 1:0 + #define CM_OTPCTL_SRC_SET 0x00000003 + #define CM_OTPCTL_SRC_CLR 0xfffffffc + #define CM_OTPCTL_SRC_MSB 1 + #define CM_OTPCTL_SRC_LSB 0 +#define CM_OTPDIV HW_REGISTER_RW( 0x7e101094 ) + #define CM_OTPDIV_MASK 0x0001f000 + #define CM_OTPDIV_WIDTH 17 + #define CM_OTPDIV_RESET 0x00004000 + #define CM_OTPDIV_DIV_BITS 16:12 + #define CM_OTPDIV_DIV_SET 0x0001f000 + #define CM_OTPDIV_DIV_CLR 0xfffe0fff + #define CM_OTPDIV_DIV_MSB 16 + #define CM_OTPDIV_DIV_LSB 12 +#define CM_PULSECTL HW_REGISTER_RW( 0x7e101190 ) + #define CM_PULSECTL_MASK 0x000003b3 + #define CM_PULSECTL_WIDTH 10 + #define CM_PULSECTL_RESET 0x00000011 + #define CM_PULSECTL_FRAC_BITS 9:9 + #define CM_PULSECTL_FRAC_SET 0x00000200 + #define CM_PULSECTL_FRAC_CLR 0xfffffdff + #define CM_PULSECTL_FRAC_MSB 9 + #define CM_PULSECTL_FRAC_LSB 9 + #define CM_PULSECTL_BUSYD_BITS 8:8 + #define CM_PULSECTL_BUSYD_SET 0x00000100 + #define CM_PULSECTL_BUSYD_CLR 0xfffffeff + #define CM_PULSECTL_BUSYD_MSB 8 + #define CM_PULSECTL_BUSYD_LSB 8 + #define CM_PULSECTL_BUSY_BITS 7:7 + #define CM_PULSECTL_BUSY_SET 0x00000080 + #define CM_PULSECTL_BUSY_CLR 0xffffff7f + #define CM_PULSECTL_BUSY_MSB 7 + #define CM_PULSECTL_BUSY_LSB 7 + #define CM_PULSECTL_KILL_BITS 5:5 + #define CM_PULSECTL_KILL_SET 0x00000020 + #define CM_PULSECTL_KILL_CLR 0xffffffdf + #define CM_PULSECTL_KILL_MSB 5 + #define CM_PULSECTL_KILL_LSB 5 + #define CM_PULSECTL_ENAB_BITS 4:4 + #define CM_PULSECTL_ENAB_SET 0x00000010 + #define CM_PULSECTL_ENAB_CLR 0xffffffef + #define CM_PULSECTL_ENAB_MSB 4 + #define CM_PULSECTL_ENAB_LSB 4 + #define CM_PULSECTL_SRC_BITS 1:0 + #define CM_PULSECTL_SRC_SET 0x00000003 + #define CM_PULSECTL_SRC_CLR 0xfffffffc + #define CM_PULSECTL_SRC_MSB 1 + #define CM_PULSECTL_SRC_LSB 0 +#define CM_PULSEDIV HW_REGISTER_RW( 0x7e101194 ) + #define CM_PULSEDIV_MASK 0x00fff000 + #define CM_PULSEDIV_WIDTH 24 + #define CM_PULSEDIV_RESET 0x00014000 + #define CM_PULSEDIV_DIV_BITS 23:12 + #define CM_PULSEDIV_DIV_SET 0x00fff000 + #define CM_PULSEDIV_DIV_CLR 0xff000fff + #define CM_PULSEDIV_DIV_MSB 23 + #define CM_PULSEDIV_DIV_LSB 12 +#define CM_PCMCTL HW_REGISTER_RW( 0x7e101098 ) + #define CM_PCMCTL_MASK 0x000007bf + #define CM_PCMCTL_WIDTH 11 + #define CM_PCMCTL_RESET 0x00000200 + #define CM_PCMCTL_MASH_BITS 10:9 + #define CM_PCMCTL_MASH_SET 0x00000600 + #define CM_PCMCTL_MASH_CLR 0xfffff9ff + #define CM_PCMCTL_MASH_MSB 10 + #define CM_PCMCTL_MASH_LSB 9 + #define CM_PCMCTL_BUSYD_BITS 8:8 + #define CM_PCMCTL_BUSYD_SET 0x00000100 + #define CM_PCMCTL_BUSYD_CLR 0xfffffeff + #define CM_PCMCTL_BUSYD_MSB 8 + #define CM_PCMCTL_BUSYD_LSB 8 + #define CM_PCMCTL_BUSY_BITS 7:7 + #define CM_PCMCTL_BUSY_SET 0x00000080 + #define CM_PCMCTL_BUSY_CLR 0xffffff7f + #define CM_PCMCTL_BUSY_MSB 7 + #define CM_PCMCTL_BUSY_LSB 7 + #define CM_PCMCTL_KILL_BITS 5:5 + #define CM_PCMCTL_KILL_SET 0x00000020 + #define CM_PCMCTL_KILL_CLR 0xffffffdf + #define CM_PCMCTL_KILL_MSB 5 + #define CM_PCMCTL_KILL_LSB 5 + #define CM_PCMCTL_ENAB_BITS 4:4 + #define CM_PCMCTL_ENAB_SET 0x00000010 + #define CM_PCMCTL_ENAB_CLR 0xffffffef + #define CM_PCMCTL_ENAB_MSB 4 + #define CM_PCMCTL_ENAB_LSB 4 + #define CM_PCMCTL_SRC_BITS 3:0 + #define CM_PCMCTL_SRC_SET 0x0000000f + #define CM_PCMCTL_SRC_CLR 0xfffffff0 + #define CM_PCMCTL_SRC_MSB 3 + #define CM_PCMCTL_SRC_LSB 0 +#define CM_PCMDIV HW_REGISTER_RW( 0x7e10109c ) + #define CM_PCMDIV_MASK 0x00ffffff + #define CM_PCMDIV_WIDTH 24 + #define CM_PCMDIV_RESET 0000000000 + #define CM_PCMDIV_DIV_BITS 23:0 + #define CM_PCMDIV_DIV_SET 0x00ffffff + #define CM_PCMDIV_DIV_CLR 0xff000000 + #define CM_PCMDIV_DIV_MSB 23 + #define CM_PCMDIV_DIV_LSB 0 +#define CM_PWMCTL HW_REGISTER_RW( 0x7e1010a0 ) + #define CM_PWMCTL_MASK 0x000007bf + #define CM_PWMCTL_WIDTH 11 + #define CM_PWMCTL_RESET 0x00000200 + #define CM_PWMCTL_MASH_BITS 10:9 + #define CM_PWMCTL_MASH_SET 0x00000600 + #define CM_PWMCTL_MASH_CLR 0xfffff9ff + #define CM_PWMCTL_MASH_MSB 10 + #define CM_PWMCTL_MASH_LSB 9 + #define CM_PWMCTL_BUSYD_BITS 8:8 + #define CM_PWMCTL_BUSYD_SET 0x00000100 + #define CM_PWMCTL_BUSYD_CLR 0xfffffeff + #define CM_PWMCTL_BUSYD_MSB 8 + #define CM_PWMCTL_BUSYD_LSB 8 + #define CM_PWMCTL_BUSY_BITS 7:7 + #define CM_PWMCTL_BUSY_SET 0x00000080 + #define CM_PWMCTL_BUSY_CLR 0xffffff7f + #define CM_PWMCTL_BUSY_MSB 7 + #define CM_PWMCTL_BUSY_LSB 7 + #define CM_PWMCTL_KILL_BITS 5:5 + #define CM_PWMCTL_KILL_SET 0x00000020 + #define CM_PWMCTL_KILL_CLR 0xffffffdf + #define CM_PWMCTL_KILL_MSB 5 + #define CM_PWMCTL_KILL_LSB 5 + #define CM_PWMCTL_ENAB_BITS 4:4 + #define CM_PWMCTL_ENAB_SET 0x00000010 + #define CM_PWMCTL_ENAB_CLR 0xffffffef + #define CM_PWMCTL_ENAB_MSB 4 + #define CM_PWMCTL_ENAB_LSB 4 + #define CM_PWMCTL_SRC_BITS 3:0 + #define CM_PWMCTL_SRC_SET 0x0000000f + #define CM_PWMCTL_SRC_CLR 0xfffffff0 + #define CM_PWMCTL_SRC_MSB 3 + #define CM_PWMCTL_SRC_LSB 0 +#define CM_PWMDIV HW_REGISTER_RW( 0x7e1010a4 ) + #define CM_PWMDIV_MASK 0x00ffffff + #define CM_PWMDIV_WIDTH 24 + #define CM_PWMDIV_RESET 0000000000 + #define CM_PWMDIV_DIV_BITS 23:0 + #define CM_PWMDIV_DIV_SET 0x00ffffff + #define CM_PWMDIV_DIV_CLR 0xff000000 + #define CM_PWMDIV_DIV_MSB 23 + #define CM_PWMDIV_DIV_LSB 0 +#define CM_SLIMCTL HW_REGISTER_RW( 0x7e1010a8 ) + #define CM_SLIMCTL_MASK 0x000007bf + #define CM_SLIMCTL_WIDTH 11 + #define CM_SLIMCTL_RESET 0x00000200 + #define CM_SLIMCTL_MASH_BITS 10:9 + #define CM_SLIMCTL_MASH_SET 0x00000600 + #define CM_SLIMCTL_MASH_CLR 0xfffff9ff + #define CM_SLIMCTL_MASH_MSB 10 + #define CM_SLIMCTL_MASH_LSB 9 + #define CM_SLIMCTL_BUSYD_BITS 8:8 + #define CM_SLIMCTL_BUSYD_SET 0x00000100 + #define CM_SLIMCTL_BUSYD_CLR 0xfffffeff + #define CM_SLIMCTL_BUSYD_MSB 8 + #define CM_SLIMCTL_BUSYD_LSB 8 + #define CM_SLIMCTL_BUSY_BITS 7:7 + #define CM_SLIMCTL_BUSY_SET 0x00000080 + #define CM_SLIMCTL_BUSY_CLR 0xffffff7f + #define CM_SLIMCTL_BUSY_MSB 7 + #define CM_SLIMCTL_BUSY_LSB 7 + #define CM_SLIMCTL_KILL_BITS 5:5 + #define CM_SLIMCTL_KILL_SET 0x00000020 + #define CM_SLIMCTL_KILL_CLR 0xffffffdf + #define CM_SLIMCTL_KILL_MSB 5 + #define CM_SLIMCTL_KILL_LSB 5 + #define CM_SLIMCTL_ENAB_BITS 4:4 + #define CM_SLIMCTL_ENAB_SET 0x00000010 + #define CM_SLIMCTL_ENAB_CLR 0xffffffef + #define CM_SLIMCTL_ENAB_MSB 4 + #define CM_SLIMCTL_ENAB_LSB 4 + #define CM_SLIMCTL_SRC_BITS 3:0 + #define CM_SLIMCTL_SRC_SET 0x0000000f + #define CM_SLIMCTL_SRC_CLR 0xfffffff0 + #define CM_SLIMCTL_SRC_MSB 3 + #define CM_SLIMCTL_SRC_LSB 0 +#define CM_SLIMDIV HW_REGISTER_RW( 0x7e1010ac ) + #define CM_SLIMDIV_MASK 0x00ffffff + #define CM_SLIMDIV_WIDTH 24 + #define CM_SLIMDIV_RESET 0000000000 + #define CM_SLIMDIV_DIV_BITS 23:0 + #define CM_SLIMDIV_DIV_SET 0x00ffffff + #define CM_SLIMDIV_DIV_CLR 0xff000000 + #define CM_SLIMDIV_DIV_MSB 23 + #define CM_SLIMDIV_DIV_LSB 0 +#define CM_SMICTL HW_REGISTER_RW( 0x7e1010b0 ) + #define CM_SMICTL_MASK 0x000003bf + #define CM_SMICTL_WIDTH 10 + #define CM_SMICTL_RESET 0000000000 + #define CM_SMICTL_FRAC_BITS 9:9 + #define CM_SMICTL_FRAC_SET 0x00000200 + #define CM_SMICTL_FRAC_CLR 0xfffffdff + #define CM_SMICTL_FRAC_MSB 9 + #define CM_SMICTL_FRAC_LSB 9 + #define CM_SMICTL_BUSYD_BITS 8:8 + #define CM_SMICTL_BUSYD_SET 0x00000100 + #define CM_SMICTL_BUSYD_CLR 0xfffffeff + #define CM_SMICTL_BUSYD_MSB 8 + #define CM_SMICTL_BUSYD_LSB 8 + #define CM_SMICTL_BUSY_BITS 7:7 + #define CM_SMICTL_BUSY_SET 0x00000080 + #define CM_SMICTL_BUSY_CLR 0xffffff7f + #define CM_SMICTL_BUSY_MSB 7 + #define CM_SMICTL_BUSY_LSB 7 + #define CM_SMICTL_KILL_BITS 5:5 + #define CM_SMICTL_KILL_SET 0x00000020 + #define CM_SMICTL_KILL_CLR 0xffffffdf + #define CM_SMICTL_KILL_MSB 5 + #define CM_SMICTL_KILL_LSB 5 + #define CM_SMICTL_ENAB_BITS 4:4 + #define CM_SMICTL_ENAB_SET 0x00000010 + #define CM_SMICTL_ENAB_CLR 0xffffffef + #define CM_SMICTL_ENAB_MSB 4 + #define CM_SMICTL_ENAB_LSB 4 + #define CM_SMICTL_SRC_BITS 3:0 + #define CM_SMICTL_SRC_SET 0x0000000f + #define CM_SMICTL_SRC_CLR 0xfffffff0 + #define CM_SMICTL_SRC_MSB 3 + #define CM_SMICTL_SRC_LSB 0 +#define CM_SMIDIV HW_REGISTER_RW( 0x7e1010b4 ) + #define CM_SMIDIV_MASK 0x0000fff0 + #define CM_SMIDIV_WIDTH 16 + #define CM_SMIDIV_RESET 0000000000 + #define CM_SMIDIV_DIV_BITS 15:4 + #define CM_SMIDIV_DIV_SET 0x0000fff0 + #define CM_SMIDIV_DIV_CLR 0xffff000f + #define CM_SMIDIV_DIV_MSB 15 + #define CM_SMIDIV_DIV_LSB 4 +#define CM_TCNTCTL HW_REGISTER_RW( 0x7e1010c0 ) + #define CM_TCNTCTL_MASK 0x000030cf + #define CM_TCNTCTL_WIDTH 14 + #define CM_TCNTCTL_RESET 0000000000 + #define CM_TCNTCTL_SRC1_BITS 13:12 + #define CM_TCNTCTL_SRC1_SET 0x00003000 + #define CM_TCNTCTL_SRC1_CLR 0xffffcfff + #define CM_TCNTCTL_SRC1_MSB 13 + #define CM_TCNTCTL_SRC1_LSB 12 + #define CM_TCNTCTL_BUSY_BITS 7:7 + #define CM_TCNTCTL_BUSY_SET 0x00000080 + #define CM_TCNTCTL_BUSY_CLR 0xffffff7f + #define CM_TCNTCTL_BUSY_MSB 7 + #define CM_TCNTCTL_BUSY_LSB 7 + #define CM_TCNTCTL_KILL_BITS 6:6 + #define CM_TCNTCTL_KILL_SET 0x00000040 + #define CM_TCNTCTL_KILL_CLR 0xffffffbf + #define CM_TCNTCTL_KILL_MSB 6 + #define CM_TCNTCTL_KILL_LSB 6 + #define CM_TCNTCTL_SRC0_BITS 3:0 + #define CM_TCNTCTL_SRC0_SET 0x0000000f + #define CM_TCNTCTL_SRC0_CLR 0xfffffff0 + #define CM_TCNTCTL_SRC0_MSB 3 + #define CM_TCNTCTL_SRC0_LSB 0 +#define CM_TCNTCNT HW_REGISTER_RW( 0x7e1010c4 ) + #define CM_TCNTCNT_MASK 0x00ffffff + #define CM_TCNTCNT_WIDTH 24 + #define CM_TCNTCNT_RESET 0000000000 + #define CM_TCNTCNT_CNT_BITS 23:0 + #define CM_TCNTCNT_CNT_SET 0x00ffffff + #define CM_TCNTCNT_CNT_CLR 0xff000000 + #define CM_TCNTCNT_CNT_MSB 23 + #define CM_TCNTCNT_CNT_LSB 0 +#define CM_TECCTL HW_REGISTER_RW( 0x7e1010c8 ) + #define CM_TECCTL_MASK 0x000003b3 + #define CM_TECCTL_WIDTH 10 + #define CM_TECCTL_RESET 0000000000 + #define CM_TECCTL_FRAC_BITS 9:9 + #define CM_TECCTL_FRAC_SET 0x00000200 + #define CM_TECCTL_FRAC_CLR 0xfffffdff + #define CM_TECCTL_FRAC_MSB 9 + #define CM_TECCTL_FRAC_LSB 9 + #define CM_TECCTL_BUSYD_BITS 8:8 + #define CM_TECCTL_BUSYD_SET 0x00000100 + #define CM_TECCTL_BUSYD_CLR 0xfffffeff + #define CM_TECCTL_BUSYD_MSB 8 + #define CM_TECCTL_BUSYD_LSB 8 + #define CM_TECCTL_BUSY_BITS 7:7 + #define CM_TECCTL_BUSY_SET 0x00000080 + #define CM_TECCTL_BUSY_CLR 0xffffff7f + #define CM_TECCTL_BUSY_MSB 7 + #define CM_TECCTL_BUSY_LSB 7 + #define CM_TECCTL_KILL_BITS 5:5 + #define CM_TECCTL_KILL_SET 0x00000020 + #define CM_TECCTL_KILL_CLR 0xffffffdf + #define CM_TECCTL_KILL_MSB 5 + #define CM_TECCTL_KILL_LSB 5 + #define CM_TECCTL_ENAB_BITS 4:4 + #define CM_TECCTL_ENAB_SET 0x00000010 + #define CM_TECCTL_ENAB_CLR 0xffffffef + #define CM_TECCTL_ENAB_MSB 4 + #define CM_TECCTL_ENAB_LSB 4 + #define CM_TECCTL_SRC_BITS 1:0 + #define CM_TECCTL_SRC_SET 0x00000003 + #define CM_TECCTL_SRC_CLR 0xfffffffc + #define CM_TECCTL_SRC_MSB 1 + #define CM_TECCTL_SRC_LSB 0 +#define CM_TECDIV HW_REGISTER_RW( 0x7e1010cc ) + #define CM_TECDIV_MASK 0x0003f000 + #define CM_TECDIV_WIDTH 18 + #define CM_TECDIV_RESET 0000000000 + #define CM_TECDIV_DIV_BITS 17:12 + #define CM_TECDIV_DIV_SET 0x0003f000 + #define CM_TECDIV_DIV_CLR 0xfffc0fff + #define CM_TECDIV_DIV_MSB 17 + #define CM_TECDIV_DIV_LSB 12 +#define CM_TD0CTL HW_REGISTER_RW( 0x7e1010d0 ) + #define CM_TD0CTL_MASK 0x00001bff + #define CM_TD0CTL_WIDTH 13 + #define CM_TD0CTL_RESET 0000000000 + #define CM_TD0CTL_STEP_BITS 12:12 + #define CM_TD0CTL_STEP_SET 0x00001000 + #define CM_TD0CTL_STEP_CLR 0xffffefff + #define CM_TD0CTL_STEP_MSB 12 + #define CM_TD0CTL_STEP_LSB 12 + #define CM_TD0CTL_FLIP_BITS 11:11 + #define CM_TD0CTL_FLIP_SET 0x00000800 + #define CM_TD0CTL_FLIP_CLR 0xfffff7ff + #define CM_TD0CTL_FLIP_MSB 11 + #define CM_TD0CTL_FLIP_LSB 11 + #define CM_TD0CTL_FRAC_BITS 9:9 + #define CM_TD0CTL_FRAC_SET 0x00000200 + #define CM_TD0CTL_FRAC_CLR 0xfffffdff + #define CM_TD0CTL_FRAC_MSB 9 + #define CM_TD0CTL_FRAC_LSB 9 + #define CM_TD0CTL_BUSYD_BITS 8:8 + #define CM_TD0CTL_BUSYD_SET 0x00000100 + #define CM_TD0CTL_BUSYD_CLR 0xfffffeff + #define CM_TD0CTL_BUSYD_MSB 8 + #define CM_TD0CTL_BUSYD_LSB 8 + #define CM_TD0CTL_BUSY_BITS 7:7 + #define CM_TD0CTL_BUSY_SET 0x00000080 + #define CM_TD0CTL_BUSY_CLR 0xffffff7f + #define CM_TD0CTL_BUSY_MSB 7 + #define CM_TD0CTL_BUSY_LSB 7 + #define CM_TD0CTL_GATE_BITS 6:6 + #define CM_TD0CTL_GATE_SET 0x00000040 + #define CM_TD0CTL_GATE_CLR 0xffffffbf + #define CM_TD0CTL_GATE_MSB 6 + #define CM_TD0CTL_GATE_LSB 6 + #define CM_TD0CTL_KILL_BITS 5:5 + #define CM_TD0CTL_KILL_SET 0x00000020 + #define CM_TD0CTL_KILL_CLR 0xffffffdf + #define CM_TD0CTL_KILL_MSB 5 + #define CM_TD0CTL_KILL_LSB 5 + #define CM_TD0CTL_ENAB_BITS 4:4 + #define CM_TD0CTL_ENAB_SET 0x00000010 + #define CM_TD0CTL_ENAB_CLR 0xffffffef + #define CM_TD0CTL_ENAB_MSB 4 + #define CM_TD0CTL_ENAB_LSB 4 + #define CM_TD0CTL_SRC_BITS 3:0 + #define CM_TD0CTL_SRC_SET 0x0000000f + #define CM_TD0CTL_SRC_CLR 0xfffffff0 + #define CM_TD0CTL_SRC_MSB 3 + #define CM_TD0CTL_SRC_LSB 0 +#define CM_TD0DIV HW_REGISTER_RW( 0x7e1010d4 ) + #define CM_TD0DIV_MASK 0x00ffffff + #define CM_TD0DIV_WIDTH 24 + #define CM_TD0DIV_RESET 0000000000 + #define CM_TD0DIV_DIV_BITS 23:0 + #define CM_TD0DIV_DIV_SET 0x00ffffff + #define CM_TD0DIV_DIV_CLR 0xff000000 + #define CM_TD0DIV_DIV_MSB 23 + #define CM_TD0DIV_DIV_LSB 0 +#define CM_TD1CTL HW_REGISTER_RW( 0x7e1010d8 ) + #define CM_TD1CTL_MASK 0x00001bff + #define CM_TD1CTL_WIDTH 13 + #define CM_TD1CTL_RESET 0000000000 + #define CM_TD1CTL_STEP_BITS 12:12 + #define CM_TD1CTL_STEP_SET 0x00001000 + #define CM_TD1CTL_STEP_CLR 0xffffefff + #define CM_TD1CTL_STEP_MSB 12 + #define CM_TD1CTL_STEP_LSB 12 + #define CM_TD1CTL_FLIP_BITS 11:11 + #define CM_TD1CTL_FLIP_SET 0x00000800 + #define CM_TD1CTL_FLIP_CLR 0xfffff7ff + #define CM_TD1CTL_FLIP_MSB 11 + #define CM_TD1CTL_FLIP_LSB 11 + #define CM_TD1CTL_FRAC_BITS 9:9 + #define CM_TD1CTL_FRAC_SET 0x00000200 + #define CM_TD1CTL_FRAC_CLR 0xfffffdff + #define CM_TD1CTL_FRAC_MSB 9 + #define CM_TD1CTL_FRAC_LSB 9 + #define CM_TD1CTL_BUSYD_BITS 8:8 + #define CM_TD1CTL_BUSYD_SET 0x00000100 + #define CM_TD1CTL_BUSYD_CLR 0xfffffeff + #define CM_TD1CTL_BUSYD_MSB 8 + #define CM_TD1CTL_BUSYD_LSB 8 + #define CM_TD1CTL_BUSY_BITS 7:7 + #define CM_TD1CTL_BUSY_SET 0x00000080 + #define CM_TD1CTL_BUSY_CLR 0xffffff7f + #define CM_TD1CTL_BUSY_MSB 7 + #define CM_TD1CTL_BUSY_LSB 7 + #define CM_TD1CTL_GATE_BITS 6:6 + #define CM_TD1CTL_GATE_SET 0x00000040 + #define CM_TD1CTL_GATE_CLR 0xffffffbf + #define CM_TD1CTL_GATE_MSB 6 + #define CM_TD1CTL_GATE_LSB 6 + #define CM_TD1CTL_KILL_BITS 5:5 + #define CM_TD1CTL_KILL_SET 0x00000020 + #define CM_TD1CTL_KILL_CLR 0xffffffdf + #define CM_TD1CTL_KILL_MSB 5 + #define CM_TD1CTL_KILL_LSB 5 + #define CM_TD1CTL_ENAB_BITS 4:4 + #define CM_TD1CTL_ENAB_SET 0x00000010 + #define CM_TD1CTL_ENAB_CLR 0xffffffef + #define CM_TD1CTL_ENAB_MSB 4 + #define CM_TD1CTL_ENAB_LSB 4 + #define CM_TD1CTL_SRC_BITS 3:0 + #define CM_TD1CTL_SRC_SET 0x0000000f + #define CM_TD1CTL_SRC_CLR 0xfffffff0 + #define CM_TD1CTL_SRC_MSB 3 + #define CM_TD1CTL_SRC_LSB 0 +#define CM_TD1DIV HW_REGISTER_RW( 0x7e1010dc ) + #define CM_TD1DIV_MASK 0x00ffffff + #define CM_TD1DIV_WIDTH 24 + #define CM_TD1DIV_RESET 0000000000 + #define CM_TD1DIV_DIV_BITS 23:0 + #define CM_TD1DIV_DIV_SET 0x00ffffff + #define CM_TD1DIV_DIV_CLR 0xff000000 + #define CM_TD1DIV_DIV_MSB 23 + #define CM_TD1DIV_DIV_LSB 0 +#define CM_TSENSCTL HW_REGISTER_RW( 0x7e1010e0 ) + #define CM_TSENSCTL_MASK 0x000003b3 + #define CM_TSENSCTL_WIDTH 10 + #define CM_TSENSCTL_RESET 0000000000 + #define CM_TSENSCTL_FRAC_BITS 9:9 + #define CM_TSENSCTL_FRAC_SET 0x00000200 + #define CM_TSENSCTL_FRAC_CLR 0xfffffdff + #define CM_TSENSCTL_FRAC_MSB 9 + #define CM_TSENSCTL_FRAC_LSB 9 + #define CM_TSENSCTL_BUSYD_BITS 8:8 + #define CM_TSENSCTL_BUSYD_SET 0x00000100 + #define CM_TSENSCTL_BUSYD_CLR 0xfffffeff + #define CM_TSENSCTL_BUSYD_MSB 8 + #define CM_TSENSCTL_BUSYD_LSB 8 + #define CM_TSENSCTL_BUSY_BITS 7:7 + #define CM_TSENSCTL_BUSY_SET 0x00000080 + #define CM_TSENSCTL_BUSY_CLR 0xffffff7f + #define CM_TSENSCTL_BUSY_MSB 7 + #define CM_TSENSCTL_BUSY_LSB 7 + #define CM_TSENSCTL_KILL_BITS 5:5 + #define CM_TSENSCTL_KILL_SET 0x00000020 + #define CM_TSENSCTL_KILL_CLR 0xffffffdf + #define CM_TSENSCTL_KILL_MSB 5 + #define CM_TSENSCTL_KILL_LSB 5 + #define CM_TSENSCTL_ENAB_BITS 4:4 + #define CM_TSENSCTL_ENAB_SET 0x00000010 + #define CM_TSENSCTL_ENAB_CLR 0xffffffef + #define CM_TSENSCTL_ENAB_MSB 4 + #define CM_TSENSCTL_ENAB_LSB 4 + #define CM_TSENSCTL_SRC_BITS 1:0 + #define CM_TSENSCTL_SRC_SET 0x00000003 + #define CM_TSENSCTL_SRC_CLR 0xfffffffc + #define CM_TSENSCTL_SRC_MSB 1 + #define CM_TSENSCTL_SRC_LSB 0 +#define CM_TSENSDIV HW_REGISTER_RW( 0x7e1010e4 ) + #define CM_TSENSDIV_MASK 0x0001f000 + #define CM_TSENSDIV_WIDTH 17 + #define CM_TSENSDIV_RESET 0000000000 + #define CM_TSENSDIV_DIV_BITS 16:12 + #define CM_TSENSDIV_DIV_SET 0x0001f000 + #define CM_TSENSDIV_DIV_CLR 0xfffe0fff + #define CM_TSENSDIV_DIV_MSB 16 + #define CM_TSENSDIV_DIV_LSB 12 +#define CM_TIMERCTL HW_REGISTER_RW( 0x7e1010e8 ) + #define CM_TIMERCTL_MASK 0x000003b3 + #define CM_TIMERCTL_WIDTH 10 + #define CM_TIMERCTL_RESET 0000000000 + #define CM_TIMERCTL_FRAC_BITS 9:9 + #define CM_TIMERCTL_FRAC_SET 0x00000200 + #define CM_TIMERCTL_FRAC_CLR 0xfffffdff + #define CM_TIMERCTL_FRAC_MSB 9 + #define CM_TIMERCTL_FRAC_LSB 9 + #define CM_TIMERCTL_BUSYD_BITS 8:8 + #define CM_TIMERCTL_BUSYD_SET 0x00000100 + #define CM_TIMERCTL_BUSYD_CLR 0xfffffeff + #define CM_TIMERCTL_BUSYD_MSB 8 + #define CM_TIMERCTL_BUSYD_LSB 8 + #define CM_TIMERCTL_BUSY_BITS 7:7 + #define CM_TIMERCTL_BUSY_SET 0x00000080 + #define CM_TIMERCTL_BUSY_CLR 0xffffff7f + #define CM_TIMERCTL_BUSY_MSB 7 + #define CM_TIMERCTL_BUSY_LSB 7 + #define CM_TIMERCTL_KILL_BITS 5:5 + #define CM_TIMERCTL_KILL_SET 0x00000020 + #define CM_TIMERCTL_KILL_CLR 0xffffffdf + #define CM_TIMERCTL_KILL_MSB 5 + #define CM_TIMERCTL_KILL_LSB 5 + #define CM_TIMERCTL_ENAB_BITS 4:4 + #define CM_TIMERCTL_ENAB_SET 0x00000010 + #define CM_TIMERCTL_ENAB_CLR 0xffffffef + #define CM_TIMERCTL_ENAB_MSB 4 + #define CM_TIMERCTL_ENAB_LSB 4 + #define CM_TIMERCTL_SRC_BITS 1:0 + #define CM_TIMERCTL_SRC_SET 0x00000003 + #define CM_TIMERCTL_SRC_CLR 0xfffffffc + #define CM_TIMERCTL_SRC_MSB 1 + #define CM_TIMERCTL_SRC_LSB 0 +#define CM_TIMERDIV HW_REGISTER_RW( 0x7e1010ec ) + #define CM_TIMERDIV_MASK 0x0003ffff + #define CM_TIMERDIV_WIDTH 18 + #define CM_TIMERDIV_RESET 0000000000 + #define CM_TIMERDIV_DIV_BITS 17:0 + #define CM_TIMERDIV_DIV_SET 0x0003ffff + #define CM_TIMERDIV_DIV_CLR 0xfffc0000 + #define CM_TIMERDIV_DIV_MSB 17 + #define CM_TIMERDIV_DIV_LSB 0 +#define CM_UARTCTL HW_REGISTER_RW( 0x7e1010f0 ) + #define CM_UARTCTL_MASK 0x000003bf + #define CM_UARTCTL_WIDTH 10 + #define CM_UARTCTL_RESET 0000000000 + #define CM_UARTCTL_FRAC_BITS 9:9 + #define CM_UARTCTL_FRAC_SET 0x00000200 + #define CM_UARTCTL_FRAC_CLR 0xfffffdff + #define CM_UARTCTL_FRAC_MSB 9 + #define CM_UARTCTL_FRAC_LSB 9 + #define CM_UARTCTL_BUSYD_BITS 8:8 + #define CM_UARTCTL_BUSYD_SET 0x00000100 + #define CM_UARTCTL_BUSYD_CLR 0xfffffeff + #define CM_UARTCTL_BUSYD_MSB 8 + #define CM_UARTCTL_BUSYD_LSB 8 + #define CM_UARTCTL_BUSY_BITS 7:7 + #define CM_UARTCTL_BUSY_SET 0x00000080 + #define CM_UARTCTL_BUSY_CLR 0xffffff7f + #define CM_UARTCTL_BUSY_MSB 7 + #define CM_UARTCTL_BUSY_LSB 7 + #define CM_UARTCTL_KILL_BITS 5:5 + #define CM_UARTCTL_KILL_SET 0x00000020 + #define CM_UARTCTL_KILL_CLR 0xffffffdf + #define CM_UARTCTL_KILL_MSB 5 + #define CM_UARTCTL_KILL_LSB 5 + #define CM_UARTCTL_ENAB_BITS 4:4 + #define CM_UARTCTL_ENAB_SET 0x00000010 + #define CM_UARTCTL_ENAB_CLR 0xffffffef + #define CM_UARTCTL_ENAB_MSB 4 + #define CM_UARTCTL_ENAB_LSB 4 + #define CM_UARTCTL_SRC_BITS 3:0 + #define CM_UARTCTL_SRC_SET 0x0000000f + #define CM_UARTCTL_SRC_CLR 0xfffffff0 + #define CM_UARTCTL_SRC_MSB 3 + #define CM_UARTCTL_SRC_LSB 0 +#define CM_UARTDIV HW_REGISTER_RW( 0x7e1010f4 ) + #define CM_UARTDIV_MASK 0x003fffff + #define CM_UARTDIV_WIDTH 22 + #define CM_UARTDIV_RESET 0000000000 + #define CM_UARTDIV_DIV_BITS 21:0 + #define CM_UARTDIV_DIV_SET 0x003fffff + #define CM_UARTDIV_DIV_CLR 0xffc00000 + #define CM_UARTDIV_DIV_MSB 21 + #define CM_UARTDIV_DIV_LSB 0 +#define CM_VECCTL HW_REGISTER_RW( 0x7e1010f8 ) + #define CM_VECCTL_MASK 0x000003bf + #define CM_VECCTL_WIDTH 10 + #define CM_VECCTL_RESET 0000000000 + #define CM_VECCTL_FRAC_BITS 9:9 + #define CM_VECCTL_FRAC_SET 0x00000200 + #define CM_VECCTL_FRAC_CLR 0xfffffdff + #define CM_VECCTL_FRAC_MSB 9 + #define CM_VECCTL_FRAC_LSB 9 + #define CM_VECCTL_BUSYD_BITS 8:8 + #define CM_VECCTL_BUSYD_SET 0x00000100 + #define CM_VECCTL_BUSYD_CLR 0xfffffeff + #define CM_VECCTL_BUSYD_MSB 8 + #define CM_VECCTL_BUSYD_LSB 8 + #define CM_VECCTL_BUSY_BITS 7:7 + #define CM_VECCTL_BUSY_SET 0x00000080 + #define CM_VECCTL_BUSY_CLR 0xffffff7f + #define CM_VECCTL_BUSY_MSB 7 + #define CM_VECCTL_BUSY_LSB 7 + #define CM_VECCTL_KILL_BITS 5:5 + #define CM_VECCTL_KILL_SET 0x00000020 + #define CM_VECCTL_KILL_CLR 0xffffffdf + #define CM_VECCTL_KILL_MSB 5 + #define CM_VECCTL_KILL_LSB 5 + #define CM_VECCTL_ENAB_BITS 4:4 + #define CM_VECCTL_ENAB_SET 0x00000010 + #define CM_VECCTL_ENAB_CLR 0xffffffef + #define CM_VECCTL_ENAB_MSB 4 + #define CM_VECCTL_ENAB_LSB 4 + #define CM_VECCTL_SRC_BITS 3:0 + #define CM_VECCTL_SRC_SET 0x0000000f + #define CM_VECCTL_SRC_CLR 0xfffffff0 + #define CM_VECCTL_SRC_MSB 3 + #define CM_VECCTL_SRC_LSB 0 +#define CM_VECDIV HW_REGISTER_RW( 0x7e1010fc ) + #define CM_VECDIV_MASK 0x0000f000 + #define CM_VECDIV_WIDTH 16 + #define CM_VECDIV_RESET 0000000000 + #define CM_VECDIV_DIV_BITS 15:12 + #define CM_VECDIV_DIV_SET 0x0000f000 + #define CM_VECDIV_DIV_CLR 0xffff0fff + #define CM_VECDIV_DIV_MSB 15 + #define CM_VECDIV_DIV_LSB 12 +#define CM_AVEOCTL HW_REGISTER_RW( 0x7e1011b8 ) + #define CM_AVEOCTL_MASK 0x000003bf + #define CM_AVEOCTL_WIDTH 10 + #define CM_AVEOCTL_RESET 0000000000 + #define CM_AVEOCTL_FRAC_BITS 9:9 + #define CM_AVEOCTL_FRAC_SET 0x00000200 + #define CM_AVEOCTL_FRAC_CLR 0xfffffdff + #define CM_AVEOCTL_FRAC_MSB 9 + #define CM_AVEOCTL_FRAC_LSB 9 + #define CM_AVEOCTL_BUSYD_BITS 8:8 + #define CM_AVEOCTL_BUSYD_SET 0x00000100 + #define CM_AVEOCTL_BUSYD_CLR 0xfffffeff + #define CM_AVEOCTL_BUSYD_MSB 8 + #define CM_AVEOCTL_BUSYD_LSB 8 + #define CM_AVEOCTL_BUSY_BITS 7:7 + #define CM_AVEOCTL_BUSY_SET 0x00000080 + #define CM_AVEOCTL_BUSY_CLR 0xffffff7f + #define CM_AVEOCTL_BUSY_MSB 7 + #define CM_AVEOCTL_BUSY_LSB 7 + #define CM_AVEOCTL_KILL_BITS 5:5 + #define CM_AVEOCTL_KILL_SET 0x00000020 + #define CM_AVEOCTL_KILL_CLR 0xffffffdf + #define CM_AVEOCTL_KILL_MSB 5 + #define CM_AVEOCTL_KILL_LSB 5 + #define CM_AVEOCTL_ENAB_BITS 4:4 + #define CM_AVEOCTL_ENAB_SET 0x00000010 + #define CM_AVEOCTL_ENAB_CLR 0xffffffef + #define CM_AVEOCTL_ENAB_MSB 4 + #define CM_AVEOCTL_ENAB_LSB 4 + #define CM_AVEOCTL_SRC_BITS 3:0 + #define CM_AVEOCTL_SRC_SET 0x0000000f + #define CM_AVEOCTL_SRC_CLR 0xfffffff0 + #define CM_AVEOCTL_SRC_MSB 3 + #define CM_AVEOCTL_SRC_LSB 0 +#define CM_AVEODIV HW_REGISTER_RW( 0x7e1011bc ) + #define CM_AVEODIV_MASK 0x0000f000 + #define CM_AVEODIV_WIDTH 16 + #define CM_AVEODIV_RESET 0000000000 + #define CM_AVEODIV_DIV_BITS 15:12 + #define CM_AVEODIV_DIV_SET 0x0000f000 + #define CM_AVEODIV_DIV_CLR 0xffff0fff + #define CM_AVEODIV_DIV_MSB 15 + #define CM_AVEODIV_DIV_LSB 12 +#define CM_EMMCCTL HW_REGISTER_RW( 0x7e1011c0 ) + #define CM_EMMCCTL_MASK 0x000003bf + #define CM_EMMCCTL_WIDTH 10 + #define CM_EMMCCTL_RESET 0000000000 + #define CM_EMMCCTL_FRAC_BITS 9:9 + #define CM_EMMCCTL_FRAC_SET 0x00000200 + #define CM_EMMCCTL_FRAC_CLR 0xfffffdff + #define CM_EMMCCTL_FRAC_MSB 9 + #define CM_EMMCCTL_FRAC_LSB 9 + #define CM_EMMCCTL_BUSYD_BITS 8:8 + #define CM_EMMCCTL_BUSYD_SET 0x00000100 + #define CM_EMMCCTL_BUSYD_CLR 0xfffffeff + #define CM_EMMCCTL_BUSYD_MSB 8 + #define CM_EMMCCTL_BUSYD_LSB 8 + #define CM_EMMCCTL_BUSY_BITS 7:7 + #define CM_EMMCCTL_BUSY_SET 0x00000080 + #define CM_EMMCCTL_BUSY_CLR 0xffffff7f + #define CM_EMMCCTL_BUSY_MSB 7 + #define CM_EMMCCTL_BUSY_LSB 7 + #define CM_EMMCCTL_KILL_BITS 5:5 + #define CM_EMMCCTL_KILL_SET 0x00000020 + #define CM_EMMCCTL_KILL_CLR 0xffffffdf + #define CM_EMMCCTL_KILL_MSB 5 + #define CM_EMMCCTL_KILL_LSB 5 + #define CM_EMMCCTL_ENAB_BITS 4:4 + #define CM_EMMCCTL_ENAB_SET 0x00000010 + #define CM_EMMCCTL_ENAB_CLR 0xffffffef + #define CM_EMMCCTL_ENAB_MSB 4 + #define CM_EMMCCTL_ENAB_LSB 4 + #define CM_EMMCCTL_SRC_BITS 3:0 + #define CM_EMMCCTL_SRC_SET 0x0000000f + #define CM_EMMCCTL_SRC_CLR 0xfffffff0 + #define CM_EMMCCTL_SRC_MSB 3 + #define CM_EMMCCTL_SRC_LSB 0 +#define CM_EMMCDIV HW_REGISTER_RW( 0x7e1011c4 ) + #define CM_EMMCDIV_MASK 0x0000fff0 + #define CM_EMMCDIV_WIDTH 16 + #define CM_EMMCDIV_RESET 0000000000 + #define CM_EMMCDIV_DIV_BITS 15:4 + #define CM_EMMCDIV_DIV_SET 0x0000fff0 + #define CM_EMMCDIV_DIV_CLR 0xffff000f + #define CM_EMMCDIV_DIV_MSB 15 + #define CM_EMMCDIV_DIV_LSB 4 +#define CM_OSCCOUNT HW_REGISTER_RW( 0x7e101100 ) + #define CM_OSCCOUNT_MASK 0x00ffffff + #define CM_OSCCOUNT_WIDTH 24 + #define CM_OSCCOUNT_RESET 0000000000 + #define CM_OSCCOUNT_NUM_BITS 23:0 + #define CM_OSCCOUNT_NUM_SET 0x00ffffff + #define CM_OSCCOUNT_NUM_CLR 0xff000000 + #define CM_OSCCOUNT_NUM_MSB 23 + #define CM_OSCCOUNT_NUM_LSB 0 +#define CM_PLLA HW_REGISTER_RW( 0x7e101104 ) + #define CM_PLLA_MASK 0x000003ff + #define CM_PLLA_WIDTH 10 + #define CM_PLLA_RESET 0x00000300 + #define CM_PLLA_DIGRST_BITS 9:9 + #define CM_PLLA_DIGRST_SET 0x00000200 + #define CM_PLLA_DIGRST_CLR 0xfffffdff + #define CM_PLLA_DIGRST_MSB 9 + #define CM_PLLA_DIGRST_LSB 9 + #define CM_PLLA_ANARST_BITS 8:8 + #define CM_PLLA_ANARST_SET 0x00000100 + #define CM_PLLA_ANARST_CLR 0xfffffeff + #define CM_PLLA_ANARST_MSB 8 + #define CM_PLLA_ANARST_LSB 8 + #define CM_PLLA_HOLDPER_BITS 7:7 + #define CM_PLLA_HOLDPER_SET 0x00000080 + #define CM_PLLA_HOLDPER_CLR 0xffffff7f + #define CM_PLLA_HOLDPER_MSB 7 + #define CM_PLLA_HOLDPER_LSB 7 + #define CM_PLLA_LOADPER_BITS 6:6 + #define CM_PLLA_LOADPER_SET 0x00000040 + #define CM_PLLA_LOADPER_CLR 0xffffffbf + #define CM_PLLA_LOADPER_MSB 6 + #define CM_PLLA_LOADPER_LSB 6 + #define CM_PLLA_HOLDCORE_BITS 5:5 + #define CM_PLLA_HOLDCORE_SET 0x00000020 + #define CM_PLLA_HOLDCORE_CLR 0xffffffdf + #define CM_PLLA_HOLDCORE_MSB 5 + #define CM_PLLA_HOLDCORE_LSB 5 + #define CM_PLLA_LOADCORE_BITS 4:4 + #define CM_PLLA_LOADCORE_SET 0x00000010 + #define CM_PLLA_LOADCORE_CLR 0xffffffef + #define CM_PLLA_LOADCORE_MSB 4 + #define CM_PLLA_LOADCORE_LSB 4 + #define CM_PLLA_HOLDCCP2_BITS 3:3 + #define CM_PLLA_HOLDCCP2_SET 0x00000008 + #define CM_PLLA_HOLDCCP2_CLR 0xfffffff7 + #define CM_PLLA_HOLDCCP2_MSB 3 + #define CM_PLLA_HOLDCCP2_LSB 3 + #define CM_PLLA_LOADCCP2_BITS 2:2 + #define CM_PLLA_LOADCCP2_SET 0x00000004 + #define CM_PLLA_LOADCCP2_CLR 0xfffffffb + #define CM_PLLA_LOADCCP2_MSB 2 + #define CM_PLLA_LOADCCP2_LSB 2 + #define CM_PLLA_HOLDDSI0_BITS 1:1 + #define CM_PLLA_HOLDDSI0_SET 0x00000002 + #define CM_PLLA_HOLDDSI0_CLR 0xfffffffd + #define CM_PLLA_HOLDDSI0_MSB 1 + #define CM_PLLA_HOLDDSI0_LSB 1 + #define CM_PLLA_LOADDSI0_BITS 0:0 + #define CM_PLLA_LOADDSI0_SET 0x00000001 + #define CM_PLLA_LOADDSI0_CLR 0xfffffffe + #define CM_PLLA_LOADDSI0_MSB 0 + #define CM_PLLA_LOADDSI0_LSB 0 +#define CM_PLLB HW_REGISTER_RW( 0x7e101170 ) + #define CM_PLLB_MASK 0x00000303 + #define CM_PLLB_WIDTH 10 + #define CM_PLLB_RESET 0x00000300 + #define CM_PLLB_DIGRST_BITS 9:9 + #define CM_PLLB_DIGRST_SET 0x00000200 + #define CM_PLLB_DIGRST_CLR 0xfffffdff + #define CM_PLLB_DIGRST_MSB 9 + #define CM_PLLB_DIGRST_LSB 9 + #define CM_PLLB_ANARST_BITS 8:8 + #define CM_PLLB_ANARST_SET 0x00000100 + #define CM_PLLB_ANARST_CLR 0xfffffeff + #define CM_PLLB_ANARST_MSB 8 + #define CM_PLLB_ANARST_LSB 8 + #define CM_PLLB_HOLDARM_BITS 1:1 + #define CM_PLLB_HOLDARM_SET 0x00000002 + #define CM_PLLB_HOLDARM_CLR 0xfffffffd + #define CM_PLLB_HOLDARM_MSB 1 + #define CM_PLLB_HOLDARM_LSB 1 + #define CM_PLLB_LOADARM_BITS 0:0 + #define CM_PLLB_LOADARM_SET 0x00000001 + #define CM_PLLB_LOADARM_CLR 0xfffffffe + #define CM_PLLB_LOADARM_MSB 0 + #define CM_PLLB_LOADARM_LSB 0 +#define CM_PLLC HW_REGISTER_RW( 0x7e101108 ) + #define CM_PLLC_MASK 0x000003ff + #define CM_PLLC_WIDTH 10 + #define CM_PLLC_RESET 0x00000300 + #define CM_PLLC_DIGRST_BITS 9:9 + #define CM_PLLC_DIGRST_SET 0x00000200 + #define CM_PLLC_DIGRST_CLR 0xfffffdff + #define CM_PLLC_DIGRST_MSB 9 + #define CM_PLLC_DIGRST_LSB 9 + #define CM_PLLC_ANARST_BITS 8:8 + #define CM_PLLC_ANARST_SET 0x00000100 + #define CM_PLLC_ANARST_CLR 0xfffffeff + #define CM_PLLC_ANARST_MSB 8 + #define CM_PLLC_ANARST_LSB 8 + #define CM_PLLC_HOLDPER_BITS 7:7 + #define CM_PLLC_HOLDPER_SET 0x00000080 + #define CM_PLLC_HOLDPER_CLR 0xffffff7f + #define CM_PLLC_HOLDPER_MSB 7 + #define CM_PLLC_HOLDPER_LSB 7 + #define CM_PLLC_LOADPER_BITS 6:6 + #define CM_PLLC_LOADPER_SET 0x00000040 + #define CM_PLLC_LOADPER_CLR 0xffffffbf + #define CM_PLLC_LOADPER_MSB 6 + #define CM_PLLC_LOADPER_LSB 6 + #define CM_PLLC_HOLDCORE2_BITS 5:5 + #define CM_PLLC_HOLDCORE2_SET 0x00000020 + #define CM_PLLC_HOLDCORE2_CLR 0xffffffdf + #define CM_PLLC_HOLDCORE2_MSB 5 + #define CM_PLLC_HOLDCORE2_LSB 5 + #define CM_PLLC_LOADCORE2_BITS 4:4 + #define CM_PLLC_LOADCORE2_SET 0x00000010 + #define CM_PLLC_LOADCORE2_CLR 0xffffffef + #define CM_PLLC_LOADCORE2_MSB 4 + #define CM_PLLC_LOADCORE2_LSB 4 + #define CM_PLLC_HOLDCORE1_BITS 3:3 + #define CM_PLLC_HOLDCORE1_SET 0x00000008 + #define CM_PLLC_HOLDCORE1_CLR 0xfffffff7 + #define CM_PLLC_HOLDCORE1_MSB 3 + #define CM_PLLC_HOLDCORE1_LSB 3 + #define CM_PLLC_LOADCORE1_BITS 2:2 + #define CM_PLLC_LOADCORE1_SET 0x00000004 + #define CM_PLLC_LOADCORE1_CLR 0xfffffffb + #define CM_PLLC_LOADCORE1_MSB 2 + #define CM_PLLC_LOADCORE1_LSB 2 + #define CM_PLLC_HOLDCORE0_BITS 1:1 + #define CM_PLLC_HOLDCORE0_SET 0x00000002 + #define CM_PLLC_HOLDCORE0_CLR 0xfffffffd + #define CM_PLLC_HOLDCORE0_MSB 1 + #define CM_PLLC_HOLDCORE0_LSB 1 + #define CM_PLLC_LOADCORE0_BITS 0:0 + #define CM_PLLC_LOADCORE0_SET 0x00000001 + #define CM_PLLC_LOADCORE0_CLR 0xfffffffe + #define CM_PLLC_LOADCORE0_MSB 0 + #define CM_PLLC_LOADCORE0_LSB 0 +#define CM_PLLD HW_REGISTER_RW( 0x7e10110c ) + #define CM_PLLD_MASK 0x000003ff + #define CM_PLLD_WIDTH 10 + #define CM_PLLD_RESET 0x00000300 + #define CM_PLLD_DIGRST_BITS 9:9 + #define CM_PLLD_DIGRST_SET 0x00000200 + #define CM_PLLD_DIGRST_CLR 0xfffffdff + #define CM_PLLD_DIGRST_MSB 9 + #define CM_PLLD_DIGRST_LSB 9 + #define CM_PLLD_ANARST_BITS 8:8 + #define CM_PLLD_ANARST_SET 0x00000100 + #define CM_PLLD_ANARST_CLR 0xfffffeff + #define CM_PLLD_ANARST_MSB 8 + #define CM_PLLD_ANARST_LSB 8 + #define CM_PLLD_HOLDPER_BITS 7:7 + #define CM_PLLD_HOLDPER_SET 0x00000080 + #define CM_PLLD_HOLDPER_CLR 0xffffff7f + #define CM_PLLD_HOLDPER_MSB 7 + #define CM_PLLD_HOLDPER_LSB 7 + #define CM_PLLD_LOADPER_BITS 6:6 + #define CM_PLLD_LOADPER_SET 0x00000040 + #define CM_PLLD_LOADPER_CLR 0xffffffbf + #define CM_PLLD_LOADPER_MSB 6 + #define CM_PLLD_LOADPER_LSB 6 + #define CM_PLLD_HOLDCORE_BITS 5:5 + #define CM_PLLD_HOLDCORE_SET 0x00000020 + #define CM_PLLD_HOLDCORE_CLR 0xffffffdf + #define CM_PLLD_HOLDCORE_MSB 5 + #define CM_PLLD_HOLDCORE_LSB 5 + #define CM_PLLD_LOADCORE_BITS 4:4 + #define CM_PLLD_LOADCORE_SET 0x00000010 + #define CM_PLLD_LOADCORE_CLR 0xffffffef + #define CM_PLLD_LOADCORE_MSB 4 + #define CM_PLLD_LOADCORE_LSB 4 + #define CM_PLLD_HOLDDSI1_BITS 3:3 + #define CM_PLLD_HOLDDSI1_SET 0x00000008 + #define CM_PLLD_HOLDDSI1_CLR 0xfffffff7 + #define CM_PLLD_HOLDDSI1_MSB 3 + #define CM_PLLD_HOLDDSI1_LSB 3 + #define CM_PLLD_LOADDSI1_BITS 2:2 + #define CM_PLLD_LOADDSI1_SET 0x00000004 + #define CM_PLLD_LOADDSI1_CLR 0xfffffffb + #define CM_PLLD_LOADDSI1_MSB 2 + #define CM_PLLD_LOADDSI1_LSB 2 + #define CM_PLLD_HOLDDSI0_BITS 1:1 + #define CM_PLLD_HOLDDSI0_SET 0x00000002 + #define CM_PLLD_HOLDDSI0_CLR 0xfffffffd + #define CM_PLLD_HOLDDSI0_MSB 1 + #define CM_PLLD_HOLDDSI0_LSB 1 + #define CM_PLLD_LOADDSI0_BITS 0:0 + #define CM_PLLD_LOADDSI0_SET 0x00000001 + #define CM_PLLD_LOADDSI0_CLR 0xfffffffe + #define CM_PLLD_LOADDSI0_MSB 0 + #define CM_PLLD_LOADDSI0_LSB 0 +#define CM_PLLH HW_REGISTER_RW( 0x7e101110 ) + #define CM_PLLH_MASK 0x00000307 + #define CM_PLLH_WIDTH 10 + #define CM_PLLH_RESET 0x00000300 + #define CM_PLLH_DIGRST_BITS 9:9 + #define CM_PLLH_DIGRST_SET 0x00000200 + #define CM_PLLH_DIGRST_CLR 0xfffffdff + #define CM_PLLH_DIGRST_MSB 9 + #define CM_PLLH_DIGRST_LSB 9 + #define CM_PLLH_ANARST_BITS 8:8 + #define CM_PLLH_ANARST_SET 0x00000100 + #define CM_PLLH_ANARST_CLR 0xfffffeff + #define CM_PLLH_ANARST_MSB 8 + #define CM_PLLH_ANARST_LSB 8 + #define CM_PLLH_LOADRCAL_BITS 2:2 + #define CM_PLLH_LOADRCAL_SET 0x00000004 + #define CM_PLLH_LOADRCAL_CLR 0xfffffffb + #define CM_PLLH_LOADRCAL_MSB 2 + #define CM_PLLH_LOADRCAL_LSB 2 + #define CM_PLLH_LOADAUX_BITS 1:1 + #define CM_PLLH_LOADAUX_SET 0x00000002 + #define CM_PLLH_LOADAUX_CLR 0xfffffffd + #define CM_PLLH_LOADAUX_MSB 1 + #define CM_PLLH_LOADAUX_LSB 1 + #define CM_PLLH_LOADPIX_BITS 0:0 + #define CM_PLLH_LOADPIX_SET 0x00000001 + #define CM_PLLH_LOADPIX_CLR 0xfffffffe + #define CM_PLLH_LOADPIX_MSB 0 + #define CM_PLLH_LOADPIX_LSB 0 +#define CM_LOCK HW_REGISTER_RW( 0x7e101114 ) + #define CM_LOCK_MASK 0x00001f1f + #define CM_LOCK_WIDTH 13 + #define CM_LOCK_RESET 0000000000 + #define CM_LOCK_FLOCKH_BITS 12:12 + #define CM_LOCK_FLOCKH_SET 0x00001000 + #define CM_LOCK_FLOCKH_CLR 0xffffefff + #define CM_LOCK_FLOCKH_MSB 12 + #define CM_LOCK_FLOCKH_LSB 12 + #define CM_LOCK_FLOCKD_BITS 11:11 + #define CM_LOCK_FLOCKD_SET 0x00000800 + #define CM_LOCK_FLOCKD_CLR 0xfffff7ff + #define CM_LOCK_FLOCKD_MSB 11 + #define CM_LOCK_FLOCKD_LSB 11 + #define CM_LOCK_FLOCKC_BITS 10:10 + #define CM_LOCK_FLOCKC_SET 0x00000400 + #define CM_LOCK_FLOCKC_CLR 0xfffffbff + #define CM_LOCK_FLOCKC_MSB 10 + #define CM_LOCK_FLOCKC_LSB 10 + #define CM_LOCK_FLOCKB_BITS 9:9 + #define CM_LOCK_FLOCKB_SET 0x00000200 + #define CM_LOCK_FLOCKB_CLR 0xfffffdff + #define CM_LOCK_FLOCKB_MSB 9 + #define CM_LOCK_FLOCKB_LSB 9 + #define CM_LOCK_FLOCKA_BITS 8:8 + #define CM_LOCK_FLOCKA_SET 0x00000100 + #define CM_LOCK_FLOCKA_CLR 0xfffffeff + #define CM_LOCK_FLOCKA_MSB 8 + #define CM_LOCK_FLOCKA_LSB 8 + #define CM_LOCK_LOCKH_BITS 4:4 + #define CM_LOCK_LOCKH_SET 0x00000010 + #define CM_LOCK_LOCKH_CLR 0xffffffef + #define CM_LOCK_LOCKH_MSB 4 + #define CM_LOCK_LOCKH_LSB 4 + #define CM_LOCK_LOCKD_BITS 3:3 + #define CM_LOCK_LOCKD_SET 0x00000008 + #define CM_LOCK_LOCKD_CLR 0xfffffff7 + #define CM_LOCK_LOCKD_MSB 3 + #define CM_LOCK_LOCKD_LSB 3 + #define CM_LOCK_LOCKC_BITS 2:2 + #define CM_LOCK_LOCKC_SET 0x00000004 + #define CM_LOCK_LOCKC_CLR 0xfffffffb + #define CM_LOCK_LOCKC_MSB 2 + #define CM_LOCK_LOCKC_LSB 2 + #define CM_LOCK_LOCKB_BITS 1:1 + #define CM_LOCK_LOCKB_SET 0x00000002 + #define CM_LOCK_LOCKB_CLR 0xfffffffd + #define CM_LOCK_LOCKB_MSB 1 + #define CM_LOCK_LOCKB_LSB 1 + #define CM_LOCK_LOCKA_BITS 0:0 + #define CM_LOCK_LOCKA_SET 0x00000001 + #define CM_LOCK_LOCKA_CLR 0xfffffffe + #define CM_LOCK_LOCKA_MSB 0 + #define CM_LOCK_LOCKA_LSB 0 +#define CM_EVENT HW_REGISTER_RW( 0x7e101118 ) + #define CM_EVENT_MASK 0x00ffffff + #define CM_EVENT_WIDTH 24 + #define CM_EVENT_RESET 0000000000 + #define CM_EVENT_BURSTDONE_BITS 23:23 + #define CM_EVENT_BURSTDONE_SET 0x00800000 + #define CM_EVENT_BURSTDONE_CLR 0xff7fffff + #define CM_EVENT_BURSTDONE_MSB 23 + #define CM_EVENT_BURSTDONE_LSB 23 + #define CM_EVENT_RESUS_BITS 22:22 + #define CM_EVENT_RESUS_SET 0x00400000 + #define CM_EVENT_RESUS_CLR 0xffbfffff + #define CM_EVENT_RESUS_MSB 22 + #define CM_EVENT_RESUS_LSB 22 + #define CM_EVENT_OCDONE_BITS 21:21 + #define CM_EVENT_OCDONE_SET 0x00200000 + #define CM_EVENT_OCDONE_CLR 0xffdfffff + #define CM_EVENT_OCDONE_MSB 21 + #define CM_EVENT_OCDONE_LSB 21 + #define CM_EVENT_A2WDONE_BITS 20:20 + #define CM_EVENT_A2WDONE_SET 0x00100000 + #define CM_EVENT_A2WDONE_CLR 0xffefffff + #define CM_EVENT_A2WDONE_MSB 20 + #define CM_EVENT_A2WDONE_LSB 20 + #define CM_EVENT_WRFAIL_BITS 19:19 + #define CM_EVENT_WRFAIL_SET 0x00080000 + #define CM_EVENT_WRFAIL_CLR 0xfff7ffff + #define CM_EVENT_WRFAIL_MSB 19 + #define CM_EVENT_WRFAIL_LSB 19 + #define CM_EVENT_BADPASS_BITS 18:18 + #define CM_EVENT_BADPASS_SET 0x00040000 + #define CM_EVENT_BADPASS_CLR 0xfffbffff + #define CM_EVENT_BADPASS_MSB 18 + #define CM_EVENT_BADPASS_LSB 18 + #define CM_EVENT_FLOSSD_BITS 17:17 + #define CM_EVENT_FLOSSD_SET 0x00020000 + #define CM_EVENT_FLOSSD_CLR 0xfffdffff + #define CM_EVENT_FLOSSD_MSB 17 + #define CM_EVENT_FLOSSD_LSB 17 + #define CM_EVENT_FLOSSC_BITS 16:16 + #define CM_EVENT_FLOSSC_SET 0x00010000 + #define CM_EVENT_FLOSSC_CLR 0xfffeffff + #define CM_EVENT_FLOSSC_MSB 16 + #define CM_EVENT_FLOSSC_LSB 16 + #define CM_EVENT_FLOSSB_BITS 15:15 + #define CM_EVENT_FLOSSB_SET 0x00008000 + #define CM_EVENT_FLOSSB_CLR 0xffff7fff + #define CM_EVENT_FLOSSB_MSB 15 + #define CM_EVENT_FLOSSB_LSB 15 + #define CM_EVENT_FLOSSA_BITS 14:14 + #define CM_EVENT_FLOSSA_SET 0x00004000 + #define CM_EVENT_FLOSSA_CLR 0xffffbfff + #define CM_EVENT_FLOSSA_MSB 14 + #define CM_EVENT_FLOSSA_LSB 14 + #define CM_EVENT_FGAIND_BITS 13:13 + #define CM_EVENT_FGAIND_SET 0x00002000 + #define CM_EVENT_FGAIND_CLR 0xffffdfff + #define CM_EVENT_FGAIND_MSB 13 + #define CM_EVENT_FGAIND_LSB 13 + #define CM_EVENT_FGAINC_BITS 12:12 + #define CM_EVENT_FGAINC_SET 0x00001000 + #define CM_EVENT_FGAINC_CLR 0xffffefff + #define CM_EVENT_FGAINC_MSB 12 + #define CM_EVENT_FGAINC_LSB 12 + #define CM_EVENT_FGAINB_BITS 11:11 + #define CM_EVENT_FGAINB_SET 0x00000800 + #define CM_EVENT_FGAINB_CLR 0xfffff7ff + #define CM_EVENT_FGAINB_MSB 11 + #define CM_EVENT_FGAINB_LSB 11 + #define CM_EVENT_FGAINA_BITS 10:10 + #define CM_EVENT_FGAINA_SET 0x00000400 + #define CM_EVENT_FGAINA_CLR 0xfffffbff + #define CM_EVENT_FGAINA_MSB 10 + #define CM_EVENT_FGAINA_LSB 10 + #define CM_EVENT_LOSSH_BITS 9:9 + #define CM_EVENT_LOSSH_SET 0x00000200 + #define CM_EVENT_LOSSH_CLR 0xfffffdff + #define CM_EVENT_LOSSH_MSB 9 + #define CM_EVENT_LOSSH_LSB 9 + #define CM_EVENT_LOSSD_BITS 8:8 + #define CM_EVENT_LOSSD_SET 0x00000100 + #define CM_EVENT_LOSSD_CLR 0xfffffeff + #define CM_EVENT_LOSSD_MSB 8 + #define CM_EVENT_LOSSD_LSB 8 + #define CM_EVENT_LOSSC_BITS 7:7 + #define CM_EVENT_LOSSC_SET 0x00000080 + #define CM_EVENT_LOSSC_CLR 0xffffff7f + #define CM_EVENT_LOSSC_MSB 7 + #define CM_EVENT_LOSSC_LSB 7 + #define CM_EVENT_LOSSB_BITS 6:6 + #define CM_EVENT_LOSSB_SET 0x00000040 + #define CM_EVENT_LOSSB_CLR 0xffffffbf + #define CM_EVENT_LOSSB_MSB 6 + #define CM_EVENT_LOSSB_LSB 6 + #define CM_EVENT_LOSSA_BITS 5:5 + #define CM_EVENT_LOSSA_SET 0x00000020 + #define CM_EVENT_LOSSA_CLR 0xffffffdf + #define CM_EVENT_LOSSA_MSB 5 + #define CM_EVENT_LOSSA_LSB 5 + #define CM_EVENT_GAINH_BITS 4:4 + #define CM_EVENT_GAINH_SET 0x00000010 + #define CM_EVENT_GAINH_CLR 0xffffffef + #define CM_EVENT_GAINH_MSB 4 + #define CM_EVENT_GAINH_LSB 4 + #define CM_EVENT_GAIND_BITS 3:3 + #define CM_EVENT_GAIND_SET 0x00000008 + #define CM_EVENT_GAIND_CLR 0xfffffff7 + #define CM_EVENT_GAIND_MSB 3 + #define CM_EVENT_GAIND_LSB 3 + #define CM_EVENT_GAINC_BITS 2:2 + #define CM_EVENT_GAINC_SET 0x00000004 + #define CM_EVENT_GAINC_CLR 0xfffffffb + #define CM_EVENT_GAINC_MSB 2 + #define CM_EVENT_GAINC_LSB 2 + #define CM_EVENT_GAINB_BITS 1:1 + #define CM_EVENT_GAINB_SET 0x00000002 + #define CM_EVENT_GAINB_CLR 0xfffffffd + #define CM_EVENT_GAINB_MSB 1 + #define CM_EVENT_GAINB_LSB 1 + #define CM_EVENT_GAINA_BITS 0:0 + #define CM_EVENT_GAINA_SET 0x00000001 + #define CM_EVENT_GAINA_CLR 0xfffffffe + #define CM_EVENT_GAINA_MSB 0 + #define CM_EVENT_GAINA_LSB 0 +#define CM_INTEN HW_REGISTER_RW( 0x7e10111c ) + #define CM_INTEN_MASK 0x00ffffff + #define CM_INTEN_WIDTH 24 + #define CM_INTEN_RESET 0000000000 + #define CM_INTEN_BURSTDONE_BITS 23:23 + #define CM_INTEN_BURSTDONE_SET 0x00800000 + #define CM_INTEN_BURSTDONE_CLR 0xff7fffff + #define CM_INTEN_BURSTDONE_MSB 23 + #define CM_INTEN_BURSTDONE_LSB 23 + #define CM_INTEN_RESUS_BITS 22:22 + #define CM_INTEN_RESUS_SET 0x00400000 + #define CM_INTEN_RESUS_CLR 0xffbfffff + #define CM_INTEN_RESUS_MSB 22 + #define CM_INTEN_RESUS_LSB 22 + #define CM_INTEN_OCDONE_BITS 21:21 + #define CM_INTEN_OCDONE_SET 0x00200000 + #define CM_INTEN_OCDONE_CLR 0xffdfffff + #define CM_INTEN_OCDONE_MSB 21 + #define CM_INTEN_OCDONE_LSB 21 + #define CM_INTEN_A2WDONE_BITS 20:20 + #define CM_INTEN_A2WDONE_SET 0x00100000 + #define CM_INTEN_A2WDONE_CLR 0xffefffff + #define CM_INTEN_A2WDONE_MSB 20 + #define CM_INTEN_A2WDONE_LSB 20 + #define CM_INTEN_WRFAIL_BITS 19:19 + #define CM_INTEN_WRFAIL_SET 0x00080000 + #define CM_INTEN_WRFAIL_CLR 0xfff7ffff + #define CM_INTEN_WRFAIL_MSB 19 + #define CM_INTEN_WRFAIL_LSB 19 + #define CM_INTEN_BADPASS_BITS 18:18 + #define CM_INTEN_BADPASS_SET 0x00040000 + #define CM_INTEN_BADPASS_CLR 0xfffbffff + #define CM_INTEN_BADPASS_MSB 18 + #define CM_INTEN_BADPASS_LSB 18 + #define CM_INTEN_FLOSSD_BITS 17:17 + #define CM_INTEN_FLOSSD_SET 0x00020000 + #define CM_INTEN_FLOSSD_CLR 0xfffdffff + #define CM_INTEN_FLOSSD_MSB 17 + #define CM_INTEN_FLOSSD_LSB 17 + #define CM_INTEN_FLOSSC_BITS 16:16 + #define CM_INTEN_FLOSSC_SET 0x00010000 + #define CM_INTEN_FLOSSC_CLR 0xfffeffff + #define CM_INTEN_FLOSSC_MSB 16 + #define CM_INTEN_FLOSSC_LSB 16 + #define CM_INTEN_FLOSSB_BITS 15:15 + #define CM_INTEN_FLOSSB_SET 0x00008000 + #define CM_INTEN_FLOSSB_CLR 0xffff7fff + #define CM_INTEN_FLOSSB_MSB 15 + #define CM_INTEN_FLOSSB_LSB 15 + #define CM_INTEN_FLOSSA_BITS 14:14 + #define CM_INTEN_FLOSSA_SET 0x00004000 + #define CM_INTEN_FLOSSA_CLR 0xffffbfff + #define CM_INTEN_FLOSSA_MSB 14 + #define CM_INTEN_FLOSSA_LSB 14 + #define CM_INTEN_FGAIND_BITS 13:13 + #define CM_INTEN_FGAIND_SET 0x00002000 + #define CM_INTEN_FGAIND_CLR 0xffffdfff + #define CM_INTEN_FGAIND_MSB 13 + #define CM_INTEN_FGAIND_LSB 13 + #define CM_INTEN_FGAINC_BITS 12:12 + #define CM_INTEN_FGAINC_SET 0x00001000 + #define CM_INTEN_FGAINC_CLR 0xffffefff + #define CM_INTEN_FGAINC_MSB 12 + #define CM_INTEN_FGAINC_LSB 12 + #define CM_INTEN_FGAINB_BITS 11:11 + #define CM_INTEN_FGAINB_SET 0x00000800 + #define CM_INTEN_FGAINB_CLR 0xfffff7ff + #define CM_INTEN_FGAINB_MSB 11 + #define CM_INTEN_FGAINB_LSB 11 + #define CM_INTEN_FGAINA_BITS 10:10 + #define CM_INTEN_FGAINA_SET 0x00000400 + #define CM_INTEN_FGAINA_CLR 0xfffffbff + #define CM_INTEN_FGAINA_MSB 10 + #define CM_INTEN_FGAINA_LSB 10 + #define CM_INTEN_LOSSH_BITS 9:9 + #define CM_INTEN_LOSSH_SET 0x00000200 + #define CM_INTEN_LOSSH_CLR 0xfffffdff + #define CM_INTEN_LOSSH_MSB 9 + #define CM_INTEN_LOSSH_LSB 9 + #define CM_INTEN_LOSSD_BITS 8:8 + #define CM_INTEN_LOSSD_SET 0x00000100 + #define CM_INTEN_LOSSD_CLR 0xfffffeff + #define CM_INTEN_LOSSD_MSB 8 + #define CM_INTEN_LOSSD_LSB 8 + #define CM_INTEN_LOSSC_BITS 7:7 + #define CM_INTEN_LOSSC_SET 0x00000080 + #define CM_INTEN_LOSSC_CLR 0xffffff7f + #define CM_INTEN_LOSSC_MSB 7 + #define CM_INTEN_LOSSC_LSB 7 + #define CM_INTEN_LOSSB_BITS 6:6 + #define CM_INTEN_LOSSB_SET 0x00000040 + #define CM_INTEN_LOSSB_CLR 0xffffffbf + #define CM_INTEN_LOSSB_MSB 6 + #define CM_INTEN_LOSSB_LSB 6 + #define CM_INTEN_LOSSA_BITS 5:5 + #define CM_INTEN_LOSSA_SET 0x00000020 + #define CM_INTEN_LOSSA_CLR 0xffffffdf + #define CM_INTEN_LOSSA_MSB 5 + #define CM_INTEN_LOSSA_LSB 5 + #define CM_INTEN_GAINH_BITS 4:4 + #define CM_INTEN_GAINH_SET 0x00000010 + #define CM_INTEN_GAINH_CLR 0xffffffef + #define CM_INTEN_GAINH_MSB 4 + #define CM_INTEN_GAINH_LSB 4 + #define CM_INTEN_GAIND_BITS 3:3 + #define CM_INTEN_GAIND_SET 0x00000008 + #define CM_INTEN_GAIND_CLR 0xfffffff7 + #define CM_INTEN_GAIND_MSB 3 + #define CM_INTEN_GAIND_LSB 3 + #define CM_INTEN_GAINC_BITS 2:2 + #define CM_INTEN_GAINC_SET 0x00000004 + #define CM_INTEN_GAINC_CLR 0xfffffffb + #define CM_INTEN_GAINC_MSB 2 + #define CM_INTEN_GAINC_LSB 2 + #define CM_INTEN_GAINB_BITS 1:1 + #define CM_INTEN_GAINB_SET 0x00000002 + #define CM_INTEN_GAINB_CLR 0xfffffffd + #define CM_INTEN_GAINB_MSB 1 + #define CM_INTEN_GAINB_LSB 1 + #define CM_INTEN_GAINA_BITS 0:0 + #define CM_INTEN_GAINA_SET 0x00000001 + #define CM_INTEN_GAINA_CLR 0xfffffffe + #define CM_INTEN_GAINA_MSB 0 + #define CM_INTEN_GAINA_LSB 0 +#define CM_DSI0HSCK HW_REGISTER_RW( 0x7e101120 ) + #define CM_DSI0HSCK_MASK 0x00000001 + #define CM_DSI0HSCK_WIDTH 1 + #define CM_DSI0HSCK_RESET 0000000000 + #define CM_DSI0HSCK_SELPLLD_BITS 0:0 + #define CM_DSI0HSCK_SELPLLD_SET 0x00000001 + #define CM_DSI0HSCK_SELPLLD_CLR 0xfffffffe + #define CM_DSI0HSCK_SELPLLD_MSB 0 + #define CM_DSI0HSCK_SELPLLD_LSB 0 +#define CM_CKSM HW_REGISTER_RW( 0x7e101124 ) + #define CM_CKSM_MASK 0x003fffff + #define CM_CKSM_WIDTH 22 + #define CM_CKSM_RESET 0000000000 + #define CM_CKSM_STEP_BITS 21:21 + #define CM_CKSM_STEP_SET 0x00200000 + #define CM_CKSM_STEP_CLR 0xffdfffff + #define CM_CKSM_STEP_MSB 21 + #define CM_CKSM_STEP_LSB 21 + #define CM_CKSM_AUTO_BITS 20:20 + #define CM_CKSM_AUTO_SET 0x00100000 + #define CM_CKSM_AUTO_CLR 0xffefffff + #define CM_CKSM_AUTO_MSB 20 + #define CM_CKSM_AUTO_LSB 20 + #define CM_CKSM_OSC_BITS 19:18 + #define CM_CKSM_OSC_SET 0x000c0000 + #define CM_CKSM_OSC_CLR 0xfff3ffff + #define CM_CKSM_OSC_MSB 19 + #define CM_CKSM_OSC_LSB 18 + #define CM_CKSM_CFG_BITS 17:16 + #define CM_CKSM_CFG_SET 0x00030000 + #define CM_CKSM_CFG_CLR 0xfffcffff + #define CM_CKSM_CFG_MSB 17 + #define CM_CKSM_CFG_LSB 16 + #define CM_CKSM_FRCE_BITS 15:8 + #define CM_CKSM_FRCE_SET 0x0000ff00 + #define CM_CKSM_FRCE_CLR 0xffff00ff + #define CM_CKSM_FRCE_MSB 15 + #define CM_CKSM_FRCE_LSB 8 + #define CM_CKSM_STATE_BITS 7:0 + #define CM_CKSM_STATE_SET 0x000000ff + #define CM_CKSM_STATE_CLR 0xffffff00 + #define CM_CKSM_STATE_MSB 7 + #define CM_CKSM_STATE_LSB 0 +#define CM_OSCFREQI HW_REGISTER_RW( 0x7e101128 ) + #define CM_OSCFREQI_MASK 0x000000ff + #define CM_OSCFREQI_WIDTH 8 + #define CM_OSCFREQI_RESET 0000000000 + #define CM_OSCFREQI_INT_BITS 7:0 + #define CM_OSCFREQI_INT_SET 0x000000ff + #define CM_OSCFREQI_INT_CLR 0xffffff00 + #define CM_OSCFREQI_INT_MSB 7 + #define CM_OSCFREQI_INT_LSB 0 +#define CM_OSCFREQF HW_REGISTER_RW( 0x7e10112c ) + #define CM_OSCFREQF_MASK 0x000fffff + #define CM_OSCFREQF_WIDTH 20 + #define CM_OSCFREQF_RESET 0000000000 + #define CM_OSCFREQF_FRAC_BITS 19:0 + #define CM_OSCFREQF_FRAC_SET 0x000fffff + #define CM_OSCFREQF_FRAC_CLR 0xfff00000 + #define CM_OSCFREQF_FRAC_MSB 19 + #define CM_OSCFREQF_FRAC_LSB 0 +#define CM_PLLTCTL HW_REGISTER_RW( 0x7e101130 ) + #define CM_PLLTCTL_MASK 0x000000a7 + #define CM_PLLTCTL_WIDTH 8 + #define CM_PLLTCTL_RESET 0000000000 + #define CM_PLLTCTL_BUSY_BITS 7:7 + #define CM_PLLTCTL_BUSY_SET 0x00000080 + #define CM_PLLTCTL_BUSY_CLR 0xffffff7f + #define CM_PLLTCTL_BUSY_MSB 7 + #define CM_PLLTCTL_BUSY_LSB 7 + #define CM_PLLTCTL_KILL_BITS 5:5 + #define CM_PLLTCTL_KILL_SET 0x00000020 + #define CM_PLLTCTL_KILL_CLR 0xffffffdf + #define CM_PLLTCTL_KILL_MSB 5 + #define CM_PLLTCTL_KILL_LSB 5 + #define CM_PLLTCTL_SRC_BITS 2:0 + #define CM_PLLTCTL_SRC_SET 0x00000007 + #define CM_PLLTCTL_SRC_CLR 0xfffffff8 + #define CM_PLLTCTL_SRC_MSB 2 + #define CM_PLLTCTL_SRC_LSB 0 +#define CM_PLLTCNT0 HW_REGISTER_RW( 0x7e101134 ) + #define CM_PLLTCNT0_MASK 0x00ffffff + #define CM_PLLTCNT0_WIDTH 24 + #define CM_PLLTCNT0_RESET 0000000000 + #define CM_PLLTCNT0_CNT_BITS 23:0 + #define CM_PLLTCNT0_CNT_SET 0x00ffffff + #define CM_PLLTCNT0_CNT_CLR 0xff000000 + #define CM_PLLTCNT0_CNT_MSB 23 + #define CM_PLLTCNT0_CNT_LSB 0 +#define CM_PLLTCNT1 HW_REGISTER_RW( 0x7e101138 ) + #define CM_PLLTCNT1_MASK 0x00ffffff + #define CM_PLLTCNT1_WIDTH 24 + #define CM_PLLTCNT1_RESET 0000000000 + #define CM_PLLTCNT1_CNT_BITS 23:0 + #define CM_PLLTCNT1_CNT_SET 0x00ffffff + #define CM_PLLTCNT1_CNT_CLR 0xff000000 + #define CM_PLLTCNT1_CNT_MSB 23 + #define CM_PLLTCNT1_CNT_LSB 0 +#define CM_PLLTCNT2 HW_REGISTER_RW( 0x7e10113c ) + #define CM_PLLTCNT2_MASK 0x00ffffff + #define CM_PLLTCNT2_WIDTH 24 + #define CM_PLLTCNT2_RESET 0000000000 + #define CM_PLLTCNT2_CNT_BITS 23:0 + #define CM_PLLTCNT2_CNT_SET 0x00ffffff + #define CM_PLLTCNT2_CNT_CLR 0xff000000 + #define CM_PLLTCNT2_CNT_MSB 23 + #define CM_PLLTCNT2_CNT_LSB 0 +#define CM_PLLTCNT3 HW_REGISTER_RW( 0x7e101140 ) + #define CM_PLLTCNT3_MASK 0x00ffffff + #define CM_PLLTCNT3_WIDTH 24 + #define CM_PLLTCNT3_RESET 0000000000 + #define CM_PLLTCNT3_CNT_BITS 23:0 + #define CM_PLLTCNT3_CNT_SET 0x00ffffff + #define CM_PLLTCNT3_CNT_CLR 0xff000000 + #define CM_PLLTCNT3_CNT_MSB 23 + #define CM_PLLTCNT3_CNT_LSB 0 +#define CM_TDCLKEN HW_REGISTER_RW( 0x7e101144 ) + #define CM_TDCLKEN_MASK 0x00003fff + #define CM_TDCLKEN_WIDTH 14 + #define CM_TDCLKEN_RESET 0000000000 + #define CM_TDCLKEN_IMAGETD_BITS 13:13 + #define CM_TDCLKEN_IMAGETD_SET 0x00002000 + #define CM_TDCLKEN_IMAGETD_CLR 0xffffdfff + #define CM_TDCLKEN_IMAGETD_MSB 13 + #define CM_TDCLKEN_IMAGETD_LSB 13 + #define CM_TDCLKEN_SLIMDFT_BITS 12:12 + #define CM_TDCLKEN_SLIMDFT_SET 0x00001000 + #define CM_TDCLKEN_SLIMDFT_CLR 0xffffefff + #define CM_TDCLKEN_SLIMDFT_MSB 12 + #define CM_TDCLKEN_SLIMDFT_LSB 12 + #define CM_TDCLKEN_USBDFT_BITS 11:11 + #define CM_TDCLKEN_USBDFT_SET 0x00000800 + #define CM_TDCLKEN_USBDFT_CLR 0xfffff7ff + #define CM_TDCLKEN_USBDFT_MSB 11 + #define CM_TDCLKEN_USBDFT_LSB 11 + #define CM_TDCLKEN_MPHIRDFT_BITS 10:10 + #define CM_TDCLKEN_MPHIRDFT_SET 0x00000400 + #define CM_TDCLKEN_MPHIRDFT_CLR 0xfffffbff + #define CM_TDCLKEN_MPHIRDFT_MSB 10 + #define CM_TDCLKEN_MPHIRDFT_LSB 10 + #define CM_TDCLKEN_MPHIWDFT_BITS 9:9 + #define CM_TDCLKEN_MPHIWDFT_SET 0x00000200 + #define CM_TDCLKEN_MPHIWDFT_CLR 0xfffffdff + #define CM_TDCLKEN_MPHIWDFT_MSB 9 + #define CM_TDCLKEN_MPHIWDFT_LSB 9 + #define CM_TDCLKEN_HDMIBYP_BITS 8:8 + #define CM_TDCLKEN_HDMIBYP_SET 0x00000100 + #define CM_TDCLKEN_HDMIBYP_CLR 0xfffffeff + #define CM_TDCLKEN_HDMIBYP_MSB 8 + #define CM_TDCLKEN_HDMIBYP_LSB 8 + #define CM_TDCLKEN_PLLDDIV2_BITS 7:7 + #define CM_TDCLKEN_PLLDDIV2_SET 0x00000080 + #define CM_TDCLKEN_PLLDDIV2_CLR 0xffffff7f + #define CM_TDCLKEN_PLLDDIV2_MSB 7 + #define CM_TDCLKEN_PLLDDIV2_LSB 7 + #define CM_TDCLKEN_PLLCDIV2_BITS 6:6 + #define CM_TDCLKEN_PLLCDIV2_SET 0x00000040 + #define CM_TDCLKEN_PLLCDIV2_CLR 0xffffffbf + #define CM_TDCLKEN_PLLCDIV2_MSB 6 + #define CM_TDCLKEN_PLLCDIV2_LSB 6 + #define CM_TDCLKEN_PLLBDIV2_BITS 5:5 + #define CM_TDCLKEN_PLLBDIV2_SET 0x00000020 + #define CM_TDCLKEN_PLLBDIV2_CLR 0xffffffdf + #define CM_TDCLKEN_PLLBDIV2_MSB 5 + #define CM_TDCLKEN_PLLBDIV2_LSB 5 + #define CM_TDCLKEN_PLLADIV2_BITS 4:4 + #define CM_TDCLKEN_PLLADIV2_SET 0x00000010 + #define CM_TDCLKEN_PLLADIV2_CLR 0xffffffef + #define CM_TDCLKEN_PLLADIV2_MSB 4 + #define CM_TDCLKEN_PLLADIV2_LSB 4 + #define CM_TDCLKEN_PLLDBYP_BITS 3:3 + #define CM_TDCLKEN_PLLDBYP_SET 0x00000008 + #define CM_TDCLKEN_PLLDBYP_CLR 0xfffffff7 + #define CM_TDCLKEN_PLLDBYP_MSB 3 + #define CM_TDCLKEN_PLLDBYP_LSB 3 + #define CM_TDCLKEN_PLLCBYP_BITS 2:2 + #define CM_TDCLKEN_PLLCBYP_SET 0x00000004 + #define CM_TDCLKEN_PLLCBYP_CLR 0xfffffffb + #define CM_TDCLKEN_PLLCBYP_MSB 2 + #define CM_TDCLKEN_PLLCBYP_LSB 2 + #define CM_TDCLKEN_PLLBBYP_BITS 1:1 + #define CM_TDCLKEN_PLLBBYP_SET 0x00000002 + #define CM_TDCLKEN_PLLBBYP_CLR 0xfffffffd + #define CM_TDCLKEN_PLLBBYP_MSB 1 + #define CM_TDCLKEN_PLLBBYP_LSB 1 + #define CM_TDCLKEN_PLLABYP_BITS 0:0 + #define CM_TDCLKEN_PLLABYP_SET 0x00000001 + #define CM_TDCLKEN_PLLABYP_CLR 0xfffffffe + #define CM_TDCLKEN_PLLABYP_MSB 0 + #define CM_TDCLKEN_PLLABYP_LSB 0 +#define CM_BURSTCTL HW_REGISTER_RW( 0x7e101148 ) + #define CM_BURSTCTL_MASK 0x000000b0 + #define CM_BURSTCTL_WIDTH 8 + #define CM_BURSTCTL_RESET 0000000000 + #define CM_BURSTCTL_BUSY_BITS 7:7 + #define CM_BURSTCTL_BUSY_SET 0x00000080 + #define CM_BURSTCTL_BUSY_CLR 0xffffff7f + #define CM_BURSTCTL_BUSY_MSB 7 + #define CM_BURSTCTL_BUSY_LSB 7 + #define CM_BURSTCTL_KILL_BITS 5:5 + #define CM_BURSTCTL_KILL_SET 0x00000020 + #define CM_BURSTCTL_KILL_CLR 0xffffffdf + #define CM_BURSTCTL_KILL_MSB 5 + #define CM_BURSTCTL_KILL_LSB 5 + #define CM_BURSTCTL_ENAB_BITS 4:4 + #define CM_BURSTCTL_ENAB_SET 0x00000010 + #define CM_BURSTCTL_ENAB_CLR 0xffffffef + #define CM_BURSTCTL_ENAB_MSB 4 + #define CM_BURSTCTL_ENAB_LSB 4 +#define CM_BURSTCNT HW_REGISTER_RW( 0x7e10114c ) + #define CM_BURSTCNT_MASK 0x00ffffff + #define CM_BURSTCNT_WIDTH 24 + #define CM_BURSTCNT_RESET 0000000000 + #define CM_BURSTCNT_CNT_BITS 23:0 + #define CM_BURSTCNT_CNT_SET 0x00ffffff + #define CM_BURSTCNT_CNT_CLR 0xff000000 + #define CM_BURSTCNT_CNT_MSB 23 + #define CM_BURSTCNT_CNT_LSB 0 +#define CM_STOPCLK HW_REGISTER_RW( 0x7e101150 ) + #define CM_STOPCLK_MASK 0x00000001 + #define CM_STOPCLK_WIDTH 1 + #define CM_STOPCLK_RESET 0000000000 + #define CM_STOPCLK_ALL_BITS 0:0 + #define CM_STOPCLK_ALL_SET 0x00000001 + #define CM_STOPCLK_ALL_CLR 0xfffffffe + #define CM_STOPCLK_ALL_MSB 0 + #define CM_STOPCLK_ALL_LSB 0 + +#else + +// This file was generated by the create_regs script +#define CM_PASSWORD 0x5a000000 +#define CM_BASE 0x7e101000 +#define CM_APB_ID 0x0000636d +#define CM_GNRICCTL HW_REGISTER_RW( 0x7e101000 ) + #define CM_GNRICCTL_MASK 0x000fffff + #define CM_GNRICCTL_WIDTH 20 + #define CM_GNRICCTL_RESET 0000000000 + #define CM_GNRICCTL_MASH_BITS 10:9 + #define CM_GNRICCTL_MASH_SET 0x00000600 + #define CM_GNRICCTL_MASH_CLR 0xfffff9ff + #define CM_GNRICCTL_MASH_MSB 10 + #define CM_GNRICCTL_MASH_LSB 9 + #define CM_GNRICCTL_FLIP_BITS 8:8 + #define CM_GNRICCTL_FLIP_SET 0x00000100 + #define CM_GNRICCTL_FLIP_CLR 0xfffffeff + #define CM_GNRICCTL_FLIP_MSB 8 + #define CM_GNRICCTL_FLIP_LSB 8 + #define CM_GNRICCTL_BUSY_BITS 7:7 + #define CM_GNRICCTL_BUSY_SET 0x00000080 + #define CM_GNRICCTL_BUSY_CLR 0xffffff7f + #define CM_GNRICCTL_BUSY_MSB 7 + #define CM_GNRICCTL_BUSY_LSB 7 + #define CM_GNRICCTL_GATE_BITS 6:6 + #define CM_GNRICCTL_GATE_SET 0x00000040 + #define CM_GNRICCTL_GATE_CLR 0xffffffbf + #define CM_GNRICCTL_GATE_MSB 6 + #define CM_GNRICCTL_GATE_LSB 6 + #define CM_GNRICCTL_KILL_BITS 5:5 + #define CM_GNRICCTL_KILL_SET 0x00000020 + #define CM_GNRICCTL_KILL_CLR 0xffffffdf + #define CM_GNRICCTL_KILL_MSB 5 + #define CM_GNRICCTL_KILL_LSB 5 + #define CM_GNRICCTL_ENAB_BITS 4:4 + #define CM_GNRICCTL_ENAB_SET 0x00000010 + #define CM_GNRICCTL_ENAB_CLR 0xffffffef + #define CM_GNRICCTL_ENAB_MSB 4 + #define CM_GNRICCTL_ENAB_LSB 4 + #define CM_GNRICCTL_SRC_BITS 3:0 + #define CM_GNRICCTL_SRC_SET 0x0000000f + #define CM_GNRICCTL_SRC_CLR 0xfffffff0 + #define CM_GNRICCTL_SRC_MSB 3 + #define CM_GNRICCTL_SRC_LSB 0 +#define CM_GNRICDIV HW_REGISTER_RW( 0x7e101004 ) + #define CM_GNRICDIV_MASK 0x00ffffff + #define CM_GNRICDIV_WIDTH 24 + #define CM_GNRICDIV_RESET 0000000000 + #define CM_GNRICDIV_DIV_BITS 23:0 + #define CM_GNRICDIV_DIV_SET 0x00ffffff + #define CM_GNRICDIV_DIV_CLR 0xff000000 + #define CM_GNRICDIV_DIV_MSB 23 + #define CM_GNRICDIV_DIV_LSB 0 +#define CM_VPUCTL HW_REGISTER_RW( 0x7e101008 ) + #define CM_VPUCTL_MASK 0x000000cf + #define CM_VPUCTL_WIDTH 8 + #define CM_VPUCTL_RESET 0x00000041 + #define CM_VPUCTL_BUSY_BITS 7:7 + #define CM_VPUCTL_BUSY_SET 0x00000080 + #define CM_VPUCTL_BUSY_CLR 0xffffff7f + #define CM_VPUCTL_BUSY_MSB 7 + #define CM_VPUCTL_BUSY_LSB 7 + #define CM_VPUCTL_GATE_BITS 6:6 + #define CM_VPUCTL_GATE_SET 0x00000040 + #define CM_VPUCTL_GATE_CLR 0xffffffbf + #define CM_VPUCTL_GATE_MSB 6 + #define CM_VPUCTL_GATE_LSB 6 + #define CM_VPUCTL_SRC_BITS 3:0 + #define CM_VPUCTL_SRC_SET 0x0000000f + #define CM_VPUCTL_SRC_CLR 0xfffffff0 + #define CM_VPUCTL_SRC_MSB 3 + #define CM_VPUCTL_SRC_LSB 0 +#define CM_VPUDIV HW_REGISTER_RW( 0x7e10100c ) + #define CM_VPUDIV_MASK 0x00fffff0 + #define CM_VPUDIV_WIDTH 24 + #define CM_VPUDIV_RESET 0x00001000 + #define CM_VPUDIV_DIV_BITS 23:4 + #define CM_VPUDIV_DIV_SET 0x00fffff0 + #define CM_VPUDIV_DIV_CLR 0xff00000f + #define CM_VPUDIV_DIV_MSB 23 + #define CM_VPUDIV_DIV_LSB 4 +#define CM_SYSCTL HW_REGISTER_RW( 0x7e101010 ) + #define CM_SYSCTL_MASK 0x00000040 + #define CM_SYSCTL_WIDTH 7 + #define CM_SYSCTL_RESET 0x00000040 + #define CM_SYSCTL_GATE_BITS 6:6 + #define CM_SYSCTL_GATE_SET 0x00000040 + #define CM_SYSCTL_GATE_CLR 0xffffffbf + #define CM_SYSCTL_GATE_MSB 6 + #define CM_SYSCTL_GATE_LSB 6 +#define CM_SYSDIV HW_REGISTER_RO( 0x7e101014 ) + #define CM_SYSDIV_MASK 0x00001000 + #define CM_SYSDIV_WIDTH 13 + #define CM_SYSDIV_RESET 0x00001000 + #define CM_SYSDIV_DIV_BITS 12:12 + #define CM_SYSDIV_DIV_SET 0x00001000 + #define CM_SYSDIV_DIV_CLR 0xffffefff + #define CM_SYSDIV_DIV_MSB 12 + #define CM_SYSDIV_DIV_LSB 12 +#define CM_PERIACTL HW_REGISTER_RW( 0x7e101018 ) + #define CM_PERIACTL_MASK 0x00000040 + #define CM_PERIACTL_WIDTH 7 + #define CM_PERIACTL_RESET 0x00000040 + #define CM_PERIACTL_GATE_BITS 6:6 + #define CM_PERIACTL_GATE_SET 0x00000040 + #define CM_PERIACTL_GATE_CLR 0xffffffbf + #define CM_PERIACTL_GATE_MSB 6 + #define CM_PERIACTL_GATE_LSB 6 +#define CM_PERIADIV HW_REGISTER_RO( 0x7e10101c ) + #define CM_PERIADIV_MASK 0x00001000 + #define CM_PERIADIV_WIDTH 13 + #define CM_PERIADIV_RESET 0x00001000 + #define CM_PERIADIV_DIV_BITS 12:12 + #define CM_PERIADIV_DIV_SET 0x00001000 + #define CM_PERIADIV_DIV_CLR 0xffffefff + #define CM_PERIADIV_DIV_MSB 12 + #define CM_PERIADIV_DIV_LSB 12 +#define CM_PERIICTL HW_REGISTER_RW( 0x7e101020 ) + #define CM_PERIICTL_MASK 0x00000040 + #define CM_PERIICTL_WIDTH 7 + #define CM_PERIICTL_RESET 0000000000 + #define CM_PERIICTL_GATE_BITS 6:6 + #define CM_PERIICTL_GATE_SET 0x00000040 + #define CM_PERIICTL_GATE_CLR 0xffffffbf + #define CM_PERIICTL_GATE_MSB 6 + #define CM_PERIICTL_GATE_LSB 6 +#define CM_PERIIDIV HW_REGISTER_RO( 0x7e101024 ) + #define CM_PERIIDIV_MASK 0x00001000 + #define CM_PERIIDIV_WIDTH 13 + #define CM_PERIIDIV_RESET 0x00001000 + #define CM_PERIIDIV_DIV_BITS 12:12 + #define CM_PERIIDIV_DIV_SET 0x00001000 + #define CM_PERIIDIV_DIV_CLR 0xffffefff + #define CM_PERIIDIV_DIV_MSB 12 + #define CM_PERIIDIV_DIV_LSB 12 +#define CM_H264CTL HW_REGISTER_RW( 0x7e101028 ) + #define CM_H264CTL_MASK 0x000000ff + #define CM_H264CTL_WIDTH 8 + #define CM_H264CTL_RESET 0x00000040 + #define CM_H264CTL_BUSY_BITS 7:7 + #define CM_H264CTL_BUSY_SET 0x00000080 + #define CM_H264CTL_BUSY_CLR 0xffffff7f + #define CM_H264CTL_BUSY_MSB 7 + #define CM_H264CTL_BUSY_LSB 7 + #define CM_H264CTL_GATE_BITS 6:6 + #define CM_H264CTL_GATE_SET 0x00000040 + #define CM_H264CTL_GATE_CLR 0xffffffbf + #define CM_H264CTL_GATE_MSB 6 + #define CM_H264CTL_GATE_LSB 6 + #define CM_H264CTL_KILL_BITS 5:5 + #define CM_H264CTL_KILL_SET 0x00000020 + #define CM_H264CTL_KILL_CLR 0xffffffdf + #define CM_H264CTL_KILL_MSB 5 + #define CM_H264CTL_KILL_LSB 5 + #define CM_H264CTL_ENAB_BITS 4:4 + #define CM_H264CTL_ENAB_SET 0x00000010 + #define CM_H264CTL_ENAB_CLR 0xffffffef + #define CM_H264CTL_ENAB_MSB 4 + #define CM_H264CTL_ENAB_LSB 4 + #define CM_H264CTL_SRC_BITS 3:0 + #define CM_H264CTL_SRC_SET 0x0000000f + #define CM_H264CTL_SRC_CLR 0xfffffff0 + #define CM_H264CTL_SRC_MSB 3 + #define CM_H264CTL_SRC_LSB 0 +#define CM_H264DIV HW_REGISTER_RW( 0x7e10102c ) + #define CM_H264DIV_MASK 0x0000fff0 + #define CM_H264DIV_WIDTH 16 + #define CM_H264DIV_RESET 0000000000 + #define CM_H264DIV_DIV_BITS 15:4 + #define CM_H264DIV_DIV_SET 0x0000fff0 + #define CM_H264DIV_DIV_CLR 0xffff000f + #define CM_H264DIV_DIV_MSB 15 + #define CM_H264DIV_DIV_LSB 4 +#define CM_ISPCTL HW_REGISTER_RW( 0x7e101030 ) + #define CM_ISPCTL_MASK 0x000000ff + #define CM_ISPCTL_WIDTH 8 + #define CM_ISPCTL_RESET 0x00000040 + #define CM_ISPCTL_BUSY_BITS 7:7 + #define CM_ISPCTL_BUSY_SET 0x00000080 + #define CM_ISPCTL_BUSY_CLR 0xffffff7f + #define CM_ISPCTL_BUSY_MSB 7 + #define CM_ISPCTL_BUSY_LSB 7 + #define CM_ISPCTL_GATE_BITS 6:6 + #define CM_ISPCTL_GATE_SET 0x00000040 + #define CM_ISPCTL_GATE_CLR 0xffffffbf + #define CM_ISPCTL_GATE_MSB 6 + #define CM_ISPCTL_GATE_LSB 6 + #define CM_ISPCTL_KILL_BITS 5:5 + #define CM_ISPCTL_KILL_SET 0x00000020 + #define CM_ISPCTL_KILL_CLR 0xffffffdf + #define CM_ISPCTL_KILL_MSB 5 + #define CM_ISPCTL_KILL_LSB 5 + #define CM_ISPCTL_ENAB_BITS 4:4 + #define CM_ISPCTL_ENAB_SET 0x00000010 + #define CM_ISPCTL_ENAB_CLR 0xffffffef + #define CM_ISPCTL_ENAB_MSB 4 + #define CM_ISPCTL_ENAB_LSB 4 + #define CM_ISPCTL_SRC_BITS 3:0 + #define CM_ISPCTL_SRC_SET 0x0000000f + #define CM_ISPCTL_SRC_CLR 0xfffffff0 + #define CM_ISPCTL_SRC_MSB 3 + #define CM_ISPCTL_SRC_LSB 0 +#define CM_ISPDIV HW_REGISTER_RW( 0x7e101034 ) + #define CM_ISPDIV_MASK 0x0000fff0 + #define CM_ISPDIV_WIDTH 16 + #define CM_ISPDIV_RESET 0000000000 + #define CM_ISPDIV_DIV_BITS 15:4 + #define CM_ISPDIV_DIV_SET 0x0000fff0 + #define CM_ISPDIV_DIV_CLR 0xffff000f + #define CM_ISPDIV_DIV_MSB 15 + #define CM_ISPDIV_DIV_LSB 4 +#define CM_ARMCTL HW_REGISTER_RW( 0x7e1011b0 ) + #define CM_ARMCTL_MASK 0x000011b3 + #define CM_ARMCTL_WIDTH 13 + #define CM_ARMCTL_RESET 0000000000 + #define CM_ARMCTL_AXIHALF_BITS 12:12 + #define CM_ARMCTL_AXIHALF_SET 0x00001000 + #define CM_ARMCTL_AXIHALF_CLR 0xffffefff + #define CM_ARMCTL_AXIHALF_MSB 12 + #define CM_ARMCTL_AXIHALF_LSB 12 + #define CM_ARMCTL_FLIP_BITS 8:8 + #define CM_ARMCTL_FLIP_SET 0x00000100 + #define CM_ARMCTL_FLIP_CLR 0xfffffeff + #define CM_ARMCTL_FLIP_MSB 8 + #define CM_ARMCTL_FLIP_LSB 8 + #define CM_ARMCTL_BUSY_BITS 7:7 + #define CM_ARMCTL_BUSY_SET 0x00000080 + #define CM_ARMCTL_BUSY_CLR 0xffffff7f + #define CM_ARMCTL_BUSY_MSB 7 + #define CM_ARMCTL_BUSY_LSB 7 + #define CM_ARMCTL_KILL_BITS 5:5 + #define CM_ARMCTL_KILL_SET 0x00000020 + #define CM_ARMCTL_KILL_CLR 0xffffffdf + #define CM_ARMCTL_KILL_MSB 5 + #define CM_ARMCTL_KILL_LSB 5 + #define CM_ARMCTL_ENAB_BITS 4:4 + #define CM_ARMCTL_ENAB_SET 0x00000010 + #define CM_ARMCTL_ENAB_CLR 0xffffffef + #define CM_ARMCTL_ENAB_MSB 4 + #define CM_ARMCTL_ENAB_LSB 4 + #define CM_ARMCTL_SRC_BITS 1:0 + #define CM_ARMCTL_SRC_SET 0x00000003 + #define CM_ARMCTL_SRC_CLR 0xfffffffc + #define CM_ARMCTL_SRC_MSB 1 + #define CM_ARMCTL_SRC_LSB 0 +#define CM_ARMDIV HW_REGISTER_RO( 0x7e1011b4 ) + #define CM_ARMDIV_MASK 0x00001000 + #define CM_ARMDIV_WIDTH 13 + #define CM_ARMDIV_RESET 0x00001000 + #define CM_ARMDIV_DIV_BITS 12:12 + #define CM_ARMDIV_DIV_SET 0x00001000 + #define CM_ARMDIV_DIV_CLR 0xffffefff + #define CM_ARMDIV_DIV_MSB 12 + #define CM_ARMDIV_DIV_LSB 12 +#define CM_SDCCTL HW_REGISTER_RW( 0x7e1011a8 ) + #define CM_SDCCTL_MASK 0x0003f0bf + #define CM_SDCCTL_WIDTH 18 + #define CM_SDCCTL_RESET 0x00004000 + #define CM_SDCCTL_UPDATE_BITS 17:17 + #define CM_SDCCTL_UPDATE_SET 0x00020000 + #define CM_SDCCTL_UPDATE_CLR 0xfffdffff + #define CM_SDCCTL_UPDATE_MSB 17 + #define CM_SDCCTL_UPDATE_LSB 17 + #define CM_SDCCTL_ACCPT_BITS 16:16 + #define CM_SDCCTL_ACCPT_SET 0x00010000 + #define CM_SDCCTL_ACCPT_CLR 0xfffeffff + #define CM_SDCCTL_ACCPT_MSB 16 + #define CM_SDCCTL_ACCPT_LSB 16 + #define CM_SDCCTL_CTRL_BITS 15:12 + #define CM_SDCCTL_CTRL_SET 0x0000f000 + #define CM_SDCCTL_CTRL_CLR 0xffff0fff + #define CM_SDCCTL_CTRL_MSB 15 + #define CM_SDCCTL_CTRL_LSB 12 + #define CM_SDCCTL_BUSY_BITS 7:7 + #define CM_SDCCTL_BUSY_SET 0x00000080 + #define CM_SDCCTL_BUSY_CLR 0xffffff7f + #define CM_SDCCTL_BUSY_MSB 7 + #define CM_SDCCTL_BUSY_LSB 7 + #define CM_SDCCTL_KILL_BITS 5:5 + #define CM_SDCCTL_KILL_SET 0x00000020 + #define CM_SDCCTL_KILL_CLR 0xffffffdf + #define CM_SDCCTL_KILL_MSB 5 + #define CM_SDCCTL_KILL_LSB 5 + #define CM_SDCCTL_ENAB_BITS 4:4 + #define CM_SDCCTL_ENAB_SET 0x00000010 + #define CM_SDCCTL_ENAB_CLR 0xffffffef + #define CM_SDCCTL_ENAB_MSB 4 + #define CM_SDCCTL_ENAB_LSB 4 + #define CM_SDCCTL_SRC_BITS 3:0 + #define CM_SDCCTL_SRC_SET 0x0000000f + #define CM_SDCCTL_SRC_CLR 0xfffffff0 + #define CM_SDCCTL_SRC_MSB 3 + #define CM_SDCCTL_SRC_LSB 0 +#define CM_SDCDIV HW_REGISTER_RW( 0x7e1011ac ) + #define CM_SDCDIV_MASK 0x0003f000 + #define CM_SDCDIV_WIDTH 18 + #define CM_SDCDIV_RESET 0000000000 + #define CM_SDCDIV_DIV_BITS 17:12 + #define CM_SDCDIV_DIV_SET 0x0003f000 + #define CM_SDCDIV_DIV_CLR 0xfffc0fff + #define CM_SDCDIV_DIV_MSB 17 + #define CM_SDCDIV_DIV_LSB 12 +#define CM_V3DCTL HW_REGISTER_RW( 0x7e101038 ) + #define CM_V3DCTL_MASK 0x000000ff + #define CM_V3DCTL_WIDTH 8 + #define CM_V3DCTL_RESET 0x00000040 + #define CM_V3DCTL_BUSY_BITS 7:7 + #define CM_V3DCTL_BUSY_SET 0x00000080 + #define CM_V3DCTL_BUSY_CLR 0xffffff7f + #define CM_V3DCTL_BUSY_MSB 7 + #define CM_V3DCTL_BUSY_LSB 7 + #define CM_V3DCTL_GATE_BITS 6:6 + #define CM_V3DCTL_GATE_SET 0x00000040 + #define CM_V3DCTL_GATE_CLR 0xffffffbf + #define CM_V3DCTL_GATE_MSB 6 + #define CM_V3DCTL_GATE_LSB 6 + #define CM_V3DCTL_KILL_BITS 5:5 + #define CM_V3DCTL_KILL_SET 0x00000020 + #define CM_V3DCTL_KILL_CLR 0xffffffdf + #define CM_V3DCTL_KILL_MSB 5 + #define CM_V3DCTL_KILL_LSB 5 + #define CM_V3DCTL_ENAB_BITS 4:4 + #define CM_V3DCTL_ENAB_SET 0x00000010 + #define CM_V3DCTL_ENAB_CLR 0xffffffef + #define CM_V3DCTL_ENAB_MSB 4 + #define CM_V3DCTL_ENAB_LSB 4 + #define CM_V3DCTL_SRC_BITS 3:0 + #define CM_V3DCTL_SRC_SET 0x0000000f + #define CM_V3DCTL_SRC_CLR 0xfffffff0 + #define CM_V3DCTL_SRC_MSB 3 + #define CM_V3DCTL_SRC_LSB 0 +#define CM_V3DDIV HW_REGISTER_RW( 0x7e10103c ) + #define CM_V3DDIV_MASK 0x0000fff0 + #define CM_V3DDIV_WIDTH 16 + #define CM_V3DDIV_RESET 0000000000 + #define CM_V3DDIV_DIV_BITS 15:4 + #define CM_V3DDIV_DIV_SET 0x0000fff0 + #define CM_V3DDIV_DIV_CLR 0xffff000f + #define CM_V3DDIV_DIV_MSB 15 + #define CM_V3DDIV_DIV_LSB 4 +#define CM_CAM0CTL HW_REGISTER_RW( 0x7e101040 ) + #define CM_CAM0CTL_MASK 0x000000bf + #define CM_CAM0CTL_WIDTH 8 + #define CM_CAM0CTL_RESET 0000000000 + #define CM_CAM0CTL_BUSY_BITS 7:7 + #define CM_CAM0CTL_BUSY_SET 0x00000080 + #define CM_CAM0CTL_BUSY_CLR 0xffffff7f + #define CM_CAM0CTL_BUSY_MSB 7 + #define CM_CAM0CTL_BUSY_LSB 7 + #define CM_CAM0CTL_KILL_BITS 5:5 + #define CM_CAM0CTL_KILL_SET 0x00000020 + #define CM_CAM0CTL_KILL_CLR 0xffffffdf + #define CM_CAM0CTL_KILL_MSB 5 + #define CM_CAM0CTL_KILL_LSB 5 + #define CM_CAM0CTL_ENAB_BITS 4:4 + #define CM_CAM0CTL_ENAB_SET 0x00000010 + #define CM_CAM0CTL_ENAB_CLR 0xffffffef + #define CM_CAM0CTL_ENAB_MSB 4 + #define CM_CAM0CTL_ENAB_LSB 4 + #define CM_CAM0CTL_SRC_BITS 3:0 + #define CM_CAM0CTL_SRC_SET 0x0000000f + #define CM_CAM0CTL_SRC_CLR 0xfffffff0 + #define CM_CAM0CTL_SRC_MSB 3 + #define CM_CAM0CTL_SRC_LSB 0 +#define CM_CAM0DIV HW_REGISTER_RW( 0x7e101044 ) + #define CM_CAM0DIV_MASK 0x0000fff0 + #define CM_CAM0DIV_WIDTH 16 + #define CM_CAM0DIV_RESET 0000000000 + #define CM_CAM0DIV_DIV_BITS 15:4 + #define CM_CAM0DIV_DIV_SET 0x0000fff0 + #define CM_CAM0DIV_DIV_CLR 0xffff000f + #define CM_CAM0DIV_DIV_MSB 15 + #define CM_CAM0DIV_DIV_LSB 4 +#define CM_CAM1CTL HW_REGISTER_RW( 0x7e101048 ) + #define CM_CAM1CTL_MASK 0x000000bf + #define CM_CAM1CTL_WIDTH 8 + #define CM_CAM1CTL_RESET 0000000000 + #define CM_CAM1CTL_BUSY_BITS 7:7 + #define CM_CAM1CTL_BUSY_SET 0x00000080 + #define CM_CAM1CTL_BUSY_CLR 0xffffff7f + #define CM_CAM1CTL_BUSY_MSB 7 + #define CM_CAM1CTL_BUSY_LSB 7 + #define CM_CAM1CTL_KILL_BITS 5:5 + #define CM_CAM1CTL_KILL_SET 0x00000020 + #define CM_CAM1CTL_KILL_CLR 0xffffffdf + #define CM_CAM1CTL_KILL_MSB 5 + #define CM_CAM1CTL_KILL_LSB 5 + #define CM_CAM1CTL_ENAB_BITS 4:4 + #define CM_CAM1CTL_ENAB_SET 0x00000010 + #define CM_CAM1CTL_ENAB_CLR 0xffffffef + #define CM_CAM1CTL_ENAB_MSB 4 + #define CM_CAM1CTL_ENAB_LSB 4 + #define CM_CAM1CTL_SRC_BITS 3:0 + #define CM_CAM1CTL_SRC_SET 0x0000000f + #define CM_CAM1CTL_SRC_CLR 0xfffffff0 + #define CM_CAM1CTL_SRC_MSB 3 + #define CM_CAM1CTL_SRC_LSB 0 +#define CM_CAM1DIV HW_REGISTER_RW( 0x7e10104c ) + #define CM_CAM1DIV_MASK 0x0000fff0 + #define CM_CAM1DIV_WIDTH 16 + #define CM_CAM1DIV_RESET 0000000000 + #define CM_CAM1DIV_DIV_BITS 15:4 + #define CM_CAM1DIV_DIV_SET 0x0000fff0 + #define CM_CAM1DIV_DIV_CLR 0xffff000f + #define CM_CAM1DIV_DIV_MSB 15 + #define CM_CAM1DIV_DIV_LSB 4 +#define CM_CCP2CTL HW_REGISTER_RW( 0x7e101050 ) + #define CM_CCP2CTL_MASK 0x00000017 + #define CM_CCP2CTL_WIDTH 5 + #define CM_CCP2CTL_RESET 0000000000 + #define CM_CCP2CTL_ENAB_BITS 4:4 + #define CM_CCP2CTL_ENAB_SET 0x00000010 + #define CM_CCP2CTL_ENAB_CLR 0xffffffef + #define CM_CCP2CTL_ENAB_MSB 4 + #define CM_CCP2CTL_ENAB_LSB 4 + #define CM_CCP2CTL_SRC_BITS 2:0 + #define CM_CCP2CTL_SRC_SET 0x00000007 + #define CM_CCP2CTL_SRC_CLR 0xfffffff8 + #define CM_CCP2CTL_SRC_MSB 2 + #define CM_CCP2CTL_SRC_LSB 0 +#define CM_DSI0ECTL HW_REGISTER_RW( 0x7e101058 ) + #define CM_DSI0ECTL_MASK 0x000000bf + #define CM_DSI0ECTL_WIDTH 8 + #define CM_DSI0ECTL_RESET 0000000000 + #define CM_DSI0ECTL_BUSY_BITS 7:7 + #define CM_DSI0ECTL_BUSY_SET 0x00000080 + #define CM_DSI0ECTL_BUSY_CLR 0xffffff7f + #define CM_DSI0ECTL_BUSY_MSB 7 + #define CM_DSI0ECTL_BUSY_LSB 7 + #define CM_DSI0ECTL_KILL_BITS 5:5 + #define CM_DSI0ECTL_KILL_SET 0x00000020 + #define CM_DSI0ECTL_KILL_CLR 0xffffffdf + #define CM_DSI0ECTL_KILL_MSB 5 + #define CM_DSI0ECTL_KILL_LSB 5 + #define CM_DSI0ECTL_ENAB_BITS 4:4 + #define CM_DSI0ECTL_ENAB_SET 0x00000010 + #define CM_DSI0ECTL_ENAB_CLR 0xffffffef + #define CM_DSI0ECTL_ENAB_MSB 4 + #define CM_DSI0ECTL_ENAB_LSB 4 + #define CM_DSI0ECTL_SRC_BITS 3:0 + #define CM_DSI0ECTL_SRC_SET 0x0000000f + #define CM_DSI0ECTL_SRC_CLR 0xfffffff0 + #define CM_DSI0ECTL_SRC_MSB 3 + #define CM_DSI0ECTL_SRC_LSB 0 +#define CM_DSI0EDIV HW_REGISTER_RW( 0x7e10105c ) + #define CM_DSI0EDIV_MASK 0x0000fff0 + #define CM_DSI0EDIV_WIDTH 16 + #define CM_DSI0EDIV_RESET 0000000000 + #define CM_DSI0EDIV_DIV_BITS 15:4 + #define CM_DSI0EDIV_DIV_SET 0x0000fff0 + #define CM_DSI0EDIV_DIV_CLR 0xffff000f + #define CM_DSI0EDIV_DIV_MSB 15 + #define CM_DSI0EDIV_DIV_LSB 4 +#define CM_DSI0PCTL HW_REGISTER_RW( 0x7e101060 ) + #define CM_DSI0PCTL_MASK 0x0000001f + #define CM_DSI0PCTL_WIDTH 5 + #define CM_DSI0PCTL_RESET 0000000000 + #define CM_DSI0PCTL_ENAB_BITS 4:4 + #define CM_DSI0PCTL_ENAB_SET 0x00000010 + #define CM_DSI0PCTL_ENAB_CLR 0xffffffef + #define CM_DSI0PCTL_ENAB_MSB 4 + #define CM_DSI0PCTL_ENAB_LSB 4 + #define CM_DSI0PCTL_SRC_BITS 3:0 + #define CM_DSI0PCTL_SRC_SET 0x0000000f + #define CM_DSI0PCTL_SRC_CLR 0xfffffff0 + #define CM_DSI0PCTL_SRC_MSB 3 + #define CM_DSI0PCTL_SRC_LSB 0 +#define CM_DSI1ECTL HW_REGISTER_RW( 0x7e101158 ) + #define CM_DSI1ECTL_MASK 0x000000bf + #define CM_DSI1ECTL_WIDTH 8 + #define CM_DSI1ECTL_RESET 0000000000 + #define CM_DSI1ECTL_BUSY_BITS 7:7 + #define CM_DSI1ECTL_BUSY_SET 0x00000080 + #define CM_DSI1ECTL_BUSY_CLR 0xffffff7f + #define CM_DSI1ECTL_BUSY_MSB 7 + #define CM_DSI1ECTL_BUSY_LSB 7 + #define CM_DSI1ECTL_KILL_BITS 5:5 + #define CM_DSI1ECTL_KILL_SET 0x00000020 + #define CM_DSI1ECTL_KILL_CLR 0xffffffdf + #define CM_DSI1ECTL_KILL_MSB 5 + #define CM_DSI1ECTL_KILL_LSB 5 + #define CM_DSI1ECTL_ENAB_BITS 4:4 + #define CM_DSI1ECTL_ENAB_SET 0x00000010 + #define CM_DSI1ECTL_ENAB_CLR 0xffffffef + #define CM_DSI1ECTL_ENAB_MSB 4 + #define CM_DSI1ECTL_ENAB_LSB 4 + #define CM_DSI1ECTL_SRC_BITS 3:0 + #define CM_DSI1ECTL_SRC_SET 0x0000000f + #define CM_DSI1ECTL_SRC_CLR 0xfffffff0 + #define CM_DSI1ECTL_SRC_MSB 3 + #define CM_DSI1ECTL_SRC_LSB 0 +#define CM_DSI1EDIV HW_REGISTER_RW( 0x7e10115c ) + #define CM_DSI1EDIV_MASK 0x0000fff0 + #define CM_DSI1EDIV_WIDTH 16 + #define CM_DSI1EDIV_RESET 0000000000 + #define CM_DSI1EDIV_DIV_BITS 15:4 + #define CM_DSI1EDIV_DIV_SET 0x0000fff0 + #define CM_DSI1EDIV_DIV_CLR 0xffff000f + #define CM_DSI1EDIV_DIV_MSB 15 + #define CM_DSI1EDIV_DIV_LSB 4 +#define CM_DSI1PCTL HW_REGISTER_RW( 0x7e101160 ) + #define CM_DSI1PCTL_MASK 0x0000001f + #define CM_DSI1PCTL_WIDTH 5 + #define CM_DSI1PCTL_RESET 0000000000 + #define CM_DSI1PCTL_ENAB_BITS 4:4 + #define CM_DSI1PCTL_ENAB_SET 0x00000010 + #define CM_DSI1PCTL_ENAB_CLR 0xffffffef + #define CM_DSI1PCTL_ENAB_MSB 4 + #define CM_DSI1PCTL_ENAB_LSB 4 + #define CM_DSI1PCTL_SRC_BITS 3:0 + #define CM_DSI1PCTL_SRC_SET 0x0000000f + #define CM_DSI1PCTL_SRC_CLR 0xfffffff0 + #define CM_DSI1PCTL_SRC_MSB 3 + #define CM_DSI1PCTL_SRC_LSB 0 +#define CM_DPICTL HW_REGISTER_RW( 0x7e101068 ) + #define CM_DPICTL_MASK 0x000000bf + #define CM_DPICTL_WIDTH 8 + #define CM_DPICTL_RESET 0000000000 + #define CM_DPICTL_BUSY_BITS 7:7 + #define CM_DPICTL_BUSY_SET 0x00000080 + #define CM_DPICTL_BUSY_CLR 0xffffff7f + #define CM_DPICTL_BUSY_MSB 7 + #define CM_DPICTL_BUSY_LSB 7 + #define CM_DPICTL_KILL_BITS 5:5 + #define CM_DPICTL_KILL_SET 0x00000020 + #define CM_DPICTL_KILL_CLR 0xffffffdf + #define CM_DPICTL_KILL_MSB 5 + #define CM_DPICTL_KILL_LSB 5 + #define CM_DPICTL_ENAB_BITS 4:4 + #define CM_DPICTL_ENAB_SET 0x00000010 + #define CM_DPICTL_ENAB_CLR 0xffffffef + #define CM_DPICTL_ENAB_MSB 4 + #define CM_DPICTL_ENAB_LSB 4 + #define CM_DPICTL_SRC_BITS 3:0 + #define CM_DPICTL_SRC_SET 0x0000000f + #define CM_DPICTL_SRC_CLR 0xfffffff0 + #define CM_DPICTL_SRC_MSB 3 + #define CM_DPICTL_SRC_LSB 0 +#define CM_DPIDIV HW_REGISTER_RW( 0x7e10106c ) + #define CM_DPIDIV_MASK 0x0000fff0 + #define CM_DPIDIV_WIDTH 16 + #define CM_DPIDIV_RESET 0000000000 + #define CM_DPIDIV_DIV_BITS 15:4 + #define CM_DPIDIV_DIV_SET 0x0000fff0 + #define CM_DPIDIV_DIV_CLR 0xffff000f + #define CM_DPIDIV_DIV_MSB 15 + #define CM_DPIDIV_DIV_LSB 4 +#define CM_DFTCTL HW_REGISTER_RW( 0x7e101168 ) + #define CM_DFTCTL_MASK 0x000000bf + #define CM_DFTCTL_WIDTH 8 + #define CM_DFTCTL_RESET 0000000000 + #define CM_DFTCTL_BUSY_BITS 7:7 + #define CM_DFTCTL_BUSY_SET 0x00000080 + #define CM_DFTCTL_BUSY_CLR 0xffffff7f + #define CM_DFTCTL_BUSY_MSB 7 + #define CM_DFTCTL_BUSY_LSB 7 + #define CM_DFTCTL_KILL_BITS 5:5 + #define CM_DFTCTL_KILL_SET 0x00000020 + #define CM_DFTCTL_KILL_CLR 0xffffffdf + #define CM_DFTCTL_KILL_MSB 5 + #define CM_DFTCTL_KILL_LSB 5 + #define CM_DFTCTL_ENAB_BITS 4:4 + #define CM_DFTCTL_ENAB_SET 0x00000010 + #define CM_DFTCTL_ENAB_CLR 0xffffffef + #define CM_DFTCTL_ENAB_MSB 4 + #define CM_DFTCTL_ENAB_LSB 4 + #define CM_DFTCTL_SRC_BITS 3:0 + #define CM_DFTCTL_SRC_SET 0x0000000f + #define CM_DFTCTL_SRC_CLR 0xfffffff0 + #define CM_DFTCTL_SRC_MSB 3 + #define CM_DFTCTL_SRC_LSB 0 +#define CM_DFTDIV HW_REGISTER_RW( 0x7e10116c ) + #define CM_DFTDIV_MASK 0x0001f000 + #define CM_DFTDIV_WIDTH 17 + #define CM_DFTDIV_RESET 0000000000 + #define CM_DFTDIV_DIV_BITS 16:12 + #define CM_DFTDIV_DIV_SET 0x0001f000 + #define CM_DFTDIV_DIV_CLR 0xfffe0fff + #define CM_DFTDIV_DIV_MSB 16 + #define CM_DFTDIV_DIV_LSB 12 +#define CM_GP0CTL HW_REGISTER_RW( 0x7e101070 ) + #define CM_GP0CTL_MASK 0x000006bf + #define CM_GP0CTL_WIDTH 11 + #define CM_GP0CTL_RESET 0x00000200 + #define CM_GP0CTL_MASH_BITS 10:9 + #define CM_GP0CTL_MASH_SET 0x00000600 + #define CM_GP0CTL_MASH_CLR 0xfffff9ff + #define CM_GP0CTL_MASH_MSB 10 + #define CM_GP0CTL_MASH_LSB 9 + #define CM_GP0CTL_BUSY_BITS 7:7 + #define CM_GP0CTL_BUSY_SET 0x00000080 + #define CM_GP0CTL_BUSY_CLR 0xffffff7f + #define CM_GP0CTL_BUSY_MSB 7 + #define CM_GP0CTL_BUSY_LSB 7 + #define CM_GP0CTL_KILL_BITS 5:5 + #define CM_GP0CTL_KILL_SET 0x00000020 + #define CM_GP0CTL_KILL_CLR 0xffffffdf + #define CM_GP0CTL_KILL_MSB 5 + #define CM_GP0CTL_KILL_LSB 5 + #define CM_GP0CTL_ENAB_BITS 4:4 + #define CM_GP0CTL_ENAB_SET 0x00000010 + #define CM_GP0CTL_ENAB_CLR 0xffffffef + #define CM_GP0CTL_ENAB_MSB 4 + #define CM_GP0CTL_ENAB_LSB 4 + #define CM_GP0CTL_SRC_BITS 3:0 + #define CM_GP0CTL_SRC_SET 0x0000000f + #define CM_GP0CTL_SRC_CLR 0xfffffff0 + #define CM_GP0CTL_SRC_MSB 3 + #define CM_GP0CTL_SRC_LSB 0 +#define CM_GP0DIV HW_REGISTER_RW( 0x7e101074 ) + #define CM_GP0DIV_MASK 0x00ffffff + #define CM_GP0DIV_WIDTH 24 + #define CM_GP0DIV_RESET 0000000000 + #define CM_GP0DIV_DIV_BITS 23:0 + #define CM_GP0DIV_DIV_SET 0x00ffffff + #define CM_GP0DIV_DIV_CLR 0xff000000 + #define CM_GP0DIV_DIV_MSB 23 + #define CM_GP0DIV_DIV_LSB 0 +#define CM_GP1CTL HW_REGISTER_RW( 0x7e101078 ) + #define CM_GP1CTL_MASK 0x000006bf + #define CM_GP1CTL_WIDTH 11 + #define CM_GP1CTL_RESET 0x00000200 + #define CM_GP1CTL_MASH_BITS 10:9 + #define CM_GP1CTL_MASH_SET 0x00000600 + #define CM_GP1CTL_MASH_CLR 0xfffff9ff + #define CM_GP1CTL_MASH_MSB 10 + #define CM_GP1CTL_MASH_LSB 9 + #define CM_GP1CTL_BUSY_BITS 7:7 + #define CM_GP1CTL_BUSY_SET 0x00000080 + #define CM_GP1CTL_BUSY_CLR 0xffffff7f + #define CM_GP1CTL_BUSY_MSB 7 + #define CM_GP1CTL_BUSY_LSB 7 + #define CM_GP1CTL_KILL_BITS 5:5 + #define CM_GP1CTL_KILL_SET 0x00000020 + #define CM_GP1CTL_KILL_CLR 0xffffffdf + #define CM_GP1CTL_KILL_MSB 5 + #define CM_GP1CTL_KILL_LSB 5 + #define CM_GP1CTL_ENAB_BITS 4:4 + #define CM_GP1CTL_ENAB_SET 0x00000010 + #define CM_GP1CTL_ENAB_CLR 0xffffffef + #define CM_GP1CTL_ENAB_MSB 4 + #define CM_GP1CTL_ENAB_LSB 4 + #define CM_GP1CTL_SRC_BITS 3:0 + #define CM_GP1CTL_SRC_SET 0x0000000f + #define CM_GP1CTL_SRC_CLR 0xfffffff0 + #define CM_GP1CTL_SRC_MSB 3 + #define CM_GP1CTL_SRC_LSB 0 +#define CM_GP1DIV HW_REGISTER_RW( 0x7e10107c ) + #define CM_GP1DIV_MASK 0x00ffffff + #define CM_GP1DIV_WIDTH 24 + #define CM_GP1DIV_RESET 0000000000 + #define CM_GP1DIV_DIV_BITS 23:0 + #define CM_GP1DIV_DIV_SET 0x00ffffff + #define CM_GP1DIV_DIV_CLR 0xff000000 + #define CM_GP1DIV_DIV_MSB 23 + #define CM_GP1DIV_DIV_LSB 0 +#define CM_GP2CTL HW_REGISTER_RW( 0x7e101080 ) + #define CM_GP2CTL_MASK 0x000000bf + #define CM_GP2CTL_WIDTH 8 + #define CM_GP2CTL_RESET 0000000000 + #define CM_GP2CTL_BUSY_BITS 7:7 + #define CM_GP2CTL_BUSY_SET 0x00000080 + #define CM_GP2CTL_BUSY_CLR 0xffffff7f + #define CM_GP2CTL_BUSY_MSB 7 + #define CM_GP2CTL_BUSY_LSB 7 + #define CM_GP2CTL_KILL_BITS 5:5 + #define CM_GP2CTL_KILL_SET 0x00000020 + #define CM_GP2CTL_KILL_CLR 0xffffffdf + #define CM_GP2CTL_KILL_MSB 5 + #define CM_GP2CTL_KILL_LSB 5 + #define CM_GP2CTL_ENAB_BITS 4:4 + #define CM_GP2CTL_ENAB_SET 0x00000010 + #define CM_GP2CTL_ENAB_CLR 0xffffffef + #define CM_GP2CTL_ENAB_MSB 4 + #define CM_GP2CTL_ENAB_LSB 4 + #define CM_GP2CTL_SRC_BITS 3:0 + #define CM_GP2CTL_SRC_SET 0x0000000f + #define CM_GP2CTL_SRC_CLR 0xfffffff0 + #define CM_GP2CTL_SRC_MSB 3 + #define CM_GP2CTL_SRC_LSB 0 +#define CM_GP2DIV HW_REGISTER_RW( 0x7e101084 ) + #define CM_GP2DIV_MASK 0x00ffffff + #define CM_GP2DIV_WIDTH 24 + #define CM_GP2DIV_RESET 0000000000 + #define CM_GP2DIV_DIV_BITS 23:0 + #define CM_GP2DIV_DIV_SET 0x00ffffff + #define CM_GP2DIV_DIV_CLR 0xff000000 + #define CM_GP2DIV_DIV_MSB 23 + #define CM_GP2DIV_DIV_LSB 0 +#define CM_HSMCTL HW_REGISTER_RW( 0x7e101088 ) + #define CM_HSMCTL_MASK 0x000000ff + #define CM_HSMCTL_WIDTH 8 + #define CM_HSMCTL_RESET 0000000000 + #define CM_HSMCTL_BUSY_BITS 7:7 + #define CM_HSMCTL_BUSY_SET 0x00000080 + #define CM_HSMCTL_BUSY_CLR 0xffffff7f + #define CM_HSMCTL_BUSY_MSB 7 + #define CM_HSMCTL_BUSY_LSB 7 + #define CM_HSMCTL_GATE_BITS 6:6 + #define CM_HSMCTL_GATE_SET 0x00000040 + #define CM_HSMCTL_GATE_CLR 0xffffffbf + #define CM_HSMCTL_GATE_MSB 6 + #define CM_HSMCTL_GATE_LSB 6 + #define CM_HSMCTL_KILL_BITS 5:5 + #define CM_HSMCTL_KILL_SET 0x00000020 + #define CM_HSMCTL_KILL_CLR 0xffffffdf + #define CM_HSMCTL_KILL_MSB 5 + #define CM_HSMCTL_KILL_LSB 5 + #define CM_HSMCTL_ENAB_BITS 4:4 + #define CM_HSMCTL_ENAB_SET 0x00000010 + #define CM_HSMCTL_ENAB_CLR 0xffffffef + #define CM_HSMCTL_ENAB_MSB 4 + #define CM_HSMCTL_ENAB_LSB 4 + #define CM_HSMCTL_SRC_BITS 3:0 + #define CM_HSMCTL_SRC_SET 0x0000000f + #define CM_HSMCTL_SRC_CLR 0xfffffff0 + #define CM_HSMCTL_SRC_MSB 3 + #define CM_HSMCTL_SRC_LSB 0 +#define CM_HSMDIV HW_REGISTER_RW( 0x7e10108c ) + #define CM_HSMDIV_MASK 0x0000fff0 + #define CM_HSMDIV_WIDTH 16 + #define CM_HSMDIV_RESET 0000000000 + #define CM_HSMDIV_DIV_BITS 15:4 + #define CM_HSMDIV_DIV_SET 0x0000fff0 + #define CM_HSMDIV_DIV_CLR 0xffff000f + #define CM_HSMDIV_DIV_MSB 15 + #define CM_HSMDIV_DIV_LSB 4 +#define CM_OTPCTL HW_REGISTER_RW( 0x7e101090 ) + #define CM_OTPCTL_MASK 0x000000b3 + #define CM_OTPCTL_WIDTH 8 + #define CM_OTPCTL_RESET 0x00000011 + #define CM_OTPCTL_BUSY_BITS 7:7 + #define CM_OTPCTL_BUSY_SET 0x00000080 + #define CM_OTPCTL_BUSY_CLR 0xffffff7f + #define CM_OTPCTL_BUSY_MSB 7 + #define CM_OTPCTL_BUSY_LSB 7 + #define CM_OTPCTL_KILL_BITS 5:5 + #define CM_OTPCTL_KILL_SET 0x00000020 + #define CM_OTPCTL_KILL_CLR 0xffffffdf + #define CM_OTPCTL_KILL_MSB 5 + #define CM_OTPCTL_KILL_LSB 5 + #define CM_OTPCTL_ENAB_BITS 4:4 + #define CM_OTPCTL_ENAB_SET 0x00000010 + #define CM_OTPCTL_ENAB_CLR 0xffffffef + #define CM_OTPCTL_ENAB_MSB 4 + #define CM_OTPCTL_ENAB_LSB 4 + #define CM_OTPCTL_SRC_BITS 1:0 + #define CM_OTPCTL_SRC_SET 0x00000003 + #define CM_OTPCTL_SRC_CLR 0xfffffffc + #define CM_OTPCTL_SRC_MSB 1 + #define CM_OTPCTL_SRC_LSB 0 +#define CM_OTPDIV HW_REGISTER_RW( 0x7e101094 ) + #define CM_OTPDIV_MASK 0x0001f000 + #define CM_OTPDIV_WIDTH 17 + #define CM_OTPDIV_RESET 0x00004000 + #define CM_OTPDIV_DIV_BITS 16:12 + #define CM_OTPDIV_DIV_SET 0x0001f000 + #define CM_OTPDIV_DIV_CLR 0xfffe0fff + #define CM_OTPDIV_DIV_MSB 16 + #define CM_OTPDIV_DIV_LSB 12 +#define CM_PULSECTL HW_REGISTER_RW( 0x7e101190 ) + #define CM_PULSECTL_MASK 0x000000b3 + #define CM_PULSECTL_WIDTH 8 + #define CM_PULSECTL_RESET 0x00000011 + #define CM_PULSECTL_BUSY_BITS 7:7 + #define CM_PULSECTL_BUSY_SET 0x00000080 + #define CM_PULSECTL_BUSY_CLR 0xffffff7f + #define CM_PULSECTL_BUSY_MSB 7 + #define CM_PULSECTL_BUSY_LSB 7 + #define CM_PULSECTL_KILL_BITS 5:5 + #define CM_PULSECTL_KILL_SET 0x00000020 + #define CM_PULSECTL_KILL_CLR 0xffffffdf + #define CM_PULSECTL_KILL_MSB 5 + #define CM_PULSECTL_KILL_LSB 5 + #define CM_PULSECTL_ENAB_BITS 4:4 + #define CM_PULSECTL_ENAB_SET 0x00000010 + #define CM_PULSECTL_ENAB_CLR 0xffffffef + #define CM_PULSECTL_ENAB_MSB 4 + #define CM_PULSECTL_ENAB_LSB 4 + #define CM_PULSECTL_SRC_BITS 1:0 + #define CM_PULSECTL_SRC_SET 0x00000003 + #define CM_PULSECTL_SRC_CLR 0xfffffffc + #define CM_PULSECTL_SRC_MSB 1 + #define CM_PULSECTL_SRC_LSB 0 +#define CM_PULSEDIV HW_REGISTER_RW( 0x7e101194 ) + #define CM_PULSEDIV_MASK 0x00fff000 + #define CM_PULSEDIV_WIDTH 24 + #define CM_PULSEDIV_RESET 0x00014000 + #define CM_PULSEDIV_DIV_BITS 23:12 + #define CM_PULSEDIV_DIV_SET 0x00fff000 + #define CM_PULSEDIV_DIV_CLR 0xff000fff + #define CM_PULSEDIV_DIV_MSB 23 + #define CM_PULSEDIV_DIV_LSB 12 +#define CM_PCMCTL HW_REGISTER_RW( 0x7e101098 ) + #define CM_PCMCTL_MASK 0x000006bf + #define CM_PCMCTL_WIDTH 11 + #define CM_PCMCTL_RESET 0x00000200 + #define CM_PCMCTL_MASH_BITS 10:9 + #define CM_PCMCTL_MASH_SET 0x00000600 + #define CM_PCMCTL_MASH_CLR 0xfffff9ff + #define CM_PCMCTL_MASH_MSB 10 + #define CM_PCMCTL_MASH_LSB 9 + #define CM_PCMCTL_BUSY_BITS 7:7 + #define CM_PCMCTL_BUSY_SET 0x00000080 + #define CM_PCMCTL_BUSY_CLR 0xffffff7f + #define CM_PCMCTL_BUSY_MSB 7 + #define CM_PCMCTL_BUSY_LSB 7 + #define CM_PCMCTL_KILL_BITS 5:5 + #define CM_PCMCTL_KILL_SET 0x00000020 + #define CM_PCMCTL_KILL_CLR 0xffffffdf + #define CM_PCMCTL_KILL_MSB 5 + #define CM_PCMCTL_KILL_LSB 5 + #define CM_PCMCTL_ENAB_BITS 4:4 + #define CM_PCMCTL_ENAB_SET 0x00000010 + #define CM_PCMCTL_ENAB_CLR 0xffffffef + #define CM_PCMCTL_ENAB_MSB 4 + #define CM_PCMCTL_ENAB_LSB 4 + #define CM_PCMCTL_SRC_BITS 3:0 + #define CM_PCMCTL_SRC_SET 0x0000000f + #define CM_PCMCTL_SRC_CLR 0xfffffff0 + #define CM_PCMCTL_SRC_MSB 3 + #define CM_PCMCTL_SRC_LSB 0 +#define CM_PCMDIV HW_REGISTER_RW( 0x7e10109c ) + #define CM_PCMDIV_MASK 0x00ffffff + #define CM_PCMDIV_WIDTH 24 + #define CM_PCMDIV_RESET 0000000000 + #define CM_PCMDIV_DIV_BITS 23:0 + #define CM_PCMDIV_DIV_SET 0x00ffffff + #define CM_PCMDIV_DIV_CLR 0xff000000 + #define CM_PCMDIV_DIV_MSB 23 + #define CM_PCMDIV_DIV_LSB 0 +#define CM_PWMCTL HW_REGISTER_RW( 0x7e1010a0 ) + #define CM_PWMCTL_MASK 0x000006bf + #define CM_PWMCTL_WIDTH 11 + #define CM_PWMCTL_RESET 0x00000200 + #define CM_PWMCTL_MASH_BITS 10:9 + #define CM_PWMCTL_MASH_SET 0x00000600 + #define CM_PWMCTL_MASH_CLR 0xfffff9ff + #define CM_PWMCTL_MASH_MSB 10 + #define CM_PWMCTL_MASH_LSB 9 + #define CM_PWMCTL_BUSY_BITS 7:7 + #define CM_PWMCTL_BUSY_SET 0x00000080 + #define CM_PWMCTL_BUSY_CLR 0xffffff7f + #define CM_PWMCTL_BUSY_MSB 7 + #define CM_PWMCTL_BUSY_LSB 7 + #define CM_PWMCTL_KILL_BITS 5:5 + #define CM_PWMCTL_KILL_SET 0x00000020 + #define CM_PWMCTL_KILL_CLR 0xffffffdf + #define CM_PWMCTL_KILL_MSB 5 + #define CM_PWMCTL_KILL_LSB 5 + #define CM_PWMCTL_ENAB_BITS 4:4 + #define CM_PWMCTL_ENAB_SET 0x00000010 + #define CM_PWMCTL_ENAB_CLR 0xffffffef + #define CM_PWMCTL_ENAB_MSB 4 + #define CM_PWMCTL_ENAB_LSB 4 + #define CM_PWMCTL_SRC_BITS 3:0 + #define CM_PWMCTL_SRC_SET 0x0000000f + #define CM_PWMCTL_SRC_CLR 0xfffffff0 + #define CM_PWMCTL_SRC_MSB 3 + #define CM_PWMCTL_SRC_LSB 0 +#define CM_PWMDIV HW_REGISTER_RW( 0x7e1010a4 ) + #define CM_PWMDIV_MASK 0x00ffffff + #define CM_PWMDIV_WIDTH 24 + #define CM_PWMDIV_RESET 0000000000 + #define CM_PWMDIV_DIV_BITS 23:0 + #define CM_PWMDIV_DIV_SET 0x00ffffff + #define CM_PWMDIV_DIV_CLR 0xff000000 + #define CM_PWMDIV_DIV_MSB 23 + #define CM_PWMDIV_DIV_LSB 0 +#define CM_SLIMCTL HW_REGISTER_RW( 0x7e1010a8 ) + #define CM_SLIMCTL_MASK 0x000006bf + #define CM_SLIMCTL_WIDTH 11 + #define CM_SLIMCTL_RESET 0x00000200 + #define CM_SLIMCTL_MASH_BITS 10:9 + #define CM_SLIMCTL_MASH_SET 0x00000600 + #define CM_SLIMCTL_MASH_CLR 0xfffff9ff + #define CM_SLIMCTL_MASH_MSB 10 + #define CM_SLIMCTL_MASH_LSB 9 + #define CM_SLIMCTL_BUSY_BITS 7:7 + #define CM_SLIMCTL_BUSY_SET 0x00000080 + #define CM_SLIMCTL_BUSY_CLR 0xffffff7f + #define CM_SLIMCTL_BUSY_MSB 7 + #define CM_SLIMCTL_BUSY_LSB 7 + #define CM_SLIMCTL_KILL_BITS 5:5 + #define CM_SLIMCTL_KILL_SET 0x00000020 + #define CM_SLIMCTL_KILL_CLR 0xffffffdf + #define CM_SLIMCTL_KILL_MSB 5 + #define CM_SLIMCTL_KILL_LSB 5 + #define CM_SLIMCTL_ENAB_BITS 4:4 + #define CM_SLIMCTL_ENAB_SET 0x00000010 + #define CM_SLIMCTL_ENAB_CLR 0xffffffef + #define CM_SLIMCTL_ENAB_MSB 4 + #define CM_SLIMCTL_ENAB_LSB 4 + #define CM_SLIMCTL_SRC_BITS 3:0 + #define CM_SLIMCTL_SRC_SET 0x0000000f + #define CM_SLIMCTL_SRC_CLR 0xfffffff0 + #define CM_SLIMCTL_SRC_MSB 3 + #define CM_SLIMCTL_SRC_LSB 0 +#define CM_SLIMDIV HW_REGISTER_RW( 0x7e1010ac ) + #define CM_SLIMDIV_MASK 0x00ffffff + #define CM_SLIMDIV_WIDTH 24 + #define CM_SLIMDIV_RESET 0000000000 + #define CM_SLIMDIV_DIV_BITS 23:0 + #define CM_SLIMDIV_DIV_SET 0x00ffffff + #define CM_SLIMDIV_DIV_CLR 0xff000000 + #define CM_SLIMDIV_DIV_MSB 23 + #define CM_SLIMDIV_DIV_LSB 0 +#define CM_SMICTL HW_REGISTER_RW( 0x7e1010b0 ) + #define CM_SMICTL_MASK 0x000000bf + #define CM_SMICTL_WIDTH 8 + #define CM_SMICTL_RESET 0000000000 + #define CM_SMICTL_BUSY_BITS 7:7 + #define CM_SMICTL_BUSY_SET 0x00000080 + #define CM_SMICTL_BUSY_CLR 0xffffff7f + #define CM_SMICTL_BUSY_MSB 7 + #define CM_SMICTL_BUSY_LSB 7 + #define CM_SMICTL_KILL_BITS 5:5 + #define CM_SMICTL_KILL_SET 0x00000020 + #define CM_SMICTL_KILL_CLR 0xffffffdf + #define CM_SMICTL_KILL_MSB 5 + #define CM_SMICTL_KILL_LSB 5 + #define CM_SMICTL_ENAB_BITS 4:4 + #define CM_SMICTL_ENAB_SET 0x00000010 + #define CM_SMICTL_ENAB_CLR 0xffffffef + #define CM_SMICTL_ENAB_MSB 4 + #define CM_SMICTL_ENAB_LSB 4 + #define CM_SMICTL_SRC_BITS 3:0 + #define CM_SMICTL_SRC_SET 0x0000000f + #define CM_SMICTL_SRC_CLR 0xfffffff0 + #define CM_SMICTL_SRC_MSB 3 + #define CM_SMICTL_SRC_LSB 0 +#define CM_SMIDIV HW_REGISTER_RW( 0x7e1010b4 ) + #define CM_SMIDIV_MASK 0x0000fff0 + #define CM_SMIDIV_WIDTH 16 + #define CM_SMIDIV_RESET 0000000000 + #define CM_SMIDIV_DIV_BITS 15:4 + #define CM_SMIDIV_DIV_SET 0x0000fff0 + #define CM_SMIDIV_DIV_CLR 0xffff000f + #define CM_SMIDIV_DIV_MSB 15 + #define CM_SMIDIV_DIV_LSB 4 +#define CM_SMPSCTL HW_REGISTER_RW( 0x7e1010b8 ) + #define CM_SMPSCTL_MASK 0x000000f3 + #define CM_SMPSCTL_WIDTH 8 + #define CM_SMPSCTL_RESET 0000000000 + #define CM_SMPSCTL_BUSY_BITS 7:7 + #define CM_SMPSCTL_BUSY_SET 0x00000080 + #define CM_SMPSCTL_BUSY_CLR 0xffffff7f + #define CM_SMPSCTL_BUSY_MSB 7 + #define CM_SMPSCTL_BUSY_LSB 7 + #define CM_SMPSCTL_GATE_BITS 6:6 + #define CM_SMPSCTL_GATE_SET 0x00000040 + #define CM_SMPSCTL_GATE_CLR 0xffffffbf + #define CM_SMPSCTL_GATE_MSB 6 + #define CM_SMPSCTL_GATE_LSB 6 + #define CM_SMPSCTL_KILL_BITS 5:5 + #define CM_SMPSCTL_KILL_SET 0x00000020 + #define CM_SMPSCTL_KILL_CLR 0xffffffdf + #define CM_SMPSCTL_KILL_MSB 5 + #define CM_SMPSCTL_KILL_LSB 5 + #define CM_SMPSCTL_ENAB_BITS 4:4 + #define CM_SMPSCTL_ENAB_SET 0x00000010 + #define CM_SMPSCTL_ENAB_CLR 0xffffffef + #define CM_SMPSCTL_ENAB_MSB 4 + #define CM_SMPSCTL_ENAB_LSB 4 + #define CM_SMPSCTL_SRC_BITS 1:0 + #define CM_SMPSCTL_SRC_SET 0x00000003 + #define CM_SMPSCTL_SRC_CLR 0xfffffffc + #define CM_SMPSCTL_SRC_MSB 1 + #define CM_SMPSCTL_SRC_LSB 0 +#define CM_SMPSDIV HW_REGISTER_RW( 0x7e1010bc ) + #define CM_SMPSDIV_MASK 0x00007000 + #define CM_SMPSDIV_WIDTH 15 + #define CM_SMPSDIV_RESET 0000000000 + #define CM_SMPSDIV_DIV_BITS 14:12 + #define CM_SMPSDIV_DIV_SET 0x00007000 + #define CM_SMPSDIV_DIV_CLR 0xffff8fff + #define CM_SMPSDIV_DIV_MSB 14 + #define CM_SMPSDIV_DIV_LSB 12 +#define CM_TCNTCTL HW_REGISTER_RW( 0x7e1010c0 ) + #define CM_TCNTCTL_MASK 0x0000f0ff + #define CM_TCNTCTL_WIDTH 16 + #define CM_TCNTCTL_RESET 0000000000 + #define CM_TCNTCTL_SRC1_BITS 15:12 + #define CM_TCNTCTL_SRC1_SET 0x0000f000 + #define CM_TCNTCTL_SRC1_CLR 0xffff0fff + #define CM_TCNTCTL_SRC1_MSB 15 + #define CM_TCNTCTL_SRC1_LSB 12 + #define CM_TCNTCTL_BUSY_BITS 7:7 + #define CM_TCNTCTL_BUSY_SET 0x00000080 + #define CM_TCNTCTL_BUSY_CLR 0xffffff7f + #define CM_TCNTCTL_BUSY_MSB 7 + #define CM_TCNTCTL_BUSY_LSB 7 + #define CM_TCNTCTL_KILL_BITS 6:6 + #define CM_TCNTCTL_KILL_SET 0x00000040 + #define CM_TCNTCTL_KILL_CLR 0xffffffbf + #define CM_TCNTCTL_KILL_MSB 6 + #define CM_TCNTCTL_KILL_LSB 6 + #define CM_TCNTCTL_SRC0_BITS 5:0 + #define CM_TCNTCTL_SRC0_SET 0x0000003f + #define CM_TCNTCTL_SRC0_CLR 0xffffffc0 + #define CM_TCNTCTL_SRC0_MSB 5 + #define CM_TCNTCTL_SRC0_LSB 0 +#define CM_TCNTCNT HW_REGISTER_RW( 0x7e1010c4 ) + #define CM_TCNTCNT_MASK 0x0003ffff + #define CM_TCNTCNT_WIDTH 18 + #define CM_TCNTCNT_RESET 0000000000 + #define CM_TCNTCNT_CNT_BITS 17:0 + #define CM_TCNTCNT_CNT_SET 0x0003ffff + #define CM_TCNTCNT_CNT_CLR 0xfffc0000 + #define CM_TCNTCNT_CNT_MSB 17 + #define CM_TCNTCNT_CNT_LSB 0 +#define CM_TECCTL HW_REGISTER_RW( 0x7e1010c8 ) + #define CM_TECCTL_MASK 0x000000b3 + #define CM_TECCTL_WIDTH 8 + #define CM_TECCTL_RESET 0000000000 + #define CM_TECCTL_BUSY_BITS 7:7 + #define CM_TECCTL_BUSY_SET 0x00000080 + #define CM_TECCTL_BUSY_CLR 0xffffff7f + #define CM_TECCTL_BUSY_MSB 7 + #define CM_TECCTL_BUSY_LSB 7 + #define CM_TECCTL_KILL_BITS 5:5 + #define CM_TECCTL_KILL_SET 0x00000020 + #define CM_TECCTL_KILL_CLR 0xffffffdf + #define CM_TECCTL_KILL_MSB 5 + #define CM_TECCTL_KILL_LSB 5 + #define CM_TECCTL_ENAB_BITS 4:4 + #define CM_TECCTL_ENAB_SET 0x00000010 + #define CM_TECCTL_ENAB_CLR 0xffffffef + #define CM_TECCTL_ENAB_MSB 4 + #define CM_TECCTL_ENAB_LSB 4 + #define CM_TECCTL_SRC_BITS 1:0 + #define CM_TECCTL_SRC_SET 0x00000003 + #define CM_TECCTL_SRC_CLR 0xfffffffc + #define CM_TECCTL_SRC_MSB 1 + #define CM_TECCTL_SRC_LSB 0 +#define CM_TECDIV HW_REGISTER_RW( 0x7e1010cc ) + #define CM_TECDIV_MASK 0x0003f000 + #define CM_TECDIV_WIDTH 18 + #define CM_TECDIV_RESET 0000000000 + #define CM_TECDIV_DIV_BITS 17:12 + #define CM_TECDIV_DIV_SET 0x0003f000 + #define CM_TECDIV_DIV_CLR 0xfffc0fff + #define CM_TECDIV_DIV_MSB 17 + #define CM_TECDIV_DIV_LSB 12 +#define CM_TD0CTL HW_REGISTER_RW( 0x7e1010d0 ) + #define CM_TD0CTL_MASK 0x000011ff + #define CM_TD0CTL_WIDTH 13 + #define CM_TD0CTL_RESET 0000000000 + #define CM_TD0CTL_STEP_BITS 12:12 + #define CM_TD0CTL_STEP_SET 0x00001000 + #define CM_TD0CTL_STEP_CLR 0xffffefff + #define CM_TD0CTL_STEP_MSB 12 + #define CM_TD0CTL_STEP_LSB 12 + #define CM_TD0CTL_FLIP_BITS 8:8 + #define CM_TD0CTL_FLIP_SET 0x00000100 + #define CM_TD0CTL_FLIP_CLR 0xfffffeff + #define CM_TD0CTL_FLIP_MSB 8 + #define CM_TD0CTL_FLIP_LSB 8 + #define CM_TD0CTL_BUSY_BITS 7:7 + #define CM_TD0CTL_BUSY_SET 0x00000080 + #define CM_TD0CTL_BUSY_CLR 0xffffff7f + #define CM_TD0CTL_BUSY_MSB 7 + #define CM_TD0CTL_BUSY_LSB 7 + #define CM_TD0CTL_GATE_BITS 6:6 + #define CM_TD0CTL_GATE_SET 0x00000040 + #define CM_TD0CTL_GATE_CLR 0xffffffbf + #define CM_TD0CTL_GATE_MSB 6 + #define CM_TD0CTL_GATE_LSB 6 + #define CM_TD0CTL_KILL_BITS 5:5 + #define CM_TD0CTL_KILL_SET 0x00000020 + #define CM_TD0CTL_KILL_CLR 0xffffffdf + #define CM_TD0CTL_KILL_MSB 5 + #define CM_TD0CTL_KILL_LSB 5 + #define CM_TD0CTL_ENAB_BITS 4:4 + #define CM_TD0CTL_ENAB_SET 0x00000010 + #define CM_TD0CTL_ENAB_CLR 0xffffffef + #define CM_TD0CTL_ENAB_MSB 4 + #define CM_TD0CTL_ENAB_LSB 4 + #define CM_TD0CTL_SRC_BITS 3:0 + #define CM_TD0CTL_SRC_SET 0x0000000f + #define CM_TD0CTL_SRC_CLR 0xfffffff0 + #define CM_TD0CTL_SRC_MSB 3 + #define CM_TD0CTL_SRC_LSB 0 +#define CM_TD0DIV HW_REGISTER_RW( 0x7e1010d4 ) + #define CM_TD0DIV_MASK 0x00ffffff + #define CM_TD0DIV_WIDTH 24 + #define CM_TD0DIV_RESET 0000000000 + #define CM_TD0DIV_DIV_BITS 23:0 + #define CM_TD0DIV_DIV_SET 0x00ffffff + #define CM_TD0DIV_DIV_CLR 0xff000000 + #define CM_TD0DIV_DIV_MSB 23 + #define CM_TD0DIV_DIV_LSB 0 +#define CM_TD1CTL HW_REGISTER_RW( 0x7e1010d8 ) + #define CM_TD1CTL_MASK 0x000011ff + #define CM_TD1CTL_WIDTH 13 + #define CM_TD1CTL_RESET 0000000000 + #define CM_TD1CTL_STEP_BITS 12:12 + #define CM_TD1CTL_STEP_SET 0x00001000 + #define CM_TD1CTL_STEP_CLR 0xffffefff + #define CM_TD1CTL_STEP_MSB 12 + #define CM_TD1CTL_STEP_LSB 12 + #define CM_TD1CTL_FLIP_BITS 8:8 + #define CM_TD1CTL_FLIP_SET 0x00000100 + #define CM_TD1CTL_FLIP_CLR 0xfffffeff + #define CM_TD1CTL_FLIP_MSB 8 + #define CM_TD1CTL_FLIP_LSB 8 + #define CM_TD1CTL_BUSY_BITS 7:7 + #define CM_TD1CTL_BUSY_SET 0x00000080 + #define CM_TD1CTL_BUSY_CLR 0xffffff7f + #define CM_TD1CTL_BUSY_MSB 7 + #define CM_TD1CTL_BUSY_LSB 7 + #define CM_TD1CTL_GATE_BITS 6:6 + #define CM_TD1CTL_GATE_SET 0x00000040 + #define CM_TD1CTL_GATE_CLR 0xffffffbf + #define CM_TD1CTL_GATE_MSB 6 + #define CM_TD1CTL_GATE_LSB 6 + #define CM_TD1CTL_KILL_BITS 5:5 + #define CM_TD1CTL_KILL_SET 0x00000020 + #define CM_TD1CTL_KILL_CLR 0xffffffdf + #define CM_TD1CTL_KILL_MSB 5 + #define CM_TD1CTL_KILL_LSB 5 + #define CM_TD1CTL_ENAB_BITS 4:4 + #define CM_TD1CTL_ENAB_SET 0x00000010 + #define CM_TD1CTL_ENAB_CLR 0xffffffef + #define CM_TD1CTL_ENAB_MSB 4 + #define CM_TD1CTL_ENAB_LSB 4 + #define CM_TD1CTL_SRC_BITS 3:0 + #define CM_TD1CTL_SRC_SET 0x0000000f + #define CM_TD1CTL_SRC_CLR 0xfffffff0 + #define CM_TD1CTL_SRC_MSB 3 + #define CM_TD1CTL_SRC_LSB 0 +#define CM_TD1DIV HW_REGISTER_RW( 0x7e1010dc ) + #define CM_TD1DIV_MASK 0x00ffffff + #define CM_TD1DIV_WIDTH 24 + #define CM_TD1DIV_RESET 0000000000 + #define CM_TD1DIV_DIV_BITS 23:0 + #define CM_TD1DIV_DIV_SET 0x00ffffff + #define CM_TD1DIV_DIV_CLR 0xff000000 + #define CM_TD1DIV_DIV_MSB 23 + #define CM_TD1DIV_DIV_LSB 0 +#define CM_TSENSCTL HW_REGISTER_RW( 0x7e1010e0 ) + #define CM_TSENSCTL_MASK 0x000000b3 + #define CM_TSENSCTL_WIDTH 8 + #define CM_TSENSCTL_RESET 0000000000 + #define CM_TSENSCTL_BUSY_BITS 7:7 + #define CM_TSENSCTL_BUSY_SET 0x00000080 + #define CM_TSENSCTL_BUSY_CLR 0xffffff7f + #define CM_TSENSCTL_BUSY_MSB 7 + #define CM_TSENSCTL_BUSY_LSB 7 + #define CM_TSENSCTL_KILL_BITS 5:5 + #define CM_TSENSCTL_KILL_SET 0x00000020 + #define CM_TSENSCTL_KILL_CLR 0xffffffdf + #define CM_TSENSCTL_KILL_MSB 5 + #define CM_TSENSCTL_KILL_LSB 5 + #define CM_TSENSCTL_ENAB_BITS 4:4 + #define CM_TSENSCTL_ENAB_SET 0x00000010 + #define CM_TSENSCTL_ENAB_CLR 0xffffffef + #define CM_TSENSCTL_ENAB_MSB 4 + #define CM_TSENSCTL_ENAB_LSB 4 + #define CM_TSENSCTL_SRC_BITS 1:0 + #define CM_TSENSCTL_SRC_SET 0x00000003 + #define CM_TSENSCTL_SRC_CLR 0xfffffffc + #define CM_TSENSCTL_SRC_MSB 1 + #define CM_TSENSCTL_SRC_LSB 0 +#define CM_TSENSDIV HW_REGISTER_RW( 0x7e1010e4 ) + #define CM_TSENSDIV_MASK 0x0001f000 + #define CM_TSENSDIV_WIDTH 17 + #define CM_TSENSDIV_RESET 0000000000 + #define CM_TSENSDIV_DIV_BITS 16:12 + #define CM_TSENSDIV_DIV_SET 0x0001f000 + #define CM_TSENSDIV_DIV_CLR 0xfffe0fff + #define CM_TSENSDIV_DIV_MSB 16 + #define CM_TSENSDIV_DIV_LSB 12 +#define CM_TIMERCTL HW_REGISTER_RW( 0x7e1010e8 ) + #define CM_TIMERCTL_MASK 0x000000b3 + #define CM_TIMERCTL_WIDTH 8 + #define CM_TIMERCTL_RESET 0000000000 + #define CM_TIMERCTL_BUSY_BITS 7:7 + #define CM_TIMERCTL_BUSY_SET 0x00000080 + #define CM_TIMERCTL_BUSY_CLR 0xffffff7f + #define CM_TIMERCTL_BUSY_MSB 7 + #define CM_TIMERCTL_BUSY_LSB 7 + #define CM_TIMERCTL_KILL_BITS 5:5 + #define CM_TIMERCTL_KILL_SET 0x00000020 + #define CM_TIMERCTL_KILL_CLR 0xffffffdf + #define CM_TIMERCTL_KILL_MSB 5 + #define CM_TIMERCTL_KILL_LSB 5 + #define CM_TIMERCTL_ENAB_BITS 4:4 + #define CM_TIMERCTL_ENAB_SET 0x00000010 + #define CM_TIMERCTL_ENAB_CLR 0xffffffef + #define CM_TIMERCTL_ENAB_MSB 4 + #define CM_TIMERCTL_ENAB_LSB 4 + #define CM_TIMERCTL_SRC_BITS 1:0 + #define CM_TIMERCTL_SRC_SET 0x00000003 + #define CM_TIMERCTL_SRC_CLR 0xfffffffc + #define CM_TIMERCTL_SRC_MSB 1 + #define CM_TIMERCTL_SRC_LSB 0 +#define CM_TIMERDIV HW_REGISTER_RW( 0x7e1010ec ) + #define CM_TIMERDIV_MASK 0x0003ffff + #define CM_TIMERDIV_WIDTH 18 + #define CM_TIMERDIV_RESET 0000000000 + #define CM_TIMERDIV_DIV_BITS 17:0 + #define CM_TIMERDIV_DIV_SET 0x0003ffff + #define CM_TIMERDIV_DIV_CLR 0xfffc0000 + #define CM_TIMERDIV_DIV_MSB 17 + #define CM_TIMERDIV_DIV_LSB 0 +#define CM_UARTCTL HW_REGISTER_RW( 0x7e1010f0 ) + #define CM_UARTCTL_MASK 0x000000bf + #define CM_UARTCTL_WIDTH 8 + #define CM_UARTCTL_RESET 0000000000 + #define CM_UARTCTL_BUSY_BITS 7:7 + #define CM_UARTCTL_BUSY_SET 0x00000080 + #define CM_UARTCTL_BUSY_CLR 0xffffff7f + #define CM_UARTCTL_BUSY_MSB 7 + #define CM_UARTCTL_BUSY_LSB 7 + #define CM_UARTCTL_KILL_BITS 5:5 + #define CM_UARTCTL_KILL_SET 0x00000020 + #define CM_UARTCTL_KILL_CLR 0xffffffdf + #define CM_UARTCTL_KILL_MSB 5 + #define CM_UARTCTL_KILL_LSB 5 + #define CM_UARTCTL_ENAB_BITS 4:4 + #define CM_UARTCTL_ENAB_SET 0x00000010 + #define CM_UARTCTL_ENAB_CLR 0xffffffef + #define CM_UARTCTL_ENAB_MSB 4 + #define CM_UARTCTL_ENAB_LSB 4 + #define CM_UARTCTL_SRC_BITS 3:0 + #define CM_UARTCTL_SRC_SET 0x0000000f + #define CM_UARTCTL_SRC_CLR 0xfffffff0 + #define CM_UARTCTL_SRC_MSB 3 + #define CM_UARTCTL_SRC_LSB 0 +#define CM_UARTDIV HW_REGISTER_RW( 0x7e1010f4 ) + #define CM_UARTDIV_MASK 0x003fffff + #define CM_UARTDIV_WIDTH 22 + #define CM_UARTDIV_RESET 0000000000 + #define CM_UARTDIV_DIV_BITS 21:0 + #define CM_UARTDIV_DIV_SET 0x003fffff + #define CM_UARTDIV_DIV_CLR 0xffc00000 + #define CM_UARTDIV_DIV_MSB 21 + #define CM_UARTDIV_DIV_LSB 0 +#define CM_VECCTL HW_REGISTER_RW( 0x7e1010f8 ) + #define CM_VECCTL_MASK 0x000000bf + #define CM_VECCTL_WIDTH 8 + #define CM_VECCTL_RESET 0000000000 + #define CM_VECCTL_BUSY_BITS 7:7 + #define CM_VECCTL_BUSY_SET 0x00000080 + #define CM_VECCTL_BUSY_CLR 0xffffff7f + #define CM_VECCTL_BUSY_MSB 7 + #define CM_VECCTL_BUSY_LSB 7 + #define CM_VECCTL_KILL_BITS 5:5 + #define CM_VECCTL_KILL_SET 0x00000020 + #define CM_VECCTL_KILL_CLR 0xffffffdf + #define CM_VECCTL_KILL_MSB 5 + #define CM_VECCTL_KILL_LSB 5 + #define CM_VECCTL_ENAB_BITS 4:4 + #define CM_VECCTL_ENAB_SET 0x00000010 + #define CM_VECCTL_ENAB_CLR 0xffffffef + #define CM_VECCTL_ENAB_MSB 4 + #define CM_VECCTL_ENAB_LSB 4 + #define CM_VECCTL_SRC_BITS 3:0 + #define CM_VECCTL_SRC_SET 0x0000000f + #define CM_VECCTL_SRC_CLR 0xfffffff0 + #define CM_VECCTL_SRC_MSB 3 + #define CM_VECCTL_SRC_LSB 0 +#define CM_VECDIV HW_REGISTER_RW( 0x7e1010fc ) + #define CM_VECDIV_MASK 0x0000f000 + #define CM_VECDIV_WIDTH 16 + #define CM_VECDIV_RESET 0000000000 + #define CM_VECDIV_DIV_BITS 15:12 + #define CM_VECDIV_DIV_SET 0x0000f000 + #define CM_VECDIV_DIV_CLR 0xffff0fff + #define CM_VECDIV_DIV_MSB 15 + #define CM_VECDIV_DIV_LSB 12 +#define CM_AVEOCTL HW_REGISTER_RW( 0x7e1011b8 ) + #define CM_AVEOCTL_MASK 0x000000bf + #define CM_AVEOCTL_WIDTH 8 + #define CM_AVEOCTL_RESET 0000000000 + #define CM_AVEOCTL_BUSY_BITS 7:7 + #define CM_AVEOCTL_BUSY_SET 0x00000080 + #define CM_AVEOCTL_BUSY_CLR 0xffffff7f + #define CM_AVEOCTL_BUSY_MSB 7 + #define CM_AVEOCTL_BUSY_LSB 7 + #define CM_AVEOCTL_KILL_BITS 5:5 + #define CM_AVEOCTL_KILL_SET 0x00000020 + #define CM_AVEOCTL_KILL_CLR 0xffffffdf + #define CM_AVEOCTL_KILL_MSB 5 + #define CM_AVEOCTL_KILL_LSB 5 + #define CM_AVEOCTL_ENAB_BITS 4:4 + #define CM_AVEOCTL_ENAB_SET 0x00000010 + #define CM_AVEOCTL_ENAB_CLR 0xffffffef + #define CM_AVEOCTL_ENAB_MSB 4 + #define CM_AVEOCTL_ENAB_LSB 4 + #define CM_AVEOCTL_SRC_BITS 3:0 + #define CM_AVEOCTL_SRC_SET 0x0000000f + #define CM_AVEOCTL_SRC_CLR 0xfffffff0 + #define CM_AVEOCTL_SRC_MSB 3 + #define CM_AVEOCTL_SRC_LSB 0 +#define CM_AVEODIV HW_REGISTER_RW( 0x7e1011bc ) + #define CM_AVEODIV_MASK 0x0000f000 + #define CM_AVEODIV_WIDTH 16 + #define CM_AVEODIV_RESET 0000000000 + #define CM_AVEODIV_DIV_BITS 15:12 + #define CM_AVEODIV_DIV_SET 0x0000f000 + #define CM_AVEODIV_DIV_CLR 0xffff0fff + #define CM_AVEODIV_DIV_MSB 15 + #define CM_AVEODIV_DIV_LSB 12 +#define CM_EMMCCTL HW_REGISTER_RW( 0x7e1011c0 ) + #define CM_EMMCCTL_MASK 0x000000bf + #define CM_EMMCCTL_WIDTH 8 + #define CM_EMMCCTL_RESET 0000000000 + #define CM_EMMCCTL_BUSY_BITS 7:7 + #define CM_EMMCCTL_BUSY_SET 0x00000080 + #define CM_EMMCCTL_BUSY_CLR 0xffffff7f + #define CM_EMMCCTL_BUSY_MSB 7 + #define CM_EMMCCTL_BUSY_LSB 7 + #define CM_EMMCCTL_KILL_BITS 5:5 + #define CM_EMMCCTL_KILL_SET 0x00000020 + #define CM_EMMCCTL_KILL_CLR 0xffffffdf + #define CM_EMMCCTL_KILL_MSB 5 + #define CM_EMMCCTL_KILL_LSB 5 + #define CM_EMMCCTL_ENAB_BITS 4:4 + #define CM_EMMCCTL_ENAB_SET 0x00000010 + #define CM_EMMCCTL_ENAB_CLR 0xffffffef + #define CM_EMMCCTL_ENAB_MSB 4 + #define CM_EMMCCTL_ENAB_LSB 4 + #define CM_EMMCCTL_SRC_BITS 3:0 + #define CM_EMMCCTL_SRC_SET 0x0000000f + #define CM_EMMCCTL_SRC_CLR 0xfffffff0 + #define CM_EMMCCTL_SRC_MSB 3 + #define CM_EMMCCTL_SRC_LSB 0 +#define CM_EMMCDIV HW_REGISTER_RW( 0x7e1011c4 ) + #define CM_EMMCDIV_MASK 0x0000fff0 + #define CM_EMMCDIV_WIDTH 16 + #define CM_EMMCDIV_RESET 0000000000 + #define CM_EMMCDIV_DIV_BITS 15:4 + #define CM_EMMCDIV_DIV_SET 0x0000fff0 + #define CM_EMMCDIV_DIV_CLR 0xffff000f + #define CM_EMMCDIV_DIV_MSB 15 + #define CM_EMMCDIV_DIV_LSB 4 +#define CM_OSCCOUNT HW_REGISTER_RW( 0x7e101100 ) + #define CM_OSCCOUNT_MASK 0x0000ffff + #define CM_OSCCOUNT_WIDTH 16 + #define CM_OSCCOUNT_RESET 0000000000 + #define CM_OSCCOUNT_NUM_BITS 15:0 + #define CM_OSCCOUNT_NUM_SET 0x0000ffff + #define CM_OSCCOUNT_NUM_CLR 0xffff0000 + #define CM_OSCCOUNT_NUM_MSB 15 + #define CM_OSCCOUNT_NUM_LSB 0 +#define CM_PLLA HW_REGISTER_RW( 0x7e101104 ) + #define CM_PLLA_MASK 0x000003ff + #define CM_PLLA_WIDTH 10 + #define CM_PLLA_RESET 0x00000300 + #define CM_PLLA_DIGRST_BITS 9:9 + #define CM_PLLA_DIGRST_SET 0x00000200 + #define CM_PLLA_DIGRST_CLR 0xfffffdff + #define CM_PLLA_DIGRST_MSB 9 + #define CM_PLLA_DIGRST_LSB 9 + #define CM_PLLA_ANARST_BITS 8:8 + #define CM_PLLA_ANARST_SET 0x00000100 + #define CM_PLLA_ANARST_CLR 0xfffffeff + #define CM_PLLA_ANARST_MSB 8 + #define CM_PLLA_ANARST_LSB 8 + #define CM_PLLA_HOLDPER_BITS 7:7 + #define CM_PLLA_HOLDPER_SET 0x00000080 + #define CM_PLLA_HOLDPER_CLR 0xffffff7f + #define CM_PLLA_HOLDPER_MSB 7 + #define CM_PLLA_HOLDPER_LSB 7 + #define CM_PLLA_LOADPER_BITS 6:6 + #define CM_PLLA_LOADPER_SET 0x00000040 + #define CM_PLLA_LOADPER_CLR 0xffffffbf + #define CM_PLLA_LOADPER_MSB 6 + #define CM_PLLA_LOADPER_LSB 6 + #define CM_PLLA_HOLDCORE_BITS 5:5 + #define CM_PLLA_HOLDCORE_SET 0x00000020 + #define CM_PLLA_HOLDCORE_CLR 0xffffffdf + #define CM_PLLA_HOLDCORE_MSB 5 + #define CM_PLLA_HOLDCORE_LSB 5 + #define CM_PLLA_LOADCORE_BITS 4:4 + #define CM_PLLA_LOADCORE_SET 0x00000010 + #define CM_PLLA_LOADCORE_CLR 0xffffffef + #define CM_PLLA_LOADCORE_MSB 4 + #define CM_PLLA_LOADCORE_LSB 4 + #define CM_PLLA_HOLDCCP2_BITS 3:3 + #define CM_PLLA_HOLDCCP2_SET 0x00000008 + #define CM_PLLA_HOLDCCP2_CLR 0xfffffff7 + #define CM_PLLA_HOLDCCP2_MSB 3 + #define CM_PLLA_HOLDCCP2_LSB 3 + #define CM_PLLA_LOADCCP2_BITS 2:2 + #define CM_PLLA_LOADCCP2_SET 0x00000004 + #define CM_PLLA_LOADCCP2_CLR 0xfffffffb + #define CM_PLLA_LOADCCP2_MSB 2 + #define CM_PLLA_LOADCCP2_LSB 2 + #define CM_PLLA_HOLDDSI0_BITS 1:1 + #define CM_PLLA_HOLDDSI0_SET 0x00000002 + #define CM_PLLA_HOLDDSI0_CLR 0xfffffffd + #define CM_PLLA_HOLDDSI0_MSB 1 + #define CM_PLLA_HOLDDSI0_LSB 1 + #define CM_PLLA_LOADDSI0_BITS 0:0 + #define CM_PLLA_LOADDSI0_SET 0x00000001 + #define CM_PLLA_LOADDSI0_CLR 0xfffffffe + #define CM_PLLA_LOADDSI0_MSB 0 + #define CM_PLLA_LOADDSI0_LSB 0 +#define CM_PLLC HW_REGISTER_RW( 0x7e101108 ) + #define CM_PLLC_MASK 0x000003ff + #define CM_PLLC_WIDTH 10 + #define CM_PLLC_RESET 0x00000300 + #define CM_PLLC_DIGRST_BITS 9:9 + #define CM_PLLC_DIGRST_SET 0x00000200 + #define CM_PLLC_DIGRST_CLR 0xfffffdff + #define CM_PLLC_DIGRST_MSB 9 + #define CM_PLLC_DIGRST_LSB 9 + #define CM_PLLC_ANARST_BITS 8:8 + #define CM_PLLC_ANARST_SET 0x00000100 + #define CM_PLLC_ANARST_CLR 0xfffffeff + #define CM_PLLC_ANARST_MSB 8 + #define CM_PLLC_ANARST_LSB 8 + #define CM_PLLC_HOLDPER_BITS 7:7 + #define CM_PLLC_HOLDPER_SET 0x00000080 + #define CM_PLLC_HOLDPER_CLR 0xffffff7f + #define CM_PLLC_HOLDPER_MSB 7 + #define CM_PLLC_HOLDPER_LSB 7 + #define CM_PLLC_LOADPER_BITS 6:6 + #define CM_PLLC_LOADPER_SET 0x00000040 + #define CM_PLLC_LOADPER_CLR 0xffffffbf + #define CM_PLLC_LOADPER_MSB 6 + #define CM_PLLC_LOADPER_LSB 6 + #define CM_PLLC_HOLDCORE2_BITS 5:5 + #define CM_PLLC_HOLDCORE2_SET 0x00000020 + #define CM_PLLC_HOLDCORE2_CLR 0xffffffdf + #define CM_PLLC_HOLDCORE2_MSB 5 + #define CM_PLLC_HOLDCORE2_LSB 5 + #define CM_PLLC_LOADCORE2_BITS 4:4 + #define CM_PLLC_LOADCORE2_SET 0x00000010 + #define CM_PLLC_LOADCORE2_CLR 0xffffffef + #define CM_PLLC_LOADCORE2_MSB 4 + #define CM_PLLC_LOADCORE2_LSB 4 + #define CM_PLLC_HOLDCORE1_BITS 3:3 + #define CM_PLLC_HOLDCORE1_SET 0x00000008 + #define CM_PLLC_HOLDCORE1_CLR 0xfffffff7 + #define CM_PLLC_HOLDCORE1_MSB 3 + #define CM_PLLC_HOLDCORE1_LSB 3 + #define CM_PLLC_LOADCORE1_BITS 2:2 + #define CM_PLLC_LOADCORE1_SET 0x00000004 + #define CM_PLLC_LOADCORE1_CLR 0xfffffffb + #define CM_PLLC_LOADCORE1_MSB 2 + #define CM_PLLC_LOADCORE1_LSB 2 + #define CM_PLLC_HOLDCORE0_BITS 1:1 + #define CM_PLLC_HOLDCORE0_SET 0x00000002 + #define CM_PLLC_HOLDCORE0_CLR 0xfffffffd + #define CM_PLLC_HOLDCORE0_MSB 1 + #define CM_PLLC_HOLDCORE0_LSB 1 + #define CM_PLLC_LOADCORE0_BITS 0:0 + #define CM_PLLC_LOADCORE0_SET 0x00000001 + #define CM_PLLC_LOADCORE0_CLR 0xfffffffe + #define CM_PLLC_LOADCORE0_MSB 0 + #define CM_PLLC_LOADCORE0_LSB 0 +#define CM_PLLD HW_REGISTER_RW( 0x7e10110c ) + #define CM_PLLD_MASK 0x000003ff + #define CM_PLLD_WIDTH 10 + #define CM_PLLD_RESET 0x00000300 + #define CM_PLLD_DIGRST_BITS 9:9 + #define CM_PLLD_DIGRST_SET 0x00000200 + #define CM_PLLD_DIGRST_CLR 0xfffffdff + #define CM_PLLD_DIGRST_MSB 9 + #define CM_PLLD_DIGRST_LSB 9 + #define CM_PLLD_ANARST_BITS 8:8 + #define CM_PLLD_ANARST_SET 0x00000100 + #define CM_PLLD_ANARST_CLR 0xfffffeff + #define CM_PLLD_ANARST_MSB 8 + #define CM_PLLD_ANARST_LSB 8 + #define CM_PLLD_HOLDPER_BITS 7:7 + #define CM_PLLD_HOLDPER_SET 0x00000080 + #define CM_PLLD_HOLDPER_CLR 0xffffff7f + #define CM_PLLD_HOLDPER_MSB 7 + #define CM_PLLD_HOLDPER_LSB 7 + #define CM_PLLD_LOADPER_BITS 6:6 + #define CM_PLLD_LOADPER_SET 0x00000040 + #define CM_PLLD_LOADPER_CLR 0xffffffbf + #define CM_PLLD_LOADPER_MSB 6 + #define CM_PLLD_LOADPER_LSB 6 + #define CM_PLLD_HOLDCORE_BITS 5:5 + #define CM_PLLD_HOLDCORE_SET 0x00000020 + #define CM_PLLD_HOLDCORE_CLR 0xffffffdf + #define CM_PLLD_HOLDCORE_MSB 5 + #define CM_PLLD_HOLDCORE_LSB 5 + #define CM_PLLD_LOADCORE_BITS 4:4 + #define CM_PLLD_LOADCORE_SET 0x00000010 + #define CM_PLLD_LOADCORE_CLR 0xffffffef + #define CM_PLLD_LOADCORE_MSB 4 + #define CM_PLLD_LOADCORE_LSB 4 + #define CM_PLLD_HOLDDSI1_BITS 3:3 + #define CM_PLLD_HOLDDSI1_SET 0x00000008 + #define CM_PLLD_HOLDDSI1_CLR 0xfffffff7 + #define CM_PLLD_HOLDDSI1_MSB 3 + #define CM_PLLD_HOLDDSI1_LSB 3 + #define CM_PLLD_LOADDSI1_BITS 2:2 + #define CM_PLLD_LOADDSI1_SET 0x00000004 + #define CM_PLLD_LOADDSI1_CLR 0xfffffffb + #define CM_PLLD_LOADDSI1_MSB 2 + #define CM_PLLD_LOADDSI1_LSB 2 + #define CM_PLLD_HOLDDSI0_BITS 1:1 + #define CM_PLLD_HOLDDSI0_SET 0x00000002 + #define CM_PLLD_HOLDDSI0_CLR 0xfffffffd + #define CM_PLLD_HOLDDSI0_MSB 1 + #define CM_PLLD_HOLDDSI0_LSB 1 + #define CM_PLLD_LOADDSI0_BITS 0:0 + #define CM_PLLD_LOADDSI0_SET 0x00000001 + #define CM_PLLD_LOADDSI0_CLR 0xfffffffe + #define CM_PLLD_LOADDSI0_MSB 0 + #define CM_PLLD_LOADDSI0_LSB 0 +#define CM_PLLH HW_REGISTER_RW( 0x7e101110 ) + #define CM_PLLH_MASK 0x00000307 + #define CM_PLLH_WIDTH 10 + #define CM_PLLH_RESET 0x00000300 + #define CM_PLLH_DIGRST_BITS 9:9 + #define CM_PLLH_DIGRST_SET 0x00000200 + #define CM_PLLH_DIGRST_CLR 0xfffffdff + #define CM_PLLH_DIGRST_MSB 9 + #define CM_PLLH_DIGRST_LSB 9 + #define CM_PLLH_ANARST_BITS 8:8 + #define CM_PLLH_ANARST_SET 0x00000100 + #define CM_PLLH_ANARST_CLR 0xfffffeff + #define CM_PLLH_ANARST_MSB 8 + #define CM_PLLH_ANARST_LSB 8 + #define CM_PLLH_LOADRCAL_BITS 2:2 + #define CM_PLLH_LOADRCAL_SET 0x00000004 + #define CM_PLLH_LOADRCAL_CLR 0xfffffffb + #define CM_PLLH_LOADRCAL_MSB 2 + #define CM_PLLH_LOADRCAL_LSB 2 + #define CM_PLLH_LOADAUX_BITS 1:1 + #define CM_PLLH_LOADAUX_SET 0x00000002 + #define CM_PLLH_LOADAUX_CLR 0xfffffffd + #define CM_PLLH_LOADAUX_MSB 1 + #define CM_PLLH_LOADAUX_LSB 1 + #define CM_PLLH_LOADPIX_BITS 0:0 + #define CM_PLLH_LOADPIX_SET 0x00000001 + #define CM_PLLH_LOADPIX_CLR 0xfffffffe + #define CM_PLLH_LOADPIX_MSB 0 + #define CM_PLLH_LOADPIX_LSB 0 +#define CM_LOCK HW_REGISTER_RW( 0x7e101114 ) + #define CM_LOCK_MASK 0x000000ff + #define CM_LOCK_WIDTH 8 + #define CM_LOCK_RESET 0000000000 + #define CM_LOCK_FLOCKH_BITS 7:7 + #define CM_LOCK_FLOCKH_SET 0x00000080 + #define CM_LOCK_FLOCKH_CLR 0xffffff7f + #define CM_LOCK_FLOCKH_MSB 7 + #define CM_LOCK_FLOCKH_LSB 7 + #define CM_LOCK_FLOCKD_BITS 6:6 + #define CM_LOCK_FLOCKD_SET 0x00000040 + #define CM_LOCK_FLOCKD_CLR 0xffffffbf + #define CM_LOCK_FLOCKD_MSB 6 + #define CM_LOCK_FLOCKD_LSB 6 + #define CM_LOCK_FLOCKA_BITS 5:5 + #define CM_LOCK_FLOCKA_SET 0x00000020 + #define CM_LOCK_FLOCKA_CLR 0xffffffdf + #define CM_LOCK_FLOCKA_MSB 5 + #define CM_LOCK_FLOCKA_LSB 5 + #define CM_LOCK_FLOCKC_BITS 4:4 + #define CM_LOCK_FLOCKC_SET 0x00000010 + #define CM_LOCK_FLOCKC_CLR 0xffffffef + #define CM_LOCK_FLOCKC_MSB 4 + #define CM_LOCK_FLOCKC_LSB 4 + #define CM_LOCK_LOCKH_BITS 3:3 + #define CM_LOCK_LOCKH_SET 0x00000008 + #define CM_LOCK_LOCKH_CLR 0xfffffff7 + #define CM_LOCK_LOCKH_MSB 3 + #define CM_LOCK_LOCKH_LSB 3 + #define CM_LOCK_LOCKD_BITS 2:2 + #define CM_LOCK_LOCKD_SET 0x00000004 + #define CM_LOCK_LOCKD_CLR 0xfffffffb + #define CM_LOCK_LOCKD_MSB 2 + #define CM_LOCK_LOCKD_LSB 2 + #define CM_LOCK_LOCKA_BITS 1:1 + #define CM_LOCK_LOCKA_SET 0x00000002 + #define CM_LOCK_LOCKA_CLR 0xfffffffd + #define CM_LOCK_LOCKA_MSB 1 + #define CM_LOCK_LOCKA_LSB 1 + #define CM_LOCK_LOCKC_BITS 0:0 + #define CM_LOCK_LOCKC_SET 0x00000001 + #define CM_LOCK_LOCKC_CLR 0xfffffffe + #define CM_LOCK_LOCKC_MSB 0 + #define CM_LOCK_LOCKC_LSB 0 +#define CM_EVENT HW_REGISTER_RW( 0x7e101118 ) + #define CM_EVENT_MASK 0x001fffff + #define CM_EVENT_WIDTH 21 + #define CM_EVENT_RESET 0000000000 + #define CM_EVENT_RESUS_BITS 20:20 + #define CM_EVENT_RESUS_SET 0x00100000 + #define CM_EVENT_RESUS_CLR 0xffefffff + #define CM_EVENT_RESUS_MSB 20 + #define CM_EVENT_RESUS_LSB 20 + #define CM_EVENT_OCDONE_BITS 19:19 + #define CM_EVENT_OCDONE_SET 0x00080000 + #define CM_EVENT_OCDONE_CLR 0xfff7ffff + #define CM_EVENT_OCDONE_MSB 19 + #define CM_EVENT_OCDONE_LSB 19 + #define CM_EVENT_A2WDONE_BITS 18:18 + #define CM_EVENT_A2WDONE_SET 0x00040000 + #define CM_EVENT_A2WDONE_CLR 0xfffbffff + #define CM_EVENT_A2WDONE_MSB 18 + #define CM_EVENT_A2WDONE_LSB 18 + #define CM_EVENT_WRFAIL_BITS 17:17 + #define CM_EVENT_WRFAIL_SET 0x00020000 + #define CM_EVENT_WRFAIL_CLR 0xfffdffff + #define CM_EVENT_WRFAIL_MSB 17 + #define CM_EVENT_WRFAIL_LSB 17 + #define CM_EVENT_BADPASS_BITS 16:16 + #define CM_EVENT_BADPASS_SET 0x00010000 + #define CM_EVENT_BADPASS_CLR 0xfffeffff + #define CM_EVENT_BADPASS_MSB 16 + #define CM_EVENT_BADPASS_LSB 16 + #define CM_EVENT_FLOSSH_BITS 15:15 + #define CM_EVENT_FLOSSH_SET 0x00008000 + #define CM_EVENT_FLOSSH_CLR 0xffff7fff + #define CM_EVENT_FLOSSH_MSB 15 + #define CM_EVENT_FLOSSH_LSB 15 + #define CM_EVENT_FLOSSD_BITS 14:14 + #define CM_EVENT_FLOSSD_SET 0x00004000 + #define CM_EVENT_FLOSSD_CLR 0xffffbfff + #define CM_EVENT_FLOSSD_MSB 14 + #define CM_EVENT_FLOSSD_LSB 14 + #define CM_EVENT_FLOSSA_BITS 13:13 + #define CM_EVENT_FLOSSA_SET 0x00002000 + #define CM_EVENT_FLOSSA_CLR 0xffffdfff + #define CM_EVENT_FLOSSA_MSB 13 + #define CM_EVENT_FLOSSA_LSB 13 + #define CM_EVENT_FLOSSC_BITS 12:12 + #define CM_EVENT_FLOSSC_SET 0x00001000 + #define CM_EVENT_FLOSSC_CLR 0xffffefff + #define CM_EVENT_FLOSSC_MSB 12 + #define CM_EVENT_FLOSSC_LSB 12 + #define CM_EVENT_FGAINH_BITS 11:11 + #define CM_EVENT_FGAINH_SET 0x00000800 + #define CM_EVENT_FGAINH_CLR 0xfffff7ff + #define CM_EVENT_FGAINH_MSB 11 + #define CM_EVENT_FGAINH_LSB 11 + #define CM_EVENT_FGAIND_BITS 10:10 + #define CM_EVENT_FGAIND_SET 0x00000400 + #define CM_EVENT_FGAIND_CLR 0xfffffbff + #define CM_EVENT_FGAIND_MSB 10 + #define CM_EVENT_FGAIND_LSB 10 + #define CM_EVENT_FGAINA_BITS 9:9 + #define CM_EVENT_FGAINA_SET 0x00000200 + #define CM_EVENT_FGAINA_CLR 0xfffffdff + #define CM_EVENT_FGAINA_MSB 9 + #define CM_EVENT_FGAINA_LSB 9 + #define CM_EVENT_FGAINC_BITS 8:8 + #define CM_EVENT_FGAINC_SET 0x00000100 + #define CM_EVENT_FGAINC_CLR 0xfffffeff + #define CM_EVENT_FGAINC_MSB 8 + #define CM_EVENT_FGAINC_LSB 8 + #define CM_EVENT_LOSSH_BITS 7:7 + #define CM_EVENT_LOSSH_SET 0x00000080 + #define CM_EVENT_LOSSH_CLR 0xffffff7f + #define CM_EVENT_LOSSH_MSB 7 + #define CM_EVENT_LOSSH_LSB 7 + #define CM_EVENT_LOSSD_BITS 6:6 + #define CM_EVENT_LOSSD_SET 0x00000040 + #define CM_EVENT_LOSSD_CLR 0xffffffbf + #define CM_EVENT_LOSSD_MSB 6 + #define CM_EVENT_LOSSD_LSB 6 + #define CM_EVENT_LOSSA_BITS 5:5 + #define CM_EVENT_LOSSA_SET 0x00000020 + #define CM_EVENT_LOSSA_CLR 0xffffffdf + #define CM_EVENT_LOSSA_MSB 5 + #define CM_EVENT_LOSSA_LSB 5 + #define CM_EVENT_LOSSC_BITS 4:4 + #define CM_EVENT_LOSSC_SET 0x00000010 + #define CM_EVENT_LOSSC_CLR 0xffffffef + #define CM_EVENT_LOSSC_MSB 4 + #define CM_EVENT_LOSSC_LSB 4 + #define CM_EVENT_GAINH_BITS 3:3 + #define CM_EVENT_GAINH_SET 0x00000008 + #define CM_EVENT_GAINH_CLR 0xfffffff7 + #define CM_EVENT_GAINH_MSB 3 + #define CM_EVENT_GAINH_LSB 3 + #define CM_EVENT_GAIND_BITS 2:2 + #define CM_EVENT_GAIND_SET 0x00000004 + #define CM_EVENT_GAIND_CLR 0xfffffffb + #define CM_EVENT_GAIND_MSB 2 + #define CM_EVENT_GAIND_LSB 2 + #define CM_EVENT_GAINA_BITS 1:1 + #define CM_EVENT_GAINA_SET 0x00000002 + #define CM_EVENT_GAINA_CLR 0xfffffffd + #define CM_EVENT_GAINA_MSB 1 + #define CM_EVENT_GAINA_LSB 1 + #define CM_EVENT_GAINC_BITS 0:0 + #define CM_EVENT_GAINC_SET 0x00000001 + #define CM_EVENT_GAINC_CLR 0xfffffffe + #define CM_EVENT_GAINC_MSB 0 + #define CM_EVENT_GAINC_LSB 0 +#define CM_INTEN HW_REGISTER_RW( 0x7e10111c ) + #define CM_INTEN_MASK 0x001fffff + #define CM_INTEN_WIDTH 21 + #define CM_INTEN_RESET 0000000000 + #define CM_INTEN_RESUS_BITS 20:20 + #define CM_INTEN_RESUS_SET 0x00100000 + #define CM_INTEN_RESUS_CLR 0xffefffff + #define CM_INTEN_RESUS_MSB 20 + #define CM_INTEN_RESUS_LSB 20 + #define CM_INTEN_OCDONE_BITS 19:19 + #define CM_INTEN_OCDONE_SET 0x00080000 + #define CM_INTEN_OCDONE_CLR 0xfff7ffff + #define CM_INTEN_OCDONE_MSB 19 + #define CM_INTEN_OCDONE_LSB 19 + #define CM_INTEN_A2WDONE_BITS 18:18 + #define CM_INTEN_A2WDONE_SET 0x00040000 + #define CM_INTEN_A2WDONE_CLR 0xfffbffff + #define CM_INTEN_A2WDONE_MSB 18 + #define CM_INTEN_A2WDONE_LSB 18 + #define CM_INTEN_WRFAIL_BITS 17:17 + #define CM_INTEN_WRFAIL_SET 0x00020000 + #define CM_INTEN_WRFAIL_CLR 0xfffdffff + #define CM_INTEN_WRFAIL_MSB 17 + #define CM_INTEN_WRFAIL_LSB 17 + #define CM_INTEN_BADPASS_BITS 16:16 + #define CM_INTEN_BADPASS_SET 0x00010000 + #define CM_INTEN_BADPASS_CLR 0xfffeffff + #define CM_INTEN_BADPASS_MSB 16 + #define CM_INTEN_BADPASS_LSB 16 + #define CM_INTEN_FLOSSH_BITS 15:15 + #define CM_INTEN_FLOSSH_SET 0x00008000 + #define CM_INTEN_FLOSSH_CLR 0xffff7fff + #define CM_INTEN_FLOSSH_MSB 15 + #define CM_INTEN_FLOSSH_LSB 15 + #define CM_INTEN_FLOSSD_BITS 14:14 + #define CM_INTEN_FLOSSD_SET 0x00004000 + #define CM_INTEN_FLOSSD_CLR 0xffffbfff + #define CM_INTEN_FLOSSD_MSB 14 + #define CM_INTEN_FLOSSD_LSB 14 + #define CM_INTEN_FLOSSA_BITS 13:13 + #define CM_INTEN_FLOSSA_SET 0x00002000 + #define CM_INTEN_FLOSSA_CLR 0xffffdfff + #define CM_INTEN_FLOSSA_MSB 13 + #define CM_INTEN_FLOSSA_LSB 13 + #define CM_INTEN_FLOSSC_BITS 12:12 + #define CM_INTEN_FLOSSC_SET 0x00001000 + #define CM_INTEN_FLOSSC_CLR 0xffffefff + #define CM_INTEN_FLOSSC_MSB 12 + #define CM_INTEN_FLOSSC_LSB 12 + #define CM_INTEN_FGAINH_BITS 11:11 + #define CM_INTEN_FGAINH_SET 0x00000800 + #define CM_INTEN_FGAINH_CLR 0xfffff7ff + #define CM_INTEN_FGAINH_MSB 11 + #define CM_INTEN_FGAINH_LSB 11 + #define CM_INTEN_FGAIND_BITS 10:10 + #define CM_INTEN_FGAIND_SET 0x00000400 + #define CM_INTEN_FGAIND_CLR 0xfffffbff + #define CM_INTEN_FGAIND_MSB 10 + #define CM_INTEN_FGAIND_LSB 10 + #define CM_INTEN_FGAINA_BITS 9:9 + #define CM_INTEN_FGAINA_SET 0x00000200 + #define CM_INTEN_FGAINA_CLR 0xfffffdff + #define CM_INTEN_FGAINA_MSB 9 + #define CM_INTEN_FGAINA_LSB 9 + #define CM_INTEN_FGAINC_BITS 8:8 + #define CM_INTEN_FGAINC_SET 0x00000100 + #define CM_INTEN_FGAINC_CLR 0xfffffeff + #define CM_INTEN_FGAINC_MSB 8 + #define CM_INTEN_FGAINC_LSB 8 + #define CM_INTEN_LOSSH_BITS 7:7 + #define CM_INTEN_LOSSH_SET 0x00000080 + #define CM_INTEN_LOSSH_CLR 0xffffff7f + #define CM_INTEN_LOSSH_MSB 7 + #define CM_INTEN_LOSSH_LSB 7 + #define CM_INTEN_LOSSD_BITS 6:6 + #define CM_INTEN_LOSSD_SET 0x00000040 + #define CM_INTEN_LOSSD_CLR 0xffffffbf + #define CM_INTEN_LOSSD_MSB 6 + #define CM_INTEN_LOSSD_LSB 6 + #define CM_INTEN_LOSSA_BITS 5:5 + #define CM_INTEN_LOSSA_SET 0x00000020 + #define CM_INTEN_LOSSA_CLR 0xffffffdf + #define CM_INTEN_LOSSA_MSB 5 + #define CM_INTEN_LOSSA_LSB 5 + #define CM_INTEN_LOSSC_BITS 4:4 + #define CM_INTEN_LOSSC_SET 0x00000010 + #define CM_INTEN_LOSSC_CLR 0xffffffef + #define CM_INTEN_LOSSC_MSB 4 + #define CM_INTEN_LOSSC_LSB 4 + #define CM_INTEN_GAINH_BITS 3:3 + #define CM_INTEN_GAINH_SET 0x00000008 + #define CM_INTEN_GAINH_CLR 0xfffffff7 + #define CM_INTEN_GAINH_MSB 3 + #define CM_INTEN_GAINH_LSB 3 + #define CM_INTEN_GAIND_BITS 2:2 + #define CM_INTEN_GAIND_SET 0x00000004 + #define CM_INTEN_GAIND_CLR 0xfffffffb + #define CM_INTEN_GAIND_MSB 2 + #define CM_INTEN_GAIND_LSB 2 + #define CM_INTEN_GAINA_BITS 1:1 + #define CM_INTEN_GAINA_SET 0x00000002 + #define CM_INTEN_GAINA_CLR 0xfffffffd + #define CM_INTEN_GAINA_MSB 1 + #define CM_INTEN_GAINA_LSB 1 + #define CM_INTEN_GAINC_BITS 0:0 + #define CM_INTEN_GAINC_SET 0x00000001 + #define CM_INTEN_GAINC_CLR 0xfffffffe + #define CM_INTEN_GAINC_MSB 0 + #define CM_INTEN_GAINC_LSB 0 +#define CM_DSI0HSCK HW_REGISTER_RW( 0x7e101120 ) + #define CM_DSI0HSCK_MASK 0x00000001 + #define CM_DSI0HSCK_WIDTH 1 + #define CM_DSI0HSCK_RESET 0000000000 + #define CM_DSI0HSCK_SELPLLD_BITS 0:0 + #define CM_DSI0HSCK_SELPLLD_SET 0x00000001 + #define CM_DSI0HSCK_SELPLLD_CLR 0xfffffffe + #define CM_DSI0HSCK_SELPLLD_MSB 0 + #define CM_DSI0HSCK_SELPLLD_LSB 0 +#define CM_CKSM HW_REGISTER_RW( 0x7e101124 ) + #define CM_CKSM_MASK 0x003fffff + #define CM_CKSM_WIDTH 22 + #define CM_CKSM_RESET 0000000000 + #define CM_CKSM_STEP_BITS 21:21 + #define CM_CKSM_STEP_SET 0x00200000 + #define CM_CKSM_STEP_CLR 0xffdfffff + #define CM_CKSM_STEP_MSB 21 + #define CM_CKSM_STEP_LSB 21 + #define CM_CKSM_AUTO_BITS 20:20 + #define CM_CKSM_AUTO_SET 0x00100000 + #define CM_CKSM_AUTO_CLR 0xffefffff + #define CM_CKSM_AUTO_MSB 20 + #define CM_CKSM_AUTO_LSB 20 + #define CM_CKSM_OSC_BITS 19:18 + #define CM_CKSM_OSC_SET 0x000c0000 + #define CM_CKSM_OSC_CLR 0xfff3ffff + #define CM_CKSM_OSC_MSB 19 + #define CM_CKSM_OSC_LSB 18 + #define CM_CKSM_CFG_BITS 17:16 + #define CM_CKSM_CFG_SET 0x00030000 + #define CM_CKSM_CFG_CLR 0xfffcffff + #define CM_CKSM_CFG_MSB 17 + #define CM_CKSM_CFG_LSB 16 + #define CM_CKSM_FRCE_BITS 15:8 + #define CM_CKSM_FRCE_SET 0x0000ff00 + #define CM_CKSM_FRCE_CLR 0xffff00ff + #define CM_CKSM_FRCE_MSB 15 + #define CM_CKSM_FRCE_LSB 8 + #define CM_CKSM_STATE_BITS 7:0 + #define CM_CKSM_STATE_SET 0x000000ff + #define CM_CKSM_STATE_CLR 0xffffff00 + #define CM_CKSM_STATE_MSB 7 + #define CM_CKSM_STATE_LSB 0 + +#endif diff --git a/bcm2708_chip/cpr_powman.h b/bcm2708_chip/cpr_powman.h new file mode 100755 index 0000000..6b4981f --- /dev/null +++ b/bcm2708_chip/cpr_powman.h @@ -0,0 +1,840 @@ +// This file was generated by the create_regs script +#define PM_PASSWORD 0x5a000000 +#define PM_BASE 0x7e100000 +#define PM_APB_ID 0x0000706d +#define PM_GNRIC HW_REGISTER_RW( 0x7e100000 ) + #define PM_GNRIC_MASK 0x007f1fff + #define PM_GNRIC_WIDTH 23 + #define PM_GNRIC_RESET 0000000000 + #define PM_GNRIC_CFG_BITS 22:16 + #define PM_GNRIC_CFG_SET 0x007f0000 + #define PM_GNRIC_CFG_CLR 0xff80ffff + #define PM_GNRIC_CFG_MSB 22 + #define PM_GNRIC_CFG_LSB 16 + #define PM_GNRIC_ENAB_BITS 12:12 + #define PM_GNRIC_ENAB_SET 0x00001000 + #define PM_GNRIC_ENAB_CLR 0xffffefff + #define PM_GNRIC_ENAB_MSB 12 + #define PM_GNRIC_ENAB_LSB 12 + #define PM_GNRIC_RSTN_BITS 11:6 + #define PM_GNRIC_RSTN_SET 0x00000fc0 + #define PM_GNRIC_RSTN_CLR 0xfffff03f + #define PM_GNRIC_RSTN_MSB 11 + #define PM_GNRIC_RSTN_LSB 6 + #define PM_GNRIC_ISFUNC_BITS 5:5 + #define PM_GNRIC_ISFUNC_SET 0x00000020 + #define PM_GNRIC_ISFUNC_CLR 0xffffffdf + #define PM_GNRIC_ISFUNC_MSB 5 + #define PM_GNRIC_ISFUNC_LSB 5 + #define PM_GNRIC_MRDONE_BITS 4:4 + #define PM_GNRIC_MRDONE_SET 0x00000010 + #define PM_GNRIC_MRDONE_CLR 0xffffffef + #define PM_GNRIC_MRDONE_MSB 4 + #define PM_GNRIC_MRDONE_LSB 4 + #define PM_GNRIC_MEMREP_BITS 3:3 + #define PM_GNRIC_MEMREP_SET 0x00000008 + #define PM_GNRIC_MEMREP_CLR 0xfffffff7 + #define PM_GNRIC_MEMREP_MSB 3 + #define PM_GNRIC_MEMREP_LSB 3 + #define PM_GNRIC_ISPOW_BITS 2:2 + #define PM_GNRIC_ISPOW_SET 0x00000004 + #define PM_GNRIC_ISPOW_CLR 0xfffffffb + #define PM_GNRIC_ISPOW_MSB 2 + #define PM_GNRIC_ISPOW_LSB 2 + #define PM_GNRIC_POWOK_BITS 1:1 + #define PM_GNRIC_POWOK_SET 0x00000002 + #define PM_GNRIC_POWOK_CLR 0xfffffffd + #define PM_GNRIC_POWOK_MSB 1 + #define PM_GNRIC_POWOK_LSB 1 + #define PM_GNRIC_POWUP_BITS 0:0 + #define PM_GNRIC_POWUP_SET 0x00000001 + #define PM_GNRIC_POWUP_CLR 0xfffffffe + #define PM_GNRIC_POWUP_MSB 0 + #define PM_GNRIC_POWUP_LSB 0 +#define PM_AUDIO HW_REGISTER_RW( 0x7e100004 ) + #define PM_AUDIO_MASK 0x003fffff + #define PM_AUDIO_WIDTH 22 + #define PM_AUDIO_RESET 0x003000ff + #define PM_AUDIO_RSTN_BITS 21:21 + #define PM_AUDIO_RSTN_SET 0x00200000 + #define PM_AUDIO_RSTN_CLR 0xffdfffff + #define PM_AUDIO_RSTN_MSB 21 + #define PM_AUDIO_RSTN_LSB 21 + #define PM_AUDIO_CTRLEN_BITS 20:20 + #define PM_AUDIO_CTRLEN_SET 0x00100000 + #define PM_AUDIO_CTRLEN_CLR 0xffefffff + #define PM_AUDIO_CTRLEN_MSB 20 + #define PM_AUDIO_CTRLEN_LSB 20 + #define PM_AUDIO_APSM_BITS 19:0 + #define PM_AUDIO_APSM_SET 0x000fffff + #define PM_AUDIO_APSM_CLR 0xfff00000 + #define PM_AUDIO_APSM_MSB 19 + #define PM_AUDIO_APSM_LSB 0 +#define PM_STATUS HW_REGISTER_RO( 0x7e100018 ) + #define PM_STATUS_MASK 0x00ffffff + #define PM_STATUS_WIDTH 24 + #define PM_STATUS_RESET 0000000000 +#define PM_IMAGE HW_REGISTER_RW( 0x7e100108 ) + #define PM_IMAGE_MASK 0x007f11ff + #define PM_IMAGE_WIDTH 23 + #define PM_IMAGE_RESET 0x00001000 + #define PM_IMAGE_CFG_BITS 22:16 + #define PM_IMAGE_CFG_SET 0x007f0000 + #define PM_IMAGE_CFG_CLR 0xff80ffff + #define PM_IMAGE_CFG_MSB 22 + #define PM_IMAGE_CFG_LSB 16 + #define PM_IMAGE_ENAB_BITS 12:12 + #define PM_IMAGE_ENAB_SET 0x00001000 + #define PM_IMAGE_ENAB_CLR 0xffffefff + #define PM_IMAGE_ENAB_MSB 12 + #define PM_IMAGE_ENAB_LSB 12 + #define PM_IMAGE_ISPRSTN_BITS 8:8 + #define PM_IMAGE_ISPRSTN_SET 0x00000100 + #define PM_IMAGE_ISPRSTN_CLR 0xfffffeff + #define PM_IMAGE_ISPRSTN_MSB 8 + #define PM_IMAGE_ISPRSTN_LSB 8 + #define PM_IMAGE_H264RSTN_BITS 7:7 + #define PM_IMAGE_H264RSTN_SET 0x00000080 + #define PM_IMAGE_H264RSTN_CLR 0xffffff7f + #define PM_IMAGE_H264RSTN_MSB 7 + #define PM_IMAGE_H264RSTN_LSB 7 + #define PM_IMAGE_PERIRSTN_BITS 6:6 + #define PM_IMAGE_PERIRSTN_SET 0x00000040 + #define PM_IMAGE_PERIRSTN_CLR 0xffffffbf + #define PM_IMAGE_PERIRSTN_MSB 6 + #define PM_IMAGE_PERIRSTN_LSB 6 + #define PM_IMAGE_ISFUNC_BITS 5:5 + #define PM_IMAGE_ISFUNC_SET 0x00000020 + #define PM_IMAGE_ISFUNC_CLR 0xffffffdf + #define PM_IMAGE_ISFUNC_MSB 5 + #define PM_IMAGE_ISFUNC_LSB 5 + #define PM_IMAGE_MRDONE_BITS 4:4 + #define PM_IMAGE_MRDONE_SET 0x00000010 + #define PM_IMAGE_MRDONE_CLR 0xffffffef + #define PM_IMAGE_MRDONE_MSB 4 + #define PM_IMAGE_MRDONE_LSB 4 + #define PM_IMAGE_MEMREP_BITS 3:3 + #define PM_IMAGE_MEMREP_SET 0x00000008 + #define PM_IMAGE_MEMREP_CLR 0xfffffff7 + #define PM_IMAGE_MEMREP_MSB 3 + #define PM_IMAGE_MEMREP_LSB 3 + #define PM_IMAGE_ISPOW_BITS 2:2 + #define PM_IMAGE_ISPOW_SET 0x00000004 + #define PM_IMAGE_ISPOW_CLR 0xfffffffb + #define PM_IMAGE_ISPOW_MSB 2 + #define PM_IMAGE_ISPOW_LSB 2 + #define PM_IMAGE_POWOK_BITS 1:1 + #define PM_IMAGE_POWOK_SET 0x00000002 + #define PM_IMAGE_POWOK_CLR 0xfffffffd + #define PM_IMAGE_POWOK_MSB 1 + #define PM_IMAGE_POWOK_LSB 1 + #define PM_IMAGE_POWUP_BITS 0:0 + #define PM_IMAGE_POWUP_SET 0x00000001 + #define PM_IMAGE_POWUP_CLR 0xfffffffe + #define PM_IMAGE_POWUP_MSB 0 + #define PM_IMAGE_POWUP_LSB 0 +#define PM_GRAFX HW_REGISTER_RW( 0x7e10010c ) + #define PM_GRAFX_MASK 0x007f107f + #define PM_GRAFX_WIDTH 23 + #define PM_GRAFX_RESET 0x00001000 + #define PM_GRAFX_CFG_BITS 22:16 + #define PM_GRAFX_CFG_SET 0x007f0000 + #define PM_GRAFX_CFG_CLR 0xff80ffff + #define PM_GRAFX_CFG_MSB 22 + #define PM_GRAFX_CFG_LSB 16 + #define PM_GRAFX_ENAB_BITS 12:12 + #define PM_GRAFX_ENAB_SET 0x00001000 + #define PM_GRAFX_ENAB_CLR 0xffffefff + #define PM_GRAFX_ENAB_MSB 12 + #define PM_GRAFX_ENAB_LSB 12 + #define PM_GRAFX_V3DRSTN_BITS 6:6 + #define PM_GRAFX_V3DRSTN_SET 0x00000040 + #define PM_GRAFX_V3DRSTN_CLR 0xffffffbf + #define PM_GRAFX_V3DRSTN_MSB 6 + #define PM_GRAFX_V3DRSTN_LSB 6 + #define PM_GRAFX_ISFUNC_BITS 5:5 + #define PM_GRAFX_ISFUNC_SET 0x00000020 + #define PM_GRAFX_ISFUNC_CLR 0xffffffdf + #define PM_GRAFX_ISFUNC_MSB 5 + #define PM_GRAFX_ISFUNC_LSB 5 + #define PM_GRAFX_MRDONE_BITS 4:4 + #define PM_GRAFX_MRDONE_SET 0x00000010 + #define PM_GRAFX_MRDONE_CLR 0xffffffef + #define PM_GRAFX_MRDONE_MSB 4 + #define PM_GRAFX_MRDONE_LSB 4 + #define PM_GRAFX_MEMREP_BITS 3:3 + #define PM_GRAFX_MEMREP_SET 0x00000008 + #define PM_GRAFX_MEMREP_CLR 0xfffffff7 + #define PM_GRAFX_MEMREP_MSB 3 + #define PM_GRAFX_MEMREP_LSB 3 + #define PM_GRAFX_ISPOW_BITS 2:2 + #define PM_GRAFX_ISPOW_SET 0x00000004 + #define PM_GRAFX_ISPOW_CLR 0xfffffffb + #define PM_GRAFX_ISPOW_MSB 2 + #define PM_GRAFX_ISPOW_LSB 2 + #define PM_GRAFX_POWOK_BITS 1:1 + #define PM_GRAFX_POWOK_SET 0x00000002 + #define PM_GRAFX_POWOK_CLR 0xfffffffd + #define PM_GRAFX_POWOK_MSB 1 + #define PM_GRAFX_POWOK_LSB 1 + #define PM_GRAFX_POWUP_BITS 0:0 + #define PM_GRAFX_POWUP_SET 0x00000001 + #define PM_GRAFX_POWUP_CLR 0xfffffffe + #define PM_GRAFX_POWUP_MSB 0 + #define PM_GRAFX_POWUP_LSB 0 +#define PM_PROC HW_REGISTER_RW( 0x7e100110 ) + #define PM_PROC_MASK 0x007f107f + #define PM_PROC_WIDTH 23 + #define PM_PROC_RESET 0000000000 + #define PM_PROC_CFG_BITS 22:16 + #define PM_PROC_CFG_SET 0x007f0000 + #define PM_PROC_CFG_CLR 0xff80ffff + #define PM_PROC_CFG_MSB 22 + #define PM_PROC_CFG_LSB 16 + #define PM_PROC_ENAB_BITS 12:12 + #define PM_PROC_ENAB_SET 0x00001000 + #define PM_PROC_ENAB_CLR 0xffffefff + #define PM_PROC_ENAB_MSB 12 + #define PM_PROC_ENAB_LSB 12 + #define PM_PROC_ARMRSTN_BITS 6:6 + #define PM_PROC_ARMRSTN_SET 0x00000040 + #define PM_PROC_ARMRSTN_CLR 0xffffffbf + #define PM_PROC_ARMRSTN_MSB 6 + #define PM_PROC_ARMRSTN_LSB 6 + #define PM_PROC_ISFUNC_BITS 5:5 + #define PM_PROC_ISFUNC_SET 0x00000020 + #define PM_PROC_ISFUNC_CLR 0xffffffdf + #define PM_PROC_ISFUNC_MSB 5 + #define PM_PROC_ISFUNC_LSB 5 + #define PM_PROC_MRDONE_BITS 4:4 + #define PM_PROC_MRDONE_SET 0x00000010 + #define PM_PROC_MRDONE_CLR 0xffffffef + #define PM_PROC_MRDONE_MSB 4 + #define PM_PROC_MRDONE_LSB 4 + #define PM_PROC_MEMREP_BITS 3:3 + #define PM_PROC_MEMREP_SET 0x00000008 + #define PM_PROC_MEMREP_CLR 0xfffffff7 + #define PM_PROC_MEMREP_MSB 3 + #define PM_PROC_MEMREP_LSB 3 + #define PM_PROC_ISPOW_BITS 2:2 + #define PM_PROC_ISPOW_SET 0x00000004 + #define PM_PROC_ISPOW_CLR 0xfffffffb + #define PM_PROC_ISPOW_MSB 2 + #define PM_PROC_ISPOW_LSB 2 + #define PM_PROC_POWOK_BITS 1:1 + #define PM_PROC_POWOK_SET 0x00000002 + #define PM_PROC_POWOK_CLR 0xfffffffd + #define PM_PROC_POWOK_MSB 1 + #define PM_PROC_POWOK_LSB 1 + #define PM_PROC_POWUP_BITS 0:0 + #define PM_PROC_POWUP_SET 0x00000001 + #define PM_PROC_POWUP_CLR 0xfffffffe + #define PM_PROC_POWUP_MSB 0 + #define PM_PROC_POWUP_LSB 0 +#define PM_RSTC HW_REGISTER_RW( 0x7e10001c ) + #define PM_RSTC_MASK 0x00333333 + #define PM_RSTC_WIDTH 22 + #define PM_RSTC_RESET 0x00000102 + #define PM_RSTC_HRCFG_BITS 21:20 + #define PM_RSTC_HRCFG_SET 0x00300000 + #define PM_RSTC_HRCFG_CLR 0xffcfffff + #define PM_RSTC_HRCFG_MSB 21 + #define PM_RSTC_HRCFG_LSB 20 + #define PM_RSTC_FRCFG_BITS 17:16 + #define PM_RSTC_FRCFG_SET 0x00030000 + #define PM_RSTC_FRCFG_CLR 0xfffcffff + #define PM_RSTC_FRCFG_MSB 17 + #define PM_RSTC_FRCFG_LSB 16 + #define PM_RSTC_QRCFG_BITS 13:12 + #define PM_RSTC_QRCFG_SET 0x00003000 + #define PM_RSTC_QRCFG_CLR 0xffffcfff + #define PM_RSTC_QRCFG_MSB 13 + #define PM_RSTC_QRCFG_LSB 12 + #define PM_RSTC_SRCFG_BITS 9:8 + #define PM_RSTC_SRCFG_SET 0x00000300 + #define PM_RSTC_SRCFG_CLR 0xfffffcff + #define PM_RSTC_SRCFG_MSB 9 + #define PM_RSTC_SRCFG_LSB 8 + #define PM_RSTC_WRCFG_BITS 5:4 + #define PM_RSTC_WRCFG_SET 0x00000030 + #define PM_RSTC_WRCFG_CLR 0xffffffcf + #define PM_RSTC_WRCFG_MSB 5 + #define PM_RSTC_WRCFG_LSB 4 + #define PM_RSTC_DRCFG_BITS 1:0 + #define PM_RSTC_DRCFG_SET 0x00000003 + #define PM_RSTC_DRCFG_CLR 0xfffffffc + #define PM_RSTC_DRCFG_MSB 1 + #define PM_RSTC_DRCFG_LSB 0 +#define PM_RSTS HW_REGISTER_RW( 0x7e100020 ) + #define PM_RSTS_MASK 0x00001777 + #define PM_RSTS_WIDTH 13 + #define PM_RSTS_RESET 0x00001000 + #define PM_RSTS_HADPOR_BITS 12:12 + #define PM_RSTS_HADPOR_SET 0x00001000 + #define PM_RSTS_HADPOR_CLR 0xffffefff + #define PM_RSTS_HADPOR_MSB 12 + #define PM_RSTS_HADPOR_LSB 12 + #define PM_RSTS_HADSRH_BITS 10:10 + #define PM_RSTS_HADSRH_SET 0x00000400 + #define PM_RSTS_HADSRH_CLR 0xfffffbff + #define PM_RSTS_HADSRH_MSB 10 + #define PM_RSTS_HADSRH_LSB 10 + #define PM_RSTS_HADSRF_BITS 9:9 + #define PM_RSTS_HADSRF_SET 0x00000200 + #define PM_RSTS_HADSRF_CLR 0xfffffdff + #define PM_RSTS_HADSRF_MSB 9 + #define PM_RSTS_HADSRF_LSB 9 + #define PM_RSTS_HADSRQ_BITS 8:8 + #define PM_RSTS_HADSRQ_SET 0x00000100 + #define PM_RSTS_HADSRQ_CLR 0xfffffeff + #define PM_RSTS_HADSRQ_MSB 8 + #define PM_RSTS_HADSRQ_LSB 8 + #define PM_RSTS_HADWRH_BITS 6:6 + #define PM_RSTS_HADWRH_SET 0x00000040 + #define PM_RSTS_HADWRH_CLR 0xffffffbf + #define PM_RSTS_HADWRH_MSB 6 + #define PM_RSTS_HADWRH_LSB 6 + #define PM_RSTS_HADWRF_BITS 5:5 + #define PM_RSTS_HADWRF_SET 0x00000020 + #define PM_RSTS_HADWRF_CLR 0xffffffdf + #define PM_RSTS_HADWRF_MSB 5 + #define PM_RSTS_HADWRF_LSB 5 + #define PM_RSTS_HADWRQ_BITS 4:4 + #define PM_RSTS_HADWRQ_SET 0x00000010 + #define PM_RSTS_HADWRQ_CLR 0xffffffef + #define PM_RSTS_HADWRQ_MSB 4 + #define PM_RSTS_HADWRQ_LSB 4 + #define PM_RSTS_HADDRH_BITS 2:2 + #define PM_RSTS_HADDRH_SET 0x00000004 + #define PM_RSTS_HADDRH_CLR 0xfffffffb + #define PM_RSTS_HADDRH_MSB 2 + #define PM_RSTS_HADDRH_LSB 2 + #define PM_RSTS_HADDRF_BITS 1:1 + #define PM_RSTS_HADDRF_SET 0x00000002 + #define PM_RSTS_HADDRF_CLR 0xfffffffd + #define PM_RSTS_HADDRF_MSB 1 + #define PM_RSTS_HADDRF_LSB 1 + #define PM_RSTS_HADDRQ_BITS 0:0 + #define PM_RSTS_HADDRQ_SET 0x00000001 + #define PM_RSTS_HADDRQ_CLR 0xfffffffe + #define PM_RSTS_HADDRQ_MSB 0 + #define PM_RSTS_HADDRQ_LSB 0 +#define PM_WDOG HW_REGISTER_RW( 0x7e100024 ) + #define PM_WDOG_MASK 0x000fffff + #define PM_WDOG_WIDTH 20 + #define PM_WDOG_RESET 0000000000 + #define PM_WDOG_TIME_BITS 19:0 + #define PM_WDOG_TIME_SET 0x000fffff + #define PM_WDOG_TIME_CLR 0xfff00000 + #define PM_WDOG_TIME_MSB 19 + #define PM_WDOG_TIME_LSB 0 +#define PM_PADS0 HW_REGISTER_RW( 0x7e100028 ) + #define PM_PADS0_MASK 0x0000003f + #define PM_PADS0_WIDTH 6 + #define PM_PADS0_RESET 0x0000001b + #define PM_PADS0_DRIVE_BITS 2:0 + #define PM_PADS0_DRIVE_SET 0x00000007 + #define PM_PADS0_DRIVE_CLR 0xfffffff8 + #define PM_PADS0_DRIVE_MSB 2 + #define PM_PADS0_DRIVE_LSB 0 + #define PM_PADS0_HYST_BITS 3:3 + #define PM_PADS0_HYST_SET 0x00000008 + #define PM_PADS0_HYST_CLR 0xfffffff7 + #define PM_PADS0_HYST_MSB 3 + #define PM_PADS0_HYST_LSB 3 + #define PM_PADS0_SLEW_BITS 4:4 + #define PM_PADS0_SLEW_SET 0x00000010 + #define PM_PADS0_SLEW_CLR 0xffffffef + #define PM_PADS0_SLEW_MSB 4 + #define PM_PADS0_SLEW_LSB 4 + #define PM_PADS0_POWOK_BITS 5:5 + #define PM_PADS0_POWOK_SET 0x00000020 + #define PM_PADS0_POWOK_CLR 0xffffffdf + #define PM_PADS0_POWOK_MSB 5 + #define PM_PADS0_POWOK_LSB 5 +#define PM_PADS2 HW_REGISTER_RW( 0x7e10002c ) + #define PM_PADS2_MASK 0x0000003f + #define PM_PADS2_WIDTH 6 + #define PM_PADS2_RESET 0x0000001b + #define PM_PADS2_DRIVE_BITS 2:0 + #define PM_PADS2_DRIVE_SET 0x00000007 + #define PM_PADS2_DRIVE_CLR 0xfffffff8 + #define PM_PADS2_DRIVE_MSB 2 + #define PM_PADS2_DRIVE_LSB 0 + #define PM_PADS2_HYST_BITS 3:3 + #define PM_PADS2_HYST_SET 0x00000008 + #define PM_PADS2_HYST_CLR 0xfffffff7 + #define PM_PADS2_HYST_MSB 3 + #define PM_PADS2_HYST_LSB 3 + #define PM_PADS2_SLEW_BITS 4:4 + #define PM_PADS2_SLEW_SET 0x00000010 + #define PM_PADS2_SLEW_CLR 0xffffffef + #define PM_PADS2_SLEW_MSB 4 + #define PM_PADS2_SLEW_LSB 4 + #define PM_PADS2_POWOK_BITS 5:5 + #define PM_PADS2_POWOK_SET 0x00000020 + #define PM_PADS2_POWOK_CLR 0xffffffdf + #define PM_PADS2_POWOK_MSB 5 + #define PM_PADS2_POWOK_LSB 5 +#define PM_PADS3 HW_REGISTER_RW( 0x7e100030 ) + #define PM_PADS3_MASK 0x0000003f + #define PM_PADS3_WIDTH 6 + #define PM_PADS3_RESET 0x0000001b + #define PM_PADS3_DRIVE_BITS 2:0 + #define PM_PADS3_DRIVE_SET 0x00000007 + #define PM_PADS3_DRIVE_CLR 0xfffffff8 + #define PM_PADS3_DRIVE_MSB 2 + #define PM_PADS3_DRIVE_LSB 0 + #define PM_PADS3_HYST_BITS 3:3 + #define PM_PADS3_HYST_SET 0x00000008 + #define PM_PADS3_HYST_CLR 0xfffffff7 + #define PM_PADS3_HYST_MSB 3 + #define PM_PADS3_HYST_LSB 3 + #define PM_PADS3_SLEW_BITS 4:4 + #define PM_PADS3_SLEW_SET 0x00000010 + #define PM_PADS3_SLEW_CLR 0xffffffef + #define PM_PADS3_SLEW_MSB 4 + #define PM_PADS3_SLEW_LSB 4 + #define PM_PADS3_POWOK_BITS 5:5 + #define PM_PADS3_POWOK_SET 0x00000020 + #define PM_PADS3_POWOK_CLR 0xffffffdf + #define PM_PADS3_POWOK_MSB 5 + #define PM_PADS3_POWOK_LSB 5 +#define PM_PADS4 HW_REGISTER_RW( 0x7e100034 ) + #define PM_PADS4_MASK 0x0000003f + #define PM_PADS4_WIDTH 6 + #define PM_PADS4_RESET 0x0000001b + #define PM_PADS4_DRIVE_BITS 2:0 + #define PM_PADS4_DRIVE_SET 0x00000007 + #define PM_PADS4_DRIVE_CLR 0xfffffff8 + #define PM_PADS4_DRIVE_MSB 2 + #define PM_PADS4_DRIVE_LSB 0 + #define PM_PADS4_HYST_BITS 3:3 + #define PM_PADS4_HYST_SET 0x00000008 + #define PM_PADS4_HYST_CLR 0xfffffff7 + #define PM_PADS4_HYST_MSB 3 + #define PM_PADS4_HYST_LSB 3 + #define PM_PADS4_SPARE_BITS 4:4 + #define PM_PADS4_SPARE_SET 0x00000010 + #define PM_PADS4_SPARE_CLR 0xffffffef + #define PM_PADS4_SPARE_MSB 4 + #define PM_PADS4_SPARE_LSB 4 + #define PM_PADS4_POWOK_BITS 5:5 + #define PM_PADS4_POWOK_SET 0x00000020 + #define PM_PADS4_POWOK_CLR 0xffffffdf + #define PM_PADS4_POWOK_MSB 5 + #define PM_PADS4_POWOK_LSB 5 +#define PM_PADS5 HW_REGISTER_RW( 0x7e100038 ) + #define PM_PADS5_MASK 0x0000007f + #define PM_PADS5_WIDTH 7 + #define PM_PADS5_RESET 0x0000001b + #define PM_PADS5_DRIVE_BITS 2:0 + #define PM_PADS5_DRIVE_SET 0x00000007 + #define PM_PADS5_DRIVE_CLR 0xfffffff8 + #define PM_PADS5_DRIVE_MSB 2 + #define PM_PADS5_DRIVE_LSB 0 + #define PM_PADS5_HYST_BITS 3:3 + #define PM_PADS5_HYST_SET 0x00000008 + #define PM_PADS5_HYST_CLR 0xfffffff7 + #define PM_PADS5_HYST_MSB 3 + #define PM_PADS5_HYST_LSB 3 + #define PM_PADS5_SLEW_BITS 4:4 + #define PM_PADS5_SLEW_SET 0x00000010 + #define PM_PADS5_SLEW_CLR 0xffffffef + #define PM_PADS5_SLEW_MSB 4 + #define PM_PADS5_SLEW_LSB 4 + #define PM_PADS5_POWOK_BITS 5:5 + #define PM_PADS5_POWOK_SET 0x00000020 + #define PM_PADS5_POWOK_CLR 0xffffffdf + #define PM_PADS5_POWOK_MSB 5 + #define PM_PADS5_POWOK_LSB 5 + #define PM_PADS5_I2CMODE_BITS 6:6 + #define PM_PADS5_I2CMODE_SET 0x00000040 + #define PM_PADS5_I2CMODE_CLR 0xffffffbf + #define PM_PADS5_I2CMODE_MSB 6 + #define PM_PADS5_I2CMODE_LSB 6 +#define PM_PADS6 HW_REGISTER_RW( 0x7e10003c ) + #define PM_PADS6_MASK 0x00000123 + #define PM_PADS6_WIDTH 9 + #define PM_PADS6_RESET 0000000000 + #define PM_PADS6_DRIVE_BITS 1:0 + #define PM_PADS6_DRIVE_SET 0x00000003 + #define PM_PADS6_DRIVE_CLR 0xfffffffc + #define PM_PADS6_DRIVE_MSB 1 + #define PM_PADS6_DRIVE_LSB 0 + #define PM_PADS6_POWOK_BITS 5:5 + #define PM_PADS6_POWOK_SET 0x00000020 + #define PM_PADS6_POWOK_CLR 0xffffffdf + #define PM_PADS6_POWOK_MSB 5 + #define PM_PADS6_POWOK_LSB 5 + #define PM_PADS6_PD_BITS 8:8 + #define PM_PADS6_PD_SET 0x00000100 + #define PM_PADS6_PD_CLR 0xfffffeff + #define PM_PADS6_PD_MSB 8 + #define PM_PADS6_PD_LSB 8 +#define PM_CAM0 HW_REGISTER_RW( 0x7e100044 ) + #define PM_CAM0_MASK 0x001fffff + #define PM_CAM0_WIDTH 21 + #define PM_CAM0_RESET 0000000000 + #define PM_CAM0_CTRLEN_BITS 0:0 + #define PM_CAM0_CTRLEN_SET 0x00000001 + #define PM_CAM0_CTRLEN_CLR 0xfffffffe + #define PM_CAM0_CTRLEN_MSB 0 + #define PM_CAM0_CTRLEN_LSB 0 + #define PM_CAM0_LDOLPEN_BITS 1:1 + #define PM_CAM0_LDOLPEN_SET 0x00000002 + #define PM_CAM0_LDOLPEN_CLR 0xfffffffd + #define PM_CAM0_LDOLPEN_MSB 1 + #define PM_CAM0_LDOLPEN_LSB 1 + #define PM_CAM0_LDOHPEN_BITS 2:2 + #define PM_CAM0_LDOHPEN_SET 0x00000004 + #define PM_CAM0_LDOHPEN_CLR 0xfffffffb + #define PM_CAM0_LDOHPEN_MSB 2 + #define PM_CAM0_LDOHPEN_LSB 2 + #define PM_CAM0_LDOCTRL_BITS 20:3 + #define PM_CAM0_LDOCTRL_SET 0x001ffff8 + #define PM_CAM0_LDOCTRL_CLR 0xffe00007 + #define PM_CAM0_LDOCTRL_MSB 20 + #define PM_CAM0_LDOCTRL_LSB 3 +#define PM_CAM1 HW_REGISTER_RW( 0x7e100048 ) + #define PM_CAM1_MASK 0x001fffff + #define PM_CAM1_WIDTH 21 + #define PM_CAM1_RESET 0000000000 + #define PM_CAM1_CTRLEN_BITS 0:0 + #define PM_CAM1_CTRLEN_SET 0x00000001 + #define PM_CAM1_CTRLEN_CLR 0xfffffffe + #define PM_CAM1_CTRLEN_MSB 0 + #define PM_CAM1_CTRLEN_LSB 0 + #define PM_CAM1_LDOLPEN_BITS 1:1 + #define PM_CAM1_LDOLPEN_SET 0x00000002 + #define PM_CAM1_LDOLPEN_CLR 0xfffffffd + #define PM_CAM1_LDOLPEN_MSB 1 + #define PM_CAM1_LDOLPEN_LSB 1 + #define PM_CAM1_LDOHPEN_BITS 2:2 + #define PM_CAM1_LDOHPEN_SET 0x00000004 + #define PM_CAM1_LDOHPEN_CLR 0xfffffffb + #define PM_CAM1_LDOHPEN_MSB 2 + #define PM_CAM1_LDOHPEN_LSB 2 + #define PM_CAM1_LDOCTRL_BITS 20:3 + #define PM_CAM1_LDOCTRL_SET 0x001ffff8 + #define PM_CAM1_LDOCTRL_CLR 0xffe00007 + #define PM_CAM1_LDOCTRL_MSB 20 + #define PM_CAM1_LDOCTRL_LSB 3 +#define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c ) + #define PM_CCP2TX_MASK 0x0007ffff + #define PM_CCP2TX_WIDTH 19 + #define PM_CCP2TX_RESET 0000000000 + #define PM_CCP2TX_CTRLEN_BITS 0:0 + #define PM_CCP2TX_CTRLEN_SET 0x00000001 + #define PM_CCP2TX_CTRLEN_CLR 0xfffffffe + #define PM_CCP2TX_CTRLEN_MSB 0 + #define PM_CCP2TX_CTRLEN_LSB 0 + #define PM_CCP2TX_LDOEN_BITS 1:1 + #define PM_CCP2TX_LDOEN_SET 0x00000002 + #define PM_CCP2TX_LDOEN_CLR 0xfffffffd + #define PM_CCP2TX_LDOEN_MSB 1 + #define PM_CCP2TX_LDOEN_LSB 1 + #define PM_CCP2TX_LDOCTRL_BITS 18:2 + #define PM_CCP2TX_LDOCTRL_SET 0x0007fffc + #define PM_CCP2TX_LDOCTRL_CLR 0xfff80003 + #define PM_CCP2TX_LDOCTRL_MSB 18 + #define PM_CCP2TX_LDOCTRL_LSB 2 +#define PM_DSI0 HW_REGISTER_RW( 0x7e100050 ) + #define PM_DSI0_MASK 0x001fffff + #define PM_DSI0_WIDTH 21 + #define PM_DSI0_RESET 0000000000 + #define PM_DSI0_CTRLEN_BITS 0:0 + #define PM_DSI0_CTRLEN_SET 0x00000001 + #define PM_DSI0_CTRLEN_CLR 0xfffffffe + #define PM_DSI0_CTRLEN_MSB 0 + #define PM_DSI0_CTRLEN_LSB 0 + #define PM_DSI0_LDOLPEN_BITS 1:1 + #define PM_DSI0_LDOLPEN_SET 0x00000002 + #define PM_DSI0_LDOLPEN_CLR 0xfffffffd + #define PM_DSI0_LDOLPEN_MSB 1 + #define PM_DSI0_LDOLPEN_LSB 1 + #define PM_DSI0_LDOHPEN_BITS 2:2 + #define PM_DSI0_LDOHPEN_SET 0x00000004 + #define PM_DSI0_LDOHPEN_CLR 0xfffffffb + #define PM_DSI0_LDOHPEN_MSB 2 + #define PM_DSI0_LDOHPEN_LSB 2 + #define PM_DSI0_LDOCTRL_BITS 20:3 + #define PM_DSI0_LDOCTRL_SET 0x001ffff8 + #define PM_DSI0_LDOCTRL_CLR 0xffe00007 + #define PM_DSI0_LDOCTRL_MSB 20 + #define PM_DSI0_LDOCTRL_LSB 3 +#define PM_DSI1 HW_REGISTER_RW( 0x7e100054 ) + #define PM_DSI1_MASK 0x001fffff + #define PM_DSI1_WIDTH 21 + #define PM_DSI1_RESET 0000000000 + #define PM_DSI1_CTRLEN_BITS 0:0 + #define PM_DSI1_CTRLEN_SET 0x00000001 + #define PM_DSI1_CTRLEN_CLR 0xfffffffe + #define PM_DSI1_CTRLEN_MSB 0 + #define PM_DSI1_CTRLEN_LSB 0 + #define PM_DSI1_LDOLPEN_BITS 1:1 + #define PM_DSI1_LDOLPEN_SET 0x00000002 + #define PM_DSI1_LDOLPEN_CLR 0xfffffffd + #define PM_DSI1_LDOLPEN_MSB 1 + #define PM_DSI1_LDOLPEN_LSB 1 + #define PM_DSI1_LDOHPEN_BITS 2:2 + #define PM_DSI1_LDOHPEN_SET 0x00000004 + #define PM_DSI1_LDOHPEN_CLR 0xfffffffb + #define PM_DSI1_LDOHPEN_MSB 2 + #define PM_DSI1_LDOHPEN_LSB 2 + #define PM_DSI1_LDOCTRL_BITS 20:3 + #define PM_DSI1_LDOCTRL_SET 0x001ffff8 + #define PM_DSI1_LDOCTRL_CLR 0xffe00007 + #define PM_DSI1_LDOCTRL_MSB 20 + #define PM_DSI1_LDOCTRL_LSB 3 +#define PM_HDMI HW_REGISTER_RW( 0x7e100058 ) + #define PM_HDMI_MASK 0x000fffff + #define PM_HDMI_WIDTH 20 + #define PM_HDMI_RESET 0x00080002 + #define PM_HDMI_CTRLEN_BITS 0:0 + #define PM_HDMI_CTRLEN_SET 0x00000001 + #define PM_HDMI_CTRLEN_CLR 0xfffffffe + #define PM_HDMI_CTRLEN_MSB 0 + #define PM_HDMI_CTRLEN_LSB 0 + #define PM_HDMI_LDOPD_BITS 1:1 + #define PM_HDMI_LDOPD_SET 0x00000002 + #define PM_HDMI_LDOPD_CLR 0xfffffffd + #define PM_HDMI_LDOPD_MSB 1 + #define PM_HDMI_LDOPD_LSB 1 + #define PM_HDMI_LDOCTRL_BITS 18:2 + #define PM_HDMI_LDOCTRL_SET 0x0007fffc + #define PM_HDMI_LDOCTRL_CLR 0xfff80003 + #define PM_HDMI_LDOCTRL_MSB 18 + #define PM_HDMI_LDOCTRL_LSB 2 + #define PM_HDMI_RSTDR_BITS 19:19 + #define PM_HDMI_RSTDR_SET 0x00080000 + #define PM_HDMI_RSTDR_CLR 0xfff7ffff + #define PM_HDMI_RSTDR_MSB 19 + #define PM_HDMI_RSTDR_LSB 19 +#define PM_USB HW_REGISTER_RW( 0x7e10005c ) + #define PM_USB_MASK 0x00000001 + #define PM_USB_WIDTH 1 + #define PM_USB_RESET 0000000000 + #define PM_USB_CTRLEN_BITS 0:0 + #define PM_USB_CTRLEN_SET 0x00000001 + #define PM_USB_CTRLEN_CLR 0xfffffffe + #define PM_USB_CTRLEN_MSB 0 + #define PM_USB_CTRLEN_LSB 0 +#define PM_PXLDO HW_REGISTER_RW( 0x7e100060 ) + #define PM_PXLDO_MASK 0x0003ffff + #define PM_PXLDO_WIDTH 18 + #define PM_PXLDO_RESET 0000000000 + #define PM_PXLDO_CTRL_BITS 15:0 + #define PM_PXLDO_CTRL_SET 0x0000ffff + #define PM_PXLDO_CTRL_CLR 0xffff0000 + #define PM_PXLDO_CTRL_MSB 15 + #define PM_PXLDO_CTRL_LSB 0 + #define PM_PXLDO_RSTOSCDR_BITS 16:16 + #define PM_PXLDO_RSTOSCDR_SET 0x00010000 + #define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff + #define PM_PXLDO_RSTOSCDR_MSB 16 + #define PM_PXLDO_RSTOSCDR_LSB 16 + #define PM_PXLDO_RSTPLLDR_BITS 17:17 + #define PM_PXLDO_RSTPLLDR_SET 0x00020000 + #define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff + #define PM_PXLDO_RSTPLLDR_MSB 17 + #define PM_PXLDO_RSTPLLDR_LSB 17 +#define PM_PXBG HW_REGISTER_RW( 0x7e100064 ) + #define PM_PXBG_MASK 0x0000ffff + #define PM_PXBG_WIDTH 16 + #define PM_PXBG_RESET 0000000000 + #define PM_PXBG_CTRL_BITS 15:0 + #define PM_PXBG_CTRL_SET 0x0000ffff + #define PM_PXBG_CTRL_CLR 0xffff0000 + #define PM_PXBG_CTRL_MSB 15 + #define PM_PXBG_CTRL_LSB 0 +#define PM_DFT HW_REGISTER_RW( 0x7e100068 ) + #define PM_DFT_MASK 0x00000003 + #define PM_DFT_WIDTH 2 + #define PM_DFT_RESET 0000000000 + #define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0 + #define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001 + #define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe + #define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0 + #define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0 + #define PM_DFT_STOPALLCLOCKS_BITS 1:1 + #define PM_DFT_STOPALLCLOCKS_SET 0x00000002 + #define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd + #define PM_DFT_STOPALLCLOCKS_MSB 1 + #define PM_DFT_STOPALLCLOCKS_LSB 1 +#define PM_SMPS HW_REGISTER_RW( 0x7e10006c ) + #define PM_SMPS_MASK 0x00000007 + #define PM_SMPS_WIDTH 3 + #define PM_SMPS_RESET 0000000000 + #define PM_SMPS_CTRLEN_BITS 0:0 + #define PM_SMPS_CTRLEN_SET 0x00000001 + #define PM_SMPS_CTRLEN_CLR 0xfffffffe + #define PM_SMPS_CTRLEN_MSB 0 + #define PM_SMPS_CTRLEN_LSB 0 + #define PM_SMPS_RSTDR_BITS 1:1 + #define PM_SMPS_RSTDR_SET 0x00000002 + #define PM_SMPS_RSTDR_CLR 0xfffffffd + #define PM_SMPS_RSTDR_MSB 1 + #define PM_SMPS_RSTDR_LSB 1 + #define PM_SMPS_UPEN_BITS 2:2 + #define PM_SMPS_UPEN_SET 0x00000004 + #define PM_SMPS_UPEN_CLR 0xfffffffb + #define PM_SMPS_UPEN_MSB 2 + #define PM_SMPS_UPEN_LSB 2 +#define PM_XOSC HW_REGISTER_RW( 0x7e100070 ) + #define PM_XOSC_MASK 0x00000001 + #define PM_XOSC_WIDTH 1 + #define PM_XOSC_RESET 0000000000 + #define PM_XOSC_USESEC_BITS 0:0 + #define PM_XOSC_USESEC_SET 0x00000001 + #define PM_XOSC_USESEC_CLR 0xfffffffe + #define PM_XOSC_USESEC_MSB 0 + #define PM_XOSC_USESEC_LSB 0 +#define PM_SPAREW HW_REGISTER_RW( 0x7e100074 ) + #define PM_SPAREW_MASK 0x00ffffff + #define PM_SPAREW_WIDTH 24 + #define PM_SPAREW_RESET 0000000000 + #define PM_SPAREW_SPARE_BITS 23:0 + #define PM_SPAREW_SPARE_SET 0x00ffffff + #define PM_SPAREW_SPARE_CLR 0xff000000 + #define PM_SPAREW_SPARE_MSB 23 + #define PM_SPAREW_SPARE_LSB 0 +#define PM_SPARER HW_REGISTER_RO( 0x7e100078 ) + #define PM_SPARER_MASK 0x00ffffff + #define PM_SPARER_WIDTH 24 + #define PM_SPARER_RESET 0000000000 + #define PM_SPARER_SPARE_BITS 23:0 + #define PM_SPARER_SPARE_SET 0x00ffffff + #define PM_SPARER_SPARE_CLR 0xff000000 + #define PM_SPARER_SPARE_MSB 23 + #define PM_SPARER_SPARE_LSB 0 +#define PM_AVS_RSTDR HW_REGISTER_RW( 0x7e10007c ) + #define PM_AVS_RSTDR_MASK 0x0000003f + #define PM_AVS_RSTDR_WIDTH 6 + #define PM_AVS_RSTDR_RESET 0000000000 + #define PM_AVS_RSTDR_PERI_A_BITS 0:0 + #define PM_AVS_RSTDR_PERI_A_SET 0x00000001 + #define PM_AVS_RSTDR_PERI_A_CLR 0xfffffffe + #define PM_AVS_RSTDR_PERI_A_MSB 0 + #define PM_AVS_RSTDR_PERI_A_LSB 0 + #define PM_AVS_RSTDR_SYSTEM_A_BITS 1:1 + #define PM_AVS_RSTDR_SYSTEM_A_SET 0x00000002 + #define PM_AVS_RSTDR_SYSTEM_A_CLR 0xfffffffd + #define PM_AVS_RSTDR_SYSTEM_A_MSB 1 + #define PM_AVS_RSTDR_SYSTEM_A_LSB 1 + #define PM_AVS_RSTDR_H264_I_BITS 2:2 + #define PM_AVS_RSTDR_H264_I_SET 0x00000004 + #define PM_AVS_RSTDR_H264_I_CLR 0xfffffffb + #define PM_AVS_RSTDR_H264_I_MSB 2 + #define PM_AVS_RSTDR_H264_I_LSB 2 + #define PM_AVS_RSTDR_V3D_G_BITS 3:3 + #define PM_AVS_RSTDR_V3D_G_SET 0x00000008 + #define PM_AVS_RSTDR_V3D_G_CLR 0xfffffff7 + #define PM_AVS_RSTDR_V3D_G_MSB 3 + #define PM_AVS_RSTDR_V3D_G_LSB 3 + #define PM_AVS_RSTDR_ARM_P_BITS 4:4 + #define PM_AVS_RSTDR_ARM_P_SET 0x00000010 + #define PM_AVS_RSTDR_ARM_P_CLR 0xffffffef + #define PM_AVS_RSTDR_ARM_P_MSB 4 + #define PM_AVS_RSTDR_ARM_P_LSB 4 + #define PM_AVS_RSTDR_ROSC_BITS 5:5 + #define PM_AVS_RSTDR_ROSC_SET 0x00000020 + #define PM_AVS_RSTDR_ROSC_CLR 0xffffffdf + #define PM_AVS_RSTDR_ROSC_MSB 5 + #define PM_AVS_RSTDR_ROSC_LSB 5 +#define PM_AVS_STAT HW_REGISTER_RW( 0x7e100080 ) + #define PM_AVS_STAT_MASK 0x0000001f + #define PM_AVS_STAT_WIDTH 5 + #define PM_AVS_STAT_RESET 0000000000 + #define PM_AVS_STAT_ALERT_PERI_A_BITS 0:0 + #define PM_AVS_STAT_ALERT_PERI_A_SET 0x00000001 + #define PM_AVS_STAT_ALERT_PERI_A_CLR 0xfffffffe + #define PM_AVS_STAT_ALERT_PERI_A_MSB 0 + #define PM_AVS_STAT_ALERT_PERI_A_LSB 0 + #define PM_AVS_STAT_ALERT_SYSTEM_A_BITS 1:1 + #define PM_AVS_STAT_ALERT_SYSTEM_A_SET 0x00000002 + #define PM_AVS_STAT_ALERT_SYSTEM_A_CLR 0xfffffffd + #define PM_AVS_STAT_ALERT_SYSTEM_A_MSB 1 + #define PM_AVS_STAT_ALERT_SYSTEM_A_LSB 1 + #define PM_AVS_STAT_ALERT_H264_I_BITS 2:2 + #define PM_AVS_STAT_ALERT_H264_I_SET 0x00000004 + #define PM_AVS_STAT_ALERT_H264_I_CLR 0xfffffffb + #define PM_AVS_STAT_ALERT_H264_I_MSB 2 + #define PM_AVS_STAT_ALERT_H264_I_LSB 2 + #define PM_AVS_STAT_ALERT_V3D_G_BITS 3:3 + #define PM_AVS_STAT_ALERT_V3D_G_SET 0x00000008 + #define PM_AVS_STAT_ALERT_V3D_G_CLR 0xfffffff7 + #define PM_AVS_STAT_ALERT_V3D_G_MSB 3 + #define PM_AVS_STAT_ALERT_V3D_G_LSB 3 + #define PM_AVS_STAT_ALERT_ARM_P_BITS 4:4 + #define PM_AVS_STAT_ALERT_ARM_P_SET 0x00000010 + #define PM_AVS_STAT_ALERT_ARM_P_CLR 0xffffffef + #define PM_AVS_STAT_ALERT_ARM_P_MSB 4 + #define PM_AVS_STAT_ALERT_ARM_P_LSB 4 +#define PM_AVS_EVENT HW_REGISTER_RW( 0x7e100084 ) + #define PM_AVS_EVENT_MASK 0x0000001f + #define PM_AVS_EVENT_WIDTH 5 + #define PM_AVS_EVENT_RESET 0000000000 + #define PM_AVS_EVENT_ALERT_PERI_A_BITS 0:0 + #define PM_AVS_EVENT_ALERT_PERI_A_SET 0x00000001 + #define PM_AVS_EVENT_ALERT_PERI_A_CLR 0xfffffffe + #define PM_AVS_EVENT_ALERT_PERI_A_MSB 0 + #define PM_AVS_EVENT_ALERT_PERI_A_LSB 0 + #define PM_AVS_EVENT_ALERT_SYSTEM_A_BITS 1:1 + #define PM_AVS_EVENT_ALERT_SYSTEM_A_SET 0x00000002 + #define PM_AVS_EVENT_ALERT_SYSTEM_A_CLR 0xfffffffd + #define PM_AVS_EVENT_ALERT_SYSTEM_A_MSB 1 + #define PM_AVS_EVENT_ALERT_SYSTEM_A_LSB 1 + #define PM_AVS_EVENT_ALERT_H264_I_BITS 2:2 + #define PM_AVS_EVENT_ALERT_H264_I_SET 0x00000004 + #define PM_AVS_EVENT_ALERT_H264_I_CLR 0xfffffffb + #define PM_AVS_EVENT_ALERT_H264_I_MSB 2 + #define PM_AVS_EVENT_ALERT_H264_I_LSB 2 + #define PM_AVS_EVENT_ALERT_V3D_G_BITS 3:3 + #define PM_AVS_EVENT_ALERT_V3D_G_SET 0x00000008 + #define PM_AVS_EVENT_ALERT_V3D_G_CLR 0xfffffff7 + #define PM_AVS_EVENT_ALERT_V3D_G_MSB 3 + #define PM_AVS_EVENT_ALERT_V3D_G_LSB 3 + #define PM_AVS_EVENT_ALERT_ARM_P_BITS 4:4 + #define PM_AVS_EVENT_ALERT_ARM_P_SET 0x00000010 + #define PM_AVS_EVENT_ALERT_ARM_P_CLR 0xffffffef + #define PM_AVS_EVENT_ALERT_ARM_P_MSB 4 + #define PM_AVS_EVENT_ALERT_ARM_P_LSB 4 +#define PM_AVS_INTEN HW_REGISTER_RW( 0x7e100088 ) + #define PM_AVS_INTEN_MASK 0x0000001f + #define PM_AVS_INTEN_WIDTH 5 + #define PM_AVS_INTEN_RESET 0000000000 + #define PM_AVS_INTEN_ALERT_PERI_A_BITS 0:0 + #define PM_AVS_INTEN_ALERT_PERI_A_SET 0x00000001 + #define PM_AVS_INTEN_ALERT_PERI_A_CLR 0xfffffffe + #define PM_AVS_INTEN_ALERT_PERI_A_MSB 0 + #define PM_AVS_INTEN_ALERT_PERI_A_LSB 0 + #define PM_AVS_INTEN_ALERT_SYSTEM_A_BITS 1:1 + #define PM_AVS_INTEN_ALERT_SYSTEM_A_SET 0x00000002 + #define PM_AVS_INTEN_ALERT_SYSTEM_A_CLR 0xfffffffd + #define PM_AVS_INTEN_ALERT_SYSTEM_A_MSB 1 + #define PM_AVS_INTEN_ALERT_SYSTEM_A_LSB 1 + #define PM_AVS_INTEN_ALERT_H264_I_BITS 2:2 + #define PM_AVS_INTEN_ALERT_H264_I_SET 0x00000004 + #define PM_AVS_INTEN_ALERT_H264_I_CLR 0xfffffffb + #define PM_AVS_INTEN_ALERT_H264_I_MSB 2 + #define PM_AVS_INTEN_ALERT_H264_I_LSB 2 + #define PM_AVS_INTEN_ALERT_V3D_G_BITS 3:3 + #define PM_AVS_INTEN_ALERT_V3D_G_SET 0x00000008 + #define PM_AVS_INTEN_ALERT_V3D_G_CLR 0xfffffff7 + #define PM_AVS_INTEN_ALERT_V3D_G_MSB 3 + #define PM_AVS_INTEN_ALERT_V3D_G_LSB 3 + #define PM_AVS_INTEN_ALERT_ARM_P_BITS 4:4 + #define PM_AVS_INTEN_ALERT_ARM_P_SET 0x00000010 + #define PM_AVS_INTEN_ALERT_ARM_P_CLR 0xffffffef + #define PM_AVS_INTEN_ALERT_ARM_P_MSB 4 + #define PM_AVS_INTEN_ALERT_ARM_P_LSB 4 +#define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc ) + #define PM_DUMMY_MASK 0x00000001 + #define PM_DUMMY_WIDTH 1 + #define PM_DUMMY_RESET 0x00000001 + #define PM_DUMMY_ONE_BITS 0:0 + #define PM_DUMMY_ONE_SET 0x00000001 + #define PM_DUMMY_ONE_CLR 0xfffffffe + #define PM_DUMMY_ONE_MSB 0 + #define PM_DUMMY_ONE_LSB 0 diff --git a/bcm2708_chip/cpr_powman_a0.h b/bcm2708_chip/cpr_powman_a0.h new file mode 100755 index 0000000..c52af0b --- /dev/null +++ b/bcm2708_chip/cpr_powman_a0.h @@ -0,0 +1,809 @@ +// This file was generated by the create_regs script +#define PM_PASSWORD 0x5a000000 +#define PM_BASE 0x7e100000 +#define PM_APB_ID 0x0000706d +#define PM_GNRIC HW_REGISTER_RW( 0x7e100000 ) + #define PM_GNRIC_MASK 0x007f0fff + #define PM_GNRIC_WIDTH 23 + #define PM_GNRIC_RESET 0000000000 + #define PM_GNRIC_CFG_BITS 22:16 + #define PM_GNRIC_CFG_SET 0x007f0000 + #define PM_GNRIC_CFG_CLR 0xff80ffff + #define PM_GNRIC_CFG_MSB 22 + #define PM_GNRIC_CFG_LSB 16 + #define PM_GNRIC_RSTN_BITS 11:6 + #define PM_GNRIC_RSTN_SET 0x00000fc0 + #define PM_GNRIC_RSTN_CLR 0xfffff03f + #define PM_GNRIC_RSTN_MSB 11 + #define PM_GNRIC_RSTN_LSB 6 + #define PM_GNRIC_ISFUNC_BITS 5:5 + #define PM_GNRIC_ISFUNC_SET 0x00000020 + #define PM_GNRIC_ISFUNC_CLR 0xffffffdf + #define PM_GNRIC_ISFUNC_MSB 5 + #define PM_GNRIC_ISFUNC_LSB 5 + #define PM_GNRIC_MRDONE_BITS 4:4 + #define PM_GNRIC_MRDONE_SET 0x00000010 + #define PM_GNRIC_MRDONE_CLR 0xffffffef + #define PM_GNRIC_MRDONE_MSB 4 + #define PM_GNRIC_MRDONE_LSB 4 + #define PM_GNRIC_MEMREP_BITS 3:3 + #define PM_GNRIC_MEMREP_SET 0x00000008 + #define PM_GNRIC_MEMREP_CLR 0xfffffff7 + #define PM_GNRIC_MEMREP_MSB 3 + #define PM_GNRIC_MEMREP_LSB 3 + #define PM_GNRIC_ISPOW_BITS 2:2 + #define PM_GNRIC_ISPOW_SET 0x00000004 + #define PM_GNRIC_ISPOW_CLR 0xfffffffb + #define PM_GNRIC_ISPOW_MSB 2 + #define PM_GNRIC_ISPOW_LSB 2 + #define PM_GNRIC_POWOK_BITS 1:1 + #define PM_GNRIC_POWOK_SET 0x00000002 + #define PM_GNRIC_POWOK_CLR 0xfffffffd + #define PM_GNRIC_POWOK_MSB 1 + #define PM_GNRIC_POWOK_LSB 1 + #define PM_GNRIC_POWUP_BITS 0:0 + #define PM_GNRIC_POWUP_SET 0x00000001 + #define PM_GNRIC_POWUP_CLR 0xfffffffe + #define PM_GNRIC_POWUP_MSB 0 + #define PM_GNRIC_POWUP_LSB 0 +#define PM_AUDIO HW_REGISTER_RW( 0x7e100004 ) + #define PM_AUDIO_MASK 0x000101ff + #define PM_AUDIO_WIDTH 17 + #define PM_AUDIO_RESET 0x00010000 + #define PM_AUDIO_RSTN_BITS 16:16 + #define PM_AUDIO_RSTN_SET 0x00010000 + #define PM_AUDIO_RSTN_CLR 0xfffeffff + #define PM_AUDIO_RSTN_MSB 16 + #define PM_AUDIO_RSTN_LSB 16 + #define PM_AUDIO_CTRLEN_BITS 8:8 + #define PM_AUDIO_CTRLEN_SET 0x00000100 + #define PM_AUDIO_CTRLEN_CLR 0xfffffeff + #define PM_AUDIO_CTRLEN_MSB 8 + #define PM_AUDIO_CTRLEN_LSB 8 + #define PM_AUDIO_APSM_BITS 7:0 + #define PM_AUDIO_APSM_SET 0x000000ff + #define PM_AUDIO_APSM_CLR 0xffffff00 + #define PM_AUDIO_APSM_MSB 7 + #define PM_AUDIO_APSM_LSB 0 +#define PM_OLDIMAGE HW_REGISTER_RW( 0x7e100008 ) + #define PM_OLDIMAGE_MASK 0x007f007f + #define PM_OLDIMAGE_WIDTH 23 + #define PM_OLDIMAGE_RESET 0000000000 + #define PM_OLDIMAGE_CFG_BITS 22:16 + #define PM_OLDIMAGE_CFG_SET 0x007f0000 + #define PM_OLDIMAGE_CFG_CLR 0xff80ffff + #define PM_OLDIMAGE_CFG_MSB 22 + #define PM_OLDIMAGE_CFG_LSB 16 + #define PM_OLDIMAGE_ISPRSTN_BITS 6:6 + #define PM_OLDIMAGE_ISPRSTN_SET 0x00000040 + #define PM_OLDIMAGE_ISPRSTN_CLR 0xffffffbf + #define PM_OLDIMAGE_ISPRSTN_MSB 6 + #define PM_OLDIMAGE_ISPRSTN_LSB 6 + #define PM_OLDIMAGE_H264RSTN_BITS 5:5 + #define PM_OLDIMAGE_H264RSTN_SET 0x00000020 + #define PM_OLDIMAGE_H264RSTN_CLR 0xffffffdf + #define PM_OLDIMAGE_H264RSTN_MSB 5 + #define PM_OLDIMAGE_H264RSTN_LSB 5 + #define PM_OLDIMAGE_PERIRSTN_BITS 4:4 + #define PM_OLDIMAGE_PERIRSTN_SET 0x00000010 + #define PM_OLDIMAGE_PERIRSTN_CLR 0xffffffef + #define PM_OLDIMAGE_PERIRSTN_MSB 4 + #define PM_OLDIMAGE_PERIRSTN_LSB 4 + #define PM_OLDIMAGE_ISFUNC_BITS 3:3 + #define PM_OLDIMAGE_ISFUNC_SET 0x00000008 + #define PM_OLDIMAGE_ISFUNC_CLR 0xfffffff7 + #define PM_OLDIMAGE_ISFUNC_MSB 3 + #define PM_OLDIMAGE_ISFUNC_LSB 3 + #define PM_OLDIMAGE_ISPOW_BITS 2:2 + #define PM_OLDIMAGE_ISPOW_SET 0x00000004 + #define PM_OLDIMAGE_ISPOW_CLR 0xfffffffb + #define PM_OLDIMAGE_ISPOW_MSB 2 + #define PM_OLDIMAGE_ISPOW_LSB 2 + #define PM_OLDIMAGE_POWOK_BITS 1:1 + #define PM_OLDIMAGE_POWOK_SET 0x00000002 + #define PM_OLDIMAGE_POWOK_CLR 0xfffffffd + #define PM_OLDIMAGE_POWOK_MSB 1 + #define PM_OLDIMAGE_POWOK_LSB 1 + #define PM_OLDIMAGE_POWUP_BITS 0:0 + #define PM_OLDIMAGE_POWUP_SET 0x00000001 + #define PM_OLDIMAGE_POWUP_CLR 0xfffffffe + #define PM_OLDIMAGE_POWUP_MSB 0 + #define PM_OLDIMAGE_POWUP_LSB 0 +#define PM_OLDGRAFX HW_REGISTER_RW( 0x7e10000c ) + #define PM_OLDGRAFX_MASK 0x007f008f + #define PM_OLDGRAFX_WIDTH 23 + #define PM_OLDGRAFX_RESET 0000000000 + #define PM_OLDGRAFX_CFG_BITS 22:16 + #define PM_OLDGRAFX_CFG_SET 0x007f0000 + #define PM_OLDGRAFX_CFG_CLR 0xff80ffff + #define PM_OLDGRAFX_CFG_MSB 22 + #define PM_OLDGRAFX_CFG_LSB 16 + #define PM_OLDGRAFX_V3DRSTN_BITS 7:7 + #define PM_OLDGRAFX_V3DRSTN_SET 0x00000080 + #define PM_OLDGRAFX_V3DRSTN_CLR 0xffffff7f + #define PM_OLDGRAFX_V3DRSTN_MSB 7 + #define PM_OLDGRAFX_V3DRSTN_LSB 7 + #define PM_OLDGRAFX_ISFUNC_BITS 3:3 + #define PM_OLDGRAFX_ISFUNC_SET 0x00000008 + #define PM_OLDGRAFX_ISFUNC_CLR 0xfffffff7 + #define PM_OLDGRAFX_ISFUNC_MSB 3 + #define PM_OLDGRAFX_ISFUNC_LSB 3 + #define PM_OLDGRAFX_ISPOW_BITS 2:2 + #define PM_OLDGRAFX_ISPOW_SET 0x00000004 + #define PM_OLDGRAFX_ISPOW_CLR 0xfffffffb + #define PM_OLDGRAFX_ISPOW_MSB 2 + #define PM_OLDGRAFX_ISPOW_LSB 2 + #define PM_OLDGRAFX_POWOK_BITS 1:1 + #define PM_OLDGRAFX_POWOK_SET 0x00000002 + #define PM_OLDGRAFX_POWOK_CLR 0xfffffffd + #define PM_OLDGRAFX_POWOK_MSB 1 + #define PM_OLDGRAFX_POWOK_LSB 1 + #define PM_OLDGRAFX_POWUP_BITS 0:0 + #define PM_OLDGRAFX_POWUP_SET 0x00000001 + #define PM_OLDGRAFX_POWUP_CLR 0xfffffffe + #define PM_OLDGRAFX_POWUP_MSB 0 + #define PM_OLDGRAFX_POWUP_LSB 0 +#define PM_IMAGE HW_REGISTER_RW( 0x7e100108 ) + #define PM_IMAGE_MASK 0x007f01ff + #define PM_IMAGE_WIDTH 23 + #define PM_IMAGE_RESET 0000000000 + #define PM_IMAGE_CFG_BITS 22:16 + #define PM_IMAGE_CFG_SET 0x007f0000 + #define PM_IMAGE_CFG_CLR 0xff80ffff + #define PM_IMAGE_CFG_MSB 22 + #define PM_IMAGE_CFG_LSB 16 + #define PM_IMAGE_ISPRSTN_BITS 8:8 + #define PM_IMAGE_ISPRSTN_SET 0x00000100 + #define PM_IMAGE_ISPRSTN_CLR 0xfffffeff + #define PM_IMAGE_ISPRSTN_MSB 8 + #define PM_IMAGE_ISPRSTN_LSB 8 + #define PM_IMAGE_H264RSTN_BITS 7:7 + #define PM_IMAGE_H264RSTN_SET 0x00000080 + #define PM_IMAGE_H264RSTN_CLR 0xffffff7f + #define PM_IMAGE_H264RSTN_MSB 7 + #define PM_IMAGE_H264RSTN_LSB 7 + #define PM_IMAGE_PERIRSTN_BITS 6:6 + #define PM_IMAGE_PERIRSTN_SET 0x00000040 + #define PM_IMAGE_PERIRSTN_CLR 0xffffffbf + #define PM_IMAGE_PERIRSTN_MSB 6 + #define PM_IMAGE_PERIRSTN_LSB 6 + #define PM_IMAGE_ISFUNC_BITS 5:5 + #define PM_IMAGE_ISFUNC_SET 0x00000020 + #define PM_IMAGE_ISFUNC_CLR 0xffffffdf + #define PM_IMAGE_ISFUNC_MSB 5 + #define PM_IMAGE_ISFUNC_LSB 5 + #define PM_IMAGE_MRDONE_BITS 4:4 + #define PM_IMAGE_MRDONE_SET 0x00000010 + #define PM_IMAGE_MRDONE_CLR 0xffffffef + #define PM_IMAGE_MRDONE_MSB 4 + #define PM_IMAGE_MRDONE_LSB 4 + #define PM_IMAGE_MEMREP_BITS 3:3 + #define PM_IMAGE_MEMREP_SET 0x00000008 + #define PM_IMAGE_MEMREP_CLR 0xfffffff7 + #define PM_IMAGE_MEMREP_MSB 3 + #define PM_IMAGE_MEMREP_LSB 3 + #define PM_IMAGE_ISPOW_BITS 2:2 + #define PM_IMAGE_ISPOW_SET 0x00000004 + #define PM_IMAGE_ISPOW_CLR 0xfffffffb + #define PM_IMAGE_ISPOW_MSB 2 + #define PM_IMAGE_ISPOW_LSB 2 + #define PM_IMAGE_POWOK_BITS 1:1 + #define PM_IMAGE_POWOK_SET 0x00000002 + #define PM_IMAGE_POWOK_CLR 0xfffffffd + #define PM_IMAGE_POWOK_MSB 1 + #define PM_IMAGE_POWOK_LSB 1 + #define PM_IMAGE_POWUP_BITS 0:0 + #define PM_IMAGE_POWUP_SET 0x00000001 + #define PM_IMAGE_POWUP_CLR 0xfffffffe + #define PM_IMAGE_POWUP_MSB 0 + #define PM_IMAGE_POWUP_LSB 0 +#define PM_GRAFX HW_REGISTER_RW( 0x7e10010c ) + #define PM_GRAFX_MASK 0x007f007f + #define PM_GRAFX_WIDTH 23 + #define PM_GRAFX_RESET 0000000000 + #define PM_GRAFX_CFG_BITS 22:16 + #define PM_GRAFX_CFG_SET 0x007f0000 + #define PM_GRAFX_CFG_CLR 0xff80ffff + #define PM_GRAFX_CFG_MSB 22 + #define PM_GRAFX_CFG_LSB 16 + #define PM_GRAFX_V3DRSTN_BITS 6:6 + #define PM_GRAFX_V3DRSTN_SET 0x00000040 + #define PM_GRAFX_V3DRSTN_CLR 0xffffffbf + #define PM_GRAFX_V3DRSTN_MSB 6 + #define PM_GRAFX_V3DRSTN_LSB 6 + #define PM_GRAFX_ISFUNC_BITS 5:5 + #define PM_GRAFX_ISFUNC_SET 0x00000020 + #define PM_GRAFX_ISFUNC_CLR 0xffffffdf + #define PM_GRAFX_ISFUNC_MSB 5 + #define PM_GRAFX_ISFUNC_LSB 5 + #define PM_GRAFX_MRDONE_BITS 4:4 + #define PM_GRAFX_MRDONE_SET 0x00000010 + #define PM_GRAFX_MRDONE_CLR 0xffffffef + #define PM_GRAFX_MRDONE_MSB 4 + #define PM_GRAFX_MRDONE_LSB 4 + #define PM_GRAFX_MEMREP_BITS 3:3 + #define PM_GRAFX_MEMREP_SET 0x00000008 + #define PM_GRAFX_MEMREP_CLR 0xfffffff7 + #define PM_GRAFX_MEMREP_MSB 3 + #define PM_GRAFX_MEMREP_LSB 3 + #define PM_GRAFX_ISPOW_BITS 2:2 + #define PM_GRAFX_ISPOW_SET 0x00000004 + #define PM_GRAFX_ISPOW_CLR 0xfffffffb + #define PM_GRAFX_ISPOW_MSB 2 + #define PM_GRAFX_ISPOW_LSB 2 + #define PM_GRAFX_POWOK_BITS 1:1 + #define PM_GRAFX_POWOK_SET 0x00000002 + #define PM_GRAFX_POWOK_CLR 0xfffffffd + #define PM_GRAFX_POWOK_MSB 1 + #define PM_GRAFX_POWOK_LSB 1 + #define PM_GRAFX_POWUP_BITS 0:0 + #define PM_GRAFX_POWUP_SET 0x00000001 + #define PM_GRAFX_POWUP_CLR 0xfffffffe + #define PM_GRAFX_POWUP_MSB 0 + #define PM_GRAFX_POWUP_LSB 0 +#define PM_PROC HW_REGISTER_RW( 0x7e100110 ) + #define PM_PROC_MASK 0x007f107f + #define PM_PROC_WIDTH 23 + #define PM_PROC_RESET 0000000000 + #define PM_PROC_CFG_BITS 22:16 + #define PM_PROC_CFG_SET 0x007f0000 + #define PM_PROC_CFG_CLR 0xff80ffff + #define PM_PROC_CFG_MSB 22 + #define PM_PROC_CFG_LSB 16 + #define PM_PROC_ENAB_BITS 12:12 + #define PM_PROC_ENAB_SET 0x00001000 + #define PM_PROC_ENAB_CLR 0xffffefff + #define PM_PROC_ENAB_MSB 12 + #define PM_PROC_ENAB_LSB 12 + #define PM_PROC_ARMRSTN_BITS 6:6 + #define PM_PROC_ARMRSTN_SET 0x00000040 + #define PM_PROC_ARMRSTN_CLR 0xffffffbf + #define PM_PROC_ARMRSTN_MSB 6 + #define PM_PROC_ARMRSTN_LSB 6 + #define PM_PROC_ISFUNC_BITS 5:5 + #define PM_PROC_ISFUNC_SET 0x00000020 + #define PM_PROC_ISFUNC_CLR 0xffffffdf + #define PM_PROC_ISFUNC_MSB 5 + #define PM_PROC_ISFUNC_LSB 5 + #define PM_PROC_MRDONE_BITS 4:4 + #define PM_PROC_MRDONE_SET 0x00000010 + #define PM_PROC_MRDONE_CLR 0xffffffef + #define PM_PROC_MRDONE_MSB 4 + #define PM_PROC_MRDONE_LSB 4 + #define PM_PROC_MEMREP_BITS 3:3 + #define PM_PROC_MEMREP_SET 0x00000008 + #define PM_PROC_MEMREP_CLR 0xfffffff7 + #define PM_PROC_MEMREP_MSB 3 + #define PM_PROC_MEMREP_LSB 3 + #define PM_PROC_ISPOW_BITS 2:2 + #define PM_PROC_ISPOW_SET 0x00000004 + #define PM_PROC_ISPOW_CLR 0xfffffffb + #define PM_PROC_ISPOW_MSB 2 + #define PM_PROC_ISPOW_LSB 2 + #define PM_PROC_POWOK_BITS 1:1 + #define PM_PROC_POWOK_SET 0x00000002 + #define PM_PROC_POWOK_CLR 0xfffffffd + #define PM_PROC_POWOK_MSB 1 + #define PM_PROC_POWOK_LSB 1 + #define PM_PROC_POWUP_BITS 0:0 + #define PM_PROC_POWUP_SET 0x00000001 + #define PM_PROC_POWUP_CLR 0xfffffffe + #define PM_PROC_POWUP_MSB 0 + #define PM_PROC_POWUP_LSB 0 +#define PM_OTPPOR HW_REGISTER_RW( 0x7e100010 ) + #define PM_OTPPOR_MASK 0x00ffffff + #define PM_OTPPOR_WIDTH 24 + #define PM_OTPPOR_RESET 0000000000 + #define PM_OTPPOR_KEY_BITS 23:0 + #define PM_OTPPOR_KEY_SET 0x00ffffff + #define PM_OTPPOR_KEY_CLR 0xff000000 + #define PM_OTPPOR_KEY_MSB 23 + #define PM_OTPPOR_KEY_LSB 0 +#define PM_AUDIOPOR HW_REGISTER_RW( 0x7e100014 ) + #define PM_AUDIOPOR_MASK 0x00ffffff + #define PM_AUDIOPOR_WIDTH 24 + #define PM_AUDIOPOR_RESET 0000000000 + #define PM_AUDIOPOR_KEY_BITS 23:0 + #define PM_AUDIOPOR_KEY_SET 0x00ffffff + #define PM_AUDIOPOR_KEY_CLR 0xff000000 + #define PM_AUDIOPOR_KEY_MSB 23 + #define PM_AUDIOPOR_KEY_LSB 0 +#define PM_POR HW_REGISTER_RO( 0x7e100018 ) + #define PM_POR_MASK 0x000007ff + #define PM_POR_WIDTH 11 + #define PM_POR_RESET 0000000000 + #define PM_POR_STATUS_BITS 10:0 + #define PM_POR_STATUS_SET 0x000007ff + #define PM_POR_STATUS_CLR 0xfffff800 + #define PM_POR_STATUS_MSB 10 + #define PM_POR_STATUS_LSB 0 +#define PM_RSTC HW_REGISTER_RW( 0x7e10001c ) + #define PM_RSTC_MASK 0x00333333 + #define PM_RSTC_WIDTH 22 + #define PM_RSTC_RESET 0x00000102 + #define PM_RSTC_HRCFG_BITS 21:20 + #define PM_RSTC_HRCFG_SET 0x00300000 + #define PM_RSTC_HRCFG_CLR 0xffcfffff + #define PM_RSTC_HRCFG_MSB 21 + #define PM_RSTC_HRCFG_LSB 20 + #define PM_RSTC_FRCFG_BITS 17:16 + #define PM_RSTC_FRCFG_SET 0x00030000 + #define PM_RSTC_FRCFG_CLR 0xfffcffff + #define PM_RSTC_FRCFG_MSB 17 + #define PM_RSTC_FRCFG_LSB 16 + #define PM_RSTC_QRCFG_BITS 13:12 + #define PM_RSTC_QRCFG_SET 0x00003000 + #define PM_RSTC_QRCFG_CLR 0xffffcfff + #define PM_RSTC_QRCFG_MSB 13 + #define PM_RSTC_QRCFG_LSB 12 + #define PM_RSTC_SRCFG_BITS 9:8 + #define PM_RSTC_SRCFG_SET 0x00000300 + #define PM_RSTC_SRCFG_CLR 0xfffffcff + #define PM_RSTC_SRCFG_MSB 9 + #define PM_RSTC_SRCFG_LSB 8 + #define PM_RSTC_WRCFG_BITS 5:4 + #define PM_RSTC_WRCFG_SET 0x00000030 + #define PM_RSTC_WRCFG_CLR 0xffffffcf + #define PM_RSTC_WRCFG_MSB 5 + #define PM_RSTC_WRCFG_LSB 4 + #define PM_RSTC_DRCFG_BITS 1:0 + #define PM_RSTC_DRCFG_SET 0x00000003 + #define PM_RSTC_DRCFG_CLR 0xfffffffc + #define PM_RSTC_DRCFG_MSB 1 + #define PM_RSTC_DRCFG_LSB 0 +#define PM_RSTS HW_REGISTER_RW( 0x7e100020 ) + #define PM_RSTS_MASK 0x00001777 + #define PM_RSTS_WIDTH 13 + #define PM_RSTS_RESET 0x00001000 + #define PM_RSTS_HADPOR_BITS 12:12 + #define PM_RSTS_HADPOR_SET 0x00001000 + #define PM_RSTS_HADPOR_CLR 0xffffefff + #define PM_RSTS_HADPOR_MSB 12 + #define PM_RSTS_HADPOR_LSB 12 + #define PM_RSTS_HADSRH_BITS 10:10 + #define PM_RSTS_HADSRH_SET 0x00000400 + #define PM_RSTS_HADSRH_CLR 0xfffffbff + #define PM_RSTS_HADSRH_MSB 10 + #define PM_RSTS_HADSRH_LSB 10 + #define PM_RSTS_HADSRF_BITS 9:9 + #define PM_RSTS_HADSRF_SET 0x00000200 + #define PM_RSTS_HADSRF_CLR 0xfffffdff + #define PM_RSTS_HADSRF_MSB 9 + #define PM_RSTS_HADSRF_LSB 9 + #define PM_RSTS_HADSRQ_BITS 8:8 + #define PM_RSTS_HADSRQ_SET 0x00000100 + #define PM_RSTS_HADSRQ_CLR 0xfffffeff + #define PM_RSTS_HADSRQ_MSB 8 + #define PM_RSTS_HADSRQ_LSB 8 + #define PM_RSTS_HADWRH_BITS 6:6 + #define PM_RSTS_HADWRH_SET 0x00000040 + #define PM_RSTS_HADWRH_CLR 0xffffffbf + #define PM_RSTS_HADWRH_MSB 6 + #define PM_RSTS_HADWRH_LSB 6 + #define PM_RSTS_HADWRF_BITS 5:5 + #define PM_RSTS_HADWRF_SET 0x00000020 + #define PM_RSTS_HADWRF_CLR 0xffffffdf + #define PM_RSTS_HADWRF_MSB 5 + #define PM_RSTS_HADWRF_LSB 5 + #define PM_RSTS_HADWRQ_BITS 4:4 + #define PM_RSTS_HADWRQ_SET 0x00000010 + #define PM_RSTS_HADWRQ_CLR 0xffffffef + #define PM_RSTS_HADWRQ_MSB 4 + #define PM_RSTS_HADWRQ_LSB 4 + #define PM_RSTS_HADDRH_BITS 2:2 + #define PM_RSTS_HADDRH_SET 0x00000004 + #define PM_RSTS_HADDRH_CLR 0xfffffffb + #define PM_RSTS_HADDRH_MSB 2 + #define PM_RSTS_HADDRH_LSB 2 + #define PM_RSTS_HADDRF_BITS 1:1 + #define PM_RSTS_HADDRF_SET 0x00000002 + #define PM_RSTS_HADDRF_CLR 0xfffffffd + #define PM_RSTS_HADDRF_MSB 1 + #define PM_RSTS_HADDRF_LSB 1 + #define PM_RSTS_HADDRQ_BITS 0:0 + #define PM_RSTS_HADDRQ_SET 0x00000001 + #define PM_RSTS_HADDRQ_CLR 0xfffffffe + #define PM_RSTS_HADDRQ_MSB 0 + #define PM_RSTS_HADDRQ_LSB 0 +#define PM_WDOG HW_REGISTER_RW( 0x7e100024 ) + #define PM_WDOG_MASK 0x00000fff + #define PM_WDOG_WIDTH 12 + #define PM_WDOG_RESET 0000000000 + #define PM_WDOG_TIME_BITS 11:0 + #define PM_WDOG_TIME_SET 0x00000fff + #define PM_WDOG_TIME_CLR 0xfffff000 + #define PM_WDOG_TIME_MSB 11 + #define PM_WDOG_TIME_LSB 0 +#define PM_PADS0 HW_REGISTER_RW( 0x7e100028 ) + #define PM_PADS0_MASK 0x0000003f + #define PM_PADS0_WIDTH 6 + #define PM_PADS0_RESET 0x0000001b + #define PM_PADS0_DRIVE_BITS 2:0 + #define PM_PADS0_DRIVE_SET 0x00000007 + #define PM_PADS0_DRIVE_CLR 0xfffffff8 + #define PM_PADS0_DRIVE_MSB 2 + #define PM_PADS0_DRIVE_LSB 0 + #define PM_PADS0_HYST_BITS 3:3 + #define PM_PADS0_HYST_SET 0x00000008 + #define PM_PADS0_HYST_CLR 0xfffffff7 + #define PM_PADS0_HYST_MSB 3 + #define PM_PADS0_HYST_LSB 3 + #define PM_PADS0_SLEW_BITS 4:4 + #define PM_PADS0_SLEW_SET 0x00000010 + #define PM_PADS0_SLEW_CLR 0xffffffef + #define PM_PADS0_SLEW_MSB 4 + #define PM_PADS0_SLEW_LSB 4 + #define PM_PADS0_POWOK_BITS 5:5 + #define PM_PADS0_POWOK_SET 0x00000020 + #define PM_PADS0_POWOK_CLR 0xffffffdf + #define PM_PADS0_POWOK_MSB 5 + #define PM_PADS0_POWOK_LSB 5 +#define PM_PADS2 HW_REGISTER_RW( 0x7e10002c ) + #define PM_PADS2_MASK 0x0000003f + #define PM_PADS2_WIDTH 6 + #define PM_PADS2_RESET 0x0000001b + #define PM_PADS2_DRIVE_BITS 2:0 + #define PM_PADS2_DRIVE_SET 0x00000007 + #define PM_PADS2_DRIVE_CLR 0xfffffff8 + #define PM_PADS2_DRIVE_MSB 2 + #define PM_PADS2_DRIVE_LSB 0 + #define PM_PADS2_HYST_BITS 3:3 + #define PM_PADS2_HYST_SET 0x00000008 + #define PM_PADS2_HYST_CLR 0xfffffff7 + #define PM_PADS2_HYST_MSB 3 + #define PM_PADS2_HYST_LSB 3 + #define PM_PADS2_SLEW_BITS 4:4 + #define PM_PADS2_SLEW_SET 0x00000010 + #define PM_PADS2_SLEW_CLR 0xffffffef + #define PM_PADS2_SLEW_MSB 4 + #define PM_PADS2_SLEW_LSB 4 + #define PM_PADS2_POWOK_BITS 5:5 + #define PM_PADS2_POWOK_SET 0x00000020 + #define PM_PADS2_POWOK_CLR 0xffffffdf + #define PM_PADS2_POWOK_MSB 5 + #define PM_PADS2_POWOK_LSB 5 +#define PM_PADS3 HW_REGISTER_RW( 0x7e100030 ) + #define PM_PADS3_MASK 0x0000003f + #define PM_PADS3_WIDTH 6 + #define PM_PADS3_RESET 0x0000001b + #define PM_PADS3_DRIVE_BITS 2:0 + #define PM_PADS3_DRIVE_SET 0x00000007 + #define PM_PADS3_DRIVE_CLR 0xfffffff8 + #define PM_PADS3_DRIVE_MSB 2 + #define PM_PADS3_DRIVE_LSB 0 + #define PM_PADS3_HYST_BITS 3:3 + #define PM_PADS3_HYST_SET 0x00000008 + #define PM_PADS3_HYST_CLR 0xfffffff7 + #define PM_PADS3_HYST_MSB 3 + #define PM_PADS3_HYST_LSB 3 + #define PM_PADS3_SLEW_BITS 4:4 + #define PM_PADS3_SLEW_SET 0x00000010 + #define PM_PADS3_SLEW_CLR 0xffffffef + #define PM_PADS3_SLEW_MSB 4 + #define PM_PADS3_SLEW_LSB 4 + #define PM_PADS3_POWOK_BITS 5:5 + #define PM_PADS3_POWOK_SET 0x00000020 + #define PM_PADS3_POWOK_CLR 0xffffffdf + #define PM_PADS3_POWOK_MSB 5 + #define PM_PADS3_POWOK_LSB 5 +#define PM_PADS4 HW_REGISTER_RW( 0x7e100034 ) + #define PM_PADS4_MASK 0x0000003f + #define PM_PADS4_WIDTH 6 + #define PM_PADS4_RESET 0x0000001b + #define PM_PADS4_DRIVE_BITS 2:0 + #define PM_PADS4_DRIVE_SET 0x00000007 + #define PM_PADS4_DRIVE_CLR 0xfffffff8 + #define PM_PADS4_DRIVE_MSB 2 + #define PM_PADS4_DRIVE_LSB 0 + #define PM_PADS4_HYST_BITS 3:3 + #define PM_PADS4_HYST_SET 0x00000008 + #define PM_PADS4_HYST_CLR 0xfffffff7 + #define PM_PADS4_HYST_MSB 3 + #define PM_PADS4_HYST_LSB 3 + #define PM_PADS4_SLEW_BITS 4:4 + #define PM_PADS4_SLEW_SET 0x00000010 + #define PM_PADS4_SLEW_CLR 0xffffffef + #define PM_PADS4_SLEW_MSB 4 + #define PM_PADS4_SLEW_LSB 4 + #define PM_PADS4_POWOK_BITS 5:5 + #define PM_PADS4_POWOK_SET 0x00000020 + #define PM_PADS4_POWOK_CLR 0xffffffdf + #define PM_PADS4_POWOK_MSB 5 + #define PM_PADS4_POWOK_LSB 5 +#define PM_PADS5 HW_REGISTER_RW( 0x7e100038 ) + #define PM_PADS5_MASK 0x0000007f + #define PM_PADS5_WIDTH 7 + #define PM_PADS5_RESET 0x0000001b + #define PM_PADS5_DRIVE_BITS 2:0 + #define PM_PADS5_DRIVE_SET 0x00000007 + #define PM_PADS5_DRIVE_CLR 0xfffffff8 + #define PM_PADS5_DRIVE_MSB 2 + #define PM_PADS5_DRIVE_LSB 0 + #define PM_PADS5_HYST_BITS 3:3 + #define PM_PADS5_HYST_SET 0x00000008 + #define PM_PADS5_HYST_CLR 0xfffffff7 + #define PM_PADS5_HYST_MSB 3 + #define PM_PADS5_HYST_LSB 3 + #define PM_PADS5_SLEW_BITS 4:4 + #define PM_PADS5_SLEW_SET 0x00000010 + #define PM_PADS5_SLEW_CLR 0xffffffef + #define PM_PADS5_SLEW_MSB 4 + #define PM_PADS5_SLEW_LSB 4 + #define PM_PADS5_POWOK_BITS 5:5 + #define PM_PADS5_POWOK_SET 0x00000020 + #define PM_PADS5_POWOK_CLR 0xffffffdf + #define PM_PADS5_POWOK_MSB 5 + #define PM_PADS5_POWOK_LSB 5 + #define PM_PADS5_I2CMODE_BITS 6:6 + #define PM_PADS5_I2CMODE_SET 0x00000040 + #define PM_PADS5_I2CMODE_CLR 0xffffffbf + #define PM_PADS5_I2CMODE_MSB 6 + #define PM_PADS5_I2CMODE_LSB 6 +#define PM_PADS6 HW_REGISTER_RW( 0x7e10003c ) + #define PM_PADS6_MASK 0x00000023 + #define PM_PADS6_WIDTH 6 + #define PM_PADS6_RESET 0000000000 + #define PM_PADS6_DRIVE_BITS 1:0 + #define PM_PADS6_DRIVE_SET 0x00000003 + #define PM_PADS6_DRIVE_CLR 0xfffffffc + #define PM_PADS6_DRIVE_MSB 1 + #define PM_PADS6_DRIVE_LSB 0 + #define PM_PADS6_POWOK_BITS 5:5 + #define PM_PADS6_POWOK_SET 0x00000020 + #define PM_PADS6_POWOK_CLR 0xffffffdf + #define PM_PADS6_POWOK_MSB 5 + #define PM_PADS6_POWOK_LSB 5 +#define PM_MEMS HW_REGISTER_RW( 0x7e100040 ) + #define PM_MEMS_MASK 0x00000001 + #define PM_MEMS_WIDTH 1 + #define PM_MEMS_RESET 0000000000 + #define PM_MEMS_LOWVOLT_BITS 0:0 + #define PM_MEMS_LOWVOLT_SET 0x00000001 + #define PM_MEMS_LOWVOLT_CLR 0xfffffffe + #define PM_MEMS_LOWVOLT_MSB 0 + #define PM_MEMS_LOWVOLT_LSB 0 +#define PM_CAM0 HW_REGISTER_RW( 0x7e100044 ) + #define PM_CAM0_MASK 0x001fffff + #define PM_CAM0_WIDTH 21 + #define PM_CAM0_RESET 0000000000 + #define PM_CAM0_CTRLEN_BITS 0:0 + #define PM_CAM0_CTRLEN_SET 0x00000001 + #define PM_CAM0_CTRLEN_CLR 0xfffffffe + #define PM_CAM0_CTRLEN_MSB 0 + #define PM_CAM0_CTRLEN_LSB 0 + #define PM_CAM0_LDOLPEN_BITS 1:1 + #define PM_CAM0_LDOLPEN_SET 0x00000002 + #define PM_CAM0_LDOLPEN_CLR 0xfffffffd + #define PM_CAM0_LDOLPEN_MSB 1 + #define PM_CAM0_LDOLPEN_LSB 1 + #define PM_CAM0_LDOHPEN_BITS 2:2 + #define PM_CAM0_LDOHPEN_SET 0x00000004 + #define PM_CAM0_LDOHPEN_CLR 0xfffffffb + #define PM_CAM0_LDOHPEN_MSB 2 + #define PM_CAM0_LDOHPEN_LSB 2 + #define PM_CAM0_LDOCTRL_BITS 20:3 + #define PM_CAM0_LDOCTRL_SET 0x001ffff8 + #define PM_CAM0_LDOCTRL_CLR 0xffe00007 + #define PM_CAM0_LDOCTRL_MSB 20 + #define PM_CAM0_LDOCTRL_LSB 3 +#define PM_CAM1 HW_REGISTER_RW( 0x7e100048 ) + #define PM_CAM1_MASK 0x001fffff + #define PM_CAM1_WIDTH 21 + #define PM_CAM1_RESET 0000000000 + #define PM_CAM1_CTRLEN_BITS 0:0 + #define PM_CAM1_CTRLEN_SET 0x00000001 + #define PM_CAM1_CTRLEN_CLR 0xfffffffe + #define PM_CAM1_CTRLEN_MSB 0 + #define PM_CAM1_CTRLEN_LSB 0 + #define PM_CAM1_LDOLPEN_BITS 1:1 + #define PM_CAM1_LDOLPEN_SET 0x00000002 + #define PM_CAM1_LDOLPEN_CLR 0xfffffffd + #define PM_CAM1_LDOLPEN_MSB 1 + #define PM_CAM1_LDOLPEN_LSB 1 + #define PM_CAM1_LDOHPEN_BITS 2:2 + #define PM_CAM1_LDOHPEN_SET 0x00000004 + #define PM_CAM1_LDOHPEN_CLR 0xfffffffb + #define PM_CAM1_LDOHPEN_MSB 2 + #define PM_CAM1_LDOHPEN_LSB 2 + #define PM_CAM1_LDOCTRL_BITS 20:3 + #define PM_CAM1_LDOCTRL_SET 0x001ffff8 + #define PM_CAM1_LDOCTRL_CLR 0xffe00007 + #define PM_CAM1_LDOCTRL_MSB 20 + #define PM_CAM1_LDOCTRL_LSB 3 +#define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c ) + #define PM_CCP2TX_MASK 0x0007ffff + #define PM_CCP2TX_WIDTH 19 + #define PM_CCP2TX_RESET 0000000000 + #define PM_CCP2TX_CTRLEN_BITS 0:0 + #define PM_CCP2TX_CTRLEN_SET 0x00000001 + #define PM_CCP2TX_CTRLEN_CLR 0xfffffffe + #define PM_CCP2TX_CTRLEN_MSB 0 + #define PM_CCP2TX_CTRLEN_LSB 0 + #define PM_CCP2TX_LDOEN_BITS 1:1 + #define PM_CCP2TX_LDOEN_SET 0x00000002 + #define PM_CCP2TX_LDOEN_CLR 0xfffffffd + #define PM_CCP2TX_LDOEN_MSB 1 + #define PM_CCP2TX_LDOEN_LSB 1 + #define PM_CCP2TX_LDOCTRL_BITS 18:2 + #define PM_CCP2TX_LDOCTRL_SET 0x0007fffc + #define PM_CCP2TX_LDOCTRL_CLR 0xfff80003 + #define PM_CCP2TX_LDOCTRL_MSB 18 + #define PM_CCP2TX_LDOCTRL_LSB 2 +#define PM_DSI0 HW_REGISTER_RW( 0x7e100050 ) + #define PM_DSI0_MASK 0x001fffff + #define PM_DSI0_WIDTH 21 + #define PM_DSI0_RESET 0000000000 + #define PM_DSI0_CTRLEN_BITS 0:0 + #define PM_DSI0_CTRLEN_SET 0x00000001 + #define PM_DSI0_CTRLEN_CLR 0xfffffffe + #define PM_DSI0_CTRLEN_MSB 0 + #define PM_DSI0_CTRLEN_LSB 0 + #define PM_DSI0_LDOLPEN_BITS 1:1 + #define PM_DSI0_LDOLPEN_SET 0x00000002 + #define PM_DSI0_LDOLPEN_CLR 0xfffffffd + #define PM_DSI0_LDOLPEN_MSB 1 + #define PM_DSI0_LDOLPEN_LSB 1 + #define PM_DSI0_LDOHPEN_BITS 2:2 + #define PM_DSI0_LDOHPEN_SET 0x00000004 + #define PM_DSI0_LDOHPEN_CLR 0xfffffffb + #define PM_DSI0_LDOHPEN_MSB 2 + #define PM_DSI0_LDOHPEN_LSB 2 + #define PM_DSI0_LDOCTRL_BITS 20:3 + #define PM_DSI0_LDOCTRL_SET 0x001ffff8 + #define PM_DSI0_LDOCTRL_CLR 0xffe00007 + #define PM_DSI0_LDOCTRL_MSB 20 + #define PM_DSI0_LDOCTRL_LSB 3 +#define PM_DSI1 HW_REGISTER_RW( 0x7e100054 ) + #define PM_DSI1_MASK 0x001fffff + #define PM_DSI1_WIDTH 21 + #define PM_DSI1_RESET 0000000000 + #define PM_DSI1_CTRLEN_BITS 0:0 + #define PM_DSI1_CTRLEN_SET 0x00000001 + #define PM_DSI1_CTRLEN_CLR 0xfffffffe + #define PM_DSI1_CTRLEN_MSB 0 + #define PM_DSI1_CTRLEN_LSB 0 + #define PM_DSI1_LDOLPEN_BITS 1:1 + #define PM_DSI1_LDOLPEN_SET 0x00000002 + #define PM_DSI1_LDOLPEN_CLR 0xfffffffd + #define PM_DSI1_LDOLPEN_MSB 1 + #define PM_DSI1_LDOLPEN_LSB 1 + #define PM_DSI1_LDOHPEN_BITS 2:2 + #define PM_DSI1_LDOHPEN_SET 0x00000004 + #define PM_DSI1_LDOHPEN_CLR 0xfffffffb + #define PM_DSI1_LDOHPEN_MSB 2 + #define PM_DSI1_LDOHPEN_LSB 2 + #define PM_DSI1_LDOCTRL_BITS 20:3 + #define PM_DSI1_LDOCTRL_SET 0x001ffff8 + #define PM_DSI1_LDOCTRL_CLR 0xffe00007 + #define PM_DSI1_LDOCTRL_MSB 20 + #define PM_DSI1_LDOCTRL_LSB 3 +#define PM_HDMI HW_REGISTER_RW( 0x7e100058 ) + #define PM_HDMI_MASK 0x000fffff + #define PM_HDMI_WIDTH 20 + #define PM_HDMI_RESET 0x00000002 + #define PM_HDMI_CTRLEN_BITS 0:0 + #define PM_HDMI_CTRLEN_SET 0x00000001 + #define PM_HDMI_CTRLEN_CLR 0xfffffffe + #define PM_HDMI_CTRLEN_MSB 0 + #define PM_HDMI_CTRLEN_LSB 0 + #define PM_HDMI_LDOPD_BITS 1:1 + #define PM_HDMI_LDOPD_SET 0x00000002 + #define PM_HDMI_LDOPD_CLR 0xfffffffd + #define PM_HDMI_LDOPD_MSB 1 + #define PM_HDMI_LDOPD_LSB 1 + #define PM_HDMI_LDOCTRL_BITS 18:2 + #define PM_HDMI_LDOCTRL_SET 0x0007fffc + #define PM_HDMI_LDOCTRL_CLR 0xfff80003 + #define PM_HDMI_LDOCTRL_MSB 18 + #define PM_HDMI_LDOCTRL_LSB 2 + #define PM_HDMI_RSTDR_BITS 19:19 + #define PM_HDMI_RSTDR_SET 0x00080000 + #define PM_HDMI_RSTDR_CLR 0xfff7ffff + #define PM_HDMI_RSTDR_MSB 19 + #define PM_HDMI_RSTDR_LSB 19 +#define PM_USB HW_REGISTER_RW( 0x7e10005c ) + #define PM_USB_MASK 0x00000001 + #define PM_USB_WIDTH 1 + #define PM_USB_RESET 0000000000 + #define PM_USB_CTRLEN_BITS 0:0 + #define PM_USB_CTRLEN_SET 0x00000001 + #define PM_USB_CTRLEN_CLR 0xfffffffe + #define PM_USB_CTRLEN_MSB 0 + #define PM_USB_CTRLEN_LSB 0 +#define PM_PXLDO HW_REGISTER_RW( 0x7e100060 ) + #define PM_PXLDO_MASK 0x0003ffff + #define PM_PXLDO_WIDTH 18 + #define PM_PXLDO_RESET 0000000000 + #define PM_PXLDO_CTRL_BITS 15:0 + #define PM_PXLDO_CTRL_SET 0x0000ffff + #define PM_PXLDO_CTRL_CLR 0xffff0000 + #define PM_PXLDO_CTRL_MSB 15 + #define PM_PXLDO_CTRL_LSB 0 + #define PM_PXLDO_RSTOSCDR_BITS 16:16 + #define PM_PXLDO_RSTOSCDR_SET 0x00010000 + #define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff + #define PM_PXLDO_RSTOSCDR_MSB 16 + #define PM_PXLDO_RSTOSCDR_LSB 16 + #define PM_PXLDO_RSTPLLDR_BITS 17:17 + #define PM_PXLDO_RSTPLLDR_SET 0x00020000 + #define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff + #define PM_PXLDO_RSTPLLDR_MSB 17 + #define PM_PXLDO_RSTPLLDR_LSB 17 +#define PM_PXBG HW_REGISTER_RW( 0x7e100064 ) + #define PM_PXBG_MASK 0x0000ffff + #define PM_PXBG_WIDTH 16 + #define PM_PXBG_RESET 0000000000 + #define PM_PXBG_CTRL_BITS 15:0 + #define PM_PXBG_CTRL_SET 0x0000ffff + #define PM_PXBG_CTRL_CLR 0xffff0000 + #define PM_PXBG_CTRL_MSB 15 + #define PM_PXBG_CTRL_LSB 0 +#define PM_DFT HW_REGISTER_RW( 0x7e100068 ) + #define PM_DFT_MASK 0x00000003 + #define PM_DFT_WIDTH 2 + #define PM_DFT_RESET 0000000000 + #define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0 + #define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001 + #define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe + #define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0 + #define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0 + #define PM_DFT_STOPALLCLOCKS_BITS 1:1 + #define PM_DFT_STOPALLCLOCKS_SET 0x00000002 + #define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd + #define PM_DFT_STOPALLCLOCKS_MSB 1 + #define PM_DFT_STOPALLCLOCKS_LSB 1 +#define PM_SMPS HW_REGISTER_RW( 0x7e10006c ) + #define PM_SMPS_MASK 0x00000007 + #define PM_SMPS_WIDTH 3 + #define PM_SMPS_RESET 0000000000 + #define PM_SMPS_CTRLEN_BITS 0:0 + #define PM_SMPS_CTRLEN_SET 0x00000001 + #define PM_SMPS_CTRLEN_CLR 0xfffffffe + #define PM_SMPS_CTRLEN_MSB 0 + #define PM_SMPS_CTRLEN_LSB 0 + #define PM_SMPS_RSTDR_BITS 1:1 + #define PM_SMPS_RSTDR_SET 0x00000002 + #define PM_SMPS_RSTDR_CLR 0xfffffffd + #define PM_SMPS_RSTDR_MSB 1 + #define PM_SMPS_RSTDR_LSB 1 + #define PM_SMPS_UPEN_BITS 2:2 + #define PM_SMPS_UPEN_SET 0x00000004 + #define PM_SMPS_UPEN_CLR 0xfffffffb + #define PM_SMPS_UPEN_MSB 2 + #define PM_SMPS_UPEN_LSB 2 +#define PM_XOSC HW_REGISTER_RW( 0x7e100070 ) + #define PM_XOSC_MASK 0x00000001 + #define PM_XOSC_WIDTH 1 + #define PM_XOSC_RESET 0000000000 + #define PM_XOSC_USESEC_BITS 0:0 + #define PM_XOSC_USESEC_SET 0x00000001 + #define PM_XOSC_USESEC_CLR 0xfffffffe + #define PM_XOSC_USESEC_MSB 0 + #define PM_XOSC_USESEC_LSB 0 +#define PM_SPAREW HW_REGISTER_RW( 0x7e100074 ) + #define PM_SPAREW_MASK 0x00ffffff + #define PM_SPAREW_WIDTH 24 + #define PM_SPAREW_RESET 0000000000 + #define PM_SPAREW_SPARE_BITS 23:0 + #define PM_SPAREW_SPARE_SET 0x00ffffff + #define PM_SPAREW_SPARE_CLR 0xff000000 + #define PM_SPAREW_SPARE_MSB 23 + #define PM_SPAREW_SPARE_LSB 0 +#define PM_SPARER HW_REGISTER_RO( 0x7e100078 ) + #define PM_SPARER_MASK 0x00ffffff + #define PM_SPARER_WIDTH 24 + #define PM_SPARER_RESET 0000000000 + #define PM_SPARER_SPARE_BITS 23:0 + #define PM_SPARER_SPARE_SET 0x00ffffff + #define PM_SPARER_SPARE_CLR 0xff000000 + #define PM_SPARER_SPARE_MSB 23 + #define PM_SPARER_SPARE_LSB 0 +#define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc ) + #define PM_DUMMY_MASK 0x00000001 + #define PM_DUMMY_WIDTH 1 + #define PM_DUMMY_RESET 0x00000001 + #define PM_DUMMY_ONE_BITS 0:0 + #define PM_DUMMY_ONE_SET 0x00000001 + #define PM_DUMMY_ONE_CLR 0xfffffffe + #define PM_DUMMY_ONE_MSB 0 + #define PM_DUMMY_ONE_LSB 0 diff --git a/bcm2708_chip/cryptohw.h b/bcm2708_chip/cryptohw.h new file mode 100755 index 0000000..5977caf --- /dev/null +++ b/bcm2708_chip/cryptohw.h @@ -0,0 +1,67 @@ +/*============================================================================= +Copyright (c) 2007 Broadcom Europe Limited. All rights reserved. + +Project : BCM2707 +Module : CRYPTO wrapper hardware header +File : $RCSfile: cryptohw.h,v $ +Revision : $Revision: 1.2 $ + +FILE DESCRIPTION +Definition of bits within CRYPTO hardware registers. +=============================================================================*/ + +#ifndef CRYPTOHW_H +#define CRYPTOHW_H + +#define CRYPTO_READFIELD(_w,_f) (((unsigned long)(_w) / _f) & (_f##_MASK)) + +enum +{ +// BCM2707 has no crypto hardware but supports RNG interrupt +// CRYPTO_ISR_RNG_INT = (1 << 2), + CRYPTO_ISR_PKA_INT = (1 << 1), + CRYPTO_ISR_SPU_INT = (1 << 0), + +// CRYPTO_IMR_RNG_INT_EN = (1 << 2), + CRYPTO_IMR_PKA_INT_EN = (1 << 1), + CRYPTO_IMR_SPU_INT_EN = (1 << 0), + + CRYPTO_CLK_CFG_PKA_CLK = (1 << 8), + CRYPTO_CLK_CFG_PKA_CLK_MASK = 3, + CRYPTO_CLK_CFG_PKA_CLK_FULL = 0, + CRYPTO_CLK_CFG_PKA_CLK_HALF = 1, + CRYPTO_CLK_CFG_PKA_CLK_THIRD = 2, + CRYPTO_CLK_CFG_PKA_CLK_DISABLED = 3, + + CRYPTO_CLK_CFG_SPU_CLK = (1 << 4), + CRYPTO_CLK_CFG_SPU_CLK_MASK = 3, + CRYPTO_CLK_CFG_SPU_CLK_FULL = 0, + CRYPTO_CLK_CFG_SPU_CLK_HALF = 1, + CRYPTO_CLK_CFG_SPU_CLK_THIRD = 2, + CRYPTO_CLK_CFG_SPU_CLK_DISABLED = 3, + + CRYPTO_CLK_CFG_OTP_CLKDIV = (1 << 0), + CRYPTO_CLK_CFG_OTP_CLKDIV_MASK = 0xf, + + CRYPTO_CLK_CFG_OTP_CLKDIV_2 = 0x0, + CRYPTO_CLK_CFG_OTP_CLKDIV_4 = 0x1, + CRYPTO_CLK_CFG_OTP_CLKDIV_6 = 0x2, + CRYPTO_CLK_CFG_OTP_CLKDIV_8 = 0x3, + CRYPTO_CLK_CFG_OTP_CLKDIV_10 = 0x4, + CRYPTO_CLK_CFG_OTP_CLKDIV_12 = 0x5, + CRYPTO_CLK_CFG_OTP_CLKDIV_14 = 0x6, + CRYPTO_CLK_CFG_OTP_CLKDIV_16 = 0x7, + CRYPTO_CLK_CFG_OTP_CLKDIV_18 = 0x8, + CRYPTO_CLK_CFG_OTP_CLKDIV_20 = 0x9, + CRYPTO_CLK_CFG_OTP_CLKDIV_22 = 0xa, + CRYPTO_CLK_CFG_OTP_CLKDIV_24 = 0xb, + CRYPTO_CLK_CFG_OTP_CLKDIV_26 = 0xc, + CRYPTO_CLK_CFG_OTP_CLKDIV_28 = 0xd, + CRYPTO_CLK_CFG_OTP_CLKDIV_30 = 0xe, + CRYPTO_CLK_CFG_OTP_CLKDIV_32 = 0xf, + + CRYPTO_SIMCTRL_DEBUG = (1 << 0), + CRYPTO_SIMCTRL_SECURE = (1 << 1) +}; + +#endif diff --git a/bcm2708_chip/csi2.h b/bcm2708_chip/csi2.h new file mode 100755 index 0000000..3e08bec --- /dev/null +++ b/bcm2708_chip/csi2.h @@ -0,0 +1,433 @@ +// This file was generated by the create_regs script +#define CS_BASE 0x7e802000 +#define CS_APB_ID 0x43534932 +#define CS_RC HW_REGISTER_RW( 0x7e802000 ) + #define CS_RC_MASK 0xffffc07f + #define CS_RC_WIDTH 32 + #define CS_RC_RESET 0x77ce0000 + #define CS_RC_CTATADJ_MSB 31 + #define CS_RC_CTATADJ_LSB 28 + #define CS_RC_PTATADJ_MSB 27 + #define CS_RC_PTATADJ_LSB 24 + #define CS_RC_RPP_MSB 23 + #define CS_RC_RPP_LSB 20 + #define CS_RC_RNP_MSB 19 + #define CS_RC_RNP_LSB 19 + #define CS_RC_BPD_MSB 18 + #define CS_RC_BPD_LSB 18 + #define CS_RC_APD_MSB 17 + #define CS_RC_APD_LSB 17 + #define CS_RC_FOE_MSB 16 + #define CS_RC_FOE_LSB 16 + #define CS_RC_FOF_MSB 15 + #define CS_RC_FOF_LSB 15 + #define CS_RC_RSYN_MSB 14 + #define CS_RC_RSYN_LSB 14 + #define CS_RC_F16B_MSB 6 + #define CS_RC_F16B_LSB 6 + #define CS_RC_GEN_MSB 5 + #define CS_RC_GEN_LSB 5 + #define CS_RC_LENC_MSB 4 + #define CS_RC_LENC_LSB 4 + #define CS_RC_LEN4_MSB 3 + #define CS_RC_LEN4_LSB 3 + #define CS_RC_LEN3_MSB 2 + #define CS_RC_LEN3_LSB 2 + #define CS_RC_LEN2_MSB 1 + #define CS_RC_LEN2_LSB 1 + #define CS_RC_LEN1_MSB 0 + #define CS_RC_LEN1_LSB 0 +#define CS_RS HW_REGISTER_RW( 0x7e802004 ) + #define CS_RS_MASK 0x0000033f + #define CS_RS_WIDTH 10 + #define CS_RS_RESET 0000000000 + #define CS_RS_IS1_MSB 9 + #define CS_RS_IS1_LSB 9 + #define CS_RS_IS0_MSB 8 + #define CS_RS_IS0_LSB 8 + #define CS_RS_OFF_MSB 5 + #define CS_RS_OFF_LSB 5 + #define CS_RS_OFP_MSB 4 + #define CS_RS_OFP_LSB 4 + #define CS_RS_PEC_MSB 3 + #define CS_RS_PEC_LSB 3 + #define CS_RS_PED_MSB 2 + #define CS_RS_PED_LSB 2 + #define CS_RS_OEB_MSB 1 + #define CS_RS_OEB_LSB 1 + #define CS_RS_GEF_MSB 0 + #define CS_RS_GEF_LSB 0 +#define CS_RDLS HW_REGISTER_RW( 0x7e802008 ) + #define CS_RDLS_MASK 0x3fffffff + #define CS_RDLS_WIDTH 30 + #define CS_RDLS_RESET 0000000000 + #define CS_RDLS_CEC_MSB 29 + #define CS_RDLS_CEC_LSB 29 + #define CS_RDLS_ESEC_MSB 28 + #define CS_RDLS_ESEC_LSB 28 + #define CS_RDLS_EEEC_MSB 27 + #define CS_RDLS_EEEC_LSB 27 + #define CS_RDLS_SOTSEC_MSB 26 + #define CS_RDLS_SOTSEC_LSB 26 + #define CS_RDLS_SOTEC_MSB 25 + #define CS_RDLS_SOTEC_LSB 25 + #define CS_RDLS_ULPSC_MSB 24 + #define CS_RDLS_ULPSC_LSB 24 + #define CS_RDLS_CE4_MSB 23 + #define CS_RDLS_CE4_LSB 23 + #define CS_RDLS_ESE4_MSB 22 + #define CS_RDLS_ESE4_LSB 22 + #define CS_RDLS_EEE4_MSB 21 + #define CS_RDLS_EEE4_LSB 21 + #define CS_RDLS_SOTSE4_MSB 20 + #define CS_RDLS_SOTSE4_LSB 20 + #define CS_RDLS_SOTE4_MSB 19 + #define CS_RDLS_SOTE4_LSB 19 + #define CS_RDLS_ULPS4_MSB 18 + #define CS_RDLS_ULPS4_LSB 18 + #define CS_RDLS_CE3_MSB 17 + #define CS_RDLS_CE3_LSB 17 + #define CS_RDLS_ESE3_MSB 16 + #define CS_RDLS_ESE3_LSB 16 + #define CS_RDLS_EEE3_MSB 15 + #define CS_RDLS_EEE3_LSB 15 + #define CS_RDLS_SOTSE3_MSB 14 + #define CS_RDLS_SOTSE3_LSB 14 + #define CS_RDLS_SOTE3_MSB 13 + #define CS_RDLS_SOTE3_LSB 13 + #define CS_RDLS_ULPS3_MSB 12 + #define CS_RDLS_ULPS3_LSB 12 + #define CS_RDLS_CE2_MSB 11 + #define CS_RDLS_CE2_LSB 11 + #define CS_RDLS_ESE2_MSB 10 + #define CS_RDLS_ESE2_LSB 10 + #define CS_RDLS_EEE2_MSB 9 + #define CS_RDLS_EEE2_LSB 9 + #define CS_RDLS_SOTSE2_MSB 8 + #define CS_RDLS_SOTSE2_LSB 8 + #define CS_RDLS_SOTE2_MSB 7 + #define CS_RDLS_SOTE2_LSB 7 + #define CS_RDLS_ULPS2_MSB 6 + #define CS_RDLS_ULPS2_LSB 6 + #define CS_RDLS_CE1_MSB 5 + #define CS_RDLS_CE1_LSB 5 + #define CS_RDLS_ESE1_MSB 4 + #define CS_RDLS_ESE1_LSB 4 + #define CS_RDLS_EEE1_MSB 3 + #define CS_RDLS_EEE1_LSB 3 + #define CS_RDLS_SOTSE1_MSB 2 + #define CS_RDLS_SOTSE1_LSB 2 + #define CS_RDLS_SOTE1_MSB 1 + #define CS_RDLS_SOTE1_LSB 1 + #define CS_RDLS_ULPS1_MSB 0 + #define CS_RDLS_ULPS1_LSB 0 +#define CS_RGSP HW_REGISTER_RO( 0x7e80200c ) + #define CS_RGSP_MASK 0x00ffffff + #define CS_RGSP_WIDTH 24 + #define CS_RGSP_DATA_MSB 23 + #define CS_RGSP_DATA_LSB 8 + #define CS_RGSP_VC_MSB 7 + #define CS_RGSP_VC_LSB 6 + #define CS_RGSP_DT_MSB 5 + #define CS_RGSP_DT_LSB 0 +#define CS_TREN HW_REGISTER_RW( 0x7e802010 ) + #define CS_TREN_MASK 0x000003ff + #define CS_TREN_WIDTH 10 + #define CS_TREN_RESET 0000000000 + #define CS_TREN_TROVC_MSB 9 + #define CS_TREN_TROVC_LSB 9 + #define CS_TREN_TROV4_MSB 8 + #define CS_TREN_TROV4_LSB 8 + #define CS_TREN_TROV3_MSB 7 + #define CS_TREN_TROV3_LSB 7 + #define CS_TREN_TROV2_MSB 6 + #define CS_TREN_TROV2_LSB 6 + #define CS_TREN_TROV1_MSB 5 + #define CS_TREN_TROV1_LSB 5 + #define CS_TREN_TRENC_MSB 4 + #define CS_TREN_TRENC_LSB 4 + #define CS_TREN_TREN4_MSB 3 + #define CS_TREN_TREN4_LSB 3 + #define CS_TREN_TREN3_MSB 2 + #define CS_TREN_TREN3_LSB 2 + #define CS_TREN_TREN2_MSB 1 + #define CS_TREN_TREN2_LSB 1 + #define CS_TREN_TREN1_MSB 0 + #define CS_TREN_TREN1_LSB 0 +#define CS_THSSTO HW_REGISTER_RW( 0x7e802014 ) + #define CS_THSSTO_MASK 0x0000ffff + #define CS_THSSTO_WIDTH 16 + #define CS_THSSTO_RESET 0000000000 + #define CS_THSSTO_THSSTO_MSB 15 + #define CS_THSSTO_THSSTO_LSB 0 +#define CS_THSSET HW_REGISTER_RW( 0x7e802018 ) + #define CS_THSSET_MASK 0x00000fff + #define CS_THSSET_WIDTH 12 + #define CS_THSSET_RESET 0000000000 + #define CS_THSSET_TD_MSB 11 + #define CS_THSSET_TD_LSB 8 + #define CS_THSSET_HSMC_MSB 7 + #define CS_THSSET_HSMC_LSB 0 +#define CS_THSCKTO HW_REGISTER_RW( 0x7e80201c ) + #define CS_THSCKTO_MASK 0x0000ffff + #define CS_THSCKTO_WIDTH 16 + #define CS_THSCKTO_RESET 0000000000 + #define CS_THSCKTO_THSCKTO_MSB 15 + #define CS_THSCKTO_THSCKTO_LSB 0 +#define CS_DBGDPHY HW_REGISTER_RO( 0x7e802080 ) + #define CS_DBGDPHY_MASK 0x000fffff + #define CS_DBGDPHY_WIDTH 20 + #define CS_DBGDPHY__MSB 19 + #define CS_DBGDPHY__LSB 0 +#define CS_DBGMISC HW_REGISTER_RO( 0x7e802084 ) + #define CS_DBGMISC_MASK 0x000001ff + #define CS_DBGMISC_WIDTH 9 + #define CS_DBGMISC__MSB 8 + #define CS_DBGMISC__LSB 0 +#define CS_TRIG HW_REGISTER_RO( 0x7e802088 ) + #define CS_TRIG_MASK 0x000fffff + #define CS_TRIG_WIDTH 20 + #define CS_TRIG__MSB 19 + #define CS_TRIG__LSB 0 +#define CS_SRST HW_REGISTER_RW( 0x7e802090 ) + #define CS_SRST_MASK 0x00000001 + #define CS_SRST_WIDTH 1 + #define CS_SRST__MSB 0 + #define CS_SRST__LSB 0 +#define CS_RDR3 HW_REGISTER_RO( 0x7e802094 ) + #define CS_RDR3_MASK 0x00001fff + #define CS_RDR3_WIDTH 13 + #define CS_RDR3__MSB 12 + #define CS_RDR3__LSB 0 +#define CS_RC0 HW_REGISTER_RW( 0x7e802100 ) + #define CS_RC0_MASK 0x1fff1f07 + #define CS_RC0_WIDTH 29 + #define CS_RC0_RESET 0000000000 + #define CS_RC0_LCIE_MSB 28 + #define CS_RC0_LCIE_LSB 16 + #define CS_RC0_GSPIE_MSB 12 + #define CS_RC0_GSPIE_LSB 12 + #define CS_RC0_LEIE_MSB 11 + #define CS_RC0_LEIE_LSB 11 + #define CS_RC0_LSIE_MSB 10 + #define CS_RC0_LSIE_LSB 10 + #define CS_RC0_FEIE_MSB 9 + #define CS_RC0_FEIE_LSB 9 + #define CS_RC0_FSIE_MSB 8 + #define CS_RC0_FSIE_LSB 8 + #define CS_RC0_VC_MSB 2 + #define CS_RC0_VC_LSB 1 + #define CS_RC0_CHEN_MSB 0 + #define CS_RC0_CHEN_LSB 0 +#define CS_RPC0 HW_REGISTER_RW( 0x7e802104 ) + #define CS_RPC0_MASK 0x01ff1f1f + #define CS_RPC0_WIDTH 25 + #define CS_RPC0_RESET 0x00200000 + #define CS_RPC0_EBL_MSB 24 + #define CS_RPC0_EBL_LSB 16 + #define CS_RPC0_EAP_MSB 12 + #define CS_RPC0_EAP_LSB 12 + #define CS_RPC0_EP_MSB 11 + #define CS_RPC0_EP_LSB 8 + #define CS_RPC0_DAP_MSB 4 + #define CS_RPC0_DAP_LSB 4 + #define CS_RPC0_DP_MSB 3 + #define CS_RPC0_DP_LSB 0 +#define CS_RS0 HW_REGISTER_RW( 0x7e802108 ) + #define CS_RS0_MASK 0x01ffffff + #define CS_RS0_WIDTH 25 + #define CS_RS0_RESET 0000000000 + #define CS_RS0_DBO_MSB 24 + #define CS_RS0_DBO_LSB 24 + #define CS_RS0_IBO_MSB 23 + #define CS_RS0_IBO_LSB 23 + #define CS_RS0_CRCE_MSB 22 + #define CS_RS0_CRCE_LSB 22 + #define CS_RS0_LCI_MSB 21 + #define CS_RS0_LCI_LSB 21 + #define CS_RS0_GSPI_MSB 20 + #define CS_RS0_GSPI_LSB 20 + #define CS_RS0_LEI_MSB 19 + #define CS_RS0_LEI_LSB 19 + #define CS_RS0_LSI_MSB 18 + #define CS_RS0_LSI_LSB 18 + #define CS_RS0_FEI_MSB 17 + #define CS_RS0_FEI_LSB 17 + #define CS_RS0_FSI_MSB 16 + #define CS_RS0_FSI_LSB 16 + #define CS_RS0_FNUM_MSB 15 + #define CS_RS0_FNUM_LSB 0 +#define CS_RSA0 HW_REGISTER_RW( 0x7e80210c ) + #define CS_RSA0_MASK 0x3fffffff + #define CS_RSA0_WIDTH 30 + #define CS_RSA0_RESET 0000000000 + #define CS_RSA0__MSB 29 + #define CS_RSA0__LSB 0 +#define CS_REA0 HW_REGISTER_RW( 0x7e802110 ) + #define CS_REA0_MASK 0x3fffffff + #define CS_REA0_WIDTH 30 + #define CS_REA0_RESET 0000000000 + #define CS_REA0__MSB 29 + #define CS_REA0__LSB 0 +#define CS_RWP0 HW_REGISTER_RO( 0x7e802114 ) + #define CS_RWP0_MASK 0x3fffffff + #define CS_RWP0_WIDTH 30 + #define CS_RWP0__MSB 29 + #define CS_RWP0__LSB 0 +#define CS_RBC0 HW_REGISTER_RO( 0x7e802118 ) + #define CS_RBC0_MASK 0xffffffff + #define CS_RBC0_WIDTH 32 + #define CS_RBC0__MSB 31 + #define CS_RBC0__LSB 0 +#define CS_RLS0 HW_REGISTER_RW( 0x7e80211c ) + #define CS_RLS0_MASK 0x0000ffff + #define CS_RLS0_WIDTH 16 + #define CS_RLS0_RESET 0000000000 + #define CS_RLS0__MSB 15 + #define CS_RLS0__LSB 0 +#define CS_RDSA0 HW_REGISTER_RW( 0x7e802120 ) + #define CS_RDSA0_MASK 0x3fffffff + #define CS_RDSA0_WIDTH 30 + #define CS_RDSA0_RESET 0000000000 + #define CS_RDSA0__MSB 29 + #define CS_RDSA0__LSB 0 +#define CS_RDEA0 HW_REGISTER_RW( 0x7e802124 ) + #define CS_RDEA0_MASK 0x3fffffff + #define CS_RDEA0_WIDTH 30 + #define CS_RDEA0_RESET 0000000000 + #define CS_RDEA0__MSB 29 + #define CS_RDEA0__LSB 0 +#define CS_RDS0 HW_REGISTER_RW( 0x7e802128 ) + #define CS_RDS0_MASK 0x0000ffff + #define CS_RDS0_WIDTH 16 + #define CS_RDS0_RESET 0000000000 + #define CS_RDS0__MSB 15 + #define CS_RDS0__LSB 0 +#define CS_DTOV0 HW_REGISTER_RW( 0x7e80212c ) + #define CS_DTOV0_MASK 0x00007f7f + #define CS_DTOV0_WIDTH 15 + #define CS_DTOV0_RESET 0000000000 + #define CS_DTOV0_IMEN_MSB 14 + #define CS_DTOV0_IMEN_LSB 14 + #define CS_DTOV0_IMDT_MSB 13 + #define CS_DTOV0_IMDT_LSB 8 + #define CS_DTOV0_EMEN_MSB 6 + #define CS_DTOV0_EMEN_LSB 6 + #define CS_DTOV0_EMDT_MSB 5 + #define CS_DTOV0_EMDT_LSB 0 +#define CS_RC1 HW_REGISTER_RW( 0x7e802200 ) + #define CS_RC1_MASK 0x1fff1f07 + #define CS_RC1_WIDTH 29 + #define CS_RC1_RESET 0000000000 + #define CS_RC1_LCIE_MSB 28 + #define CS_RC1_LCIE_LSB 16 + #define CS_RC1_GSPIE_MSB 12 + #define CS_RC1_GSPIE_LSB 12 + #define CS_RC1_LEIE_MSB 11 + #define CS_RC1_LEIE_LSB 11 + #define CS_RC1_LSIE_MSB 10 + #define CS_RC1_LSIE_LSB 10 + #define CS_RC1_FEIE_MSB 9 + #define CS_RC1_FEIE_LSB 9 + #define CS_RC1_FSIE_MSB 8 + #define CS_RC1_FSIE_LSB 8 + #define CS_RC1_VC_MSB 2 + #define CS_RC1_VC_LSB 1 + #define CS_RC1_CHEN_MSB 0 + #define CS_RC1_CHEN_LSB 0 +#define CS_RPC1 HW_REGISTER_RW( 0x7e802204 ) + #define CS_RPC1_MASK 0x01ff1f1f + #define CS_RPC1_WIDTH 25 + #define CS_RPC1_RESET 0x00200000 + #define CS_RPC1_EBL_MSB 24 + #define CS_RPC1_EBL_LSB 16 + #define CS_RPC1_EAP_MSB 12 + #define CS_RPC1_EAP_LSB 12 + #define CS_RPC1_EP_MSB 11 + #define CS_RPC1_EP_LSB 8 + #define CS_RPC1_DAP_MSB 4 + #define CS_RPC1_DAP_LSB 4 + #define CS_RPC1_DP_MSB 3 + #define CS_RPC1_DP_LSB 0 +#define CS_RS1 HW_REGISTER_RW( 0x7e802208 ) + #define CS_RS1_MASK 0x01ffffff + #define CS_RS1_WIDTH 25 + #define CS_RS1_RESET 0000000000 + #define CS_RS1_DBO_MSB 24 + #define CS_RS1_DBO_LSB 24 + #define CS_RS1_IBO_MSB 23 + #define CS_RS1_IBO_LSB 23 + #define CS_RS1_CRCE_MSB 22 + #define CS_RS1_CRCE_LSB 22 + #define CS_RS1_LCI_MSB 21 + #define CS_RS1_LCI_LSB 21 + #define CS_RS1_GSPI_MSB 20 + #define CS_RS1_GSPI_LSB 20 + #define CS_RS1_LEI_MSB 19 + #define CS_RS1_LEI_LSB 19 + #define CS_RS1_LSI_MSB 18 + #define CS_RS1_LSI_LSB 18 + #define CS_RS1_FEI_MSB 17 + #define CS_RS1_FEI_LSB 17 + #define CS_RS1_FSI_MSB 16 + #define CS_RS1_FSI_LSB 16 + #define CS_RS1_FNUM_MSB 15 + #define CS_RS1_FNUM_LSB 0 +#define CS_RSA1 HW_REGISTER_RW( 0x7e80220c ) + #define CS_RSA1_MASK 0x3fffffff + #define CS_RSA1_WIDTH 30 + #define CS_RSA1_RESET 0000000000 + #define CS_RSA1__MSB 29 + #define CS_RSA1__LSB 0 +#define CS_REA1 HW_REGISTER_RW( 0x7e802210 ) + #define CS_REA1_MASK 0x3fffffff + #define CS_REA1_WIDTH 30 + #define CS_REA1_RESET 0000000000 + #define CS_REA1__MSB 29 + #define CS_REA1__LSB 0 +#define CS_RWP1 HW_REGISTER_RO( 0x7e802214 ) + #define CS_RWP1_MASK 0x3fffffff + #define CS_RWP1_WIDTH 30 + #define CS_RWP1__MSB 29 + #define CS_RWP1__LSB 0 +#define CS_RBC1 HW_REGISTER_RO( 0x7e802218 ) + #define CS_RBC1_MASK 0xffffffff + #define CS_RBC1_WIDTH 32 + #define CS_RBC1__MSB 31 + #define CS_RBC1__LSB 0 +#define CS_RLS1 HW_REGISTER_RW( 0x7e80221c ) + #define CS_RLS1_MASK 0x0000ffff + #define CS_RLS1_WIDTH 16 + #define CS_RLS1_RESET 0000000000 + #define CS_RLS1__MSB 15 + #define CS_RLS1__LSB 0 +#define CS_RDSA1 HW_REGISTER_RW( 0x7e802220 ) + #define CS_RDSA1_MASK 0x3fffffff + #define CS_RDSA1_WIDTH 30 + #define CS_RDSA1_RESET 0000000000 + #define CS_RDSA1__MSB 29 + #define CS_RDSA1__LSB 0 +#define CS_RDEA1 HW_REGISTER_RW( 0x7e802224 ) + #define CS_RDEA1_MASK 0x3fffffff + #define CS_RDEA1_WIDTH 30 + #define CS_RDEA1_RESET 0000000000 + #define CS_RDEA1__MSB 29 + #define CS_RDEA1__LSB 0 +#define CS_RDS1 HW_REGISTER_RW( 0x7e802228 ) + #define CS_RDS1_MASK 0x0000ffff + #define CS_RDS1_WIDTH 16 + #define CS_RDS1_RESET 0000000000 + #define CS_RDS1__MSB 15 + #define CS_RDS1__LSB 0 +#define CS_DTOV1 HW_REGISTER_RW( 0x7e80222c ) + #define CS_DTOV1_MASK 0x00007f7f + #define CS_DTOV1_WIDTH 15 + #define CS_DTOV1_RESET 0000000000 + #define CS_DTOV1_IMEN_MSB 14 + #define CS_DTOV1_IMEN_LSB 14 + #define CS_DTOV1_IMDT_MSB 13 + #define CS_DTOV1_IMDT_LSB 8 + #define CS_DTOV1_EMEN_MSB 6 + #define CS_DTOV1_EMEN_LSB 6 + #define CS_DTOV1_EMDT_MSB 5 + #define CS_DTOV1_EMDT_LSB 0 diff --git a/bcm2708_chip/dpi.h b/bcm2708_chip/dpi.h new file mode 100755 index 0000000..130986c --- /dev/null +++ b/bcm2708_chip/dpi.h @@ -0,0 +1,7 @@ +// This file was generated by the create_regs script +#define DPI_BASE 0x7e208000 +#define DPI_APB_ID 0x44504920 +#define DPI_C HW_REGISTER_RW( 0x7e208000 ) + #define DPI_C_MASK 0x0000ffff + #define DPI_C_WIDTH 16 + #define DPI_C_RESET 0x00003000 diff --git a/bcm2708_chip/dsi.h b/bcm2708_chip/dsi.h new file mode 100755 index 0000000..1dfb178 --- /dev/null +++ b/bcm2708_chip/dsi.h @@ -0,0 +1,178 @@ +// This file was generated by the create_regs script +#define DSI0_BASE 0x7e209000 +#define DSI0_APB_ID 0x00647369 +#define DSI0_CTRL HW_REGISTER_RW( 0x7e209000 ) + #define DSI0_CTRL_MASK 0x00000007 + #define DSI0_CTRL_WIDTH 3 + #define DSI0_CTRL_RESET 0000000000 + #define DSI0_CTRL_CTRL2_BITS 2:2 + #define DSI0_CTRL_CTRL2_SET 0x00000004 + #define DSI0_CTRL_CTRL2_CLR 0xfffffffb + #define DSI0_CTRL_CTRL2_MSB 2 + #define DSI0_CTRL_CTRL2_LSB 2 + #define DSI0_CTRL_CTRL1_BITS 1:1 + #define DSI0_CTRL_CTRL1_SET 0x00000002 + #define DSI0_CTRL_CTRL1_CLR 0xfffffffd + #define DSI0_CTRL_CTRL1_MSB 1 + #define DSI0_CTRL_CTRL1_LSB 1 + #define DSI0_CTRL_CTRL0_BITS 0:0 + #define DSI0_CTRL_CTRL0_SET 0x00000001 + #define DSI0_CTRL_CTRL0_CLR 0xfffffffe + #define DSI0_CTRL_CTRL0_MSB 0 + #define DSI0_CTRL_CTRL0_LSB 0 +#define DSI0_CMD_PKTC HW_REGISTER_RW( 0x7e209004 ) + #define DSI0_CMD_PKTC_MASK 0xffffffff + #define DSI0_CMD_PKTC_WIDTH 32 + #define DSI0_CMD_PKTC_RESET 0000000000 +#define DSI0_CMD_PKTH HW_REGISTER_RW( 0x7e209008 ) + #define DSI0_CMD_PKTH_MASK 0xffffffff + #define DSI0_CMD_PKTH_WIDTH 32 + #define DSI0_CMD_PKTH_RESET 0000000000 +#define DSI0_RX1_PKTH HW_REGISTER_RO( 0x7e20900c ) + #define DSI0_RX1_PKTH_MASK 0xffffffff + #define DSI0_RX1_PKTH_WIDTH 32 +#define DSI0_RX2_PKTH HW_REGISTER_RO( 0x7e209010 ) + #define DSI0_RX2_PKTH_MASK 0xffffffff + #define DSI0_RX2_PKTH_WIDTH 32 +#define DSI0_CMD_DATAF HW_REGISTER_RW( 0x7e209014 ) + #define DSI0_CMD_DATAF_MASK 0x000000ff + #define DSI0_CMD_DATAF_WIDTH 8 +#define DSI0_DISP0_CTR HW_REGISTER_RW( 0x7e209018 ) + #define DSI0_DISP0_CTR_MASK 0xffffffff + #define DSI0_DISP0_CTR_WIDTH 32 + #define DSI0_DISP0_CTR_RESET 0000000000 +#define DSI0_DISP1_CTR HW_REGISTER_RW( 0x7e20901c ) + #define DSI0_DISP1_CTR_MASK 0xffffffff + #define DSI0_DISP1_CTR_WIDTH 32 + #define DSI0_DISP1_CTR_RESET 0000000000 +#define DSI0_PIX_FIFO HW_REGISTER_RW( 0x7e209020 ) + #define DSI0_PIX_FIFO_MASK 0xffffffff + #define DSI0_PIX_FIFO_WIDTH 32 +#define DSI0_INT_STAT HW_REGISTER_RW( 0x7e209024 ) + #define DSI0_INT_STAT_MASK 0xffffffff + #define DSI0_INT_STAT_WIDTH 32 +#define DSI0_INT_EN HW_REGISTER_RW( 0x7e209028 ) + #define DSI0_INT_EN_MASK 0x0fffffff + #define DSI0_INT_EN_WIDTH 28 + #define DSI0_INT_EN_RESET 0000000000 +#define DSI0_STAT HW_REGISTER_RW( 0x7e20902c ) + #define DSI0_STAT_MASK 0xffffffff + #define DSI0_STAT_WIDTH 32 +#define DSI0_HSTX_TO_C HW_REGISTER_RW( 0x7e209030 ) + #define DSI0_HSTX_TO_C_MASK 0x00ffffff + #define DSI0_HSTX_TO_C_WIDTH 24 + #define DSI0_HSTX_TO_C_RESET 0000000000 +#define DSI0_LPRX_TO_C HW_REGISTER_RW( 0x7e209034 ) + #define DSI0_LPRX_TO_C_MASK 0xffffffff + #define DSI0_LPRX_TO_C_WIDTH 32 + #define DSI0_LPRX_TO_C_RESET 0000000000 +#define DSI0_TA_TO_CNT HW_REGISTER_RW( 0x7e209038 ) + #define DSI0_TA_TO_CNT_MASK 0xffffffff + #define DSI0_TA_TO_CNT_WIDTH 32 + #define DSI0_TA_TO_CNT_RESET 0000000000 +#define DSI0_PR_TO_CNT HW_REGISTER_RW( 0x7e20903c ) + #define DSI0_PR_TO_CNT_MASK 0xffffffff + #define DSI0_PR_TO_CNT_WIDTH 32 + #define DSI0_PR_TO_CNT_RESET 0000000000 +#define DSI0_PHYC HW_REGISTER_RW( 0x7e209040 ) + #define DSI0_PHYC_MASK 0x0003f777 + #define DSI0_PHYC_WIDTH 18 + #define DSI0_PHYC_RESET 0000000000 + #define DSI0_PHYC_dsi_esc_lpdt_BITS 17:12 + #define DSI0_PHYC_dsi_esc_lpdt_SET 0x0003f000 + #define DSI0_PHYC_dsi_esc_lpdt_CLR 0xfffc0fff + #define DSI0_PHYC_dsi_esc_lpdt_MSB 17 + #define DSI0_PHYC_dsi_esc_lpdt_LSB 12 + #define DSI0_PHYC_txhsclk_cont_sync_BITS 10:10 + #define DSI0_PHYC_txhsclk_cont_sync_SET 0x00000400 + #define DSI0_PHYC_txhsclk_cont_sync_CLR 0xfffffbff + #define DSI0_PHYC_txhsclk_cont_sync_MSB 10 + #define DSI0_PHYC_txhsclk_cont_sync_LSB 10 + #define DSI0_PHYC_txulps_clk_sync_BITS 9:9 + #define DSI0_PHYC_txulps_clk_sync_SET 0x00000200 + #define DSI0_PHYC_txulps_clk_sync_CLR 0xfffffdff + #define DSI0_PHYC_txulps_clk_sync_MSB 9 + #define DSI0_PHYC_txulps_clk_sync_LSB 9 + #define DSI0_PHYC_clane_hsen_sync_BITS 8:8 + #define DSI0_PHYC_clane_hsen_sync_SET 0x00000100 + #define DSI0_PHYC_clane_hsen_sync_CLR 0xfffffeff + #define DSI0_PHYC_clane_hsen_sync_MSB 8 + #define DSI0_PHYC_clane_hsen_sync_LSB 8 + #define DSI0_PHYC_txulpshs_1_sync_BITS 6:6 + #define DSI0_PHYC_txulpshs_1_sync_SET 0x00000040 + #define DSI0_PHYC_txulpshs_1_sync_CLR 0xffffffbf + #define DSI0_PHYC_txulpshs_1_sync_MSB 6 + #define DSI0_PHYC_txulpshs_1_sync_LSB 6 + #define DSI0_PHYC_dlane_hsen_1_sync_BITS 5:5 + #define DSI0_PHYC_dlane_hsen_1_sync_SET 0x00000020 + #define DSI0_PHYC_dlane_hsen_1_sync_CLR 0xffffffdf + #define DSI0_PHYC_dlane_hsen_1_sync_MSB 5 + #define DSI0_PHYC_dlane_hsen_1_sync_LSB 5 + #define DSI0_PHYC_unused_BITS 4:4 + #define DSI0_PHYC_unused_SET 0x00000010 + #define DSI0_PHYC_unused_CLR 0xffffffef + #define DSI0_PHYC_unused_MSB 4 + #define DSI0_PHYC_unused_LSB 4 + #define DSI0_PHYC_forcehsstop_sync_BITS 2:2 + #define DSI0_PHYC_forcehsstop_sync_SET 0x00000004 + #define DSI0_PHYC_forcehsstop_sync_CLR 0xfffffffb + #define DSI0_PHYC_forcehsstop_sync_MSB 2 + #define DSI0_PHYC_forcehsstop_sync_LSB 2 + #define DSI0_PHYC_txulpshs_0_sync_BITS 1:1 + #define DSI0_PHYC_txulpshs_0_sync_SET 0x00000002 + #define DSI0_PHYC_txulpshs_0_sync_CLR 0xfffffffd + #define DSI0_PHYC_txulpshs_0_sync_MSB 1 + #define DSI0_PHYC_txulpshs_0_sync_LSB 1 + #define DSI0_PHYC_dlane_hsen_0_sync_BITS 0:0 + #define DSI0_PHYC_dlane_hsen_0_sync_SET 0x00000001 + #define DSI0_PHYC_dlane_hsen_0_sync_CLR 0xfffffffe + #define DSI0_PHYC_dlane_hsen_0_sync_MSB 0 + #define DSI0_PHYC_dlane_hsen_0_sync_LSB 0 +#define DSI0_HS_CLT0 HW_REGISTER_RW( 0x7e209044 ) + #define DSI0_HS_CLT0_MASK 0xfffffffc + #define DSI0_HS_CLT0_WIDTH 32 + #define DSI0_HS_CLT0_RESET 0000000000 +#define DSI0_HS_CLT1 HW_REGISTER_RW( 0x7e209048 ) + #define DSI0_HS_CLT1_MASK 0x000003fc + #define DSI0_HS_CLT1_WIDTH 10 + #define DSI0_HS_CLT1_RESET 0000000000 +#define DSI0_HS_CLT2 HW_REGISTER_RW( 0x7e20904c ) + #define DSI0_HS_CLT2_MASK 0x000003fc + #define DSI0_HS_CLT2_WIDTH 10 + #define DSI0_HS_CLT2_RESET 0000000000 +#define DSI0_HS_DLT3 HW_REGISTER_RW( 0x7e209050 ) + #define DSI0_HS_DLT3_MASK 0x000003fc + #define DSI0_HS_DLT3_WIDTH 10 + #define DSI0_HS_DLT3_RESET 0000000000 +#define DSI0_HS_DLT4 HW_REGISTER_RW( 0x7e209054 ) + #define DSI0_HS_DLT4_MASK 0x000003fc + #define DSI0_HS_DLT4_WIDTH 10 + #define DSI0_HS_DLT4_RESET 0000000000 +#define DSI0_HS_DLT5 HW_REGISTER_RW( 0x7e209058 ) + #define DSI0_HS_DLT5_MASK 0x000003fc + #define DSI0_HS_DLT5_WIDTH 10 + #define DSI0_HS_DLT5_RESET 0000000000 +#define DSI0_LP_DLT6 HW_REGISTER_RW( 0x7e20905c ) + #define DSI0_LP_DLT6_MASK 0x000003fc + #define DSI0_LP_DLT6_WIDTH 10 + #define DSI0_LP_DLT6_RESET 0000000000 +#define DSI0_LP_DLT7 HW_REGISTER_RW( 0x7e209060 ) + #define DSI0_LP_DLT7_MASK 0x000003fc + #define DSI0_LP_DLT7_WIDTH 10 + #define DSI0_LP_DLT7_RESET 0000000000 +#define DSI0_PHY_AFEC0 HW_REGISTER_RW( 0x7e209064 ) + #define DSI0_PHY_AFEC0_MASK 0x000000ff + #define DSI0_PHY_AFEC0_WIDTH 8 + #define DSI0_PHY_AFEC0_RESET 0000000000 +#define DSI0_PHY_AFEC1 HW_REGISTER_RW( 0x7e209068 ) + #define DSI0_PHY_AFEC1_MASK 0xffffffff + #define DSI0_PHY_AFEC1_WIDTH 32 + #define DSI0_PHY_AFEC1_RESET 0000000000 +#define DSI0_TST_SEL HW_REGISTER_RW( 0x7e20906c ) + #define DSI0_TST_SEL_MASK 0x000000ff + #define DSI0_TST_SEL_WIDTH 8 + #define DSI0_TST_SEL_RESET 0000000000 +#define DSI0_TST_MON HW_REGISTER_RW( 0x7e209070 ) + #define DSI0_TST_MON_MASK 0x000000ff + #define DSI0_TST_MON_WIDTH 8 + #define DSI0_TST_MON_RESET 0000000000 diff --git a/bcm2708_chip/dsi4.h b/bcm2708_chip/dsi4.h new file mode 100755 index 0000000..a326f50 --- /dev/null +++ b/bcm2708_chip/dsi4.h @@ -0,0 +1,124 @@ +// This file was generated by the create_regs script +#define DSI1_BASE 0x7e700000 +#define DSI1_APB_ID 0x64736934 +#define DSI1_CTRL HW_REGISTER_RW( 0x7e700000 ) + #define DSI1_CTRL_MASK 0xffffffff + #define DSI1_CTRL_WIDTH 32 + #define DSI1_CTRL_RESET 0000000000 +#define DSI1_TXPKT1_C HW_REGISTER_RW( 0x7e700004 ) + #define DSI1_TXPKT1_C_MASK 0xffffffff + #define DSI1_TXPKT1_C_WIDTH 32 + #define DSI1_TXPKT1_C_RESET 0000000000 +#define DSI1_TXPKT1_H HW_REGISTER_RW( 0x7e700008 ) + #define DSI1_TXPKT1_H_MASK 0xffffffff + #define DSI1_TXPKT1_H_WIDTH 32 + #define DSI1_TXPKT1_H_RESET 0000000000 +#define DSI1_TXPKT2_C HW_REGISTER_RW( 0x7e70000c ) + #define DSI1_TXPKT2_C_MASK 0xffffffff + #define DSI1_TXPKT2_C_WIDTH 32 + #define DSI1_TXPKT2_C_RESET 0000000000 +#define DSI1_TXPKT2_H HW_REGISTER_RW( 0x7e700010 ) + #define DSI1_TXPKT2_H_MASK 0xffffffff + #define DSI1_TXPKT2_H_WIDTH 32 + #define DSI1_TXPKT2_H_RESET 0000000000 +#define DSI1_RXPKT1_H HW_REGISTER_RO( 0x7e700014 ) + #define DSI1_RXPKT1_H_MASK 0xffffffff + #define DSI1_RXPKT1_H_WIDTH 32 +#define DSI1_RXPKT2_H HW_REGISTER_RO( 0x7e700018 ) + #define DSI1_RXPKT2_H_MASK 0xffffffff + #define DSI1_RXPKT2_H_WIDTH 32 +#define DSI1_TXPKT_CMD_FIFO HW_REGISTER_RW( 0x7e70001c ) + #define DSI1_TXPKT_CMD_FIFO_MASK 0x000000ff + #define DSI1_TXPKT_CMD_FIFO_WIDTH 8 +#define DSI1_TXPKT_PIXD_FIFO HW_REGISTER_RW( 0x7e700020 ) + #define DSI1_TXPKT_PIXD_FIFO_MASK 0xffffffff + #define DSI1_TXPKT_PIXD_FIFO_WIDTH 32 + #define DSI1_TXPKT_PIXD_FIFO_RESET 0000000000 +#define DSI1_RXPKT_FIFO HW_REGISTER_RW( 0x7e700024 ) + #define DSI1_RXPKT_FIFO_MASK 0xffffffff + #define DSI1_RXPKT_FIFO_WIDTH 32 + #define DSI1_RXPKT_FIFO_RESET 0000000000 +#define DSI1_DISP0_CTRL HW_REGISTER_RW( 0x7e700028 ) + #define DSI1_DISP0_CTRL_MASK 0xffffffff + #define DSI1_DISP0_CTRL_WIDTH 32 +#define DSI1_DISP1_CTRL HW_REGISTER_RW( 0x7e70002c ) + #define DSI1_DISP1_CTRL_MASK 0xffffffff + #define DSI1_DISP1_CTRL_WIDTH 32 +#define DSI1_INT_STAT HW_REGISTER_RW( 0x7e700030 ) + #define DSI1_INT_STAT_MASK 0xffffffff + #define DSI1_INT_STAT_WIDTH 32 +#define DSI1_INT_EN HW_REGISTER_RW( 0x7e700034 ) + #define DSI1_INT_EN_MASK 0x0fffffff + #define DSI1_INT_EN_WIDTH 28 + #define DSI1_INT_EN_RESET 0000000000 +#define DSI1_STAT HW_REGISTER_RW( 0x7e700038 ) + #define DSI1_STAT_MASK 0xffffffff + #define DSI1_STAT_WIDTH 32 +#define DSI1_HSTX_TO_CNT HW_REGISTER_RW( 0x7e70003c ) + #define DSI1_HSTX_TO_CNT_MASK 0x00ffffff + #define DSI1_HSTX_TO_CNT_WIDTH 24 + #define DSI1_HSTX_TO_CNT_RESET 0000000000 +#define DSI1_LPRX_TO_CNT HW_REGISTER_RW( 0x7e700040 ) + #define DSI1_LPRX_TO_CNT_MASK 0xffffffff + #define DSI1_LPRX_TO_CNT_WIDTH 32 + #define DSI1_LPRX_TO_CNT_RESET 0000000000 +#define DSI1_TA_TO_CNT HW_REGISTER_RW( 0x7e700044 ) + #define DSI1_TA_TO_CNT_MASK 0xffffffff + #define DSI1_TA_TO_CNT_WIDTH 32 + #define DSI1_TA_TO_CNT_RESET 0000000000 +#define DSI1_PR_TO_CNT HW_REGISTER_RW( 0x7e700048 ) + #define DSI1_PR_TO_CNT_MASK 0xffffffff + #define DSI1_PR_TO_CNT_WIDTH 32 + #define DSI1_PR_TO_CNT_RESET 0000000000 +#define DSI1_PHYC HW_REGISTER_RW( 0x7e70004c ) + #define DSI1_PHYC_MASK 0xffffffff + #define DSI1_PHYC_WIDTH 32 + #define DSI1_PHYC_RESET 0000000000 +#define DSI1_HS_CLT0 HW_REGISTER_RW( 0x7e700050 ) + #define DSI1_HS_CLT0_MASK 0xffffffff + #define DSI1_HS_CLT0_WIDTH 32 + #define DSI1_HS_CLT0_RESET 0000000000 +#define DSI1_HS_CLT1 HW_REGISTER_RW( 0x7e700054 ) + #define DSI1_HS_CLT1_MASK 0xffffffff + #define DSI1_HS_CLT1_WIDTH 32 + #define DSI1_HS_CLT1_RESET 0000000000 +#define DSI1_HS_CLT2 HW_REGISTER_RW( 0x7e700058 ) + #define DSI1_HS_CLT2_MASK 0xffffffff + #define DSI1_HS_CLT2_WIDTH 32 + #define DSI1_HS_CLT2_RESET 0000000000 +#define DSI1_HS_DLT3 HW_REGISTER_RW( 0x7e70005c ) + #define DSI1_HS_DLT3_MASK 0xffffffff + #define DSI1_HS_DLT3_WIDTH 32 + #define DSI1_HS_DLT3_RESET 0000000000 +#define DSI1_HS_DLT4 HW_REGISTER_RW( 0x7e700060 ) + #define DSI1_HS_DLT4_MASK 0xffffffff + #define DSI1_HS_DLT4_WIDTH 32 + #define DSI1_HS_DLT4_RESET 0000000000 +#define DSI1_HS_DLT5 HW_REGISTER_RW( 0x7e700064 ) + #define DSI1_HS_DLT5_MASK 0xffffffff + #define DSI1_HS_DLT5_WIDTH 32 + #define DSI1_HS_DLT5_RESET 0000000000 +#define DSI1_LP_DLT6 HW_REGISTER_RW( 0x7e700068 ) + #define DSI1_LP_DLT6_MASK 0xffffffff + #define DSI1_LP_DLT6_WIDTH 32 + #define DSI1_LP_DLT6_RESET 0000000000 +#define DSI1_LP_DLT7 HW_REGISTER_RW( 0x7e70006c ) + #define DSI1_LP_DLT7_MASK 0xffffffff + #define DSI1_LP_DLT7_WIDTH 32 + #define DSI1_LP_DLT7_RESET 0000000000 +#define DSI1_PHY_AFEC0 HW_REGISTER_RW( 0x7e700070 ) + #define DSI1_PHY_AFEC0_MASK 0xffffffff + #define DSI1_PHY_AFEC0_WIDTH 32 + #define DSI1_PHY_AFEC0_RESET 0000000000 +#define DSI1_PHY_AFEC1 HW_REGISTER_RW( 0x7e700074 ) + #define DSI1_PHY_AFEC1_MASK 0xffffffff + #define DSI1_PHY_AFEC1_WIDTH 32 + #define DSI1_PHY_AFEC1_RESET 0000000000 +#define DSI1_TST_SEL HW_REGISTER_RW( 0x7e700078 ) + #define DSI1_TST_SEL_MASK 0xffffffff + #define DSI1_TST_SEL_WIDTH 32 + #define DSI1_TST_SEL_RESET 0000000000 +#define DSI1_TST_MON HW_REGISTER_RW( 0x7e70007c ) + #define DSI1_TST_MON_MASK 0xffffffff + #define DSI1_TST_MON_WIDTH 32 + #define DSI1_TST_MON_RESET 0000000000 diff --git a/bcm2708_chip/emmc.h b/bcm2708_chip/emmc.h new file mode 100755 index 0000000..54b4336 --- /dev/null +++ b/bcm2708_chip/emmc.h @@ -0,0 +1,1276 @@ +// This file was generated by the create_regs script +#define EMMC_BASE 0x7e300000 +#define EMMC_ARG2 HW_REGISTER_RW( 0x7e300000 ) + #define EMMC_ARG2_MASK 0xffffffff + #define EMMC_ARG2_WIDTH 32 + #define EMMC_ARG2_RESET 0000000000 +#define EMMC_BLKSIZECNT HW_REGISTER_RW( 0x7e300004 ) + #define EMMC_BLKSIZECNT_MASK 0xffffffff + #define EMMC_BLKSIZECNT_WIDTH 32 + #define EMMC_BLKSIZECNT_RESET 0000000000 + #define EMMC_BLKSIZECNT_BLKCNT_BITS 31:16 + #define EMMC_BLKSIZECNT_BLKCNT_SET 0xffff0000 + #define EMMC_BLKSIZECNT_BLKCNT_CLR 0x0000ffff + #define EMMC_BLKSIZECNT_BLKCNT_MSB 31 + #define EMMC_BLKSIZECNT_BLKCNT_LSB 16 + #define EMMC_BLKSIZECNT_BLKSIZE_MS1_BITS 15:15 + #define EMMC_BLKSIZECNT_BLKSIZE_MS1_SET 0x00008000 + #define EMMC_BLKSIZECNT_BLKSIZE_MS1_CLR 0xffff7fff + #define EMMC_BLKSIZECNT_BLKSIZE_MS1_MSB 15 + #define EMMC_BLKSIZECNT_BLKSIZE_MS1_LSB 15 + #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_BITS 14:12 + #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_SET 0x00007000 + #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_CLR 0xffff8fff + #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_MSB 14 + #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_LSB 12 + #define EMMC_BLKSIZECNT_BLKSIZE_BITS 11:0 + #define EMMC_BLKSIZECNT_BLKSIZE_SET 0x00000fff + #define EMMC_BLKSIZECNT_BLKSIZE_CLR 0xfffff000 + #define EMMC_BLKSIZECNT_BLKSIZE_MSB 11 + #define EMMC_BLKSIZECNT_BLKSIZE_LSB 0 +#define EMMC_ARG1 HW_REGISTER_RW( 0x7e300008 ) + #define EMMC_ARG1_MASK 0xffffffff + #define EMMC_ARG1_WIDTH 32 + #define EMMC_ARG1_RESET 0000000000 +#define EMMC_CMDTM HW_REGISTER_RW( 0x7e30000c ) + #define EMMC_CMDTM_MASK 0x3ffb003f + #define EMMC_CMDTM_WIDTH 30 + #define EMMC_CMDTM_RESET 0000000000 + #define EMMC_CMDTM_CMD_INDEX_BITS 29:24 + #define EMMC_CMDTM_CMD_INDEX_SET 0x3f000000 + #define EMMC_CMDTM_CMD_INDEX_CLR 0xc0ffffff + #define EMMC_CMDTM_CMD_INDEX_MSB 29 + #define EMMC_CMDTM_CMD_INDEX_LSB 24 + #define EMMC_CMDTM_CMD_TYPE_BITS 23:22 + #define EMMC_CMDTM_CMD_TYPE_SET 0x00c00000 + #define EMMC_CMDTM_CMD_TYPE_CLR 0xff3fffff + #define EMMC_CMDTM_CMD_TYPE_MSB 23 + #define EMMC_CMDTM_CMD_TYPE_LSB 22 + #define EMMC_CMDTM_CMD_ISDATA_BITS 21:21 + #define EMMC_CMDTM_CMD_ISDATA_SET 0x00200000 + #define EMMC_CMDTM_CMD_ISDATA_CLR 0xffdfffff + #define EMMC_CMDTM_CMD_ISDATA_MSB 21 + #define EMMC_CMDTM_CMD_ISDATA_LSB 21 + #define EMMC_CMDTM_CMD_IXCHK_EN_BITS 20:20 + #define EMMC_CMDTM_CMD_IXCHK_EN_SET 0x00100000 + #define EMMC_CMDTM_CMD_IXCHK_EN_CLR 0xffefffff + #define EMMC_CMDTM_CMD_IXCHK_EN_MSB 20 + #define EMMC_CMDTM_CMD_IXCHK_EN_LSB 20 + #define EMMC_CMDTM_CMD_CRCCHK_EN_BITS 19:19 + #define EMMC_CMDTM_CMD_CRCCHK_EN_SET 0x00080000 + #define EMMC_CMDTM_CMD_CRCCHK_EN_CLR 0xfff7ffff + #define EMMC_CMDTM_CMD_CRCCHK_EN_MSB 19 + #define EMMC_CMDTM_CMD_CRCCHK_EN_LSB 19 + #define EMMC_CMDTM_CMD_RSPNS_TYPE_BITS 17:16 + #define EMMC_CMDTM_CMD_RSPNS_TYPE_SET 0x00030000 + #define EMMC_CMDTM_CMD_RSPNS_TYPE_CLR 0xfffcffff + #define EMMC_CMDTM_CMD_RSPNS_TYPE_MSB 17 + #define EMMC_CMDTM_CMD_RSPNS_TYPE_LSB 16 + #define EMMC_CMDTM_TM_MULTI_BLOCK_BITS 5:5 + #define EMMC_CMDTM_TM_MULTI_BLOCK_SET 0x00000020 + #define EMMC_CMDTM_TM_MULTI_BLOCK_CLR 0xffffffdf + #define EMMC_CMDTM_TM_MULTI_BLOCK_MSB 5 + #define EMMC_CMDTM_TM_MULTI_BLOCK_LSB 5 + #define EMMC_CMDTM_TM_DAT_DIR_BITS 4:4 + #define EMMC_CMDTM_TM_DAT_DIR_SET 0x00000010 + #define EMMC_CMDTM_TM_DAT_DIR_CLR 0xffffffef + #define EMMC_CMDTM_TM_DAT_DIR_MSB 4 + #define EMMC_CMDTM_TM_DAT_DIR_LSB 4 + #define EMMC_CMDTM_TM_AUTO_CMD_EN_BITS 3:2 + #define EMMC_CMDTM_TM_AUTO_CMD_EN_SET 0x0000000c + #define EMMC_CMDTM_TM_AUTO_CMD_EN_CLR 0xfffffff3 + #define EMMC_CMDTM_TM_AUTO_CMD_EN_MSB 3 + #define EMMC_CMDTM_TM_AUTO_CMD_EN_LSB 2 + #define EMMC_CMDTM_TM_BLKCNT_EN_BITS 1:1 + #define EMMC_CMDTM_TM_BLKCNT_EN_SET 0x00000002 + #define EMMC_CMDTM_TM_BLKCNT_EN_CLR 0xfffffffd + #define EMMC_CMDTM_TM_BLKCNT_EN_MSB 1 + #define EMMC_CMDTM_TM_BLKCNT_EN_LSB 1 + #define EMMC_CMDTM_TM_DMA_EN_BITS 0:0 + #define EMMC_CMDTM_TM_DMA_EN_SET 0x00000001 + #define EMMC_CMDTM_TM_DMA_EN_CLR 0xfffffffe + #define EMMC_CMDTM_TM_DMA_EN_MSB 0 + #define EMMC_CMDTM_TM_DMA_EN_LSB 0 +#define EMMC_RESP0 HW_REGISTER_RW( 0x7e300010 ) + #define EMMC_RESP0_MASK 0xffffffff + #define EMMC_RESP0_WIDTH 32 + #define EMMC_RESP0_RESET 0000000000 +#define EMMC_RESP1 HW_REGISTER_RW( 0x7e300014 ) + #define EMMC_RESP1_MASK 0xffffffff + #define EMMC_RESP1_WIDTH 32 + #define EMMC_RESP1_RESET 0000000000 +#define EMMC_RESP2 HW_REGISTER_RW( 0x7e300018 ) + #define EMMC_RESP2_MASK 0xffffffff + #define EMMC_RESP2_WIDTH 32 + #define EMMC_RESP2_RESET 0000000000 +#define EMMC_RESP3 HW_REGISTER_RW( 0x7e30001c ) + #define EMMC_RESP3_MASK 0xffffffff + #define EMMC_RESP3_WIDTH 32 + #define EMMC_RESP3_RESET 0000000000 +#define EMMC_DATA HW_REGISTER_RW( 0x7e300020 ) + #define EMMC_DATA_MASK 0xffffffff + #define EMMC_DATA_WIDTH 32 + #define EMMC_DATA_RESET 0000000000 +#define EMMC_STATUS HW_REGISTER_RW( 0x7e300024 ) + #define EMMC_STATUS_MASK 0x1fff0f0f + #define EMMC_STATUS_WIDTH 29 + #define EMMC_STATUS_RESET 0x1ff00000 + #define EMMC_STATUS_DAT_LEVEL1_BITS 28:25 + #define EMMC_STATUS_DAT_LEVEL1_SET 0x1e000000 + #define EMMC_STATUS_DAT_LEVEL1_CLR 0xe1ffffff + #define EMMC_STATUS_DAT_LEVEL1_MSB 28 + #define EMMC_STATUS_DAT_LEVEL1_LSB 25 + #define EMMC_STATUS_CMD_LEVEL_BITS 24:24 + #define EMMC_STATUS_CMD_LEVEL_SET 0x01000000 + #define EMMC_STATUS_CMD_LEVEL_CLR 0xfeffffff + #define EMMC_STATUS_CMD_LEVEL_MSB 24 + #define EMMC_STATUS_CMD_LEVEL_LSB 24 + #define EMMC_STATUS_DAT_LEVEL0_BITS 23:20 + #define EMMC_STATUS_DAT_LEVEL0_SET 0x00f00000 + #define EMMC_STATUS_DAT_LEVEL0_CLR 0xff0fffff + #define EMMC_STATUS_DAT_LEVEL0_MSB 23 + #define EMMC_STATUS_DAT_LEVEL0_LSB 20 + #define EMMC_STATUS_WRT_PROTECT_BITS 19:19 + #define EMMC_STATUS_WRT_PROTECT_SET 0x00080000 + #define EMMC_STATUS_WRT_PROTECT_CLR 0xfff7ffff + #define EMMC_STATUS_WRT_PROTECT_MSB 19 + #define EMMC_STATUS_WRT_PROTECT_LSB 19 + #define EMMC_STATUS_CARD_DETECT_BITS 18:18 + #define EMMC_STATUS_CARD_DETECT_SET 0x00040000 + #define EMMC_STATUS_CARD_DETECT_CLR 0xfffbffff + #define EMMC_STATUS_CARD_DETECT_MSB 18 + #define EMMC_STATUS_CARD_DETECT_LSB 18 + #define EMMC_STATUS_CARD_STABLE_BITS 17:17 + #define EMMC_STATUS_CARD_STABLE_SET 0x00020000 + #define EMMC_STATUS_CARD_STABLE_CLR 0xfffdffff + #define EMMC_STATUS_CARD_STABLE_MSB 17 + #define EMMC_STATUS_CARD_STABLE_LSB 17 + #define EMMC_STATUS_CARD_INSERT_BITS 16:16 + #define EMMC_STATUS_CARD_INSERT_SET 0x00010000 + #define EMMC_STATUS_CARD_INSERT_CLR 0xfffeffff + #define EMMC_STATUS_CARD_INSERT_MSB 16 + #define EMMC_STATUS_CARD_INSERT_LSB 16 + #define EMMC_STATUS_NEW_READ_DATA_BITS 11:11 + #define EMMC_STATUS_NEW_READ_DATA_SET 0x00000800 + #define EMMC_STATUS_NEW_READ_DATA_CLR 0xfffff7ff + #define EMMC_STATUS_NEW_READ_DATA_MSB 11 + #define EMMC_STATUS_NEW_READ_DATA_LSB 11 + #define EMMC_STATUS_NEW_WRITE_DATA_BITS 10:10 + #define EMMC_STATUS_NEW_WRITE_DATA_SET 0x00000400 + #define EMMC_STATUS_NEW_WRITE_DATA_CLR 0xfffffbff + #define EMMC_STATUS_NEW_WRITE_DATA_MSB 10 + #define EMMC_STATUS_NEW_WRITE_DATA_LSB 10 + #define EMMC_STATUS_READ_TRANSFER_BITS 9:9 + #define EMMC_STATUS_READ_TRANSFER_SET 0x00000200 + #define EMMC_STATUS_READ_TRANSFER_CLR 0xfffffdff + #define EMMC_STATUS_READ_TRANSFER_MSB 9 + #define EMMC_STATUS_READ_TRANSFER_LSB 9 + #define EMMC_STATUS_WRITE_TRANSFER_BITS 8:8 + #define EMMC_STATUS_WRITE_TRANSFER_SET 0x00000100 + #define EMMC_STATUS_WRITE_TRANSFER_CLR 0xfffffeff + #define EMMC_STATUS_WRITE_TRANSFER_MSB 8 + #define EMMC_STATUS_WRITE_TRANSFER_LSB 8 + #define EMMC_STATUS_RETUNING_REQ_BITS 3:3 + #define EMMC_STATUS_RETUNING_REQ_SET 0x00000008 + #define EMMC_STATUS_RETUNING_REQ_CLR 0xfffffff7 + #define EMMC_STATUS_RETUNING_REQ_MSB 3 + #define EMMC_STATUS_RETUNING_REQ_LSB 3 + #define EMMC_STATUS_DAT_ACTIVE_BITS 2:2 + #define EMMC_STATUS_DAT_ACTIVE_SET 0x00000004 + #define EMMC_STATUS_DAT_ACTIVE_CLR 0xfffffffb + #define EMMC_STATUS_DAT_ACTIVE_MSB 2 + #define EMMC_STATUS_DAT_ACTIVE_LSB 2 + #define EMMC_STATUS_DAT_INHIBIT_BITS 1:1 + #define EMMC_STATUS_DAT_INHIBIT_SET 0x00000002 + #define EMMC_STATUS_DAT_INHIBIT_CLR 0xfffffffd + #define EMMC_STATUS_DAT_INHIBIT_MSB 1 + #define EMMC_STATUS_DAT_INHIBIT_LSB 1 + #define EMMC_STATUS_CMD_INHIBIT_BITS 0:0 + #define EMMC_STATUS_CMD_INHIBIT_SET 0x00000001 + #define EMMC_STATUS_CMD_INHIBIT_CLR 0xfffffffe + #define EMMC_STATUS_CMD_INHIBIT_MSB 0 + #define EMMC_STATUS_CMD_INHIBIT_LSB 0 +#define EMMC_CONTROL0 HW_REGISTER_RW( 0x7e300028 ) + #define EMMC_CONTROL0_MASK 0x07ff1fff + #define EMMC_CONTROL0_WIDTH 27 + #define EMMC_CONTROL0_RESET 0000000000 + #define EMMC_CONTROL0_WAKE_ONREM_EN_BITS 26:26 + #define EMMC_CONTROL0_WAKE_ONREM_EN_SET 0x04000000 + #define EMMC_CONTROL0_WAKE_ONREM_EN_CLR 0xfbffffff + #define EMMC_CONTROL0_WAKE_ONREM_EN_MSB 26 + #define EMMC_CONTROL0_WAKE_ONREM_EN_LSB 26 + #define EMMC_CONTROL0_WAKE_ONINS_EN_BITS 25:25 + #define EMMC_CONTROL0_WAKE_ONINS_EN_SET 0x02000000 + #define EMMC_CONTROL0_WAKE_ONINS_EN_CLR 0xfdffffff + #define EMMC_CONTROL0_WAKE_ONINS_EN_MSB 25 + #define EMMC_CONTROL0_WAKE_ONINS_EN_LSB 25 + #define EMMC_CONTROL0_WAKE_ONINT_EN_BITS 24:24 + #define EMMC_CONTROL0_WAKE_ONINT_EN_SET 0x01000000 + #define EMMC_CONTROL0_WAKE_ONINT_EN_CLR 0xfeffffff + #define EMMC_CONTROL0_WAKE_ONINT_EN_MSB 24 + #define EMMC_CONTROL0_WAKE_ONINT_EN_LSB 24 + #define EMMC_CONTROL0_ALT_BOOT_EN_BITS 22:22 + #define EMMC_CONTROL0_ALT_BOOT_EN_SET 0x00400000 + #define EMMC_CONTROL0_ALT_BOOT_EN_CLR 0xffbfffff + #define EMMC_CONTROL0_ALT_BOOT_EN_MSB 22 + #define EMMC_CONTROL0_ALT_BOOT_EN_LSB 22 + #define EMMC_CONTROL0_BOOT_EN_BITS 21:21 + #define EMMC_CONTROL0_BOOT_EN_SET 0x00200000 + #define EMMC_CONTROL0_BOOT_EN_CLR 0xffdfffff + #define EMMC_CONTROL0_BOOT_EN_MSB 21 + #define EMMC_CONTROL0_BOOT_EN_LSB 21 + #define EMMC_CONTROL0_SPI_MODE_BITS 20:20 + #define EMMC_CONTROL0_SPI_MODE_SET 0x00100000 + #define EMMC_CONTROL0_SPI_MODE_CLR 0xffefffff + #define EMMC_CONTROL0_SPI_MODE_MSB 20 + #define EMMC_CONTROL0_SPI_MODE_LSB 20 + #define EMMC_CONTROL0_GAP_IEN_BITS 19:19 + #define EMMC_CONTROL0_GAP_IEN_SET 0x00080000 + #define EMMC_CONTROL0_GAP_IEN_CLR 0xfff7ffff + #define EMMC_CONTROL0_GAP_IEN_MSB 19 + #define EMMC_CONTROL0_GAP_IEN_LSB 19 + #define EMMC_CONTROL0_READWAIT_EN_BITS 18:18 + #define EMMC_CONTROL0_READWAIT_EN_SET 0x00040000 + #define EMMC_CONTROL0_READWAIT_EN_CLR 0xfffbffff + #define EMMC_CONTROL0_READWAIT_EN_MSB 18 + #define EMMC_CONTROL0_READWAIT_EN_LSB 18 + #define EMMC_CONTROL0_GAP_RESTART_BITS 17:17 + #define EMMC_CONTROL0_GAP_RESTART_SET 0x00020000 + #define EMMC_CONTROL0_GAP_RESTART_CLR 0xfffdffff + #define EMMC_CONTROL0_GAP_RESTART_MSB 17 + #define EMMC_CONTROL0_GAP_RESTART_LSB 17 + #define EMMC_CONTROL0_GAP_STOP_BITS 16:16 + #define EMMC_CONTROL0_GAP_STOP_SET 0x00010000 + #define EMMC_CONTROL0_GAP_STOP_CLR 0xfffeffff + #define EMMC_CONTROL0_GAP_STOP_MSB 16 + #define EMMC_CONTROL0_GAP_STOP_LSB 16 + #define EMMC_CONTROL0_PWCTL_HWRST_BITS 12:12 + #define EMMC_CONTROL0_PWCTL_HWRST_SET 0x00001000 + #define EMMC_CONTROL0_PWCTL_HWRST_CLR 0xffffefff + #define EMMC_CONTROL0_PWCTL_HWRST_MSB 12 + #define EMMC_CONTROL0_PWCTL_HWRST_LSB 12 + #define EMMC_CONTROL0_PWCTL_SDVOLTS_BITS 11:9 + #define EMMC_CONTROL0_PWCTL_SDVOLTS_SET 0x00000e00 + #define EMMC_CONTROL0_PWCTL_SDVOLTS_CLR 0xfffff1ff + #define EMMC_CONTROL0_PWCTL_SDVOLTS_MSB 11 + #define EMMC_CONTROL0_PWCTL_SDVOLTS_LSB 9 + #define EMMC_CONTROL0_PWCTL_ON_BITS 8:8 + #define EMMC_CONTROL0_PWCTL_ON_SET 0x00000100 + #define EMMC_CONTROL0_PWCTL_ON_CLR 0xfffffeff + #define EMMC_CONTROL0_PWCTL_ON_MSB 8 + #define EMMC_CONTROL0_PWCTL_ON_LSB 8 + #define EMMC_CONTROL0_HCTL_CRDDET_S_BITS 7:7 + #define EMMC_CONTROL0_HCTL_CRDDET_S_SET 0x00000080 + #define EMMC_CONTROL0_HCTL_CRDDET_S_CLR 0xffffff7f + #define EMMC_CONTROL0_HCTL_CRDDET_S_MSB 7 + #define EMMC_CONTROL0_HCTL_CRDDET_S_LSB 7 + #define EMMC_CONTROL0_HCTL_CRDDET_BITS 6:6 + #define EMMC_CONTROL0_HCTL_CRDDET_SET 0x00000040 + #define EMMC_CONTROL0_HCTL_CRDDET_CLR 0xffffffbf + #define EMMC_CONTROL0_HCTL_CRDDET_MSB 6 + #define EMMC_CONTROL0_HCTL_CRDDET_LSB 6 + #define EMMC_CONTROL0_HCTL_8BIT_BITS 5:5 + #define EMMC_CONTROL0_HCTL_8BIT_SET 0x00000020 + #define EMMC_CONTROL0_HCTL_8BIT_CLR 0xffffffdf + #define EMMC_CONTROL0_HCTL_8BIT_MSB 5 + #define EMMC_CONTROL0_HCTL_8BIT_LSB 5 + #define EMMC_CONTROL0_HCTL_DMA_BITS 4:3 + #define EMMC_CONTROL0_HCTL_DMA_SET 0x00000018 + #define EMMC_CONTROL0_HCTL_DMA_CLR 0xffffffe7 + #define EMMC_CONTROL0_HCTL_DMA_MSB 4 + #define EMMC_CONTROL0_HCTL_DMA_LSB 3 + #define EMMC_CONTROL0_HCTL_HS_EN_BITS 2:2 + #define EMMC_CONTROL0_HCTL_HS_EN_SET 0x00000004 + #define EMMC_CONTROL0_HCTL_HS_EN_CLR 0xfffffffb + #define EMMC_CONTROL0_HCTL_HS_EN_MSB 2 + #define EMMC_CONTROL0_HCTL_HS_EN_LSB 2 + #define EMMC_CONTROL0_HCTL_DWIDTH_BITS 1:1 + #define EMMC_CONTROL0_HCTL_DWIDTH_SET 0x00000002 + #define EMMC_CONTROL0_HCTL_DWIDTH_CLR 0xfffffffd + #define EMMC_CONTROL0_HCTL_DWIDTH_MSB 1 + #define EMMC_CONTROL0_HCTL_DWIDTH_LSB 1 + #define EMMC_CONTROL0_HCTL_LED_BITS 0:0 + #define EMMC_CONTROL0_HCTL_LED_SET 0x00000001 + #define EMMC_CONTROL0_HCTL_LED_CLR 0xfffffffe + #define EMMC_CONTROL0_HCTL_LED_MSB 0 + #define EMMC_CONTROL0_HCTL_LED_LSB 0 +#define EMMC_CONTROL1 HW_REGISTER_RW( 0x7e30002c ) + #define EMMC_CONTROL1_MASK 0x070fffe7 + #define EMMC_CONTROL1_WIDTH 27 + #define EMMC_CONTROL1_RESET 0000000000 + #define EMMC_CONTROL1_SRST_DATA_BITS 26:26 + #define EMMC_CONTROL1_SRST_DATA_SET 0x04000000 + #define EMMC_CONTROL1_SRST_DATA_CLR 0xfbffffff + #define EMMC_CONTROL1_SRST_DATA_MSB 26 + #define EMMC_CONTROL1_SRST_DATA_LSB 26 + #define EMMC_CONTROL1_SRST_CMD_BITS 25:25 + #define EMMC_CONTROL1_SRST_CMD_SET 0x02000000 + #define EMMC_CONTROL1_SRST_CMD_CLR 0xfdffffff + #define EMMC_CONTROL1_SRST_CMD_MSB 25 + #define EMMC_CONTROL1_SRST_CMD_LSB 25 + #define EMMC_CONTROL1_SRST_HC_BITS 24:24 + #define EMMC_CONTROL1_SRST_HC_SET 0x01000000 + #define EMMC_CONTROL1_SRST_HC_CLR 0xfeffffff + #define EMMC_CONTROL1_SRST_HC_MSB 24 + #define EMMC_CONTROL1_SRST_HC_LSB 24 + #define EMMC_CONTROL1_DATA_TOUNIT_BITS 19:16 + #define EMMC_CONTROL1_DATA_TOUNIT_SET 0x000f0000 + #define EMMC_CONTROL1_DATA_TOUNIT_CLR 0xfff0ffff + #define EMMC_CONTROL1_DATA_TOUNIT_MSB 19 + #define EMMC_CONTROL1_DATA_TOUNIT_LSB 16 + #define EMMC_CONTROL1_CLK_FREQ8_BITS 15:8 + #define EMMC_CONTROL1_CLK_FREQ8_SET 0x0000ff00 + #define EMMC_CONTROL1_CLK_FREQ8_CLR 0xffff00ff + #define EMMC_CONTROL1_CLK_FREQ8_MSB 15 + #define EMMC_CONTROL1_CLK_FREQ8_LSB 8 + #define EMMC_CONTROL1_CLK_FREQ_MS2_BITS 7:6 + #define EMMC_CONTROL1_CLK_FREQ_MS2_SET 0x000000c0 + #define EMMC_CONTROL1_CLK_FREQ_MS2_CLR 0xffffff3f + #define EMMC_CONTROL1_CLK_FREQ_MS2_MSB 7 + #define EMMC_CONTROL1_CLK_FREQ_MS2_LSB 6 + #define EMMC_CONTROL1_CLK_GENSEL_BITS 5:5 + #define EMMC_CONTROL1_CLK_GENSEL_SET 0x00000020 + #define EMMC_CONTROL1_CLK_GENSEL_CLR 0xffffffdf + #define EMMC_CONTROL1_CLK_GENSEL_MSB 5 + #define EMMC_CONTROL1_CLK_GENSEL_LSB 5 + #define EMMC_CONTROL1_CLK_EN_BITS 2:2 + #define EMMC_CONTROL1_CLK_EN_SET 0x00000004 + #define EMMC_CONTROL1_CLK_EN_CLR 0xfffffffb + #define EMMC_CONTROL1_CLK_EN_MSB 2 + #define EMMC_CONTROL1_CLK_EN_LSB 2 + #define EMMC_CONTROL1_CLK_STABLE_BITS 1:1 + #define EMMC_CONTROL1_CLK_STABLE_SET 0x00000002 + #define EMMC_CONTROL1_CLK_STABLE_CLR 0xfffffffd + #define EMMC_CONTROL1_CLK_STABLE_MSB 1 + #define EMMC_CONTROL1_CLK_STABLE_LSB 1 + #define EMMC_CONTROL1_CLK_INTLEN_BITS 0:0 + #define EMMC_CONTROL1_CLK_INTLEN_SET 0x00000001 + #define EMMC_CONTROL1_CLK_INTLEN_CLR 0xfffffffe + #define EMMC_CONTROL1_CLK_INTLEN_MSB 0 + #define EMMC_CONTROL1_CLK_INTLEN_LSB 0 +#define EMMC_INTERRUPT HW_REGISTER_RW( 0x7e300030 ) + #define EMMC_INTERRUPT_MASK 0xffffffff + #define EMMC_INTERRUPT_WIDTH 32 + #define EMMC_INTERRUPT_RESET 0000000000 + #define EMMC_INTERRUPT_OEM_ERR_BITS 31:30 + #define EMMC_INTERRUPT_OEM_ERR_SET 0xc0000000 + #define EMMC_INTERRUPT_OEM_ERR_CLR 0x3fffffff + #define EMMC_INTERRUPT_OEM_ERR_MSB 31 + #define EMMC_INTERRUPT_OEM_ERR_LSB 30 + #define EMMC_INTERRUPT_ATA_ERR_BITS 29:29 + #define EMMC_INTERRUPT_ATA_ERR_SET 0x20000000 + #define EMMC_INTERRUPT_ATA_ERR_CLR 0xdfffffff + #define EMMC_INTERRUPT_ATA_ERR_MSB 29 + #define EMMC_INTERRUPT_ATA_ERR_LSB 29 + #define EMMC_INTERRUPT_DMA_ERR_BITS 28:28 + #define EMMC_INTERRUPT_DMA_ERR_SET 0x10000000 + #define EMMC_INTERRUPT_DMA_ERR_CLR 0xefffffff + #define EMMC_INTERRUPT_DMA_ERR_MSB 28 + #define EMMC_INTERRUPT_DMA_ERR_LSB 28 + #define EMMC_INTERRUPT_TUNE_ERR_BITS 26:26 + #define EMMC_INTERRUPT_TUNE_ERR_SET 0x04000000 + #define EMMC_INTERRUPT_TUNE_ERR_CLR 0xfbffffff + #define EMMC_INTERRUPT_TUNE_ERR_MSB 26 + #define EMMC_INTERRUPT_TUNE_ERR_LSB 26 + #define EMMC_INTERRUPT_ADMA_ERR_BITS 25:25 + #define EMMC_INTERRUPT_ADMA_ERR_SET 0x02000000 + #define EMMC_INTERRUPT_ADMA_ERR_CLR 0xfdffffff + #define EMMC_INTERRUPT_ADMA_ERR_MSB 25 + #define EMMC_INTERRUPT_ADMA_ERR_LSB 25 + #define EMMC_INTERRUPT_ACMD_ERR_BITS 24:24 + #define EMMC_INTERRUPT_ACMD_ERR_SET 0x01000000 + #define EMMC_INTERRUPT_ACMD_ERR_CLR 0xfeffffff + #define EMMC_INTERRUPT_ACMD_ERR_MSB 24 + #define EMMC_INTERRUPT_ACMD_ERR_LSB 24 + #define EMMC_INTERRUPT_SDOFF_ERR_BITS 23:23 + #define EMMC_INTERRUPT_SDOFF_ERR_SET 0x00800000 + #define EMMC_INTERRUPT_SDOFF_ERR_CLR 0xff7fffff + #define EMMC_INTERRUPT_SDOFF_ERR_MSB 23 + #define EMMC_INTERRUPT_SDOFF_ERR_LSB 23 + #define EMMC_INTERRUPT_DEND_ERR_BITS 22:22 + #define EMMC_INTERRUPT_DEND_ERR_SET 0x00400000 + #define EMMC_INTERRUPT_DEND_ERR_CLR 0xffbfffff + #define EMMC_INTERRUPT_DEND_ERR_MSB 22 + #define EMMC_INTERRUPT_DEND_ERR_LSB 22 + #define EMMC_INTERRUPT_DCRC_ERR_BITS 21:21 + #define EMMC_INTERRUPT_DCRC_ERR_SET 0x00200000 + #define EMMC_INTERRUPT_DCRC_ERR_CLR 0xffdfffff + #define EMMC_INTERRUPT_DCRC_ERR_MSB 21 + #define EMMC_INTERRUPT_DCRC_ERR_LSB 21 + #define EMMC_INTERRUPT_DTO_ERR_BITS 20:20 + #define EMMC_INTERRUPT_DTO_ERR_SET 0x00100000 + #define EMMC_INTERRUPT_DTO_ERR_CLR 0xffefffff + #define EMMC_INTERRUPT_DTO_ERR_MSB 20 + #define EMMC_INTERRUPT_DTO_ERR_LSB 20 + #define EMMC_INTERRUPT_CBAD_ERR_BITS 19:19 + #define EMMC_INTERRUPT_CBAD_ERR_SET 0x00080000 + #define EMMC_INTERRUPT_CBAD_ERR_CLR 0xfff7ffff + #define EMMC_INTERRUPT_CBAD_ERR_MSB 19 + #define EMMC_INTERRUPT_CBAD_ERR_LSB 19 + #define EMMC_INTERRUPT_CEND_ERR_BITS 18:18 + #define EMMC_INTERRUPT_CEND_ERR_SET 0x00040000 + #define EMMC_INTERRUPT_CEND_ERR_CLR 0xfffbffff + #define EMMC_INTERRUPT_CEND_ERR_MSB 18 + #define EMMC_INTERRUPT_CEND_ERR_LSB 18 + #define EMMC_INTERRUPT_CCRC_ERR_BITS 17:17 + #define EMMC_INTERRUPT_CCRC_ERR_SET 0x00020000 + #define EMMC_INTERRUPT_CCRC_ERR_CLR 0xfffdffff + #define EMMC_INTERRUPT_CCRC_ERR_MSB 17 + #define EMMC_INTERRUPT_CCRC_ERR_LSB 17 + #define EMMC_INTERRUPT_CTO_ERR_BITS 16:16 + #define EMMC_INTERRUPT_CTO_ERR_SET 0x00010000 + #define EMMC_INTERRUPT_CTO_ERR_CLR 0xfffeffff + #define EMMC_INTERRUPT_CTO_ERR_MSB 16 + #define EMMC_INTERRUPT_CTO_ERR_LSB 16 + #define EMMC_INTERRUPT_ERR_BITS 15:15 + #define EMMC_INTERRUPT_ERR_SET 0x00008000 + #define EMMC_INTERRUPT_ERR_CLR 0xffff7fff + #define EMMC_INTERRUPT_ERR_MSB 15 + #define EMMC_INTERRUPT_ERR_LSB 15 + #define EMMC_INTERRUPT_ENDBOOT_BITS 14:14 + #define EMMC_INTERRUPT_ENDBOOT_SET 0x00004000 + #define EMMC_INTERRUPT_ENDBOOT_CLR 0xffffbfff + #define EMMC_INTERRUPT_ENDBOOT_MSB 14 + #define EMMC_INTERRUPT_ENDBOOT_LSB 14 + #define EMMC_INTERRUPT_BOOTACK_BITS 13:13 + #define EMMC_INTERRUPT_BOOTACK_SET 0x00002000 + #define EMMC_INTERRUPT_BOOTACK_CLR 0xffffdfff + #define EMMC_INTERRUPT_BOOTACK_MSB 13 + #define EMMC_INTERRUPT_BOOTACK_LSB 13 + #define EMMC_INTERRUPT_RETUNE_BITS 12:12 + #define EMMC_INTERRUPT_RETUNE_SET 0x00001000 + #define EMMC_INTERRUPT_RETUNE_CLR 0xffffefff + #define EMMC_INTERRUPT_RETUNE_MSB 12 + #define EMMC_INTERRUPT_RETUNE_LSB 12 + #define EMMC_INTERRUPT_INT_C_BITS 11:11 + #define EMMC_INTERRUPT_INT_C_SET 0x00000800 + #define EMMC_INTERRUPT_INT_C_CLR 0xfffff7ff + #define EMMC_INTERRUPT_INT_C_MSB 11 + #define EMMC_INTERRUPT_INT_C_LSB 11 + #define EMMC_INTERRUPT_INT_B_BITS 10:10 + #define EMMC_INTERRUPT_INT_B_SET 0x00000400 + #define EMMC_INTERRUPT_INT_B_CLR 0xfffffbff + #define EMMC_INTERRUPT_INT_B_MSB 10 + #define EMMC_INTERRUPT_INT_B_LSB 10 + #define EMMC_INTERRUPT_INT_A_BITS 9:9 + #define EMMC_INTERRUPT_INT_A_SET 0x00000200 + #define EMMC_INTERRUPT_INT_A_CLR 0xfffffdff + #define EMMC_INTERRUPT_INT_A_MSB 9 + #define EMMC_INTERRUPT_INT_A_LSB 9 + #define EMMC_INTERRUPT_CARD_BITS 8:8 + #define EMMC_INTERRUPT_CARD_SET 0x00000100 + #define EMMC_INTERRUPT_CARD_CLR 0xfffffeff + #define EMMC_INTERRUPT_CARD_MSB 8 + #define EMMC_INTERRUPT_CARD_LSB 8 + #define EMMC_INTERRUPT_CARD_OUT_BITS 7:7 + #define EMMC_INTERRUPT_CARD_OUT_SET 0x00000080 + #define EMMC_INTERRUPT_CARD_OUT_CLR 0xffffff7f + #define EMMC_INTERRUPT_CARD_OUT_MSB 7 + #define EMMC_INTERRUPT_CARD_OUT_LSB 7 + #define EMMC_INTERRUPT_CARD_IN_BITS 6:6 + #define EMMC_INTERRUPT_CARD_IN_SET 0x00000040 + #define EMMC_INTERRUPT_CARD_IN_CLR 0xffffffbf + #define EMMC_INTERRUPT_CARD_IN_MSB 6 + #define EMMC_INTERRUPT_CARD_IN_LSB 6 + #define EMMC_INTERRUPT_READ_RDY_BITS 5:5 + #define EMMC_INTERRUPT_READ_RDY_SET 0x00000020 + #define EMMC_INTERRUPT_READ_RDY_CLR 0xffffffdf + #define EMMC_INTERRUPT_READ_RDY_MSB 5 + #define EMMC_INTERRUPT_READ_RDY_LSB 5 + #define EMMC_INTERRUPT_WRITE_RDY_BITS 4:4 + #define EMMC_INTERRUPT_WRITE_RDY_SET 0x00000010 + #define EMMC_INTERRUPT_WRITE_RDY_CLR 0xffffffef + #define EMMC_INTERRUPT_WRITE_RDY_MSB 4 + #define EMMC_INTERRUPT_WRITE_RDY_LSB 4 + #define EMMC_INTERRUPT_DMA_BITS 3:3 + #define EMMC_INTERRUPT_DMA_SET 0x00000008 + #define EMMC_INTERRUPT_DMA_CLR 0xfffffff7 + #define EMMC_INTERRUPT_DMA_MSB 3 + #define EMMC_INTERRUPT_DMA_LSB 3 + #define EMMC_INTERRUPT_BLOCK_GAP_BITS 2:2 + #define EMMC_INTERRUPT_BLOCK_GAP_SET 0x00000004 + #define EMMC_INTERRUPT_BLOCK_GAP_CLR 0xfffffffb + #define EMMC_INTERRUPT_BLOCK_GAP_MSB 2 + #define EMMC_INTERRUPT_BLOCK_GAP_LSB 2 + #define EMMC_INTERRUPT_DATA_DONE_BITS 1:1 + #define EMMC_INTERRUPT_DATA_DONE_SET 0x00000002 + #define EMMC_INTERRUPT_DATA_DONE_CLR 0xfffffffd + #define EMMC_INTERRUPT_DATA_DONE_MSB 1 + #define EMMC_INTERRUPT_DATA_DONE_LSB 1 + #define EMMC_INTERRUPT_CMD_DONE_BITS 0:0 + #define EMMC_INTERRUPT_CMD_DONE_SET 0x00000001 + #define EMMC_INTERRUPT_CMD_DONE_CLR 0xfffffffe + #define EMMC_INTERRUPT_CMD_DONE_MSB 0 + #define EMMC_INTERRUPT_CMD_DONE_LSB 0 +#define EMMC_IRPT_MASK HW_REGISTER_RW( 0x7e300034 ) + #define EMMC_IRPT_MASK_MASK 0xffffffff + #define EMMC_IRPT_MASK_WIDTH 32 + #define EMMC_IRPT_MASK_RESET 0000000000 + #define EMMC_IRPT_MASK_OEM_ERR_BITS 31:30 + #define EMMC_IRPT_MASK_OEM_ERR_SET 0xc0000000 + #define EMMC_IRPT_MASK_OEM_ERR_CLR 0x3fffffff + #define EMMC_IRPT_MASK_OEM_ERR_MSB 31 + #define EMMC_IRPT_MASK_OEM_ERR_LSB 30 + #define EMMC_IRPT_MASK_ATA_ERR_BITS 29:29 + #define EMMC_IRPT_MASK_ATA_ERR_SET 0x20000000 + #define EMMC_IRPT_MASK_ATA_ERR_CLR 0xdfffffff + #define EMMC_IRPT_MASK_ATA_ERR_MSB 29 + #define EMMC_IRPT_MASK_ATA_ERR_LSB 29 + #define EMMC_IRPT_MASK_DMA_ERR_BITS 28:28 + #define EMMC_IRPT_MASK_DMA_ERR_SET 0x10000000 + #define EMMC_IRPT_MASK_DMA_ERR_CLR 0xefffffff + #define EMMC_IRPT_MASK_DMA_ERR_MSB 28 + #define EMMC_IRPT_MASK_DMA_ERR_LSB 28 + #define EMMC_IRPT_MASK_ADMA_ERR_BITS 25:25 + #define EMMC_IRPT_MASK_ADMA_ERR_SET 0x02000000 + #define EMMC_IRPT_MASK_ADMA_ERR_CLR 0xfdffffff + #define EMMC_IRPT_MASK_ADMA_ERR_MSB 25 + #define EMMC_IRPT_MASK_ADMA_ERR_LSB 25 + #define EMMC_IRPT_MASK_ACMD_ERR_BITS 24:24 + #define EMMC_IRPT_MASK_ACMD_ERR_SET 0x01000000 + #define EMMC_IRPT_MASK_ACMD_ERR_CLR 0xfeffffff + #define EMMC_IRPT_MASK_ACMD_ERR_MSB 24 + #define EMMC_IRPT_MASK_ACMD_ERR_LSB 24 + #define EMMC_IRPT_MASK_SDOFF_ERR_BITS 23:23 + #define EMMC_IRPT_MASK_SDOFF_ERR_SET 0x00800000 + #define EMMC_IRPT_MASK_SDOFF_ERR_CLR 0xff7fffff + #define EMMC_IRPT_MASK_SDOFF_ERR_MSB 23 + #define EMMC_IRPT_MASK_SDOFF_ERR_LSB 23 + #define EMMC_IRPT_MASK_DEND_ERR_BITS 22:22 + #define EMMC_IRPT_MASK_DEND_ERR_SET 0x00400000 + #define EMMC_IRPT_MASK_DEND_ERR_CLR 0xffbfffff + #define EMMC_IRPT_MASK_DEND_ERR_MSB 22 + #define EMMC_IRPT_MASK_DEND_ERR_LSB 22 + #define EMMC_IRPT_MASK_DCRC_ERR_BITS 21:21 + #define EMMC_IRPT_MASK_DCRC_ERR_SET 0x00200000 + #define EMMC_IRPT_MASK_DCRC_ERR_CLR 0xffdfffff + #define EMMC_IRPT_MASK_DCRC_ERR_MSB 21 + #define EMMC_IRPT_MASK_DCRC_ERR_LSB 21 + #define EMMC_IRPT_MASK_DTO_ERR_BITS 20:20 + #define EMMC_IRPT_MASK_DTO_ERR_SET 0x00100000 + #define EMMC_IRPT_MASK_DTO_ERR_CLR 0xffefffff + #define EMMC_IRPT_MASK_DTO_ERR_MSB 20 + #define EMMC_IRPT_MASK_DTO_ERR_LSB 20 + #define EMMC_IRPT_MASK_CBAD_ERR_BITS 19:19 + #define EMMC_IRPT_MASK_CBAD_ERR_SET 0x00080000 + #define EMMC_IRPT_MASK_CBAD_ERR_CLR 0xfff7ffff + #define EMMC_IRPT_MASK_CBAD_ERR_MSB 19 + #define EMMC_IRPT_MASK_CBAD_ERR_LSB 19 + #define EMMC_IRPT_MASK_CEND_ERR_BITS 18:18 + #define EMMC_IRPT_MASK_CEND_ERR_SET 0x00040000 + #define EMMC_IRPT_MASK_CEND_ERR_CLR 0xfffbffff + #define EMMC_IRPT_MASK_CEND_ERR_MSB 18 + #define EMMC_IRPT_MASK_CEND_ERR_LSB 18 + #define EMMC_IRPT_MASK_CCRC_ERR_BITS 17:17 + #define EMMC_IRPT_MASK_CCRC_ERR_SET 0x00020000 + #define EMMC_IRPT_MASK_CCRC_ERR_CLR 0xfffdffff + #define EMMC_IRPT_MASK_CCRC_ERR_MSB 17 + #define EMMC_IRPT_MASK_CCRC_ERR_LSB 17 + #define EMMC_IRPT_MASK_CTO_ERR_BITS 16:16 + #define EMMC_IRPT_MASK_CTO_ERR_SET 0x00010000 + #define EMMC_IRPT_MASK_CTO_ERR_CLR 0xfffeffff + #define EMMC_IRPT_MASK_CTO_ERR_MSB 16 + #define EMMC_IRPT_MASK_CTO_ERR_LSB 16 + #define EMMC_IRPT_MASK_ENDBOOT_BITS 14:14 + #define EMMC_IRPT_MASK_ENDBOOT_SET 0x00004000 + #define EMMC_IRPT_MASK_ENDBOOT_CLR 0xffffbfff + #define EMMC_IRPT_MASK_ENDBOOT_MSB 14 + #define EMMC_IRPT_MASK_ENDBOOT_LSB 14 + #define EMMC_IRPT_MASK_BOOTACK_BITS 13:13 + #define EMMC_IRPT_MASK_BOOTACK_SET 0x00002000 + #define EMMC_IRPT_MASK_BOOTACK_CLR 0xffffdfff + #define EMMC_IRPT_MASK_BOOTACK_MSB 13 + #define EMMC_IRPT_MASK_BOOTACK_LSB 13 + #define EMMC_IRPT_MASK_RETUNE_BITS 12:12 + #define EMMC_IRPT_MASK_RETUNE_SET 0x00001000 + #define EMMC_IRPT_MASK_RETUNE_CLR 0xffffefff + #define EMMC_IRPT_MASK_RETUNE_MSB 12 + #define EMMC_IRPT_MASK_RETUNE_LSB 12 + #define EMMC_IRPT_MASK_INT_C_BITS 11:11 + #define EMMC_IRPT_MASK_INT_C_SET 0x00000800 + #define EMMC_IRPT_MASK_INT_C_CLR 0xfffff7ff + #define EMMC_IRPT_MASK_INT_C_MSB 11 + #define EMMC_IRPT_MASK_INT_C_LSB 11 + #define EMMC_IRPT_MASK_INT_B_BITS 10:10 + #define EMMC_IRPT_MASK_INT_B_SET 0x00000400 + #define EMMC_IRPT_MASK_INT_B_CLR 0xfffffbff + #define EMMC_IRPT_MASK_INT_B_MSB 10 + #define EMMC_IRPT_MASK_INT_B_LSB 10 + #define EMMC_IRPT_MASK_INT_A_BITS 9:9 + #define EMMC_IRPT_MASK_INT_A_SET 0x00000200 + #define EMMC_IRPT_MASK_INT_A_CLR 0xfffffdff + #define EMMC_IRPT_MASK_INT_A_MSB 9 + #define EMMC_IRPT_MASK_INT_A_LSB 9 + #define EMMC_IRPT_MASK_CARD_BITS 8:8 + #define EMMC_IRPT_MASK_CARD_SET 0x00000100 + #define EMMC_IRPT_MASK_CARD_CLR 0xfffffeff + #define EMMC_IRPT_MASK_CARD_MSB 8 + #define EMMC_IRPT_MASK_CARD_LSB 8 + #define EMMC_IRPT_MASK_CARD_OUT_BITS 7:7 + #define EMMC_IRPT_MASK_CARD_OUT_SET 0x00000080 + #define EMMC_IRPT_MASK_CARD_OUT_CLR 0xffffff7f + #define EMMC_IRPT_MASK_CARD_OUT_MSB 7 + #define EMMC_IRPT_MASK_CARD_OUT_LSB 7 + #define EMMC_IRPT_MASK_CARD_IN_BITS 6:6 + #define EMMC_IRPT_MASK_CARD_IN_SET 0x00000040 + #define EMMC_IRPT_MASK_CARD_IN_CLR 0xffffffbf + #define EMMC_IRPT_MASK_CARD_IN_MSB 6 + #define EMMC_IRPT_MASK_CARD_IN_LSB 6 + #define EMMC_IRPT_MASK_READ_RDY_BITS 5:5 + #define EMMC_IRPT_MASK_READ_RDY_SET 0x00000020 + #define EMMC_IRPT_MASK_READ_RDY_CLR 0xffffffdf + #define EMMC_IRPT_MASK_READ_RDY_MSB 5 + #define EMMC_IRPT_MASK_READ_RDY_LSB 5 + #define EMMC_IRPT_MASK_WRITE_RDY_BITS 4:4 + #define EMMC_IRPT_MASK_WRITE_RDY_SET 0x00000010 + #define EMMC_IRPT_MASK_WRITE_RDY_CLR 0xffffffef + #define EMMC_IRPT_MASK_WRITE_RDY_MSB 4 + #define EMMC_IRPT_MASK_WRITE_RDY_LSB 4 + #define EMMC_IRPT_MASK_DMA_BITS 3:3 + #define EMMC_IRPT_MASK_DMA_SET 0x00000008 + #define EMMC_IRPT_MASK_DMA_CLR 0xfffffff7 + #define EMMC_IRPT_MASK_DMA_MSB 3 + #define EMMC_IRPT_MASK_DMA_LSB 3 + #define EMMC_IRPT_MASK_BLOCK_GAP_BITS 2:2 + #define EMMC_IRPT_MASK_BLOCK_GAP_SET 0x00000004 + #define EMMC_IRPT_MASK_BLOCK_GAP_CLR 0xfffffffb + #define EMMC_IRPT_MASK_BLOCK_GAP_MSB 2 + #define EMMC_IRPT_MASK_BLOCK_GAP_LSB 2 + #define EMMC_IRPT_MASK_DATA_DONE_BITS 1:1 + #define EMMC_IRPT_MASK_DATA_DONE_SET 0x00000002 + #define EMMC_IRPT_MASK_DATA_DONE_CLR 0xfffffffd + #define EMMC_IRPT_MASK_DATA_DONE_MSB 1 + #define EMMC_IRPT_MASK_DATA_DONE_LSB 1 + #define EMMC_IRPT_MASK_CMD_DONE_BITS 0:0 + #define EMMC_IRPT_MASK_CMD_DONE_SET 0x00000001 + #define EMMC_IRPT_MASK_CMD_DONE_CLR 0xfffffffe + #define EMMC_IRPT_MASK_CMD_DONE_MSB 0 + #define EMMC_IRPT_MASK_CMD_DONE_LSB 0 +#define EMMC_IRPT_EN HW_REGISTER_RW( 0x7e300038 ) + #define EMMC_IRPT_EN_MASK 0xffffffff + #define EMMC_IRPT_EN_WIDTH 32 + #define EMMC_IRPT_EN_RESET 0000000000 + #define EMMC_IRPT_EN_OEM_ERR_BITS 31:30 + #define EMMC_IRPT_EN_OEM_ERR_SET 0xc0000000 + #define EMMC_IRPT_EN_OEM_ERR_CLR 0x3fffffff + #define EMMC_IRPT_EN_OEM_ERR_MSB 31 + #define EMMC_IRPT_EN_OEM_ERR_LSB 30 + #define EMMC_IRPT_EN_ATA_ERR_BITS 29:29 + #define EMMC_IRPT_EN_ATA_ERR_SET 0x20000000 + #define EMMC_IRPT_EN_ATA_ERR_CLR 0xdfffffff + #define EMMC_IRPT_EN_ATA_ERR_MSB 29 + #define EMMC_IRPT_EN_ATA_ERR_LSB 29 + #define EMMC_IRPT_EN_DMA_ERR_BITS 28:28 + #define EMMC_IRPT_EN_DMA_ERR_SET 0x10000000 + #define EMMC_IRPT_EN_DMA_ERR_CLR 0xefffffff + #define EMMC_IRPT_EN_DMA_ERR_MSB 28 + #define EMMC_IRPT_EN_DMA_ERR_LSB 28 + #define EMMC_IRPT_EN_TUNE_ERR_BITS 26:26 + #define EMMC_IRPT_EN_TUNE_ERR_SET 0x04000000 + #define EMMC_IRPT_EN_TUNE_ERR_CLR 0xfbffffff + #define EMMC_IRPT_EN_TUNE_ERR_MSB 26 + #define EMMC_IRPT_EN_TUNE_ERR_LSB 26 + #define EMMC_IRPT_EN_ADMA_ERR_BITS 25:25 + #define EMMC_IRPT_EN_ADMA_ERR_SET 0x02000000 + #define EMMC_IRPT_EN_ADMA_ERR_CLR 0xfdffffff + #define EMMC_IRPT_EN_ADMA_ERR_MSB 25 + #define EMMC_IRPT_EN_ADMA_ERR_LSB 25 + #define EMMC_IRPT_EN_ACMD_ERR_BITS 24:24 + #define EMMC_IRPT_EN_ACMD_ERR_SET 0x01000000 + #define EMMC_IRPT_EN_ACMD_ERR_CLR 0xfeffffff + #define EMMC_IRPT_EN_ACMD_ERR_MSB 24 + #define EMMC_IRPT_EN_ACMD_ERR_LSB 24 + #define EMMC_IRPT_EN_SDOFF_ERR_BITS 23:23 + #define EMMC_IRPT_EN_SDOFF_ERR_SET 0x00800000 + #define EMMC_IRPT_EN_SDOFF_ERR_CLR 0xff7fffff + #define EMMC_IRPT_EN_SDOFF_ERR_MSB 23 + #define EMMC_IRPT_EN_SDOFF_ERR_LSB 23 + #define EMMC_IRPT_EN_DEND_ERR_BITS 22:22 + #define EMMC_IRPT_EN_DEND_ERR_SET 0x00400000 + #define EMMC_IRPT_EN_DEND_ERR_CLR 0xffbfffff + #define EMMC_IRPT_EN_DEND_ERR_MSB 22 + #define EMMC_IRPT_EN_DEND_ERR_LSB 22 + #define EMMC_IRPT_EN_DCRC_ERR_BITS 21:21 + #define EMMC_IRPT_EN_DCRC_ERR_SET 0x00200000 + #define EMMC_IRPT_EN_DCRC_ERR_CLR 0xffdfffff + #define EMMC_IRPT_EN_DCRC_ERR_MSB 21 + #define EMMC_IRPT_EN_DCRC_ERR_LSB 21 + #define EMMC_IRPT_EN_DTO_ERR_BITS 20:20 + #define EMMC_IRPT_EN_DTO_ERR_SET 0x00100000 + #define EMMC_IRPT_EN_DTO_ERR_CLR 0xffefffff + #define EMMC_IRPT_EN_DTO_ERR_MSB 20 + #define EMMC_IRPT_EN_DTO_ERR_LSB 20 + #define EMMC_IRPT_EN_CBAD_ERR_BITS 19:19 + #define EMMC_IRPT_EN_CBAD_ERR_SET 0x00080000 + #define EMMC_IRPT_EN_CBAD_ERR_CLR 0xfff7ffff + #define EMMC_IRPT_EN_CBAD_ERR_MSB 19 + #define EMMC_IRPT_EN_CBAD_ERR_LSB 19 + #define EMMC_IRPT_EN_CEND_ERR_BITS 18:18 + #define EMMC_IRPT_EN_CEND_ERR_SET 0x00040000 + #define EMMC_IRPT_EN_CEND_ERR_CLR 0xfffbffff + #define EMMC_IRPT_EN_CEND_ERR_MSB 18 + #define EMMC_IRPT_EN_CEND_ERR_LSB 18 + #define EMMC_IRPT_EN_CCRC_ERR_BITS 17:17 + #define EMMC_IRPT_EN_CCRC_ERR_SET 0x00020000 + #define EMMC_IRPT_EN_CCRC_ERR_CLR 0xfffdffff + #define EMMC_IRPT_EN_CCRC_ERR_MSB 17 + #define EMMC_IRPT_EN_CCRC_ERR_LSB 17 + #define EMMC_IRPT_EN_CTO_ERR_BITS 16:16 + #define EMMC_IRPT_EN_CTO_ERR_SET 0x00010000 + #define EMMC_IRPT_EN_CTO_ERR_CLR 0xfffeffff + #define EMMC_IRPT_EN_CTO_ERR_MSB 16 + #define EMMC_IRPT_EN_CTO_ERR_LSB 16 + #define EMMC_IRPT_EN_ENDBOOT_BITS 14:14 + #define EMMC_IRPT_EN_ENDBOOT_SET 0x00004000 + #define EMMC_IRPT_EN_ENDBOOT_CLR 0xffffbfff + #define EMMC_IRPT_EN_ENDBOOT_MSB 14 + #define EMMC_IRPT_EN_ENDBOOT_LSB 14 + #define EMMC_IRPT_EN_BOOTACK_BITS 13:13 + #define EMMC_IRPT_EN_BOOTACK_SET 0x00002000 + #define EMMC_IRPT_EN_BOOTACK_CLR 0xffffdfff + #define EMMC_IRPT_EN_BOOTACK_MSB 13 + #define EMMC_IRPT_EN_BOOTACK_LSB 13 + #define EMMC_IRPT_EN_RETUNE_BITS 12:12 + #define EMMC_IRPT_EN_RETUNE_SET 0x00001000 + #define EMMC_IRPT_EN_RETUNE_CLR 0xffffefff + #define EMMC_IRPT_EN_RETUNE_MSB 12 + #define EMMC_IRPT_EN_RETUNE_LSB 12 + #define EMMC_IRPT_EN_INT_C_BITS 11:11 + #define EMMC_IRPT_EN_INT_C_SET 0x00000800 + #define EMMC_IRPT_EN_INT_C_CLR 0xfffff7ff + #define EMMC_IRPT_EN_INT_C_MSB 11 + #define EMMC_IRPT_EN_INT_C_LSB 11 + #define EMMC_IRPT_EN_INT_B_BITS 10:10 + #define EMMC_IRPT_EN_INT_B_SET 0x00000400 + #define EMMC_IRPT_EN_INT_B_CLR 0xfffffbff + #define EMMC_IRPT_EN_INT_B_MSB 10 + #define EMMC_IRPT_EN_INT_B_LSB 10 + #define EMMC_IRPT_EN_INT_A_BITS 9:9 + #define EMMC_IRPT_EN_INT_A_SET 0x00000200 + #define EMMC_IRPT_EN_INT_A_CLR 0xfffffdff + #define EMMC_IRPT_EN_INT_A_MSB 9 + #define EMMC_IRPT_EN_INT_A_LSB 9 + #define EMMC_IRPT_EN_CARD_BITS 8:8 + #define EMMC_IRPT_EN_CARD_SET 0x00000100 + #define EMMC_IRPT_EN_CARD_CLR 0xfffffeff + #define EMMC_IRPT_EN_CARD_MSB 8 + #define EMMC_IRPT_EN_CARD_LSB 8 + #define EMMC_IRPT_EN_CARD_OUT_BITS 7:7 + #define EMMC_IRPT_EN_CARD_OUT_SET 0x00000080 + #define EMMC_IRPT_EN_CARD_OUT_CLR 0xffffff7f + #define EMMC_IRPT_EN_CARD_OUT_MSB 7 + #define EMMC_IRPT_EN_CARD_OUT_LSB 7 + #define EMMC_IRPT_EN_CARD_IN_BITS 6:6 + #define EMMC_IRPT_EN_CARD_IN_SET 0x00000040 + #define EMMC_IRPT_EN_CARD_IN_CLR 0xffffffbf + #define EMMC_IRPT_EN_CARD_IN_MSB 6 + #define EMMC_IRPT_EN_CARD_IN_LSB 6 + #define EMMC_IRPT_EN_READ_RDY_BITS 5:5 + #define EMMC_IRPT_EN_READ_RDY_SET 0x00000020 + #define EMMC_IRPT_EN_READ_RDY_CLR 0xffffffdf + #define EMMC_IRPT_EN_READ_RDY_MSB 5 + #define EMMC_IRPT_EN_READ_RDY_LSB 5 + #define EMMC_IRPT_EN_WRITE_RDY_BITS 4:4 + #define EMMC_IRPT_EN_WRITE_RDY_SET 0x00000010 + #define EMMC_IRPT_EN_WRITE_RDY_CLR 0xffffffef + #define EMMC_IRPT_EN_WRITE_RDY_MSB 4 + #define EMMC_IRPT_EN_WRITE_RDY_LSB 4 + #define EMMC_IRPT_EN_DMA_BITS 3:3 + #define EMMC_IRPT_EN_DMA_SET 0x00000008 + #define EMMC_IRPT_EN_DMA_CLR 0xfffffff7 + #define EMMC_IRPT_EN_DMA_MSB 3 + #define EMMC_IRPT_EN_DMA_LSB 3 + #define EMMC_IRPT_EN_BLOCK_GAP_BITS 2:2 + #define EMMC_IRPT_EN_BLOCK_GAP_SET 0x00000004 + #define EMMC_IRPT_EN_BLOCK_GAP_CLR 0xfffffffb + #define EMMC_IRPT_EN_BLOCK_GAP_MSB 2 + #define EMMC_IRPT_EN_BLOCK_GAP_LSB 2 + #define EMMC_IRPT_EN_DATA_DONE_BITS 1:1 + #define EMMC_IRPT_EN_DATA_DONE_SET 0x00000002 + #define EMMC_IRPT_EN_DATA_DONE_CLR 0xfffffffd + #define EMMC_IRPT_EN_DATA_DONE_MSB 1 + #define EMMC_IRPT_EN_DATA_DONE_LSB 1 + #define EMMC_IRPT_EN_CMD_DONE_BITS 0:0 + #define EMMC_IRPT_EN_CMD_DONE_SET 0x00000001 + #define EMMC_IRPT_EN_CMD_DONE_CLR 0xfffffffe + #define EMMC_IRPT_EN_CMD_DONE_MSB 0 + #define EMMC_IRPT_EN_CMD_DONE_LSB 0 +#define EMMC_CONTROL2 HW_REGISTER_RW( 0x7e30003c ) + #define EMMC_CONTROL2_MASK 0xc0ff009f + #define EMMC_CONTROL2_WIDTH 32 + #define EMMC_CONTROL2_RESET 0x00080000 + #define EMMC_CONTROL2_EN_PSV_BITS 31:31 + #define EMMC_CONTROL2_EN_PSV_SET 0x80000000 + #define EMMC_CONTROL2_EN_PSV_CLR 0x7fffffff + #define EMMC_CONTROL2_EN_PSV_MSB 31 + #define EMMC_CONTROL2_EN_PSV_LSB 31 + #define EMMC_CONTROL2_EN_AINT_BITS 30:30 + #define EMMC_CONTROL2_EN_AINT_SET 0x40000000 + #define EMMC_CONTROL2_EN_AINT_CLR 0xbfffffff + #define EMMC_CONTROL2_EN_AINT_MSB 30 + #define EMMC_CONTROL2_EN_AINT_LSB 30 + #define EMMC_CONTROL2_TUNED_BITS 23:23 + #define EMMC_CONTROL2_TUNED_SET 0x00800000 + #define EMMC_CONTROL2_TUNED_CLR 0xff7fffff + #define EMMC_CONTROL2_TUNED_MSB 23 + #define EMMC_CONTROL2_TUNED_LSB 23 + #define EMMC_CONTROL2_TUNEON_BITS 22:22 + #define EMMC_CONTROL2_TUNEON_SET 0x00400000 + #define EMMC_CONTROL2_TUNEON_CLR 0xffbfffff + #define EMMC_CONTROL2_TUNEON_MSB 22 + #define EMMC_CONTROL2_TUNEON_LSB 22 + #define EMMC_CONTROL2_DRVTYPE_BITS 21:20 + #define EMMC_CONTROL2_DRVTYPE_SET 0x00300000 + #define EMMC_CONTROL2_DRVTYPE_CLR 0xffcfffff + #define EMMC_CONTROL2_DRVTYPE_MSB 21 + #define EMMC_CONTROL2_DRVTYPE_LSB 20 + #define EMMC_CONTROL2_SIGTYPE_BITS 19:19 + #define EMMC_CONTROL2_SIGTYPE_SET 0x00080000 + #define EMMC_CONTROL2_SIGTYPE_CLR 0xfff7ffff + #define EMMC_CONTROL2_SIGTYPE_MSB 19 + #define EMMC_CONTROL2_SIGTYPE_LSB 19 + #define EMMC_CONTROL2_UHSMODE_BITS 18:16 + #define EMMC_CONTROL2_UHSMODE_SET 0x00070000 + #define EMMC_CONTROL2_UHSMODE_CLR 0xfff8ffff + #define EMMC_CONTROL2_UHSMODE_MSB 18 + #define EMMC_CONTROL2_UHSMODE_LSB 16 + #define EMMC_CONTROL2_NOTC12_ERR_BITS 7:7 + #define EMMC_CONTROL2_NOTC12_ERR_SET 0x00000080 + #define EMMC_CONTROL2_NOTC12_ERR_CLR 0xffffff7f + #define EMMC_CONTROL2_NOTC12_ERR_MSB 7 + #define EMMC_CONTROL2_NOTC12_ERR_LSB 7 + #define EMMC_CONTROL2_ACBAD_ERR_BITS 4:4 + #define EMMC_CONTROL2_ACBAD_ERR_SET 0x00000010 + #define EMMC_CONTROL2_ACBAD_ERR_CLR 0xffffffef + #define EMMC_CONTROL2_ACBAD_ERR_MSB 4 + #define EMMC_CONTROL2_ACBAD_ERR_LSB 4 + #define EMMC_CONTROL2_ACEND_ERR_BITS 3:3 + #define EMMC_CONTROL2_ACEND_ERR_SET 0x00000008 + #define EMMC_CONTROL2_ACEND_ERR_CLR 0xfffffff7 + #define EMMC_CONTROL2_ACEND_ERR_MSB 3 + #define EMMC_CONTROL2_ACEND_ERR_LSB 3 + #define EMMC_CONTROL2_ACCRC_ERR_BITS 2:2 + #define EMMC_CONTROL2_ACCRC_ERR_SET 0x00000004 + #define EMMC_CONTROL2_ACCRC_ERR_CLR 0xfffffffb + #define EMMC_CONTROL2_ACCRC_ERR_MSB 2 + #define EMMC_CONTROL2_ACCRC_ERR_LSB 2 + #define EMMC_CONTROL2_ACTO_ERR_BITS 1:1 + #define EMMC_CONTROL2_ACTO_ERR_SET 0x00000002 + #define EMMC_CONTROL2_ACTO_ERR_CLR 0xfffffffd + #define EMMC_CONTROL2_ACTO_ERR_MSB 1 + #define EMMC_CONTROL2_ACTO_ERR_LSB 1 + #define EMMC_CONTROL2_ACNOX_ERR_BITS 0:0 + #define EMMC_CONTROL2_ACNOX_ERR_SET 0x00000001 + #define EMMC_CONTROL2_ACNOX_ERR_CLR 0xfffffffe + #define EMMC_CONTROL2_ACNOX_ERR_MSB 0 + #define EMMC_CONTROL2_ACNOX_ERR_LSB 0 +#define EMMC_HWCAP0 HW_REGISTER_RW( 0x7e300040 ) + #define EMMC_HWCAP0_MASK 0xffffffff + #define EMMC_HWCAP0_WIDTH 32 + #define EMMC_HWCAP0_RESET 0000000000 + #define EMMC_HWCAP0_SLOT_TYPE_BITS 31:30 + #define EMMC_HWCAP0_SLOT_TYPE_SET 0xc0000000 + #define EMMC_HWCAP0_SLOT_TYPE_CLR 0x3fffffff + #define EMMC_HWCAP0_SLOT_TYPE_MSB 31 + #define EMMC_HWCAP0_SLOT_TYPE_LSB 30 + #define EMMC_HWCAP0_AINT_BITS 29:29 + #define EMMC_HWCAP0_AINT_SET 0x20000000 + #define EMMC_HWCAP0_AINT_CLR 0xdfffffff + #define EMMC_HWCAP0_AINT_MSB 29 + #define EMMC_HWCAP0_AINT_LSB 29 + #define EMMC_HWCAP0_BUS64_BITS 28:28 + #define EMMC_HWCAP0_BUS64_SET 0x10000000 + #define EMMC_HWCAP0_BUS64_CLR 0xefffffff + #define EMMC_HWCAP0_BUS64_MSB 28 + #define EMMC_HWCAP0_BUS64_LSB 28 + #define EMMC_HWCAP0_V1_8_BITS 26:26 + #define EMMC_HWCAP0_V1_8_SET 0x04000000 + #define EMMC_HWCAP0_V1_8_CLR 0xfbffffff + #define EMMC_HWCAP0_V1_8_MSB 26 + #define EMMC_HWCAP0_V1_8_LSB 26 + #define EMMC_HWCAP0_V3_0_BITS 25:25 + #define EMMC_HWCAP0_V3_0_SET 0x02000000 + #define EMMC_HWCAP0_V3_0_CLR 0xfdffffff + #define EMMC_HWCAP0_V3_0_MSB 25 + #define EMMC_HWCAP0_V3_0_LSB 25 + #define EMMC_HWCAP0_V3_3_BITS 24:24 + #define EMMC_HWCAP0_V3_3_SET 0x01000000 + #define EMMC_HWCAP0_V3_3_CLR 0xfeffffff + #define EMMC_HWCAP0_V3_3_MSB 24 + #define EMMC_HWCAP0_V3_3_LSB 24 + #define EMMC_HWCAP0_RESUME_BITS 23:23 + #define EMMC_HWCAP0_RESUME_SET 0x00800000 + #define EMMC_HWCAP0_RESUME_CLR 0xff7fffff + #define EMMC_HWCAP0_RESUME_MSB 23 + #define EMMC_HWCAP0_RESUME_LSB 23 + #define EMMC_HWCAP0_SDMA_BITS 22:22 + #define EMMC_HWCAP0_SDMA_SET 0x00400000 + #define EMMC_HWCAP0_SDMA_CLR 0xffbfffff + #define EMMC_HWCAP0_SDMA_MSB 22 + #define EMMC_HWCAP0_SDMA_LSB 22 + #define EMMC_HWCAP0_HS_BITS 21:21 + #define EMMC_HWCAP0_HS_SET 0x00200000 + #define EMMC_HWCAP0_HS_CLR 0xffdfffff + #define EMMC_HWCAP0_HS_MSB 21 + #define EMMC_HWCAP0_HS_LSB 21 + #define EMMC_HWCAP0_ADMA2_BITS 19:19 + #define EMMC_HWCAP0_ADMA2_SET 0x00080000 + #define EMMC_HWCAP0_ADMA2_CLR 0xfff7ffff + #define EMMC_HWCAP0_ADMA2_MSB 19 + #define EMMC_HWCAP0_ADMA2_LSB 19 + #define EMMC_HWCAP0_XMEDBUS_BITS 18:18 + #define EMMC_HWCAP0_XMEDBUS_SET 0x00040000 + #define EMMC_HWCAP0_XMEDBUS_CLR 0xfffbffff + #define EMMC_HWCAP0_XMEDBUS_MSB 18 + #define EMMC_HWCAP0_XMEDBUS_LSB 18 + #define EMMC_HWCAP0_MAXLEN_BITS 17:16 + #define EMMC_HWCAP0_MAXLEN_SET 0x00030000 + #define EMMC_HWCAP0_MAXLEN_CLR 0xfffcffff + #define EMMC_HWCAP0_MAXLEN_MSB 17 + #define EMMC_HWCAP0_MAXLEN_LSB 16 + #define EMMC_HWCAP0_BASEMHZ_BITS 15:8 + #define EMMC_HWCAP0_BASEMHZ_SET 0x0000ff00 + #define EMMC_HWCAP0_BASEMHZ_CLR 0xffff00ff + #define EMMC_HWCAP0_BASEMHZ_MSB 15 + #define EMMC_HWCAP0_BASEMHZ_LSB 8 + #define EMMC_HWCAP0_TCLKUNIT_BITS 7:7 + #define EMMC_HWCAP0_TCLKUNIT_SET 0x00000080 + #define EMMC_HWCAP0_TCLKUNIT_CLR 0xffffff7f + #define EMMC_HWCAP0_TCLKUNIT_MSB 7 + #define EMMC_HWCAP0_TCLKUNIT_LSB 7 + #define EMMC_HWCAP0_TCLKFREQ_BITS 5:0 + #define EMMC_HWCAP0_TCLKFREQ_SET 0x0000003f + #define EMMC_HWCAP0_TCLKFREQ_CLR 0xffffffc0 + #define EMMC_HWCAP0_TCLKFREQ_MSB 5 + #define EMMC_HWCAP0_TCLKFREQ_LSB 0 +#define EMMC_HWCAP1 HW_REGISTER_RW( 0x7e300044 ) + #define EMMC_HWCAP1_MASK 0x03ffef77 + #define EMMC_HWCAP1_WIDTH 26 + #define EMMC_HWCAP1_RESET 0x03000777 + #define EMMC_HWCAP1_SPI_BLOCKMODE_BITS 25:25 + #define EMMC_HWCAP1_SPI_BLOCKMODE_SET 0x02000000 + #define EMMC_HWCAP1_SPI_BLOCKMODE_CLR 0xfdffffff + #define EMMC_HWCAP1_SPI_BLOCKMODE_MSB 25 + #define EMMC_HWCAP1_SPI_BLOCKMODE_LSB 25 + #define EMMC_HWCAP1_SPI_MODE_BITS 24:24 + #define EMMC_HWCAP1_SPI_MODE_SET 0x01000000 + #define EMMC_HWCAP1_SPI_MODE_CLR 0xfeffffff + #define EMMC_HWCAP1_SPI_MODE_MSB 24 + #define EMMC_HWCAP1_SPI_MODE_LSB 24 + #define EMMC_HWCAP1_MULTIPLIER_BITS 23:16 + #define EMMC_HWCAP1_MULTIPLIER_SET 0x00ff0000 + #define EMMC_HWCAP1_MULTIPLIER_CLR 0xff00ffff + #define EMMC_HWCAP1_MULTIPLIER_MSB 23 + #define EMMC_HWCAP1_MULTIPLIER_LSB 16 + #define EMMC_HWCAP1_DATA_RETUNE_BITS 15:14 + #define EMMC_HWCAP1_DATA_RETUNE_SET 0x0000c000 + #define EMMC_HWCAP1_DATA_RETUNE_CLR 0xffff3fff + #define EMMC_HWCAP1_DATA_RETUNE_MSB 15 + #define EMMC_HWCAP1_DATA_RETUNE_LSB 14 + #define EMMC_HWCAP1_SDR50_TUNE_BITS 13:13 + #define EMMC_HWCAP1_SDR50_TUNE_SET 0x00002000 + #define EMMC_HWCAP1_SDR50_TUNE_CLR 0xffffdfff + #define EMMC_HWCAP1_SDR50_TUNE_MSB 13 + #define EMMC_HWCAP1_SDR50_TUNE_LSB 13 + #define EMMC_HWCAP1_RETUNE_TMR_BITS 11:8 + #define EMMC_HWCAP1_RETUNE_TMR_SET 0x00000f00 + #define EMMC_HWCAP1_RETUNE_TMR_CLR 0xfffff0ff + #define EMMC_HWCAP1_RETUNE_TMR_MSB 11 + #define EMMC_HWCAP1_RETUNE_TMR_LSB 8 + #define EMMC_HWCAP1_DRV18_TYPED_BITS 6:6 + #define EMMC_HWCAP1_DRV18_TYPED_SET 0x00000040 + #define EMMC_HWCAP1_DRV18_TYPED_CLR 0xffffffbf + #define EMMC_HWCAP1_DRV18_TYPED_MSB 6 + #define EMMC_HWCAP1_DRV18_TYPED_LSB 6 + #define EMMC_HWCAP1_DRV18_TYPEC_BITS 5:5 + #define EMMC_HWCAP1_DRV18_TYPEC_SET 0x00000020 + #define EMMC_HWCAP1_DRV18_TYPEC_CLR 0xffffffdf + #define EMMC_HWCAP1_DRV18_TYPEC_MSB 5 + #define EMMC_HWCAP1_DRV18_TYPEC_LSB 5 + #define EMMC_HWCAP1_DRV18_TYPEA_BITS 4:4 + #define EMMC_HWCAP1_DRV18_TYPEA_SET 0x00000010 + #define EMMC_HWCAP1_DRV18_TYPEA_CLR 0xffffffef + #define EMMC_HWCAP1_DRV18_TYPEA_MSB 4 + #define EMMC_HWCAP1_DRV18_TYPEA_LSB 4 + #define EMMC_HWCAP1_DDR50_BITS 2:2 + #define EMMC_HWCAP1_DDR50_SET 0x00000004 + #define EMMC_HWCAP1_DDR50_CLR 0xfffffffb + #define EMMC_HWCAP1_DDR50_MSB 2 + #define EMMC_HWCAP1_DDR50_LSB 2 + #define EMMC_HWCAP1_SDR104_BITS 1:1 + #define EMMC_HWCAP1_SDR104_SET 0x00000002 + #define EMMC_HWCAP1_SDR104_CLR 0xfffffffd + #define EMMC_HWCAP1_SDR104_MSB 1 + #define EMMC_HWCAP1_SDR104_LSB 1 + #define EMMC_HWCAP1_SDR50_BITS 0:0 + #define EMMC_HWCAP1_SDR50_SET 0x00000001 + #define EMMC_HWCAP1_SDR50_CLR 0xfffffffe + #define EMMC_HWCAP1_SDR50_MSB 0 + #define EMMC_HWCAP1_SDR50_LSB 0 +#define EMMC_HWMAXAMP0 HW_REGISTER_RW( 0x7e300048 ) + #define EMMC_HWMAXAMP0_MASK 0x00ffffff + #define EMMC_HWMAXAMP0_WIDTH 24 + #define EMMC_HWMAXAMP0_RESET 0000000000 + #define EMMC_HWMAXAMP0_AMP_18V_BITS 23:16 + #define EMMC_HWMAXAMP0_AMP_18V_SET 0x00ff0000 + #define EMMC_HWMAXAMP0_AMP_18V_CLR 0xff00ffff + #define EMMC_HWMAXAMP0_AMP_18V_MSB 23 + #define EMMC_HWMAXAMP0_AMP_18V_LSB 16 + #define EMMC_HWMAXAMP0_AMP_30V_BITS 15:8 + #define EMMC_HWMAXAMP0_AMP_30V_SET 0x0000ff00 + #define EMMC_HWMAXAMP0_AMP_30V_CLR 0xffff00ff + #define EMMC_HWMAXAMP0_AMP_30V_MSB 15 + #define EMMC_HWMAXAMP0_AMP_30V_LSB 8 + #define EMMC_HWMAXAMP0_AMP_33V_BITS 7:0 + #define EMMC_HWMAXAMP0_AMP_33V_SET 0x000000ff + #define EMMC_HWMAXAMP0_AMP_33V_CLR 0xffffff00 + #define EMMC_HWMAXAMP0_AMP_33V_MSB 7 + #define EMMC_HWMAXAMP0_AMP_33V_LSB 0 +#define EMMC_FORCE_IRPT HW_REGISTER_RW( 0x7e300050 ) + #define EMMC_FORCE_IRPT_MASK 0xffff00ff + #define EMMC_FORCE_IRPT_WIDTH 32 + #define EMMC_FORCE_IRPT_RESET 0x00000001 + #define EMMC_FORCE_IRPT_OEM_ERR_BITS 31:30 + #define EMMC_FORCE_IRPT_OEM_ERR_SET 0xc0000000 + #define EMMC_FORCE_IRPT_OEM_ERR_CLR 0x3fffffff + #define EMMC_FORCE_IRPT_OEM_ERR_MSB 31 + #define EMMC_FORCE_IRPT_OEM_ERR_LSB 30 + #define EMMC_FORCE_IRPT_ATA_ERR_BITS 29:29 + #define EMMC_FORCE_IRPT_ATA_ERR_SET 0x20000000 + #define EMMC_FORCE_IRPT_ATA_ERR_CLR 0xdfffffff + #define EMMC_FORCE_IRPT_ATA_ERR_MSB 29 + #define EMMC_FORCE_IRPT_ATA_ERR_LSB 29 + #define EMMC_FORCE_IRPT_DMA_ERR_BITS 28:28 + #define EMMC_FORCE_IRPT_DMA_ERR_SET 0x10000000 + #define EMMC_FORCE_IRPT_DMA_ERR_CLR 0xefffffff + #define EMMC_FORCE_IRPT_DMA_ERR_MSB 28 + #define EMMC_FORCE_IRPT_DMA_ERR_LSB 28 + #define EMMC_FORCE_IRPT_TUNE_ERR_BITS 26:26 + #define EMMC_FORCE_IRPT_TUNE_ERR_SET 0x04000000 + #define EMMC_FORCE_IRPT_TUNE_ERR_CLR 0xfbffffff + #define EMMC_FORCE_IRPT_TUNE_ERR_MSB 26 + #define EMMC_FORCE_IRPT_TUNE_ERR_LSB 26 + #define EMMC_FORCE_IRPT_ADMA_ERR_BITS 25:25 + #define EMMC_FORCE_IRPT_ADMA_ERR_SET 0x02000000 + #define EMMC_FORCE_IRPT_ADMA_ERR_CLR 0xfdffffff + #define EMMC_FORCE_IRPT_ADMA_ERR_MSB 25 + #define EMMC_FORCE_IRPT_ADMA_ERR_LSB 25 + #define EMMC_FORCE_IRPT_ACMD_ERR_BITS 24:24 + #define EMMC_FORCE_IRPT_ACMD_ERR_SET 0x01000000 + #define EMMC_FORCE_IRPT_ACMD_ERR_CLR 0xfeffffff + #define EMMC_FORCE_IRPT_ACMD_ERR_MSB 24 + #define EMMC_FORCE_IRPT_ACMD_ERR_LSB 24 + #define EMMC_FORCE_IRPT_SDOFF_ERR_BITS 23:23 + #define EMMC_FORCE_IRPT_SDOFF_ERR_SET 0x00800000 + #define EMMC_FORCE_IRPT_SDOFF_ERR_CLR 0xff7fffff + #define EMMC_FORCE_IRPT_SDOFF_ERR_MSB 23 + #define EMMC_FORCE_IRPT_SDOFF_ERR_LSB 23 + #define EMMC_FORCE_IRPT_DEND_ERR_BITS 22:22 + #define EMMC_FORCE_IRPT_DEND_ERR_SET 0x00400000 + #define EMMC_FORCE_IRPT_DEND_ERR_CLR 0xffbfffff + #define EMMC_FORCE_IRPT_DEND_ERR_MSB 22 + #define EMMC_FORCE_IRPT_DEND_ERR_LSB 22 + #define EMMC_FORCE_IRPT_DCRC_ERR_BITS 21:21 + #define EMMC_FORCE_IRPT_DCRC_ERR_SET 0x00200000 + #define EMMC_FORCE_IRPT_DCRC_ERR_CLR 0xffdfffff + #define EMMC_FORCE_IRPT_DCRC_ERR_MSB 21 + #define EMMC_FORCE_IRPT_DCRC_ERR_LSB 21 + #define EMMC_FORCE_IRPT_DTO_ERR_BITS 20:20 + #define EMMC_FORCE_IRPT_DTO_ERR_SET 0x00100000 + #define EMMC_FORCE_IRPT_DTO_ERR_CLR 0xffefffff + #define EMMC_FORCE_IRPT_DTO_ERR_MSB 20 + #define EMMC_FORCE_IRPT_DTO_ERR_LSB 20 + #define EMMC_FORCE_IRPT_CBAD_ERR_BITS 19:19 + #define EMMC_FORCE_IRPT_CBAD_ERR_SET 0x00080000 + #define EMMC_FORCE_IRPT_CBAD_ERR_CLR 0xfff7ffff + #define EMMC_FORCE_IRPT_CBAD_ERR_MSB 19 + #define EMMC_FORCE_IRPT_CBAD_ERR_LSB 19 + #define EMMC_FORCE_IRPT_CEND_ERR_BITS 18:18 + #define EMMC_FORCE_IRPT_CEND_ERR_SET 0x00040000 + #define EMMC_FORCE_IRPT_CEND_ERR_CLR 0xfffbffff + #define EMMC_FORCE_IRPT_CEND_ERR_MSB 18 + #define EMMC_FORCE_IRPT_CEND_ERR_LSB 18 + #define EMMC_FORCE_IRPT_CCRC_ERR_BITS 17:17 + #define EMMC_FORCE_IRPT_CCRC_ERR_SET 0x00020000 + #define EMMC_FORCE_IRPT_CCRC_ERR_CLR 0xfffdffff + #define EMMC_FORCE_IRPT_CCRC_ERR_MSB 17 + #define EMMC_FORCE_IRPT_CCRC_ERR_LSB 17 + #define EMMC_FORCE_IRPT_CTO_ERR_BITS 16:16 + #define EMMC_FORCE_IRPT_CTO_ERR_SET 0x00010000 + #define EMMC_FORCE_IRPT_CTO_ERR_CLR 0xfffeffff + #define EMMC_FORCE_IRPT_CTO_ERR_MSB 16 + #define EMMC_FORCE_IRPT_CTO_ERR_LSB 16 + #define EMMC_FORCE_IRPT_CARD_OUT_BITS 7:7 + #define EMMC_FORCE_IRPT_CARD_OUT_SET 0x00000080 + #define EMMC_FORCE_IRPT_CARD_OUT_CLR 0xffffff7f + #define EMMC_FORCE_IRPT_CARD_OUT_MSB 7 + #define EMMC_FORCE_IRPT_CARD_OUT_LSB 7 + #define EMMC_FORCE_IRPT_CARD_IN_BITS 6:6 + #define EMMC_FORCE_IRPT_CARD_IN_SET 0x00000040 + #define EMMC_FORCE_IRPT_CARD_IN_CLR 0xffffffbf + #define EMMC_FORCE_IRPT_CARD_IN_MSB 6 + #define EMMC_FORCE_IRPT_CARD_IN_LSB 6 + #define EMMC_FORCE_IRPT_READ_RDY_BITS 5:5 + #define EMMC_FORCE_IRPT_READ_RDY_SET 0x00000020 + #define EMMC_FORCE_IRPT_READ_RDY_CLR 0xffffffdf + #define EMMC_FORCE_IRPT_READ_RDY_MSB 5 + #define EMMC_FORCE_IRPT_READ_RDY_LSB 5 + #define EMMC_FORCE_IRPT_WRITE_RDY_BITS 4:4 + #define EMMC_FORCE_IRPT_WRITE_RDY_SET 0x00000010 + #define EMMC_FORCE_IRPT_WRITE_RDY_CLR 0xffffffef + #define EMMC_FORCE_IRPT_WRITE_RDY_MSB 4 + #define EMMC_FORCE_IRPT_WRITE_RDY_LSB 4 + #define EMMC_FORCE_IRPT_DMA_BITS 3:3 + #define EMMC_FORCE_IRPT_DMA_SET 0x00000008 + #define EMMC_FORCE_IRPT_DMA_CLR 0xfffffff7 + #define EMMC_FORCE_IRPT_DMA_MSB 3 + #define EMMC_FORCE_IRPT_DMA_LSB 3 + #define EMMC_FORCE_IRPT_BLOCK_GAP_BITS 2:2 + #define EMMC_FORCE_IRPT_BLOCK_GAP_SET 0x00000004 + #define EMMC_FORCE_IRPT_BLOCK_GAP_CLR 0xfffffffb + #define EMMC_FORCE_IRPT_BLOCK_GAP_MSB 2 + #define EMMC_FORCE_IRPT_BLOCK_GAP_LSB 2 + #define EMMC_FORCE_IRPT_DATA_DONE_BITS 1:1 + #define EMMC_FORCE_IRPT_DATA_DONE_SET 0x00000002 + #define EMMC_FORCE_IRPT_DATA_DONE_CLR 0xfffffffd + #define EMMC_FORCE_IRPT_DATA_DONE_MSB 1 + #define EMMC_FORCE_IRPT_DATA_DONE_LSB 1 + #define EMMC_FORCE_IRPT_CMD_DONE_BITS 0:0 + #define EMMC_FORCE_IRPT_CMD_DONE_SET 0x00000001 + #define EMMC_FORCE_IRPT_CMD_DONE_CLR 0xfffffffe + #define EMMC_FORCE_IRPT_CMD_DONE_MSB 0 + #define EMMC_FORCE_IRPT_CMD_DONE_LSB 0 +#define EMMC_DMA_STATUS HW_REGISTER_RW( 0x7e300054 ) + #define EMMC_DMA_STATUS_MASK 0xffff00ff + #define EMMC_DMA_STATUS_WIDTH 32 + #define EMMC_DMA_STATUS_RESET 0000000000 + #define EMMC_DMA_STATUS_LEN_NOMATCH_BITS 2:2 + #define EMMC_DMA_STATUS_LEN_NOMATCH_SET 0x00000004 + #define EMMC_DMA_STATUS_LEN_NOMATCH_CLR 0xfffffffb + #define EMMC_DMA_STATUS_LEN_NOMATCH_MSB 2 + #define EMMC_DMA_STATUS_LEN_NOMATCH_LSB 2 + #define EMMC_DMA_STATUS_ERR_AT_BITS 1:0 + #define EMMC_DMA_STATUS_ERR_AT_SET 0x00000003 + #define EMMC_DMA_STATUS_ERR_AT_CLR 0xfffffffc + #define EMMC_DMA_STATUS_ERR_AT_MSB 1 + #define EMMC_DMA_STATUS_ERR_AT_LSB 0 +#define EMMC_BOOT_TIMEOUT HW_REGISTER_RW( 0x7e300070 ) + #define EMMC_BOOT_TIMEOUT_MASK 0xffffffff + #define EMMC_BOOT_TIMEOUT_WIDTH 32 + #define EMMC_BOOT_TIMEOUT_RESET 0000000000 + #define EMMC_BOOT_TIMEOUT_TIMEOUT_BITS 31:0 + #define EMMC_BOOT_TIMEOUT_TIMEOUT_SET 0xffffffff + #define EMMC_BOOT_TIMEOUT_TIMEOUT_CLR 0x00000000 + #define EMMC_BOOT_TIMEOUT_TIMEOUT_MSB 31 + #define EMMC_BOOT_TIMEOUT_TIMEOUT_LSB 0 +#define EMMC_DBG_SEL HW_REGISTER_RW( 0x7e300074 ) + #define EMMC_DBG_SEL_MASK 0x00000001 + #define EMMC_DBG_SEL_WIDTH 1 + #define EMMC_DBG_SEL_RESET 0000000000 + #define EMMC_DBG_SEL_SELECT_BITS 0:0 + #define EMMC_DBG_SEL_SELECT_SET 0x00000001 + #define EMMC_DBG_SEL_SELECT_CLR 0xfffffffe + #define EMMC_DBG_SEL_SELECT_MSB 0 + #define EMMC_DBG_SEL_SELECT_LSB 0 +#define EMMC_EXRDFIFO_CFG HW_REGISTER_RW( 0x7e300080 ) + #define EMMC_EXRDFIFO_CFG_MASK 0x00000007 + #define EMMC_EXRDFIFO_CFG_WIDTH 3 + #define EMMC_EXRDFIFO_CFG_RESET 0000000000 + #define EMMC_EXRDFIFO_CFG_RD_THRSH_BITS 2:0 + #define EMMC_EXRDFIFO_CFG_RD_THRSH_SET 0x00000007 + #define EMMC_EXRDFIFO_CFG_RD_THRSH_CLR 0xfffffff8 + #define EMMC_EXRDFIFO_CFG_RD_THRSH_MSB 2 + #define EMMC_EXRDFIFO_CFG_RD_THRSH_LSB 0 +#define EMMC_EXRDFIFO_EN HW_REGISTER_RW( 0x7e300084 ) + #define EMMC_EXRDFIFO_EN_MASK 0x00000001 + #define EMMC_EXRDFIFO_EN_WIDTH 1 + #define EMMC_EXRDFIFO_EN_RESET 0000000000 + #define EMMC_EXRDFIFO_EN_ENABLE_BITS 0:0 + #define EMMC_EXRDFIFO_EN_ENABLE_SET 0x00000001 + #define EMMC_EXRDFIFO_EN_ENABLE_CLR 0xfffffffe + #define EMMC_EXRDFIFO_EN_ENABLE_MSB 0 + #define EMMC_EXRDFIFO_EN_ENABLE_LSB 0 +#define EMMC_TUNE_STEP HW_REGISTER_RW( 0x7e300088 ) + #define EMMC_TUNE_STEP_MASK 0x00000007 + #define EMMC_TUNE_STEP_WIDTH 3 + #define EMMC_TUNE_STEP_RESET 0000000000 + #define EMMC_TUNE_STEP_DELAY_BITS 2:0 + #define EMMC_TUNE_STEP_DELAY_SET 0x00000007 + #define EMMC_TUNE_STEP_DELAY_CLR 0xfffffff8 + #define EMMC_TUNE_STEP_DELAY_MSB 2 + #define EMMC_TUNE_STEP_DELAY_LSB 0 +#define EMMC_TUNE_STEPS_STD HW_REGISTER_RW( 0x7e30008c ) + #define EMMC_TUNE_STEPS_STD_MASK 0x0000003f + #define EMMC_TUNE_STEPS_STD_WIDTH 6 + #define EMMC_TUNE_STEPS_STD_RESET 0000000000 + #define EMMC_TUNE_STEPS_STD_STEPS_BITS 5:0 + #define EMMC_TUNE_STEPS_STD_STEPS_SET 0x0000003f + #define EMMC_TUNE_STEPS_STD_STEPS_CLR 0xffffffc0 + #define EMMC_TUNE_STEPS_STD_STEPS_MSB 5 + #define EMMC_TUNE_STEPS_STD_STEPS_LSB 0 +#define EMMC_TUNE_STEPS_DDR HW_REGISTER_RW( 0x7e300090 ) + #define EMMC_TUNE_STEPS_DDR_MASK 0x0000003f + #define EMMC_TUNE_STEPS_DDR_WIDTH 6 + #define EMMC_TUNE_STEPS_DDR_RESET 0000000000 + #define EMMC_TUNE_STEPS_DDR_STEPS_BITS 5:0 + #define EMMC_TUNE_STEPS_DDR_STEPS_SET 0x0000003f + #define EMMC_TUNE_STEPS_DDR_STEPS_CLR 0xffffffc0 + #define EMMC_TUNE_STEPS_DDR_STEPS_MSB 5 + #define EMMC_TUNE_STEPS_DDR_STEPS_LSB 0 +#define EMMC_BUS_CTRL HW_REGISTER_RW( 0x7e3000e0 ) + #define EMMC_BUS_CTRL_MASK 0xffffffff + #define EMMC_BUS_CTRL_WIDTH 32 + #define EMMC_BUS_CTRL_RESET 0000000000 + #define EMMC_BUS_CTRL_BE_PWR_BITS 30:24 + #define EMMC_BUS_CTRL_BE_PWR_SET 0x7f000000 + #define EMMC_BUS_CTRL_BE_PWR_CLR 0x80ffffff + #define EMMC_BUS_CTRL_BE_PWR_MSB 30 + #define EMMC_BUS_CTRL_BE_PWR_LSB 24 + #define EMMC_BUS_CTRL_IRQSEL_BITS 22:20 + #define EMMC_BUS_CTRL_IRQSEL_SET 0x00700000 + #define EMMC_BUS_CTRL_IRQSEL_CLR 0xff8fffff + #define EMMC_BUS_CTRL_IRQSEL_MSB 22 + #define EMMC_BUS_CTRL_IRQSEL_LSB 20 + #define EMMC_BUS_CTRL_BUS_WIDTH_BITS 14:8 + #define EMMC_BUS_CTRL_BUS_WIDTH_SET 0x00007f00 + #define EMMC_BUS_CTRL_BUS_WIDTH_CLR 0xffff80ff + #define EMMC_BUS_CTRL_BUS_WIDTH_MSB 14 + #define EMMC_BUS_CTRL_BUS_WIDTH_LSB 8 + #define EMMC_BUS_CTRL_IRQ_PINS_BITS 5:3 + #define EMMC_BUS_CTRL_IRQ_PINS_SET 0x00000038 + #define EMMC_BUS_CTRL_IRQ_PINS_CLR 0xffffffc7 + #define EMMC_BUS_CTRL_IRQ_PINS_MSB 5 + #define EMMC_BUS_CTRL_IRQ_PINS_LSB 3 + #define EMMC_BUS_CTRL_CLK_PINS_BITS 2:0 + #define EMMC_BUS_CTRL_CLK_PINS_SET 0x00000007 + #define EMMC_BUS_CTRL_CLK_PINS_CLR 0xfffffff8 + #define EMMC_BUS_CTRL_CLK_PINS_MSB 2 + #define EMMC_BUS_CTRL_CLK_PINS_LSB 0 +#define EMMC_SPI_INT_SPT HW_REGISTER_RW( 0x7e3000f0 ) + #define EMMC_SPI_INT_SPT_MASK 0x000000ff + #define EMMC_SPI_INT_SPT_WIDTH 8 + #define EMMC_SPI_INT_SPT_RESET 0000000000 + #define EMMC_SPI_INT_SPT_SELECT_BITS 7:0 + #define EMMC_SPI_INT_SPT_SELECT_SET 0x000000ff + #define EMMC_SPI_INT_SPT_SELECT_CLR 0xffffff00 + #define EMMC_SPI_INT_SPT_SELECT_MSB 7 + #define EMMC_SPI_INT_SPT_SELECT_LSB 0 +#define EMMC_SLOTISR_VER HW_REGISTER_RW( 0x7e3000fc ) + #define EMMC_SLOTISR_VER_MASK 0xffff00ff + #define EMMC_SLOTISR_VER_WIDTH 32 + #define EMMC_SLOTISR_VER_RESET 0x99020000 + #define EMMC_SLOTISR_VER_VENDOR_BITS 31:24 + #define EMMC_SLOTISR_VER_VENDOR_SET 0xff000000 + #define EMMC_SLOTISR_VER_VENDOR_CLR 0x00ffffff + #define EMMC_SLOTISR_VER_VENDOR_MSB 31 + #define EMMC_SLOTISR_VER_VENDOR_LSB 24 + #define EMMC_SLOTISR_VER_SDVERSION_BITS 23:16 + #define EMMC_SLOTISR_VER_SDVERSION_SET 0x00ff0000 + #define EMMC_SLOTISR_VER_SDVERSION_CLR 0xff00ffff + #define EMMC_SLOTISR_VER_SDVERSION_MSB 23 + #define EMMC_SLOTISR_VER_SDVERSION_LSB 16 + #define EMMC_SLOTISR_VER_SLOT_STATUS_BITS 7:0 + #define EMMC_SLOTISR_VER_SLOT_STATUS_SET 0x000000ff + #define EMMC_SLOTISR_VER_SLOT_STATUS_CLR 0xffffff00 + #define EMMC_SLOTISR_VER_SLOT_STATUS_MSB 7 + #define EMMC_SLOTISR_VER_SLOT_STATUS_LSB 0 diff --git a/bcm2708_chip/flow_config.tcl b/bcm2708_chip/flow_config.tcl new file mode 100755 index 0000000..1e4ac49 --- /dev/null +++ b/bcm2708_chip/flow_config.tcl @@ -0,0 +1,2 @@ +enable_flow create_regs + diff --git a/bcm2708_chip/fpga_microblaze.h b/bcm2708_chip/fpga_microblaze.h new file mode 100755 index 0000000..eaea863 --- /dev/null +++ b/bcm2708_chip/fpga_microblaze.h @@ -0,0 +1,44 @@ +// This file was generated by the create_regs script +#define FPGA_MB_BASE 0x7e20b700 +#define FPGA_MB_XSYS_BUILD_NUM HW_REGISTER_RO( 0x7e20b700 ) + #define FPGA_MB_XSYS_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XSYS_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XC0_BUILD_NUM HW_REGISTER_RO( 0x7e20b704 ) + #define FPGA_MB_XC0_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XC0_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b708 ) + #define FPGA_MB_XC1_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XC1_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XPERI_BUILD_NUM HW_REGISTER_RO( 0x7e20b70c ) + #define FPGA_MB_XPERI_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XPERI_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XH264_BUILD_NUM HW_REGISTER_RO( 0x7e20b710 ) + #define FPGA_MB_XH264_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XH264_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XV3D_BUILD_NUM HW_REGISTER_RO( 0x7e20b714 ) + #define FPGA_MB_XV3D_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XV3D_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XSLC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b718 ) + #define FPGA_MB_XSLC1_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XSLC1_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XSLC2_BUILD_NUM HW_REGISTER_RO( 0x7e20b71c ) + #define FPGA_MB_XSLC2_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XSLC2_BUILD_NUM_WIDTH 32 +#define FPGA_MB_XSLC3_BUILD_NUM HW_REGISTER_RO( 0x7e20b720 ) + #define FPGA_MB_XSLC3_BUILD_NUM_MASK 0xffffffff + #define FPGA_MB_XSLC3_BUILD_NUM_WIDTH 32 +#define FPGA_MB_CORE_CLK_FREQ HW_REGISTER_RO( 0x7e20b724 ) + #define FPGA_MB_CORE_CLK_FREQ_MASK 0xffffffff + #define FPGA_MB_CORE_CLK_FREQ_WIDTH 32 +#define FPGA_MB_SDC_CLK_FREQ HW_REGISTER_RO( 0x7e20b728 ) + #define FPGA_MB_SDC_CLK_FREQ_MASK 0xffffffff + #define FPGA_MB_SDC_CLK_FREQ_WIDTH 32 +#define FPGA_MB_SDC_H264_FREQ HW_REGISTER_RO( 0x7e20b72c ) + #define FPGA_MB_SDC_H264_FREQ_MASK 0xffffffff + #define FPGA_MB_SDC_H264_FREQ_WIDTH 32 +#define FPGA_MB_SDC_V3D_FREQ HW_REGISTER_RO( 0x7e20b730 ) + #define FPGA_MB_SDC_V3D_FREQ_MASK 0xffffffff + #define FPGA_MB_SDC_V3D_FREQ_WIDTH 32 +#define FPGA_MB_SDC_ISP_FREQ HW_REGISTER_RO( 0x7e20b734 ) + #define FPGA_MB_SDC_ISP_FREQ_MASK 0xffffffff + #define FPGA_MB_SDC_ISP_FREQ_WIDTH 32 diff --git a/bcm2708_chip/fpga_peripheral.h b/bcm2708_chip/fpga_peripheral.h new file mode 100755 index 0000000..e37652d --- /dev/null +++ b/bcm2708_chip/fpga_peripheral.h @@ -0,0 +1,206 @@ +#define FPGA_A0_BASE 0x7e213000 +#define FPGA_B0_BASE 0x7e214000 +#define FPGA_CTRL0_OFFSET 0x08 +#define FPGA_STATUS0_OFFSET 0x0C + + +// This file was generated by the create_regs script + +#define FPGA_BASE 0x7e20b600 +#define FPGA_APB_ID 0x66706761 +#define FPGA_VERSION HW_REGISTER_RO( 0x7e20b600 ) + #define FPGA_VERSION_MASK 0xffffffff + #define FPGA_VERSION_WIDTH 32 +#define FPGA_SCRATCH HW_REGISTER_RW( 0x7e20b604 ) + #define FPGA_SCRATCH_MASK 0xffffffff + #define FPGA_SCRATCH_WIDTH 32 +#define FPGA_CTRL0 HW_REGISTER_RW( 0x7e20b608 ) + #define FPGA_CTRL0_MASK 0xfffff3fff + #define FPGA_CTRL0_WIDTH 36 + #define FPGA_CTRL0_SPARE_OUT_BITS 31:20 + #define FPGA_CTRL0_SPARE_OUT_SET 0xfff00000 + #define FPGA_CTRL0_SPARE_OUT_CLR 0x000fffff + #define FPGA_CTRL0_SPARE_OUT_MSB 31 + #define FPGA_CTRL0_SPARE_OUT_LSB 20 + #define FPGA_CTRL0_LV_SPARE_OUT_BITS 19:18 + #define FPGA_CTRL0_LV_SPARE_OUT_SET 0x000c0000 + #define FPGA_CTRL0_LV_SPARE_OUT_CLR 0xfff3ffff + #define FPGA_CTRL0_LV_SPARE_OUT_MSB 19 + #define FPGA_CTRL0_LV_SPARE_OUT_LSB 18 + #define FPGA_CTRL0_TERMEN_CLK_BITS 17:17 + #define FPGA_CTRL0_TERMEN_CLK_SET 0x00020000 + #define FPGA_CTRL0_TERMEN_CLK_CLR 0xfffdffff + #define FPGA_CTRL0_TERMEN_CLK_MSB 17 + #define FPGA_CTRL0_TERMEN_CLK_LSB 17 + #define FPGA_CTRL0_TERMEN_DO_BITS 16:16 + #define FPGA_CTRL0_TERMEN_DO_SET 0x00010000 + #define FPGA_CTRL0_TERMEN_DO_CLR 0xfffeffff + #define FPGA_CTRL0_TERMEN_DO_MSB 16 + #define FPGA_CTRL0_TERMEN_DO_LSB 16 + #define FPGA_CTRL0_TV_ACTIVITY_BITS 13:13 + #define FPGA_CTRL0_TV_ACTIVITY_SET 0x00002000 + #define FPGA_CTRL0_TV_ACTIVITY_CLR 0xffffdfff + #define FPGA_CTRL0_TV_ACTIVITY_MSB 13 + #define FPGA_CTRL0_TV_ACTIVITY_LSB 13 + #define FPGA_CTRL0_SPI0_SEL_B_BITS 12:12 + #define FPGA_CTRL0_SPI0_SEL_B_SET 0x00001000 + #define FPGA_CTRL0_SPI0_SEL_B_CLR 0xffffefff + #define FPGA_CTRL0_SPI0_SEL_B_MSB 12 + #define FPGA_CTRL0_SPI0_SEL_B_LSB 12 + #define FPGA_CTRL0_DISP_BUFFER_BITS 11:11 + #define FPGA_CTRL0_DISP_BUFFER_SET 0x00000800 + #define FPGA_CTRL0_DISP_BUFFER_CLR 0xfffff7ff + #define FPGA_CTRL0_DISP_BUFFER_MSB 11 + #define FPGA_CTRL0_DISP_BUFFER_LSB 11 + #define FPGA_CTRL0_SPI1_SEL_BITS 10:10 + #define FPGA_CTRL0_SPI1_SEL_SET 0x00000400 + #define FPGA_CTRL0_SPI1_SEL_CLR 0xfffffbff + #define FPGA_CTRL0_SPI1_SEL_MSB 10 + #define FPGA_CTRL0_SPI1_SEL_LSB 10 + #define FPGA_CTRL0_SPI0_SEL_A_BITS 9:9 + #define FPGA_CTRL0_SPI0_SEL_A_SET 0x00000200 + #define FPGA_CTRL0_SPI0_SEL_A_CLR 0xfffffdff + #define FPGA_CTRL0_SPI0_SEL_A_MSB 9 + #define FPGA_CTRL0_SPI0_SEL_A_LSB 9 + #define FPGA_CTRL0_SW_SPI_CS_BITS 8:8 + #define FPGA_CTRL0_SW_SPI_CS_SET 0x00000100 + #define FPGA_CTRL0_SW_SPI_CS_CLR 0xfffffeff + #define FPGA_CTRL0_SW_SPI_CS_MSB 8 + #define FPGA_CTRL0_SW_SPI_CS_LSB 8 + #define FPGA_CTRL0_SW_SPI_SDA_O_BITS 7:7 + #define FPGA_CTRL0_SW_SPI_SDA_O_SET 0x00000080 + #define FPGA_CTRL0_SW_SPI_SDA_O_CLR 0xffffff7f + #define FPGA_CTRL0_SW_SPI_SDA_O_MSB 7 + #define FPGA_CTRL0_SW_SPI_SDA_O_LSB 7 + #define FPGA_CTRL0_SW_SPI_SCL_BITS 6:6 + #define FPGA_CTRL0_SW_SPI_SCL_SET 0x00000040 + #define FPGA_CTRL0_SW_SPI_SCL_CLR 0xffffffbf + #define FPGA_CTRL0_SW_SPI_SCL_MSB 6 + #define FPGA_CTRL0_SW_SPI_SCL_LSB 6 + #define FPGA_CTRL0_DIS_SW_SPI_BITS 5:5 + #define FPGA_CTRL0_DIS_SW_SPI_SET 0x00000020 + #define FPGA_CTRL0_DIS_SW_SPI_CLR 0xffffffdf + #define FPGA_CTRL0_DIS_SW_SPI_MSB 5 + #define FPGA_CTRL0_DIS_SW_SPI_LSB 5 + #define FPGA_CTRL0_SD_PSU_EN_BITS 4:4 + #define FPGA_CTRL0_SD_PSU_EN_SET 0x00000010 + #define FPGA_CTRL0_SD_PSU_EN_CLR 0xffffffef + #define FPGA_CTRL0_SD_PSU_EN_MSB 4 + #define FPGA_CTRL0_SD_PSU_EN_LSB 4 + #define FPGA_CTRL0_DIS_RST_BITS 3:3 + #define FPGA_CTRL0_DIS_RST_SET 0x00000008 + #define FPGA_CTRL0_DIS_RST_CLR 0xfffffff7 + #define FPGA_CTRL0_DIS_RST_MSB 3 + #define FPGA_CTRL0_DIS_RST_LSB 3 + #define FPGA_CTRL0_DIS_CTL2_BITS 2:2 + #define FPGA_CTRL0_DIS_CTL2_SET 0x00000004 + #define FPGA_CTRL0_DIS_CTL2_CLR 0xfffffffb + #define FPGA_CTRL0_DIS_CTL2_MSB 2 + #define FPGA_CTRL0_DIS_CTL2_LSB 2 + #define FPGA_CTRL0_DIS_BL_BITS 1:1 + #define FPGA_CTRL0_DIS_BL_SET 0x00000002 + #define FPGA_CTRL0_DIS_BL_CLR 0xfffffffd + #define FPGA_CTRL0_DIS_BL_MSB 1 + #define FPGA_CTRL0_DIS_BL_LSB 1 + #define FPGA_CTRL0_DIS_CTL0_BITS 0:0 + #define FPGA_CTRL0_DIS_CTL0_SET 0x00000001 + #define FPGA_CTRL0_DIS_CTL0_CLR 0xfffffffe + #define FPGA_CTRL0_DIS_CTL0_MSB 0 + #define FPGA_CTRL0_DIS_CTL0_LSB 0 + #define FPGA_CTRL0_CAM_CTL2_BITS 2:2 + #define FPGA_CTRL0_CAM_CTL2_SET 0x00000004 + #define FPGA_CTRL0_CAM_CTL2_CLR 0xfffffffb + #define FPGA_CTRL0_CAM_CTL2_MSB 2 + #define FPGA_CTRL0_CAM_CTL2_LSB 2 + #define FPGA_CTRL0_CAM_CTL1_BITS 1:1 + #define FPGA_CTRL0_CAM_CTL1_SET 0x00000002 + #define FPGA_CTRL0_CAM_CTL1_CLR 0xfffffffd + #define FPGA_CTRL0_CAM_CTL1_MSB 1 + #define FPGA_CTRL0_CAM_CTL1_LSB 1 + #define FPGA_CTRL0_CAM_CTL0_BITS 0:0 + #define FPGA_CTRL0_CAM_CTL0_SET 0x00000001 + #define FPGA_CTRL0_CAM_CTL0_CLR 0xfffffffe + #define FPGA_CTRL0_CAM_CTL0_MSB 0 + #define FPGA_CTRL0_CAM_CTL0_LSB 0 +#define FPGA_STATUS0 HW_REGISTER_RO( 0x7e20b60c ) + #define FPGA_STATUS0_MASK 0xfff800ff + #define FPGA_STATUS0_WIDTH 32 + #define FPGA_STATUS0_SPARE_IN_BITS 31:19 + #define FPGA_STATUS0_SPARE_IN_SET 0xfff80000 + #define FPGA_STATUS0_SPARE_IN_CLR 0x0007ffff + #define FPGA_STATUS0_SPARE_IN_MSB 31 + #define FPGA_STATUS0_SPARE_IN_LSB 19 + #define FPGA_STATUS0_SW_SPI_SPI_IN_BITS 7:7 + #define FPGA_STATUS0_SW_SPI_SPI_IN_SET 0x00000080 + #define FPGA_STATUS0_SW_SPI_SPI_IN_CLR 0xffffff7f + #define FPGA_STATUS0_SW_SPI_SPI_IN_MSB 7 + #define FPGA_STATUS0_SW_SPI_SPI_IN_LSB 7 + #define FPGA_STATUS0_NAND_RNB_BITS 6:6 + #define FPGA_STATUS0_NAND_RNB_SET 0x00000040 + #define FPGA_STATUS0_NAND_RNB_CLR 0xffffffbf + #define FPGA_STATUS0_NAND_RNB_MSB 6 + #define FPGA_STATUS0_NAND_RNB_LSB 6 + #define FPGA_STATUS0_SD_CD_BITS 5:5 + #define FPGA_STATUS0_SD_CD_SET 0x00000020 + #define FPGA_STATUS0_SD_CD_CLR 0xffffffdf + #define FPGA_STATUS0_SD_CD_MSB 5 + #define FPGA_STATUS0_SD_CD_LSB 5 + #define FPGA_STATUS0_SD_WP_BITS 4:4 + #define FPGA_STATUS0_SD_WP_SET 0x00000010 + #define FPGA_STATUS0_SD_WP_CLR 0xffffffef + #define FPGA_STATUS0_SD_WP_MSB 4 + #define FPGA_STATUS0_SD_WP_LSB 4 + #define FPGA_STATUS0_HW_ID_BITS 3:0 + #define FPGA_STATUS0_HW_ID_SET 0x0000000f + #define FPGA_STATUS0_HW_ID_CLR 0xfffffff0 + #define FPGA_STATUS0_HW_ID_MSB 3 + #define FPGA_STATUS0_HW_ID_LSB 0 +#define FPGA_DCM_WR_DATA HW_REGISTER_RW( 0x7e20b610 ) + #define FPGA_DCM_WR_DATA_MASK 0x00ffffff + #define FPGA_DCM_WR_DATA_WIDTH 24 + #define FPGA_DCM_WR_DATA_ADDRESS_BITS 23:16 + #define FPGA_DCM_WR_DATA_ADDRESS_SET 0x00ff0000 + #define FPGA_DCM_WR_DATA_ADDRESS_CLR 0xff00ffff + #define FPGA_DCM_WR_DATA_ADDRESS_MSB 23 + #define FPGA_DCM_WR_DATA_ADDRESS_LSB 16 + #define FPGA_DCM_WR_DATA_DATA_BITS 15:0 + #define FPGA_DCM_WR_DATA_DATA_SET 0x0000ffff + #define FPGA_DCM_WR_DATA_DATA_CLR 0xffff0000 + #define FPGA_DCM_WR_DATA_DATA_MSB 15 + #define FPGA_DCM_WR_DATA_DATA_LSB 0 +#define FPGA_DCM_CTRL HW_REGISTER_RW( 0x7e20b614 ) + #define FPGA_DCM_CTRL_MASK 0xff0fffff + #define FPGA_DCM_CTRL_WIDTH 32 + #define FPGA_DCM_CTRL_PERI_WR_EN_BITS 31:28 + #define FPGA_DCM_CTRL_PERI_WR_EN_SET 0xf0000000 + #define FPGA_DCM_CTRL_PERI_WR_EN_CLR 0x0fffffff + #define FPGA_DCM_CTRL_PERI_WR_EN_MSB 31 + #define FPGA_DCM_CTRL_PERI_WR_EN_LSB 28 + #define FPGA_DCM_CTRL_PERI_EN_BITS 27:24 + #define FPGA_DCM_CTRL_PERI_EN_SET 0x0f000000 + #define FPGA_DCM_CTRL_PERI_EN_CLR 0xf0ffffff + #define FPGA_DCM_CTRL_PERI_EN_MSB 27 + #define FPGA_DCM_CTRL_PERI_EN_LSB 24 + #define FPGA_DCM_CTRL_PERI_RST_BITS 19:16 + #define FPGA_DCM_CTRL_PERI_RST_SET 0x000f0000 + #define FPGA_DCM_CTRL_PERI_RST_CLR 0xfff0ffff + #define FPGA_DCM_CTRL_PERI_RST_MSB 19 + #define FPGA_DCM_CTRL_PERI_RST_LSB 16 + #define FPGA_DCM_CTRL_REMOTE_EN_BITS 12:8 + #define FPGA_DCM_CTRL_REMOTE_EN_SET 0x00001f00 + #define FPGA_DCM_CTRL_REMOTE_EN_CLR 0xffffe0ff + #define FPGA_DCM_CTRL_REMOTE_EN_MSB 12 + #define FPGA_DCM_CTRL_REMOTE_EN_LSB 8 + #define FPGA_DCM_CTRL_REMOTE_RST_BITS 4:0 + #define FPGA_DCM_CTRL_REMOTE_RST_SET 0x0000001f + #define FPGA_DCM_CTRL_REMOTE_RST_CLR 0xffffffe0 + #define FPGA_DCM_CTRL_REMOTE_RST_MSB 4 + #define FPGA_DCM_CTRL_REMOTE_RST_LSB 0 +#define FPGA_DCM_RD_DATA HW_REGISTER_RO( 0x7e20b618 ) + #define FPGA_DCM_RD_DATA_MASK 0x0000ffff + #define FPGA_DCM_RD_DATA_WIDTH 16 + #define FPGA_DCM_RD_DATA_DATA_BITS 15:0 + #define FPGA_DCM_RD_DATA_DATA_SET 0x0000ffff + #define FPGA_DCM_RD_DATA_DATA_CLR 0xffff0000 + #define FPGA_DCM_RD_DATA_DATA_MSB 15 + #define FPGA_DCM_RD_DATA_DATA_LSB 0 diff --git a/bcm2708_chip/gpio.h b/bcm2708_chip/gpio.h new file mode 100755 index 0000000..c80f389 --- /dev/null +++ b/bcm2708_chip/gpio.h @@ -0,0 +1,735 @@ +// This file was generated by the create_regs script +#define GP_BASE 0x7e200000 +#define GP_APB_ID 0x6770696f +#define GP_FSEL0 HW_REGISTER_RW( 0x7e200000 ) + #define GP_FSEL0_MASK 0x3fffffff + #define GP_FSEL0_WIDTH 30 + #define GP_FSEL0_RESET 0000000000 + #define GP_FSEL0_FSEL09_BITS 29:27 + #define GP_FSEL0_FSEL09_SET 0x38000000 + #define GP_FSEL0_FSEL09_CLR 0xc7ffffff + #define GP_FSEL0_FSEL09_MSB 29 + #define GP_FSEL0_FSEL09_LSB 27 + #define GP_FSEL0_FSEL08_BITS 26:24 + #define GP_FSEL0_FSEL08_SET 0x07000000 + #define GP_FSEL0_FSEL08_CLR 0xf8ffffff + #define GP_FSEL0_FSEL08_MSB 26 + #define GP_FSEL0_FSEL08_LSB 24 + #define GP_FSEL0_FSEL07_BITS 23:21 + #define GP_FSEL0_FSEL07_SET 0x00e00000 + #define GP_FSEL0_FSEL07_CLR 0xff1fffff + #define GP_FSEL0_FSEL07_MSB 23 + #define GP_FSEL0_FSEL07_LSB 21 + #define GP_FSEL0_FSEL06_BITS 20:18 + #define GP_FSEL0_FSEL06_SET 0x001c0000 + #define GP_FSEL0_FSEL06_CLR 0xffe3ffff + #define GP_FSEL0_FSEL06_MSB 20 + #define GP_FSEL0_FSEL06_LSB 18 + #define GP_FSEL0_FSEL05_BITS 17:15 + #define GP_FSEL0_FSEL05_SET 0x00038000 + #define GP_FSEL0_FSEL05_CLR 0xfffc7fff + #define GP_FSEL0_FSEL05_MSB 17 + #define GP_FSEL0_FSEL05_LSB 15 + #define GP_FSEL0_FSEL04_BITS 14:12 + #define GP_FSEL0_FSEL04_SET 0x00007000 + #define GP_FSEL0_FSEL04_CLR 0xffff8fff + #define GP_FSEL0_FSEL04_MSB 14 + #define GP_FSEL0_FSEL04_LSB 12 + #define GP_FSEL0_FSEL03_BITS 11:9 + #define GP_FSEL0_FSEL03_SET 0x00000e00 + #define GP_FSEL0_FSEL03_CLR 0xfffff1ff + #define GP_FSEL0_FSEL03_MSB 11 + #define GP_FSEL0_FSEL03_LSB 9 + #define GP_FSEL0_FSEL02_BITS 8:6 + #define GP_FSEL0_FSEL02_SET 0x000001c0 + #define GP_FSEL0_FSEL02_CLR 0xfffffe3f + #define GP_FSEL0_FSEL02_MSB 8 + #define GP_FSEL0_FSEL02_LSB 6 + #define GP_FSEL0_FSEL01_BITS 5:3 + #define GP_FSEL0_FSEL01_SET 0x00000038 + #define GP_FSEL0_FSEL01_CLR 0xffffffc7 + #define GP_FSEL0_FSEL01_MSB 5 + #define GP_FSEL0_FSEL01_LSB 3 + #define GP_FSEL0_FSEL00_BITS 2:0 + #define GP_FSEL0_FSEL00_SET 0x00000007 + #define GP_FSEL0_FSEL00_CLR 0xfffffff8 + #define GP_FSEL0_FSEL00_MSB 2 + #define GP_FSEL0_FSEL00_LSB 0 +#define GP_FSEL1 HW_REGISTER_RW( 0x7e200004 ) + #define GP_FSEL1_MASK 0x3fffffff + #define GP_FSEL1_WIDTH 30 + #define GP_FSEL1_RESET 0000000000 + #define GP_FSEL1_FSEL19_BITS 29:27 + #define GP_FSEL1_FSEL19_SET 0x38000000 + #define GP_FSEL1_FSEL19_CLR 0xc7ffffff + #define GP_FSEL1_FSEL19_MSB 29 + #define GP_FSEL1_FSEL19_LSB 27 + #define GP_FSEL1_FSEL18_BITS 26:24 + #define GP_FSEL1_FSEL18_SET 0x07000000 + #define GP_FSEL1_FSEL18_CLR 0xf8ffffff + #define GP_FSEL1_FSEL18_MSB 26 + #define GP_FSEL1_FSEL18_LSB 24 + #define GP_FSEL1_FSEL17_BITS 23:21 + #define GP_FSEL1_FSEL17_SET 0x00e00000 + #define GP_FSEL1_FSEL17_CLR 0xff1fffff + #define GP_FSEL1_FSEL17_MSB 23 + #define GP_FSEL1_FSEL17_LSB 21 + #define GP_FSEL1_FSEL16_BITS 20:18 + #define GP_FSEL1_FSEL16_SET 0x001c0000 + #define GP_FSEL1_FSEL16_CLR 0xffe3ffff + #define GP_FSEL1_FSEL16_MSB 20 + #define GP_FSEL1_FSEL16_LSB 18 + #define GP_FSEL1_FSEL15_BITS 17:15 + #define GP_FSEL1_FSEL15_SET 0x00038000 + #define GP_FSEL1_FSEL15_CLR 0xfffc7fff + #define GP_FSEL1_FSEL15_MSB 17 + #define GP_FSEL1_FSEL15_LSB 15 + #define GP_FSEL1_FSEL14_BITS 14:12 + #define GP_FSEL1_FSEL14_SET 0x00007000 + #define GP_FSEL1_FSEL14_CLR 0xffff8fff + #define GP_FSEL1_FSEL14_MSB 14 + #define GP_FSEL1_FSEL14_LSB 12 + #define GP_FSEL1_FSEL13_BITS 11:9 + #define GP_FSEL1_FSEL13_SET 0x00000e00 + #define GP_FSEL1_FSEL13_CLR 0xfffff1ff + #define GP_FSEL1_FSEL13_MSB 11 + #define GP_FSEL1_FSEL13_LSB 9 + #define GP_FSEL1_FSEL12_BITS 8:6 + #define GP_FSEL1_FSEL12_SET 0x000001c0 + #define GP_FSEL1_FSEL12_CLR 0xfffffe3f + #define GP_FSEL1_FSEL12_MSB 8 + #define GP_FSEL1_FSEL12_LSB 6 + #define GP_FSEL1_FSEL11_BITS 5:3 + #define GP_FSEL1_FSEL11_SET 0x00000038 + #define GP_FSEL1_FSEL11_CLR 0xffffffc7 + #define GP_FSEL1_FSEL11_MSB 5 + #define GP_FSEL1_FSEL11_LSB 3 + #define GP_FSEL1_FSEL10_BITS 2:0 + #define GP_FSEL1_FSEL10_SET 0x00000007 + #define GP_FSEL1_FSEL10_CLR 0xfffffff8 + #define GP_FSEL1_FSEL10_MSB 2 + #define GP_FSEL1_FSEL10_LSB 0 +#define GP_FSEL2 HW_REGISTER_RW( 0x7e200008 ) + #define GP_FSEL2_MASK 0x3fffffff + #define GP_FSEL2_WIDTH 30 + #define GP_FSEL2_RESET 0000000000 + #define GP_FSEL2_FSEL29_BITS 29:27 + #define GP_FSEL2_FSEL29_SET 0x38000000 + #define GP_FSEL2_FSEL29_CLR 0xc7ffffff + #define GP_FSEL2_FSEL29_MSB 29 + #define GP_FSEL2_FSEL29_LSB 27 + #define GP_FSEL2_FSEL28_BITS 26:24 + #define GP_FSEL2_FSEL28_SET 0x07000000 + #define GP_FSEL2_FSEL28_CLR 0xf8ffffff + #define GP_FSEL2_FSEL28_MSB 26 + #define GP_FSEL2_FSEL28_LSB 24 + #define GP_FSEL2_FSEL27_BITS 23:21 + #define GP_FSEL2_FSEL27_SET 0x00e00000 + #define GP_FSEL2_FSEL27_CLR 0xff1fffff + #define GP_FSEL2_FSEL27_MSB 23 + #define GP_FSEL2_FSEL27_LSB 21 + #define GP_FSEL2_FSEL26_BITS 20:18 + #define GP_FSEL2_FSEL26_SET 0x001c0000 + #define GP_FSEL2_FSEL26_CLR 0xffe3ffff + #define GP_FSEL2_FSEL26_MSB 20 + #define GP_FSEL2_FSEL26_LSB 18 + #define GP_FSEL2_FSEL25_BITS 17:15 + #define GP_FSEL2_FSEL25_SET 0x00038000 + #define GP_FSEL2_FSEL25_CLR 0xfffc7fff + #define GP_FSEL2_FSEL25_MSB 17 + #define GP_FSEL2_FSEL25_LSB 15 + #define GP_FSEL2_FSEL24_BITS 14:12 + #define GP_FSEL2_FSEL24_SET 0x00007000 + #define GP_FSEL2_FSEL24_CLR 0xffff8fff + #define GP_FSEL2_FSEL24_MSB 14 + #define GP_FSEL2_FSEL24_LSB 12 + #define GP_FSEL2_FSEL23_BITS 11:9 + #define GP_FSEL2_FSEL23_SET 0x00000e00 + #define GP_FSEL2_FSEL23_CLR 0xfffff1ff + #define GP_FSEL2_FSEL23_MSB 11 + #define GP_FSEL2_FSEL23_LSB 9 + #define GP_FSEL2_FSEL22_BITS 8:6 + #define GP_FSEL2_FSEL22_SET 0x000001c0 + #define GP_FSEL2_FSEL22_CLR 0xfffffe3f + #define GP_FSEL2_FSEL22_MSB 8 + #define GP_FSEL2_FSEL22_LSB 6 + #define GP_FSEL2_FSEL21_BITS 5:3 + #define GP_FSEL2_FSEL21_SET 0x00000038 + #define GP_FSEL2_FSEL21_CLR 0xffffffc7 + #define GP_FSEL2_FSEL21_MSB 5 + #define GP_FSEL2_FSEL21_LSB 3 + #define GP_FSEL2_FSEL20_BITS 2:0 + #define GP_FSEL2_FSEL20_SET 0x00000007 + #define GP_FSEL2_FSEL20_CLR 0xfffffff8 + #define GP_FSEL2_FSEL20_MSB 2 + #define GP_FSEL2_FSEL20_LSB 0 +#define GP_FSEL3 HW_REGISTER_RW( 0x7e20000c ) + #define GP_FSEL3_MASK 0x3fffffff + #define GP_FSEL3_WIDTH 30 + #define GP_FSEL3_RESET 0000000000 + #define GP_FSEL3_FSEL39_BITS 29:27 + #define GP_FSEL3_FSEL39_SET 0x38000000 + #define GP_FSEL3_FSEL39_CLR 0xc7ffffff + #define GP_FSEL3_FSEL39_MSB 29 + #define GP_FSEL3_FSEL39_LSB 27 + #define GP_FSEL3_FSEL38_BITS 26:24 + #define GP_FSEL3_FSEL38_SET 0x07000000 + #define GP_FSEL3_FSEL38_CLR 0xf8ffffff + #define GP_FSEL3_FSEL38_MSB 26 + #define GP_FSEL3_FSEL38_LSB 24 + #define GP_FSEL3_FSEL37_BITS 23:21 + #define GP_FSEL3_FSEL37_SET 0x00e00000 + #define GP_FSEL3_FSEL37_CLR 0xff1fffff + #define GP_FSEL3_FSEL37_MSB 23 + #define GP_FSEL3_FSEL37_LSB 21 + #define GP_FSEL3_FSEL36_BITS 20:18 + #define GP_FSEL3_FSEL36_SET 0x001c0000 + #define GP_FSEL3_FSEL36_CLR 0xffe3ffff + #define GP_FSEL3_FSEL36_MSB 20 + #define GP_FSEL3_FSEL36_LSB 18 + #define GP_FSEL3_FSEL35_BITS 17:15 + #define GP_FSEL3_FSEL35_SET 0x00038000 + #define GP_FSEL3_FSEL35_CLR 0xfffc7fff + #define GP_FSEL3_FSEL35_MSB 17 + #define GP_FSEL3_FSEL35_LSB 15 + #define GP_FSEL3_FSEL34_BITS 14:12 + #define GP_FSEL3_FSEL34_SET 0x00007000 + #define GP_FSEL3_FSEL34_CLR 0xffff8fff + #define GP_FSEL3_FSEL34_MSB 14 + #define GP_FSEL3_FSEL34_LSB 12 + #define GP_FSEL3_FSEL33_BITS 11:9 + #define GP_FSEL3_FSEL33_SET 0x00000e00 + #define GP_FSEL3_FSEL33_CLR 0xfffff1ff + #define GP_FSEL3_FSEL33_MSB 11 + #define GP_FSEL3_FSEL33_LSB 9 + #define GP_FSEL3_FSEL32_BITS 8:6 + #define GP_FSEL3_FSEL32_SET 0x000001c0 + #define GP_FSEL3_FSEL32_CLR 0xfffffe3f + #define GP_FSEL3_FSEL32_MSB 8 + #define GP_FSEL3_FSEL32_LSB 6 + #define GP_FSEL3_FSEL31_BITS 5:3 + #define GP_FSEL3_FSEL31_SET 0x00000038 + #define GP_FSEL3_FSEL31_CLR 0xffffffc7 + #define GP_FSEL3_FSEL31_MSB 5 + #define GP_FSEL3_FSEL31_LSB 3 + #define GP_FSEL3_FSEL30_BITS 2:0 + #define GP_FSEL3_FSEL30_SET 0x00000007 + #define GP_FSEL3_FSEL30_CLR 0xfffffff8 + #define GP_FSEL3_FSEL30_MSB 2 + #define GP_FSEL3_FSEL30_LSB 0 +#define GP_FSEL4 HW_REGISTER_RW( 0x7e200010 ) + #define GP_FSEL4_MASK 0x3fffffff + #define GP_FSEL4_WIDTH 30 + #define GP_FSEL4_RESET 0000000000 + #define GP_FSEL4_FSEL49_BITS 29:27 + #define GP_FSEL4_FSEL49_SET 0x38000000 + #define GP_FSEL4_FSEL49_CLR 0xc7ffffff + #define GP_FSEL4_FSEL49_MSB 29 + #define GP_FSEL4_FSEL49_LSB 27 + #define GP_FSEL4_FSEL48_BITS 26:24 + #define GP_FSEL4_FSEL48_SET 0x07000000 + #define GP_FSEL4_FSEL48_CLR 0xf8ffffff + #define GP_FSEL4_FSEL48_MSB 26 + #define GP_FSEL4_FSEL48_LSB 24 + #define GP_FSEL4_FSEL47_BITS 23:21 + #define GP_FSEL4_FSEL47_SET 0x00e00000 + #define GP_FSEL4_FSEL47_CLR 0xff1fffff + #define GP_FSEL4_FSEL47_MSB 23 + #define GP_FSEL4_FSEL47_LSB 21 + #define GP_FSEL4_FSEL46_BITS 20:18 + #define GP_FSEL4_FSEL46_SET 0x001c0000 + #define GP_FSEL4_FSEL46_CLR 0xffe3ffff + #define GP_FSEL4_FSEL46_MSB 20 + #define GP_FSEL4_FSEL46_LSB 18 + #define GP_FSEL4_FSEL45_BITS 17:15 + #define GP_FSEL4_FSEL45_SET 0x00038000 + #define GP_FSEL4_FSEL45_CLR 0xfffc7fff + #define GP_FSEL4_FSEL45_MSB 17 + #define GP_FSEL4_FSEL45_LSB 15 + #define GP_FSEL4_FSEL44_BITS 14:12 + #define GP_FSEL4_FSEL44_SET 0x00007000 + #define GP_FSEL4_FSEL44_CLR 0xffff8fff + #define GP_FSEL4_FSEL44_MSB 14 + #define GP_FSEL4_FSEL44_LSB 12 + #define GP_FSEL4_FSEL43_BITS 11:9 + #define GP_FSEL4_FSEL43_SET 0x00000e00 + #define GP_FSEL4_FSEL43_CLR 0xfffff1ff + #define GP_FSEL4_FSEL43_MSB 11 + #define GP_FSEL4_FSEL43_LSB 9 + #define GP_FSEL4_FSEL42_BITS 8:6 + #define GP_FSEL4_FSEL42_SET 0x000001c0 + #define GP_FSEL4_FSEL42_CLR 0xfffffe3f + #define GP_FSEL4_FSEL42_MSB 8 + #define GP_FSEL4_FSEL42_LSB 6 + #define GP_FSEL4_FSEL41_BITS 5:3 + #define GP_FSEL4_FSEL41_SET 0x00000038 + #define GP_FSEL4_FSEL41_CLR 0xffffffc7 + #define GP_FSEL4_FSEL41_MSB 5 + #define GP_FSEL4_FSEL41_LSB 3 + #define GP_FSEL4_FSEL40_BITS 2:0 + #define GP_FSEL4_FSEL40_SET 0x00000007 + #define GP_FSEL4_FSEL40_CLR 0xfffffff8 + #define GP_FSEL4_FSEL40_MSB 2 + #define GP_FSEL4_FSEL40_LSB 0 +#define GP_FSEL5 HW_REGISTER_RW( 0x7e200014 ) + #define GP_FSEL5_MASK 0x3fffffff + #define GP_FSEL5_WIDTH 30 + #define GP_FSEL5_RESET 0000000000 + #define GP_FSEL5_FSEL59_BITS 29:27 + #define GP_FSEL5_FSEL59_SET 0x38000000 + #define GP_FSEL5_FSEL59_CLR 0xc7ffffff + #define GP_FSEL5_FSEL59_MSB 29 + #define GP_FSEL5_FSEL59_LSB 27 + #define GP_FSEL5_FSEL58_BITS 26:24 + #define GP_FSEL5_FSEL58_SET 0x07000000 + #define GP_FSEL5_FSEL58_CLR 0xf8ffffff + #define GP_FSEL5_FSEL58_MSB 26 + #define GP_FSEL5_FSEL58_LSB 24 + #define GP_FSEL5_FSEL57_BITS 23:21 + #define GP_FSEL5_FSEL57_SET 0x00e00000 + #define GP_FSEL5_FSEL57_CLR 0xff1fffff + #define GP_FSEL5_FSEL57_MSB 23 + #define GP_FSEL5_FSEL57_LSB 21 + #define GP_FSEL5_FSEL56_BITS 20:18 + #define GP_FSEL5_FSEL56_SET 0x001c0000 + #define GP_FSEL5_FSEL56_CLR 0xffe3ffff + #define GP_FSEL5_FSEL56_MSB 20 + #define GP_FSEL5_FSEL56_LSB 18 + #define GP_FSEL5_FSEL55_BITS 17:15 + #define GP_FSEL5_FSEL55_SET 0x00038000 + #define GP_FSEL5_FSEL55_CLR 0xfffc7fff + #define GP_FSEL5_FSEL55_MSB 17 + #define GP_FSEL5_FSEL55_LSB 15 + #define GP_FSEL5_FSEL54_BITS 14:12 + #define GP_FSEL5_FSEL54_SET 0x00007000 + #define GP_FSEL5_FSEL54_CLR 0xffff8fff + #define GP_FSEL5_FSEL54_MSB 14 + #define GP_FSEL5_FSEL54_LSB 12 + #define GP_FSEL5_FSEL53_BITS 11:9 + #define GP_FSEL5_FSEL53_SET 0x00000e00 + #define GP_FSEL5_FSEL53_CLR 0xfffff1ff + #define GP_FSEL5_FSEL53_MSB 11 + #define GP_FSEL5_FSEL53_LSB 9 + #define GP_FSEL5_FSEL52_BITS 8:6 + #define GP_FSEL5_FSEL52_SET 0x000001c0 + #define GP_FSEL5_FSEL52_CLR 0xfffffe3f + #define GP_FSEL5_FSEL52_MSB 8 + #define GP_FSEL5_FSEL52_LSB 6 + #define GP_FSEL5_FSEL51_BITS 5:3 + #define GP_FSEL5_FSEL51_SET 0x00000038 + #define GP_FSEL5_FSEL51_CLR 0xffffffc7 + #define GP_FSEL5_FSEL51_MSB 5 + #define GP_FSEL5_FSEL51_LSB 3 + #define GP_FSEL5_FSEL50_BITS 2:0 + #define GP_FSEL5_FSEL50_SET 0x00000007 + #define GP_FSEL5_FSEL50_CLR 0xfffffff8 + #define GP_FSEL5_FSEL50_MSB 2 + #define GP_FSEL5_FSEL50_LSB 0 +#define GP_FSEL6 HW_REGISTER_RW( 0x7e200018 ) + #define GP_FSEL6_MASK 0x3fffffff + #define GP_FSEL6_WIDTH 30 + #define GP_FSEL6_RESET 0000000000 + #define GP_FSEL6_FSEL69_BITS 29:27 + #define GP_FSEL6_FSEL69_SET 0x38000000 + #define GP_FSEL6_FSEL69_CLR 0xc7ffffff + #define GP_FSEL6_FSEL69_MSB 29 + #define GP_FSEL6_FSEL69_LSB 27 + #define GP_FSEL6_FSEL68_BITS 26:24 + #define GP_FSEL6_FSEL68_SET 0x07000000 + #define GP_FSEL6_FSEL68_CLR 0xf8ffffff + #define GP_FSEL6_FSEL68_MSB 26 + #define GP_FSEL6_FSEL68_LSB 24 + #define GP_FSEL6_FSEL67_BITS 23:21 + #define GP_FSEL6_FSEL67_SET 0x00e00000 + #define GP_FSEL6_FSEL67_CLR 0xff1fffff + #define GP_FSEL6_FSEL67_MSB 23 + #define GP_FSEL6_FSEL67_LSB 21 + #define GP_FSEL6_FSEL66_BITS 20:18 + #define GP_FSEL6_FSEL66_SET 0x001c0000 + #define GP_FSEL6_FSEL66_CLR 0xffe3ffff + #define GP_FSEL6_FSEL66_MSB 20 + #define GP_FSEL6_FSEL66_LSB 18 + #define GP_FSEL6_FSEL65_BITS 17:15 + #define GP_FSEL6_FSEL65_SET 0x00038000 + #define GP_FSEL6_FSEL65_CLR 0xfffc7fff + #define GP_FSEL6_FSEL65_MSB 17 + #define GP_FSEL6_FSEL65_LSB 15 + #define GP_FSEL6_FSEL64_BITS 14:12 + #define GP_FSEL6_FSEL64_SET 0x00007000 + #define GP_FSEL6_FSEL64_CLR 0xffff8fff + #define GP_FSEL6_FSEL64_MSB 14 + #define GP_FSEL6_FSEL64_LSB 12 + #define GP_FSEL6_FSEL63_BITS 11:9 + #define GP_FSEL6_FSEL63_SET 0x00000e00 + #define GP_FSEL6_FSEL63_CLR 0xfffff1ff + #define GP_FSEL6_FSEL63_MSB 11 + #define GP_FSEL6_FSEL63_LSB 9 + #define GP_FSEL6_FSEL62_BITS 8:6 + #define GP_FSEL6_FSEL62_SET 0x000001c0 + #define GP_FSEL6_FSEL62_CLR 0xfffffe3f + #define GP_FSEL6_FSEL62_MSB 8 + #define GP_FSEL6_FSEL62_LSB 6 + #define GP_FSEL6_FSEL61_BITS 5:3 + #define GP_FSEL6_FSEL61_SET 0x00000038 + #define GP_FSEL6_FSEL61_CLR 0xffffffc7 + #define GP_FSEL6_FSEL61_MSB 5 + #define GP_FSEL6_FSEL61_LSB 3 + #define GP_FSEL6_FSEL60_BITS 2:0 + #define GP_FSEL6_FSEL60_SET 0x00000007 + #define GP_FSEL6_FSEL60_CLR 0xfffffff8 + #define GP_FSEL6_FSEL60_MSB 2 + #define GP_FSEL6_FSEL60_LSB 0 +#define GP_SET0 HW_REGISTER_RW( 0x7e20001c ) + #define GP_SET0_MASK 0xffffffff + #define GP_SET0_WIDTH 32 + #define GP_SET0_RESET 0000000000 + #define GP_SET0_SETn0_BITS 31:0 + #define GP_SET0_SETn0_SET 0xffffffff + #define GP_SET0_SETn0_CLR 0x00000000 + #define GP_SET0_SETn0_MSB 31 + #define GP_SET0_SETn0_LSB 0 +#define GP_SET1 HW_REGISTER_RW( 0x7e200020 ) + #define GP_SET1_MASK 0xffffffff + #define GP_SET1_WIDTH 32 + #define GP_SET1_RESET 0000000000 + #define GP_SET1_SETn32_BITS 31:0 + #define GP_SET1_SETn32_SET 0xffffffff + #define GP_SET1_SETn32_CLR 0x00000000 + #define GP_SET1_SETn32_MSB 31 + #define GP_SET1_SETn32_LSB 0 +#define GP_SET2 HW_REGISTER_RW( 0x7e200024 ) + #define GP_SET2_MASK 0x0000003f + #define GP_SET2_WIDTH 6 + #define GP_SET2_RESET 0000000000 + #define GP_SET2_SETn64_BITS 5:0 + #define GP_SET2_SETn64_SET 0x0000003f + #define GP_SET2_SETn64_CLR 0xffffffc0 + #define GP_SET2_SETn64_MSB 5 + #define GP_SET2_SETn64_LSB 0 +#define GP_CLR0 HW_REGISTER_RW( 0x7e200028 ) + #define GP_CLR0_MASK 0xffffffff + #define GP_CLR0_WIDTH 32 + #define GP_CLR0_RESET 0000000000 + #define GP_CLR0_CLRn0_BITS 31:0 + #define GP_CLR0_CLRn0_SET 0xffffffff + #define GP_CLR0_CLRn0_CLR 0x00000000 + #define GP_CLR0_CLRn0_MSB 31 + #define GP_CLR0_CLRn0_LSB 0 +#define GP_CLR1 HW_REGISTER_RW( 0x7e20002c ) + #define GP_CLR1_MASK 0xffffffff + #define GP_CLR1_WIDTH 32 + #define GP_CLR1_RESET 0000000000 + #define GP_CLR1_CLRn32_BITS 31:0 + #define GP_CLR1_CLRn32_SET 0xffffffff + #define GP_CLR1_CLRn32_CLR 0x00000000 + #define GP_CLR1_CLRn32_MSB 31 + #define GP_CLR1_CLRn32_LSB 0 +#define GP_CLR2 HW_REGISTER_RW( 0x7e200030 ) + #define GP_CLR2_MASK 0x0000003f + #define GP_CLR2_WIDTH 6 + #define GP_CLR2_RESET 0000000000 + #define GP_CLR2_CLRn64_BITS 5:0 + #define GP_CLR2_CLRn64_SET 0x0000003f + #define GP_CLR2_CLRn64_CLR 0xffffffc0 + #define GP_CLR2_CLRn64_MSB 5 + #define GP_CLR2_CLRn64_LSB 0 +#define GP_LEV0 HW_REGISTER_RO( 0x7e200034 ) + #define GP_LEV0_MASK 0xffffffff + #define GP_LEV0_WIDTH 32 + #define GP_LEV0_RESET 0000000000 + #define GP_LEV0_LEVn0_BITS 31:0 + #define GP_LEV0_LEVn0_SET 0xffffffff + #define GP_LEV0_LEVn0_CLR 0x00000000 + #define GP_LEV0_LEVn0_MSB 31 + #define GP_LEV0_LEVn0_LSB 0 +#define GP_LEV1 HW_REGISTER_RO( 0x7e200038 ) + #define GP_LEV1_MASK 0xffffffff + #define GP_LEV1_WIDTH 32 + #define GP_LEV1_RESET 0000000000 + #define GP_LEV1_LEVn32_BITS 31:0 + #define GP_LEV1_LEVn32_SET 0xffffffff + #define GP_LEV1_LEVn32_CLR 0x00000000 + #define GP_LEV1_LEVn32_MSB 31 + #define GP_LEV1_LEVn32_LSB 0 +#define GP_LEV2 HW_REGISTER_RO( 0x7e20003c ) + #define GP_LEV2_MASK 0x0000003f + #define GP_LEV2_WIDTH 6 + #define GP_LEV2_RESET 0000000000 + #define GP_LEV2_LEVn64_BITS 5:0 + #define GP_LEV2_LEVn64_SET 0x0000003f + #define GP_LEV2_LEVn64_CLR 0xffffffc0 + #define GP_LEV2_LEVn64_MSB 5 + #define GP_LEV2_LEVn64_LSB 0 +#define GP_EDS0 HW_REGISTER_RW( 0x7e200040 ) + #define GP_EDS0_MASK 0xffffffff + #define GP_EDS0_WIDTH 32 + #define GP_EDS0_RESET 0000000000 + #define GP_EDS0_EDSn0_BITS 31:0 + #define GP_EDS0_EDSn0_SET 0xffffffff + #define GP_EDS0_EDSn0_CLR 0x00000000 + #define GP_EDS0_EDSn0_MSB 31 + #define GP_EDS0_EDSn0_LSB 0 +#define GP_EDS1 HW_REGISTER_RW( 0x7e200044 ) + #define GP_EDS1_MASK 0xffffffff + #define GP_EDS1_WIDTH 32 + #define GP_EDS1_RESET 0000000000 + #define GP_EDS1_EDSn32_BITS 31:0 + #define GP_EDS1_EDSn32_SET 0xffffffff + #define GP_EDS1_EDSn32_CLR 0x00000000 + #define GP_EDS1_EDSn32_MSB 31 + #define GP_EDS1_EDSn32_LSB 0 +#define GP_EDS2 HW_REGISTER_RW( 0x7e200048 ) + #define GP_EDS2_MASK 0x0000003f + #define GP_EDS2_WIDTH 6 + #define GP_EDS2_RESET 0000000000 + #define GP_EDS2_EDSn64_BITS 5:0 + #define GP_EDS2_EDSn64_SET 0x0000003f + #define GP_EDS2_EDSn64_CLR 0xffffffc0 + #define GP_EDS2_EDSn64_MSB 5 + #define GP_EDS2_EDSn64_LSB 0 +#define GP_REN0 HW_REGISTER_RW( 0x7e20004c ) + #define GP_REN0_MASK 0xffffffff + #define GP_REN0_WIDTH 32 + #define GP_REN0_RESET 0000000000 + #define GP_REN0_RENn0_BITS 31:0 + #define GP_REN0_RENn0_SET 0xffffffff + #define GP_REN0_RENn0_CLR 0x00000000 + #define GP_REN0_RENn0_MSB 31 + #define GP_REN0_RENn0_LSB 0 +#define GP_REN1 HW_REGISTER_RW( 0x7e200050 ) + #define GP_REN1_MASK 0xffffffff + #define GP_REN1_WIDTH 32 + #define GP_REN1_RESET 0000000000 + #define GP_REN1_RENn32_BITS 31:0 + #define GP_REN1_RENn32_SET 0xffffffff + #define GP_REN1_RENn32_CLR 0x00000000 + #define GP_REN1_RENn32_MSB 31 + #define GP_REN1_RENn32_LSB 0 +#define GP_REN2 HW_REGISTER_RW( 0x7e200054 ) + #define GP_REN2_MASK 0x0000003f + #define GP_REN2_WIDTH 6 + #define GP_REN2_RESET 0000000000 + #define GP_REN2_RENn64_BITS 5:0 + #define GP_REN2_RENn64_SET 0x0000003f + #define GP_REN2_RENn64_CLR 0xffffffc0 + #define GP_REN2_RENn64_MSB 5 + #define GP_REN2_RENn64_LSB 0 +#define GP_FEN0 HW_REGISTER_RW( 0x7e200058 ) + #define GP_FEN0_MASK 0xffffffff + #define GP_FEN0_WIDTH 32 + #define GP_FEN0_RESET 0000000000 + #define GP_FEN0_FENn0_BITS 31:0 + #define GP_FEN0_FENn0_SET 0xffffffff + #define GP_FEN0_FENn0_CLR 0x00000000 + #define GP_FEN0_FENn0_MSB 31 + #define GP_FEN0_FENn0_LSB 0 +#define GP_FEN1 HW_REGISTER_RW( 0x7e20005c ) + #define GP_FEN1_MASK 0xffffffff + #define GP_FEN1_WIDTH 32 + #define GP_FEN1_RESET 0000000000 + #define GP_FEN1_FENn32_BITS 31:0 + #define GP_FEN1_FENn32_SET 0xffffffff + #define GP_FEN1_FENn32_CLR 0x00000000 + #define GP_FEN1_FENn32_MSB 31 + #define GP_FEN1_FENn32_LSB 0 +#define GP_FEN2 HW_REGISTER_RW( 0x7e200060 ) + #define GP_FEN2_MASK 0x0000003f + #define GP_FEN2_WIDTH 6 + #define GP_FEN2_RESET 0000000000 + #define GP_FEN2_FENn64_BITS 5:0 + #define GP_FEN2_FENn64_SET 0x0000003f + #define GP_FEN2_FENn64_CLR 0xffffffc0 + #define GP_FEN2_FENn64_MSB 5 + #define GP_FEN2_FENn64_LSB 0 +#define GP_HEN0 HW_REGISTER_RW( 0x7e200064 ) + #define GP_HEN0_MASK 0xffffffff + #define GP_HEN0_WIDTH 32 + #define GP_HEN0_RESET 0000000000 + #define GP_HEN0_HENn0_BITS 31:0 + #define GP_HEN0_HENn0_SET 0xffffffff + #define GP_HEN0_HENn0_CLR 0x00000000 + #define GP_HEN0_HENn0_MSB 31 + #define GP_HEN0_HENn0_LSB 0 +#define GP_HEN1 HW_REGISTER_RW( 0x7e200068 ) + #define GP_HEN1_MASK 0xffffffff + #define GP_HEN1_WIDTH 32 + #define GP_HEN1_RESET 0000000000 + #define GP_HEN1_HENn32_BITS 31:0 + #define GP_HEN1_HENn32_SET 0xffffffff + #define GP_HEN1_HENn32_CLR 0x00000000 + #define GP_HEN1_HENn32_MSB 31 + #define GP_HEN1_HENn32_LSB 0 +#define GP_HEN2 HW_REGISTER_RW( 0x7e20006c ) + #define GP_HEN2_MASK 0x0000003f + #define GP_HEN2_WIDTH 6 + #define GP_HEN2_RESET 0000000000 + #define GP_HEN2_HENn64_BITS 5:0 + #define GP_HEN2_HENn64_SET 0x0000003f + #define GP_HEN2_HENn64_CLR 0xffffffc0 + #define GP_HEN2_HENn64_MSB 5 + #define GP_HEN2_HENn64_LSB 0 +#define GP_LEN0 HW_REGISTER_RW( 0x7e200070 ) + #define GP_LEN0_MASK 0xffffffff + #define GP_LEN0_WIDTH 32 + #define GP_LEN0_RESET 0000000000 + #define GP_LEN0_LENn0_BITS 31:0 + #define GP_LEN0_LENn0_SET 0xffffffff + #define GP_LEN0_LENn0_CLR 0x00000000 + #define GP_LEN0_LENn0_MSB 31 + #define GP_LEN0_LENn0_LSB 0 +#define GP_LEN1 HW_REGISTER_RW( 0x7e200074 ) + #define GP_LEN1_MASK 0xffffffff + #define GP_LEN1_WIDTH 32 + #define GP_LEN1_RESET 0000000000 + #define GP_LEN1_LENn32_BITS 31:0 + #define GP_LEN1_LENn32_SET 0xffffffff + #define GP_LEN1_LENn32_CLR 0x00000000 + #define GP_LEN1_LENn32_MSB 31 + #define GP_LEN1_LENn32_LSB 0 +#define GP_LEN2 HW_REGISTER_RW( 0x7e200078 ) + #define GP_LEN2_MASK 0x0000003f + #define GP_LEN2_WIDTH 6 + #define GP_LEN2_RESET 0000000000 + #define GP_LEN2_LENn64_BITS 5:0 + #define GP_LEN2_LENn64_SET 0x0000003f + #define GP_LEN2_LENn64_CLR 0xffffffc0 + #define GP_LEN2_LENn64_MSB 5 + #define GP_LEN2_LENn64_LSB 0 +#define GP_AREN0 HW_REGISTER_RW( 0x7e20007c ) + #define GP_AREN0_MASK 0xffffffff + #define GP_AREN0_WIDTH 32 + #define GP_AREN0_RESET 0000000000 + #define GP_AREN0_ARENn0_BITS 31:0 + #define GP_AREN0_ARENn0_SET 0xffffffff + #define GP_AREN0_ARENn0_CLR 0x00000000 + #define GP_AREN0_ARENn0_MSB 31 + #define GP_AREN0_ARENn0_LSB 0 +#define GP_AREN1 HW_REGISTER_RW( 0x7e200080 ) + #define GP_AREN1_MASK 0xffffffff + #define GP_AREN1_WIDTH 32 + #define GP_AREN1_RESET 0000000000 + #define GP_AREN1_ARENn32_BITS 31:0 + #define GP_AREN1_ARENn32_SET 0xffffffff + #define GP_AREN1_ARENn32_CLR 0x00000000 + #define GP_AREN1_ARENn32_MSB 31 + #define GP_AREN1_ARENn32_LSB 0 +#define GP_AREN2 HW_REGISTER_RW( 0x7e200084 ) + #define GP_AREN2_MASK 0x0000003f + #define GP_AREN2_WIDTH 6 + #define GP_AREN2_RESET 0000000000 + #define GP_AREN2_ARENn64_BITS 5:0 + #define GP_AREN2_ARENn64_SET 0x0000003f + #define GP_AREN2_ARENn64_CLR 0xffffffc0 + #define GP_AREN2_ARENn64_MSB 5 + #define GP_AREN2_ARENn64_LSB 0 +#define GP_AFEN0 HW_REGISTER_RW( 0x7e200088 ) + #define GP_AFEN0_MASK 0xffffffff + #define GP_AFEN0_WIDTH 32 + #define GP_AFEN0_RESET 0000000000 + #define GP_AFEN0_AFENn0_BITS 31:0 + #define GP_AFEN0_AFENn0_SET 0xffffffff + #define GP_AFEN0_AFENn0_CLR 0x00000000 + #define GP_AFEN0_AFENn0_MSB 31 + #define GP_AFEN0_AFENn0_LSB 0 +#define GP_AFEN1 HW_REGISTER_RW( 0x7e20008c ) + #define GP_AFEN1_MASK 0xffffffff + #define GP_AFEN1_WIDTH 32 + #define GP_AFEN1_RESET 0000000000 + #define GP_AFEN1_AFENn32_BITS 31:0 + #define GP_AFEN1_AFENn32_SET 0xffffffff + #define GP_AFEN1_AFENn32_CLR 0x00000000 + #define GP_AFEN1_AFENn32_MSB 31 + #define GP_AFEN1_AFENn32_LSB 0 +#define GP_AFEN2 HW_REGISTER_RW( 0x7e200090 ) + #define GP_AFEN2_MASK 0x0000003f + #define GP_AFEN2_WIDTH 6 + #define GP_AFEN2_RESET 0000000000 + #define GP_AFEN2_AFENn64_BITS 5:0 + #define GP_AFEN2_AFENn64_SET 0x0000003f + #define GP_AFEN2_AFENn64_CLR 0xffffffc0 + #define GP_AFEN2_AFENn64_MSB 5 + #define GP_AFEN2_AFENn64_LSB 0 +#define GP_PUD HW_REGISTER_RW( 0x7e200094 ) + #define GP_PUD_MASK 0x00000003 + #define GP_PUD_WIDTH 2 + #define GP_PUD_RESET 0000000000 + #define GP_PUD_PUD_BITS 1:0 + #define GP_PUD_PUD_SET 0x00000003 + #define GP_PUD_PUD_CLR 0xfffffffc + #define GP_PUD_PUD_MSB 1 + #define GP_PUD_PUD_LSB 0 +#define GP_PUDCLK0 HW_REGISTER_RW( 0x7e200098 ) + #define GP_PUDCLK0_MASK 0xffffffff + #define GP_PUDCLK0_WIDTH 32 + #define GP_PUDCLK0_RESET 0000000000 + #define GP_PUDCLK0_PUDCLKn0_BITS 31:0 + #define GP_PUDCLK0_PUDCLKn0_SET 0xffffffff + #define GP_PUDCLK0_PUDCLKn0_CLR 0x00000000 + #define GP_PUDCLK0_PUDCLKn0_MSB 31 + #define GP_PUDCLK0_PUDCLKn0_LSB 0 +#define GP_PUDCLK1 HW_REGISTER_RW( 0x7e20009c ) + #define GP_PUDCLK1_MASK 0xffffffff + #define GP_PUDCLK1_WIDTH 32 + #define GP_PUDCLK1_RESET 0000000000 + #define GP_PUDCLK1_PUDCLKn32_BITS 31:0 + #define GP_PUDCLK1_PUDCLKn32_SET 0xffffffff + #define GP_PUDCLK1_PUDCLKn32_CLR 0x00000000 + #define GP_PUDCLK1_PUDCLKn32_MSB 31 + #define GP_PUDCLK1_PUDCLKn32_LSB 0 +#define GP_PUDCLK2 HW_REGISTER_RW( 0x7e2000a0 ) + #define GP_PUDCLK2_MASK 0x0000003f + #define GP_PUDCLK2_WIDTH 6 + #define GP_PUDCLK2_RESET 0000000000 + #define GP_PUDCLK2_PUDCLKn64_BITS 5:0 + #define GP_PUDCLK2_PUDCLKn64_SET 0x0000003f + #define GP_PUDCLK2_PUDCLKn64_CLR 0xffffffc0 + #define GP_PUDCLK2_PUDCLKn64_MSB 5 + #define GP_PUDCLK2_PUDCLKn64_LSB 0 +#define GP_SEN0 HW_REGISTER_RW( 0x7e2000a4 ) + #define GP_SEN0_MASK 0xffffffff + #define GP_SEN0_WIDTH 32 + #define GP_SEN0_RESET 0xffffffff + #define GP_SEN0_SEN_BITS 31:0 + #define GP_SEN0_SEN_SET 0xffffffff + #define GP_SEN0_SEN_CLR 0x00000000 + #define GP_SEN0_SEN_MSB 31 + #define GP_SEN0_SEN_LSB 0 +#define GP_SEN1 HW_REGISTER_RW( 0x7e2000a8 ) + #define GP_SEN1_MASK 0x003fffff + #define GP_SEN1_WIDTH 22 + #define GP_SEN1_RESET 0x003fffff + #define GP_SEN1_SEN_BITS 21:0 + #define GP_SEN1_SEN_SET 0x003fffff + #define GP_SEN1_SEN_CLR 0xffc00000 + #define GP_SEN1_SEN_MSB 21 + #define GP_SEN1_SEN_LSB 0 +#define GP_GPTEST HW_REGISTER_RW( 0x7e2000b0 ) + #define GP_GPTEST_MASK 0x0000000f + #define GP_GPTEST_WIDTH 4 + #define GP_GPTEST_RESET 0000000000 + #define GP_GPTEST_SMPS_BITS 0:0 + #define GP_GPTEST_SMPS_SET 0x00000001 + #define GP_GPTEST_SMPS_CLR 0xfffffffe + #define GP_GPTEST_SMPS_MSB 0 + #define GP_GPTEST_SMPS_LSB 0 + #define GP_GPTEST_SPARE_BITS 3:1 + #define GP_GPTEST_SPARE_SET 0x0000000e + #define GP_GPTEST_SPARE_CLR 0xfffffff1 + #define GP_GPTEST_SPARE_MSB 3 + #define GP_GPTEST_SPARE_LSB 1 +#define GP_AJBCONF HW_REGISTER_RW( 0x7e2000c0 ) + #define GP_AJBCONF_MASK 0x80ffffff + #define GP_AJBCONF_WIDTH 32 + #define GP_AJBCONF_RESET 0000000000 +#define GP_AJBTMS HW_REGISTER_RW( 0x7e2000c4 ) + #define GP_AJBTMS_MASK 0xffffffff + #define GP_AJBTMS_WIDTH 32 + #define GP_AJBTMS_RESET 0000000000 +#define GP_AJBTDI HW_REGISTER_RW( 0x7e2000c8 ) + #define GP_AJBTDI_MASK 0xffffffff + #define GP_AJBTDI_WIDTH 32 + #define GP_AJBTDI_RESET 0000000000 +#define GP_AJBTDO HW_REGISTER_RW( 0x7e2000cc ) + #define GP_AJBTDO_MASK 0xffffffff + #define GP_AJBTDO_WIDTH 32 + #define GP_AJBTDO_RESET 0000000000 diff --git a/bcm2708_chip/h264.h b/bcm2708_chip/h264.h new file mode 100755 index 0000000..223805c --- /dev/null +++ b/bcm2708_chip/h264.h @@ -0,0 +1,6 @@ +// This file was generated by the create_regs script +#define H264_BASE 0x7f000000 +#define H264_APB_ID 0x68323634 +#define H264_RC HW_REGISTER_RW( 0x7f000000 ) + #define H264_RC_MASK 0xffffffff + #define H264_RC_WIDTH 32 diff --git a/bcm2708_chip/hardware.h b/bcm2708_chip/hardware.h new file mode 100755 index 0000000..093a71b --- /dev/null +++ b/bcm2708_chip/hardware.h @@ -0,0 +1,142 @@ + +// macro definitions plus aliases to maintain some old reg names +// Commented out to reveal fake defines +//#include "register_map_macros.h" + +// Necessary macros to make C code understand registers +#if defined(_ATHENA_) + #define HW_REGISTER_RW(addr) ((addr)) +#else + #define HW_REGISTER_RW(addr) (*(volatile unsigned long *)(addr)) +#endif + #define HW_REGISTER_RO(addr) (*(const volatile unsigned long *)(addr)) + #define HW_POINTER_TO_ADDRESS(pointer) ((uint32_t)(void *)&(pointer)) + +//interrupt definitions + #define INTERRUPT_HW_NUM (64) + #define INTERRUPT_HW_OFFSET (64) + #define INTERRUPT_SW_OFFSET (32) + #define INTERRUPT_SW_NUM (32) + #define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 ) + #define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 ) + #define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 ) + #define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 ) + #define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 ) + #define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 ) + #define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 ) + #define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 ) + #define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 ) + #define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 ) + #define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 ) + #define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 ) + #define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 ) + #define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 ) + #define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 ) + #define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 ) + #define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 ) + #define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 ) + #define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 ) + #define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 ) + #define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 ) + #define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 ) + #define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 ) + #define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 ) + #define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 ) + #define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 ) + #define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 ) + #define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 ) + #define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 ) + #define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 ) + #define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 ) + #define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 ) + #define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 ) + #define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 ) + #define INTERRUPT_CCP2TX (INTERRUPT_HW_OFFSET + 34 ) + #define INTERRUPT_SDC (INTERRUPT_HW_OFFSET + 35 ) + #define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 ) + #define INTERRUPT_SPARE2 (INTERRUPT_HW_OFFSET + 37 ) + #define INTERRUPT_CAM0 (INTERRUPT_HW_OFFSET + 38 ) + #define INTERRUPT_CAM1 (INTERRUPT_HW_OFFSET + 39 ) + #define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 ) + #define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 ) + #define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 ) + #define INTERRUPT_SPARE3 (INTERRUPT_HW_OFFSET + 43 ) + #define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 44 ) + #define INTERRUPT_PWA0 (INTERRUPT_HW_OFFSET + 45 ) + #define INTERRUPT_PWA1 (INTERRUPT_HW_OFFSET + 46 ) + #define INTERRUPT_CPR (INTERRUPT_HW_OFFSET + 47 ) + #define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 48 ) + #define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 49 ) + #define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 50 ) + #define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 51 ) + #define INTERRUPT_GPIO3 (INTERRUPT_HW_OFFSET + 52 ) + #define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 ) + #define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 ) + #define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 ) + #define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 ) + #define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 ) + #define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 58 ) + #define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 ) + #define INTERRUPT_CPG (INTERRUPT_HW_OFFSET + 60 ) + #define INTERRUPT_RNG (INTERRUPT_HW_OFFSET + 61 ) + #define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 ) + #define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 ) + #define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 ) + #define ISRC0_0 IC0_SRC0 + #define ISRC0_1 IC1_SRC0 + #define ISRC1_0 IC0_SRC1 + #define ISRC1_1 IC1_SRC1 + + + +/*---------------------------------------------------------------------------*/ + +// auto generated regestermap +#include "register_map.h" + + /*---------------------------------------------------------------------------*/ + /* DMA Source Definitions */ + + // port 0 is wired as permanently on inside the DMA + #define CAM_DMA (0<>28)&0xf)==0) + #define IS_ALIAS_STREAMING(x) ((((unsigned)(x)>>28)&0xf)==1) + #define IS_ALIAS_COHERENT(x) ((((unsigned)(x)>>28)&0xf)==2) + #define IS_ALIAS_DIRECT(x) ((((unsigned)(x)>>28)&0xf)==3) + #define IS_ALIAS_NONALLOCATING(x) ((((unsigned)(x)>>28)&0xe)==2) + + //default interrupt vector table base address + #define INTERRUPT_VECTOR_BASE 0 + + //common interrupts + #define INTERRUPT_EXCEPTION_OFFSET 0 + #define INTERRUPT_EXCEPTION_NUM 32 + + #define INTERRUPT_SOFTINT_OFFSET 32 + #define INTERRUPT_SOFTINT_NUM 32 + + #define INTERRUPT_HARDINT_OFFSET 64 + #define INTERRUPT_HARDINT_NUM 64 + + #define MAX_DMA_NUM 8 + #define MAX_DMA_SUB 1 + #define MAX_GPIO_NUM 2 + #define MAX_TIMER_NUM 4 + #define MAX_EXCEPTION_NUM 8 + + #define BOOTROM_BASE_ADDRESS 0x10000000 + + //VRF defines + #define VRF_SIZE (4096+64+64) + + // no of GPIO pins + #define VIDEOCORE_NUM_GPIO_PINS 70 + + + //interrupt definitions + #define INTERRUPT_HW_NUM (64) + #define INTERRUPT_HW_OFFSET (64) + #define INTERRUPT_SW_OFFSET (32) + #define INTERRUPT_SW_NUM (32) + + #define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 ) + #define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 ) + #define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 ) + #define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 ) + #define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 ) + #define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 ) + #define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 ) + #define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 ) + #define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 ) + #define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 ) + #define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 ) + #define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 ) + #define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 ) + #define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 ) + #define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 ) + #define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 ) + #define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 ) + #define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 ) + #define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 ) + #define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 ) + #define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 ) + #define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 ) + #define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 ) + #define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 ) + #define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 ) + #define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 ) + #define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 ) + #define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 ) + #define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 ) + #define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 ) + #define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 ) + #define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 ) + #define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 ) + #define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 ) + #define INTERRUPT_CRYPTO (INTERRUPT_HW_OFFSET + 34 ) + #define INTERRUPT_SPARE1 (INTERRUPT_HW_OFFSET + 35 ) + #define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 ) +// #define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 37 ) + #define INTERRUPT_CCP2 (INTERRUPT_HW_OFFSET + 38 ) + #define INTERRUPT_CSI2 (INTERRUPT_HW_OFFSET + 39 ) + #define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 ) + #define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 ) +// #define INTERRUPT_HDMI2 (INTERRUPT_HW_OFFSET + 42 ) + #define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 ) + #define INTERRUPT_PARALLELCAMERA (INTERRUPT_HW_OFFSET + 43 ) + #define INTERRUPT_PIXELVALVE0 (INTERRUPT_HW_OFFSET + 44 ) + #define INTERRUPT_PLL (INTERRUPT_HW_OFFSET + 45 ) + #define INTERRUPT_CDP (INTERRUPT_HW_OFFSET + 46 ) + #define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 47 ) + #define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 48 ) + #define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 49 ) + #define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 50 ) + #define INTERRUPT_GPION (INTERRUPT_HW_OFFSET + 51 ) + #define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 52 ) + #define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 ) + #define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 ) + #define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 ) + #define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 ) + #define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 ) + #define INTERRUPT_ADC (INTERRUPT_HW_OFFSET + 58 ) + #define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 ) + #define INTERRUPT_SPARE2 (INTERRUPT_HW_OFFSET + 60 ) + #define INTERRUPT_SPARE3 (INTERRUPT_HW_OFFSET + 61 ) + #define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 ) + #define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 ) + #define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 ) + + // aliases + #define INTERRUPT_HOSTINTERFACE INTERRUPT_HOSTPORT + #define INTERRUPT_SDCARDHOST INTERRUPT_SDIO + + // temporary dummy register definitions to avoid compile errors + #define DUMMYREG HW_REGISTER_RW( 0x7C ) //software exception vector 15 + + + + + /*---------------------------------------------------------------------------*/ + /*---------------------------------------------------------------------------*/ + // ALIAS TABLE + // this is currently here to avoid problems with the new reg definition names + // not matching the old. This needs to be sorted and removed + // TODO FIXME + /*---------------------------------------------------------------------------*/ + /*---------------------------------------------------------------------------*/ + + /* Cache controller */ + #define IC0CS L1_IC0_CONTROL + #define IC0START L1_I_FLUSH_S + #define IC0END L1_I_FLUSH_E + #define DC0CS L1_D_CONTROL + #define DC0START L1_D_FLUSH_S + #define DC0END L1_D_FLUSH_E + #define L2CS L2_CONT_OFF + #define L2START L2_FLUSH_STA + #define L2END L2_FLUSH_END + + + + + /*---------------------------------------------------------------------------*/ + /* Priority arbiter */ + + #define AM_VP_L2_PRI HW_REGISTER_RW( 0x1800d000 ) + #define AM_VP_UC_PRI HW_REGISTER_RW( 0x1800d004 ) + #define AM_VP_PERPRI HW_REGISTER_RW( 0x1800d008 ) + #define AM_HO_MEMPRI HW_REGISTER_RW( 0x1800d00c ) + #define AM_HO_PERPRI HW_REGISTER_RW( 0x1800d010 ) + #define AM_DB_MEMPRI HW_REGISTER_RW( 0x1800d014 ) + #define AM_DB_PERPRI HW_REGISTER_RW( 0x1800d018 ) + #define AM_HVSM_PRI HW_REGISTER_RW( 0x1800d01c ) + + /*---------------------------------------------------------------------------*/ + /* Nexus Controller */ + + #define NOWNT HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x4) + #define NIOREQ HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x0) + + /*---------------------------------------------------------------------------*/ + /* Reset Controller */ + + #define RSTCS HW_REGISTER_RW(RS_BASE + 0x0) + #define RSTWD HW_REGISTER_RW(RS_BASE + 0x4) + #define RSTID HW_REGISTER_RW(RS_BASE + 0x8) + #define RSTFD HW_REGISTER_RW(RS_BASE + 0xc) + #define RSC0ADDR HW_REGISTER_RW(RS_BASE + 0x10) + + + + + + //the start location of the scalers context memory + #define SCALER_CONTEXT_MEM_SIZE ( 1024 * 16 ) //16k + + //the size of the line buffer memory + #define SCALER_LINE_BUFFER_MEM_SIZE ( 1024 * 64 ) //64k + + //The maximum size of the COB buffer (the output fifo) + #define SCALER_COB_FIFO_SIZE (0x4000) //8Kbytes + + /*---------------------------------------------------------------------------*/ + /* Transposer */ + + #define TRANSPOSER_DST_PTR TXP_DST_PTR + #define TRANSPOSER_DST_PITCH TXP_DST_PITCH + #define TRANSPOSER_DIMENSIONS TXP_DIM + #define TRANSPOSER_CONTROL TXP_CTRL + #define TRANSPOSER_PROGRESS TXP_PROGRESS + + /*---------------------------------------------------------------------------*/ + /* Pixel Valve */ + + #define PIXELVALVE_C_0 PIXELVALVE0_C + #define PIXELVALVE_VC_0 PIXELVALVE0_VC + #define PIXELVALVE_HSYNC_0 PIXELVALVE0_HSYNC + #define PIXELVALVE_VSYNC_0 PIXELVALVE0_VSYNC + #define PIXELVALVE_VSIZE_0 PIXELVALVE0_VSIZE + #define PIXELVALVE_INTEN_0 PIXELVALVE0_INTEN + #define PIXELVALVE_INTSTAT_0 PIXELVALVE0_INTSTAT + #define PIXELVALVE_STAT_0 PIXELVALVE0_STAT + + #define PIXELVALVE_C_1 PIXELVALVE1_C + #define PIXELVALVE_VC_1 PIXELVALVE1_VC + #define PIXELVALVE_HSYNC_1 PIXELVALVE1_HSYNC + #define PIXELVALVE_VSYNC_1 PIXELVALVE1_VSYNC + #define PIXELVALVE_VSIZE_1 PIXELVALVE1_VSIZE + #define PIXELVALVE_INTEN_1 PIXELVALVE1_INTEN + #define PIXELVALVE_INTSTAT_1 PIXELVALVE1_INTSTAT + #define PIXELVALVE_STAT_1 PIXELVALVE1_STAT + + #define PIXELVALVE_C_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x00 ) + #define PIXELVALVE_VC_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x04 ) + #define PIXELVALVE_HSYNC_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x08 ) + #define PIXELVALVE_VSYNC_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x0C ) + #define PIXELVALVE_VSIZE_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x10 ) + #define PIXELVALVE_INTEN_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x14 ) + #define PIXELVALVE_INTSTAT_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x18 ) + #define PIXELVALVE_STAT_x( x ) HW_REGISTER_RW( ((0 == x) ? PIXELVALVE0_BASE : PIXELVALVE1_BASE) + 0x1C ) + + /*---------------------------------------------------------------------------*/ + /* DSI */ + + #define DSI_CTRL HW_REGISTER_RW( DSI_BASE + 0x00 ) + #define DSI_CMD_PKTC HW_REGISTER_RW( DSI_BASE + 0x04 ) + #define DSI_CMD_PKTH HW_REGISTER_RW( DSI_BASE + 0x08 ) + #define DSI_RX1_PKTH HW_REGISTER_RW( DSI_BASE + 0x0C ) + #define DSI_RX2_PKTH HW_REGISTER_RW( DSI_BASE + 0x10 ) + #define DSI_CMD_DATA_FIFO HW_REGISTER_RW( DSI_BASE + 0x14 ) + #define DSI_DISP0_CTRL HW_REGISTER_RW( DSI_BASE + 0x18 ) + #define DSI_DISP1_CTRL HW_REGISTER_RW( DSI_BASE + 0x1C ) + #define DSI_PIX_FIFO HW_REGISTER_RW( DSI_BASE + 0x20 ) + #define DSI_INT_STATUS HW_REGISTER_RW( DSI_BASE + 0x24 ) + #define DSI_INT_ENABLE HW_REGISTER_RW( DSI_BASE + 0x28 ) + #define DSI_STAT HW_REGISTER_RW( DSI_BASE + 0x2C ) + #define DSI_HSTX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x30 ) + #define DSI_LPRX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x34 ) + #define DSI_TA_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x38 ) + #define DSI_PR_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x3C ) + #define DSI_PHY_CONTROL HW_REGISTER_RW( DSI_BASE + 0x40 ) + // HSCLKZERO, HSCLKPRE, HSCLKPREP + #define DSI_HS_CLT0 HW_REGISTER_RW( DSI_BASE + 0x44 ) + // HSCLKTRAIL, HSCLKPOST + #define DSI_HS_CLT1 HW_REGISTER_RW( DSI_BASE + 0x48 ) + // HSWAKEUP + #define DSI_HS_CLT2 HW_REGISTER_RW( DSI_BASE + 0x4C ) + // HS EXIT, ZERO, PRE + #define DSI_HS_DLT3 HW_REGISTER_RW( DSI_BASE + 0x50 ) + // HS TRAIL LPX + #define DSI_HS_DLT4 HW_REGISTER_RW( DSI_BASE + 0x54 ) + // HS INIT + #define DSI_HS_DLT5 HW_REGISTER_RW( DSI_BASE + 0x58 ) + // lp GET SURE GO LPX + #define DSI_LP_DLT6 HW_REGISTER_RW( DSI_BASE + 0x5C ) + // LP WAKEUP + #define DSI_LP_DLT7 HW_REGISTER_RW( DSI_BASE + 0x60 ) + #define DSI_AFEC0 HW_REGISTER_RW( DSI_BASE + 0x64 ) + #define DSI_AFEC1 HW_REGISTER_RW( DSI_BASE + 0x68 ) + #define DSI_TST_SEL HW_REGISTER_RW( DSI_BASE + 0x6C ) + #define DSI_TST_MON HW_REGISTER_RW( DSI_BASE + 0x70 ) + + /*---------------------------------------------------------------------------*/ + /* CDP */ + + #define CDPC HW_REGISTER_RW( CDP_BASE + 0x00 ) + #define CDP_PHYC HW_REGISTER_RW( CDP_BASE + 0x04 ) + #define CDP_PHYTSTDAT HW_REGISTER_RW( CDP_BASE + 0x08 ) + #define CDP_DEBUG0 HW_REGISTER_RW( CDP_BASE + 0x0C ) + #define CDP_DEBUG1 HW_REGISTER_RW( CDP_BASE + 0x10 ) + + /*---------------------------------------------------------------------------*/ + /* BootROM Peripheral */ + + #define BOOTROM_ROM_START ( BOOTROM_BASE_ADDRESS + 0x0 ) //Start of the ROM + #define BOOTROM_ROM_LENGTH ( 1024 * 32 ) // Length of the Boot ROM + + #define BOOTROM_RAM_START ( BOOTROM_BASE_ADDRESS + 0x8000 ) //Start of the RAM + #define BOOTROM_RAM_LENGTH ( 1024 * 2 ) // Length of the Boot RAM + + #define BOOTROM_BRCTL HW_REGISTER_RW( BOOTROM_BASE_ADDRESS + 0xC000 ) + + /*---------------------------------------------------------------------------*/ + /* Multicore sync block */ + + //number of hardware semaphores + #define MULTICORE_SYNC_NUM_SEMAPHORES (32) + + //registers... + #define MULTICORE_SYNC_SEMA_MASK( num ) HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + ((num) * 0x4) ) + + #define MULTICORE_SYNC_SEMA_MASK_0 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x00 ) + #define MULTICORE_SYNC_SEMA_MASK_1 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x04 ) + #define MULTICORE_SYNC_SEMA_MASK_2 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x08 ) + #define MULTICORE_SYNC_SEMA_MASK_3 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x0C ) + #define MULTICORE_SYNC_SEMA_MASK_4 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x10 ) + #define MULTICORE_SYNC_SEMA_MASK_5 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x14 ) + #define MULTICORE_SYNC_SEMA_MASK_6 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x18 ) + #define MULTICORE_SYNC_SEMA_MASK_7 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x1C ) + #define MULTICORE_SYNC_SEMA_MASK_8 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x20 ) + #define MULTICORE_SYNC_SEMA_MASK_9 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x24 ) + #define MULTICORE_SYNC_SEMA_MASK_10 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x28 ) + #define MULTICORE_SYNC_SEMA_MASK_11 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x2C ) + #define MULTICORE_SYNC_SEMA_MASK_12 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x30 ) + #define MULTICORE_SYNC_SEMA_MASK_13 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x34 ) + #define MULTICORE_SYNC_SEMA_MASK_14 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x38 ) + #define MULTICORE_SYNC_SEMA_MASK_15 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x3C ) + #define MULTICORE_SYNC_SEMA_MASK_16 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x40 ) + #define MULTICORE_SYNC_SEMA_MASK_17 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x44 ) + #define MULTICORE_SYNC_SEMA_MASK_18 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x48 ) + #define MULTICORE_SYNC_SEMA_MASK_19 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x4C ) + #define MULTICORE_SYNC_SEMA_MASK_20 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x50 ) + #define MULTICORE_SYNC_SEMA_MASK_21 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x54 ) + #define MULTICORE_SYNC_SEMA_MASK_22 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x58 ) + #define MULTICORE_SYNC_SEMA_MASK_23 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x5C ) + #define MULTICORE_SYNC_SEMA_MASK_24 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x60 ) + #define MULTICORE_SYNC_SEMA_MASK_25 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x64 ) + #define MULTICORE_SYNC_SEMA_MASK_26 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x68 ) + #define MULTICORE_SYNC_SEMA_MASK_27 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x6C ) + #define MULTICORE_SYNC_SEMA_MASK_28 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x70 ) + #define MULTICORE_SYNC_SEMA_MASK_29 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x74 ) + #define MULTICORE_SYNC_SEMA_MASK_30 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x78 ) + #define MULTICORE_SYNC_SEMA_MASK_31 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x7C ) + + #define MULTICORE_SYNC_SEMA_STATUS HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x80 ) + #define MULTICORE_SYNC_IREQ_0 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x84 ) + #define MULTICORE_SYNC_IREQ_1 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x88 ) + + #define MULTICORE_SYNC_ICSET_0 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x90 ) + #define MULTICORE_SYNC_ICSET_1 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x94 ) + #define MULTICORE_SYNC_ICCLR_0 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x98 ) + #define MULTICORE_SYNC_ICCLR_1 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0x9C ) + + #define MULTICORE_SYNC_MBOX_0 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xA0 ) + #define MULTICORE_SYNC_MBOX_1 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xA4 ) + #define MULTICORE_SYNC_MBOX_2 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xA8 ) + #define MULTICORE_SYNC_MBOX_3 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xAC ) + #define MULTICORE_SYNC_MBOX_4 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xB0 ) + #define MULTICORE_SYNC_MBOX_5 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xB4 ) + #define MULTICORE_SYNC_MBOX_6 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xB8 ) + #define MULTICORE_SYNC_MBOX_7 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xBC ) + + #define MULTICORE_SYNC_MBOX_MASK( num ) HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + ((num) * 0x4) ) + + //The special intercore system semaphore, used for fine grained counting + #define MULTICORE_SYNC_VPU_SEMA_0 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xC0 ) + #define MULTICORE_SYNC_VPU_SEMA_1 HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xC4 ) + + #define MULTICORE_SYNC_VPU_SEMA_x( x ) ( ((x) == 0) ? MULTICORE_SYNC_VPU_SEMA_0 : MULTICORE_SYNC_VPU_SEMA_1 ) + + #define MULTICORE_SYNC_VPU_SEMA_STATUS HW_REGISTER_RW( MULTICORE_SYNC_BASE_ADDRESS + 0xC8 ) + + //read a semaphore block until its '0' + //when the semaphore is free, allow it to increment a shared counter + + + /*---------------------------------------------------------------------------*/ + /* CCP2 Peripheral */ + + #define CCP2RC HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x00 ) + #define CCP2RS HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x04 ) + #define CCP2RDR1 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x80 ) + #define CCP2RDR2 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x84 ) + #define CCP2RDR3 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x88 ) + + #define CCP2RC0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x100 ) + #define CCP2RPC0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x104 ) + #define CCP2RS0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x108 ) + #define CCP2RSA0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x10C ) + #define CCP2REA0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x110 ) + #define CCP2RWP0 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x114 ) + #define CCP2RBC0 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x118 ) + #define CCP2RLS0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x11C ) + #define CCP2RDSA0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x120 ) + #define CCP2RDEA0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x124 ) + #define CCP2RDS0 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x128 ) + + #define CCP2RC1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x200 ) + #define CCP2RPC1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x204 ) + #define CCP2RS1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x208 ) + #define CCP2RSA1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x20C ) + #define CCP2REA1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x210 ) + #define CCP2RWP1 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x214 ) + #define CCP2RBC1 HW_REGISTER_RO( CCP2_BASE_ADDRESS + 0x218 ) + #define CCP2RLS1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x21C ) + #define CCP2RDSA1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x220 ) + #define CCP2RDEA1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x224 ) + #define CCP2RDS1 HW_REGISTER_RW( CCP2_BASE_ADDRESS + 0x228 ) + + + /*---------------------------------------------------------------------------*/ + /* CSI2 Peripheral */ + + #define CSI2_RC HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x00 ) + #define CSI2_RS HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x04 ) + #define CSI2_RDLS HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x08 ) + #define CSI2_RGSP HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x0C ) + #define CSI2_TREN HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x10 ) + #define CSI2_THSSTO HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x14 ) + #define CSI2_THSSET HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x18 ) + #define CSI2_THSCKTO HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x1C ) + + #define CSI2LPRX0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x20 ) + #define CSI2LPRX1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x24 ) + #define CSI2LPRX2 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x28 ) + #define CSI2LPRX3 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x2C ) + #define CSI2LPRXC HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x30 ) + #define CSI2TRIG HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x40 ) + + #define CSI2DBGDPHY HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x80 ) + #define CSI2DBGMISC HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x84 ) + + #define CSI2_SRST HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x90 ) + #define CSI2RDR3 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x94 ) + + #define CSI2_RC0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x100 ) + #define CSI2_RPC0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x104 ) + #define CSI2_RS0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x108 ) + #define CSI2_RSA0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x10C ) + #define CSI2_REA0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x110 ) + #define CSI2_RWP0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x114 ) + #define CSI2_RBC0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x118 ) + #define CSI2_RLS0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x11C ) + #define CSI2_RDSA0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x120 ) + #define CSI2_RDEA0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x124 ) + #define CSI2_RDS0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x128 ) + #define CSI2_DTOV0 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x12C ) + + #define CSI2_RC1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x200 ) + #define CSI2_RPC1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x204 ) + #define CSI2_RS1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x208 ) + #define CSI2_RSA1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x20C ) + #define CSI2_REA1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x210 ) + #define CSI2_RWP1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x214 ) + #define CSI2_RBC1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x218 ) + #define CSI2_RLS1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x21C ) + #define CSI2_RDSA1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x220 ) + #define CSI2_RDEA1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x224 ) + #define CSI2_RDS1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x228 ) + #define CSI2_DTOV1 HW_REGISTER_RW( CSI2_BASE_ADDRESS + 0x22C ) + + #define CSI2_RC_x( x ) ( ((x) == 0) ? CSI2_RC0 : CSI2_RC1 ) + #define CSI2_RPC_x( x ) ( ((x) == 0) ? CSI2_RPC0 : CSI2_RPC1 ) + #define CSI2_RS_x( x ) ( ((x) == 0) ? CSI2_RS0 : CSI2_RS1 ) + #define CSI2_RSA_x( x ) ( ((x) == 0) ? CSI2_RSA0 : CSI2_RSA1 ) + #define CSI2_REA_x( x ) ( ((x) == 0) ? CSI2_REA0 : CSI2_REA1 ) + #define CSI2_RWP_x( x ) ( ((x) == 0) ? CSI2_RWP0 : CSI2_RWP1 ) + #define CSI2_RBC_x( x ) ( ((x) == 0) ? CSI2_RBC0 : CSI2_RBC1 ) + #define CSI2_RLS_x( x ) ( ((x) == 0) ? CSI2_RLS0 : CSI2_RLS1 ) + #define CSI2_RDSA_x( x ) ( ((x) == 0) ? CSI2_RDSA0 : CSI2_RDSA1 ) + #define CSI2_RDEA_x( x ) ( ((x) == 0) ? CSI2_RDEA0 : CSI2_RDEA1 ) + #define CSI2_RDS_x( x ) ( ((x) == 0) ? CSI2_RDS0 : CSI2_RDS1 ) + #define CSI2_DTOV_x( x ) ( ((x) == 0) ? CSI2_DTOV0 : CSI2_DTOV1 ) + + /*---------------------------------------------------------------------------*/ + /* DPI Peripheral */ + + #define DPI_DPIC HW_REGISTER_RW( DPI_BASE_ADDRESS + 0x00 ) + + /*---------------------------------------------------------------------------*/ + /* VEC Peripheral */ + #define WSE_RESET VEC_WSE_RESET + #define WSE_CONTROL VEC_WSE_CONTROL + #define WSE_WSS_DATA VEC_WSE_WSS_DATA + #define WSE_VPS_DATA_1 VEC_WSE_VPS_DATA_1 + #define WSE_VPS_CONTROL VEC_WSE_VPS_CONTROL + #define CGMSAE_RESET VEC_CGMSAE_RESET + #define CGMSAE_TOP_CONTROL VEC_CGMSAE_TOP_CONTROL + #define CGMSAE_BOT_CONTROL VEC_CGMSAE_BOT_CONTROL + #define CGMSAE_TOP_FORMAT VEC_CGMSAE_TOP_FORMAT + #define CGMSAE_BOT_FORMAT VEC_CGMSAE_BOT_FORMAT + #define CGMSAE_TOP_DATA VEC_CGMSAE_TOP_DATA + #define CGMSAE_BOT_DATA VEC_CGMSAE_BOT_DATA + #define CGMSAE_REVID VEC_CGMSAE_REVID + #define VIDEO_ENC_RevID VEC_ENC_RevID + #define VIDEO_ENC_PrimaryControl VEC_ENC_PrimaryControl + + + /*---------------------------------------------------------------------------*/ + /* HDMI Peripheral */ + + #define HDMI_RBUS_REGS + + #define HDMI_CORE_REV HW_REGISTER_RW( HDMI_BASE_ADDRESS + 0 ) + #define HDMI_SW_RESET_CNTRL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 4 ) + #define HDMI_HOTPLUG_INT HW_REGISTER_RW( HDMI_BASE_ADDRESS + 8 ) + #define HDMI_HOTPLUG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 12 ) + #define HDMI_BKSV0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 16 ) + #define HDMI_BKSV1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 20 ) + #define HDMI_AN0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 24 ) + #define HDMI_AN1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 28 ) + #define HDMI_AN_INFLUENCE_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 32 ) + #define HDMI_AN_INFLUENCE_2 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 36 ) + #define HDMI_TST_AN0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 40 ) + #define HDMI_TST_AN1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 44 ) + #define HDMI_KSV_FIFO_0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 48 ) + #define HDMI_KSV_FIFO_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 52 ) + #define HDMI_V HW_REGISTER_RW( HDMI_BASE_ADDRESS + 56 ) + #define HDMI_HDCP_KEY_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 60 ) + #define HDMI_HDCP_KEY_2 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 64 ) + #define HDMI_HDCP_CTL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 68 ) + #define HDMI_CP_STATUS HW_REGISTER_RW( HDMI_BASE_ADDRESS + 72 ) + #define HDMI_CP_INTEGRITY HW_REGISTER_RW( HDMI_BASE_ADDRESS + 76 ) + #define HDMI_CP_INTEGRITY_CFG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 80 ) + #define HDMI_CP_CONFIG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 84 ) + #define HDMI_CP_TST HW_REGISTER_RW( HDMI_BASE_ADDRESS + 88 ) + #define HDMI_FIFO_CTL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 92 ) + #define HDMI_READ_POINTERS HW_REGISTER_RW( HDMI_BASE_ADDRESS + 96 ) + #define HDMI_ENCODER_CTL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 112 ) + #define HDMI_PERT_CONFIG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 116 ) + #define HDMI_PERT_LFSR_PRELOAD HW_REGISTER_RW( HDMI_BASE_ADDRESS + 120 ) + #define HDMI_PERT_LFSR_FEEDBACK_MASK HW_REGISTER_RW( HDMI_BASE_ADDRESS + 124 ) + #define HDMI_PERT_INSERT_ERR HW_REGISTER_RW( HDMI_BASE_ADDRESS + 128 ) + #define HDMI_PERT_INSERT_ERR_SEPARATION HW_REGISTER_RW( HDMI_BASE_ADDRESS + 132 ) + #define HDMI_PERT_TEST_LENGTH HW_REGISTER_RW( HDMI_BASE_ADDRESS + 136 ) + #define HDMI_PERT_DATA HW_REGISTER_RW( HDMI_BASE_ADDRESS + 140 ) + #define HDMI_MAI_CHANNEL_MAP HW_REGISTER_RW( HDMI_BASE_ADDRESS + 144 ) + #define HDMI_MAI_CONFIG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 148 ) + #define HDMI_MAI_FORMAT HW_REGISTER_RW( HDMI_BASE_ADDRESS + 152 ) + #define HDMI_AUDIO_PACKET_CONFIG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 156 ) + #define HDMI_RAM_PACKET_CONFIG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 160 ) + #define HDMI_RAM_PACKET_STATUS HW_REGISTER_RW( HDMI_BASE_ADDRESS + 164 ) + #define HDMI_CRP_CFG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 168 ) + #define HDMI_CTS_0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 172 ) + #define HDMI_CTS_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 176 ) + #define HDMI_CTS_PERIOD_0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 180 ) + #define HDMI_CTS_PERIOD_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 184 ) + #define HDMI_BCH_CONFIGURATION HW_REGISTER_RW( HDMI_BASE_ADDRESS + 188 ) + #define HDMI_SCHEDULER_CONTROL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 192 ) + #define HDMI_HORZA HW_REGISTER_RW( HDMI_BASE_ADDRESS + 196 ) + #define HDMI_HORZB HW_REGISTER_RW( HDMI_BASE_ADDRESS + 200 ) + #define HDMI_VERTA0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 204 ) + #define HDMI_VERTB0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 208 ) + #define HDMI_VERTA1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 212 ) + #define HDMI_VERTB1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 216 ) + #define HDMI_TEST HW_REGISTER_RW( HDMI_BASE_ADDRESS + 220 ) + #define HDMI_MBIST_TM HW_REGISTER_RW( HDMI_BASE_ADDRESS + 224 ) + #define HDMI_MISC_CONTROL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 228 ) + #define HDMI_CEC_CNTRL_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 232 ) + #define HDMI_CEC_CNTRL_2 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 236 ) + #define HDMI_CEC_CNTRL_3 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 240 ) + #define HDMI_CEC_CNTRL_4 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 244 ) + #define HDMI_CEC_CNTRL_5 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 248 ) + #define HDMI_CEC_TX_DATA_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 252 ) + #define HDMI_CEC_TX_DATA_2 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 256 ) + #define HDMI_CEC_TX_DATA_3 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 260 ) + #define HDMI_CEC_TX_DATA_4 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 264 ) + #define HDMI_CEC_RX_DATA_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 268 ) + #define HDMI_CEC_RX_DATA_2 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 272 ) + #define HDMI_CEC_RX_DATA_3 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 276 ) + #define HDMI_CEC_RX_DATA_4 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 280 ) + #define HDMI_PACKET_FIFO_CTL HW_REGISTER_RW( HDMI_BASE_ADDRESS + 284 ) + #define HDMI_PACKET_FIFO_CFG HW_REGISTER_RW( HDMI_BASE_ADDRESS + 288 ) + #define HDMI_PACKET_FIFO_STATUS HW_REGISTER_RW( HDMI_BASE_ADDRESS + 292 ) + #define HDMI_DVO_TIMING_ADJUST_A HW_REGISTER_RW( HDMI_BASE_ADDRESS + 296 ) + #define HDMI_DVO_TIMING_ADJUST_B HW_REGISTER_RW( HDMI_BASE_ADDRESS + 300 ) + #define HDMI_DVO_TIMING_ADJUST_C HW_REGISTER_RW( HDMI_BASE_ADDRESS + 304 ) + #define HDMI_DVO_TIMING_ADJUST_D HW_REGISTER_RW( HDMI_BASE_ADDRESS + 308 ) + #define HDMI_DETECTED_HORZA HW_REGISTER_RW( HDMI_BASE_ADDRESS + 312 ) + #define HDMI_DETECTED_HORZB HW_REGISTER_RW( HDMI_BASE_ADDRESS + 316 ) + #define HDMI_DETECTED_VERTA0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 320 ) + #define HDMI_DETECTED_VERTB0 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 324 ) + #define HDMI_DETECTED_VERTA1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 328 ) + #define HDMI_DETECTED_VERTB1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 332 ) + #define HDMI_HDMI_13_AUDIO_CFG_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 336 ) + #define HDMI_HDMI_13_AUDIO_STATUS_1 HW_REGISTER_RW( HDMI_BASE_ADDRESS + 340 ) + #define HDMI_HDMI_HBR_AUDIO_PACKET_HEADER HW_REGISTER_RW( HDMI_BASE_ADDRESS + 344 ) + + + #define HDMI_TX_PHY_BASE (HDMI_BASE_ADDRESS + 0x2c0) + + #define HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL HW_REGISTER_RW( HDMI_TX_PHY_BASE + 0 ) + #define HDMI_TX_PHY_HDMI_TX_PHY_CTL_0 HW_REGISTER_RW( HDMI_TX_PHY_BASE + 4 ) + #define HDMI_TX_PHY_HDMI_TX_PHY_CTL_1 HW_REGISTER_RW( HDMI_TX_PHY_BASE + 8 ) + #define HDMI_TX_PHY_HDMI_TX_PHY_CTL_2 HW_REGISTER_RW( HDMI_TX_PHY_BASE + 12 ) + #define HDMI_TX_PHY_HDMI_TX_PHY_PLL_CFG HW_REGISTER_RW( HDMI_TX_PHY_BASE + 16 ) + #define HDMI_TX_PHY_HDMI65_TX_PHY_TMDS_CFG HW_REGISTER_RW( HDMI_TX_PHY_BASE + 20 ) + #define HDMI_TX_PHY_HDMI_TX_PHY_STATUS HW_REGISTER_RW( HDMI_TX_PHY_BASE + 24 ) + #define HDMI_TX_PHY_SPREAD_SPECTRUM HW_REGISTER_RW( HDMI_TX_PHY_BASE + 28 ) + #define HDMI_TX_PHY_HDMI_TX_PHY_SPARE HW_REGISTER_RW( HDMI_TX_PHY_BASE + 32 ) + + #define HDMI_ASYNC_RM_BASE (HDMI_BASE_ADDRESS + 0x300) + + #define HDMI_ASYNC_RM_CONTROL HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 0 ) + #define HDMI_ASYNC_RM_RATE_RATIO HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 4 ) + #define HDMI_ASYNC_RM_SAMPLE_INC HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 8 ) + #define HDMI_ASYNC_RM_PHASE_INC HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 12 ) + #define HDMI_ASYNC_RM_INTEGRATOR HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 16 ) + #define HDMI_ASYNC_RM_OFFSET HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 20 ) + #define HDMI_ASYNC_RM_FORMAT HW_REGISTER_RW( HDMI_ASYNC_RM_BASE + 24 ) + + #define HDMI_INTR2_BASE (HDMI_BASE_ADDRESS + 0x340) + + #define HDMI_CPU_STATUS HW_REGISTER_RW( HDMI_INTR2_BASE + 0x00 ) + #define HDMI_CPU_SET HW_REGISTER_RW( HDMI_INTR2_BASE + 0x04 ) + #define HDMI_CPU_CLEAR HW_REGISTER_RW( HDMI_INTR2_BASE + 0x08 ) + #define HDMI_CPU_MASK_STATUS HW_REGISTER_RW( HDMI_INTR2_BASE + 0x0c ) + #define HDMI_CPU_MASK_SET HW_REGISTER_RW( HDMI_INTR2_BASE + 0x10 ) + #define HDMI_CPU_MASK_CLEAR HW_REGISTER_RW( HDMI_INTR2_BASE + 0x14 ) + #define HDMI_PCI_STATUS HW_REGISTER_RW( HDMI_INTR2_BASE + 0x18 ) + #define HDMI_PCI_SET HW_REGISTER_RW( HDMI_INTR2_BASE + 0x1c ) + #define HDMI_PCI_CLEAR HW_REGISTER_RW( HDMI_INTR2_BASE + 0x20 ) + #define HDMI_PCI_MASK_STATUS HW_REGISTER_RW( HDMI_INTR2_BASE + 0x24 ) + #define HDMI_PCI_MASK_SET HW_REGISTER_RW( HDMI_INTR2_BASE + 0x28 ) + #define HDMI_PCI_MASK_CLEAR HW_REGISTER_RW( HDMI_INTR2_BASE + 0x2c ) + + #define HDMI_RAM_BASE (HDMI_BASE_ADDRESS + 0x400) + + #define HDMI_RAM_GCP_0 HW_REGISTER_RW( HDMI_RAM_BASE + 0 ) + #define HDMI_RAM_GCP_1 HW_REGISTER_RW( HDMI_RAM_BASE + 4 ) + #define HDMI_RAM_GCP_2 HW_REGISTER_RW( HDMI_RAM_BASE + 8 ) + #define HDMI_RAM_GCP_3 HW_REGISTER_RW( HDMI_RAM_BASE + 12 ) + #define HDMI_RAM_GCP_4 HW_REGISTER_RW( HDMI_RAM_BASE + 16 ) + #define HDMI_RAM_GCP_5 HW_REGISTER_RW( HDMI_RAM_BASE + 20 ) + #define HDMI_RAM_GCP_6 HW_REGISTER_RW( HDMI_RAM_BASE + 24 ) + #define HDMI_RAM_GCP_7 HW_REGISTER_RW( HDMI_RAM_BASE + 28 ) + #define HDMI_RAM_GCP_8 HW_REGISTER_RW( HDMI_RAM_BASE + 32 ) + #define HDMI_RAM_PACKET_1_0 HW_REGISTER_RW( HDMI_RAM_BASE + 36 ) + #define HDMI_RAM_PACKET_1_1 HW_REGISTER_RW( HDMI_RAM_BASE + 40 ) + #define HDMI_RAM_PACKET_1_2 HW_REGISTER_RW( HDMI_RAM_BASE + 44 ) + #define HDMI_RAM_PACKET_1_3 HW_REGISTER_RW( HDMI_RAM_BASE + 48 ) + #define HDMI_RAM_PACKET_1_4 HW_REGISTER_RW( HDMI_RAM_BASE + 52 ) + #define HDMI_RAM_PACKET_1_5 HW_REGISTER_RW( HDMI_RAM_BASE + 56 ) + #define HDMI_RAM_PACKET_1_6 HW_REGISTER_RW( HDMI_RAM_BASE + 60 ) + #define HDMI_RAM_PACKET_1_7 HW_REGISTER_RW( HDMI_RAM_BASE + 64 ) + #define HDMI_RAM_PACKET_1_8 HW_REGISTER_RW( HDMI_RAM_BASE + 68 ) + #define HDMI_RAM_PACKET_2_0 HW_REGISTER_RW( HDMI_RAM_BASE + 72 ) + #define HDMI_RAM_PACKET_2_1 HW_REGISTER_RW( HDMI_RAM_BASE + 76 ) + #define HDMI_RAM_PACKET_2_2 HW_REGISTER_RW( HDMI_RAM_BASE + 80 ) + #define HDMI_RAM_PACKET_2_3 HW_REGISTER_RW( HDMI_RAM_BASE + 84 ) + #define HDMI_RAM_PACKET_2_4 HW_REGISTER_RW( HDMI_RAM_BASE + 88 ) + #define HDMI_RAM_PACKET_2_5 HW_REGISTER_RW( HDMI_RAM_BASE + 92 ) + #define HDMI_RAM_PACKET_2_6 HW_REGISTER_RW( HDMI_RAM_BASE + 96 ) + #define HDMI_RAM_PACKET_2_7 HW_REGISTER_RW( HDMI_RAM_BASE + 100 ) + #define HDMI_RAM_PACKET_2_8 HW_REGISTER_RW( HDMI_RAM_BASE + 104 ) + #define HDMI_RAM_PACKET_3_0 HW_REGISTER_RW( HDMI_RAM_BASE + 108 ) + #define HDMI_RAM_PACKET_3_1 HW_REGISTER_RW( HDMI_RAM_BASE + 112 ) + #define HDMI_RAM_PACKET_3_2 HW_REGISTER_RW( HDMI_RAM_BASE + 116 ) + #define HDMI_RAM_PACKET_3_3 HW_REGISTER_RW( HDMI_RAM_BASE + 120 ) + #define HDMI_RAM_PACKET_3_4 HW_REGISTER_RW( HDMI_RAM_BASE + 124 ) + #define HDMI_RAM_PACKET_3_5 HW_REGISTER_RW( HDMI_RAM_BASE + 128 ) + #define HDMI_RAM_PACKET_3_6 HW_REGISTER_RW( HDMI_RAM_BASE + 132 ) + #define HDMI_RAM_PACKET_3_7 HW_REGISTER_RW( HDMI_RAM_BASE + 136 ) + #define HDMI_RAM_PACKET_3_8 HW_REGISTER_RW( HDMI_RAM_BASE + 140 ) + #define HDMI_RAM_PACKET_4_0 HW_REGISTER_RW( HDMI_RAM_BASE + 144 ) + #define HDMI_RAM_PACKET_4_1 HW_REGISTER_RW( HDMI_RAM_BASE + 148 ) + #define HDMI_RAM_PACKET_4_2 HW_REGISTER_RW( HDMI_RAM_BASE + 152 ) + #define HDMI_RAM_PACKET_4_3 HW_REGISTER_RW( HDMI_RAM_BASE + 156 ) + #define HDMI_RAM_PACKET_4_4 HW_REGISTER_RW( HDMI_RAM_BASE + 160 ) + #define HDMI_RAM_PACKET_4_5 HW_REGISTER_RW( HDMI_RAM_BASE + 164 ) + #define HDMI_RAM_PACKET_4_6 HW_REGISTER_RW( HDMI_RAM_BASE + 168 ) + #define HDMI_RAM_PACKET_4_7 HW_REGISTER_RW( HDMI_RAM_BASE + 172 ) + #define HDMI_RAM_PACKET_4_8 HW_REGISTER_RW( HDMI_RAM_BASE + 176 ) + #define HDMI_RAM_PACKET_5_0 HW_REGISTER_RW( HDMI_RAM_BASE + 180 ) + #define HDMI_RAM_PACKET_5_1 HW_REGISTER_RW( HDMI_RAM_BASE + 184 ) + #define HDMI_RAM_PACKET_5_2 HW_REGISTER_RW( HDMI_RAM_BASE + 188 ) + #define HDMI_RAM_PACKET_5_3 HW_REGISTER_RW( HDMI_RAM_BASE + 192 ) + #define HDMI_RAM_PACKET_5_4 HW_REGISTER_RW( HDMI_RAM_BASE + 196 ) + #define HDMI_RAM_PACKET_5_5 HW_REGISTER_RW( HDMI_RAM_BASE + 200 ) + #define HDMI_RAM_PACKET_5_6 HW_REGISTER_RW( HDMI_RAM_BASE + 204 ) + #define HDMI_RAM_PACKET_5_7 HW_REGISTER_RW( HDMI_RAM_BASE + 208 ) + #define HDMI_RAM_PACKET_5_8 HW_REGISTER_RW( HDMI_RAM_BASE + 212 ) + #define HDMI_RAM_PACKET_6_0 HW_REGISTER_RW( HDMI_RAM_BASE + 216 ) + #define HDMI_RAM_PACKET_6_1 HW_REGISTER_RW( HDMI_RAM_BASE + 220 ) + #define HDMI_RAM_PACKET_6_2 HW_REGISTER_RW( HDMI_RAM_BASE + 224 ) + #define HDMI_RAM_PACKET_6_3 HW_REGISTER_RW( HDMI_RAM_BASE + 228 ) + #define HDMI_RAM_PACKET_6_4 HW_REGISTER_RW( HDMI_RAM_BASE + 232 ) + #define HDMI_RAM_PACKET_6_5 HW_REGISTER_RW( HDMI_RAM_BASE + 236 ) + #define HDMI_RAM_PACKET_6_6 HW_REGISTER_RW( HDMI_RAM_BASE + 240 ) + #define HDMI_RAM_PACKET_6_7 HW_REGISTER_RW( HDMI_RAM_BASE + 244 ) + #define HDMI_RAM_PACKET_6_8 HW_REGISTER_RW( HDMI_RAM_BASE + 248 ) + #define HDMI_RAM_PACKET_7_0 HW_REGISTER_RW( HDMI_RAM_BASE + 252 ) + #define HDMI_RAM_PACKET_7_1 HW_REGISTER_RW( HDMI_RAM_BASE + 256 ) + #define HDMI_RAM_PACKET_7_2 HW_REGISTER_RW( HDMI_RAM_BASE + 260 ) + #define HDMI_RAM_PACKET_7_3 HW_REGISTER_RW( HDMI_RAM_BASE + 264 ) + #define HDMI_RAM_PACKET_7_4 HW_REGISTER_RW( HDMI_RAM_BASE + 268 ) + #define HDMI_RAM_PACKET_7_5 HW_REGISTER_RW( HDMI_RAM_BASE + 272 ) + #define HDMI_RAM_PACKET_7_6 HW_REGISTER_RW( HDMI_RAM_BASE + 276 ) + #define HDMI_RAM_PACKET_7_7 HW_REGISTER_RW( HDMI_RAM_BASE + 280 ) + #define HDMI_RAM_PACKET_7_8 HW_REGISTER_RW( HDMI_RAM_BASE + 284 ) + #define HDMI_RAM_PACKET_8_0 HW_REGISTER_RW( HDMI_RAM_BASE + 288 ) + #define HDMI_RAM_PACKET_8_1 HW_REGISTER_RW( HDMI_RAM_BASE + 292 ) + #define HDMI_RAM_PACKET_8_2 HW_REGISTER_RW( HDMI_RAM_BASE + 296 ) + #define HDMI_RAM_PACKET_8_3 HW_REGISTER_RW( HDMI_RAM_BASE + 300 ) + #define HDMI_RAM_PACKET_8_4 HW_REGISTER_RW( HDMI_RAM_BASE + 304 ) + #define HDMI_RAM_PACKET_8_5 HW_REGISTER_RW( HDMI_RAM_BASE + 308 ) + #define HDMI_RAM_PACKET_8_6 HW_REGISTER_RW( HDMI_RAM_BASE + 312 ) + #define HDMI_RAM_PACKET_8_7 HW_REGISTER_RW( HDMI_RAM_BASE + 316 ) + #define HDMI_RAM_PACKET_8_8 HW_REGISTER_RW( HDMI_RAM_BASE + 320 ) + #define HDMI_RAM_PACKET_9_0 HW_REGISTER_RW( HDMI_RAM_BASE + 324 ) + #define HDMI_RAM_PACKET_9_1 HW_REGISTER_RW( HDMI_RAM_BASE + 328 ) + #define HDMI_RAM_PACKET_9_2 HW_REGISTER_RW( HDMI_RAM_BASE + 332 ) + #define HDMI_RAM_PACKET_9_3 HW_REGISTER_RW( HDMI_RAM_BASE + 336 ) + #define HDMI_RAM_PACKET_9_4 HW_REGISTER_RW( HDMI_RAM_BASE + 340 ) + #define HDMI_RAM_PACKET_9_5 HW_REGISTER_RW( HDMI_RAM_BASE + 344 ) + #define HDMI_RAM_PACKET_9_6 HW_REGISTER_RW( HDMI_RAM_BASE + 348 ) + #define HDMI_RAM_PACKET_9_7 HW_REGISTER_RW( HDMI_RAM_BASE + 352 ) + #define HDMI_RAM_PACKET_9_8 HW_REGISTER_RW( HDMI_RAM_BASE + 356 ) + #define HDMI_RAM_PACKET_10_0 HW_REGISTER_RW( HDMI_RAM_BASE + 360 ) + #define HDMI_RAM_PACKET_10_1 HW_REGISTER_RW( HDMI_RAM_BASE + 364 ) + #define HDMI_RAM_PACKET_10_2 HW_REGISTER_RW( HDMI_RAM_BASE + 368 ) + #define HDMI_RAM_PACKET_10_3 HW_REGISTER_RW( HDMI_RAM_BASE + 372 ) + #define HDMI_RAM_PACKET_10_4 HW_REGISTER_RW( HDMI_RAM_BASE + 376 ) + #define HDMI_RAM_PACKET_10_5 HW_REGISTER_RW( HDMI_RAM_BASE + 380 ) + #define HDMI_RAM_PACKET_10_6 HW_REGISTER_RW( HDMI_RAM_BASE + 384 ) + #define HDMI_RAM_PACKET_10_7 HW_REGISTER_RW( HDMI_RAM_BASE + 388 ) + #define HDMI_RAM_PACKET_10_8 HW_REGISTER_RW( HDMI_RAM_BASE + 392 ) + #define HDMI_RAM_PACKET_11_0 HW_REGISTER_RW( HDMI_RAM_BASE + 396 ) + #define HDMI_RAM_PACKET_11_1 HW_REGISTER_RW( HDMI_RAM_BASE + 400 ) + #define HDMI_RAM_PACKET_11_2 HW_REGISTER_RW( HDMI_RAM_BASE + 404 ) + #define HDMI_RAM_PACKET_11_3 HW_REGISTER_RW( HDMI_RAM_BASE + 408 ) + #define HDMI_RAM_PACKET_11_4 HW_REGISTER_RW( HDMI_RAM_BASE + 412 ) + #define HDMI_RAM_PACKET_11_5 HW_REGISTER_RW( HDMI_RAM_BASE + 416 ) + #define HDMI_RAM_PACKET_11_6 HW_REGISTER_RW( HDMI_RAM_BASE + 420 ) + #define HDMI_RAM_PACKET_11_7 HW_REGISTER_RW( HDMI_RAM_BASE + 424 ) + #define HDMI_RAM_PACKET_11_8 HW_REGISTER_RW( HDMI_RAM_BASE + 428 ) + #define HDMI_RAM_PACKET_12_0 HW_REGISTER_RW( HDMI_RAM_BASE + 432 ) + #define HDMI_RAM_PACKET_12_1 HW_REGISTER_RW( HDMI_RAM_BASE + 436 ) + #define HDMI_RAM_PACKET_12_2 HW_REGISTER_RW( HDMI_RAM_BASE + 440 ) + #define HDMI_RAM_PACKET_12_3 HW_REGISTER_RW( HDMI_RAM_BASE + 444 ) + #define HDMI_RAM_PACKET_12_4 HW_REGISTER_RW( HDMI_RAM_BASE + 448 ) + #define HDMI_RAM_PACKET_12_5 HW_REGISTER_RW( HDMI_RAM_BASE + 452 ) + #define HDMI_RAM_PACKET_12_6 HW_REGISTER_RW( HDMI_RAM_BASE + 456 ) + #define HDMI_RAM_PACKET_12_7 HW_REGISTER_RW( HDMI_RAM_BASE + 460 ) + #define HDMI_RAM_PACKET_12_8 HW_REGISTER_RW( HDMI_RAM_BASE + 464 ) + #define HDMI_RAM_PACKET_13_0 HW_REGISTER_RW( HDMI_RAM_BASE + 468 ) + #define HDMI_RAM_PACKET_13_1 HW_REGISTER_RW( HDMI_RAM_BASE + 472 ) + #define HDMI_RAM_PACKET_13_2 HW_REGISTER_RW( HDMI_RAM_BASE + 476 ) + #define HDMI_RAM_PACKET_13_3 HW_REGISTER_RW( HDMI_RAM_BASE + 480 ) + #define HDMI_RAM_PACKET_13_4 HW_REGISTER_RW( HDMI_RAM_BASE + 484 ) + #define HDMI_RAM_PACKET_13_5 HW_REGISTER_RW( HDMI_RAM_BASE + 488 ) + #define HDMI_RAM_PACKET_13_6 HW_REGISTER_RW( HDMI_RAM_BASE + 492 ) + #define HDMI_RAM_PACKET_13_7 HW_REGISTER_RW( HDMI_RAM_BASE + 496 ) + #define HDMI_RAM_PACKET_13_8 HW_REGISTER_RW( HDMI_RAM_BASE + 500 ) + #define HDMI_RAM_PACKET_RSVD_0 HW_REGISTER_RW( HDMI_RAM_BASE + 504 ) + #define HDMI_RAM_PACKET_RSVD_1 HW_REGISTER_RW( HDMI_RAM_BASE + 508 ) + + + + + /*---------------------------------------------------------------------------*/ + /* DMA Controller */ + + /* DMA Source Definitions */ + + #define CAM_DMA (0*DMA_TI_PERMAP) + #define DISP_DMA (0*DMA_TI_PERMAP) + #define MS_DMA (0*DMA_TI_PERMAP) + #define BIT_STREAM_DMA (0*DMA_TI_PERMAP) + #define ACIS_DMA (0*DMA_TI_PERMAP) + #define SDRAM_CTRL_DMA (0*DMA_TI_PERMAP) + + #define DSI_DMA ( 1*DMA_TI_PERMAP) + #define PCM_TX_DMA ( 2*DMA_TI_PERMAP) + #define PCM_RX_DMA ( 3*DMA_TI_PERMAP) + #define SMI_DMA ( 4*DMA_TI_PERMAP) + #define PWM_DMA ( 5*DMA_TI_PERMAP) + #define SPI_TX_DMA ( 6*DMA_TI_PERMAP) + #define SPI_RX_DMA ( 7*DMA_TI_PERMAP) + #define SLIM_DTX_DMA ( 8*DMA_TI_PERMAP) + #define SLIM_DRX_DMA ( 9*DMA_TI_PERMAP) + #define SLIM_CTX_DMA (10*DMA_TI_PERMAP) + #define SLIM_CRX_DMA (11*DMA_TI_PERMAP) + #define UNUSED_DMA_12 (12*DMA_TI_PERMAP) + #define SD_HOST_DMA (13*DMA_TI_PERMAP) + #define UNUSED_DMA_14 (14*DMA_TI_PERMAP) + #define ADC_DMA (15*DMA_TI_PERMAP) + #define DSI2_DMA (16*DMA_TI_PERMAP) + #define HDMI_DMA (17*DMA_TI_PERMAP) + // 18 unused + #define CRYPTO_IP_DMA (19*DMA_TI_PERMAP) + #define CRYPTO_OP_DMA (20*DMA_TI_PERMAP) + #define SCALER_0_DMA (21*DMA_TI_PERMAP) + #define SCALER_1_DMA (22*DMA_TI_PERMAP) + #define SCALER_2_DMA (23*DMA_TI_PERMAP) + #define SMI_SCALER_0_DMA (24*DMA_TI_PERMAP) + #define SMI_SCALER_1_DMA (25*DMA_TI_PERMAP) + #define SMI_SCALER_2_DMA (26*DMA_TI_PERMAP) + // 27-31 unused + + + /*---------------------------------------------------------------------------*/ + + #define DMA_CH_BASE(n) (DMA0_BASE+(n)*0x100) + #define DMA_REG(n,offset) HW_REGISTER_RW(DMA_CH_BASE(n)+(offset)) + #define DMA_INTERRUPT(n) (INTERRUPT_DMA0+(n)) + + + /* DMA Register Addresses */ + #define DMA_CS(n) DMA_REG(n,0x00) + #define DMA_CB_ADDR(n) DMA_REG(n,0x04) + #define DMA_CB_TI(n) DMA_REG(n,0x08) + #define DMA_CB_SA(n) DMA_REG(n,0x0C) + #define DMA_CB_DA(n) DMA_REG(n,0x10) + #define DMA_CB_TL(n) DMA_REG(n,0x14) + #define DMA_CB_2DSTR(n) DMA_REG(n,0x18) + #define DMA_CB_NEXT(n) DMA_REG(n,0x1C) + #define DMA_DEBUG(n) DMA_REG(n,0x20) + + +/* B0 DEFINITIONS */ + /* DMA_CS - Control and status reg bit fields */ + #define DMA_CS_ACTIVE (1<<0) + #define DMA_CS_END (1<<1) + #define DMA_CS_INT (1<<2) + #define DMA_CS_DREQ (1<<3) + #define DMA_CS_PAUSED (1<<4) + #define DMA_CS_DREQ_PAUSED (1<<5) + #define DMA_CS_WAITING_FOR_LAST_WRITE (1<<6) + #define DMA_CS_ERROR (1<<8) + #define DMA_CS_PRIORITY (1<<16) + #define DMA_CS_PANIC_PRIORITY (1<<20) + #define DMA_CS_WAIT_FOR_LAST_WRITE (1<<28) + #define DMA_CS_DIS_DBS_PAUSE (1<<29) + #define DMA_CS_ABORT (1<<30) + #define DMA_CS_RESET (1<<31) + + /* DMA_CB_TI - Control Block, Transfer Information fields */ + #define DMA_TI_INT (1<<0) + #define DMA_TI_TDMODE (1<<1) + #define DMA_TI_WAIT_RESP (1<<3) + #define DMA_TI_D_INC (1<<4) + #define DMA_TI_D_WIDTH (1<<5) + #define DMA_TI_D_128 (1<<5) + #define DMA_TI_D_32 0 + #define DMA_TI_D_DREQ (1<<6) + #define DMA_TI_D_IGNORE (1<<7) + #define DMA_TI_S_INC (1<<8) + #define DMA_TI_S_WIDTH (1<<9) + #define DMA_TI_S_128 (1<<9) + #define DMA_TI_S_32 0 + #define DMA_TI_S_DREQ (1<<10) + #define DMA_TI_S_IGNORE (1<<11) + #define DMA_TI_BURST_N(n) (((n) & 0x0f) <<12) + #define DMA_TI_PERMAP (1<<16) + #define DMA_TI_PER_MAP(n) (((n) & 0x1f) <<16) + #define DMA_TI_WAITS(n) (((n) & 0x1f) <<21) + #define DMA_TI_NO_WIDE_BURSTS (1<<26) + + /* DMA_DEBUG - Debug Register bit fields */ + #define DMA_DEBUG_VERSION (1<<25) + #define DMA_DEBUG_STATE (1<<16) + #define DMA_DEBUG_ID (1<<8) + #define DMA_DEBUG_OUTSTANDING_WRITES (1<<4) + #define DMA_DEBUG_READ_ERR (1<<2) + #define DMA_DEBUG_FIFO_ERR (1<<1) + #define DMA_DEBUG_READ_LAST_ERR (0) + + /* dma15 address is used as a highlevel enable for each DMA for clock gate purposes */ + #define DMA_ENABLE HW_REGISTER_RW(DMA_CH_BASE(15)) + + + + + + + + /*---------------------------------------------------------------------------*/ + /* Startup uses these so point them to core 0 int controller */ + #define IC_VADDR IC0_VADDR + #define IC_MASK0 IC0_MASK0 + + /*---------------------------------------------------------------------------*/ + /* Interrupt Controller for core 0 */ + + + #define IC_0 IC0_C + #define IS_0 IC0_S + #define ISRC0_0 IC0_SRC0 + #define ISRC1_0 IC0_SRC1 + #define IMASK0_0 IC0_MASK0 + #define IMASK1_0 IC0_MASK1 + #define IMASK2_0 IC0_MASK2 + #define IMASK3_0 IC0_MASK3 + #define IMASK4_0 IC0_MASK4 + #define IMASK5_0 IC0_MASK5 + #define IMASK6_0 IC0_MASK6 + #define IMASK7_0 IC0_MASK7 + #define IMASKx_0( x ) IC0_MASKx( x ) + #define IVADDR_0 IC0_VADDR + #define IWAKEUP_0 IC0_WAKEUP + #define IPROFILE_0 IC0_PROFILE + #define IFORCE0_0 IC0_FORCE0 + #define IFORCE1_0 IC0_FORCE1 + + + //we are assigning the VCII regs to core 0 for temp software compatability + #define IC IC_0 + #define IS IS_0 + #define ISRC ISRC0_0 + #define IMASK0 IMASK0_0 + #define IMASK1 IMASK1_0 + #define IMASK2 IMASK2_0 + #define IMASK3 IMASK3_0 + + /*---------------------------------------------------------------------------*/ + /* System Timer */ + + //the first core's timer block + #define STCS_0 ST_CS + #define STC_0 ST_CLO + #define STCLO_0 ST_CLO + #define STCHI_0 ST_CHI + #define STC0_0 ST_C0 + #define STC1_0 ST_C1 + #define STC2_0 ST_C2 + #define STC3_0 ST_C3 + + + //Sys timer select macro's + #define STCS_x( x ) ( ((x)==0) ? STCS_0 : STCS_1 ) + #define STC_x( x ) ( ((x)==0) ? STC_0 : STC_1 ) + #define STCLO_x( x ) ( ((x)==0) ? STCLO_0 : STCLO_1 ) + #define STCHI_x( x ) ( ((x)==0) ? STCHI_0 : STCHI_1 ) + #define STC0_x( x ) ( ((x)==0) ? STC0_0 : STC0_1 ) + #define STC1_x( x ) ( ((x)==0) ? STC1_0 : STC1_1 ) + #define STC2_x( x ) ( ((x)==0) ? STC2_0 : STC2_1 ) + #define STC3_x( x ) ( ((x)==0) ? STC3_0 : STC3_1 ) + + //Temp - define the old register names to look like timer_0 on core 0 + #define STCS STCS_0 + #define STC STC_0 + #define STCLO STCLO_0 + #define STCHI STCHI_0 + #define STC0 STC0_0 + #define STC1 STC1_0 + #define STC2 STC2_0 + #define STC3 STC3_0 + + /*---------------------------------------------------------------------------*/ + /* Crypto/ID module */ + #define IDCLVWMCU HW_REGISTER_RW(0x10002000) + #define IDCMDIDU HW_REGISTER_RW(0x10002004) + #define IDCKEYHU HW_REGISTER_RW(0x10002008) + #define IDCKEYLU HW_REGISTER_RW(0x1000200C) + #define IDCCMD HW_REGISTER_RW(0x10002010) + #define IDCCFG HW_REGISTER_RW(0x10002014) + #define IDCKSEL HW_REGISTER_RW(0x10002018) + #define IDCLVWMC HW_REGISTER_RW(0x10002020) + #define IDCMDID HW_REGISTER_RW(0x10002024) + + /*---------------------------------------------------------------------------*/ + /* Single 16550 UART */ + #define URBR HW_REGISTER_RO(UART_BASE + 0x00) + #define UTHR HW_REGISTER_RW(UART_BASE + 0x00) + #define UIER HW_REGISTER_RW(UART_BASE + 0x04) + #define UIIR HW_REGISTER_RO(UART_BASE + 0x08) + #define UFCR HW_REGISTER_RW(UART_BASE + 0x08) + #define ULCR HW_REGISTER_RW(UART_BASE + 0x0C) + #define UMCR HW_REGISTER_RW(UART_BASE + 0x10) + #define ULSR HW_REGISTER_RW(UART_BASE + 0x14) + #define UMSR HW_REGISTER_RW(UART_BASE + 0x18) + #define USCR HW_REGISTER_RW(UART_BASE + 0x1C) + #define UDLL HW_REGISTER_RW(UART_BASE + 0x00) + #define UDLM HW_REGISTER_RW(UART_BASE + 0x04) + #define UEN HW_REGISTER_RW(UART_BASE + 0x20) + + #define VIDEOCORE_NUM_UART_PORTS 1 + + /*---------------------------------------------------------------------------*/ + /* ADC */ + #define ADCCS HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x00) + #define ADCR0 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x04) + #define ADCR1 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x08) + + /*---------------------------------------------------------------------------*/ + /* General Purpose I/O */ + #define GPFSEL0 HW_REGISTER_RW(GP_BASE + 0x00) + #define GPFSEL1 HW_REGISTER_RW(GP_BASE + 0x04) + #define GPFSEL2 HW_REGISTER_RW(GP_BASE + 0x08) + #define GPFSEL3 HW_REGISTER_RW(GP_BASE + 0x0c) + #define GPFSEL4 HW_REGISTER_RW(GP_BASE + 0x10) + #define GPFSEL5 HW_REGISTER_RW(GP_BASE + 0x14) + #define GPFSEL6 HW_REGISTER_RW(GP_BASE + 0x18) + + #define GPSET0 HW_REGISTER_RW(GP_BASE + 0x1C) + #define GPSET1 HW_REGISTER_RW(GP_BASE + 0x20) + #define GPSET2 HW_REGISTER_RW(GP_BASE + 0x24) + + #define GPCLR0 HW_REGISTER_RW(GP_BASE + 0x28) + #define GPCLR1 HW_REGISTER_RW(GP_BASE + 0x2C) + #define GPCLR2 HW_REGISTER_RW(GP_BASE + 0x30) + + #define GPLEV0 HW_REGISTER_RW(GP_BASE + 0x34) + #define GPLEV1 HW_REGISTER_RW(GP_BASE + 0x38) + #define GPLEV2 HW_REGISTER_RW(GP_BASE + 0x3C) + + #define GPEDS0 HW_REGISTER_RW(GP_BASE + 0x40) + #define GPEDS1 HW_REGISTER_RW(GP_BASE + 0x44) + #define GPEDS2 HW_REGISTER_RW(GP_BASE + 0x48) + + #define GPREN0 HW_REGISTER_RW(GP_BASE + 0x4C) + #define GPREN1 HW_REGISTER_RW(GP_BASE + 0x50) + #define GPREN2 HW_REGISTER_RW(GP_BASE + 0x54) + + #define GPFEN0 HW_REGISTER_RW(GP_BASE + 0x58) + #define GPFEN1 HW_REGISTER_RW(GP_BASE + 0x5C) + #define GPFEN2 HW_REGISTER_RW(GP_BASE + 0x60) + + #define GPHEN0 HW_REGISTER_RW(GP_BASE + 0x64) + #define GPHEN1 HW_REGISTER_RW(GP_BASE + 0x68) + #define GPHEN2 HW_REGISTER_RW(GP_BASE + 0x6C) + + #define GPLEN0 HW_REGISTER_RW(GP_BASE + 0x70) + #define GPLEN1 HW_REGISTER_RW(GP_BASE + 0x74) + #define GPLEN2 HW_REGISTER_RW(GP_BASE + 0x78) + + #define GPAREN0 HW_REGISTER_RW(GP_BASE + 0x7C) + #define GPAREN1 HW_REGISTER_RW(GP_BASE + 0x80) + #define GPAREN2 HW_REGISTER_RW(GP_BASE + 0x84) + + #define GPAFEN0 HW_REGISTER_RW(GP_BASE + 0x88) + #define GPAFEN1 HW_REGISTER_RW(GP_BASE + 0x8C) + #define GPAFEN2 HW_REGISTER_RW(GP_BASE + 0x90) + + #define GPPUD HW_REGISTER_RW(GP_BASE + 0x94) + #define GPPUDCLK0 HW_REGISTER_RW(GP_BASE + 0x98) + #define GPPUDCLK1 HW_REGISTER_RW(GP_BASE + 0x9C) + #define GPPUDCLK2 HW_REGISTER_RW(GP_BASE + 0xA0) + + /*---------------------------------------------------------------------------*/ + /* JPEG block */ + #define JCTRL HW_REGISTER_RW(JP_BASE + 0) + #define JICST HW_REGISTER_RW(JP_BASE + 0x4) + #define JMCTRL HW_REGISTER_RW(JP_BASE + 0x8) + #define JDCCTRL HW_REGISTER_RW(JP_BASE + 0x0C) + #define JCBA HW_REGISTER_RW(JP_BASE + 0x10) + #define JNCB HW_REGISTER_RW(JP_BASE + 0x14) + #define JSDA HW_REGISTER_RW(JP_BASE + 0x18) + #define JNSB HW_REGISTER_RW(JP_BASE + 0x1C) + #define JSBO HW_REGISTER_RW(JP_BASE + 0x20) + #define JMOP HW_REGISTER_RW(JP_BASE + 0x24) + #define JHADDR HW_REGISTER_RW(JP_BASE + 0x28) + #define JHWDATA HW_REGISTER_RW(JP_BASE + 0x2C) + #define JMADDR HW_REGISTER_RW(JP_BASE + 0x30) + #define JMWDATA HW_REGISTER_RW(JP_BASE + 0x34) + #define JOADDR HW_REGISTER_RW(JP_BASE + 0x38) + #define JOWDATA HW_REGISTER_RW(JP_BASE + 0x3C) + + #define JCTRL_START (1 << 7) + #define JCTRL_RESET (1 << 3) + #define JCTRL_FLUSH (1 << 2) + #define JCTRL_STUFF (1 << 1) + #define JCTRL_MODE (1 << 0) + + #define JHADDR_TABLEF (1 << 31) + + #define JICST_ERR (1 << 19) + #define JICST_MARKER (1 << 18) + #define JICST_SDONE (1 << 17) + #define JICST_CDONE (1 << 16) + #define JICST_INTE (1 << 3) + #define JICST_INTM (1 << 2) + #define JICST_INTSD (1 << 1) + #define JICST_INTCD (1 << 0) + + #define JDCCTRL_DISDC (1 << 20) + #define JDCCTRL_SETDC(n) (1 << ((n) + 16)) + #define JDCCTRL_DCCOMP_MASK 0xFFFF + + #define JMCTRL_DC_TAB(n) (1 << (2*(n))) + #define JMCTRL_AC_TAB(n) (1 << (2*(n)+1)) + #define JMCTRL_NUMCMP (1 << 8) + #define JMCTRL_CMP(n) (1 << (4*(n) + 16)) + + #define JMCTRL_UNUSED_BITS ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12) | (1 << 11)) + + #define AC_HUFFTABLE_OFFSET(t) ((t) * 0x100) + #define DC_HUFFTABLE_OFFSET(t) ((t) * 0x10 + 0x200) + + #define AC_OSETTABLE_OFFSET(t) ((t) * 0x10) + #define DC_OSETTABLE_OFFSET(t) ((t) * 0x10 + 0x20) + + #define AC_MAXCTABLE_OFFSET(t) ((t) * 0x10) + #define DC_MAXCTABLE_OFFSET(t) ((t) * 0x10 + 0x20) + + /*---------------------------------------------------------------------------*/ + /* External Memory Interface */ + #define SDCS SD_CS + #define SDSA SD_SA + #define SDSB SD_SB + #define SDSC SD_SC + #define SDEM SD_EM + #define SDPT SD_PT + #define SDIDL SD_IDL + #define SDRTC SD_RTC + #define SDWTC SD_WTC + #define SDRDC SD_RDC + #define SDWDC SD_WDC + #define SDRAC SD_RAC + #define SDCYC SD_CYC + #define SDACC SD_ACC + #define SDDAT SD_DAT + #define SDSECSRT0 SD_SECSRT0 + #define SDSECEND0 SD_SECEND0 + #define SDSECSRT1 SD_SECSRT1 + #define SDSECEND1 SD_SECEND1 + #define SDSECSRT2 SD_SECSRT2 + #define SDSECEND2 SD_SECEND2 + #define SDSECSRT3 SD_SECSRT3 + #define SDSECEND3 SD_SECEND3 + #define SDDELC0 SD_DELC0 + #define SDDELS0 SD_DELS0 + #define SDDELC1 SD_DELC1 + #define SDDELS1 SD_DELS1 + #define SDDELC2 SD_DELC2 + #define SDDELS2 SD_DELS2 + #define SDDELC3 SD_DELC3 + #define SDDELS3 SD_DELS3 + #define SDTMC SD_TMC + + + /*---------------------------------------------------------------------------*/ + /* SPI Master */ + #define SPICS HW_REGISTER_RW(SPI_BASE_ADDRESS + 0x00) + #define SPIFIFO HW_REGISTER_RW(SPI_BASE_ADDRESS + 0x04) + #define SPICLK HW_REGISTER_RW(SPI_BASE_ADDRESS + 0x08) + #define SPIDLEN HW_REGISTER_RW(SPI_BASE_ADDRESS + 0x0C) + + /*---------------------------------------------------------------------------*/ + /* Secondary Memory Interface */ + + #define SMICS HW_REGISTER_RW(SMI_BASE + 0x00) + #define SMIL HW_REGISTER_RW(SMI_BASE + 0x04) + #define SMIA HW_REGISTER_RW(SMI_BASE + 0x08) + #define SMID HW_REGISTER_RW(SMI_BASE + 0x0C) + #define SMIDSR0 HW_REGISTER_RW(SMI_BASE + 0x10) + #define SMIDSW0 HW_REGISTER_RW(SMI_BASE + 0x14) + #define SMIDSR1 HW_REGISTER_RW(SMI_BASE + 0x18) + #define SMIDSW1 HW_REGISTER_RW(SMI_BASE + 0x1C) + #define SMIDSR2 HW_REGISTER_RW(SMI_BASE + 0x20) + #define SMIDSW2 HW_REGISTER_RW(SMI_BASE + 0x24) + #define SMIDSR3 HW_REGISTER_RW(SMI_BASE + 0x28) + #define SMIDSW3 HW_REGISTER_RW(SMI_BASE + 0x2C) + #define SMIDC HW_REGISTER_RW(SMI_BASE + 0x30) + #define SMIDCS HW_REGISTER_RW(SMI_BASE + 0x34) + #define SMIDA HW_REGISTER_RW(SMI_BASE + 0x38) + #define SMIDD HW_REGISTER_RW(SMI_BASE + 0x3C) + + #define SMI_FIFO_ADDRESS(device,addr) (((((device))&0x3)<<8)|((addr)&0xff)) + + /*---------------------------------------------------------------------------*/ + /* TE Controller */ + + #define TE0C HW_REGISTER_RW(TECTL_BASE_ADDRESS + 0x00) + #define TE1C HW_REGISTER_RW(TECTL_BASE_ADDRESS + 0x04) + #define TE0_VSWIDTH HW_REGISTER_RW(TECTL_BASE_ADDRESS + 0x08) + #define TE1_VSWIDTH HW_REGISTER_RW(TECTL_BASE_ADDRESS + 0x0C) + + /*---------------------------------------------------------------------------*/ + /* AC'97/I2S Controller */ + #define ACISCS HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x00 ) + #define ACISFIFO HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x04 ) + #define ACISCA HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x08 ) + #define ACISCD HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x0C ) + #define ACISMODE HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x10 ) + #define ACISASR HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x14 ) + + #define ACPLAYRATE 0x2c + #define ACRECORDRATE 0x32 + + /*---------------------------------------------------------------------------*/ + /* SD card host */ + #define SDCMD HW_REGISTER_RW(SDCARD_BASE + 0x00) + #define SDARG HW_REGISTER_RW(SDCARD_BASE + 0x04) + #define SDTOUT HW_REGISTER_RW(SDCARD_BASE + 0x08) + #define SDCDIV HW_REGISTER_RW(SDCARD_BASE + 0x0C) + #define SDRSP0 HW_REGISTER_RW(SDCARD_BASE + 0x10) + #define SDRSP1 HW_REGISTER_RW(SDCARD_BASE + 0x14) + #define SDRSP2 HW_REGISTER_RW(SDCARD_BASE + 0x18) + #define SDRSP3 HW_REGISTER_RW(SDCARD_BASE + 0x1C) + #define SDHSTS HW_REGISTER_RW(SDCARD_BASE + 0x20) + #define SDVDD HW_REGISTER_RW(SDCARD_BASE + 0x30) + #define SDEDM HW_REGISTER_RW(SDCARD_BASE + 0x34) + #define SDHCFG HW_REGISTER_RW(SDCARD_BASE + 0x38) + #define SDHBCT HW_REGISTER_RW(SDCARD_BASE + 0x3C) + #define SDDATA HW_REGISTER_RW(SDCARD_BASE + 0x40) + #define SDHBLC HW_REGISTER_RW(SDCARD_BASE + 0x50) + + /*---------------------------------------------------------------------------*/ + /* SLIMbus interface */ + #ifdef __BCM2707_A0__ + #define SLIM_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x000) + #define SLIM_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x004) + #define SLIM_FS HW_REGISTER_RW(SLIMBUS_BASE + 0x008) + #define SLIM_DMA_SMC_RX HW_REGISTER_RW(SLIMBUS_BASE + 0x010) + #define SLIM_DMA_SMC_TX HW_REGISTER_RW(SLIMBUS_BASE + 0x014) + #define SLIM_DMA_DC_RX HW_REGISTER_RW(SLIMBUS_BASE + 0x018) + #define SLIM_DMA_DC_TX HW_REGISTER_RW(SLIMBUS_BASE + 0x01C) + #define SLIM_SMC_IN_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x100) + #define SLIM_SMC_IN_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x104) + #define SLIM_SMC_OUT_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x120) + #define SLIM_SMC_OUT_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x124) + #define SLIM_DCC0_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x200) + #define SLIM_DCC0_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x204) + #define SLIM_DCC0_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x208) + #define SLIM_DCC0_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x20c) + #define SLIM_DCC1_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x220) + #define SLIM_DCC1_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x224) + #define SLIM_DCC1_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x228) + #define SLIM_DCC1_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x22c) + #define SLIM_DCC2_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x240) + #define SLIM_DCC2_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x244) + #define SLIM_DCC2_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x248) + #define SLIM_DCC2_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x24c) + #define SLIM_DCC3_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x260) + #define SLIM_DCC3_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x264) + #define SLIM_DCC3_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x268) + #define SLIM_DCC3_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x26c) + #define SLIM_DCC4_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x280) + #define SLIM_DCC4_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x284) + #define SLIM_DCC4_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x288) + #define SLIM_DCC4_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x28c) + #define SLIM_DCC5_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x2a0) + #define SLIM_DCC5_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x2a4) + #define SLIM_DCC5_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x2a8) + #define SLIM_DCC5_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x2ac) + #define SLIM_DCC6_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x2c0) + #define SLIM_DCC6_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x2c4) + #define SLIM_DCC6_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x2c8) + #define SLIM_DCC6_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x2cc) + #define SLIM_DCC7_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x2e0) + #define SLIM_DCC7_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x2e4) + #define SLIM_DCC7_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x2e8) + #define SLIM_DCC7_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x2ec) + #define SLIM_DCC8_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x300) + #define SLIM_DCC8_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x304) + #define SLIM_DCC8_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x308) + #define SLIM_DCC8_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x30c) + #define SLIM_DCC9_PA0 HW_REGISTER_RW(SLIMBUS_BASE + 0x320) + #define SLIM_DCC9_PA1 HW_REGISTER_RW(SLIMBUS_BASE + 0x324) + #define SLIM_DCC9_CON HW_REGISTER_RW(SLIMBUS_BASE + 0x328) + #define SLIM_DCC9_STAT HW_REGISTER_RW(SLIMBUS_BASE + 0x32c) + #endif + /*---------------------------------------------------------------------------*/ + /* PCM Controller */ + #define PCMCS HW_REGISTER_RW( PCM_BASE_ADDRESS + 0x00 ) + #define PCMFIFO HW_REGISTER_RW( PCM_BASE_ADDRESS + 0x04 ) + #define PCMMODE HW_REGISTER_RW( PCM_BASE_ADDRESS + 0x08 ) + #define PCMRXC HW_REGISTER_RW( PCM_BASE_ADDRESS + 0x0C ) + #define PCMTXC HW_REGISTER_RW( PCM_BASE_ADDRESS + 0x10 ) + #define PCMDREQ HW_REGISTER_RW( PCM_BASE_ADDRESS + 0x14 ) + + /*---------------------------------------------------------------------------*/ + /* I2C Master */ + #define I2CC_0 HW_REGISTER_RW(I2C_BASE_0 + 0x00) + #define I2CS_0 HW_REGISTER_RW(I2C_BASE_0 + 0x04) + #define I2CDLEN_0 HW_REGISTER_RW(I2C_BASE_0 + 0x08) + #define I2CA_0 HW_REGISTER_RW(I2C_BASE_0 + 0x0C) + #define I2CFIFO_0 HW_REGISTER_RW(I2C_BASE_0 + 0x10) + #define I2CDIV_0 HW_REGISTER_RW(I2C_BASE_0 + 0x14) + #define I2CDEL_0 HW_REGISTER_RW(I2C_BASE_0 + 0x18) + #define I2CCLKT_0 HW_REGISTER_RW(I2C_BASE_0 + 0x1C) + + #define I2CC_1 HW_REGISTER_RW(I2C_BASE_1 + 0x00) + #define I2CS_1 HW_REGISTER_RW(I2C_BASE_1 + 0x04) + #define I2CDLEN_1 HW_REGISTER_RW(I2C_BASE_1 + 0x08) + #define I2CA_1 HW_REGISTER_RW(I2C_BASE_1 + 0x0C) + #define I2CFIFO_1 HW_REGISTER_RW(I2C_BASE_1 + 0x10) + #define I2CDIV_1 HW_REGISTER_RW(I2C_BASE_1 + 0x14) + #define I2CDEL_1 HW_REGISTER_RW(I2C_BASE_1 + 0x18) + #define I2CCLKT_1 HW_REGISTER_RW(I2C_BASE_1 + 0x1C) + + #define I2CC_2 HW_REGISTER_RW(I2C_BASE_2 + 0x00) + #define I2CS_2 HW_REGISTER_RW(I2C_BASE_2 + 0x04) + #define I2CDLEN_2 HW_REGISTER_RW(I2C_BASE_2 + 0x08) + #define I2CA_2 HW_REGISTER_RW(I2C_BASE_2 + 0x0C) + #define I2CFIFO_2 HW_REGISTER_RW(I2C_BASE_2 + 0x10) + #define I2CDIV_2 HW_REGISTER_RW(I2C_BASE_2 + 0x14) + #define I2CDEL_2 HW_REGISTER_RW(I2C_BASE_2 + 0x18) + #define I2CCLKT_2 HW_REGISTER_RW(I2C_BASE_2 + 0x1C) + + #define I2CC_3 HW_REGISTER_RW(I2C_BASE_3 + 0x00) + #define I2CS_3 HW_REGISTER_RW(I2C_BASE_3 + 0x04) + #define I2CDLEN_3 HW_REGISTER_RW(I2C_BASE_3 + 0x08) + #define I2CA_3 HW_REGISTER_RW(I2C_BASE_3 + 0x0C) + #define I2CFIFO_3 HW_REGISTER_RW(I2C_BASE_3 + 0x10) + #define I2CDIV_3 HW_REGISTER_RW(I2C_BASE_3 + 0x14) + #define I2CDEL_3 HW_REGISTER_RW(I2C_BASE_3 + 0x18) + #define I2CCLKT_3 HW_REGISTER_RW(I2C_BASE_3 + 0x1C) + + #define I2CC_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x00 ) + #define I2CS_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x04 ) + #define I2CDLEN_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x08 ) + #define I2CA_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x0C ) + #define I2CFIFO_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x10 ) + #define I2CDIV_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x14 ) + #define I2CDEL_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x18 ) + #define I2CCLKT_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x1C ) + + //Note! Remove this eventually. + //Just define the old VCII I2C peripheral + #define I2CC I2CC_0 + #define I2CS I2CS_0 + #define I2CDLEN I2CDLEN_0 + #define I2CA I2CA_0 + #define I2CFIFO I2CFIFO_0 + #define I2CDIV I2CDIV_0 + #define I2CDEL I2CDEL_0 + #define I2CCLKT I2CCLKT_0 + + /*---------------------------------------------------------------------------*/ + /* Performance Monitor */ + #define PRMCS HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x00) + #define PRMCV HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x04) + #define PRMSCC HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x08) + + //--------------------------------------------------------------------------- + // RNG interrupt no longer uses Crypto local interrupt register + // It is connected to interrupt bit 52 : ISRC1_0 bit 52-32=20 (0x0100000) + // Mask has 6 IRQ/reg => floor(52/8)=6 Bits = 16:19 + + #define CRYPTO_ISR ISRC1_0 + #define CRYPTO_ISR_RNG_INT 0x0100000 +// FIXME dunno what this means #define RNG_INT_MASK IMASK6_0 + // for RNG_INT_MASK_ENABLE/DISABLE see rnghw.h + + + /*---------------------------------------------------------------------------*/ + /* Threading unit */ + + /* Registers for the threading unit */ + #define TH0_BASE 0x18011000 + #define TH0_ADDR_MASK 0x0000003F + #define TH1_BASE 0x1A008000 + #define TH1_ADDR_MASK 0x0000003F + + #define TH0CS HW_REGISTER_RW(TH0_BASE + 0x00) + #define TH0CFG HW_REGISTER_RW(TH0_BASE + 0x04) + #define TH0STPC HW_REGISTER_RW(TH0_BASE + 0x08) + #define TH0ITPC HW_REGISTER_RW(TH0_BASE + 0x0C) + #define TH0T0PC HW_REGISTER_RW(TH0_BASE + 0x10) + #define TH0T0UD HW_REGISTER_RW(TH0_BASE + 0x14) + #define TH0T1PC HW_REGISTER_RW(TH0_BASE + 0x18) + #define TH0T1UD HW_REGISTER_RW(TH0_BASE + 0x1C) + #define TH0T2PC HW_REGISTER_RW(TH0_BASE + 0x20) + #define TH0T2UD HW_REGISTER_RW(TH0_BASE + 0x24) + #define TH0T3PC HW_REGISTER_RW(TH0_BASE + 0x28) + #define TH0T3UD HW_REGISTER_RW(TH0_BASE + 0x2C) + + #define TH1CS HW_REGISTER_RW(TH1_BASE + 0x00) + #define TH1CFG HW_REGISTER_RW(TH1_BASE + 0x04) + #define TH1STPC HW_REGISTER_RW(TH1_BASE + 0x08) + #define TH1ITPC HW_REGISTER_RW(TH1_BASE + 0x0C) + #define TH1T0PC HW_REGISTER_RW(TH1_BASE + 0x10) + #define TH1T0UD HW_REGISTER_RW(TH1_BASE + 0x14) + #define TH1T1PC HW_REGISTER_RW(TH1_BASE + 0x18) + #define TH1T1UD HW_REGISTER_RW(TH1_BASE + 0x1C) + #define TH1T2PC HW_REGISTER_RW(TH1_BASE + 0x20) + #define TH1T2UD HW_REGISTER_RW(TH1_BASE + 0x24) + #define TH1T3PC HW_REGISTER_RW(TH1_BASE + 0x28) + #define TH1T3UD HW_REGISTER_RW(TH1_BASE + 0x2C) + + /* Windows Open GL plugin - emulator only */ + #define WOGLPTR HW_REGISTER_RW(0x1820FFFC) + + /* Hardware 3D unit */ + + #define GR_VCACHE_BASE 0x1a00a000 + #define GR_UNIFORM_BASE 0x1a00c000 + + #define GR_VCACHE_ADDR_MASK 0x00001fff + #define GR_VCACHE_SIZE 0x00002000 // in bytes + + #define GR_UNIFORM_ADDR_MASK 0x00000fff + #define GR_UNIFORM_SIZE 0x00001000 // in bytes + + + /* Registers for Vertex Cache Manager */ + #define GR_VCM_BASE 0x1A005C00 + #define GR_VCM_ADDR_MASK 0x0000003f + #define GR_VCM_CI_BASE 0x1A005C80 + #define GR_VCM_CI_ADDR_MASK 0x0000007f + + #define GRMCS HW_REGISTER_RW(GR_VCM_BASE + 0x00) + #define GRMCFG HW_REGISTER_RW(GR_VCM_BASE + 0x04) + #define GRMSVI HW_REGISTER_RW(GR_VCM_BASE + 0x08) + #define GRMSADR HW_REGISTER_RW(GR_VCM_BASE + 0x0C) + #define GRMSCT HW_REGISTER_RW(GR_VCM_BASE + 0x10) + #define GRMOADR HW_REGISTER_RW(GR_VCM_BASE + 0x14) + #define GRMOCT HW_REGISTER_RW(GR_VCM_BASE + 0x18) + #define GRMMCT HW_REGISTER_RW(GR_VCM_BASE + 0x1C) + #define GRMSSI0 HW_REGISTER_RW(GR_VCM_BASE + 0x20) + #define GRMSSI1 HW_REGISTER_RW(GR_VCM_BASE + 0x24) + #define GRMCCT HW_REGISTER_RW(GR_VCM_BASE + 0x28) + + #define GRMCIL0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x00) + #define GRMCIL1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x20) + #define GRMCIH0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x40) + #define GRMCIH1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x60) + + #define GR_VCD_BASE 0x1A005A00 + #define GR_VCD_ADDR_MASK 0x0000007f + + #define GRDCS HW_REGISTER_RW(GR_VCD_BASE + 0x00) + #define GRDCFG HW_REGISTER_RW(GR_VCD_BASE + 0x04) + #define GRDACFG0 HW_REGISTER_RW(GR_VCD_BASE + 0x20) + #define GRDACFG1 HW_REGISTER_RW(GR_VCD_BASE + 0x24) + #define GRDACFG2 HW_REGISTER_RW(GR_VCD_BASE + 0x28) + #define GRDACFG3 HW_REGISTER_RW(GR_VCD_BASE + 0x2C) + #define GRDACFG4 HW_REGISTER_RW(GR_VCD_BASE + 0x30) + #define GRDACFG5 HW_REGISTER_RW(GR_VCD_BASE + 0x34) + #define GRDACFG6 HW_REGISTER_RW(GR_VCD_BASE + 0x38) + #define GRDACFG7 HW_REGISTER_RW(GR_VCD_BASE + 0x3C) + #define GRDAADR0 HW_REGISTER_RW(GR_VCD_BASE + 0x40) + #define GRDAADR1 HW_REGISTER_RW(GR_VCD_BASE + 0x44) + #define GRDAADR2 HW_REGISTER_RW(GR_VCD_BASE + 0x48) + #define GRDAADR3 HW_REGISTER_RW(GR_VCD_BASE + 0x4C) + #define GRDAADR4 HW_REGISTER_RW(GR_VCD_BASE + 0x50) + #define GRDAADR5 HW_REGISTER_RW(GR_VCD_BASE + 0x54) + #define GRDAADR6 HW_REGISTER_RW(GR_VCD_BASE + 0x58) + #define GRDAADR7 HW_REGISTER_RW(GR_VCD_BASE + 0x5C) + + /* Registers for Primitive Setup Engine */ + #define GR_PSE_BASE 0x1A005800 + #define GR_PSE_ADDR_MASK 0x0000007f + + #define GRSCS HW_REGISTER_RW(GR_PSE_BASE + 0x00) + #define GRSCFG HW_REGISTER_RW(GR_PSE_BASE + 0x04) + #define GRSVADR HW_REGISTER_RW(GR_PSE_BASE + 0x08) + #define GRSVFMT HW_REGISTER_RW(GR_PSE_BASE + 0x0C) + #define GRSSP HW_REGISTER_RW(GR_PSE_BASE + 0x10) + #define GRSPADR HW_REGISTER_RW(GR_PSE_BASE + 0x14) + #define GRSPCT HW_REGISTER_RW(GR_PSE_BASE + 0x18) + #define GRSAADR HW_REGISTER_RW(GR_PSE_BASE + 0x1C) + #define GRSACT HW_REGISTER_RW(GR_PSE_BASE + 0x20) + #define GRSDOF HW_REGISTER_RW(GR_PSE_BASE + 0x24) + #define GRSDOU HW_REGISTER_RW(GR_PSE_BASE + 0x28) + #define GRSDMIN HW_REGISTER_RW(GR_PSE_BASE + 0x2C) + #define GRSDMAX HW_REGISTER_RW(GR_PSE_BASE + 0x30) + #define GRSPSZ HW_REGISTER_RW(GR_PSE_BASE + 0x34) + #define GRSLW HW_REGISTER_RW(GR_PSE_BASE + 0x38) + #define GRSFSF HW_REGISTER_RW(GR_PSE_BASE + 0x3C) + #define GRSDZS HW_REGISTER_RW(GR_PSE_BASE + 0x40) + #define GRSHPX HW_REGISTER_RW(GR_PSE_BASE + 0x44) + + /* Debug Registers for Primitive Setup Engine */ + #define GR_PSE_DEBUG_BASE 0x1A005900 + #define GR_PSE_DEBUG_ADDR_MASK 0x00000003 + + #define GRS_DBGE HW_REGISTER_RW(GR_PSE_DEBUG_BASE + 0x00) + + /* Registers for Pixel Pipeline */ + #define GR_PPL_BASE 0x1A005600 + #define GR_PPL_ADDR_MASK 0x0000007F + + #define GRPCS HW_REGISTER_RW(GR_PPL_BASE + 0x00) + #define GRPCFG HW_REGISTER_RW(GR_PPL_BASE + 0x04) + #define GRPCLXY HW_REGISTER_RW(GR_PPL_BASE + 0x08) + #define GRPCLSZ HW_REGISTER_RW(GR_PPL_BASE + 0x0C) + #define GRPVORG HW_REGISTER_RW(GR_PPL_BASE + 0x10) + // gap of 8 bytes + // gap of 16 bytes + // gap of 16 bytes + #define GRPZBCG HW_REGISTER_RW(GR_PPL_BASE + 0x40) + #define GRPSFCG HW_REGISTER_RW(GR_PPL_BASE + 0x44) + #define GRPSBCG HW_REGISTER_RW(GR_PPL_BASE + 0x48) + #define GRPSCC HW_REGISTER_RW(GR_PPL_BASE + 0x4C) + #define GRPBCFG HW_REGISTER_RW(GR_PPL_BASE + 0x50) + #define GRPBCC HW_REGISTER_RW(GR_PPL_BASE + 0x54) + #define GRPCDSM HW_REGISTER_RW(GR_PPL_BASE + 0x58) // xxx dc4 + #define GRPCZSM HW_REGISTER_RW(GR_PPL_BASE + 0x58) + + #define GRPCBS HW_REGISTER_RW(GR_PPL_BASE + 0x5C) + #define GRPABS HW_REGISTER_RW(GR_PPL_BASE + 0x60) + #define GRPFCOL HW_REGISTER_RW(GR_PPL_BASE + 0x64) + + /* Debug Registers for Pixel Pipeline */ + #define GR_PPL_DEBUG_BASE 0x1A005740 + #define GR_PPL_DEBUG_ADDR_MASK 0x0000001F + + #define GRP_FDBGO HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x00) + #define GRP_FDBGB HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x04) + #define GRP_FDBGR HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x08) + #define GRP_FDBGS HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x0C) + #define GRP_SDBG0 HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x10) + + + /* Registers for the Frame Buffer Cache */ + #define GR_FBC_BASE 0x1A005400 + #define GR_FBC_ADDR_MASK 0x0000007F + + #define GRFCS HW_REGISTER_RW(GR_FBC_BASE + 0x00) + #define GRFCFG HW_REGISTER_RW(GR_FBC_BASE + 0x04) + #define GRFTLOC HW_REGISTER_RW(GR_FBC_BASE + 0x08) + #define GRFDIMS HW_REGISTER_RW(GR_FBC_BASE + 0x0C) + #define GRFCCFG HW_REGISTER_RW(GR_FBC_BASE + 0x10) + #define GRFCBA HW_REGISTER_RW(GR_FBC_BASE + 0x14) + #define GRFZCFG HW_REGISTER_RW(GR_FBC_BASE + 0x1C) + #define GRFZBA HW_REGISTER_RW(GR_FBC_BASE + 0x20) + #define GRFZCV HW_REGISTER_RW(GR_FBC_BASE + 0x24) + #define GRFSCV HW_REGISTER_RW(GR_FBC_BASE + 0x28) + #define GRFCMSK HW_REGISTER_RW(GR_FBC_BASE + 0x2C) + #define GRFECFG HW_REGISTER_RW(GR_FBC_BASE + 0x30) + #define GRFEBA HW_REGISTER_RW(GR_FBC_BASE + 0x34) + #define GRFCCV0 HW_REGISTER_RW(GR_FBC_BASE + 0x40) + #define GRFCCV1 HW_REGISTER_RW(GR_FBC_BASE + 0x44) + #define GRFCCV2 HW_REGISTER_RW(GR_FBC_BASE + 0x48) + #define GRFCCV3 HW_REGISTER_RW(GR_FBC_BASE + 0x4C) + #define GRFCCV4 HW_REGISTER_RW(GR_FBC_BASE + 0x50) + #define GRFCCV5 HW_REGISTER_RW(GR_FBC_BASE + 0x54) + #define GRFCCV6 HW_REGISTER_RW(GR_FBC_BASE + 0x58) + #define GRFCCV7 HW_REGISTER_RW(GR_FBC_BASE + 0x5C) + + #define GR_FBC_DEBUG_BASE 0x1A005500 + #define GR_FBC_DEBUG_ADDR_MASK 0x7F + + #define GRFCSTAT HW_REGISTER_RW(GR_FBC_DEBUG_BASE + 0x00) + + /* VPM access via VRF configuration */ + #define GR_VPM_VRFCFG_BASE 0x1A005D00 + #define GR_VPM_VRFCFG_ADDR_MASK 0x00000003 + #define GRVVSTRD HW_REGISTER_RW(GR_VPM_VRFCFG_BASE + 0x00) + + /* Registers for the Texture Unit */ + + /* Mipmap pointer memoies (TU0 & TU1) */ + #define GRTMPM0_BASE 0x1A005E00 + #define GRTMPM1_BASE 0x1A005F00 + + #define GRTMPM_MASK 0xFFFFFF00 + + #define GR_TU_BASE0 0x1A005200 + #define GR_TU_BASE1 0x1A005220 + #define GR_TU_BASE2 0x1A005240 + #define GR_TU_BASE3 0x1A005260 + + #define GR_TU_BASE4 0x1A005280 + #define GR_TU_BASE5 0x1A0052A0 + #define GR_TU_BASE6 0x1A0052C0 + #define GR_TU_BASE7 0x1A0052E0 + + #define GR_TU_DBG_BASE 0x1A005300 + + #define GR_TU_ADDR_MASK 0x000000FF + #define GR_TU_UNIT_MASK 0xFFFFFF1F + + /* Control/Status registers for TU0 & TU1 */ + #define GRTCS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x00) + #define GRTCS1 HW_REGISTER_RW(GR_TU_BASE4 + 0x00) + + /* Common palette for all contexts per texutre unit */ + #define GRTPTBA0 HW_REGISTER_RW(GR_TU_BASE1 + 0x00) + #define GRTPTBA1 HW_REGISTER_RW(GR_TU_BASE5 + 0x00) + + /* 4 sets of context registers for physical texture unit 0 */ + #define GRTCFG0 HW_REGISTER_RW(GR_TU_BASE0 + 0x04) + #define GRTDIM0 HW_REGISTER_RW(GR_TU_BASE0 + 0x08) + #define GRTBCOL0 HW_REGISTER_RW(GR_TU_BASE0 + 0x0C) + #define GRTLBIAS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x1C) + + #define GRTCFG1 HW_REGISTER_RW(GR_TU_BASE1 + 0x04) + #define GRTDIM1 HW_REGISTER_RW(GR_TU_BASE1 + 0x08) + #define GRTBCOL1 HW_REGISTER_RW(GR_TU_BASE1 + 0x0C) + #define GRTLBIAS1 HW_REGISTER_RW(GR_TU_BASE1 + 0x1C) + + #define GRTCFG2 HW_REGISTER_RW(GR_TU_BASE2 + 0x04) + #define GRTDIM2 HW_REGISTER_RW(GR_TU_BASE2 + 0x08) + #define GRTBCOL2 HW_REGISTER_RW(GR_TU_BASE2 + 0x0C) + #define GRTLBIAS2 HW_REGISTER_RW(GR_TU_BASE2 + 0x1C) + + #define GRTCFG3 HW_REGISTER_RW(GR_TU_BASE3 + 0x04) + #define GRTDIM3 HW_REGISTER_RW(GR_TU_BASE3 + 0x08) + #define GRTBCOL3 HW_REGISTER_RW(GR_TU_BASE3 + 0x0C) + #define GRTLBIAS3 HW_REGISTER_RW(GR_TU_BASE3 + 0x1C) + + /* 4 sets of context registers for physical texture unit 1 */ + #define GRTCFG4 HW_REGISTER_RW(GR_TU_BASE4 + 0x04) + #define GRTDIM4 HW_REGISTER_RW(GR_TU_BASE4 + 0x08) + #define GRTBCOL4 HW_REGISTER_RW(GR_TU_BASE4 + 0x0C) + #define GRTLBIAS4 HW_REGISTER_RW(GR_TU_BASE4 + 0x1C) + + #define GRTCFG5 HW_REGISTER_RW(GR_TU_BASE5 + 0x04) + #define GRTDIM5 HW_REGISTER_RW(GR_TU_BASE5 + 0x08) + #define GRTBCOL5 HW_REGISTER_RW(GR_TU_BASE5 + 0x0C) + #define GRTLBIAS5 HW_REGISTER_RW(GR_TU_BASE5 + 0x1C) + + #define GRTCFG6 HW_REGISTER_RW(GR_TU_BASE6 + 0x04) + #define GRTDIM6 HW_REGISTER_RW(GR_TU_BASE6 + 0x08) + #define GRTBCOL6 HW_REGISTER_RW(GR_TU_BASE6 + 0x0C) + #define GRTLBIAS6 HW_REGISTER_RW(GR_TU_BASE6 + 0x1C) + + #define GRTCFG7 HW_REGISTER_RW(GR_TU_BASE7 + 0x04) + #define GRTDIM7 HW_REGISTER_RW(GR_TU_BASE7 + 0x08) + #define GRTBCOL7 HW_REGISTER_RW(GR_TU_BASE7 + 0x0C) + #define GRTLBIAS7 HW_REGISTER_RW(GR_TU_BASE7 + 0x1C) + + /* TU debug registers */ + #define GRTDBG0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x00) + + /* Extra registers per TU for child image support */ + #define GRTCOFF0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x04) + #define GRTCDIM0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x08) + #define GRTCOFF1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x84) + #define GRTCDIM1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x88) + + + /* System Registers */ + #define GR_SYSTEM_BASE 0x1A005000 + + #define GROCS HW_REGISTER_RW(GR_SYSTEM_BASE) + #define GROCFG HW_REGISTER_RW(GR_SYSTEM_BASE + 4) + #define GROIDC HW_REGISTER_RW(GR_SYSTEM_BASE + 8) + + /* System debug register */ + #define GR_SYSTEM_DEBUG_BASE 0x1A005100 + + #define GRODBGA HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x000) + + /* Performance Counters Regs */ + #define GROPCTRC HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x070) + #define GROPCTRE HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x074) + + #define GROPCTR0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x080) + #define GROPCTRS0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x084) + #define GROPCTR1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x088) + #define GROPCTRS1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x08C) + #define GROPCTR2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x090) + #define GROPCTRS2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x094) + #define GROPCTR3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x098) + #define GROPCTRS3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x09C) + #define GROPCTR4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A0) + #define GROPCTRS4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A4) + #define GROPCTR5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A8) + #define GROPCTRS5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0AC) + #define GROPCTR6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B0) + #define GROPCTRS6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B4) + #define GROPCTR7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B8) + #define GROPCTRS7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0BC) + #define GROPCTR8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C0) + #define GROPCTRS8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C4) + #define GROPCTR9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C8) + #define GROPCTRS9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0CC) + #define GROPCTR10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D0) + #define GROPCTRS10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D4) + #define GROPCTR11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D8) + #define GROPCTRS11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0DC) + + /* Performance Counters Defs */ + + #define GROPCTR_FOVCULLEDPRIMS 0x01 + #define GROPCTR_FOVCLIPPEDPRIMS 0x02 + #define GROPCTR_REVCULLEDPRIMS 0x03 + #define GROPCTR_NOFEPIXELPRIMS 0x04 + #define GROPCTR_FEVALIDPRIMS 0x05 + #define GROPCTR_FEZCULLEDQUADS 0x06 + #define GROPCTR_FEVALIDQUADS 0x07 + #define GROPCTR_FEINVALIDPIXELS 0x08 + #define GROPCTR_FEPEZRDY 0x09 + #define GROPCTR_FEPEZIDLE 0x0A + #define GROPCTR_FESTALLPREFETCH 0x0B + #define GROPCTR_FESPMRDY 0x0C + #define GROPCTR_FESPMSTALL 0x0D + #define GROPCTR_TU0_SAME_SET_STALL 0x0E + #define GROPCTR_TU0_SAME_BANK_STALL 0x0F + #define GROPCTR_TU0_AXI_REQ_FIFO_FULL 0x10 + #define GROPCTR_TU0_CACHE_ACCESSES 0x11 + #define GROPCTR_TU0_CACHE_STALLS 0x12 + #define GROPCTR_TU0_CACHE_REQ_STALLS 0x13 + #define GROPCTR_TU0_CACHE_MISSES 0x14 + #define GROPCTR_TU0_CACHE_RCV_WAITS 0x15 + #define GROPCTR_TU1_SAME_SET_STALL 0x16 + #define GROPCTR_TU1_SAME_BANK_STALL 0x17 + #define GROPCTR_TU1_AXI_REQ_FIFO_FULL 0x18 + #define GROPCTR_TU1_CACHE_ACCESSES 0x19 + #define GROPCTR_TU1_CACHE_STALLS 0x1A + #define GROPCTR_TU1_CACHE_REQ_STALLS 0x1B + #define GROPCTR_TU1_CACHE_MISSES 0x1C + #define GROPCTR_TU1_CACHE_RCV_WAITS 0x1D + #define GROPCTR_PBE_FE_STALLS 0x1E + #define GROPCTR_PBE_DEPTH_TEST_FAIL 0x1F + #define GROPCTR_PBE_STCL_TEST_FAIL 0x20 + #define GROPCTR_PBE_DPTH_STCL_PASS 0x21 + #define GROPCTR_FBC_CZ_CLRFLG_FETCHES 0x22 + #define GROPCTR_FBC_CZ_LINE_FLUSHES 0x23 + #define GROPCTR_FBC_CZ_PBE_REQS 0x24 + #define GROPCTR_FBC_CZ_PBE_STALLS 0x25 + #define GROPCTR_FBC_CZ_PBE_MISSES 0x26 + #define GROPCTR_FBC_CZ_PBE_HITS 0x27 + #define GROPCTR_FBC_CZ_FETCH_STALLS 0x28 + #define GROPCTR_FBC_CZ_FE_QUAD_REQS 0x29 + #define GROPCTR_FBC_CZ_FE_LINE_REQS 0x2A + #define GROPCTR_FBC_CZ_FE_UNUSED 0x2B + #define GROPCTR_FBC_CZ_FE_MISSES 0x2C + #define GROPCTR_FBC_CZ_FE_HITS 0x2D + #define GROPCTR_FBC_CZ_FE_DISCARDED 0x2E + #define GROPCTR_FBC_CZ_UM_STALLS 0x2F + #define GROPCTR_FBC_CZ_FETCHES 0x30 + #define GROPCTR_FBC_CZ_EVICTIONS 0x31 + #define GROPCTR_FBC_EZ_CLRFLG_FETCHES 0x32 + #define GROPCTR_FBC_EZ_LINE_FLUSHES 0x33 + #define GROPCTR_FBC_EZ_PBE_REQS 0x34 + #define GROPCTR_FBC_EZ_PBE_STALLS 0x35 + #define GROPCTR_FBC_EZ_PBE_MISSES 0x36 + #define GROPCTR_FBC_EZ_PBE_HITS 0x37 + #define GROPCTR_FBC_EZ_FETCH_STALLS 0x38 + #define GROPCTR_FBC_EZ_FE_REQS 0x39 + #define GROPCTR_FBC_EZ_FE_MISSES 0x3A + #define GROPCTR_FBC_EZ_FE_HITS 0x3B + #define GROPCTR_FBC_EZ_FE_FETCHES 0x3C + #define GROPCTR_FBC_EZ_UM_STALLS 0x3D + #define GROPCTR_FBC_EZ_FETCHES 0x3E + #define GROPCTR_FBC_EZ_EVICTIONS 0x3F + + + + //--------------------------------------------------------------- + // illegal addresses - no hardware anymore + // shouldnt even be in the code FIXME TODO + //--------------------------------------------------------------- + #define I1CACHE_BASE HW_REGISTER_RW(0xffffffff) + #define D1CACHE_BASE HW_REGISTER_RW(0xffffffff) + #define INT_CTL_BASE_ADDR1 HW_REGISTER_RW(0xffffffff) + #define INT_CTL_BASE_ADDR1 HW_REGISTER_RW(0xffffffff) + #define RUN_ARBITER_CTRL_BASE_ADDRESS HW_REGISTER_RW(0xffffffff) + #define SYSTEM_TIMER_BASE1 HW_REGISTER_RW(0xffffffff) + #define VPU1_THREAD_CTRL_BASE_ADDRESS HW_REGISTER_RW(0xffffffff) + #define VPU1_UNIFORM_MEM_BASE_ADDRESS HW_REGISTER_RW(0xffffffff) + #define IC1CS HW_REGISTER_RW(0xffffffff) + #define IC1START HW_REGISTER_RW(0xffffffff) + #define IC1END HW_REGISTER_RW(0xffffffff) + #define DC1CS HW_REGISTER_RW(0xffffffff) + #define DC1START HW_REGISTER_RW(0xffffffff) + #define DC1END HW_REGISTER_RW(0xffffffff) + /* Interrupt Controller for core 1 */ + #define IC_1 HW_REGISTER_RW(0xffffffff) + #define IS_1 HW_REGISTER_RW(0xffffffff) + #define ISRC0_1 HW_REGISTER_RW(0xffffffff) + #define ISRC1_1 HW_REGISTER_RW(0xffffffff) + #define IMASK0_1 HW_REGISTER_RW(0xffffffff) + #define IMASK1_1 HW_REGISTER_RW(0xffffffff) + #define IMASK2_1 HW_REGISTER_RW(0xffffffff) + #define IMASK3_1 HW_REGISTER_RW(0xffffffff) + #define IMASK4_1 HW_REGISTER_RW(0xffffffff) + #define IMASK5_1 HW_REGISTER_RW(0xffffffff) + #define IMASK6_1 HW_REGISTER_RW(0xffffffff) + #define IMASK7_1 HW_REGISTER_RW(0xffffffff) + #define IMASKx_1( x ) HW_REGISTER_RW(0xffffffff) + #define IVADDR_1 HW_REGISTER_RW(0xffffffff) + #define IWAKEUP_1 HW_REGISTER_RW(0xffffffff) + #define IPROFILE_1 HW_REGISTER_RW(0xffffffff) + #define IFORCE0_1 HW_REGISTER_RW(0xffffffff) + #define IFORCE1_1 HW_REGISTER_RW(0xffffffff) + //The 2nd core's timer block + #define STCS_1 HW_REGISTER_RW(0xffffffff) + #define STC_1 HW_REGISTER_RO(0xffffffff) + #define STCLO_1 HW_REGISTER_RO(0xffffffff) + #define STCHI_1 HW_REGISTER_RO(0xffffffff) + #define STC0_1 HW_REGISTER_RW(0xffffffff) + #define STC1_1 HW_REGISTER_RW(0xffffffff) + #define STC2_1 HW_REGISTER_RW(0xffffffff) + #define STC3_1 HW_REGISTER_RW(0xffffffff) + +#endif diff --git a/bcm2708_chip/rng.h b/bcm2708_chip/rng.h new file mode 100755 index 0000000..9e806d5 --- /dev/null +++ b/bcm2708_chip/rng.h @@ -0,0 +1,18 @@ +// This file was generated by the create_regs script +#define RNG_BASE 0x7e104000 +#define RNG_APB_ID 0x20726e67 +#define RNG_CTRL HW_REGISTER_RW( 0x7e104000 ) + #define RNG_CTRL_MASK 0xffffffff + #define RNG_CTRL_WIDTH 32 +#define RNG_STATUS HW_REGISTER_RW( 0x7e104004 ) + #define RNG_STATUS_MASK 0xffffffff + #define RNG_STATUS_WIDTH 32 +#define RNG_DATA HW_REGISTER_RW( 0x7e104008 ) + #define RNG_DATA_MASK 0xffffffff + #define RNG_DATA_WIDTH 32 +#define RNG_FF_THRESHOLD HW_REGISTER_RW( 0x7e10400c ) + #define RNG_FF_THRESHOLD_MASK 0xffffffff + #define RNG_FF_THRESHOLD_WIDTH 32 +#define RNG_INT_MASK HW_REGISTER_RW( 0x7e104010 ) + #define RNG_INT_MASK_MASK 0xffffffff + #define RNG_INT_MASK_WIDTH 32 diff --git a/bcm2708_chip/rng_a0.h b/bcm2708_chip/rng_a0.h new file mode 100755 index 0000000..8fac77c --- /dev/null +++ b/bcm2708_chip/rng_a0.h @@ -0,0 +1,43 @@ +#ifndef __BCM2708A0__ + +// This file was generated by the create_regs script +#define RNG_BASE 0x7e104000 +#define RNG_APB_ID 0x20726e67 +#define RNG_CTRL HW_REGISTER_RW( 0x7e104000 ) + #define RNG_CTRL_MASK 0xffffffff + #define RNG_CTRL_WIDTH 32 +#define RNG_STATUS HW_REGISTER_RW( 0x7e104004 ) + #define RNG_STATUS_MASK 0xffffffff + #define RNG_STATUS_WIDTH 32 +#define RNG_DATA HW_REGISTER_RW( 0x7e104008 ) + #define RNG_DATA_MASK 0xffffffff + #define RNG_DATA_WIDTH 32 +#define RNG_FF_THRESHOLD HW_REGISTER_RW( 0x7e10400c ) + #define RNG_FF_THRESHOLD_MASK 0xffffffff + #define RNG_FF_THRESHOLD_WIDTH 32 +#define RNG_INT_MASK HW_REGISTER_RW( 0x7e104010 ) + #define RNG_INT_MASK_MASK 0xffffffff + #define RNG_INT_MASK_WIDTH 32 + +#else + +// This file was generated by the create_regs script +#define RNG_BASE 0x7ee03000 +#define RNG_APB_ID 0x20726e67 +#define RNG_CTRL HW_REGISTER_RW( 0x7ee03000 ) + #define RNG_CTRL_MASK 0xffffffff + #define RNG_CTRL_WIDTH 32 +#define RNG_STATUS HW_REGISTER_RW( 0x7ee03004 ) + #define RNG_STATUS_MASK 0xffffffff + #define RNG_STATUS_WIDTH 32 +#define RNG_DATA HW_REGISTER_RW( 0x7ee03008 ) + #define RNG_DATA_MASK 0xffffffff + #define RNG_DATA_WIDTH 32 +#define RNG_FF_THRESHOLD HW_REGISTER_RW( 0x7ee0300c ) + #define RNG_FF_THRESHOLD_MASK 0xffffffff + #define RNG_FF_THRESHOLD_WIDTH 32 +#define RNG_INT_MASK HW_REGISTER_RW( 0x7ee03010 ) + #define RNG_INT_MASK_MASK 0xffffffff + #define RNG_INT_MASK_WIDTH 32 + +#endif diff --git a/bcm2708_chip/rnghw.h b/bcm2708_chip/rnghw.h new file mode 100755 index 0000000..bd4585c --- /dev/null +++ b/bcm2708_chip/rnghw.h @@ -0,0 +1,44 @@ +/*============================================================================= +Copyright (c) 2007 Broadcom Europe Limited. All rights reserved. + +Project : BCM2707 +Module : RNG hardware header +File : $RCSfile: rnghw.h,v $ +Revision : $Revision: 1.2 $ + +FILE DESCRIPTION +Definition of bits within RNG hardware registers. +=============================================================================*/ + + + +#ifndef RNGHW_H +#define RNGHW_H + +#define RNG_READFIELD(_w,_f) (((unsigned long)(_w) / _f) & (_f##_MASK)) + +enum +{ + RNG_CTRL_RBG_2X = (1 << 1), + RNG_CTRL_RBG_EN = (1 << 0), + + RNG_STATUS_WARM_CNT = (1 << 0), + RNG_STATUS_WARM_CNT_MASK = 0xfffff, + RNG_STATUS_VAL = (1 << 24), + RNG_STATUS_VAL_MASK = 0xff, + + RNG_FF_THRESHOLD_MAX = 0x04, + +// BCM2707_B0: +// RNG interrupt no longer uses Crypto local interrupt register +// It is connected to interrupt bit 52 : ISRC1_0 bit 52-32=20 (0x0100000) +// Mask has 6 IRQ/reg => floor(52/8)=6 Bits = 16:19 + + RNG_INT_MASK_ENABLE = (1 << 16), + RNG_INT_MASK_DISABLE = (0 << 16), + + RNG_SIMCTRL_DEBUG = (1 << 0), + RNG_SIMCTRL_SECURE = (1 << 1) +}; + +#endif diff --git a/bcm2708_chip/sdc_addr_front.h b/bcm2708_chip/sdc_addr_front.h new file mode 100755 index 0000000..e70aa84 --- /dev/null +++ b/bcm2708_chip/sdc_addr_front.h @@ -0,0 +1,39 @@ +// This file was generated by the create_regs script +#define APHY_CSR_BASE 0x7ee06000 +#define APHY_CSR_ADDR_REV_ID HW_REGISTER_RW( 0x7ee06000 ) +#define APHY_CSR_GLBL_ADDR_DLL_RESET HW_REGISTER_RW( 0x7ee06004 ) +#define APHY_CSR_GLBL_ADDR_DLL_RECAL HW_REGISTER_RW( 0x7ee06008 ) +#define APHY_CSR_GLBL_ADDR_DLL_CNTRL HW_REGISTER_RW( 0x7ee0600c ) +#define APHY_CSR_GLBL_ADDR_DLL_PH_LD_VAL HW_REGISTER_RW( 0x7ee06010 ) +#define APHY_CSR_ADDR_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee06014 ) +#define APHY_CSR_ADDR_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee06018 ) +#define APHY_CSR_GLBL_ADR_MSTR_DLL_BYPEN HW_REGISTER_RW( 0x7ee0601c ) +#define APHY_CSR_GLBL_ADR_DLL_LOCK_STAT HW_REGISTER_RW( 0x7ee06020 ) +#define APHY_CSR_DDR_PLL_GLOBAL_RESET HW_REGISTER_RW( 0x7ee06024 ) +#define APHY_CSR_DDR_PLL_POST_DIV_RESET HW_REGISTER_RW( 0x7ee06028 ) +#define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 HW_REGISTER_RW( 0x7ee0602c ) +#define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 HW_REGISTER_RW( 0x7ee06030 ) +#define APHY_CSR_DDR_PLL_MDIV_VALUE HW_REGISTER_RW( 0x7ee06034 ) +#define APHY_CSR_DDR_PLL_CONFIG_CNTRL HW_REGISTER_RW( 0x7ee06038 ) +#define APHY_CSR_DDR_PLL_MISC_CNTRL HW_REGISTER_RW( 0x7ee0603c ) +#define APHY_CSR_DDR_PLL_SPRDSPECT_CTRL0 HW_REGISTER_RW( 0x7ee06040 ) +#define APHY_CSR_DDR_PLL_SPRDSPECT_CTRL1 HW_REGISTER_RW( 0x7ee06044 ) +#define APHY_CSR_DDR_PLL_LOCK_STATUS HW_REGISTER_RW( 0x7ee06048 ) +#define APHY_CSR_DDR_PLL_HOLD_CH HW_REGISTER_RW( 0x7ee0604c ) +#define APHY_CSR_DDR_PLL_ENABLE_CH HW_REGISTER_RW( 0x7ee06050 ) +#define APHY_CSR_DDR_PLL_BYPASS HW_REGISTER_RW( 0x7ee06054 ) +#define APHY_CSR_DDR_PLL_PWRDWN HW_REGISTER_RW( 0x7ee06058 ) +#define APHY_CSR_DDR_PLL_CH0_DESKEW_CTRL HW_REGISTER_RW( 0x7ee0605c ) +#define APHY_CSR_DDR_PLL_CH1_DESKEW_CTRL HW_REGISTER_RW( 0x7ee06060 ) +#define APHY_CSR_DDR_PLL_DESKEW_STATUS HW_REGISTER_RW( 0x7ee06064 ) +#define APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL HW_REGISTER_RW( 0x7ee06068 ) +#define APHY_CSR_ADDR_PAD_MISC_CTRL HW_REGISTER_RW( 0x7ee0606c ) +#define APHY_CSR_ADDR_PVT_COMP_CTRL HW_REGISTER_RW( 0x7ee06070 ) +#define APHY_CSR_ADDR_PVT_COMP_OVRD_CTRL HW_REGISTER_RW( 0x7ee06074 ) +#define APHY_CSR_ADDR_PVT_COMP_STATUS HW_REGISTER_RW( 0x7ee06078 ) +#define APHY_CSR_ADDR_PVT_COMP_DEBUG HW_REGISTER_RW( 0x7ee0607c ) +#define APHY_CSR_PHY_BIST_CNTRL_SPR HW_REGISTER_RW( 0x7ee06080 ) +#define APHY_CSR_PHY_BIST_CA_CRC_SPR HW_REGISTER_RW( 0x7ee06084 ) +#define APHY_CSR_ADDR_SPR0_RW HW_REGISTER_RW( 0x7ee06088 ) +#define APHY_CSR_ADDR_SPR1_RO HW_REGISTER_RW( 0x7ee0608c ) +#define APHY_CSR_ADDR_SPR_RO HW_REGISTER_RW( 0x7ee06090 ) diff --git a/bcm2708_chip/sdc_ctrl.h b/bcm2708_chip/sdc_ctrl.h new file mode 100755 index 0000000..dab2212 --- /dev/null +++ b/bcm2708_chip/sdc_ctrl.h @@ -0,0 +1,1316 @@ +// This file was generated by the create_regs script +#define SD_BASE 0x7ee00000 +#define SD_APB_ID 0x5344434f +#define SD_CS HW_REGISTER_RW( 0x7ee00000 ) + #define SD_CS_MASK 0x01ffffff + #define SD_CS_WIDTH 25 + #define SD_CS_STALLING_BITS 24:24 + #define SD_CS_STALLING_SET 0x01000000 + #define SD_CS_STALLING_CLR 0xfeffffff + #define SD_CS_STALLING_MSB 24 + #define SD_CS_STALLING_LSB 24 + #define SD_CS_STALLING_RESET 0x0 + #define SD_CS_EXCEPTION_BITS 23:23 + #define SD_CS_EXCEPTION_SET 0x00800000 + #define SD_CS_EXCEPTION_CLR 0xff7fffff + #define SD_CS_EXCEPTION_MSB 23 + #define SD_CS_EXCEPTION_LSB 23 + #define SD_CS_EXCEPTION_RESET 0x0 + #define SD_CS_ASHDN_T_BITS 22:19 + #define SD_CS_ASHDN_T_SET 0x00780000 + #define SD_CS_ASHDN_T_CLR 0xff87ffff + #define SD_CS_ASHDN_T_MSB 22 + #define SD_CS_ASHDN_T_LSB 19 + #define SD_CS_ASHDN_T_RESET 0xf + #define SD_CS_DEL_KEEP_BITS 18:18 + #define SD_CS_DEL_KEEP_SET 0x00040000 + #define SD_CS_DEL_KEEP_CLR 0xfffbffff + #define SD_CS_DEL_KEEP_MSB 18 + #define SD_CS_DEL_KEEP_LSB 18 + #define SD_CS_DEL_KEEP_RESET 0x0 + #define SD_CS_ASHDNE_BITS 17:17 + #define SD_CS_ASHDNE_SET 0x00020000 + #define SD_CS_ASHDNE_CLR 0xfffdffff + #define SD_CS_ASHDNE_MSB 17 + #define SD_CS_ASHDNE_LSB 17 + #define SD_CS_ASHDNE_RESET 0x0 + #define SD_CS_RDH_IDLE_BITS 16:16 + #define SD_CS_RDH_IDLE_SET 0x00010000 + #define SD_CS_RDH_IDLE_CLR 0xfffeffff + #define SD_CS_RDH_IDLE_MSB 16 + #define SD_CS_RDH_IDLE_LSB 16 + #define SD_CS_RDH_IDLE_RESET 0x0 + #define SD_CS_SDUP_BITS 15:15 + #define SD_CS_SDUP_SET 0x00008000 + #define SD_CS_SDUP_CLR 0xffff7fff + #define SD_CS_SDUP_MSB 15 + #define SD_CS_SDUP_LSB 15 + #define SD_CS_SDUP_RESET 0x0 + #define SD_CS_CLKOFF_BITS 14:14 + #define SD_CS_CLKOFF_SET 0x00004000 + #define SD_CS_CLKOFF_CLR 0xffffbfff + #define SD_CS_CLKOFF_MSB 14 + #define SD_CS_CLKOFF_LSB 14 + #define SD_CS_CLKOFF_RESET 0x1 + #define SD_CS_DLLCAL_BITS 11:10 + #define SD_CS_DLLCAL_SET 0x00000c00 + #define SD_CS_DLLCAL_CLR 0xfffff3ff + #define SD_CS_DLLCAL_MSB 11 + #define SD_CS_DLLCAL_LSB 10 + #define SD_CS_DLLCAL_RESET 0x0 + #define SD_CS_IDLE_BITS 9:9 + #define SD_CS_IDLE_SET 0x00000200 + #define SD_CS_IDLE_CLR 0xfffffdff + #define SD_CS_IDLE_MSB 9 + #define SD_CS_IDLE_LSB 9 + #define SD_CS_IDLE_RESET 0x0 + #define SD_CS_SREF2RUN_BITS 8:8 + #define SD_CS_SREF2RUN_SET 0x00000100 + #define SD_CS_SREF2RUN_CLR 0xfffffeff + #define SD_CS_SREF2RUN_MSB 8 + #define SD_CS_SREF2RUN_LSB 8 + #define SD_CS_SREF2RUN_RESET 0x0 + #define SD_CS_STOP_BITS 7:7 + #define SD_CS_STOP_SET 0x00000080 + #define SD_CS_STOP_CLR 0xffffff7f + #define SD_CS_STOP_MSB 7 + #define SD_CS_STOP_LSB 7 + #define SD_CS_STOP_RESET 0x0 + #define SD_CS_STATEN_BITS 6:6 + #define SD_CS_STATEN_SET 0x00000040 + #define SD_CS_STATEN_CLR 0xffffffbf + #define SD_CS_STATEN_MSB 6 + #define SD_CS_STATEN_LSB 6 + #define SD_CS_STATEN_RESET 0x0 + #define SD_CS_SDTST_BITS 5:5 + #define SD_CS_SDTST_SET 0x00000020 + #define SD_CS_SDTST_CLR 0xffffffdf + #define SD_CS_SDTST_MSB 5 + #define SD_CS_SDTST_LSB 5 + #define SD_CS_SDTST_RESET 0x0 + #define SD_CS_PUSKIP_BITS 4:4 + #define SD_CS_PUSKIP_SET 0x00000010 + #define SD_CS_PUSKIP_CLR 0xffffffef + #define SD_CS_PUSKIP_MSB 4 + #define SD_CS_PUSKIP_LSB 4 + #define SD_CS_PUSKIP_RESET 0x0 + #define SD_CS_STBY_BITS 3:3 + #define SD_CS_STBY_SET 0x00000008 + #define SD_CS_STBY_CLR 0xfffffff7 + #define SD_CS_STBY_MSB 3 + #define SD_CS_STBY_LSB 3 + #define SD_CS_STBY_RESET 0x0 + #define SD_CS_DPD_BITS 2:2 + #define SD_CS_DPD_SET 0x00000004 + #define SD_CS_DPD_CLR 0xfffffffb + #define SD_CS_DPD_MSB 2 + #define SD_CS_DPD_LSB 2 + #define SD_CS_DPD_RESET 0x0 + #define SD_CS_EN_BITS 1:1 + #define SD_CS_EN_SET 0x00000002 + #define SD_CS_EN_CLR 0xfffffffd + #define SD_CS_EN_MSB 1 + #define SD_CS_EN_LSB 1 + #define SD_CS_EN_RESET 0x0 + #define SD_CS_RESTRT_BITS 0:0 + #define SD_CS_RESTRT_SET 0x00000001 + #define SD_CS_RESTRT_CLR 0xfffffffe + #define SD_CS_RESTRT_MSB 0 + #define SD_CS_RESTRT_LSB 0 + #define SD_CS_RESTRT_RESET 0x0 +#define SD_SA HW_REGISTER_RW( 0x7ee00004 ) + #define SD_SA_MASK 0xffffffff + #define SD_SA_WIDTH 32 + #define SD_SA_RFSH_T_BITS 31:16 + #define SD_SA_RFSH_T_SET 0xffff0000 + #define SD_SA_RFSH_T_CLR 0x0000ffff + #define SD_SA_RFSH_T_MSB 31 + #define SD_SA_RFSH_T_LSB 16 + #define SD_SA_RFSH_T_RESET 0x30c + #define SD_SA_PGEHLD_IDL_BITS 15:15 + #define SD_SA_PGEHLD_IDL_SET 0x00008000 + #define SD_SA_PGEHLD_IDL_CLR 0xffff7fff + #define SD_SA_PGEHLD_IDL_MSB 15 + #define SD_SA_PGEHLD_IDL_LSB 15 + #define SD_SA_PGEHLD_IDL_RESET 0x0 + #define SD_SA_PGEHLDE_BITS 8:8 + #define SD_SA_PGEHLDE_SET 0x00000100 + #define SD_SA_PGEHLDE_CLR 0xfffffeff + #define SD_SA_PGEHLDE_MSB 8 + #define SD_SA_PGEHLDE_LSB 8 + #define SD_SA_PGEHLDE_RESET 0x0 + #define SD_SA_CLKSTOP_BITS 7:7 + #define SD_SA_CLKSTOP_SET 0x00000080 + #define SD_SA_CLKSTOP_CLR 0xffffff7f + #define SD_SA_CLKSTOP_MSB 7 + #define SD_SA_CLKSTOP_LSB 7 + #define SD_SA_CLKSTOP_RESET 0x1 + #define SD_SA_POWSAVE_BITS 0:0 + #define SD_SA_POWSAVE_SET 0x00000001 + #define SD_SA_POWSAVE_CLR 0xfffffffe + #define SD_SA_POWSAVE_MSB 0 + #define SD_SA_POWSAVE_LSB 0 + #define SD_SA_POWSAVE_RESET 0x0 +#define SD_SB HW_REGISTER_RW( 0x7ee00008 ) + #define SD_SB_MASK 0xfff001ff + #define SD_SB_WIDTH 32 + #define SD_SB_STBY_T_BITS 31:20 + #define SD_SB_STBY_T_SET 0xfff00000 + #define SD_SB_STBY_T_CLR 0x000fffff + #define SD_SB_STBY_T_MSB 31 + #define SD_SB_STBY_T_LSB 20 + #define SD_SB_STBY_T_RESET 0x0 + #define SD_SB_INHIBIT_LA_BITS 8:8 + #define SD_SB_INHIBIT_LA_SET 0x00000100 + #define SD_SB_INHIBIT_LA_CLR 0xfffffeff + #define SD_SB_INHIBIT_LA_MSB 8 + #define SD_SB_INHIBIT_LA_LSB 8 + #define SD_SB_INHIBIT_LA_RESET 0x0 + #define SD_SB_REORDER_BITS 7:7 + #define SD_SB_REORDER_SET 0x00000080 + #define SD_SB_REORDER_CLR 0xffffff7f + #define SD_SB_REORDER_MSB 7 + #define SD_SB_REORDER_LSB 7 + #define SD_SB_REORDER_RESET 0x0 + #define SD_SB_BANKLOW_BITS 6:5 + #define SD_SB_BANKLOW_SET 0x00000060 + #define SD_SB_BANKLOW_CLR 0xffffff9f + #define SD_SB_BANKLOW_MSB 6 + #define SD_SB_BANKLOW_LSB 5 + #define SD_SB_BANKLOW_RESET 0x0 + #define SD_SB_EIGHTBANK_BITS 4:4 + #define SD_SB_EIGHTBANK_SET 0x00000010 + #define SD_SB_EIGHTBANK_CLR 0xffffffef + #define SD_SB_EIGHTBANK_MSB 4 + #define SD_SB_EIGHTBANK_LSB 4 + #define SD_SB_EIGHTBANK_RESET 0x0 + #define SD_SB_ROWBITS_BITS 3:2 + #define SD_SB_ROWBITS_SET 0x0000000c + #define SD_SB_ROWBITS_CLR 0xfffffff3 + #define SD_SB_ROWBITS_MSB 3 + #define SD_SB_ROWBITS_LSB 2 + #define SD_SB_ROWBITS_RESET 0x1 + #define SD_SB_COLBITS_BITS 1:0 + #define SD_SB_COLBITS_SET 0x00000003 + #define SD_SB_COLBITS_CLR 0xfffffffc + #define SD_SB_COLBITS_MSB 1 + #define SD_SB_COLBITS_LSB 0 + #define SD_SB_COLBITS_RESET 0x1 +#define SD_SC HW_REGISTER_RW( 0x7ee0000c ) + #define SD_SC_MASK 0x7ff00f77 + #define SD_SC_WIDTH 31 + #define SD_SC_T_RFC_BITS 30:24 + #define SD_SC_T_RFC_SET 0x7f000000 + #define SD_SC_T_RFC_CLR 0x80ffffff + #define SD_SC_T_RFC_MSB 30 + #define SD_SC_T_RFC_LSB 24 + #define SD_SC_T_RFC_RESET 0x1e + #define SD_SC_T_RRD_BITS 23:20 + #define SD_SC_T_RRD_SET 0x00f00000 + #define SD_SC_T_RRD_CLR 0xff0fffff + #define SD_SC_T_RRD_MSB 23 + #define SD_SC_T_RRD_LSB 20 + #define SD_SC_T_RRD_RESET 0x4 + #define SD_SC_T_WR_BITS 11:8 + #define SD_SC_T_WR_SET 0x00000f00 + #define SD_SC_T_WR_CLR 0xfffff0ff + #define SD_SC_T_WR_MSB 11 + #define SD_SC_T_WR_LSB 8 + #define SD_SC_T_WR_RESET 0x6 + #define SD_SC_T_WTR_BITS 6:4 + #define SD_SC_T_WTR_SET 0x00000070 + #define SD_SC_T_WTR_CLR 0xffffff8f + #define SD_SC_T_WTR_MSB 6 + #define SD_SC_T_WTR_LSB 4 + #define SD_SC_T_WTR_RESET 0x3 + #define SD_SC_WL_BITS 2:0 + #define SD_SC_WL_SET 0x00000007 + #define SD_SC_WL_CLR 0xfffffff8 + #define SD_SC_WL_MSB 2 + #define SD_SC_WL_LSB 0 + #define SD_SC_WL_RESET 0x2 +#define SD_SD HW_REGISTER_RW( 0x7ee00094 ) + #define SD_SD_MASK 0xf1f71fff + #define SD_SD_WIDTH 32 + #define SD_SD_T_RPab_BITS 31:28 + #define SD_SD_T_RPab_SET 0xf0000000 + #define SD_SD_T_RPab_CLR 0x0fffffff + #define SD_SD_T_RPab_MSB 31 + #define SD_SD_T_RPab_LSB 28 + #define SD_SD_T_RPab_RESET 0xa + #define SD_SD_T_RC_BITS 24:20 + #define SD_SD_T_RC_SET 0x01f00000 + #define SD_SD_T_RC_CLR 0xfe0fffff + #define SD_SD_T_RC_MSB 24 + #define SD_SD_T_RC_LSB 20 + #define SD_SD_T_RC_RESET 0x14 + #define SD_SD_T_XP_BITS 18:16 + #define SD_SD_T_XP_SET 0x00070000 + #define SD_SD_T_XP_CLR 0xfff8ffff + #define SD_SD_T_XP_MSB 18 + #define SD_SD_T_XP_LSB 16 + #define SD_SD_T_XP_RESET 0x2 + #define SD_SD_T_RAS_BITS 12:8 + #define SD_SD_T_RAS_SET 0x00001f00 + #define SD_SD_T_RAS_CLR 0xffffe0ff + #define SD_SD_T_RAS_MSB 12 + #define SD_SD_T_RAS_LSB 8 + #define SD_SD_T_RAS_RESET 0xe + #define SD_SD_T_RPpb_BITS 7:4 + #define SD_SD_T_RPpb_SET 0x000000f0 + #define SD_SD_T_RPpb_CLR 0xffffff0f + #define SD_SD_T_RPpb_MSB 7 + #define SD_SD_T_RPpb_LSB 4 + #define SD_SD_T_RPpb_RESET 0x8 + #define SD_SD_T_RCD_BITS 3:0 + #define SD_SD_T_RCD_SET 0x0000000f + #define SD_SD_T_RCD_CLR 0xfffffff0 + #define SD_SD_T_RCD_MSB 3 + #define SD_SD_T_RCD_LSB 0 + #define SD_SD_T_RCD_RESET 0x8 +#define SD_SE HW_REGISTER_RW( 0x7ee00098 ) + #define SD_SE_MASK 0x13f3f73f + #define SD_SE_WIDTH 29 + #define SD_SE_RL_EN_BITS 28:28 + #define SD_SE_RL_EN_SET 0x10000000 + #define SD_SE_RL_EN_CLR 0xefffffff + #define SD_SE_RL_EN_MSB 28 + #define SD_SE_RL_EN_LSB 28 + #define SD_SE_RL_EN_RESET 0x0 + #define SD_SE_RL_BITS 25:20 + #define SD_SE_RL_SET 0x03f00000 + #define SD_SE_RL_CLR 0xfc0fffff + #define SD_SE_RL_MSB 25 + #define SD_SE_RL_LSB 20 + #define SD_SE_RL_RESET 0x8 + #define SD_SE_T_FAW_BITS 17:12 + #define SD_SE_T_FAW_SET 0x0003f000 + #define SD_SE_T_FAW_CLR 0xfffc0fff + #define SD_SE_T_FAW_MSB 17 + #define SD_SE_T_FAW_LSB 12 + #define SD_SE_T_FAW_RESET 0x19 + #define SD_SE_T_RTP_BITS 10:8 + #define SD_SE_T_RTP_SET 0x00000700 + #define SD_SE_T_RTP_CLR 0xfffff8ff + #define SD_SE_T_RTP_MSB 10 + #define SD_SE_T_RTP_LSB 8 + #define SD_SE_T_RTP_RESET 0x3 + #define SD_SE_T_XSR_BITS 5:0 + #define SD_SE_T_XSR_SET 0x0000003f + #define SD_SE_T_XSR_CLR 0xffffffc0 + #define SD_SE_T_XSR_MSB 5 + #define SD_SE_T_XSR_LSB 0 + #define SD_SE_T_XSR_RESET 0x28 +#define SD_SF HW_REGISTER_RW( 0x7ee000b4 ) + #define SD_SF_MASK 0x3fffffff + #define SD_SF_WIDTH 30 + #define SD_SF_PHYHOLD_BITS 29:29 + #define SD_SF_PHYHOLD_SET 0x20000000 + #define SD_SF_PHYHOLD_CLR 0xdfffffff + #define SD_SF_PHYHOLD_MSB 29 + #define SD_SF_PHYHOLD_LSB 29 + #define SD_SF_PHYHOLD_RESET 0x0 + #define SD_SF_PGEHLD_T_BITS 28:19 + #define SD_SF_PGEHLD_T_SET 0x1ff80000 + #define SD_SF_PGEHLD_T_CLR 0xe007ffff + #define SD_SF_PGEHLD_T_MSB 28 + #define SD_SF_PGEHLD_T_LSB 19 + #define SD_SF_PGEHLD_T_RESET 0x100 + #define SD_SF_POWSAV_T_BITS 18:9 + #define SD_SF_POWSAV_T_SET 0x0007fe00 + #define SD_SF_POWSAV_T_CLR 0xfff801ff + #define SD_SF_POWSAV_T_MSB 18 + #define SD_SF_POWSAV_T_LSB 9 + #define SD_SF_POWSAV_T_RESET 0x040 + #define SD_SF_MDLL_CAL_BITS 8:0 + #define SD_SF_MDLL_CAL_SET 0x000001ff + #define SD_SF_MDLL_CAL_CLR 0xfffffe00 + #define SD_SF_MDLL_CAL_MSB 8 + #define SD_SF_MDLL_CAL_LSB 0 + #define SD_SF_MDLL_CAL_RESET 0x12c +#define SD_MR HW_REGISTER_RW( 0x7ee00090 ) + #define SD_MR_MASK 0xf0ffffff + #define SD_MR_WIDTH 32 + #define SD_MR_DONE_BITS 31:31 + #define SD_MR_DONE_SET 0x80000000 + #define SD_MR_DONE_CLR 0x7fffffff + #define SD_MR_DONE_MSB 31 + #define SD_MR_DONE_LSB 31 + #define SD_MR_DONE_RESET 0x1 + #define SD_MR_TIMEOUT_BITS 30:30 + #define SD_MR_TIMEOUT_SET 0x40000000 + #define SD_MR_TIMEOUT_CLR 0xbfffffff + #define SD_MR_TIMEOUT_MSB 30 + #define SD_MR_TIMEOUT_LSB 30 + #define SD_MR_TIMEOUT_RESET 0x0 + #define SD_MR_HI_Z_BITS 29:29 + #define SD_MR_HI_Z_SET 0x20000000 + #define SD_MR_HI_Z_CLR 0xdfffffff + #define SD_MR_HI_Z_MSB 29 + #define SD_MR_HI_Z_LSB 29 + #define SD_MR_HI_Z_RESET 0x0 + #define SD_MR_RW_BITS 28:28 + #define SD_MR_RW_SET 0x10000000 + #define SD_MR_RW_CLR 0xefffffff + #define SD_MR_RW_MSB 28 + #define SD_MR_RW_LSB 28 + #define SD_MR_RW_RESET 0x0 + #define SD_MR_RDATA_BITS 23:16 + #define SD_MR_RDATA_SET 0x00ff0000 + #define SD_MR_RDATA_CLR 0xff00ffff + #define SD_MR_RDATA_MSB 23 + #define SD_MR_RDATA_LSB 16 + #define SD_MR_RDATA_RESET 0x0 + #define SD_MR_WDATA_BITS 15:8 + #define SD_MR_WDATA_SET 0x0000ff00 + #define SD_MR_WDATA_CLR 0xffff00ff + #define SD_MR_WDATA_MSB 15 + #define SD_MR_WDATA_LSB 8 + #define SD_MR_WDATA_RESET 0x0 + #define SD_MR_ADDR_BITS 7:0 + #define SD_MR_ADDR_SET 0x000000ff + #define SD_MR_ADDR_CLR 0xffffff00 + #define SD_MR_ADDR_MSB 7 + #define SD_MR_ADDR_LSB 0 + #define SD_MR_ADDR_RESET 0x0 +#define SD_MRT HW_REGISTER_RW( 0x7ee00064 ) + #define SD_MRT_MASK 0x000001ff + #define SD_MRT_WIDTH 9 + #define SD_MRT_T_MRW_BITS 8:0 + #define SD_MRT_T_MRW_SET 0x000001ff + #define SD_MRT_T_MRW_CLR 0xfffffe00 + #define SD_MRT_T_MRW_MSB 8 + #define SD_MRT_T_MRW_LSB 0 + #define SD_MRT_T_MRW_RESET 0x4 +#define SD_PT1 HW_REGISTER_RW( 0x7ee00014 ) + #define SD_PT1_MASK 0x0fffffff + #define SD_PT1_WIDTH 28 + #define SD_PT1_T_INIT3_BITS 27:8 + #define SD_PT1_T_INIT3_SET 0x0fffff00 + #define SD_PT1_T_INIT3_CLR 0xf00000ff + #define SD_PT1_T_INIT3_MSB 27 + #define SD_PT1_T_INIT3_LSB 8 + #define SD_PT1_T_INIT3_RESET 0x13880 + #define SD_PT1_T_INIT1_BITS 7:0 + #define SD_PT1_T_INIT1_SET 0x000000ff + #define SD_PT1_T_INIT1_CLR 0xffffff00 + #define SD_PT1_T_INIT1_MSB 7 + #define SD_PT1_T_INIT1_LSB 0 + #define SD_PT1_T_INIT1_RESET 0x28 +#define SD_PT2 HW_REGISTER_RW( 0x7ee00010 ) + #define SD_PT2_MASK 0xffffffff + #define SD_PT2_WIDTH 32 + #define SD_PT2_T_INIT5_BITS 15:0 + #define SD_PT2_T_INIT5_SET 0x0000ffff + #define SD_PT2_T_INIT5_CLR 0xffff0000 + #define SD_PT2_T_INIT5_MSB 15 + #define SD_PT2_T_INIT5_LSB 0 + #define SD_PT2_T_INIT5_RESET 0xfa0 +#define SD_IDL HW_REGISTER_RW( 0x7ee00018 ) + #define SD_IDL_MASK 0x0fffffff + #define SD_IDL_WIDTH 28 + #define SD_IDL_RESET 0000000000 +#define SD_RTC HW_REGISTER_RW( 0x7ee0001c ) + #define SD_RTC_MASK 0xffffffff + #define SD_RTC_WIDTH 32 + #define SD_RTC_RESET 0000000000 +#define SD_WTC HW_REGISTER_RO( 0x7ee00020 ) + #define SD_WTC_MASK 0x0fffffff + #define SD_WTC_WIDTH 28 + #define SD_WTC_RESET 0000000000 +#define SD_RDC HW_REGISTER_RO( 0x7ee00024 ) + #define SD_RDC_MASK 0x0fffffff + #define SD_RDC_WIDTH 28 + #define SD_RDC_RESET 0000000000 +#define SD_WDC HW_REGISTER_RO( 0x7ee00028 ) + #define SD_WDC_MASK 0x0fffffff + #define SD_WDC_WIDTH 28 + #define SD_WDC_RESET 0000000000 +#define SD_RAC HW_REGISTER_RO( 0x7ee0002c ) + #define SD_RAC_MASK 0x0fffffff + #define SD_RAC_WIDTH 28 + #define SD_RAC_RESET 0000000000 +#define SD_CYC HW_REGISTER_RO( 0x7ee00030 ) + #define SD_CYC_MASK 0x0fffffff + #define SD_CYC_WIDTH 28 + #define SD_CYC_RESET 0000000000 +#define SD_CMD HW_REGISTER_RO( 0x7ee00034 ) + #define SD_CMD_MASK 0x0fffffff + #define SD_CMD_WIDTH 28 + #define SD_CMD_RESET 0000000000 +#define SD_DAT HW_REGISTER_RO( 0x7ee00038 ) + #define SD_DAT_MASK 0x0fffffff + #define SD_DAT_WIDTH 28 + #define SD_DAT_RESET 0000000000 +#define SD_REORD HW_REGISTER_RO( 0x7ee000a8 ) + #define SD_REORD_MASK 0x0fffffff + #define SD_REORD_WIDTH 28 + #define SD_REORD_RESET 0000000000 +#define SD_LAC HW_REGISTER_RO( 0x7ee000ac ) + #define SD_LAC_MASK 0x0fffffff + #define SD_LAC_WIDTH 28 + #define SD_LAC_RESET 0000000000 +#define SD_PRE HW_REGISTER_RO( 0x7ee000b0 ) + #define SD_PRE_MASK 0x0fffffff + #define SD_PRE_WIDTH 28 + #define SD_PRE_RESET 0000000000 +#define SD_SECSRT0 HW_REGISTER_RW( 0x7ee0003c ) + #define SD_SECSRT0_MASK 0xffffffff + #define SD_SECSRT0_WIDTH 32 + #define SD_SECSRT0_ADDR_MS_BITS 31:13 + #define SD_SECSRT0_ADDR_MS_SET 0xffffe000 + #define SD_SECSRT0_ADDR_MS_CLR 0x00001fff + #define SD_SECSRT0_ADDR_MS_MSB 31 + #define SD_SECSRT0_ADDR_MS_LSB 13 + #define SD_SECSRT0_ADDR_MS_RESET 0x0 + #define SD_SECSRT0_ADDR_LS_BITS 12:1 + #define SD_SECSRT0_ADDR_LS_SET 0x00001ffe + #define SD_SECSRT0_ADDR_LS_CLR 0xffffe001 + #define SD_SECSRT0_ADDR_LS_MSB 12 + #define SD_SECSRT0_ADDR_LS_LSB 1 + #define SD_SECSRT0_ADDR_LS_RESET 0x0 + #define SD_SECSRT0_EN_BITS 0:0 + #define SD_SECSRT0_EN_SET 0x00000001 + #define SD_SECSRT0_EN_CLR 0xfffffffe + #define SD_SECSRT0_EN_MSB 0 + #define SD_SECSRT0_EN_LSB 0 + #define SD_SECSRT0_EN_RESET 0x0 +#define SD_SECEND0 HW_REGISTER_RW( 0x7ee00040 ) + #define SD_SECEND0_MASK 0xffffffff + #define SD_SECEND0_WIDTH 32 + #define SD_SECEND0_ADDR_MS_BITS 31:13 + #define SD_SECEND0_ADDR_MS_SET 0xffffe000 + #define SD_SECEND0_ADDR_MS_CLR 0x00001fff + #define SD_SECEND0_ADDR_MS_MSB 31 + #define SD_SECEND0_ADDR_MS_LSB 13 + #define SD_SECEND0_ADDR_MS_RESET 0x0 + #define SD_SECEND0_ADDR_LS_BITS 12:0 + #define SD_SECEND0_ADDR_LS_SET 0x00001fff + #define SD_SECEND0_ADDR_LS_CLR 0xffffe000 + #define SD_SECEND0_ADDR_LS_MSB 12 + #define SD_SECEND0_ADDR_LS_LSB 0 + #define SD_SECEND0_ADDR_LS_RESET 0xfff +#define SD_SECSRT1 HW_REGISTER_RW( 0x7ee00044 ) + #define SD_SECSRT1_MASK 0xffffffff + #define SD_SECSRT1_WIDTH 32 + #define SD_SECSRT1_ADDR_MS_BITS 31:13 + #define SD_SECSRT1_ADDR_MS_SET 0xffffe000 + #define SD_SECSRT1_ADDR_MS_CLR 0x00001fff + #define SD_SECSRT1_ADDR_MS_MSB 31 + #define SD_SECSRT1_ADDR_MS_LSB 13 + #define SD_SECSRT1_ADDR_MS_RESET 0x0 + #define SD_SECSRT1_ADDR_LS_BITS 12:1 + #define SD_SECSRT1_ADDR_LS_SET 0x00001ffe + #define SD_SECSRT1_ADDR_LS_CLR 0xffffe001 + #define SD_SECSRT1_ADDR_LS_MSB 12 + #define SD_SECSRT1_ADDR_LS_LSB 1 + #define SD_SECSRT1_ADDR_LS_RESET 0x0 + #define SD_SECSRT1_EN_BITS 0:0 + #define SD_SECSRT1_EN_SET 0x00000001 + #define SD_SECSRT1_EN_CLR 0xfffffffe + #define SD_SECSRT1_EN_MSB 0 + #define SD_SECSRT1_EN_LSB 0 + #define SD_SECSRT1_EN_RESET 0x0 +#define SD_SECEND1 HW_REGISTER_RW( 0x7ee00048 ) + #define SD_SECEND1_MASK 0xffffffff + #define SD_SECEND1_WIDTH 32 + #define SD_SECEND1_ADDR_MS_BITS 31:13 + #define SD_SECEND1_ADDR_MS_SET 0xffffe000 + #define SD_SECEND1_ADDR_MS_CLR 0x00001fff + #define SD_SECEND1_ADDR_MS_MSB 31 + #define SD_SECEND1_ADDR_MS_LSB 13 + #define SD_SECEND1_ADDR_MS_RESET 0x0 + #define SD_SECEND1_ADDR_LS_BITS 12:0 + #define SD_SECEND1_ADDR_LS_SET 0x00001fff + #define SD_SECEND1_ADDR_LS_CLR 0xffffe000 + #define SD_SECEND1_ADDR_LS_MSB 12 + #define SD_SECEND1_ADDR_LS_LSB 0 + #define SD_SECEND1_ADDR_LS_RESET 0xfff +#define SD_SECSRT2 HW_REGISTER_RW( 0x7ee0004c ) + #define SD_SECSRT2_MASK 0xffffffff + #define SD_SECSRT2_WIDTH 32 + #define SD_SECSRT2_ADDR_MS_BITS 31:13 + #define SD_SECSRT2_ADDR_MS_SET 0xffffe000 + #define SD_SECSRT2_ADDR_MS_CLR 0x00001fff + #define SD_SECSRT2_ADDR_MS_MSB 31 + #define SD_SECSRT2_ADDR_MS_LSB 13 + #define SD_SECSRT2_ADDR_MS_RESET 0x0 + #define SD_SECSRT2_ADDR_LS_BITS 12:1 + #define SD_SECSRT2_ADDR_LS_SET 0x00001ffe + #define SD_SECSRT2_ADDR_LS_CLR 0xffffe001 + #define SD_SECSRT2_ADDR_LS_MSB 12 + #define SD_SECSRT2_ADDR_LS_LSB 1 + #define SD_SECSRT2_ADDR_LS_RESET 0x0 + #define SD_SECSRT2_EN_BITS 0:0 + #define SD_SECSRT2_EN_SET 0x00000001 + #define SD_SECSRT2_EN_CLR 0xfffffffe + #define SD_SECSRT2_EN_MSB 0 + #define SD_SECSRT2_EN_LSB 0 + #define SD_SECSRT2_EN_RESET 0x0 +#define SD_SECEND2 HW_REGISTER_RW( 0x7ee00050 ) + #define SD_SECEND2_MASK 0xffffffff + #define SD_SECEND2_WIDTH 32 + #define SD_SECEND2_ADDR_MS_BITS 31:13 + #define SD_SECEND2_ADDR_MS_SET 0xffffe000 + #define SD_SECEND2_ADDR_MS_CLR 0x00001fff + #define SD_SECEND2_ADDR_MS_MSB 31 + #define SD_SECEND2_ADDR_MS_LSB 13 + #define SD_SECEND2_ADDR_MS_RESET 0x0 + #define SD_SECEND2_ADDR_LS_BITS 12:0 + #define SD_SECEND2_ADDR_LS_SET 0x00001fff + #define SD_SECEND2_ADDR_LS_CLR 0xffffe000 + #define SD_SECEND2_ADDR_LS_MSB 12 + #define SD_SECEND2_ADDR_LS_LSB 0 + #define SD_SECEND2_ADDR_LS_RESET 0xfff +#define SD_SECSRT3 HW_REGISTER_RW( 0x7ee00054 ) + #define SD_SECSRT3_MASK 0xffffffff + #define SD_SECSRT3_WIDTH 32 + #define SD_SECSRT3_ADDR_MS_BITS 31:13 + #define SD_SECSRT3_ADDR_MS_SET 0xffffe000 + #define SD_SECSRT3_ADDR_MS_CLR 0x00001fff + #define SD_SECSRT3_ADDR_MS_MSB 31 + #define SD_SECSRT3_ADDR_MS_LSB 13 + #define SD_SECSRT3_ADDR_MS_RESET 0x0 + #define SD_SECSRT3_ADDR_LS_BITS 12:1 + #define SD_SECSRT3_ADDR_LS_SET 0x00001ffe + #define SD_SECSRT3_ADDR_LS_CLR 0xffffe001 + #define SD_SECSRT3_ADDR_LS_MSB 12 + #define SD_SECSRT3_ADDR_LS_LSB 1 + #define SD_SECSRT3_ADDR_LS_RESET 0x0 + #define SD_SECSRT3_EN_BITS 0:0 + #define SD_SECSRT3_EN_SET 0x00000001 + #define SD_SECSRT3_EN_CLR 0xfffffffe + #define SD_SECSRT3_EN_MSB 0 + #define SD_SECSRT3_EN_LSB 0 + #define SD_SECSRT3_EN_RESET 0x0 +#define SD_SECEND3 HW_REGISTER_RW( 0x7ee00058 ) + #define SD_SECEND3_MASK 0xffffffff + #define SD_SECEND3_WIDTH 32 + #define SD_SECEND3_ADDR_MS_BITS 31:13 + #define SD_SECEND3_ADDR_MS_SET 0xffffe000 + #define SD_SECEND3_ADDR_MS_CLR 0x00001fff + #define SD_SECEND3_ADDR_MS_MSB 31 + #define SD_SECEND3_ADDR_MS_LSB 13 + #define SD_SECEND3_ADDR_MS_RESET 0x0 + #define SD_SECEND3_ADDR_LS_BITS 12:0 + #define SD_SECEND3_ADDR_LS_SET 0x00001fff + #define SD_SECEND3_ADDR_LS_CLR 0xffffe000 + #define SD_SECEND3_ADDR_LS_MSB 12 + #define SD_SECEND3_ADDR_LS_LSB 0 + #define SD_SECEND3_ADDR_LS_RESET 0xfff +#define SD_PHYC HW_REGISTER_RW( 0x7ee00060 ) + #define SD_PHYC_MASK 0x01111111 + #define SD_PHYC_WIDTH 25 + #define SD_PHYC_CRC_CLR_BITS 24:24 + #define SD_PHYC_CRC_CLR_SET 0x01000000 + #define SD_PHYC_CRC_CLR_CLR 0xfeffffff + #define SD_PHYC_CRC_CLR_MSB 24 + #define SD_PHYC_CRC_CLR_LSB 24 + #define SD_PHYC_CRC_CLR_RESET 0x0 + #define SD_PHYC_CRC_EN_BITS 20:20 + #define SD_PHYC_CRC_EN_SET 0x00100000 + #define SD_PHYC_CRC_EN_CLR 0xffefffff + #define SD_PHYC_CRC_EN_MSB 20 + #define SD_PHYC_CRC_EN_LSB 20 + #define SD_PHYC_CRC_EN_RESET 0x0 + #define SD_PHYC_MDLL_TMODE_BITS 16:16 + #define SD_PHYC_MDLL_TMODE_SET 0x00010000 + #define SD_PHYC_MDLL_TMODE_CLR 0xfffeffff + #define SD_PHYC_MDLL_TMODE_MSB 16 + #define SD_PHYC_MDLL_TMODE_LSB 16 + #define SD_PHYC_MDLL_TMODE_RESET 0x0 + #define SD_PHYC_IOB_TMODE_BITS 12:12 + #define SD_PHYC_IOB_TMODE_SET 0x00001000 + #define SD_PHYC_IOB_TMODE_CLR 0xffffefff + #define SD_PHYC_IOB_TMODE_MSB 12 + #define SD_PHYC_IOB_TMODE_LSB 12 + #define SD_PHYC_IOB_TMODE_RESET 0x0 + #define SD_PHYC_BIST_MODE_BITS 8:8 + #define SD_PHYC_BIST_MODE_SET 0x00000100 + #define SD_PHYC_BIST_MODE_CLR 0xfffffeff + #define SD_PHYC_BIST_MODE_MSB 8 + #define SD_PHYC_BIST_MODE_LSB 8 + #define SD_PHYC_BIST_MODE_RESET 0x0 + #define SD_PHYC_VREF_ENB_BITS 4:4 + #define SD_PHYC_VREF_ENB_SET 0x00000010 + #define SD_PHYC_VREF_ENB_CLR 0xffffffef + #define SD_PHYC_VREF_ENB_MSB 4 + #define SD_PHYC_VREF_ENB_LSB 4 + #define SD_PHYC_VREF_ENB_RESET 0x0 + #define SD_PHYC_PHYRST_BITS 0:0 + #define SD_PHYC_PHYRST_SET 0x00000001 + #define SD_PHYC_PHYRST_CLR 0xfffffffe + #define SD_PHYC_PHYRST_MSB 0 + #define SD_PHYC_PHYRST_LSB 0 + #define SD_PHYC_PHYRST_RESET 0x0 +#define SD_TMC HW_REGISTER_RW( 0x7ee0007c ) + #define SD_TMC_MASK 0xffffff73 + #define SD_TMC_WIDTH 32 + #define SD_TMC_TSTPAT_BITS 31:16 + #define SD_TMC_TSTPAT_SET 0xffff0000 + #define SD_TMC_TSTPAT_CLR 0x0000ffff + #define SD_TMC_TSTPAT_MSB 31 + #define SD_TMC_TSTPAT_LSB 16 + #define SD_TMC_TSTPAT_RESET 0x0 + #define SD_TMC_IPRD_BITS 15:8 + #define SD_TMC_IPRD_SET 0x0000ff00 + #define SD_TMC_IPRD_CLR 0xffff00ff + #define SD_TMC_IPRD_MSB 15 + #define SD_TMC_IPRD_LSB 8 + #define SD_TMC_IPRD_RESET 0x0 + #define SD_TMC_IPSEL_BITS 6:4 + #define SD_TMC_IPSEL_SET 0x00000070 + #define SD_TMC_IPSEL_CLR 0xffffff8f + #define SD_TMC_IPSEL_MSB 6 + #define SD_TMC_IPSEL_LSB 4 + #define SD_TMC_IPSEL_RESET 0x0 + #define SD_TMC_TS_BITS 1:1 + #define SD_TMC_TS_SET 0x00000002 + #define SD_TMC_TS_CLR 0xfffffffd + #define SD_TMC_TS_MSB 1 + #define SD_TMC_TS_LSB 1 + #define SD_TMC_TS_RESET 0x0 + #define SD_TMC_TSTCLK_BITS 0:0 + #define SD_TMC_TSTCLK_SET 0x00000001 + #define SD_TMC_TSTCLK_CLR 0xfffffffe + #define SD_TMC_TSTCLK_MSB 0 + #define SD_TMC_TSTCLK_LSB 0 + #define SD_TMC_TSTCLK_RESET 0x0 +#define SD_RWC HW_REGISTER_RW( 0x7ee00080 ) + #define SD_RWC_MASK 0x9fdf9f9f + #define SD_RWC_WIDTH 32 + #define SD_RWC_RSTMAX_BITS 31:31 + #define SD_RWC_RSTMAX_SET 0x80000000 + #define SD_RWC_RSTMAX_CLR 0x7fffffff + #define SD_RWC_RSTMAX_MSB 31 + #define SD_RWC_RSTMAX_LSB 31 + #define SD_RWC_RSTMAX_RESET 0x0 + #define SD_RWC_MAXCNT_BITS 28:24 + #define SD_RWC_MAXCNT_SET 0x1f000000 + #define SD_RWC_MAXCNT_CLR 0xe0ffffff + #define SD_RWC_MAXCNT_MSB 28 + #define SD_RWC_MAXCNT_LSB 24 + #define SD_RWC_MAXCNT_RESET 0x0 + #define SD_RWC_MARGIN_BITS 23:22 + #define SD_RWC_MARGIN_SET 0x00c00000 + #define SD_RWC_MARGIN_CLR 0xff3fffff + #define SD_RWC_MARGIN_MSB 23 + #define SD_RWC_MARGIN_LSB 22 + #define SD_RWC_MARGIN_RESET 0x1 + #define SD_RWC_LASTCNT_BITS 20:16 + #define SD_RWC_LASTCNT_SET 0x001f0000 + #define SD_RWC_LASTCNT_CLR 0xffe0ffff + #define SD_RWC_LASTCNT_MSB 20 + #define SD_RWC_LASTCNT_LSB 16 + #define SD_RWC_LASTCNT_RESET 0x0 + #define SD_RWC_WRTOVR_BITS 15:15 + #define SD_RWC_WRTOVR_SET 0x00008000 + #define SD_RWC_WRTOVR_CLR 0xffff7fff + #define SD_RWC_WRTOVR_MSB 15 + #define SD_RWC_WRTOVR_LSB 15 + #define SD_RWC_WRTOVR_RESET 0x0 + #define SD_RWC_WRTVAL_BITS 12:8 + #define SD_RWC_WRTVAL_SET 0x00001f00 + #define SD_RWC_WRTVAL_CLR 0xffffe0ff + #define SD_RWC_WRTVAL_MSB 12 + #define SD_RWC_WRTVAL_LSB 8 + #define SD_RWC_WRTVAL_RESET 0x0 + #define SD_RWC_RXOVR_BITS 7:7 + #define SD_RWC_RXOVR_SET 0x00000080 + #define SD_RWC_RXOVR_CLR 0xffffff7f + #define SD_RWC_RXOVR_MSB 7 + #define SD_RWC_RXOVR_LSB 7 + #define SD_RWC_RXOVR_RESET 0x0 + #define SD_RWC_RXVAL_BITS 4:0 + #define SD_RWC_RXVAL_SET 0x0000001f + #define SD_RWC_RXVAL_CLR 0xffffffe0 + #define SD_RWC_RXVAL_MSB 4 + #define SD_RWC_RXVAL_LSB 0 + #define SD_RWC_RXVAL_RESET 0x0 +#define SD_VAD HW_REGISTER_RO( 0x7ee00084 ) + #define SD_VAD_MASK 0xffffffff + #define SD_VAD_WIDTH 32 + #define SD_VAD_RESET 0000000000 +#define SD_VIN HW_REGISTER_RW( 0x7ee00088 ) + #define SD_VIN_MASK 0x9113ffff + #define SD_VIN_WIDTH 32 + #define SD_VIN_CLEAR_BITS 31:31 + #define SD_VIN_CLEAR_SET 0x80000000 + #define SD_VIN_CLEAR_CLR 0x7fffffff + #define SD_VIN_CLEAR_MSB 31 + #define SD_VIN_CLEAR_LSB 31 + #define SD_VIN_CLEAR_RESET 0x0 + #define SD_VIN_INT_EN_BITS 28:28 + #define SD_VIN_INT_EN_SET 0x10000000 + #define SD_VIN_INT_EN_CLR 0xefffffff + #define SD_VIN_INT_EN_MSB 28 + #define SD_VIN_INT_EN_LSB 28 + #define SD_VIN_INT_EN_RESET 0x0 + #define SD_VIN_MULT_BITS 24:24 + #define SD_VIN_MULT_SET 0x01000000 + #define SD_VIN_MULT_CLR 0xfeffffff + #define SD_VIN_MULT_MSB 24 + #define SD_VIN_MULT_LSB 24 + #define SD_VIN_MULT_RESET 0x0 + #define SD_VIN_VIO_BITS 20:20 + #define SD_VIN_VIO_SET 0x00100000 + #define SD_VIN_VIO_CLR 0xffefffff + #define SD_VIN_VIO_MSB 20 + #define SD_VIN_VIO_LSB 20 + #define SD_VIN_VIO_RESET 0x0 + #define SD_VIN_SPLIT_BITS 17:17 + #define SD_VIN_SPLIT_SET 0x00020000 + #define SD_VIN_SPLIT_CLR 0xfffdffff + #define SD_VIN_SPLIT_MSB 17 + #define SD_VIN_SPLIT_LSB 17 + #define SD_VIN_SPLIT_RESET 0x0 + #define SD_VIN_WRITE_BITS 16:16 + #define SD_VIN_WRITE_SET 0x00010000 + #define SD_VIN_WRITE_CLR 0xfffeffff + #define SD_VIN_WRITE_MSB 16 + #define SD_VIN_WRITE_LSB 16 + #define SD_VIN_WRITE_RESET 0x0 + #define SD_VIN_ID_BITS 15:0 + #define SD_VIN_ID_SET 0x0000ffff + #define SD_VIN_ID_CLR 0xffff0000 + #define SD_VIN_ID_MSB 15 + #define SD_VIN_ID_LSB 0 + #define SD_VIN_ID_RESET 0x0 +#define SD_VER HW_REGISTER_RO( 0x7ee0009c ) + #define SD_VER_MASK 0xffffffff + #define SD_VER_WIDTH 32 + #define SD_VER_RESET 0x00000009 +#define SD_STALL HW_REGISTER_RW( 0x7ee000a0 ) // ENGINEERING & DEBUG USE ONLY + #define SD_STALL_MASK 0x000003ff + #define SD_STALL_WIDTH 10 + #define SD_STALL_CYCLES_BITS 9:0 + #define SD_STALL_CYCLES_SET 0x000003ff + #define SD_STALL_CYCLES_CLR 0xfffffc00 + #define SD_STALL_CYCLES_MSB 9 + #define SD_STALL_CYCLES_LSB 0 + #define SD_STALL_CYCLES_RESET 0x0 +#define SD_CARCRC HW_REGISTER_RO( 0x7ee00100 ) + #define SD_CARCRC_MASK 0xffffffff + #define SD_CARCRC_WIDTH 32 + #define SD_CARCRC_RISE_BITS 31:16 + #define SD_CARCRC_RISE_SET 0xffff0000 + #define SD_CARCRC_RISE_CLR 0x0000ffff + #define SD_CARCRC_RISE_MSB 31 + #define SD_CARCRC_RISE_LSB 16 + #define SD_CARCRC_RISE_RESET 0x0 + #define SD_CARCRC_FALL_BITS 15:0 + #define SD_CARCRC_FALL_SET 0x0000ffff + #define SD_CARCRC_FALL_CLR 0xffff0000 + #define SD_CARCRC_FALL_MSB 15 + #define SD_CARCRC_FALL_LSB 0 + #define SD_CARCRC_FALL_RESET 0x0 +#define SD_DMRCRC0 HW_REGISTER_RO( 0x7ee00104 ) + #define SD_DMRCRC0_MASK 0xffffffff + #define SD_DMRCRC0_WIDTH 32 + #define SD_DMRCRC0_HIGH_BITS 31:16 + #define SD_DMRCRC0_HIGH_SET 0xffff0000 + #define SD_DMRCRC0_HIGH_CLR 0x0000ffff + #define SD_DMRCRC0_HIGH_MSB 31 + #define SD_DMRCRC0_HIGH_LSB 16 + #define SD_DMRCRC0_HIGH_RESET 0x0 + #define SD_DMRCRC0_LOW_BITS 15:0 + #define SD_DMRCRC0_LOW_SET 0x0000ffff + #define SD_DMRCRC0_LOW_CLR 0xffff0000 + #define SD_DMRCRC0_LOW_MSB 15 + #define SD_DMRCRC0_LOW_LSB 0 + #define SD_DMRCRC0_LOW_RESET 0x0 +#define SD_DMRCRC1 HW_REGISTER_RO( 0x7ee00108 ) // (only for 64 bit wide SDRAM) + #define SD_DMRCRC1_MASK 0xffffffff + #define SD_DMRCRC1_WIDTH 32 + #define SD_DMRCRC1_HIGH_BITS 31:16 + #define SD_DMRCRC1_HIGH_SET 0xffff0000 + #define SD_DMRCRC1_HIGH_CLR 0x0000ffff + #define SD_DMRCRC1_HIGH_MSB 31 + #define SD_DMRCRC1_HIGH_LSB 16 + #define SD_DMRCRC1_HIGH_RESET 0x0 + #define SD_DMRCRC1_LOW_BITS 15:0 + #define SD_DMRCRC1_LOW_SET 0x0000ffff + #define SD_DMRCRC1_LOW_CLR 0xffff0000 + #define SD_DMRCRC1_LOW_MSB 15 + #define SD_DMRCRC1_LOW_LSB 0 + #define SD_DMRCRC1_LOW_RESET 0x0 +#define SD_DQRCRC0 HW_REGISTER_RO( 0x7ee0010c ) + #define SD_DQRCRC0_MASK 0xffffffff + #define SD_DQRCRC0_WIDTH 32 + #define SD_DQRCRC0_RISE_BITS 31:16 + #define SD_DQRCRC0_RISE_SET 0xffff0000 + #define SD_DQRCRC0_RISE_CLR 0x0000ffff + #define SD_DQRCRC0_RISE_MSB 31 + #define SD_DQRCRC0_RISE_LSB 16 + #define SD_DQRCRC0_RISE_RESET 0x0 + #define SD_DQRCRC0_FALL_BITS 15:0 + #define SD_DQRCRC0_FALL_SET 0x0000ffff + #define SD_DQRCRC0_FALL_CLR 0xffff0000 + #define SD_DQRCRC0_FALL_MSB 15 + #define SD_DQRCRC0_FALL_LSB 0 + #define SD_DQRCRC0_FALL_RESET 0x0 +#define SD_DQRCRC1 HW_REGISTER_RO( 0x7ee00110 ) + #define SD_DQRCRC1_MASK 0xffffffff + #define SD_DQRCRC1_WIDTH 32 + #define SD_DQRCRC1_RISE_BITS 31:16 + #define SD_DQRCRC1_RISE_SET 0xffff0000 + #define SD_DQRCRC1_RISE_CLR 0x0000ffff + #define SD_DQRCRC1_RISE_MSB 31 + #define SD_DQRCRC1_RISE_LSB 16 + #define SD_DQRCRC1_RISE_RESET 0x0 + #define SD_DQRCRC1_FALL_BITS 15:0 + #define SD_DQRCRC1_FALL_SET 0x0000ffff + #define SD_DQRCRC1_FALL_CLR 0xffff0000 + #define SD_DQRCRC1_FALL_MSB 15 + #define SD_DQRCRC1_FALL_LSB 0 + #define SD_DQRCRC1_FALL_RESET 0x0 +#define SD_DQRCRC2 HW_REGISTER_RO( 0x7ee00114 ) + #define SD_DQRCRC2_MASK 0xffffffff + #define SD_DQRCRC2_WIDTH 32 + #define SD_DQRCRC2_RISE_BITS 31:16 + #define SD_DQRCRC2_RISE_SET 0xffff0000 + #define SD_DQRCRC2_RISE_CLR 0x0000ffff + #define SD_DQRCRC2_RISE_MSB 31 + #define SD_DQRCRC2_RISE_LSB 16 + #define SD_DQRCRC2_RISE_RESET 0x0 + #define SD_DQRCRC2_FALL_BITS 15:0 + #define SD_DQRCRC2_FALL_SET 0x0000ffff + #define SD_DQRCRC2_FALL_CLR 0xffff0000 + #define SD_DQRCRC2_FALL_MSB 15 + #define SD_DQRCRC2_FALL_LSB 0 + #define SD_DQRCRC2_FALL_RESET 0x0 +#define SD_DQRCRC3 HW_REGISTER_RO( 0x7ee00118 ) + #define SD_DQRCRC3_MASK 0xffffffff + #define SD_DQRCRC3_WIDTH 32 + #define SD_DQRCRC3_RISE_BITS 31:16 + #define SD_DQRCRC3_RISE_SET 0xffff0000 + #define SD_DQRCRC3_RISE_CLR 0x0000ffff + #define SD_DQRCRC3_RISE_MSB 31 + #define SD_DQRCRC3_RISE_LSB 16 + #define SD_DQRCRC3_RISE_RESET 0x0 + #define SD_DQRCRC3_FALL_BITS 15:0 + #define SD_DQRCRC3_FALL_SET 0x0000ffff + #define SD_DQRCRC3_FALL_CLR 0xffff0000 + #define SD_DQRCRC3_FALL_MSB 15 + #define SD_DQRCRC3_FALL_LSB 0 + #define SD_DQRCRC3_FALL_RESET 0x0 +#define SD_DQRCRC4 HW_REGISTER_RO( 0x7ee0011c ) + #define SD_DQRCRC4_MASK 0xffffffff + #define SD_DQRCRC4_WIDTH 32 + #define SD_DQRCRC4_RISE_BITS 31:16 + #define SD_DQRCRC4_RISE_SET 0xffff0000 + #define SD_DQRCRC4_RISE_CLR 0x0000ffff + #define SD_DQRCRC4_RISE_MSB 31 + #define SD_DQRCRC4_RISE_LSB 16 + #define SD_DQRCRC4_RISE_RESET 0x0 + #define SD_DQRCRC4_FALL_BITS 15:0 + #define SD_DQRCRC4_FALL_SET 0x0000ffff + #define SD_DQRCRC4_FALL_CLR 0xffff0000 + #define SD_DQRCRC4_FALL_MSB 15 + #define SD_DQRCRC4_FALL_LSB 0 + #define SD_DQRCRC4_FALL_RESET 0x0 +#define SD_DQRCRC5 HW_REGISTER_RO( 0x7ee00120 ) + #define SD_DQRCRC5_MASK 0xffffffff + #define SD_DQRCRC5_WIDTH 32 + #define SD_DQRCRC5_RISE_BITS 31:16 + #define SD_DQRCRC5_RISE_SET 0xffff0000 + #define SD_DQRCRC5_RISE_CLR 0x0000ffff + #define SD_DQRCRC5_RISE_MSB 31 + #define SD_DQRCRC5_RISE_LSB 16 + #define SD_DQRCRC5_RISE_RESET 0x0 + #define SD_DQRCRC5_FALL_BITS 15:0 + #define SD_DQRCRC5_FALL_SET 0x0000ffff + #define SD_DQRCRC5_FALL_CLR 0xffff0000 + #define SD_DQRCRC5_FALL_MSB 15 + #define SD_DQRCRC5_FALL_LSB 0 + #define SD_DQRCRC5_FALL_RESET 0x0 +#define SD_DQRCRC6 HW_REGISTER_RO( 0x7ee00124 ) + #define SD_DQRCRC6_MASK 0xffffffff + #define SD_DQRCRC6_WIDTH 32 + #define SD_DQRCRC6_RISE_BITS 31:16 + #define SD_DQRCRC6_RISE_SET 0xffff0000 + #define SD_DQRCRC6_RISE_CLR 0x0000ffff + #define SD_DQRCRC6_RISE_MSB 31 + #define SD_DQRCRC6_RISE_LSB 16 + #define SD_DQRCRC6_RISE_RESET 0x0 + #define SD_DQRCRC6_FALL_BITS 15:0 + #define SD_DQRCRC6_FALL_SET 0x0000ffff + #define SD_DQRCRC6_FALL_CLR 0xffff0000 + #define SD_DQRCRC6_FALL_MSB 15 + #define SD_DQRCRC6_FALL_LSB 0 + #define SD_DQRCRC6_FALL_RESET 0x0 +#define SD_DQRCRC7 HW_REGISTER_RO( 0x7ee00128 ) + #define SD_DQRCRC7_MASK 0xffffffff + #define SD_DQRCRC7_WIDTH 32 + #define SD_DQRCRC7_RISE_BITS 31:16 + #define SD_DQRCRC7_RISE_SET 0xffff0000 + #define SD_DQRCRC7_RISE_CLR 0x0000ffff + #define SD_DQRCRC7_RISE_MSB 31 + #define SD_DQRCRC7_RISE_LSB 16 + #define SD_DQRCRC7_RISE_RESET 0x0 + #define SD_DQRCRC7_FALL_BITS 15:0 + #define SD_DQRCRC7_FALL_SET 0x0000ffff + #define SD_DQRCRC7_FALL_CLR 0xffff0000 + #define SD_DQRCRC7_FALL_MSB 15 + #define SD_DQRCRC7_FALL_LSB 0 + #define SD_DQRCRC7_FALL_RESET 0x0 +#define SD_DQRCRC8 HW_REGISTER_RO( 0x7ee0012c ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC8_MASK 0xffffffff + #define SD_DQRCRC8_WIDTH 32 + #define SD_DQRCRC8_RISE_BITS 31:16 + #define SD_DQRCRC8_RISE_SET 0xffff0000 + #define SD_DQRCRC8_RISE_CLR 0x0000ffff + #define SD_DQRCRC8_RISE_MSB 31 + #define SD_DQRCRC8_RISE_LSB 16 + #define SD_DQRCRC8_RISE_RESET 0x0 + #define SD_DQRCRC8_FALL_BITS 15:0 + #define SD_DQRCRC8_FALL_SET 0x0000ffff + #define SD_DQRCRC8_FALL_CLR 0xffff0000 + #define SD_DQRCRC8_FALL_MSB 15 + #define SD_DQRCRC8_FALL_LSB 0 + #define SD_DQRCRC8_FALL_RESET 0x0 +#define SD_DQRCRC9 HW_REGISTER_RO( 0x7ee00130 ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC9_MASK 0xffffffff + #define SD_DQRCRC9_WIDTH 32 + #define SD_DQRCRC9_RISE_BITS 31:16 + #define SD_DQRCRC9_RISE_SET 0xffff0000 + #define SD_DQRCRC9_RISE_CLR 0x0000ffff + #define SD_DQRCRC9_RISE_MSB 31 + #define SD_DQRCRC9_RISE_LSB 16 + #define SD_DQRCRC9_RISE_RESET 0x0 + #define SD_DQRCRC9_FALL_BITS 15:0 + #define SD_DQRCRC9_FALL_SET 0x0000ffff + #define SD_DQRCRC9_FALL_CLR 0xffff0000 + #define SD_DQRCRC9_FALL_MSB 15 + #define SD_DQRCRC9_FALL_LSB 0 + #define SD_DQRCRC9_FALL_RESET 0x0 +#define SD_DQRCRC10 HW_REGISTER_RO( 0x7ee00134 ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC10_MASK 0xffffffff + #define SD_DQRCRC10_WIDTH 32 + #define SD_DQRCRC10_RISE_BITS 31:16 + #define SD_DQRCRC10_RISE_SET 0xffff0000 + #define SD_DQRCRC10_RISE_CLR 0x0000ffff + #define SD_DQRCRC10_RISE_MSB 31 + #define SD_DQRCRC10_RISE_LSB 16 + #define SD_DQRCRC10_RISE_RESET 0x0 + #define SD_DQRCRC10_FALL_BITS 15:0 + #define SD_DQRCRC10_FALL_SET 0x0000ffff + #define SD_DQRCRC10_FALL_CLR 0xffff0000 + #define SD_DQRCRC10_FALL_MSB 15 + #define SD_DQRCRC10_FALL_LSB 0 + #define SD_DQRCRC10_FALL_RESET 0x0 +#define SD_DQRCRC11 HW_REGISTER_RO( 0x7ee00138 ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC11_MASK 0xffffffff + #define SD_DQRCRC11_WIDTH 32 + #define SD_DQRCRC11_RISE_BITS 31:16 + #define SD_DQRCRC11_RISE_SET 0xffff0000 + #define SD_DQRCRC11_RISE_CLR 0x0000ffff + #define SD_DQRCRC11_RISE_MSB 31 + #define SD_DQRCRC11_RISE_LSB 16 + #define SD_DQRCRC11_RISE_RESET 0x0 + #define SD_DQRCRC11_FALL_BITS 15:0 + #define SD_DQRCRC11_FALL_SET 0x0000ffff + #define SD_DQRCRC11_FALL_CLR 0xffff0000 + #define SD_DQRCRC11_FALL_MSB 15 + #define SD_DQRCRC11_FALL_LSB 0 + #define SD_DQRCRC11_FALL_RESET 0x0 +#define SD_DQRCRC12 HW_REGISTER_RO( 0x7ee0013c ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC12_MASK 0xffffffff + #define SD_DQRCRC12_WIDTH 32 + #define SD_DQRCRC12_RISE_BITS 31:16 + #define SD_DQRCRC12_RISE_SET 0xffff0000 + #define SD_DQRCRC12_RISE_CLR 0x0000ffff + #define SD_DQRCRC12_RISE_MSB 31 + #define SD_DQRCRC12_RISE_LSB 16 + #define SD_DQRCRC12_RISE_RESET 0x0 + #define SD_DQRCRC12_FALL_BITS 15:0 + #define SD_DQRCRC12_FALL_SET 0x0000ffff + #define SD_DQRCRC12_FALL_CLR 0xffff0000 + #define SD_DQRCRC12_FALL_MSB 15 + #define SD_DQRCRC12_FALL_LSB 0 + #define SD_DQRCRC12_FALL_RESET 0x0 +#define SD_DQRCRC13 HW_REGISTER_RO( 0x7ee00140 ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC13_MASK 0xffffffff + #define SD_DQRCRC13_WIDTH 32 + #define SD_DQRCRC13_RISE_BITS 31:16 + #define SD_DQRCRC13_RISE_SET 0xffff0000 + #define SD_DQRCRC13_RISE_CLR 0x0000ffff + #define SD_DQRCRC13_RISE_MSB 31 + #define SD_DQRCRC13_RISE_LSB 16 + #define SD_DQRCRC13_RISE_RESET 0x0 + #define SD_DQRCRC13_FALL_BITS 15:0 + #define SD_DQRCRC13_FALL_SET 0x0000ffff + #define SD_DQRCRC13_FALL_CLR 0xffff0000 + #define SD_DQRCRC13_FALL_MSB 15 + #define SD_DQRCRC13_FALL_LSB 0 + #define SD_DQRCRC13_FALL_RESET 0x0 +#define SD_DQRCRC14 HW_REGISTER_RO( 0x7ee00144 ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC14_MASK 0xffffffff + #define SD_DQRCRC14_WIDTH 32 + #define SD_DQRCRC14_RISE_BITS 31:16 + #define SD_DQRCRC14_RISE_SET 0xffff0000 + #define SD_DQRCRC14_RISE_CLR 0x0000ffff + #define SD_DQRCRC14_RISE_MSB 31 + #define SD_DQRCRC14_RISE_LSB 16 + #define SD_DQRCRC14_RISE_RESET 0x0 + #define SD_DQRCRC14_FALL_BITS 15:0 + #define SD_DQRCRC14_FALL_SET 0x0000ffff + #define SD_DQRCRC14_FALL_CLR 0xffff0000 + #define SD_DQRCRC14_FALL_MSB 15 + #define SD_DQRCRC14_FALL_LSB 0 + #define SD_DQRCRC14_FALL_RESET 0x0 +#define SD_DQRCRC15 HW_REGISTER_RO( 0x7ee00148 ) // (only for 64 bit wide SDRAM) + #define SD_DQRCRC15_MASK 0xffffffff + #define SD_DQRCRC15_WIDTH 32 + #define SD_DQRCRC15_RISE_BITS 31:16 + #define SD_DQRCRC15_RISE_SET 0xffff0000 + #define SD_DQRCRC15_RISE_CLR 0x0000ffff + #define SD_DQRCRC15_RISE_MSB 31 + #define SD_DQRCRC15_RISE_LSB 16 + #define SD_DQRCRC15_RISE_RESET 0x0 + #define SD_DQRCRC15_FALL_BITS 15:0 + #define SD_DQRCRC15_FALL_SET 0x0000ffff + #define SD_DQRCRC15_FALL_CLR 0xffff0000 + #define SD_DQRCRC15_FALL_MSB 15 + #define SD_DQRCRC15_FALL_LSB 0 + #define SD_DQRCRC15_FALL_RESET 0x0 +#define SD_DQLCRC0 HW_REGISTER_RO( 0x7ee0014c ) + #define SD_DQLCRC0_MASK 0xffffffff + #define SD_DQLCRC0_WIDTH 32 + #define SD_DQLCRC0_RISE_BITS 31:16 + #define SD_DQLCRC0_RISE_SET 0xffff0000 + #define SD_DQLCRC0_RISE_CLR 0x0000ffff + #define SD_DQLCRC0_RISE_MSB 31 + #define SD_DQLCRC0_RISE_LSB 16 + #define SD_DQLCRC0_RISE_RESET 0x0 + #define SD_DQLCRC0_FALL_BITS 15:0 + #define SD_DQLCRC0_FALL_SET 0x0000ffff + #define SD_DQLCRC0_FALL_CLR 0xffff0000 + #define SD_DQLCRC0_FALL_MSB 15 + #define SD_DQLCRC0_FALL_LSB 0 + #define SD_DQLCRC0_FALL_RESET 0x0 +#define SD_DQLCRC1 HW_REGISTER_RO( 0x7ee00150 ) + #define SD_DQLCRC1_MASK 0xffffffff + #define SD_DQLCRC1_WIDTH 32 + #define SD_DQLCRC1_RISE_BITS 31:16 + #define SD_DQLCRC1_RISE_SET 0xffff0000 + #define SD_DQLCRC1_RISE_CLR 0x0000ffff + #define SD_DQLCRC1_RISE_MSB 31 + #define SD_DQLCRC1_RISE_LSB 16 + #define SD_DQLCRC1_RISE_RESET 0x0 + #define SD_DQLCRC1_FALL_BITS 15:0 + #define SD_DQLCRC1_FALL_SET 0x0000ffff + #define SD_DQLCRC1_FALL_CLR 0xffff0000 + #define SD_DQLCRC1_FALL_MSB 15 + #define SD_DQLCRC1_FALL_LSB 0 + #define SD_DQLCRC1_FALL_RESET 0x0 +#define SD_DQLCRC2 HW_REGISTER_RO( 0x7ee00154 ) + #define SD_DQLCRC2_MASK 0xffffffff + #define SD_DQLCRC2_WIDTH 32 + #define SD_DQLCRC2_RISE_BITS 31:16 + #define SD_DQLCRC2_RISE_SET 0xffff0000 + #define SD_DQLCRC2_RISE_CLR 0x0000ffff + #define SD_DQLCRC2_RISE_MSB 31 + #define SD_DQLCRC2_RISE_LSB 16 + #define SD_DQLCRC2_RISE_RESET 0x0 + #define SD_DQLCRC2_FALL_BITS 15:0 + #define SD_DQLCRC2_FALL_SET 0x0000ffff + #define SD_DQLCRC2_FALL_CLR 0xffff0000 + #define SD_DQLCRC2_FALL_MSB 15 + #define SD_DQLCRC2_FALL_LSB 0 + #define SD_DQLCRC2_FALL_RESET 0x0 +#define SD_DQLCRC3 HW_REGISTER_RO( 0x7ee00158 ) + #define SD_DQLCRC3_MASK 0xffffffff + #define SD_DQLCRC3_WIDTH 32 + #define SD_DQLCRC3_RISE_BITS 31:16 + #define SD_DQLCRC3_RISE_SET 0xffff0000 + #define SD_DQLCRC3_RISE_CLR 0x0000ffff + #define SD_DQLCRC3_RISE_MSB 31 + #define SD_DQLCRC3_RISE_LSB 16 + #define SD_DQLCRC3_RISE_RESET 0x0 + #define SD_DQLCRC3_FALL_BITS 15:0 + #define SD_DQLCRC3_FALL_SET 0x0000ffff + #define SD_DQLCRC3_FALL_CLR 0xffff0000 + #define SD_DQLCRC3_FALL_MSB 15 + #define SD_DQLCRC3_FALL_LSB 0 + #define SD_DQLCRC3_FALL_RESET 0x0 +#define SD_DQLCRC4 HW_REGISTER_RO( 0x7ee0015c ) + #define SD_DQLCRC4_MASK 0xffffffff + #define SD_DQLCRC4_WIDTH 32 + #define SD_DQLCRC4_RISE_BITS 31:16 + #define SD_DQLCRC4_RISE_SET 0xffff0000 + #define SD_DQLCRC4_RISE_CLR 0x0000ffff + #define SD_DQLCRC4_RISE_MSB 31 + #define SD_DQLCRC4_RISE_LSB 16 + #define SD_DQLCRC4_RISE_RESET 0x0 + #define SD_DQLCRC4_FALL_BITS 15:0 + #define SD_DQLCRC4_FALL_SET 0x0000ffff + #define SD_DQLCRC4_FALL_CLR 0xffff0000 + #define SD_DQLCRC4_FALL_MSB 15 + #define SD_DQLCRC4_FALL_LSB 0 + #define SD_DQLCRC4_FALL_RESET 0x0 +#define SD_DQLCRC5 HW_REGISTER_RO( 0x7ee00160 ) + #define SD_DQLCRC5_MASK 0xffffffff + #define SD_DQLCRC5_WIDTH 32 + #define SD_DQLCRC5_RISE_BITS 31:16 + #define SD_DQLCRC5_RISE_SET 0xffff0000 + #define SD_DQLCRC5_RISE_CLR 0x0000ffff + #define SD_DQLCRC5_RISE_MSB 31 + #define SD_DQLCRC5_RISE_LSB 16 + #define SD_DQLCRC5_RISE_RESET 0x0 + #define SD_DQLCRC5_FALL_BITS 15:0 + #define SD_DQLCRC5_FALL_SET 0x0000ffff + #define SD_DQLCRC5_FALL_CLR 0xffff0000 + #define SD_DQLCRC5_FALL_MSB 15 + #define SD_DQLCRC5_FALL_LSB 0 + #define SD_DQLCRC5_FALL_RESET 0x0 +#define SD_DQLCRC6 HW_REGISTER_RO( 0x7ee00164 ) + #define SD_DQLCRC6_MASK 0xffffffff + #define SD_DQLCRC6_WIDTH 32 + #define SD_DQLCRC6_RISE_BITS 31:16 + #define SD_DQLCRC6_RISE_SET 0xffff0000 + #define SD_DQLCRC6_RISE_CLR 0x0000ffff + #define SD_DQLCRC6_RISE_MSB 31 + #define SD_DQLCRC6_RISE_LSB 16 + #define SD_DQLCRC6_RISE_RESET 0x0 + #define SD_DQLCRC6_FALL_BITS 15:0 + #define SD_DQLCRC6_FALL_SET 0x0000ffff + #define SD_DQLCRC6_FALL_CLR 0xffff0000 + #define SD_DQLCRC6_FALL_MSB 15 + #define SD_DQLCRC6_FALL_LSB 0 + #define SD_DQLCRC6_FALL_RESET 0x0 +#define SD_DQLCRC7 HW_REGISTER_RO( 0x7ee00168 ) + #define SD_DQLCRC7_MASK 0xffffffff + #define SD_DQLCRC7_WIDTH 32 + #define SD_DQLCRC7_RISE_BITS 31:16 + #define SD_DQLCRC7_RISE_SET 0xffff0000 + #define SD_DQLCRC7_RISE_CLR 0x0000ffff + #define SD_DQLCRC7_RISE_MSB 31 + #define SD_DQLCRC7_RISE_LSB 16 + #define SD_DQLCRC7_RISE_RESET 0x0 + #define SD_DQLCRC7_FALL_BITS 15:0 + #define SD_DQLCRC7_FALL_SET 0x0000ffff + #define SD_DQLCRC7_FALL_CLR 0xffff0000 + #define SD_DQLCRC7_FALL_MSB 15 + #define SD_DQLCRC7_FALL_LSB 0 + #define SD_DQLCRC7_FALL_RESET 0x0 +#define SD_DQLCRC8 HW_REGISTER_RO( 0x7ee0016c ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC8_MASK 0xffffffff + #define SD_DQLCRC8_WIDTH 32 + #define SD_DQLCRC8_RISE_BITS 31:16 + #define SD_DQLCRC8_RISE_SET 0xffff0000 + #define SD_DQLCRC8_RISE_CLR 0x0000ffff + #define SD_DQLCRC8_RISE_MSB 31 + #define SD_DQLCRC8_RISE_LSB 16 + #define SD_DQLCRC8_RISE_RESET 0x0 + #define SD_DQLCRC8_FALL_BITS 15:0 + #define SD_DQLCRC8_FALL_SET 0x0000ffff + #define SD_DQLCRC8_FALL_CLR 0xffff0000 + #define SD_DQLCRC8_FALL_MSB 15 + #define SD_DQLCRC8_FALL_LSB 0 + #define SD_DQLCRC8_FALL_RESET 0x0 +#define SD_DQLCRC9 HW_REGISTER_RO( 0x7ee00170 ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC9_MASK 0xffffffff + #define SD_DQLCRC9_WIDTH 32 + #define SD_DQLCRC9_RISE_BITS 31:16 + #define SD_DQLCRC9_RISE_SET 0xffff0000 + #define SD_DQLCRC9_RISE_CLR 0x0000ffff + #define SD_DQLCRC9_RISE_MSB 31 + #define SD_DQLCRC9_RISE_LSB 16 + #define SD_DQLCRC9_RISE_RESET 0x0 + #define SD_DQLCRC9_FALL_BITS 15:0 + #define SD_DQLCRC9_FALL_SET 0x0000ffff + #define SD_DQLCRC9_FALL_CLR 0xffff0000 + #define SD_DQLCRC9_FALL_MSB 15 + #define SD_DQLCRC9_FALL_LSB 0 + #define SD_DQLCRC9_FALL_RESET 0x0 +#define SD_DQLCRC10 HW_REGISTER_RO( 0x7ee00174 ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC10_MASK 0xffffffff + #define SD_DQLCRC10_WIDTH 32 + #define SD_DQLCRC10_RISE_BITS 31:16 + #define SD_DQLCRC10_RISE_SET 0xffff0000 + #define SD_DQLCRC10_RISE_CLR 0x0000ffff + #define SD_DQLCRC10_RISE_MSB 31 + #define SD_DQLCRC10_RISE_LSB 16 + #define SD_DQLCRC10_RISE_RESET 0x0 + #define SD_DQLCRC10_FALL_BITS 15:0 + #define SD_DQLCRC10_FALL_SET 0x0000ffff + #define SD_DQLCRC10_FALL_CLR 0xffff0000 + #define SD_DQLCRC10_FALL_MSB 15 + #define SD_DQLCRC10_FALL_LSB 0 + #define SD_DQLCRC10_FALL_RESET 0x0 +#define SD_DQLCRC11 HW_REGISTER_RO( 0x7ee00178 ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC11_MASK 0xffffffff + #define SD_DQLCRC11_WIDTH 32 + #define SD_DQLCRC11_RISE_BITS 31:16 + #define SD_DQLCRC11_RISE_SET 0xffff0000 + #define SD_DQLCRC11_RISE_CLR 0x0000ffff + #define SD_DQLCRC11_RISE_MSB 31 + #define SD_DQLCRC11_RISE_LSB 16 + #define SD_DQLCRC11_RISE_RESET 0x0 + #define SD_DQLCRC11_FALL_BITS 15:0 + #define SD_DQLCRC11_FALL_SET 0x0000ffff + #define SD_DQLCRC11_FALL_CLR 0xffff0000 + #define SD_DQLCRC11_FALL_MSB 15 + #define SD_DQLCRC11_FALL_LSB 0 + #define SD_DQLCRC11_FALL_RESET 0x0 +#define SD_DQLCRC12 HW_REGISTER_RO( 0x7ee0017c ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC12_MASK 0xffffffff + #define SD_DQLCRC12_WIDTH 32 + #define SD_DQLCRC12_RISE_BITS 31:16 + #define SD_DQLCRC12_RISE_SET 0xffff0000 + #define SD_DQLCRC12_RISE_CLR 0x0000ffff + #define SD_DQLCRC12_RISE_MSB 31 + #define SD_DQLCRC12_RISE_LSB 16 + #define SD_DQLCRC12_RISE_RESET 0x0 + #define SD_DQLCRC12_FALL_BITS 15:0 + #define SD_DQLCRC12_FALL_SET 0x0000ffff + #define SD_DQLCRC12_FALL_CLR 0xffff0000 + #define SD_DQLCRC12_FALL_MSB 15 + #define SD_DQLCRC12_FALL_LSB 0 + #define SD_DQLCRC12_FALL_RESET 0x0 +#define SD_DQLCRC13 HW_REGISTER_RO( 0x7ee00180 ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC13_MASK 0xffffffff + #define SD_DQLCRC13_WIDTH 32 + #define SD_DQLCRC13_RISE_BITS 31:16 + #define SD_DQLCRC13_RISE_SET 0xffff0000 + #define SD_DQLCRC13_RISE_CLR 0x0000ffff + #define SD_DQLCRC13_RISE_MSB 31 + #define SD_DQLCRC13_RISE_LSB 16 + #define SD_DQLCRC13_RISE_RESET 0x0 + #define SD_DQLCRC13_FALL_BITS 15:0 + #define SD_DQLCRC13_FALL_SET 0x0000ffff + #define SD_DQLCRC13_FALL_CLR 0xffff0000 + #define SD_DQLCRC13_FALL_MSB 15 + #define SD_DQLCRC13_FALL_LSB 0 + #define SD_DQLCRC13_FALL_RESET 0x0 +#define SD_DQLCRC14 HW_REGISTER_RO( 0x7ee00184 ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC14_MASK 0xffffffff + #define SD_DQLCRC14_WIDTH 32 + #define SD_DQLCRC14_RISE_BITS 31:16 + #define SD_DQLCRC14_RISE_SET 0xffff0000 + #define SD_DQLCRC14_RISE_CLR 0x0000ffff + #define SD_DQLCRC14_RISE_MSB 31 + #define SD_DQLCRC14_RISE_LSB 16 + #define SD_DQLCRC14_RISE_RESET 0x0 + #define SD_DQLCRC14_FALL_BITS 15:0 + #define SD_DQLCRC14_FALL_SET 0x0000ffff + #define SD_DQLCRC14_FALL_CLR 0xffff0000 + #define SD_DQLCRC14_FALL_MSB 15 + #define SD_DQLCRC14_FALL_LSB 0 + #define SD_DQLCRC14_FALL_RESET 0x0 +#define SD_DQLCRC15 HW_REGISTER_RO( 0x7ee00188 ) // (only for 64 bit wide SDRAM) + #define SD_DQLCRC15_MASK 0xffffffff + #define SD_DQLCRC15_WIDTH 32 + #define SD_DQLCRC15_RISE_BITS 31:16 + #define SD_DQLCRC15_RISE_SET 0xffff0000 + #define SD_DQLCRC15_RISE_CLR 0x0000ffff + #define SD_DQLCRC15_RISE_MSB 31 + #define SD_DQLCRC15_RISE_LSB 16 + #define SD_DQLCRC15_RISE_RESET 0x0 + #define SD_DQLCRC15_FALL_BITS 15:0 + #define SD_DQLCRC15_FALL_SET 0x0000ffff + #define SD_DQLCRC15_FALL_CLR 0xffff0000 + #define SD_DQLCRC15_FALL_MSB 15 + #define SD_DQLCRC15_FALL_LSB 0 + #define SD_DQLCRC15_FALL_RESET 0x0 diff --git a/bcm2708_chip/sdc_dq_front.h b/bcm2708_chip/sdc_dq_front.h new file mode 100755 index 0000000..e990489 --- /dev/null +++ b/bcm2708_chip/sdc_dq_front.h @@ -0,0 +1,40 @@ +// This file was generated by the create_regs script +#define DPHY_CSR_BASE 0x7ee07000 +#define DPHY_CSR_DQ_REV_ID HW_REGISTER_RW( 0x7ee07000 ) +#define DPHY_CSR_GLBL_DQ_DLL_RESET HW_REGISTER_RW( 0x7ee07004 ) +#define DPHY_CSR_GLBL_DQ_DLL_RECALIBRATE HW_REGISTER_RW( 0x7ee07008 ) +#define DPHY_CSR_GLBL_DQ_DLL_CNTRL HW_REGISTER_RW( 0x7ee0700c ) +#define DPHY_CSR_GLBL_DQ_DLL_PHASE_LD_VL HW_REGISTER_RW( 0x7ee07010 ) +#define DPHY_CSR_GLBL_DQ_MSTR_DLL_BYP_EN HW_REGISTER_RW( 0x7ee07014 ) +#define DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT HW_REGISTER_RW( 0x7ee07018 ) +#define DPHY_CSR_BYTE0_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee0701c ) +#define DPHY_CSR_BYTE1_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee07020 ) +#define DPHY_CSR_BYTE2_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee07024 ) +#define DPHY_CSR_BYTE3_SLAVE_DLL_OFFSET HW_REGISTER_RW( 0x7ee07028 ) +#define DPHY_CSR_BYTE0_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee0702c ) +#define DPHY_CSR_BYTE1_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee07030 ) +#define DPHY_CSR_BYTE2_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee07034 ) +#define DPHY_CSR_BYTE3_MASTER_DLL_OUTPUT HW_REGISTER_RW( 0x7ee07038 ) +#define DPHY_CSR_NORM_READ_DQS_GATE_CTRL HW_REGISTER_RW( 0x7ee0703c ) +#define DPHY_CSR_BOOT_READ_DQS_GATE_CTRL HW_REGISTER_RW( 0x7ee07040 ) +#define DPHY_CSR_PHY_FIFO_PNTRS HW_REGISTER_RW( 0x7ee07044 ) +#define DPHY_CSR_DQ_PHY_MISC_CTRL HW_REGISTER_RW( 0x7ee07048 ) +#define DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL HW_REGISTER_RW( 0x7ee0704c ) +#define DPHY_CSR_DQ_PAD_MISC_CTRL HW_REGISTER_RW( 0x7ee07050 ) +#define DPHY_CSR_DQ_PVT_COMP_CTRL HW_REGISTER_RW( 0x7ee07054 ) +#define DPHY_CSR_DQ_PVT_COMP_OVERRD_CTRL HW_REGISTER_RW( 0x7ee07058 ) +#define DPHY_CSR_DQ_PVT_COMP_STATUS HW_REGISTER_RW( 0x7ee0705c ) +#define DPHY_CSR_DQ_PVT_COMP_DEBUG HW_REGISTER_RW( 0x7ee07060 ) +#define DPHY_CSR_DQ_PHY_READ_CTRL HW_REGISTER_RW( 0x7ee07064 ) +#define DPHY_CSR_DQ_PHY_READ_STATUS HW_REGISTER_RW( 0x7ee07068 ) +#define DPHY_CSR_DQ_SPR_RW HW_REGISTER_RW( 0x7ee0706c ) +#define DPHY_CSR_DQ_SPR1_RO HW_REGISTER_RW( 0x7ee07070 ) +#define DPHY_CSR_DQ_SPR_RO HW_REGISTER_RW( 0x7ee07074 ) +#define DPHY_CSR_CRC_CTRL HW_REGISTER_RW( 0x7ee07800 ) + #define DPHY_CSR_CRC_CTRL_MASK 0x00000111 + #define DPHY_CSR_CRC_CTRL_WIDTH 9 + #define DPHY_CSR_CRC_CTRL_RESET 0000000000 +#define DPHY_CSR_CRC_DATA HW_REGISTER_RW( 0x7ee07804 ) + #define DPHY_CSR_CRC_DATA_MASK 0x0fffffff + #define DPHY_CSR_CRC_DATA_WIDTH 28 + #define DPHY_CSR_CRC_DATA_RESET 0000000000 diff --git a/bcm2708_chip/sdhost.h b/bcm2708_chip/sdhost.h new file mode 100755 index 0000000..c985be0 --- /dev/null +++ b/bcm2708_chip/sdhost.h @@ -0,0 +1,259 @@ +// This file was generated by the create_regs script +#define SH_BASE 0x7e202000 +#define SH_CMD HW_REGISTER_RW( 0x7e202000 ) + #define SH_CMD_MASK 0x0000cfff + #define SH_CMD_WIDTH 16 + #define SH_CMD_RESET 0000000000 + #define SH_CMD_NEW_FLAG_BITS 15:15 + #define SH_CMD_NEW_FLAG_SET 0x00008000 + #define SH_CMD_NEW_FLAG_CLR 0xffff7fff + #define SH_CMD_NEW_FLAG_MSB 15 + #define SH_CMD_NEW_FLAG_LSB 15 + #define SH_CMD_FAIL_FLAG_BITS 14:14 + #define SH_CMD_FAIL_FLAG_SET 0x00004000 + #define SH_CMD_FAIL_FLAG_CLR 0xffffbfff + #define SH_CMD_FAIL_FLAG_MSB 14 + #define SH_CMD_FAIL_FLAG_LSB 14 + #define SH_CMD_BUSY_CMD_BITS 11:11 + #define SH_CMD_BUSY_CMD_SET 0x00000800 + #define SH_CMD_BUSY_CMD_CLR 0xfffff7ff + #define SH_CMD_BUSY_CMD_MSB 11 + #define SH_CMD_BUSY_CMD_LSB 11 + #define SH_CMD_NO_RESPONSE_BITS 10:10 + #define SH_CMD_NO_RESPONSE_SET 0x00000400 + #define SH_CMD_NO_RESPONSE_CLR 0xfffffbff + #define SH_CMD_NO_RESPONSE_MSB 10 + #define SH_CMD_NO_RESPONSE_LSB 10 + #define SH_CMD_LONG_RESPONSE_BITS 9:9 + #define SH_CMD_LONG_RESPONSE_SET 0x00000200 + #define SH_CMD_LONG_RESPONSE_CLR 0xfffffdff + #define SH_CMD_LONG_RESPONSE_MSB 9 + #define SH_CMD_LONG_RESPONSE_LSB 9 + #define SH_CMD_WRITE_CMD_BITS 8:7 + #define SH_CMD_WRITE_CMD_SET 0x00000180 + #define SH_CMD_WRITE_CMD_CLR 0xfffffe7f + #define SH_CMD_WRITE_CMD_MSB 8 + #define SH_CMD_WRITE_CMD_LSB 7 + #define SH_CMD_READ_CMD_BITS 6:6 + #define SH_CMD_READ_CMD_SET 0x00000040 + #define SH_CMD_READ_CMD_CLR 0xffffffbf + #define SH_CMD_READ_CMD_MSB 6 + #define SH_CMD_READ_CMD_LSB 6 + #define SH_CMD_COMMAND_BITS 5:0 + #define SH_CMD_COMMAND_SET 0x0000003f + #define SH_CMD_COMMAND_CLR 0xffffffc0 + #define SH_CMD_COMMAND_MSB 5 + #define SH_CMD_COMMAND_LSB 0 +#define SH_ARG HW_REGISTER_RW( 0x7e202004 ) + #define SH_ARG_MASK 0xffffffff + #define SH_ARG_WIDTH 32 + #define SH_ARG_RESET 0000000000 + #define SH_ARG_ARGUMENT_BITS 31:0 + #define SH_ARG_ARGUMENT_SET 0xffffffff + #define SH_ARG_ARGUMENT_CLR 0x00000000 + #define SH_ARG_ARGUMENT_MSB 31 + #define SH_ARG_ARGUMENT_LSB 0 +#define SH_TOUT HW_REGISTER_RW( 0x7e202008 ) + #define SH_TOUT_MASK 0xffffffff + #define SH_TOUT_WIDTH 32 + #define SH_TOUT_RESET 0x00a00000 + #define SH_TOUT_TIME_OUT_BITS 31:0 + #define SH_TOUT_TIME_OUT_SET 0xffffffff + #define SH_TOUT_TIME_OUT_CLR 0x00000000 + #define SH_TOUT_TIME_OUT_MSB 31 + #define SH_TOUT_TIME_OUT_LSB 0 +#define SH_CDIV HW_REGISTER_RW( 0x7e20200c ) + #define SH_CDIV_MASK 0x000007ff + #define SH_CDIV_WIDTH 11 + #define SH_CDIV_RESET 0x000001fb + #define SH_CDIV_CLOCKDIV_BITS 10:0 + #define SH_CDIV_CLOCKDIV_SET 0x000007ff + #define SH_CDIV_CLOCKDIV_CLR 0xfffff800 + #define SH_CDIV_CLOCKDIV_MSB 10 + #define SH_CDIV_CLOCKDIV_LSB 0 +#define SH_RSP0 HW_REGISTER_RO( 0x7e202010 ) + #define SH_RSP0_MASK 0xffffffff + #define SH_RSP0_WIDTH 32 + #define SH_RSP0_CARD_STATUS_BITS 31:0 + #define SH_RSP0_CARD_STATUS_SET 0xffffffff + #define SH_RSP0_CARD_STATUS_CLR 0x00000000 + #define SH_RSP0_CARD_STATUS_MSB 31 + #define SH_RSP0_CARD_STATUS_LSB 0 +#define SH_RSP1 HW_REGISTER_RO( 0x7e202014 ) + #define SH_RSP1_MASK 0xffffffff + #define SH_RSP1_WIDTH 32 + #define SH_RSP1_RESET 0000000000 + #define SH_RSP1_CID_CSD_BITS 31:0 + #define SH_RSP1_CID_CSD_SET 0xffffffff + #define SH_RSP1_CID_CSD_CLR 0x00000000 + #define SH_RSP1_CID_CSD_MSB 31 + #define SH_RSP1_CID_CSD_LSB 0 +#define SH_RSP2 HW_REGISTER_RO( 0x7e202018 ) + #define SH_RSP2_MASK 0xffffffff + #define SH_RSP2_WIDTH 32 + #define SH_RSP2_RESET 0000000000 + #define SH_RSP2_CID_CSD_BITS 31:0 + #define SH_RSP2_CID_CSD_SET 0xffffffff + #define SH_RSP2_CID_CSD_CLR 0x00000000 + #define SH_RSP2_CID_CSD_MSB 31 + #define SH_RSP2_CID_CSD_LSB 0 +#define SH_RSP3 HW_REGISTER_RO( 0x7e20201c ) + #define SH_RSP3_MASK 0xffffffff + #define SH_RSP3_WIDTH 32 + #define SH_RSP3_RESET 0000000000 + #define SH_RSP3_CID_CSD_BITS 31:0 + #define SH_RSP3_CID_CSD_SET 0xffffffff + #define SH_RSP3_CID_CSD_CLR 0x00000000 + #define SH_RSP3_CID_CSD_MSB 31 + #define SH_RSP3_CID_CSD_LSB 0 +#define SH_HSTS HW_REGISTER_RW( 0x7e202020 ) + #define SH_HSTS_MASK 0x000007f9 + #define SH_HSTS_WIDTH 11 + #define SH_HSTS_RESET 0000000000 + #define SH_HSTS_BUSY_IRPT_BITS 10:10 + #define SH_HSTS_BUSY_IRPT_SET 0x00000400 + #define SH_HSTS_BUSY_IRPT_CLR 0xfffffbff + #define SH_HSTS_BUSY_IRPT_MSB 10 + #define SH_HSTS_BUSY_IRPT_LSB 10 + #define SH_HSTS_BLOCK_IRPT_BITS 9:9 + #define SH_HSTS_BLOCK_IRPT_SET 0x00000200 + #define SH_HSTS_BLOCK_IRPT_CLR 0xfffffdff + #define SH_HSTS_BLOCK_IRPT_MSB 9 + #define SH_HSTS_BLOCK_IRPT_LSB 9 + #define SH_HSTS_SDIO_IRPT_BITS 8:8 + #define SH_HSTS_SDIO_IRPT_SET 0x00000100 + #define SH_HSTS_SDIO_IRPT_CLR 0xfffffeff + #define SH_HSTS_SDIO_IRPT_MSB 8 + #define SH_HSTS_SDIO_IRPT_LSB 8 + #define SH_HSTS_REW_TIME_OUT_BITS 7:7 + #define SH_HSTS_REW_TIME_OUT_SET 0x00000080 + #define SH_HSTS_REW_TIME_OUT_CLR 0xffffff7f + #define SH_HSTS_REW_TIME_OUT_MSB 7 + #define SH_HSTS_REW_TIME_OUT_LSB 7 + #define SH_HSTS_CMD_TIME_OUT_BITS 6:6 + #define SH_HSTS_CMD_TIME_OUT_SET 0x00000040 + #define SH_HSTS_CMD_TIME_OUT_CLR 0xffffffbf + #define SH_HSTS_CMD_TIME_OUT_MSB 6 + #define SH_HSTS_CMD_TIME_OUT_LSB 6 + #define SH_HSTS_CRC16_ERROR_BITS 5:5 + #define SH_HSTS_CRC16_ERROR_SET 0x00000020 + #define SH_HSTS_CRC16_ERROR_CLR 0xffffffdf + #define SH_HSTS_CRC16_ERROR_MSB 5 + #define SH_HSTS_CRC16_ERROR_LSB 5 + #define SH_HSTS_CRC7_ERROR_BITS 4:4 + #define SH_HSTS_CRC7_ERROR_SET 0x00000010 + #define SH_HSTS_CRC7_ERROR_CLR 0xffffffef + #define SH_HSTS_CRC7_ERROR_MSB 4 + #define SH_HSTS_CRC7_ERROR_LSB 4 + #define SH_HSTS_FIFO_ERROR_BITS 3:3 + #define SH_HSTS_FIFO_ERROR_SET 0x00000008 + #define SH_HSTS_FIFO_ERROR_CLR 0xfffffff7 + #define SH_HSTS_FIFO_ERROR_MSB 3 + #define SH_HSTS_FIFO_ERROR_LSB 3 + #define SH_HSTS_DATA_FLAG_BITS 0:0 + #define SH_HSTS_DATA_FLAG_SET 0x00000001 + #define SH_HSTS_DATA_FLAG_CLR 0xfffffffe + #define SH_HSTS_DATA_FLAG_MSB 0 + #define SH_HSTS_DATA_FLAG_LSB 0 +#define SH_VDD HW_REGISTER_RW( 0x7e202030 ) + #define SH_VDD_MASK 0x00000001 + #define SH_VDD_WIDTH 1 + #define SH_VDD_RESET 0000000000 + #define SH_VDD_POWER_ON_BITS 0:0 + #define SH_VDD_POWER_ON_SET 0x00000001 + #define SH_VDD_POWER_ON_CLR 0xfffffffe + #define SH_VDD_POWER_ON_MSB 0 + #define SH_VDD_POWER_ON_LSB 0 +#define SH_EDM HW_REGISTER_RW( 0x7e202034 ) + #define SH_EDM_MASK 0x0007ffff + #define SH_EDM_WIDTH 19 + #define SH_EDM_READ_THRESHOLD_BITS 18:14 + #define SH_EDM_READ_THRESHOLD_SET 0x0007c000 + #define SH_EDM_READ_THRESHOLD_CLR 0xfff83fff + #define SH_EDM_READ_THRESHOLD_MSB 18 + #define SH_EDM_READ_THRESHOLD_LSB 14 + #define SH_EDM_WRITE_THRESHOLD_BITS 13:9 + #define SH_EDM_WRITE_THRESHOLD_SET 0x00003e00 + #define SH_EDM_WRITE_THRESHOLD_CLR 0xffffc1ff + #define SH_EDM_WRITE_THRESHOLD_MSB 13 + #define SH_EDM_WRITE_THRESHOLD_LSB 9 + #define SH_EDM_FIFO_COUNT_BITS 8:4 + #define SH_EDM_FIFO_COUNT_SET 0x000001f0 + #define SH_EDM_FIFO_COUNT_CLR 0xfffffe0f + #define SH_EDM_FIFO_COUNT_MSB 8 + #define SH_EDM_FIFO_COUNT_LSB 4 + #define SH_EDM_STATE_MACHINE_BITS 3:0 + #define SH_EDM_STATE_MACHINE_SET 0x0000000f + #define SH_EDM_STATE_MACHINE_CLR 0xfffffff0 + #define SH_EDM_STATE_MACHINE_MSB 3 + #define SH_EDM_STATE_MACHINE_LSB 0 +#define SH_HCFG HW_REGISTER_RW( 0x7e202038 ) + #define SH_HCFG_MASK 0x0000073f + #define SH_HCFG_WIDTH 11 + #define SH_HCFG_RESET 0000000000 + #define SH_HCFG_BUSY_IRPT_EN_BITS 10:10 + #define SH_HCFG_BUSY_IRPT_EN_SET 0x00000400 + #define SH_HCFG_BUSY_IRPT_EN_CLR 0xfffffbff + #define SH_HCFG_BUSY_IRPT_EN_MSB 10 + #define SH_HCFG_BUSY_IRPT_EN_LSB 10 + #define SH_HCFG_BLOCK_IRPT_EN_BITS 8:8 + #define SH_HCFG_BLOCK_IRPT_EN_SET 0x00000100 + #define SH_HCFG_BLOCK_IRPT_EN_CLR 0xfffffeff + #define SH_HCFG_BLOCK_IRPT_EN_MSB 8 + #define SH_HCFG_BLOCK_IRPT_EN_LSB 8 + #define SH_HCFG_SDIO_IRPT_EN_BITS 5:5 + #define SH_HCFG_SDIO_IRPT_EN_SET 0x00000020 + #define SH_HCFG_SDIO_IRPT_EN_CLR 0xffffffdf + #define SH_HCFG_SDIO_IRPT_EN_MSB 5 + #define SH_HCFG_SDIO_IRPT_EN_LSB 5 + #define SH_HCFG_DATA_IRPT_EN_BITS 4:4 + #define SH_HCFG_DATA_IRPT_EN_SET 0x00000010 + #define SH_HCFG_DATA_IRPT_EN_CLR 0xffffffef + #define SH_HCFG_DATA_IRPT_EN_MSB 4 + #define SH_HCFG_DATA_IRPT_EN_LSB 4 + #define SH_HCFG_SLOW_CARD_BITS 3:3 + #define SH_HCFG_SLOW_CARD_SET 0x00000008 + #define SH_HCFG_SLOW_CARD_CLR 0xfffffff7 + #define SH_HCFG_SLOW_CARD_MSB 3 + #define SH_HCFG_SLOW_CARD_LSB 3 + #define SH_HCFG_WIDE_EXT_BUS_BITS 2:2 + #define SH_HCFG_WIDE_EXT_BUS_SET 0x00000004 + #define SH_HCFG_WIDE_EXT_BUS_CLR 0xfffffffb + #define SH_HCFG_WIDE_EXT_BUS_MSB 2 + #define SH_HCFG_WIDE_EXT_BUS_LSB 2 + #define SH_HCFG_WIDE_INT_BUS_BITS 1:1 + #define SH_HCFG_WIDE_INT_BUS_SET 0x00000002 + #define SH_HCFG_WIDE_INT_BUS_CLR 0xfffffffd + #define SH_HCFG_WIDE_INT_BUS_MSB 1 + #define SH_HCFG_WIDE_INT_BUS_LSB 1 + #define SH_HCFG_REL_CMD_LINE_BITS 0:0 + #define SH_HCFG_REL_CMD_LINE_SET 0x00000001 + #define SH_HCFG_REL_CMD_LINE_CLR 0xfffffffe + #define SH_HCFG_REL_CMD_LINE_MSB 0 + #define SH_HCFG_REL_CMD_LINE_LSB 0 +#define SH_HBCT HW_REGISTER_RW( 0x7e20203c ) + #define SH_HBCT_MASK 0xffffffff + #define SH_HBCT_WIDTH 32 + #define SH_HBCT_RESET 0x00000400 + #define SH_HBCT_BYTECOUNT_BITS 31:0 + #define SH_HBCT_BYTECOUNT_SET 0xffffffff + #define SH_HBCT_BYTECOUNT_CLR 0x00000000 + #define SH_HBCT_BYTECOUNT_MSB 31 + #define SH_HBCT_BYTECOUNT_LSB 0 +#define SH_DATA HW_REGISTER_RW( 0x7e202040 ) + #define SH_DATA_MASK 0xffffffff + #define SH_DATA_WIDTH 32 + #define SH_DATA_DATA_BITS 31:0 + #define SH_DATA_DATA_SET 0xffffffff + #define SH_DATA_DATA_CLR 0x00000000 + #define SH_DATA_DATA_MSB 31 + #define SH_DATA_DATA_LSB 0 +#define SH_HBLC HW_REGISTER_RW( 0x7e202050 ) + #define SH_HBLC_MASK 0x0000ffff + #define SH_HBLC_WIDTH 16 + #define SH_HBLC_RESET 0000000000 + #define SH_HBLC_BLOCKCOUNT_BITS 8:0 + #define SH_HBLC_BLOCKCOUNT_SET 0x000001ff + #define SH_HBLC_BLOCKCOUNT_CLR 0xfffffe00 + #define SH_HBLC_BLOCKCOUNT_MSB 8 + #define SH_HBLC_BLOCKCOUNT_LSB 0 diff --git a/bcm2708_chip/slimbus.h b/bcm2708_chip/slimbus.h new file mode 100755 index 0000000..94d8806 --- /dev/null +++ b/bcm2708_chip/slimbus.h @@ -0,0 +1,311 @@ +// This file was generated by the create_regs script +#define SLIM_BASE 0x7e210000 +#define SLIM_APB_ID 0x736c696d +#define SLIM_CON HW_REGISTER_RW( 0x7e210000 ) + #define SLIM_CON_MASK 0xfffff0ff + #define SLIM_CON_WIDTH 32 + #define SLIM_CON_RESET 0x000000c1 +#define SLIM_CON2 HW_REGISTER_RW( 0x7e210004 ) + #define SLIM_CON2_MASK 0xff008001 + #define SLIM_CON2_WIDTH 32 + #define SLIM_CON2_RESET 0000000000 +#define SLIM_STAT HW_REGISTER_RW( 0x7e210008 ) + #define SLIM_STAT_MASK 0x03ffffff + #define SLIM_STAT_WIDTH 26 + #define SLIM_STAT_RESET 0000000000 +#define SLIM_FS HW_REGISTER_RW( 0x7e21000c ) + #define SLIM_FS_MASK 0x00003fff + #define SLIM_FS_WIDTH 14 + #define SLIM_FS_RESET 0000000000 +#define SLIM_EA0 HW_REGISTER_RW( 0x7e210010 ) + #define SLIM_EA0_MASK 0xffff00ff + #define SLIM_EA0_WIDTH 32 + #define SLIM_EA0_RESET 0000000000 +#define SLIM_EA1 HW_REGISTER_RW( 0x7e210014 ) + #define SLIM_EA1_MASK 0x8000ffff + #define SLIM_EA1_WIDTH 32 + #define SLIM_EA1_RESET 0000000000 +#define SLIM_DMA_MC_RX HW_REGISTER_RW( 0x7e210020 ) + #define SLIM_DMA_MC_RX_MASK 0xffffffff + #define SLIM_DMA_MC_RX_WIDTH 32 + #define SLIM_DMA_MC_RX_RESET 0000000000 +#define SLIM_DMA_MC_TX HW_REGISTER_RW( 0x7e210024 ) + #define SLIM_DMA_MC_TX_MASK 0xffffffff + #define SLIM_DMA_MC_TX_WIDTH 32 + #define SLIM_DMA_MC_TX_RESET 0000000000 +#define SLIM_DMA_DC0 HW_REGISTER_RW( 0x7e210030 ) + #define SLIM_DMA_DC0_MASK 0xffffffff + #define SLIM_DMA_DC0_WIDTH 32 + #define SLIM_DMA_DC0_RESET 0000000000 +#define SLIM_DMA_DC1 HW_REGISTER_RW( 0x7e210034 ) + #define SLIM_DMA_DC1_MASK 0xffffffff + #define SLIM_DMA_DC1_WIDTH 32 + #define SLIM_DMA_DC1_RESET 0000000000 +#define SLIM_DMA_DC2 HW_REGISTER_RW( 0x7e210038 ) + #define SLIM_DMA_DC2_MASK 0xffffffff + #define SLIM_DMA_DC2_WIDTH 32 + #define SLIM_DMA_DC2_RESET 0000000000 +#define SLIM_DMA_DC3 HW_REGISTER_RW( 0x7e21003c ) + #define SLIM_DMA_DC3_MASK 0xffffffff + #define SLIM_DMA_DC3_WIDTH 32 + #define SLIM_DMA_DC3_RESET 0000000000 +#define SLIM_DMA_DC4 HW_REGISTER_RW( 0x7e210040 ) + #define SLIM_DMA_DC4_MASK 0xffffffff + #define SLIM_DMA_DC4_WIDTH 32 + #define SLIM_DMA_DC4_RESET 0000000000 +#define SLIM_DMA_DC5 HW_REGISTER_RW( 0x7e210044 ) + #define SLIM_DMA_DC5_MASK 0xffffffff + #define SLIM_DMA_DC5_WIDTH 32 + #define SLIM_DMA_DC5_RESET 0000000000 +#define SLIM_DMA_DC6 HW_REGISTER_RW( 0x7e210048 ) + #define SLIM_DMA_DC6_MASK 0xffffffff + #define SLIM_DMA_DC6_WIDTH 32 + #define SLIM_DMA_DC6_RESET 0000000000 +#define SLIM_DMA_DC7 HW_REGISTER_RW( 0x7e21004c ) + #define SLIM_DMA_DC7_MASK 0xffffffff + #define SLIM_DMA_DC7_WIDTH 32 + #define SLIM_DMA_DC7_RESET 0000000000 +#define SLIM_DMA_DC8 HW_REGISTER_RW( 0x7e210050 ) + #define SLIM_DMA_DC8_MASK 0xffffffff + #define SLIM_DMA_DC8_WIDTH 32 + #define SLIM_DMA_DC8_RESET 0000000000 +#define SLIM_DMA_DC9 HW_REGISTER_RW( 0x7e210054 ) + #define SLIM_DMA_DC9_MASK 0xffffffff + #define SLIM_DMA_DC9_WIDTH 32 + #define SLIM_DMA_DC9_RESET 0000000000 +#define SLIM_DMA_MC_CON HW_REGISTER_RW( 0x7e210080 ) + #define SLIM_DMA_MC_CON_MASK 0x00000003 + #define SLIM_DMA_MC_CON_WIDTH 2 + #define SLIM_DMA_MC_CON_RESET 0000000000 +#define SLIM_DMA_DC_CON HW_REGISTER_RW( 0x7e210084 ) + #define SLIM_DMA_DC_CON_MASK 0x000fffff + #define SLIM_DMA_DC_CON_WIDTH 20 + #define SLIM_DMA_DC_CON_RESET 0000000000 +#define SLIM_DMA_MC_STAT HW_REGISTER_RW( 0x7e210088 ) + #define SLIM_DMA_MC_STAT_MASK 0x0000000f + #define SLIM_DMA_MC_STAT_WIDTH 4 + #define SLIM_DMA_MC_STAT_RESET 0000000000 +#define SLIM_DMA_DC_STAT_0 HW_REGISTER_RW( 0x7e21008c ) + #define SLIM_DMA_DC_STAT_0_MASK 0xffffffff + #define SLIM_DMA_DC_STAT_0_WIDTH 32 + #define SLIM_DMA_DC_STAT_0_RESET 0000000000 +#define SLIM_DMA_DC_STAT_1 HW_REGISTER_RW( 0x7e210090 ) + #define SLIM_DMA_DC_STAT_1_MASK 0x000f000f + #define SLIM_DMA_DC_STAT_1_WIDTH 20 + #define SLIM_DMA_DC_STAT_1_RESET 0000000000 +#define SLIM_MC_IN_CON HW_REGISTER_RW( 0x7e210100 ) + #define SLIM_MC_IN_CON_MASK 0x00000f1d + #define SLIM_MC_IN_CON_WIDTH 12 + #define SLIM_MC_IN_CON_RESET 0000000000 +#define SLIM_MC_IN_STAT HW_REGISTER_RW( 0x7e210104 ) + #define SLIM_MC_IN_STAT_MASK 0x0000000f + #define SLIM_MC_IN_STAT_WIDTH 4 + #define SLIM_MC_IN_STAT_RESET 0000000000 +#define SLIM_MC_OUT_CON HW_REGISTER_RW( 0x7e210120 ) + #define SLIM_MC_OUT_CON_MASK 0x00000048 + #define SLIM_MC_OUT_CON_WIDTH 7 + #define SLIM_MC_OUT_CON_RESET 0000000000 +#define SLIM_MC_OUT_STAT HW_REGISTER_RW( 0x7e210124 ) + #define SLIM_MC_OUT_STAT_MASK 0x00000008 + #define SLIM_MC_OUT_STAT_WIDTH 4 + #define SLIM_MC_OUT_STAT_RESET 0000000000 +#define SLIM_DCC0_PA0 HW_REGISTER_RW( 0x7e210200 ) + #define SLIM_DCC0_PA0_MASK 0x00ffff1f + #define SLIM_DCC0_PA0_WIDTH 24 + #define SLIM_DCC0_PA0_RESET 0000000000 +#define SLIM_DCC0_PA1 HW_REGISTER_RW( 0x7e210204 ) + #define SLIM_DCC0_PA1_MASK 0x00ffff3f + #define SLIM_DCC0_PA1_WIDTH 24 + #define SLIM_DCC0_PA1_RESET 0000000000 +#define SLIM_DCC0_CON HW_REGISTER_RW( 0x7e210208 ) + #define SLIM_DCC0_CON_MASK 0xffff0070 + #define SLIM_DCC0_CON_WIDTH 32 + #define SLIM_DCC0_CON_RESET 0000000000 +#define SLIM_DCC0_STAT HW_REGISTER_RW( 0x7e21020c ) + #define SLIM_DCC0_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC0_STAT_WIDTH 32 + #define SLIM_DCC0_STAT_RESET 0000000000 +#define SLIM_DCC0_PROT HW_REGISTER_RW( 0x7e210210 ) + #define SLIM_DCC0_PROT_MASK 0xc001ffff + #define SLIM_DCC0_PROT_WIDTH 32 + #define SLIM_DCC0_PROT_RESET 0x000093a0 +#define SLIM_DCC1_PA0 HW_REGISTER_RW( 0x7e210220 ) + #define SLIM_DCC1_PA0_MASK 0x00ffff1f + #define SLIM_DCC1_PA0_WIDTH 24 + #define SLIM_DCC1_PA0_RESET 0000000000 +#define SLIM_DCC1_PA1 HW_REGISTER_RW( 0x7e210224 ) + #define SLIM_DCC1_PA1_MASK 0x00ffff3f + #define SLIM_DCC1_PA1_WIDTH 24 + #define SLIM_DCC1_PA1_RESET 0000000000 +#define SLIM_DCC1_CON HW_REGISTER_RW( 0x7e210228 ) + #define SLIM_DCC1_CON_MASK 0xffff0070 + #define SLIM_DCC1_CON_WIDTH 32 + #define SLIM_DCC1_CON_RESET 0000000000 +#define SLIM_DCC1_STAT HW_REGISTER_RW( 0x7e21022c ) + #define SLIM_DCC1_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC1_STAT_WIDTH 32 + #define SLIM_DCC1_STAT_RESET 0000000000 +#define SLIM_DCC1_PROT HW_REGISTER_RW( 0x7e210230 ) + #define SLIM_DCC1_PROT_MASK 0xc001ffff + #define SLIM_DCC1_PROT_WIDTH 32 + #define SLIM_DCC1_PROT_RESET 0x000093a0 +#define SLIM_DCC2_PA0 HW_REGISTER_RW( 0x7e210240 ) + #define SLIM_DCC2_PA0_MASK 0x00ffff1f + #define SLIM_DCC2_PA0_WIDTH 24 + #define SLIM_DCC2_PA0_RESET 0000000000 +#define SLIM_DCC2_PA1 HW_REGISTER_RW( 0x7e210244 ) + #define SLIM_DCC2_PA1_MASK 0x00ffff3f + #define SLIM_DCC2_PA1_WIDTH 24 + #define SLIM_DCC2_PA1_RESET 0000000000 +#define SLIM_DCC2_CON HW_REGISTER_RW( 0x7e210248 ) + #define SLIM_DCC2_CON_MASK 0xffff0070 + #define SLIM_DCC2_CON_WIDTH 32 + #define SLIM_DCC2_CON_RESET 0000000000 +#define SLIM_DCC2_STAT HW_REGISTER_RW( 0x7e21024c ) + #define SLIM_DCC2_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC2_STAT_WIDTH 32 + #define SLIM_DCC2_STAT_RESET 0000000000 +#define SLIM_DCC2_PROT HW_REGISTER_RW( 0x7e210250 ) + #define SLIM_DCC2_PROT_MASK 0xc001ffff + #define SLIM_DCC2_PROT_WIDTH 32 + #define SLIM_DCC2_PROT_RESET 0x000093a0 +#define SLIM_DCC3_PA0 HW_REGISTER_RW( 0x7e210260 ) + #define SLIM_DCC3_PA0_MASK 0x00ffff1f + #define SLIM_DCC3_PA0_WIDTH 24 + #define SLIM_DCC3_PA0_RESET 0000000000 +#define SLIM_DCC3_PA1 HW_REGISTER_RW( 0x7e210264 ) + #define SLIM_DCC3_PA1_MASK 0x00ffff3f + #define SLIM_DCC3_PA1_WIDTH 24 + #define SLIM_DCC3_PA1_RESET 0000000000 +#define SLIM_DCC3_CON HW_REGISTER_RW( 0x7e210268 ) + #define SLIM_DCC3_CON_MASK 0xffff0070 + #define SLIM_DCC3_CON_WIDTH 32 + #define SLIM_DCC3_CON_RESET 0000000000 +#define SLIM_DCC3_STAT HW_REGISTER_RW( 0x7e21026c ) + #define SLIM_DCC3_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC3_STAT_WIDTH 32 + #define SLIM_DCC3_STAT_RESET 0000000000 +#define SLIM_DCC3_PROT HW_REGISTER_RW( 0x7e210270 ) + #define SLIM_DCC3_PROT_MASK 0xc001ffff + #define SLIM_DCC3_PROT_WIDTH 32 + #define SLIM_DCC3_PROT_RESET 0x000093a0 +#define SLIM_DCC4_PA0 HW_REGISTER_RW( 0x7e210280 ) + #define SLIM_DCC4_PA0_MASK 0x00ffff1f + #define SLIM_DCC4_PA0_WIDTH 24 + #define SLIM_DCC4_PA0_RESET 0000000000 +#define SLIM_DCC4_PA1 HW_REGISTER_RW( 0x7e210284 ) + #define SLIM_DCC4_PA1_MASK 0x00ffff3f + #define SLIM_DCC4_PA1_WIDTH 24 + #define SLIM_DCC4_PA1_RESET 0000000000 +#define SLIM_DCC4_CON HW_REGISTER_RW( 0x7e210288 ) + #define SLIM_DCC4_CON_MASK 0xffff0070 + #define SLIM_DCC4_CON_WIDTH 32 + #define SLIM_DCC4_CON_RESET 0000000000 +#define SLIM_DCC4_STAT HW_REGISTER_RW( 0x7e21028c ) + #define SLIM_DCC4_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC4_STAT_WIDTH 32 + #define SLIM_DCC4_STAT_RESET 0000000000 +#define SLIM_DCC4_PROT HW_REGISTER_RW( 0x7e210290 ) + #define SLIM_DCC4_PROT_MASK 0xc001ffff + #define SLIM_DCC4_PROT_WIDTH 32 + #define SLIM_DCC4_PROT_RESET 0x000093a0 +#define SLIM_DCC5_PA0 HW_REGISTER_RW( 0x7e2102a0 ) + #define SLIM_DCC5_PA0_MASK 0x00ffff1f + #define SLIM_DCC5_PA0_WIDTH 24 + #define SLIM_DCC5_PA0_RESET 0000000000 +#define SLIM_DCC5_PA1 HW_REGISTER_RW( 0x7e2102a4 ) + #define SLIM_DCC5_PA1_MASK 0x00ffff3f + #define SLIM_DCC5_PA1_WIDTH 24 + #define SLIM_DCC5_PA1_RESET 0000000000 +#define SLIM_DCC5_CON HW_REGISTER_RW( 0x7e2102a8 ) + #define SLIM_DCC5_CON_MASK 0xffff0070 + #define SLIM_DCC5_CON_WIDTH 32 + #define SLIM_DCC5_CON_RESET 0000000000 +#define SLIM_DCC5_STAT HW_REGISTER_RW( 0x7e2102ac ) + #define SLIM_DCC5_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC5_STAT_WIDTH 32 + #define SLIM_DCC5_STAT_RESET 0000000000 +#define SLIM_DCC5_PROT HW_REGISTER_RW( 0x7e2102b0 ) + #define SLIM_DCC5_PROT_MASK 0xc001ffff + #define SLIM_DCC5_PROT_WIDTH 32 + #define SLIM_DCC5_PROT_RESET 0x000093a0 +#define SLIM_DCC6_PA0 HW_REGISTER_RW( 0x7e2102c0 ) + #define SLIM_DCC6_PA0_MASK 0x00ffff1f + #define SLIM_DCC6_PA0_WIDTH 24 + #define SLIM_DCC6_PA0_RESET 0000000000 +#define SLIM_DCC6_PA1 HW_REGISTER_RW( 0x7e2102c4 ) + #define SLIM_DCC6_PA1_MASK 0x00ffff3f + #define SLIM_DCC6_PA1_WIDTH 24 + #define SLIM_DCC6_PA1_RESET 0000000000 +#define SLIM_DCC6_CON HW_REGISTER_RW( 0x7e2102c8 ) + #define SLIM_DCC6_CON_MASK 0xffff0070 + #define SLIM_DCC6_CON_WIDTH 32 + #define SLIM_DCC6_CON_RESET 0000000000 +#define SLIM_DCC6_STAT HW_REGISTER_RW( 0x7e2102cc ) + #define SLIM_DCC6_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC6_STAT_WIDTH 32 + #define SLIM_DCC6_STAT_RESET 0000000000 +#define SLIM_DCC6_PROT HW_REGISTER_RW( 0x7e2102d0 ) + #define SLIM_DCC6_PROT_MASK 0xc001ffff + #define SLIM_DCC6_PROT_WIDTH 32 + #define SLIM_DCC6_PROT_RESET 0x000093a0 +#define SLIM_DCC7_PA0 HW_REGISTER_RW( 0x7e2102e0 ) + #define SLIM_DCC7_PA0_MASK 0x00ffff1f + #define SLIM_DCC7_PA0_WIDTH 24 + #define SLIM_DCC7_PA0_RESET 0000000000 +#define SLIM_DCC7_PA1 HW_REGISTER_RW( 0x7e2102e4 ) + #define SLIM_DCC7_PA1_MASK 0x00ffff3f + #define SLIM_DCC7_PA1_WIDTH 24 + #define SLIM_DCC7_PA1_RESET 0000000000 +#define SLIM_DCC7_CON HW_REGISTER_RW( 0x7e2102e8 ) + #define SLIM_DCC7_CON_MASK 0xffff0070 + #define SLIM_DCC7_CON_WIDTH 32 + #define SLIM_DCC7_CON_RESET 0000000000 +#define SLIM_DCC7_STAT HW_REGISTER_RW( 0x7e2102ec ) + #define SLIM_DCC7_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC7_STAT_WIDTH 32 + #define SLIM_DCC7_STAT_RESET 0000000000 +#define SLIM_DCC7_PROT HW_REGISTER_RW( 0x7e2102f0 ) + #define SLIM_DCC7_PROT_MASK 0xc001ffff + #define SLIM_DCC7_PROT_WIDTH 32 + #define SLIM_DCC7_PROT_RESET 0x000093a0 +#define SLIM_DCC8_PA0 HW_REGISTER_RW( 0x7e210300 ) + #define SLIM_DCC8_PA0_MASK 0x00ffff1f + #define SLIM_DCC8_PA0_WIDTH 24 + #define SLIM_DCC8_PA0_RESET 0000000000 +#define SLIM_DCC8_PA1 HW_REGISTER_RW( 0x7e210304 ) + #define SLIM_DCC8_PA1_MASK 0x00ffff3f + #define SLIM_DCC8_PA1_WIDTH 24 + #define SLIM_DCC8_PA1_RESET 0000000000 +#define SLIM_DCC8_CON HW_REGISTER_RW( 0x7e210308 ) + #define SLIM_DCC8_CON_MASK 0xffff0070 + #define SLIM_DCC8_CON_WIDTH 32 + #define SLIM_DCC8_CON_RESET 0000000000 +#define SLIM_DCC8_STAT HW_REGISTER_RW( 0x7e21030c ) + #define SLIM_DCC8_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC8_STAT_WIDTH 32 + #define SLIM_DCC8_STAT_RESET 0000000000 +#define SLIM_DCC8_PROT HW_REGISTER_RW( 0x7e210310 ) + #define SLIM_DCC8_PROT_MASK 0xc001ffff + #define SLIM_DCC8_PROT_WIDTH 32 + #define SLIM_DCC8_PROT_RESET 0x000093a0 +#define SLIM_DCC9_PA0 HW_REGISTER_RW( 0x7e210320 ) + #define SLIM_DCC9_PA0_MASK 0x00ffff1f + #define SLIM_DCC9_PA0_WIDTH 24 + #define SLIM_DCC9_PA0_RESET 0000000000 +#define SLIM_DCC9_PA1 HW_REGISTER_RW( 0x7e210324 ) + #define SLIM_DCC9_PA1_MASK 0x00ffff3f + #define SLIM_DCC9_PA1_WIDTH 24 + #define SLIM_DCC9_PA1_RESET 0000000000 +#define SLIM_DCC9_CON HW_REGISTER_RW( 0x7e210328 ) + #define SLIM_DCC9_CON_MASK 0xffff0070 + #define SLIM_DCC9_CON_WIDTH 32 + #define SLIM_DCC9_CON_RESET 0000000000 +#define SLIM_DCC9_STAT HW_REGISTER_RW( 0x7e21032c ) + #define SLIM_DCC9_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC9_STAT_WIDTH 32 + #define SLIM_DCC9_STAT_RESET 0000000000 +#define SLIM_DCC9_PROT HW_REGISTER_RW( 0x7e210330 ) + #define SLIM_DCC9_PROT_MASK 0xc001ffff + #define SLIM_DCC9_PROT_WIDTH 32 + #define SLIM_DCC9_PROT_RESET 0x000093a0 diff --git a/bcm2708_chip/slimbus_a0.h b/bcm2708_chip/slimbus_a0.h new file mode 100755 index 0000000..17562bb --- /dev/null +++ b/bcm2708_chip/slimbus_a0.h @@ -0,0 +1,227 @@ +// This file was generated by the create_regs script +#define SLIM_BASE 0x7e210000 +#define SLIM_APB_ID 0x736c696d +#define SLIM_CON HW_REGISTER_RW( 0x7e210000 ) + #define SLIM_CON_MASK 0xffffffff + #define SLIM_CON_WIDTH 32 + #define SLIM_CON_RESET 0x000005c1 +#define SLIM_STAT HW_REGISTER_RW( 0x7e210004 ) + #define SLIM_STAT_MASK 0x03ffffff + #define SLIM_STAT_WIDTH 26 + #define SLIM_STAT_RESET 0000000000 +#define SLIM_FS HW_REGISTER_RW( 0x7e210008 ) + #define SLIM_FS_MASK 0x00003fff + #define SLIM_FS_WIDTH 14 + #define SLIM_FS_RESET 0000000000 +#define SLIM_CON2 HW_REGISTER_RW( 0x7e210008 ) + #define SLIM_CON2_MASK 0x00000001 + #define SLIM_CON2_WIDTH 1 + #define SLIM_CON2_RESET 0000000000 +#define SLIM_DMA_SMC_RX HW_REGISTER_RW( 0x7e210010 ) + #define SLIM_DMA_SMC_RX_MASK 0xffffffff + #define SLIM_DMA_SMC_RX_WIDTH 32 + #define SLIM_DMA_SMC_RX_RESET 0000000000 +#define SLIM_DMA_SMC_TX HW_REGISTER_RW( 0x7e210014 ) + #define SLIM_DMA_SMC_TX_MASK 0xffffffff + #define SLIM_DMA_SMC_TX_WIDTH 32 + #define SLIM_DMA_SMC_TX_RESET 0000000000 +#define SLIM_DMA_DC_RX HW_REGISTER_RW( 0x7e210018 ) + #define SLIM_DMA_DC_RX_MASK 0xffffffff + #define SLIM_DMA_DC_RX_WIDTH 32 + #define SLIM_DMA_DC_RX_RESET 0000000000 +#define SLIM_DMA_DC_TX HW_REGISTER_RW( 0x7e21001c ) + #define SLIM_DMA_DC_TX_MASK 0xffffffff + #define SLIM_DMA_DC_TX_WIDTH 32 + #define SLIM_DMA_DC_TX_RESET 0000000000 +#define SLIM_DMA_CON HW_REGISTER_RW( 0x7e210020 ) + #define SLIM_DMA_CON_MASK 0x0000000f + #define SLIM_DMA_CON_WIDTH 4 + #define SLIM_DMA_CON_RESET 0000000000 +#define SLIM_DMA_STAT HW_REGISTER_RW( 0x7e210024 ) + #define SLIM_DMA_STAT_MASK 0x000000ff + #define SLIM_DMA_STAT_WIDTH 8 + #define SLIM_DMA_STAT_RESET 0000000000 +#define SLIM_EA0 HW_REGISTER_RW( 0x7e210030 ) + #define SLIM_EA0_MASK 0xffff00ff + #define SLIM_EA0_WIDTH 32 + #define SLIM_EA0_RESET 0000000000 +#define SLIM_EA1 HW_REGISTER_RW( 0x7e210034 ) + #define SLIM_EA1_MASK 0x8000ffff + #define SLIM_EA1_WIDTH 32 + #define SLIM_EA1_RESET 0000000000 +#define SLIM_SMC_IN_CON HW_REGISTER_RW( 0x7e210100 ) + #define SLIM_SMC_IN_CON_MASK 0x00000f0f + #define SLIM_SMC_IN_CON_WIDTH 12 + #define SLIM_SMC_IN_CON_RESET 0000000000 +#define SLIM_SMC_IN_STAT HW_REGISTER_RW( 0x7e210104 ) + #define SLIM_SMC_IN_STAT_MASK 0x0000000f + #define SLIM_SMC_IN_STAT_WIDTH 4 + #define SLIM_SMC_IN_STAT_RESET 0000000000 +#define SLIM_SMC_OUT_CON HW_REGISTER_RW( 0x7e210120 ) + #define SLIM_SMC_OUT_CON_MASK 0x000000c8 + #define SLIM_SMC_OUT_CON_WIDTH 8 + #define SLIM_SMC_OUT_CON_RESET 0000000000 +#define SLIM_SMC_OUT_STAT HW_REGISTER_RW( 0x7e210124 ) + #define SLIM_SMC_OUT_STAT_MASK 0x0000000c + #define SLIM_SMC_OUT_STAT_WIDTH 4 + #define SLIM_SMC_OUT_STAT_RESET 0000000000 +#define SLIM_DCC0_PA0 HW_REGISTER_RW( 0x7e210200 ) + #define SLIM_DCC0_PA0_MASK 0x00ffff1f + #define SLIM_DCC0_PA0_WIDTH 24 + #define SLIM_DCC0_PA0_RESET 0000000000 +#define SLIM_DCC0_PA1 HW_REGISTER_RW( 0x7e210204 ) + #define SLIM_DCC0_PA1_MASK 0x00ffff3f + #define SLIM_DCC0_PA1_WIDTH 24 + #define SLIM_DCC0_PA1_RESET 0000000000 +#define SLIM_DCC0_CON HW_REGISTER_RW( 0x7e210208 ) + #define SLIM_DCC0_CON_MASK 0xffff0073 + #define SLIM_DCC0_CON_WIDTH 32 + #define SLIM_DCC0_CON_RESET 0000000000 +#define SLIM_DCC0_STAT HW_REGISTER_RW( 0x7e21020c ) + #define SLIM_DCC0_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC0_STAT_WIDTH 32 + #define SLIM_DCC0_STAT_RESET 0000000000 +#define SLIM_DCC1_PA0 HW_REGISTER_RW( 0x7e210220 ) + #define SLIM_DCC1_PA0_MASK 0x00ffff1f + #define SLIM_DCC1_PA0_WIDTH 24 + #define SLIM_DCC1_PA0_RESET 0000000000 +#define SLIM_DCC1_PA1 HW_REGISTER_RW( 0x7e210224 ) + #define SLIM_DCC1_PA1_MASK 0x00ffff3f + #define SLIM_DCC1_PA1_WIDTH 24 + #define SLIM_DCC1_PA1_RESET 0000000000 +#define SLIM_DCC1_CON HW_REGISTER_RW( 0x7e210228 ) + #define SLIM_DCC1_CON_MASK 0xffff0073 + #define SLIM_DCC1_CON_WIDTH 32 + #define SLIM_DCC1_CON_RESET 0000000000 +#define SLIM_DCC1_STAT HW_REGISTER_RW( 0x7e21022c ) + #define SLIM_DCC1_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC1_STAT_WIDTH 32 + #define SLIM_DCC1_STAT_RESET 0000000000 +#define SLIM_DCC2_PA0 HW_REGISTER_RW( 0x7e210240 ) + #define SLIM_DCC2_PA0_MASK 0x00ffff1f + #define SLIM_DCC2_PA0_WIDTH 24 + #define SLIM_DCC2_PA0_RESET 0000000000 +#define SLIM_DCC2_PA1 HW_REGISTER_RW( 0x7e210244 ) + #define SLIM_DCC2_PA1_MASK 0x00ffff3f + #define SLIM_DCC2_PA1_WIDTH 24 + #define SLIM_DCC2_PA1_RESET 0000000000 +#define SLIM_DCC2_CON HW_REGISTER_RW( 0x7e210248 ) + #define SLIM_DCC2_CON_MASK 0xffff0073 + #define SLIM_DCC2_CON_WIDTH 32 + #define SLIM_DCC2_CON_RESET 0000000000 +#define SLIM_DCC2_STAT HW_REGISTER_RW( 0x7e21024c ) + #define SLIM_DCC2_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC2_STAT_WIDTH 32 + #define SLIM_DCC2_STAT_RESET 0000000000 +#define SLIM_DCC3_PA0 HW_REGISTER_RW( 0x7e210260 ) + #define SLIM_DCC3_PA0_MASK 0x00ffff1f + #define SLIM_DCC3_PA0_WIDTH 24 + #define SLIM_DCC3_PA0_RESET 0000000000 +#define SLIM_DCC3_PA1 HW_REGISTER_RW( 0x7e210264 ) + #define SLIM_DCC3_PA1_MASK 0x00ffff3f + #define SLIM_DCC3_PA1_WIDTH 24 + #define SLIM_DCC3_PA1_RESET 0000000000 +#define SLIM_DCC3_CON HW_REGISTER_RW( 0x7e210268 ) + #define SLIM_DCC3_CON_MASK 0xffff0073 + #define SLIM_DCC3_CON_WIDTH 32 + #define SLIM_DCC3_CON_RESET 0000000000 +#define SLIM_DCC3_STAT HW_REGISTER_RW( 0x7e21026c ) + #define SLIM_DCC3_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC3_STAT_WIDTH 32 + #define SLIM_DCC3_STAT_RESET 0000000000 +#define SLIM_DCC4_PA0 HW_REGISTER_RW( 0x7e210280 ) + #define SLIM_DCC4_PA0_MASK 0x00ffff1f + #define SLIM_DCC4_PA0_WIDTH 24 + #define SLIM_DCC4_PA0_RESET 0000000000 +#define SLIM_DCC4_PA1 HW_REGISTER_RW( 0x7e210284 ) + #define SLIM_DCC4_PA1_MASK 0x00ffff3f + #define SLIM_DCC4_PA1_WIDTH 24 + #define SLIM_DCC4_PA1_RESET 0000000000 +#define SLIM_DCC4_CON HW_REGISTER_RW( 0x7e210288 ) + #define SLIM_DCC4_CON_MASK 0xffff0073 + #define SLIM_DCC4_CON_WIDTH 32 + #define SLIM_DCC4_CON_RESET 0000000000 +#define SLIM_DCC4_STAT HW_REGISTER_RW( 0x7e21028c ) + #define SLIM_DCC4_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC4_STAT_WIDTH 32 + #define SLIM_DCC4_STAT_RESET 0000000000 +#define SLIM_DCC5_PA0 HW_REGISTER_RW( 0x7e2102a0 ) + #define SLIM_DCC5_PA0_MASK 0x00ffff1f + #define SLIM_DCC5_PA0_WIDTH 24 + #define SLIM_DCC5_PA0_RESET 0000000000 +#define SLIM_DCC5_PA1 HW_REGISTER_RW( 0x7e2102a4 ) + #define SLIM_DCC5_PA1_MASK 0x00ffff3f + #define SLIM_DCC5_PA1_WIDTH 24 + #define SLIM_DCC5_PA1_RESET 0000000000 +#define SLIM_DCC5_CON HW_REGISTER_RW( 0x7e2102a8 ) + #define SLIM_DCC5_CON_MASK 0xffff0073 + #define SLIM_DCC5_CON_WIDTH 32 + #define SLIM_DCC5_CON_RESET 0000000000 +#define SLIM_DCC5_STAT HW_REGISTER_RW( 0x7e2102ac ) + #define SLIM_DCC5_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC5_STAT_WIDTH 32 + #define SLIM_DCC5_STAT_RESET 0000000000 +#define SLIM_DCC6_PA0 HW_REGISTER_RW( 0x7e2102c0 ) + #define SLIM_DCC6_PA0_MASK 0x00ffff1f + #define SLIM_DCC6_PA0_WIDTH 24 + #define SLIM_DCC6_PA0_RESET 0000000000 +#define SLIM_DCC6_PA1 HW_REGISTER_RW( 0x7e2102c4 ) + #define SLIM_DCC6_PA1_MASK 0x00ffff3f + #define SLIM_DCC6_PA1_WIDTH 24 + #define SLIM_DCC6_PA1_RESET 0000000000 +#define SLIM_DCC6_CON HW_REGISTER_RW( 0x7e2102c8 ) + #define SLIM_DCC6_CON_MASK 0xffff0073 + #define SLIM_DCC6_CON_WIDTH 32 + #define SLIM_DCC6_CON_RESET 0000000000 +#define SLIM_DCC6_STAT HW_REGISTER_RW( 0x7e2102cc ) + #define SLIM_DCC6_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC6_STAT_WIDTH 32 + #define SLIM_DCC6_STAT_RESET 0000000000 +#define SLIM_DCC7_PA0 HW_REGISTER_RW( 0x7e2102e0 ) + #define SLIM_DCC7_PA0_MASK 0x00ffff1f + #define SLIM_DCC7_PA0_WIDTH 24 + #define SLIM_DCC7_PA0_RESET 0000000000 +#define SLIM_DCC7_PA1 HW_REGISTER_RW( 0x7e2102e4 ) + #define SLIM_DCC7_PA1_MASK 0x00ffff3f + #define SLIM_DCC7_PA1_WIDTH 24 + #define SLIM_DCC7_PA1_RESET 0000000000 +#define SLIM_DCC7_CON HW_REGISTER_RW( 0x7e2102e8 ) + #define SLIM_DCC7_CON_MASK 0xffff0073 + #define SLIM_DCC7_CON_WIDTH 32 + #define SLIM_DCC7_CON_RESET 0000000000 +#define SLIM_DCC7_STAT HW_REGISTER_RW( 0x7e2102ec ) + #define SLIM_DCC7_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC7_STAT_WIDTH 32 + #define SLIM_DCC7_STAT_RESET 0000000000 +#define SLIM_DCC8_PA0 HW_REGISTER_RW( 0x7e210300 ) + #define SLIM_DCC8_PA0_MASK 0x00ffff1f + #define SLIM_DCC8_PA0_WIDTH 24 + #define SLIM_DCC8_PA0_RESET 0000000000 +#define SLIM_DCC8_PA1 HW_REGISTER_RW( 0x7e210304 ) + #define SLIM_DCC8_PA1_MASK 0x00ffff3f + #define SLIM_DCC8_PA1_WIDTH 24 + #define SLIM_DCC8_PA1_RESET 0000000000 +#define SLIM_DCC8_CON HW_REGISTER_RW( 0x7e210308 ) + #define SLIM_DCC8_CON_MASK 0xffff0073 + #define SLIM_DCC8_CON_WIDTH 32 + #define SLIM_DCC8_CON_RESET 0000000000 +#define SLIM_DCC8_STAT HW_REGISTER_RW( 0x7e21030c ) + #define SLIM_DCC8_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC8_STAT_WIDTH 32 + #define SLIM_DCC8_STAT_RESET 0000000000 +#define SLIM_DCC9_PA0 HW_REGISTER_RW( 0x7e210320 ) + #define SLIM_DCC9_PA0_MASK 0x00ffff1f + #define SLIM_DCC9_PA0_WIDTH 24 + #define SLIM_DCC9_PA0_RESET 0000000000 +#define SLIM_DCC9_PA1 HW_REGISTER_RW( 0x7e210324 ) + #define SLIM_DCC9_PA1_MASK 0x00ffff3f + #define SLIM_DCC9_PA1_WIDTH 24 + #define SLIM_DCC9_PA1_RESET 0000000000 +#define SLIM_DCC9_CON HW_REGISTER_RW( 0x7e210328 ) + #define SLIM_DCC9_CON_MASK 0xffff0073 + #define SLIM_DCC9_CON_WIDTH 32 + #define SLIM_DCC9_CON_RESET 0000000000 +#define SLIM_DCC9_STAT HW_REGISTER_RW( 0x7e21032c ) + #define SLIM_DCC9_STAT_MASK 0xc0ff00c7 + #define SLIM_DCC9_STAT_WIDTH 32 + #define SLIM_DCC9_STAT_RESET 0000000000 diff --git a/bcm2708_chip/smi.h b/bcm2708_chip/smi.h new file mode 100755 index 0000000..1ef7bf5 --- /dev/null +++ b/bcm2708_chip/smi.h @@ -0,0 +1,650 @@ +// This file was generated by the create_regs script +#define SMI_BASE 0x7e600000 +#define SMI_APB_ID 0x534d4958 +#define SMI_CS HW_REGISTER_RW( 0x7e600000 ) + #define SMI_CS_MASK 0xff00ffff + #define SMI_CS_WIDTH 32 + #define SMI_CS_RXF_BITS 31:31 + #define SMI_CS_RXF_SET 0x80000000 + #define SMI_CS_RXF_CLR 0x7fffffff + #define SMI_CS_RXF_MSB 31 + #define SMI_CS_RXF_LSB 31 + #define SMI_CS_RXF_RESET 0x0 + #define SMI_CS_TXE_BITS 30:30 + #define SMI_CS_TXE_SET 0x40000000 + #define SMI_CS_TXE_CLR 0xbfffffff + #define SMI_CS_TXE_MSB 30 + #define SMI_CS_TXE_LSB 30 + #define SMI_CS_TXE_RESET 0x1 + #define SMI_CS_RXD_BITS 29:29 + #define SMI_CS_RXD_SET 0x20000000 + #define SMI_CS_RXD_CLR 0xdfffffff + #define SMI_CS_RXD_MSB 29 + #define SMI_CS_RXD_LSB 29 + #define SMI_CS_RXD_RESET 0x0 + #define SMI_CS_TXD_BITS 28:28 + #define SMI_CS_TXD_SET 0x10000000 + #define SMI_CS_TXD_CLR 0xefffffff + #define SMI_CS_TXD_MSB 28 + #define SMI_CS_TXD_LSB 28 + #define SMI_CS_TXD_RESET 0x1 + #define SMI_CS_RXR_BITS 27:27 + #define SMI_CS_RXR_SET 0x08000000 + #define SMI_CS_RXR_CLR 0xf7ffffff + #define SMI_CS_RXR_MSB 27 + #define SMI_CS_RXR_LSB 27 + #define SMI_CS_RXR_RESET 0x0 + #define SMI_CS_TXW_BITS 26:26 + #define SMI_CS_TXW_SET 0x04000000 + #define SMI_CS_TXW_CLR 0xfbffffff + #define SMI_CS_TXW_MSB 26 + #define SMI_CS_TXW_LSB 26 + #define SMI_CS_TXW_RESET 0x1 + #define SMI_CS_AFERR_BITS 25:25 + #define SMI_CS_AFERR_SET 0x02000000 + #define SMI_CS_AFERR_CLR 0xfdffffff + #define SMI_CS_AFERR_MSB 25 + #define SMI_CS_AFERR_LSB 25 + #define SMI_CS_AFERR_RESET 0x0 + #define SMI_CS_PRDY_BITS 24:24 + #define SMI_CS_PRDY_SET 0x01000000 + #define SMI_CS_PRDY_CLR 0xfeffffff + #define SMI_CS_PRDY_MSB 24 + #define SMI_CS_PRDY_LSB 24 + #define SMI_CS_PRDY_RESET 0x0 + #define SMI_CS_EDREQ_BITS 15:15 + #define SMI_CS_EDREQ_SET 0x00008000 + #define SMI_CS_EDREQ_CLR 0xffff7fff + #define SMI_CS_EDREQ_MSB 15 + #define SMI_CS_EDREQ_LSB 15 + #define SMI_CS_EDREQ_RESET 0x0 + #define SMI_CS_PXLDAT_BITS 14:14 + #define SMI_CS_PXLDAT_SET 0x00004000 + #define SMI_CS_PXLDAT_CLR 0xffffbfff + #define SMI_CS_PXLDAT_MSB 14 + #define SMI_CS_PXLDAT_LSB 14 + #define SMI_CS_PXLDAT_RESET 0x0 + #define SMI_CS_SETERR_BITS 13:13 + #define SMI_CS_SETERR_SET 0x00002000 + #define SMI_CS_SETERR_CLR 0xffffdfff + #define SMI_CS_SETERR_MSB 13 + #define SMI_CS_SETERR_LSB 13 + #define SMI_CS_SETERR_RESET 0x0 + #define SMI_CS_PVMODE_BITS 12:12 + #define SMI_CS_PVMODE_SET 0x00001000 + #define SMI_CS_PVMODE_CLR 0xffffefff + #define SMI_CS_PVMODE_MSB 12 + #define SMI_CS_PVMODE_LSB 12 + #define SMI_CS_PVMODE_RESET 0x0 + #define SMI_CS_INTR_BITS 11:11 + #define SMI_CS_INTR_SET 0x00000800 + #define SMI_CS_INTR_CLR 0xfffff7ff + #define SMI_CS_INTR_MSB 11 + #define SMI_CS_INTR_LSB 11 + #define SMI_CS_INTR_RESET 0x0 + #define SMI_CS_INTT_BITS 10:10 + #define SMI_CS_INTT_SET 0x00000400 + #define SMI_CS_INTT_CLR 0xfffffbff + #define SMI_CS_INTT_MSB 10 + #define SMI_CS_INTT_LSB 10 + #define SMI_CS_INTT_RESET 0x0 + #define SMI_CS_INTD_BITS 9:9 + #define SMI_CS_INTD_SET 0x00000200 + #define SMI_CS_INTD_CLR 0xfffffdff + #define SMI_CS_INTD_MSB 9 + #define SMI_CS_INTD_LSB 9 + #define SMI_CS_INTD_RESET 0x0 + #define SMI_CS_TEEN_BITS 8:8 + #define SMI_CS_TEEN_SET 0x00000100 + #define SMI_CS_TEEN_CLR 0xfffffeff + #define SMI_CS_TEEN_MSB 8 + #define SMI_CS_TEEN_LSB 8 + #define SMI_CS_TEEN_RESET 0x0 + #define SMI_CS_PAD_BITS 7:6 + #define SMI_CS_PAD_SET 0x000000c0 + #define SMI_CS_PAD_CLR 0xffffff3f + #define SMI_CS_PAD_MSB 7 + #define SMI_CS_PAD_LSB 6 + #define SMI_CS_PAD_RESET 0x0 + #define SMI_CS_WRITE_BITS 5:5 + #define SMI_CS_WRITE_SET 0x00000020 + #define SMI_CS_WRITE_CLR 0xffffffdf + #define SMI_CS_WRITE_MSB 5 + #define SMI_CS_WRITE_LSB 5 + #define SMI_CS_WRITE_RESET 0x0 + #define SMI_CS_CLEAR_BITS 4:4 + #define SMI_CS_CLEAR_SET 0x00000010 + #define SMI_CS_CLEAR_CLR 0xffffffef + #define SMI_CS_CLEAR_MSB 4 + #define SMI_CS_CLEAR_LSB 4 + #define SMI_CS_CLEAR_RESET 0x0 + #define SMI_CS_START_BITS 3:3 + #define SMI_CS_START_SET 0x00000008 + #define SMI_CS_START_CLR 0xfffffff7 + #define SMI_CS_START_MSB 3 + #define SMI_CS_START_LSB 3 + #define SMI_CS_START_RESET 0x0 + #define SMI_CS_ACTIVE_BITS 2:2 + #define SMI_CS_ACTIVE_SET 0x00000004 + #define SMI_CS_ACTIVE_CLR 0xfffffffb + #define SMI_CS_ACTIVE_MSB 2 + #define SMI_CS_ACTIVE_LSB 2 + #define SMI_CS_ACTIVE_RESET 0x0 + #define SMI_CS_DONE_BITS 1:1 + #define SMI_CS_DONE_SET 0x00000002 + #define SMI_CS_DONE_CLR 0xfffffffd + #define SMI_CS_DONE_MSB 1 + #define SMI_CS_DONE_LSB 1 + #define SMI_CS_DONE_RESET 0x0 + #define SMI_CS_ENABLE_BITS 0:0 + #define SMI_CS_ENABLE_SET 0x00000001 + #define SMI_CS_ENABLE_CLR 0xfffffffe + #define SMI_CS_ENABLE_MSB 0 + #define SMI_CS_ENABLE_LSB 0 + #define SMI_CS_ENABLE_RESET 0x0 +#define SMI_L HW_REGISTER_RW( 0x7e600004 ) + #define SMI_L_MASK 0xffffffff + #define SMI_L_WIDTH 32 + #define SMI_L_RESET 0000000000 +#define SMI_A HW_REGISTER_RW( 0x7e600008 ) + #define SMI_A_MASK 0x0000033f + #define SMI_A_WIDTH 10 + #define SMI_A_RESET 0000000000 + #define SMI_A_DEVICE_BITS 9:8 + #define SMI_A_DEVICE_SET 0x00000300 + #define SMI_A_DEVICE_CLR 0xfffffcff + #define SMI_A_DEVICE_MSB 9 + #define SMI_A_DEVICE_LSB 8 + #define SMI_A_ADDR_BITS 5:0 + #define SMI_A_ADDR_SET 0x0000003f + #define SMI_A_ADDR_CLR 0xffffffc0 + #define SMI_A_ADDR_MSB 5 + #define SMI_A_ADDR_LSB 0 +#define SMI_D HW_REGISTER_RW( 0x7e60000c ) + #define SMI_D_MASK 0xffffffff + #define SMI_D_WIDTH 32 + #define SMI_D_RESET 0000000000 +#define SMI_DSR0 HW_REGISTER_RW( 0x7e600010 ) + #define SMI_DSR0_MASK 0xffffffff + #define SMI_DSR0_WIDTH 32 + #define SMI_DSR0_RESET 0x0101000c + #define SMI_DSR0_RWIDTH_BITS 31:30 + #define SMI_DSR0_RWIDTH_SET 0xc0000000 + #define SMI_DSR0_RWIDTH_CLR 0x3fffffff + #define SMI_DSR0_RWIDTH_MSB 31 + #define SMI_DSR0_RWIDTH_LSB 30 + #define SMI_DSR0_RSETUP_BITS 29:24 + #define SMI_DSR0_RSETUP_SET 0x3f000000 + #define SMI_DSR0_RSETUP_CLR 0xc0ffffff + #define SMI_DSR0_RSETUP_MSB 29 + #define SMI_DSR0_RSETUP_LSB 24 + #define SMI_DSR0_MODE68_BITS 23:23 + #define SMI_DSR0_MODE68_SET 0x00800000 + #define SMI_DSR0_MODE68_CLR 0xff7fffff + #define SMI_DSR0_MODE68_MSB 23 + #define SMI_DSR0_MODE68_LSB 23 + #define SMI_DSR0_FSETUP_BITS 22:22 + #define SMI_DSR0_FSETUP_SET 0x00400000 + #define SMI_DSR0_FSETUP_CLR 0xffbfffff + #define SMI_DSR0_FSETUP_MSB 22 + #define SMI_DSR0_FSETUP_LSB 22 + #define SMI_DSR0_RHOLD_BITS 21:16 + #define SMI_DSR0_RHOLD_SET 0x003f0000 + #define SMI_DSR0_RHOLD_CLR 0xffc0ffff + #define SMI_DSR0_RHOLD_MSB 21 + #define SMI_DSR0_RHOLD_LSB 16 + #define SMI_DSR0_RPACEALL_BITS 15:15 + #define SMI_DSR0_RPACEALL_SET 0x00008000 + #define SMI_DSR0_RPACEALL_CLR 0xffff7fff + #define SMI_DSR0_RPACEALL_MSB 15 + #define SMI_DSR0_RPACEALL_LSB 15 + #define SMI_DSR0_RPACE_BITS 14:8 + #define SMI_DSR0_RPACE_SET 0x00007f00 + #define SMI_DSR0_RPACE_CLR 0xffff80ff + #define SMI_DSR0_RPACE_MSB 14 + #define SMI_DSR0_RPACE_LSB 8 + #define SMI_DSR0_RDREQ_BITS 7:7 + #define SMI_DSR0_RDREQ_SET 0x00000080 + #define SMI_DSR0_RDREQ_CLR 0xffffff7f + #define SMI_DSR0_RDREQ_MSB 7 + #define SMI_DSR0_RDREQ_LSB 7 + #define SMI_DSR0_RSTROBE_BITS 6:0 + #define SMI_DSR0_RSTROBE_SET 0x0000007f + #define SMI_DSR0_RSTROBE_CLR 0xffffff80 + #define SMI_DSR0_RSTROBE_MSB 6 + #define SMI_DSR0_RSTROBE_LSB 0 +#define SMI_DSW0 HW_REGISTER_RW( 0x7e600014 ) + #define SMI_DSW0_MASK 0xffffffff + #define SMI_DSW0_WIDTH 32 + #define SMI_DSW0_RESET 0x0101000c + #define SMI_DSW0_WWIDTH_BITS 31:30 + #define SMI_DSW0_WWIDTH_SET 0xc0000000 + #define SMI_DSW0_WWIDTH_CLR 0x3fffffff + #define SMI_DSW0_WWIDTH_MSB 31 + #define SMI_DSW0_WWIDTH_LSB 30 + #define SMI_DSW0_WSETUP_BITS 29:24 + #define SMI_DSW0_WSETUP_SET 0x3f000000 + #define SMI_DSW0_WSETUP_CLR 0xc0ffffff + #define SMI_DSW0_WSETUP_MSB 29 + #define SMI_DSW0_WSETUP_LSB 24 + #define SMI_DSW0_WFORMAT_BITS 23:23 + #define SMI_DSW0_WFORMAT_SET 0x00800000 + #define SMI_DSW0_WFORMAT_CLR 0xff7fffff + #define SMI_DSW0_WFORMAT_MSB 23 + #define SMI_DSW0_WFORMAT_LSB 23 + #define SMI_DSW0_WSWAP_BITS 22:22 + #define SMI_DSW0_WSWAP_SET 0x00400000 + #define SMI_DSW0_WSWAP_CLR 0xffbfffff + #define SMI_DSW0_WSWAP_MSB 22 + #define SMI_DSW0_WSWAP_LSB 22 + #define SMI_DSW0_WHOLD_BITS 21:16 + #define SMI_DSW0_WHOLD_SET 0x003f0000 + #define SMI_DSW0_WHOLD_CLR 0xffc0ffff + #define SMI_DSW0_WHOLD_MSB 21 + #define SMI_DSW0_WHOLD_LSB 16 + #define SMI_DSW0_WPACEALL_BITS 15:15 + #define SMI_DSW0_WPACEALL_SET 0x00008000 + #define SMI_DSW0_WPACEALL_CLR 0xffff7fff + #define SMI_DSW0_WPACEALL_MSB 15 + #define SMI_DSW0_WPACEALL_LSB 15 + #define SMI_DSW0_WPACE_BITS 14:8 + #define SMI_DSW0_WPACE_SET 0x00007f00 + #define SMI_DSW0_WPACE_CLR 0xffff80ff + #define SMI_DSW0_WPACE_MSB 14 + #define SMI_DSW0_WPACE_LSB 8 + #define SMI_DSW0_WDREQ_BITS 7:7 + #define SMI_DSW0_WDREQ_SET 0x00000080 + #define SMI_DSW0_WDREQ_CLR 0xffffff7f + #define SMI_DSW0_WDREQ_MSB 7 + #define SMI_DSW0_WDREQ_LSB 7 + #define SMI_DSW0_WSTROBE_BITS 6:0 + #define SMI_DSW0_WSTROBE_SET 0x0000007f + #define SMI_DSW0_WSTROBE_CLR 0xffffff80 + #define SMI_DSW0_WSTROBE_MSB 6 + #define SMI_DSW0_WSTROBE_LSB 0 +#define SMI_DSR1 HW_REGISTER_RW( 0x7e600018 ) + #define SMI_DSR1_MASK 0xffffffff + #define SMI_DSR1_WIDTH 32 + #define SMI_DSR1_RESET 0x0101000c + #define SMI_DSR1_RWIDTH_BITS 31:30 + #define SMI_DSR1_RWIDTH_SET 0xc0000000 + #define SMI_DSR1_RWIDTH_CLR 0x3fffffff + #define SMI_DSR1_RWIDTH_MSB 31 + #define SMI_DSR1_RWIDTH_LSB 30 + #define SMI_DSR1_RSETUP_BITS 29:24 + #define SMI_DSR1_RSETUP_SET 0x3f000000 + #define SMI_DSR1_RSETUP_CLR 0xc0ffffff + #define SMI_DSR1_RSETUP_MSB 29 + #define SMI_DSR1_RSETUP_LSB 24 + #define SMI_DSR1_MODE68_BITS 23:23 + #define SMI_DSR1_MODE68_SET 0x00800000 + #define SMI_DSR1_MODE68_CLR 0xff7fffff + #define SMI_DSR1_MODE68_MSB 23 + #define SMI_DSR1_MODE68_LSB 23 + #define SMI_DSR1_FSETUP_BITS 22:22 + #define SMI_DSR1_FSETUP_SET 0x00400000 + #define SMI_DSR1_FSETUP_CLR 0xffbfffff + #define SMI_DSR1_FSETUP_MSB 22 + #define SMI_DSR1_FSETUP_LSB 22 + #define SMI_DSR1_RHOLD_BITS 21:16 + #define SMI_DSR1_RHOLD_SET 0x003f0000 + #define SMI_DSR1_RHOLD_CLR 0xffc0ffff + #define SMI_DSR1_RHOLD_MSB 21 + #define SMI_DSR1_RHOLD_LSB 16 + #define SMI_DSR1_RPACEALL_BITS 15:15 + #define SMI_DSR1_RPACEALL_SET 0x00008000 + #define SMI_DSR1_RPACEALL_CLR 0xffff7fff + #define SMI_DSR1_RPACEALL_MSB 15 + #define SMI_DSR1_RPACEALL_LSB 15 + #define SMI_DSR1_RPACE_BITS 14:8 + #define SMI_DSR1_RPACE_SET 0x00007f00 + #define SMI_DSR1_RPACE_CLR 0xffff80ff + #define SMI_DSR1_RPACE_MSB 14 + #define SMI_DSR1_RPACE_LSB 8 + #define SMI_DSR1_RDREQ_BITS 7:7 + #define SMI_DSR1_RDREQ_SET 0x00000080 + #define SMI_DSR1_RDREQ_CLR 0xffffff7f + #define SMI_DSR1_RDREQ_MSB 7 + #define SMI_DSR1_RDREQ_LSB 7 + #define SMI_DSR1_RSTROBE_BITS 6:0 + #define SMI_DSR1_RSTROBE_SET 0x0000007f + #define SMI_DSR1_RSTROBE_CLR 0xffffff80 + #define SMI_DSR1_RSTROBE_MSB 6 + #define SMI_DSR1_RSTROBE_LSB 0 +#define SMI_DSW1 HW_REGISTER_RW( 0x7e60001c ) + #define SMI_DSW1_MASK 0xffffffff + #define SMI_DSW1_WIDTH 32 + #define SMI_DSW1_RESET 0x0101000c + #define SMI_DSW1_WWIDTH_BITS 31:30 + #define SMI_DSW1_WWIDTH_SET 0xc0000000 + #define SMI_DSW1_WWIDTH_CLR 0x3fffffff + #define SMI_DSW1_WWIDTH_MSB 31 + #define SMI_DSW1_WWIDTH_LSB 30 + #define SMI_DSW1_WSETUP_BITS 29:24 + #define SMI_DSW1_WSETUP_SET 0x3f000000 + #define SMI_DSW1_WSETUP_CLR 0xc0ffffff + #define SMI_DSW1_WSETUP_MSB 29 + #define SMI_DSW1_WSETUP_LSB 24 + #define SMI_DSW1_WFORMAT_BITS 23:23 + #define SMI_DSW1_WFORMAT_SET 0x00800000 + #define SMI_DSW1_WFORMAT_CLR 0xff7fffff + #define SMI_DSW1_WFORMAT_MSB 23 + #define SMI_DSW1_WFORMAT_LSB 23 + #define SMI_DSW1_WSWAP_BITS 22:22 + #define SMI_DSW1_WSWAP_SET 0x00400000 + #define SMI_DSW1_WSWAP_CLR 0xffbfffff + #define SMI_DSW1_WSWAP_MSB 22 + #define SMI_DSW1_WSWAP_LSB 22 + #define SMI_DSW1_WHOLD_BITS 21:16 + #define SMI_DSW1_WHOLD_SET 0x003f0000 + #define SMI_DSW1_WHOLD_CLR 0xffc0ffff + #define SMI_DSW1_WHOLD_MSB 21 + #define SMI_DSW1_WHOLD_LSB 16 + #define SMI_DSW1_WPACEALL_BITS 15:15 + #define SMI_DSW1_WPACEALL_SET 0x00008000 + #define SMI_DSW1_WPACEALL_CLR 0xffff7fff + #define SMI_DSW1_WPACEALL_MSB 15 + #define SMI_DSW1_WPACEALL_LSB 15 + #define SMI_DSW1_WPACE_BITS 14:8 + #define SMI_DSW1_WPACE_SET 0x00007f00 + #define SMI_DSW1_WPACE_CLR 0xffff80ff + #define SMI_DSW1_WPACE_MSB 14 + #define SMI_DSW1_WPACE_LSB 8 + #define SMI_DSW1_WDREQ_BITS 7:7 + #define SMI_DSW1_WDREQ_SET 0x00000080 + #define SMI_DSW1_WDREQ_CLR 0xffffff7f + #define SMI_DSW1_WDREQ_MSB 7 + #define SMI_DSW1_WDREQ_LSB 7 + #define SMI_DSW1_WSTROBE_BITS 6:0 + #define SMI_DSW1_WSTROBE_SET 0x0000007f + #define SMI_DSW1_WSTROBE_CLR 0xffffff80 + #define SMI_DSW1_WSTROBE_MSB 6 + #define SMI_DSW1_WSTROBE_LSB 0 +#define SMI_DSR2 HW_REGISTER_RW( 0x7e600020 ) + #define SMI_DSR2_MASK 0xffffffff + #define SMI_DSR2_WIDTH 32 + #define SMI_DSR2_RESET 0x0101000c + #define SMI_DSR2_RWIDTH_BITS 31:30 + #define SMI_DSR2_RWIDTH_SET 0xc0000000 + #define SMI_DSR2_RWIDTH_CLR 0x3fffffff + #define SMI_DSR2_RWIDTH_MSB 31 + #define SMI_DSR2_RWIDTH_LSB 30 + #define SMI_DSR2_RSETUP_BITS 29:24 + #define SMI_DSR2_RSETUP_SET 0x3f000000 + #define SMI_DSR2_RSETUP_CLR 0xc0ffffff + #define SMI_DSR2_RSETUP_MSB 29 + #define SMI_DSR2_RSETUP_LSB 24 + #define SMI_DSR2_MODE68_BITS 23:23 + #define SMI_DSR2_MODE68_SET 0x00800000 + #define SMI_DSR2_MODE68_CLR 0xff7fffff + #define SMI_DSR2_MODE68_MSB 23 + #define SMI_DSR2_MODE68_LSB 23 + #define SMI_DSR2_FSETUP_BITS 22:22 + #define SMI_DSR2_FSETUP_SET 0x00400000 + #define SMI_DSR2_FSETUP_CLR 0xffbfffff + #define SMI_DSR2_FSETUP_MSB 22 + #define SMI_DSR2_FSETUP_LSB 22 + #define SMI_DSR2_RHOLD_BITS 21:16 + #define SMI_DSR2_RHOLD_SET 0x003f0000 + #define SMI_DSR2_RHOLD_CLR 0xffc0ffff + #define SMI_DSR2_RHOLD_MSB 21 + #define SMI_DSR2_RHOLD_LSB 16 + #define SMI_DSR2_RPACEALL_BITS 15:15 + #define SMI_DSR2_RPACEALL_SET 0x00008000 + #define SMI_DSR2_RPACEALL_CLR 0xffff7fff + #define SMI_DSR2_RPACEALL_MSB 15 + #define SMI_DSR2_RPACEALL_LSB 15 + #define SMI_DSR2_RPACE_BITS 14:8 + #define SMI_DSR2_RPACE_SET 0x00007f00 + #define SMI_DSR2_RPACE_CLR 0xffff80ff + #define SMI_DSR2_RPACE_MSB 14 + #define SMI_DSR2_RPACE_LSB 8 + #define SMI_DSR2_RDREQ_BITS 7:7 + #define SMI_DSR2_RDREQ_SET 0x00000080 + #define SMI_DSR2_RDREQ_CLR 0xffffff7f + #define SMI_DSR2_RDREQ_MSB 7 + #define SMI_DSR2_RDREQ_LSB 7 + #define SMI_DSR2_RSTROBE_BITS 6:0 + #define SMI_DSR2_RSTROBE_SET 0x0000007f + #define SMI_DSR2_RSTROBE_CLR 0xffffff80 + #define SMI_DSR2_RSTROBE_MSB 6 + #define SMI_DSR2_RSTROBE_LSB 0 +#define SMI_DSW2 HW_REGISTER_RW( 0x7e600024 ) + #define SMI_DSW2_MASK 0xffffffff + #define SMI_DSW2_WIDTH 32 + #define SMI_DSW2_RESET 0x0101000c + #define SMI_DSW2_WWIDTH_BITS 31:30 + #define SMI_DSW2_WWIDTH_SET 0xc0000000 + #define SMI_DSW2_WWIDTH_CLR 0x3fffffff + #define SMI_DSW2_WWIDTH_MSB 31 + #define SMI_DSW2_WWIDTH_LSB 30 + #define SMI_DSW2_WSETUP_BITS 29:24 + #define SMI_DSW2_WSETUP_SET 0x3f000000 + #define SMI_DSW2_WSETUP_CLR 0xc0ffffff + #define SMI_DSW2_WSETUP_MSB 29 + #define SMI_DSW2_WSETUP_LSB 24 + #define SMI_DSW2_WFORMAT_BITS 23:23 + #define SMI_DSW2_WFORMAT_SET 0x00800000 + #define SMI_DSW2_WFORMAT_CLR 0xff7fffff + #define SMI_DSW2_WFORMAT_MSB 23 + #define SMI_DSW2_WFORMAT_LSB 23 + #define SMI_DSW2_WSWAP_BITS 22:22 + #define SMI_DSW2_WSWAP_SET 0x00400000 + #define SMI_DSW2_WSWAP_CLR 0xffbfffff + #define SMI_DSW2_WSWAP_MSB 22 + #define SMI_DSW2_WSWAP_LSB 22 + #define SMI_DSW2_WHOLD_BITS 21:16 + #define SMI_DSW2_WHOLD_SET 0x003f0000 + #define SMI_DSW2_WHOLD_CLR 0xffc0ffff + #define SMI_DSW2_WHOLD_MSB 21 + #define SMI_DSW2_WHOLD_LSB 16 + #define SMI_DSW2_WPACEALL_BITS 15:15 + #define SMI_DSW2_WPACEALL_SET 0x00008000 + #define SMI_DSW2_WPACEALL_CLR 0xffff7fff + #define SMI_DSW2_WPACEALL_MSB 15 + #define SMI_DSW2_WPACEALL_LSB 15 + #define SMI_DSW2_WPACE_BITS 14:8 + #define SMI_DSW2_WPACE_SET 0x00007f00 + #define SMI_DSW2_WPACE_CLR 0xffff80ff + #define SMI_DSW2_WPACE_MSB 14 + #define SMI_DSW2_WPACE_LSB 8 + #define SMI_DSW2_WDREQ_BITS 7:7 + #define SMI_DSW2_WDREQ_SET 0x00000080 + #define SMI_DSW2_WDREQ_CLR 0xffffff7f + #define SMI_DSW2_WDREQ_MSB 7 + #define SMI_DSW2_WDREQ_LSB 7 + #define SMI_DSW2_WSTROBE_BITS 6:0 + #define SMI_DSW2_WSTROBE_SET 0x0000007f + #define SMI_DSW2_WSTROBE_CLR 0xffffff80 + #define SMI_DSW2_WSTROBE_MSB 6 + #define SMI_DSW2_WSTROBE_LSB 0 +#define SMI_DSR3 HW_REGISTER_RW( 0x7e600028 ) + #define SMI_DSR3_MASK 0xffffffff + #define SMI_DSR3_WIDTH 32 + #define SMI_DSR3_RESET 0x0101000c + #define SMI_DSR3_RWIDTH_BITS 31:30 + #define SMI_DSR3_RWIDTH_SET 0xc0000000 + #define SMI_DSR3_RWIDTH_CLR 0x3fffffff + #define SMI_DSR3_RWIDTH_MSB 31 + #define SMI_DSR3_RWIDTH_LSB 30 + #define SMI_DSR3_RSETUP_BITS 29:24 + #define SMI_DSR3_RSETUP_SET 0x3f000000 + #define SMI_DSR3_RSETUP_CLR 0xc0ffffff + #define SMI_DSR3_RSETUP_MSB 29 + #define SMI_DSR3_RSETUP_LSB 24 + #define SMI_DSR3_MODE68_BITS 23:23 + #define SMI_DSR3_MODE68_SET 0x00800000 + #define SMI_DSR3_MODE68_CLR 0xff7fffff + #define SMI_DSR3_MODE68_MSB 23 + #define SMI_DSR3_MODE68_LSB 23 + #define SMI_DSR3_FSETUP_BITS 22:22 + #define SMI_DSR3_FSETUP_SET 0x00400000 + #define SMI_DSR3_FSETUP_CLR 0xffbfffff + #define SMI_DSR3_FSETUP_MSB 22 + #define SMI_DSR3_FSETUP_LSB 22 + #define SMI_DSR3_RHOLD_BITS 21:16 + #define SMI_DSR3_RHOLD_SET 0x003f0000 + #define SMI_DSR3_RHOLD_CLR 0xffc0ffff + #define SMI_DSR3_RHOLD_MSB 21 + #define SMI_DSR3_RHOLD_LSB 16 + #define SMI_DSR3_RPACEALL_BITS 15:15 + #define SMI_DSR3_RPACEALL_SET 0x00008000 + #define SMI_DSR3_RPACEALL_CLR 0xffff7fff + #define SMI_DSR3_RPACEALL_MSB 15 + #define SMI_DSR3_RPACEALL_LSB 15 + #define SMI_DSR3_RPACE_BITS 14:8 + #define SMI_DSR3_RPACE_SET 0x00007f00 + #define SMI_DSR3_RPACE_CLR 0xffff80ff + #define SMI_DSR3_RPACE_MSB 14 + #define SMI_DSR3_RPACE_LSB 8 + #define SMI_DSR3_RDREQ_BITS 7:7 + #define SMI_DSR3_RDREQ_SET 0x00000080 + #define SMI_DSR3_RDREQ_CLR 0xffffff7f + #define SMI_DSR3_RDREQ_MSB 7 + #define SMI_DSR3_RDREQ_LSB 7 + #define SMI_DSR3_RSTROBE_BITS 6:0 + #define SMI_DSR3_RSTROBE_SET 0x0000007f + #define SMI_DSR3_RSTROBE_CLR 0xffffff80 + #define SMI_DSR3_RSTROBE_MSB 6 + #define SMI_DSR3_RSTROBE_LSB 0 +#define SMI_DSW3 HW_REGISTER_RW( 0x7e60002c ) + #define SMI_DSW3_MASK 0xffffffff + #define SMI_DSW3_WIDTH 32 + #define SMI_DSW3_RESET 0x0101000c + #define SMI_DSW3_WWIDTH_BITS 31:30 + #define SMI_DSW3_WWIDTH_SET 0xc0000000 + #define SMI_DSW3_WWIDTH_CLR 0x3fffffff + #define SMI_DSW3_WWIDTH_MSB 31 + #define SMI_DSW3_WWIDTH_LSB 30 + #define SMI_DSW3_WSETUP_BITS 29:24 + #define SMI_DSW3_WSETUP_SET 0x3f000000 + #define SMI_DSW3_WSETUP_CLR 0xc0ffffff + #define SMI_DSW3_WSETUP_MSB 29 + #define SMI_DSW3_WSETUP_LSB 24 + #define SMI_DSW3_WFORMAT_BITS 23:23 + #define SMI_DSW3_WFORMAT_SET 0x00800000 + #define SMI_DSW3_WFORMAT_CLR 0xff7fffff + #define SMI_DSW3_WFORMAT_MSB 23 + #define SMI_DSW3_WFORMAT_LSB 23 + #define SMI_DSW3_WSWAP_BITS 22:22 + #define SMI_DSW3_WSWAP_SET 0x00400000 + #define SMI_DSW3_WSWAP_CLR 0xffbfffff + #define SMI_DSW3_WSWAP_MSB 22 + #define SMI_DSW3_WSWAP_LSB 22 + #define SMI_DSW3_WHOLD_BITS 21:16 + #define SMI_DSW3_WHOLD_SET 0x003f0000 + #define SMI_DSW3_WHOLD_CLR 0xffc0ffff + #define SMI_DSW3_WHOLD_MSB 21 + #define SMI_DSW3_WHOLD_LSB 16 + #define SMI_DSW3_WPACEALL_BITS 15:15 + #define SMI_DSW3_WPACEALL_SET 0x00008000 + #define SMI_DSW3_WPACEALL_CLR 0xffff7fff + #define SMI_DSW3_WPACEALL_MSB 15 + #define SMI_DSW3_WPACEALL_LSB 15 + #define SMI_DSW3_WPACE_BITS 14:8 + #define SMI_DSW3_WPACE_SET 0x00007f00 + #define SMI_DSW3_WPACE_CLR 0xffff80ff + #define SMI_DSW3_WPACE_MSB 14 + #define SMI_DSW3_WPACE_LSB 8 + #define SMI_DSW3_WDREQ_BITS 7:7 + #define SMI_DSW3_WDREQ_SET 0x00000080 + #define SMI_DSW3_WDREQ_CLR 0xffffff7f + #define SMI_DSW3_WDREQ_MSB 7 + #define SMI_DSW3_WDREQ_LSB 7 + #define SMI_DSW3_WSTROBE_BITS 6:0 + #define SMI_DSW3_WSTROBE_SET 0x0000007f + #define SMI_DSW3_WSTROBE_CLR 0xffffff80 + #define SMI_DSW3_WSTROBE_MSB 6 + #define SMI_DSW3_WSTROBE_LSB 0 +#define SMI_DC HW_REGISTER_RW( 0x7e600030 ) + #define SMI_DC_MASK 0x11ffffff + #define SMI_DC_WIDTH 29 + #define SMI_DC_RESET 0x00c10820 + #define SMI_DC_DMAEN_BITS 28:28 + #define SMI_DC_DMAEN_SET 0x10000000 + #define SMI_DC_DMAEN_CLR 0xefffffff + #define SMI_DC_DMAEN_MSB 28 + #define SMI_DC_DMAEN_LSB 28 + #define SMI_DC_DMAP_BITS 24:24 + #define SMI_DC_DMAP_SET 0x01000000 + #define SMI_DC_DMAP_CLR 0xfeffffff + #define SMI_DC_DMAP_MSB 24 + #define SMI_DC_DMAP_LSB 24 + #define SMI_DC_PANICR_BITS 23:18 + #define SMI_DC_PANICR_SET 0x00fc0000 + #define SMI_DC_PANICR_CLR 0xff03ffff + #define SMI_DC_PANICR_MSB 23 + #define SMI_DC_PANICR_LSB 18 + #define SMI_DC_PANICW_BITS 17:12 + #define SMI_DC_PANICW_SET 0x0003f000 + #define SMI_DC_PANICW_CLR 0xfffc0fff + #define SMI_DC_PANICW_MSB 17 + #define SMI_DC_PANICW_LSB 12 + #define SMI_DC_REQR_BITS 11:6 + #define SMI_DC_REQR_SET 0x00000fc0 + #define SMI_DC_REQR_CLR 0xfffff03f + #define SMI_DC_REQR_MSB 11 + #define SMI_DC_REQR_LSB 6 + #define SMI_DC_REQW_BITS 5:0 + #define SMI_DC_REQW_SET 0x0000003f + #define SMI_DC_REQW_CLR 0xffffffc0 + #define SMI_DC_REQW_MSB 5 + #define SMI_DC_REQW_LSB 0 +#define SMI_DCS HW_REGISTER_RW( 0x7e600034 ) + #define SMI_DCS_MASK 0x0000000f + #define SMI_DCS_WIDTH 4 + #define SMI_DCS_RESET 0000000000 + #define SMI_DCS_WRITE_BITS 3:3 + #define SMI_DCS_WRITE_SET 0x00000008 + #define SMI_DCS_WRITE_CLR 0xfffffff7 + #define SMI_DCS_WRITE_MSB 3 + #define SMI_DCS_WRITE_LSB 3 + #define SMI_DCS_DONE_BITS 2:2 + #define SMI_DCS_DONE_SET 0x00000004 + #define SMI_DCS_DONE_CLR 0xfffffffb + #define SMI_DCS_DONE_MSB 2 + #define SMI_DCS_DONE_LSB 2 + #define SMI_DCS_START_BITS 1:1 + #define SMI_DCS_START_SET 0x00000002 + #define SMI_DCS_START_CLR 0xfffffffd + #define SMI_DCS_START_MSB 1 + #define SMI_DCS_START_LSB 1 + #define SMI_DCS_EANBLE_BITS 0:0 + #define SMI_DCS_EANBLE_SET 0x00000001 + #define SMI_DCS_EANBLE_CLR 0xfffffffe + #define SMI_DCS_EANBLE_MSB 0 + #define SMI_DCS_EANBLE_LSB 0 +#define SMI_DA HW_REGISTER_RW( 0x7e600038 ) + #define SMI_DA_MASK 0x0000033f + #define SMI_DA_WIDTH 10 + #define SMI_DA_RESET 0000000000 + #define SMI_DA_WRITE_BITS 9:8 + #define SMI_DA_WRITE_SET 0x00000300 + #define SMI_DA_WRITE_CLR 0xfffffcff + #define SMI_DA_WRITE_MSB 9 + #define SMI_DA_WRITE_LSB 8 + #define SMI_DA_ADDR_BITS 5:0 + #define SMI_DA_ADDR_SET 0x0000003f + #define SMI_DA_ADDR_CLR 0xffffffc0 + #define SMI_DA_ADDR_MSB 5 + #define SMI_DA_ADDR_LSB 0 +#define SMI_DD HW_REGISTER_RW( 0x7e60003c ) + #define SMI_DD_MASK 0x0003ffff + #define SMI_DD_WIDTH 18 + #define SMI_DD_RESET 0000000000 +#define SMI_FD HW_REGISTER_RW( 0x7e600040 ) + #define SMI_FD_MASK 0x00003f3f + #define SMI_FD_WIDTH 14 + #define SMI_FD_RESET 0000000000 + #define SMI_FD_FLVL_BITS 13:8 + #define SMI_FD_FLVL_SET 0x00003f00 + #define SMI_FD_FLVL_CLR 0xffffc0ff + #define SMI_FD_FLVL_MSB 13 + #define SMI_FD_FLVL_LSB 8 + #define SMI_FD_FLVL_RESET 0x0 + #define SMI_FD_FCNT_BITS 5:0 + #define SMI_FD_FCNT_SET 0x0000003f + #define SMI_FD_FCNT_CLR 0xffffffc0 + #define SMI_FD_FCNT_MSB 5 + #define SMI_FD_FCNT_LSB 0 + #define SMI_FD_FCNT_RESET 0x0 diff --git a/bcm2708_chip/spi_master.h b/bcm2708_chip/spi_master.h new file mode 100755 index 0000000..15842ca --- /dev/null +++ b/bcm2708_chip/spi_master.h @@ -0,0 +1,107 @@ +// This file was generated by the create_regs script +#define SPI_BASE 0x7e204000 +#define SPI_CS HW_REGISTER_RW( 0x7e204000 ) + #define SPI_CS_MASK 0x001f07ff + #define SPI_CS_WIDTH 21 + #define SPI_CS_RESET 0000000000 + #define SPI_CS_RXF_BITS 20:20 + #define SPI_CS_RXF_SET 0x00100000 + #define SPI_CS_RXF_CLR 0xffefffff + #define SPI_CS_RXF_MSB 20 + #define SPI_CS_RXF_LSB 20 + #define SPI_CS_RXR_BITS 19:19 + #define SPI_CS_RXR_SET 0x00080000 + #define SPI_CS_RXR_CLR 0xfff7ffff + #define SPI_CS_RXR_MSB 19 + #define SPI_CS_RXR_LSB 19 + #define SPI_CS_TXD_BITS 18:18 + #define SPI_CS_TXD_SET 0x00040000 + #define SPI_CS_TXD_CLR 0xfffbffff + #define SPI_CS_TXD_MSB 18 + #define SPI_CS_TXD_LSB 18 + #define SPI_CS_RXD_BITS 17:17 + #define SPI_CS_RXD_SET 0x00020000 + #define SPI_CS_RXD_CLR 0xfffdffff + #define SPI_CS_RXD_MSB 17 + #define SPI_CS_RXD_LSB 17 + #define SPI_CS_DONE_BITS 16:16 + #define SPI_CS_DONE_SET 0x00010000 + #define SPI_CS_DONE_CLR 0xfffeffff + #define SPI_CS_DONE_MSB 16 + #define SPI_CS_DONE_LSB 16 + #define SPI_CS_INTR_BITS 10:10 + #define SPI_CS_INTR_SET 0x00000400 + #define SPI_CS_INTR_CLR 0xfffffbff + #define SPI_CS_INTR_MSB 10 + #define SPI_CS_INTR_LSB 10 + #define SPI_CS_INTD_BITS 9:9 + #define SPI_CS_INTD_SET 0x00000200 + #define SPI_CS_INTD_CLR 0xfffffdff + #define SPI_CS_INTD_MSB 9 + #define SPI_CS_INTD_LSB 9 + #define SPI_CS_DMAEN_BITS 8:8 + #define SPI_CS_DMAEN_SET 0x00000100 + #define SPI_CS_DMAEN_CLR 0xfffffeff + #define SPI_CS_DMAEN_MSB 8 + #define SPI_CS_DMAEN_LSB 8 + #define SPI_CS_TA_BITS 7:7 + #define SPI_CS_TA_SET 0x00000080 + #define SPI_CS_TA_CLR 0xffffff7f + #define SPI_CS_TA_MSB 7 + #define SPI_CS_TA_LSB 7 + #define SPI_CS_CSPOL_BITS 6:6 + #define SPI_CS_CSPOL_SET 0x00000040 + #define SPI_CS_CSPOL_CLR 0xffffffbf + #define SPI_CS_CSPOL_MSB 6 + #define SPI_CS_CSPOL_LSB 6 + #define SPI_CS_CLEAR_BITS 5:4 + #define SPI_CS_CLEAR_SET 0x00000030 + #define SPI_CS_CLEAR_CLR 0xffffffcf + #define SPI_CS_CLEAR_MSB 5 + #define SPI_CS_CLEAR_LSB 4 + #define SPI_CS_CPOL_BITS 3:3 + #define SPI_CS_CPOL_SET 0x00000008 + #define SPI_CS_CPOL_CLR 0xfffffff7 + #define SPI_CS_CPOL_MSB 3 + #define SPI_CS_CPOL_LSB 3 + #define SPI_CS_CPHA_BITS 2:2 + #define SPI_CS_CPHA_SET 0x00000004 + #define SPI_CS_CPHA_CLR 0xfffffffb + #define SPI_CS_CPHA_MSB 2 + #define SPI_CS_CPHA_LSB 2 +#define SPI_FIFO HW_REGISTER_RW( 0x7e204004 ) + #define SPI_FIFO_MASK 0x000000ff + #define SPI_FIFO_WIDTH 8 + #define SPI_FIFO_RESET 0000000000 + #define SPI_FIFO_DATA_BITS 7:0 + #define SPI_FIFO_DATA_SET 0x000000ff + #define SPI_FIFO_DATA_CLR 0xffffff00 + #define SPI_FIFO_DATA_MSB 7 + #define SPI_FIFO_DATA_LSB 0 +#define SPI_CLK HW_REGISTER_RW( 0x7e204008 ) + #define SPI_CLK_MASK 0x0000ffff + #define SPI_CLK_WIDTH 16 + #define SPI_CLK_RESET 0000000000 + #define SPI_CLK_CDIV_BITS 15:0 + #define SPI_CLK_CDIV_SET 0x0000ffff + #define SPI_CLK_CDIV_CLR 0xffff0000 + #define SPI_CLK_CDIV_MSB 15 + #define SPI_CLK_CDIV_LSB 0 +#define SPI_DLEN HW_REGISTER_RW( 0x7e20400c ) + #define SPI_DLEN_MASK 0x0000ffff + #define SPI_DLEN_WIDTH 16 + #define SPI_DLEN_RESET 0000000000 + #define SPI_DLEN_LEN_BITS 15:0 + #define SPI_DLEN_LEN_SET 0x0000ffff + #define SPI_DLEN_LEN_CLR 0xffff0000 + #define SPI_DLEN_LEN_MSB 15 + #define SPI_DLEN_LEN_LSB 0 +#define SPI_LTOH HW_REGISTER_RW( 0x7e204010 ) + #define SPI_LTOH_MASK 0x0000000f + #define SPI_LTOH_WIDTH 4 + #define SPI_LTOH_RESET 0x00000001 + #define SPI_LTOH_TOH_BITS 3:0 + #define SPI_LTOH_TOH_SET 0x0000000f + #define SPI_LTOH_TOH_CLR 0xfffffff0 + #define SPI_LTOH_TOH_MSB 3 + #define SPI_LTOH_TOH_LSB 0 diff --git a/bcm2708_chip/sv_chip_regmap.h b/bcm2708_chip/sv_chip_regmap.h new file mode 100755 index 0000000..5bc34ee --- /dev/null +++ b/bcm2708_chip/sv_chip_regmap.h @@ -0,0 +1,11455 @@ +/***************************************************************************** +* * +* Copyright (c) 2003, 2004, 2005 Broadcom * +* All Rights Reserved * +* * +* Confidential and Proprietary. * +* The copyright notice above does not evidence any actual or intended * +* publication. Possession, use, or copying is authorized only pursuant to a * +* valid written license from Sand Video. * +* * +* * +******************************************************************************/ + +/* DO NOT ADD INCLUDE GUARDS TO THIS FILE. IT IS INTENTIONALLY INCLUDED */ +/* MULTIPLE TIMES */ + +#define VCMODS_REGMAP + +/* */ +/* THIS IS A DERIVED FILE!!! DO NOT EDIT THIS FILE!! */ +/* */ +/* THIS FILE IS DERIVED FROM .../hw/doc/Register map.xls */ +/* */ + +// Function formats: +// RegFunc(, , , , +// , ) +// FdFunc(, , , ) + + +#ifndef RegAreaFunc +#define RegAreaFunc(a,b,c) +#endif +#ifndef RegFunc +#define RegFunc(mod, modbase, regname, offset, name, addr) +#endif +#ifndef FldFunc +#define FldFunc(a,b,c,d) +#endif + + +//****************************************************************************** +// +// Decoder Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_DECODER + +RegAreaFunc(DecodeRbnodeRegsBase, 0x0, 0x7F) +RegFunc(DecodeRbnodeRegs, 0x0, RbConfig , 0x0, DecRRs_RbConfig , 0x0) + FldFunc(DecRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(DecRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(DecodeRbnodeRegs, 0x0, RbStickyError, 0x4, DecRRs_RbStickyError, 0x4) + FldFunc(DecRRs_RbStickyError, Node, 1, 1) + FldFunc(DecRRs_RbStickyError, Tgt, 0, 1) +RegFunc(DecodeRbnodeRegs, 0x0, RbCurrentError, 0x8, DecRRs_RbCurrentError, 0x8) + FldFunc(DecRRs_RbCurrentError, Node, 1, 1) + FldFunc(DecRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(DecodeRbnodeRegs, 0x0, RbReadData, 0xC, DecRRs_RbReadData, 0xc) + FldFunc(DecRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(DecodeRingbusDebugRegsBase, 0x80, 0xFF) +RegFunc(DecodeRingbusDebugRegs, 0x80, RbDebugConfig, 0x0, DecRDRs_RbDebugConfig, 0x80) + FldFunc(DecRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(DecRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(DecodeRingbusDebugRegs, 0x80, RbDebugReg0Addr, 0x4, DecRDRs_RbDebugReg0Addr, 0x84) + FldFunc(DecRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(DecodeRingbusDebugRegs, 0x80, RbDebugReg1Addr, 0x8, DecRDRs_RbDebugReg1Addr, 0x88) + FldFunc(DecRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(DecodeRingbusDebugRegs, 0x80, RbDebugReg2Addr, 0xC, DecRDRs_RbDebugReg2Addr, 0x8c) + FldFunc(DecRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(DecodeRingbusDebugRegs, 0x80, RbDebugReg3Addr, 0x10, DecRDRs_RbDebugReg3Addr, 0x90) + FldFunc(DecRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(DecodeRingbusDebugRegs, 0x80, RbDebugOutputReg, 0x14, DecRDRs_RbDebugOutputReg, 0x94) + FldFunc(DecRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(DecRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(DecodeMainBase, 0x100, 0x1FF) +RegFunc(DecodeMain, 0x100, RegMainctl, 0x0, DecMn_RegMainctl, 0x100) + FldFunc(DecMn_RegMainctl, Use2Off, 31, 1) + FldFunc(DecMn_RegMainctl, QpcOffset2, 24, 5) + FldFunc(DecMn_RegMainctl, QpcOffset, 16, 5) + FldFunc(DecMn_RegMainctl, Fls, 15, 1) + FldFunc(DecMn_RegMainctl, Standard, 7, 3) + FldFunc(DecMn_RegMainctl, Profile, 4, 3) + FldFunc(DecMn_RegMainctl, Rst, 0, 1) +RegFunc(DecodeMain, 0x100, RegFramesize, 0x4, DecMn_RegFramesize, 0x104) + FldFunc(DecMn_RegFramesize, Lines, 16, 12) + FldFunc(DecMn_RegFramesize, Pixels, 0, 12) +RegFunc(DecodeMain, 0x100, RegDecVersion, 0x8, DecMn_RegDecVersion, 0x108) + FldFunc(DecMn_RegDecVersion, Major, 16, 16) + FldFunc(DecMn_RegDecVersion, Minor, 8, 8) + FldFunc(DecMn_RegDecVersion, Fixid, 0, 8) +RegFunc(DecodeMain, 0x100, RegStatus, 0x10, DecMn_RegStatus, 0x110) + FldFunc(DecMn_RegStatus, Ixfm, 30, 2) + FldFunc(DecMn_RegStatus, Spre, 28, 2) + FldFunc(DecMn_RegStatus, Mcom, 26, 2) + FldFunc(DecMn_RegStatus, InpbufOverflow, 16, 6) + FldFunc(DecMn_RegStatus, Output, 12, 2) + FldFunc(DecMn_RegStatus, Dblk, 10, 2) + FldFunc(DecMn_RegStatus, Recon, 8, 2) +RegFunc(DecodeMain, 0x100, RegPmonctl, 0x20, DecMn_RegPmonctl, 0x120) + FldFunc(DecMn_RegPmonctl, Cnt1Sel, 8, 4) + FldFunc(DecMn_RegPmonctl, Cnt0Sel, 0, 4) +RegFunc(DecodeMain, 0x100, RegPmoncnt0, 0x24, DecMn_RegPmoncnt0, 0x124) + FldFunc(DecMn_RegPmoncnt0, Data, 16, 16) + FldFunc(DecMn_RegPmoncnt0, Count, 0, 12) +RegFunc(DecodeMain, 0x100, RegPmoncnt1, 0x28, DecMn_RegPmoncnt1, 0x128) + FldFunc(DecMn_RegPmoncnt1, Data, 16, 16) + FldFunc(DecMn_RegPmoncnt1, Count, 0, 12) +RegFunc(DecodeMain, 0x100, RegPmonMbctl, 0x2C, DecMn_RegPmonMbctl, 0x12c) + FldFunc(DecMn_RegPmonMbctl, SwPmon, 1, 1) + FldFunc(DecMn_RegPmonMbctl, Mbctlena, 0, 1) + +RegAreaFunc(SdramDebugBase, 0x200, 0x27F) +RegFunc(SdramDebug, 0x200, SdDebugConfig , 0x0, SdrDg_SdDebugConfig , 0x200) + FldFunc(SdrDg_SdDebugConfig , Inv, 0, 1) +RegFunc(SdramDebug, 0x200, SdDebugStart, 0x4, SdrDg_SdDebugStart, 0x204) + FldFunc(SdrDg_SdDebugStart, DramAddress, 0, 28) +RegFunc(SdramDebug, 0x200, SdDebugEnd, 0x8, SdrDg_SdDebugEnd, 0x208) + FldFunc(SdrDg_SdDebugEnd, DramAddress, 0, 28) +RegFunc(SdramDebug, 0x200, SdDebugRmask , 0xC, SdrDg_SdDebugRmask , 0x20c) + FldFunc(SdrDg_SdDebugRmask , Deblock, 11, 1) + FldFunc(SdrDg_SdDebugRmask , Cabac, 10, 1) + FldFunc(SdrDg_SdDebugRmask , Iloop, 9, 1) + FldFunc(SdrDg_SdDebugRmask , Oloop, 8, 1) + FldFunc(SdrDg_SdDebugRmask , Codein, 7, 1) + FldFunc(SdrDg_SdDebugRmask , Host, 6, 1) + FldFunc(SdrDg_SdDebugRmask , Stream, 5, 1) + FldFunc(SdrDg_SdDebugRmask , Audio, 4, 1) + FldFunc(SdrDg_SdDebugRmask , VppOutput, 3, 1) + FldFunc(SdrDg_SdDebugRmask , Mocomp, 2, 1) + FldFunc(SdrDg_SdDebugRmask , VppFetch, 1, 1) +RegFunc(SdramDebug, 0x200, SdDebugWmask , 0x10, SdrDg_SdDebugWmask , 0x210) + FldFunc(SdrDg_SdDebugWmask , Deblock, 11, 1) + FldFunc(SdrDg_SdDebugWmask , Cabac, 10, 1) + FldFunc(SdrDg_SdDebugWmask , Iloop, 9, 1) + FldFunc(SdrDg_SdDebugWmask , Oloop, 8, 1) + FldFunc(SdrDg_SdDebugWmask , Codein, 7, 1) + FldFunc(SdrDg_SdDebugWmask , Host, 6, 1) + FldFunc(SdrDg_SdDebugWmask , Stream, 5, 1) + FldFunc(SdrDg_SdDebugWmask , Audio, 4, 1) + FldFunc(SdrDg_SdDebugWmask , VppOutput, 3, 1) + FldFunc(SdrDg_SdDebugWmask , Mocomp, 2, 1) + FldFunc(SdrDg_SdDebugWmask , VppFetch, 1, 1) +RegFunc(SdramDebug, 0x200, SdDebugRstatus , 0x14, SdrDg_SdDebugRstatus , 0x214) + FldFunc(SdrDg_SdDebugRstatus , Deblock, 11, 1) + FldFunc(SdrDg_SdDebugRstatus , Cabac, 10, 1) + FldFunc(SdrDg_SdDebugRstatus , Iloop, 9, 1) + FldFunc(SdrDg_SdDebugRstatus , Oloop, 8, 1) + FldFunc(SdrDg_SdDebugRstatus , Codein, 7, 1) + FldFunc(SdrDg_SdDebugRstatus , Host, 6, 1) + FldFunc(SdrDg_SdDebugRstatus , Stream, 5, 1) + FldFunc(SdrDg_SdDebugRstatus , Audio, 4, 1) + FldFunc(SdrDg_SdDebugRstatus , VppOutput, 3, 1) + FldFunc(SdrDg_SdDebugRstatus , Mocomp, 2, 1) + FldFunc(SdrDg_SdDebugRstatus , VppFetch, 1, 1) +RegFunc(SdramDebug, 0x200, SdDebugWstatus , 0x18, SdrDg_SdDebugWstatus , 0x218) + FldFunc(SdrDg_SdDebugWstatus , Deblock, 11, 1) + FldFunc(SdrDg_SdDebugWstatus , Cabac, 10, 1) + FldFunc(SdrDg_SdDebugWstatus , Iloop, 9, 1) + FldFunc(SdrDg_SdDebugWstatus , Oloop, 8, 1) + FldFunc(SdrDg_SdDebugWstatus , Codein, 7, 1) + FldFunc(SdrDg_SdDebugWstatus , Host, 6, 1) + FldFunc(SdrDg_SdDebugWstatus , Stream, 5, 1) + FldFunc(SdrDg_SdDebugWstatus , Audio, 4, 1) + FldFunc(SdrDg_SdDebugWstatus , VppOutput, 3, 1) + FldFunc(SdrDg_SdDebugWstatus , Mocomp, 2, 1) + FldFunc(SdrDg_SdDebugWstatus , VppFetch, 1, 1) +RegFunc(SdramDebug, 0x200, SdPmonConfig, 0x20, SdrDg_SdPmonConfig, 0x220) + FldFunc(SdrDg_SdPmonConfig, Eventselbins, 24, 3) + FldFunc(SdrDg_SdPmonConfig, Eventselport, 16, 4) + FldFunc(SdrDg_SdPmonConfig, Eventselsize, 3, 1) + FldFunc(SdrDg_SdPmonConfig, Eventselread, 2, 1) + FldFunc(SdrDg_SdPmonConfig, Eventdis, 1, 1) + FldFunc(SdrDg_SdPmonConfig, Sdramdis, 0, 1) +RegFunc(SdramDebug, 0x200, SdSdramCycles, 0x24, SdrDg_SdSdramCycles, 0x224) + FldFunc(SdrDg_SdSdramCycles, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdSdramIdles, 0x28, SdrDg_SdSdramIdles, 0x228) + FldFunc(SdrDg_SdSdramIdles, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdSdramWrites, 0x2C, SdrDg_SdSdramWrites, 0x22c) + FldFunc(SdrDg_SdSdramWrites, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdSdramReadsa, 0x30, SdrDg_SdSdramReadsa, 0x230) + FldFunc(SdrDg_SdSdramReadsa, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdSdramReadsb, 0x34, SdrDg_SdSdramReadsb, 0x234) + FldFunc(SdrDg_SdSdramReadsb, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventCount, 0x40, SdrDg_SdEventCount, 0x240) + FldFunc(SdrDg_SdEventCount, Events, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventSum, 0x44, SdrDg_SdEventSum, 0x244) + FldFunc(SdrDg_SdEventSum, Delay, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventMax, 0x48, SdrDg_SdEventMax, 0x248) + FldFunc(SdrDg_SdEventMax, Delay, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin0, 0x60, SdrDg_SdEventBin0, 0x260) + FldFunc(SdrDg_SdEventBin0, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin1, 0x64, SdrDg_SdEventBin1, 0x264) + FldFunc(SdrDg_SdEventBin1, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin2, 0x68, SdrDg_SdEventBin2, 0x268) + FldFunc(SdrDg_SdEventBin2, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin3, 0x6C, SdrDg_SdEventBin3, 0x26c) + FldFunc(SdrDg_SdEventBin3, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin4, 0x70, SdrDg_SdEventBin4, 0x270) + FldFunc(SdrDg_SdEventBin4, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin5, 0x74, SdrDg_SdEventBin5, 0x274) + FldFunc(SdrDg_SdEventBin5, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin6, 0x78, SdrDg_SdEventBin6, 0x278) + FldFunc(SdrDg_SdEventBin6, Count, 0, 24) +RegFunc(SdramDebug, 0x200, SdEventBin7, 0x7C, SdrDg_SdEventBin7, 0x27c) + FldFunc(SdrDg_SdEventBin7, Count, 0, 24) + +RegAreaFunc(DecodeMcomBase, 0x300, 0x31F) +RegFunc(DecodeMcom, 0x300, RegMcomCtl, 0x0, DecMm_RegMcomCtl, 0x300) + FldFunc(DecMm_RegMcomCtl, Bintl, 31, 1) + FldFunc(DecMm_RegMcomCtl, Bref, 24, 7) + FldFunc(DecMm_RegMcomCtl, Aintl, 23, 1) + FldFunc(DecMm_RegMcomCtl, Aref, 16, 7) + FldFunc(DecMm_RegMcomCtl, Subblock, 12, 4) + FldFunc(DecMm_RegMcomCtl, Bbot, 11, 1) + FldFunc(DecMm_RegMcomCtl, Bfld, 10, 1) + FldFunc(DecMm_RegMcomCtl, Abot, 9, 1) + FldFunc(DecMm_RegMcomCtl, Afld, 8, 1) + FldFunc(DecMm_RegMcomCtl, Ysize, 6, 2) + FldFunc(DecMm_RegMcomCtl, Xsize, 4, 2) + FldFunc(DecMm_RegMcomCtl, Luma, 3, 1) + FldFunc(DecMm_RegMcomCtl, Filter261, 2, 1) + FldFunc(DecMm_RegMcomCtl, Mde, 1, 1) + FldFunc(DecMm_RegMcomCtl, Back, 0, 1) +RegFunc(DecodeMcom, 0x300, RegMcomSrcA, 0x4, DecMm_RegMcomSrcA, 0x304) + FldFunc(DecMm_RegMcomSrcA, Ysrc, 16, 16) + FldFunc(DecMm_RegMcomSrcA, Xsrc, 0, 16) +RegFunc(DecodeMcom, 0x300, RegMcomSrcB, 0x8, DecMm_RegMcomSrcB, 0x308) + FldFunc(DecMm_RegMcomSrcB, Ysrc, 16, 16) + FldFunc(DecMm_RegMcomSrcB, Xsrc, 0, 16) +RegFunc(DecodeMcom, 0x300, RegWprdVc1Pic, 0xC, DecMm_RegWprdVc1Pic, 0x30c) + FldFunc(DecMm_RegWprdVc1Pic, 2isoffscrn, 28, 1) + FldFunc(DecMm_RegWprdVc1Pic, Shift2, 22, 6) + FldFunc(DecMm_RegWprdVc1Pic, Scale2, 16, 6) + FldFunc(DecMm_RegWprdVc1Pic, Shift1, 10, 6) + FldFunc(DecMm_RegWprdVc1Pic, Scale1, 4, 6) + FldFunc(DecMm_RegWprdVc1Pic, Bicubic, 1, 1) + FldFunc(DecMm_RegWprdVc1Pic, Rnd, 0, 1) +RegFunc(DecodeMcom, 0x300, RegWprdVc1BotPic, 0x10, DecMm_RegWprdVc1BotPic, 0x310) + FldFunc(DecMm_RegWprdVc1BotPic, 2isoffscrn, 28, 1) + FldFunc(DecMm_RegWprdVc1BotPic, Shift2, 22, 6) + FldFunc(DecMm_RegWprdVc1BotPic, Scale2, 16, 6) + FldFunc(DecMm_RegWprdVc1BotPic, Shift1, 10, 6) + FldFunc(DecMm_RegWprdVc1BotPic, Scale1, 4, 6) +RegFunc(DecodeMcom, 0x300, RegWprdSel, 0x14, DecMm_RegWprdSel, 0x314) + FldFunc(DecMm_RegWprdSel, Wt0, 31, 1) + FldFunc(DecMm_RegWprdSel, A0l1, 30, 1) + FldFunc(DecMm_RegWprdSel, Vecawtsel0, 25, 5) + FldFunc(DecMm_RegWprdSel, Vecbwtsel0, 16, 9) + FldFunc(DecMm_RegWprdSel, Wt1, 15, 1) + FldFunc(DecMm_RegWprdSel, A1l1, 14, 1) + FldFunc(DecMm_RegWprdSel, Vecawtsel1, 9, 5) + FldFunc(DecMm_RegWprdSel, Vecbwtsel1, 0, 9) +RegFunc(DecodeMcom, 0x300, RegWprdVc1BackPic, 0x18, DecMm_RegWprdVc1BackPic, 0x318) + FldFunc(DecMm_RegWprdVc1BackPic, Shift1, 10, 6) + FldFunc(DecMm_RegWprdVc1BackPic, Scale1, 4, 6) + FldFunc(DecMm_RegWprdVc1BackPic, Bot, 0, 1) + +RegAreaFunc(DecodeSpreBase, 0x320, 0x33F) +RegFunc(DecodeSpre, 0x320, RegSpreCtl, 0x0, DecSe_RegSpreCtl, 0x320) + FldFunc(DecSe_RegSpreCtl, Clumode, 16, 2) + FldFunc(DecSe_RegSpreCtl, Predtype, 8, 2) + FldFunc(DecSe_RegSpreCtl, CnstIntra, 4, 1) + FldFunc(DecSe_RegSpreCtl, Ulft, 3, 1) + FldFunc(DecSe_RegSpreCtl, Top, 2, 1) + FldFunc(DecSe_RegSpreCtl, Left, 1, 1) + FldFunc(DecSe_RegSpreCtl, Urt, 0, 1) +RegFunc(DecodeSpre, 0x320, RegSpreMode, 0x4, DecSe_RegSpreMode, 0x324) + FldFunc(DecSe_RegSpreMode, Mode7, 28, 4) + FldFunc(DecSe_RegSpreMode, Mode6, 24, 4) + FldFunc(DecSe_RegSpreMode, Mode5, 20, 4) + FldFunc(DecSe_RegSpreMode, Mode4, 16, 4) + FldFunc(DecSe_RegSpreMode, Mode3, 12, 4) + FldFunc(DecSe_RegSpreMode, Mode2, 8, 4) + FldFunc(DecSe_RegSpreMode, Mode1, 4, 4) + FldFunc(DecSe_RegSpreMode, Mode0, 0, 4) + +RegAreaFunc(DecodeWprdBase, 0x340, 0x35F) +RegFunc(DecodeWprd, 0x340, RegWprdCtl, 0x0, DecWd_RegWprdCtl, 0x340) + FldFunc(DecWd_RegWprdCtl, Chromadenom, 12, 3) + FldFunc(DecWd_RegWprdCtl, Lumdenom, 8, 3) + FldFunc(DecWd_RegWprdCtl, Predtype, 0, 2) + +RegAreaFunc(DecodeDqntBase, 0x400, 0x45F) + +RegAreaFunc(DecodeDqnt8x8Base, 0x500, 0x57F) + +RegAreaFunc(DecodeXfrmBase, 0x700, 0x71F) +RegFunc(DecodeXfrm, 0x700, RegIxfmCtl, 0x0, DecXm_RegIxfmCtl, 0x700) + FldFunc(DecXm_RegIxfmCtl, Xfm, 30, 2) + FldFunc(DecXm_RegIxfmCtl, Scan, 29, 1) + FldFunc(DecXm_RegIxfmCtl, UseQsTab, 28, 1) + FldFunc(DecXm_RegIxfmCtl, Fld, 26, 1) + FldFunc(DecXm_RegIxfmCtl, Odd, 25, 1) + FldFunc(DecXm_RegIxfmCtl, Type, 24, 1) + FldFunc(DecXm_RegIxfmCtl, Qpy, 16, 7) + + //---------------------------------------------------------------------- + // DecXm_RegIxfmCtl + //---------------------------------------------------------------------- + // #define OVERLAPTXM_BIT_SHIFT bit12 + FldFunc(DecXm_RegIxfmCtl, OverlaptxmBitShift, 12, 1) + + FldFunc(DecXm_RegIxfmCtl, Nonuniform, 11, 1) + FldFunc(DecXm_RegIxfmCtl, Acpred, 10, 1) + FldFunc(DecXm_RegIxfmCtl, Halfqp, 9, 1) + FldFunc(DecXm_RegIxfmCtl, Topavail, 8, 1) + FldFunc(DecXm_RegIxfmCtl, Cbp, 0, 5) +RegFunc(DecodeXfrm, 0x700, RegIxfmCoef, 0x4, DecXm_RegIxfmCoef, 0x704) + FldFunc(DecXm_RegIxfmCoef, Run0, 28, 4) + FldFunc(DecXm_RegIxfmCoef, Coef0, 16, 12) + FldFunc(DecXm_RegIxfmCoef, Run1, 12, 4) + FldFunc(DecXm_RegIxfmCoef, Coef1, 0, 12) +RegFunc(DecodeXfrm, 0x700, RegIxfmPcm, 0xC, DecXm_RegIxfmPcm, 0x70c) + FldFunc(DecXm_RegIxfmPcm, Pixel0, 24, 8) + FldFunc(DecXm_RegIxfmPcm, Pixel1, 16, 8) + FldFunc(DecXm_RegIxfmPcm, Pixel2, 8, 8) + FldFunc(DecXm_RegIxfmPcm, Pixel3, 0, 8) +RegFunc(DecodeXfrm, 0x700, RegIxfm264CoefNorun, 0x10, DecXm_RegIxfm264CoefNorun, 0x710) + FldFunc(DecXm_RegIxfm264CoefNorun, Coef1, 16, 16) + FldFunc(DecXm_RegIxfm264CoefNorun, Coef0, 0, 16) +RegFunc(DecodeXfrm, 0x700, RegIxfmBlkSize, 0x14, DecXm_RegIxfmBlkSize, 0x714) + FldFunc(DecXm_RegIxfmBlkSize, Intra, 2, 1) + FldFunc(DecXm_RegIxfmBlkSize, Size, 0, 2) + +RegAreaFunc(DecodeDblkBase, 0x720, 0x73F) +RegFunc(DecodeDblk, 0x720, RegDblkCtl, 0x0, DecDk_RegDblkCtl, 0x720) + FldFunc(DecDk_RegDblkCtl, Mpeg, 8, 1) + FldFunc(DecDk_RegDblkCtl, H2648x8, 7, 1) + FldFunc(DecDk_RegDblkCtl, Mono, 6, 1) + FldFunc(DecDk_RegDblkCtl, IsLast, 5, 1) + FldFunc(DecDk_RegDblkCtl, Intra, 4, 1) + FldFunc(DecDk_RegDblkCtl, Fleft, 3, 1) + FldFunc(DecDk_RegDblkCtl, Ftop, 2, 1) + FldFunc(DecDk_RegDblkCtl, Fint, 1, 1) + FldFunc(DecDk_RegDblkCtl, Ces, 0, 1) +RegFunc(DecodeDblk, 0x720, RegDblkOut, 0x4, DecDk_RegDblkOut, 0x724) + FldFunc(DecDk_RegDblkOut, Out2, 16, 1) + FldFunc(DecDk_RegDblkOut, Picnum2, 8, 8) + FldFunc(DecDk_RegDblkOut, Picnum, 0, 8) +RegFunc(DecodeDblk, 0x720, RegOlapXform, 0x8, DecDk_RegOlapXform, 0x728) + FldFunc(DecDk_RegOlapXform, Topvintra, 29, 1) + FldFunc(DecDk_RegOlapXform, Topuintra, 28, 1) + FldFunc(DecDk_RegOlapXform, Toplintra, 24, 4) + FldFunc(DecDk_RegOlapXform, Vintra, 21, 1) + FldFunc(DecDk_RegOlapXform, Uintra, 20, 1) + FldFunc(DecDk_RegOlapXform, Lumaintra, 16, 4) + FldFunc(DecDk_RegOlapXform, Vv, 11, 1) + FldFunc(DecDk_RegOlapXform, Vh, 10, 1) + FldFunc(DecDk_RegOlapXform, Uv, 9, 1) + FldFunc(DecDk_RegOlapXform, Uh, 8, 1) + FldFunc(DecDk_RegOlapXform, Lumavert, 4, 4) + FldFunc(DecDk_RegOlapXform, Lumahoriz, 0, 4) +RegFunc(DecodeDblk, 0x720, RegDblkQnt, 0xC, DecDk_RegDblkQnt, 0x72c) + FldFunc(DecDk_RegDblkQnt, Opvtoptop, 16, 8) + FldFunc(DecDk_RegDblkQnt, Opvtop, 8, 8) + FldFunc(DecDk_RegDblkQnt, Opv, 0, 8) +RegFunc(DecodeDblk, 0x720, RegDblkOffset, 0x10, DecDk_RegDblkOffset, 0x730) + FldFunc(DecDk_RegDblkOffset, Offsetb, 8, 8) + FldFunc(DecDk_RegDblkOffset, Offseta, 0, 8) +RegFunc(DecodeDblk, 0x720, RegDblkTopCtx, 0x14, DecDk_RegDblkTopCtx, 0x734) + FldFunc(DecDk_RegDblkTopCtx, Tb15, 21, 1) + FldFunc(DecDk_RegDblkTopCtx, Tb14, 20, 1) + FldFunc(DecDk_RegDblkTopCtx, Tb11, 19, 1) + FldFunc(DecDk_RegDblkTopCtx, Tb10, 18, 1) + FldFunc(DecDk_RegDblkTopCtx, Tintra, 16, 1) + FldFunc(DecDk_RegDblkTopCtx, B15, 5, 1) + FldFunc(DecDk_RegDblkTopCtx, B14, 4, 1) + FldFunc(DecDk_RegDblkTopCtx, B11, 3, 1) + FldFunc(DecDk_RegDblkTopCtx, B10, 2, 1) + FldFunc(DecDk_RegDblkTopCtx, Field, 1, 1) + FldFunc(DecDk_RegDblkTopCtx, Intra, 0, 1) +RegFunc(DecodeDblk, 0x720, RegDblkXzero, 0x18, DecDk_RegDblkXzero, 0x738) + FldFunc(DecDk_RegDblkXzero, B15, 15, 1) + FldFunc(DecDk_RegDblkXzero, B14, 14, 1) + FldFunc(DecDk_RegDblkXzero, B13, 13, 1) + FldFunc(DecDk_RegDblkXzero, B12, 12, 1) + FldFunc(DecDk_RegDblkXzero, B11, 11, 1) + FldFunc(DecDk_RegDblkXzero, B10, 10, 1) + FldFunc(DecDk_RegDblkXzero, B9, 9, 1) + FldFunc(DecDk_RegDblkXzero, B8, 8, 1) + FldFunc(DecDk_RegDblkXzero, B7, 7, 1) + FldFunc(DecDk_RegDblkXzero, B6, 6, 1) + FldFunc(DecDk_RegDblkXzero, B5, 5, 1) + FldFunc(DecDk_RegDblkXzero, B4, 4, 1) + FldFunc(DecDk_RegDblkXzero, B3, 3, 1) + FldFunc(DecDk_RegDblkXzero, B2, 2, 1) + FldFunc(DecDk_RegDblkXzero, B1, 1, 1) + FldFunc(DecDk_RegDblkXzero, B0, 0, 1) +RegFunc(DecodeDblk, 0x720, RegDblkMvdiff, 0x1C, DecDk_RegDblkMvdiff, 0x73c) + FldFunc(DecDk_RegDblkMvdiff, V15, 31, 1) + FldFunc(DecDk_RegDblkMvdiff, V14, 30, 1) + FldFunc(DecDk_RegDblkMvdiff, V13, 29, 1) + FldFunc(DecDk_RegDblkMvdiff, V12, 28, 1) + FldFunc(DecDk_RegDblkMvdiff, V11, 27, 1) + FldFunc(DecDk_RegDblkMvdiff, V10, 26, 1) + FldFunc(DecDk_RegDblkMvdiff, V9, 25, 1) + FldFunc(DecDk_RegDblkMvdiff, V8, 24, 1) + FldFunc(DecDk_RegDblkMvdiff, V7, 23, 1) + FldFunc(DecDk_RegDblkMvdiff, V6, 22, 1) + FldFunc(DecDk_RegDblkMvdiff, V5, 21, 1) + FldFunc(DecDk_RegDblkMvdiff, V4, 20, 1) + FldFunc(DecDk_RegDblkMvdiff, V3, 19, 1) + FldFunc(DecDk_RegDblkMvdiff, V2, 18, 1) + FldFunc(DecDk_RegDblkMvdiff, V1, 17, 1) + FldFunc(DecDk_RegDblkMvdiff, V0, 16, 1) + FldFunc(DecDk_RegDblkMvdiff, H15, 15, 1) + FldFunc(DecDk_RegDblkMvdiff, H14, 14, 1) + FldFunc(DecDk_RegDblkMvdiff, H13, 13, 1) + FldFunc(DecDk_RegDblkMvdiff, H12, 12, 1) + FldFunc(DecDk_RegDblkMvdiff, H11, 11, 1) + FldFunc(DecDk_RegDblkMvdiff, H10, 10, 1) + FldFunc(DecDk_RegDblkMvdiff, H9, 9, 1) + FldFunc(DecDk_RegDblkMvdiff, H8, 8, 1) + FldFunc(DecDk_RegDblkMvdiff, H7, 7, 1) + FldFunc(DecDk_RegDblkMvdiff, H6, 6, 1) + FldFunc(DecDk_RegDblkMvdiff, H5, 5, 1) + FldFunc(DecDk_RegDblkMvdiff, H4, 4, 1) + FldFunc(DecDk_RegDblkMvdiff, H3, 3, 1) + FldFunc(DecDk_RegDblkMvdiff, H2, 2, 1) + FldFunc(DecDk_RegDblkMvdiff, H1, 1, 1) + FldFunc(DecDk_RegDblkMvdiff, H0, 0, 1) + +RegAreaFunc(DecodeMbBase, 0x740, 0x75F) +RegFunc(DecodeMb, 0x740, RegMbCtl, 0x0, DecMb_RegMbCtl, 0x740) + FldFunc(DecMb_RegMbCtl, Fcm, 26, 2) + FldFunc(DecMb_RegMbCtl, Type, 24, 2) + FldFunc(DecMb_RegMbCtl, Mbaff, 18, 1) + FldFunc(DecMb_RegMbCtl, Top, 17, 1) + FldFunc(DecMb_RegMbCtl, Fld, 16, 1) + FldFunc(DecMb_RegMbCtl, Ydestmb, 8, 7) + FldFunc(DecMb_RegMbCtl, Rv, 7, 1) + FldFunc(DecMb_RegMbCtl, Xdestmb, 0, 7) + +RegAreaFunc(DecodeIpShimBase, 0x60000, 0x6002F) +RegFunc(DecodeIpShim, 0x60000, Stc0Reg, 0x0, DecISm_Stc0Reg, 0x60000) + FldFunc(DecISm_Stc0Reg, Stc, 0, 32) +RegFunc(DecodeIpShim, 0x60000, Stc1Reg, 0x4, DecISm_Stc1Reg, 0x60004) + FldFunc(DecISm_Stc1Reg, Stc, 0, 32) +RegFunc(DecodeIpShim, 0x60000, EndianReg, 0x8, DecISm_EndianReg, 0x60008) + FldFunc(DecISm_EndianReg, B1l0, 0, 1) +RegFunc(DecodeIpShim, 0x60000, BvnIntReg, 0xC, DecISm_BvnIntReg, 0x6000c) + FldFunc(DecISm_BvnIntReg, Desc, 1, 1) + FldFunc(DecISm_BvnIntReg, Trigger, 0, 1) +RegFunc(DecodeIpShim, 0x60000, CpuId, 0x10, DecISm_CpuId, 0x60010) + FldFunc(DecISm_CpuId, CpuId, 0, 8) +RegFunc(DecodeIpShim, 0x60000, RbusPageReg, 0x14, DecISm_RbusPageReg, 0x60014) + FldFunc(DecISm_RbusPageReg, PageNum, 0, 32) +RegFunc(DecodeIpShim, 0x60000, PfriReg, 0x18, DecISm_PfriReg, 0x60018) + FldFunc(DecISm_PfriReg, PfriError, 16, 1) + FldFunc(DecISm_PfriReg, RstRdPtr, 2, 1) + FldFunc(DecISm_PfriReg, RstWrPtr, 1, 1) + FldFunc(DecISm_PfriReg, RstPfriError, 0, 1) +RegFunc(DecodeIpShim, 0x60000, ScbReg, 0x1C, DecISm_ScbReg, 0x6001c) +RegFunc(DecodeIpShim, 0x60000, ScbPageReg, 0x20, DecISm_ScbPageReg, 0x60020) + FldFunc(DecISm_ScbPageReg, Ena, 31, 1) + FldFunc(DecISm_ScbPageReg, PageVal, 0, 29) +RegFunc(DecodeIpShim, 0x60000, PfriPageReg, 0x24, DecISm_PfriPageReg, 0x60024) + FldFunc(DecISm_PfriPageReg, Ena, 31, 1) + FldFunc(DecISm_PfriPageReg, PageVal, 0, 30) +RegFunc(DecodeIpShim, 0x60000, IntPageReg, 0x28, DecISm_IntPageReg, 0x60028) + FldFunc(DecISm_IntPageReg, PageVal, 2, 30) + FldFunc(DecISm_IntPageReg, Ena, 1, 1) + FldFunc(DecISm_IntPageReg, Id, 0, 1) +RegFunc(DecodeIpShim, 0x60000, DbPageReg, 0x2C, DecISm_DbPageReg, 0x6002c) + FldFunc(DecISm_DbPageReg, Ena, 31, 1) + FldFunc(DecISm_DbPageReg, PageVal, 0, 29) + +RegAreaFunc(DecodeCinABase, 0xA00, 0xA1F) +RegFunc(DecodeCinA, 0xA00, RegCinCtl, 0x0, DecCA_RegCinCtl, 0xa00) + FldFunc(DecCA_RegCinCtl, Emu, 1, 1) + FldFunc(DecCA_RegCinCtl, Ena, 0, 1) +RegFunc(DecodeCinA, 0xA00, RegCinWrPtr, 0x4, DecCA_RegCinWrPtr, 0xa04) + FldFunc(DecCA_RegCinWrPtr, Wrptr, 5, 27) +RegFunc(DecodeCinA, 0xA00, RegCinRdPtr, 0x8, DecCA_RegCinRdPtr, 0xa08) + FldFunc(DecCA_RegCinRdPtr, Rdptr, 5, 27) +RegFunc(DecodeCinA, 0xA00, RegCinBase, 0xC, DecCA_RegCinBase, 0xa0c) + FldFunc(DecCA_RegCinBase, Base, 6, 26) +RegFunc(DecodeCinA, 0xA00, RegCinEnd, 0x10, DecCA_RegCinEnd, 0xa10) + FldFunc(DecCA_RegCinEnd, End, 6, 26) +RegFunc(DecodeCinA, 0xA00, RegCinChannel, 0x14, DecCA_RegCinChannel, 0xa14) + FldFunc(DecCA_RegCinChannel, Channel, 0, 4) +RegFunc(DecodeCinA, 0xA00, RegCinChannelCtl, 0x18, DecCA_RegCinChannelCtl, 0xa18) + FldFunc(DecCA_RegCinChannelCtl, Emul, 1, 1) + FldFunc(DecCA_RegCinChannelCtl, Ena, 0, 1) + +RegAreaFunc(DecodeCinBBase, 0xA20, 0xA3F) +RegFunc(DecodeCinB, 0xA20, RegCinCtl, 0x0, DecCB_RegCinCtl, 0xa20) + FldFunc(DecCB_RegCinCtl, Emu, 1, 1) + FldFunc(DecCB_RegCinCtl, Ena, 0, 1) +RegFunc(DecodeCinB, 0xA20, RegCinWrPtr, 0x4, DecCB_RegCinWrPtr, 0xa24) + FldFunc(DecCB_RegCinWrPtr, Wrptr, 5, 27) +RegFunc(DecodeCinB, 0xA20, RegCinRdPtr, 0x8, DecCB_RegCinRdPtr, 0xa28) + FldFunc(DecCB_RegCinRdPtr, Rdptr, 5, 27) +RegFunc(DecodeCinB, 0xA20, RegCinBase, 0xC, DecCB_RegCinBase, 0xa2c) + FldFunc(DecCB_RegCinBase, Base, 6, 26) +RegFunc(DecodeCinB, 0xA20, RegCinEnd, 0x10, DecCB_RegCinEnd, 0xa30) + FldFunc(DecCB_RegCinEnd, End, 6, 26) +RegFunc(DecodeCinB, 0xA20, RegCinChannel, 0x14, DecCB_RegCinChannel, 0xa34) + FldFunc(DecCB_RegCinChannel, Channel, 0, 4) +RegFunc(DecodeCinB, 0xA20, RegCinChannelCtl, 0x18, DecCB_RegCinChannelCtl, 0xa38) + FldFunc(DecCB_RegCinChannelCtl, Emul, 1, 1) + FldFunc(DecCB_RegCinChannelCtl, Ena, 0, 1) + +RegAreaFunc(RegCabac2binsBase, 0xB00, 0xBFF) +RegFunc(RegCabac2bins, 0xB00, RegCabac2binsImgCtxLast, 0xBC, RegCs_RegCabac2binsImgCtxLast, 0xbbc) + FldFunc(RegCs_RegCabac2binsImgCtxLast, Ctxlast, 0, 9) +RegFunc(RegCabac2bins, 0xB00, RegCabac2binsRdContextBaseAddr, 0xD0, RegCs_RegCabac2binsRdContextBaseAddr, 0xbd0) + FldFunc(RegCs_RegCabac2binsRdContextBaseAddr, Addr, 0, 32) +RegFunc(RegCabac2bins, 0xB00, RegCabac2binsWrContextBaseAddr, 0xD4, RegCs_RegCabac2binsWrContextBaseAddr, 0xbd4) + FldFunc(RegCs_RegCabac2binsWrContextBaseAddr, Addr, 0, 32) + +RegAreaFunc(DecodeSintBase, 0xC00, 0xDFF) +RegFunc(DecodeSint, 0xC00, RegSintDmaAddr, 0x0, DecSt_RegSintDmaAddr, 0xc00) + FldFunc(DecSt_RegSintDmaAddr, Addr, 5, 27) +RegFunc(DecodeSint, 0xC00, RegSintDmaLen, 0x4, DecSt_RegSintDmaLen, 0xc04) + FldFunc(DecSt_RegSintDmaLen, Length, 5, 27) +RegFunc(DecodeSint, 0xC00, RegSintDmaBase, 0x8, DecSt_RegSintDmaBase, 0xc08) + FldFunc(DecSt_RegSintDmaBase, Base, 6, 26) +RegFunc(DecodeSint, 0xC00, RegSintDmaEnd, 0xC, DecSt_RegSintDmaEnd, 0xc0c) + FldFunc(DecSt_RegSintDmaEnd, End, 6, 26) +RegFunc(DecodeSint, 0xC00, RegSintStrmPos, 0x10, DecSt_RegSintStrmPos, 0xc10) + FldFunc(DecSt_RegSintStrmPos, BitPos, 0, 32) +RegFunc(DecodeSint, 0xC00, RegSintStrmStat, 0x14, DecSt_RegSintStrmStat, 0xc14) + FldFunc(DecSt_RegSintStrmStat, Rst, 16, 1) + FldFunc(DecSt_RegSintStrmStat, MvdAvail, 10, 1) + FldFunc(DecSt_RegSintStrmStat, Derr, 9, 1) + FldFunc(DecSt_RegSintStrmStat, Serr, 8, 1) + FldFunc(DecSt_RegSintStrmStat, Ccac, 6, 1) + FldFunc(DecSt_RegSintStrmStat, Vcac, 5, 1) + FldFunc(DecSt_RegSintStrmStat, Vact, 4, 1) + FldFunc(DecSt_RegSintStrmStat, Dact, 3, 1) + FldFunc(DecSt_RegSintStrmStat, Sact, 2, 1) + FldFunc(DecSt_RegSintStrmStat, Cact, 1, 1) + FldFunc(DecSt_RegSintStrmStat, Sval, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintIena, 0x18, DecSt_RegSintIena, 0xc18) + FldFunc(DecSt_RegSintIena, Derr, 9, 1) + FldFunc(DecSt_RegSintIena, Serr, 8, 1) +RegFunc(DecodeSint, 0xC00, RegSintStrmBits, 0x1C, DecSt_RegSintStrmBits, 0xc1c) + FldFunc(DecSt_RegSintStrmBits, StreamBits, 0, 32) +RegFunc(DecodeSint, 0xC00, RegSintGetSymb, 0x20, DecSt_RegSintGetSymb, 0xc20) + FldFunc(DecSt_RegSintGetSymb, Type, 12, 4) + FldFunc(DecSt_RegSintGetSymb, Subtype, 8, 4) + FldFunc(DecSt_RegSintGetSymb, N, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintMpegDc, 0x24, DecSt_RegSintMpegDc, 0xc24) + FldFunc(DecSt_RegSintMpegDc, Comp, 12, 2) + FldFunc(DecSt_RegSintMpegDc, DcPred, 0, 12) +RegFunc(DecodeSint, 0xC00, RegSintDoResid, 0x28, DecSt_RegSintDoResid, 0xc28) + FldFunc(DecSt_RegSintDoResid, Type, 14, 2) + FldFunc(DecSt_RegSintDoResid, Subtype, 12, 2) + FldFunc(DecSt_RegSintDoResid, Wrxnzero, 10, 1) + FldFunc(DecSt_RegSintDoResid, Dcprecision, 8, 2) + FldFunc(DecSt_RegSintDoResid, Vlctable1, 7, 1) + FldFunc(DecSt_RegSintDoResid, Intra, 6, 1) + FldFunc(DecSt_RegSintDoResid, Cbp, 0, 6) +RegFunc(DecodeSint, 0xC00, RegSintXnzero, 0x2C, DecSt_RegSintXnzero, 0xc2c) + FldFunc(DecSt_RegSintXnzero, B15, 15, 1) + FldFunc(DecSt_RegSintXnzero, B14, 14, 1) + FldFunc(DecSt_RegSintXnzero, B13, 13, 1) + FldFunc(DecSt_RegSintXnzero, B12, 12, 1) + FldFunc(DecSt_RegSintXnzero, B11, 11, 1) + FldFunc(DecSt_RegSintXnzero, B10, 10, 1) + FldFunc(DecSt_RegSintXnzero, B9, 9, 1) + FldFunc(DecSt_RegSintXnzero, B8, 8, 1) + FldFunc(DecSt_RegSintXnzero, B7, 7, 1) + FldFunc(DecSt_RegSintXnzero, B6, 6, 1) + FldFunc(DecSt_RegSintXnzero, B5, 5, 1) + FldFunc(DecSt_RegSintXnzero, B4, 4, 1) + FldFunc(DecSt_RegSintXnzero, B3, 3, 1) + FldFunc(DecSt_RegSintXnzero, B2, 2, 1) + FldFunc(DecSt_RegSintXnzero, B1, 1, 1) + FldFunc(DecSt_RegSintXnzero, B0, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintVecMbtype, 0x30, DecSt_RegSintVecMbtype, 0xc30) + FldFunc(DecSt_RegSintVecMbtype, Submbtype3, 21, 4) + FldFunc(DecSt_RegSintVecMbtype, Submbtype2, 16, 4) + FldFunc(DecSt_RegSintVecMbtype, Submbtype1, 11, 4) + FldFunc(DecSt_RegSintVecMbtype, Submbtype0, 6, 4) + FldFunc(DecSt_RegSintVecMbtype, Mbtype, 1, 5) + FldFunc(DecSt_RegSintVecMbtype, Isb, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintVecRegstart, 0x30, DecSt_RegSintVecRegstart, 0xc30) +RegFunc(DecodeSint, 0xC00, RegSintVecResid, 0x34, DecSt_RegSintVecResid, 0xc34) + FldFunc(DecSt_RegSintVecResid, YResidual, 16, 16) + FldFunc(DecSt_RegSintVecResid, XResidual, 0, 16) +RegFunc(DecodeSint, 0xC00, RegSintVecDmode, 0x38, DecSt_RegSintVecDmode, 0xc38) + FldFunc(DecSt_RegSintVecDmode, Dmode, 0, 4) +RegFunc(DecodeSint, 0xC00, RegSintVecTopLd, 0x3C, DecSt_RegSintVecTopLd, 0xc3c) + FldFunc(DecSt_RegSintVecTopLd, TopRow, 30, 2) + FldFunc(DecSt_RegSintVecTopLd, TtropOffset, 16, 8) + FldFunc(DecSt_RegSintVecTopLd, UrtOffset, 8, 8) + FldFunc(DecSt_RegSintVecTopLd, TopOffest, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintVecDoConst, 0x40, DecSt_RegSintVecDoConst, 0xc40) + FldFunc(DecSt_RegSintVecDoConst, Mvdiff, 9, 1) + FldFunc(DecSt_RegSintVecDoConst, Rolt, 8, 1) + FldFunc(DecSt_RegSintVecDoConst, Lcpy, 7, 1) + FldFunc(DecSt_RegSintVecDoConst, Ulfld, 6, 1) + FldFunc(DecSt_RegSintVecDoConst, Pskip, 5, 1) + FldFunc(DecSt_RegSintVecDoConst, Intra, 4, 1) +RegFunc(DecodeSint, 0xC00, RegSintVecMvdiff, 0x44, DecSt_RegSintVecMvdiff, 0xc44) + FldFunc(DecSt_RegSintVecMvdiff, V15, 31, 1) + FldFunc(DecSt_RegSintVecMvdiff, V14, 30, 1) + FldFunc(DecSt_RegSintVecMvdiff, V13, 29, 1) + FldFunc(DecSt_RegSintVecMvdiff, V12, 28, 1) + FldFunc(DecSt_RegSintVecMvdiff, V11, 27, 1) + FldFunc(DecSt_RegSintVecMvdiff, V10, 26, 1) + FldFunc(DecSt_RegSintVecMvdiff, V9, 25, 1) + FldFunc(DecSt_RegSintVecMvdiff, V8, 24, 1) + FldFunc(DecSt_RegSintVecMvdiff, V7, 23, 1) + FldFunc(DecSt_RegSintVecMvdiff, V6, 22, 1) + FldFunc(DecSt_RegSintVecMvdiff, V5, 21, 1) + FldFunc(DecSt_RegSintVecMvdiff, V4, 20, 1) + FldFunc(DecSt_RegSintVecMvdiff, V3, 19, 1) + FldFunc(DecSt_RegSintVecMvdiff, V2, 18, 1) + FldFunc(DecSt_RegSintVecMvdiff, V1, 17, 1) + FldFunc(DecSt_RegSintVecMvdiff, V0, 16, 1) + FldFunc(DecSt_RegSintVecMvdiff, H15, 15, 1) + FldFunc(DecSt_RegSintVecMvdiff, H14, 14, 1) + FldFunc(DecSt_RegSintVecMvdiff, H13, 13, 1) + FldFunc(DecSt_RegSintVecMvdiff, H12, 12, 1) + FldFunc(DecSt_RegSintVecMvdiff, H11, 11, 1) + FldFunc(DecSt_RegSintVecMvdiff, H10, 10, 1) + FldFunc(DecSt_RegSintVecMvdiff, H9, 9, 1) + FldFunc(DecSt_RegSintVecMvdiff, H8, 8, 1) + FldFunc(DecSt_RegSintVecMvdiff, H7, 7, 1) + FldFunc(DecSt_RegSintVecMvdiff, H6, 6, 1) + FldFunc(DecSt_RegSintVecMvdiff, H5, 5, 1) + FldFunc(DecSt_RegSintVecMvdiff, H4, 4, 1) + FldFunc(DecSt_RegSintVecMvdiff, H3, 3, 1) + FldFunc(DecSt_RegSintVecMvdiff, H2, 2, 1) + FldFunc(DecSt_RegSintVecMvdiff, H1, 1, 1) + FldFunc(DecSt_RegSintVecMvdiff, H0, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintVecRefidx, 0x48, DecSt_RegSintVecRefidx, 0xc48) + FldFunc(DecSt_RegSintVecRefidx, Refidx3, 24, 6) + FldFunc(DecSt_RegSintVecRefidx, Refidx2, 16, 6) + FldFunc(DecSt_RegSintVecRefidx, Refidx1, 8, 6) + FldFunc(DecSt_RegSintVecRefidx, Refidx0, 0, 6) +RegFunc(DecodeSint, 0xC00, RegSintVecTopref, 0x4C, DecSt_RegSintVecTopref, 0xc4c) + FldFunc(DecSt_RegSintVecTopref, L1refb1, 24, 8) + FldFunc(DecSt_RegSintVecTopref, L1refb0, 16, 8) + FldFunc(DecSt_RegSintVecTopref, L0refb1, 8, 8) + FldFunc(DecSt_RegSintVecTopref, L0refb0, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintVecToppic, 0x5C, DecSt_RegSintVecToppic, 0xc5c) + FldFunc(DecSt_RegSintVecToppic, L1picb1, 24, 8) + FldFunc(DecSt_RegSintVecToppic, L1picb0, 16, 8) + FldFunc(DecSt_RegSintVecToppic, L0picb1, 8, 8) + FldFunc(DecSt_RegSintVecToppic, L0picb0, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintVecToptopref, 0x50, DecSt_RegSintVecToptopref, 0xc50) + FldFunc(DecSt_RegSintVecToptopref, L1picb1, 24, 8) + FldFunc(DecSt_RegSintVecToptopref, L0picb1, 8, 8) +RegFunc(DecodeSint, 0xC00, RegSintVecColType, 0x54, DecSt_RegSintVecColType, 0xc54) + FldFunc(DecSt_RegSintVecColType, Mbaff, 31, 1) + FldFunc(DecSt_RegSintVecColType, Tfld, 30, 1) + FldFunc(DecSt_RegSintVecColType, Field, 29, 1) + FldFunc(DecSt_RegSintVecColType, Sub3, 8, 2) + FldFunc(DecSt_RegSintVecColType, Sub2, 6, 2) + FldFunc(DecSt_RegSintVecColType, Sub1, 4, 2) + FldFunc(DecSt_RegSintVecColType, Sub0, 2, 2) + FldFunc(DecSt_RegSintVecColType, Type, 0, 2) +RegFunc(DecodeSint, 0xC00, RegSintVecColRefid, 0x58, DecSt_RegSintVecColRefid, 0xc58) + FldFunc(DecSt_RegSintVecColRefid, Refidx3, 24, 5) + FldFunc(DecSt_RegSintVecColRefid, Refidx2, 16, 5) + FldFunc(DecSt_RegSintVecColRefid, Refidx1, 8, 5) + FldFunc(DecSt_RegSintVecColRefid, Refidx0, 0, 5) +RegFunc(DecodeSint, 0xC00, RegSintVecVc1Info, 0x60, DecSt_RegSintVecVc1Info, 0xc60) + FldFunc(DecSt_RegSintVecVc1Info, IntraFlags, 16, 6) + FldFunc(DecSt_RegSintVecVc1Info, Cbpcy, 8, 6) + FldFunc(DecSt_RegSintVecVc1Info, BmvType, 4, 2) + FldFunc(DecSt_RegSintVecVc1Info, 4mv, 3, 1) + FldFunc(DecSt_RegSintVecVc1Info, GetAcPred, 2, 1) + FldFunc(DecSt_RegSintVecVc1Info, CoefsPres, 1, 1) + FldFunc(DecSt_RegSintVecVc1Info, Intra, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintVecRefpic, 0x64, DecSt_RegSintVecRefpic, 0xc64) + FldFunc(DecSt_RegSintVecRefpic, Hwimpiwt, 2, 1) + FldFunc(DecSt_RegSintVecRefpic, Userrev, 1, 1) + FldFunc(DecSt_RegSintVecRefpic, Ramsel, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintVecCount, 0x68, DecSt_RegSintVecCount, 0xc68) + FldFunc(DecSt_RegSintVecCount, Cnt8x8ua, 16, 16) + FldFunc(DecSt_RegSintVecCount, Cnt8x8, 0, 16) +RegFunc(DecodeSint, 0xC00, RegSintVecMvdFifo, 0x6C, DecSt_RegSintVecMvdFifo, 0xc6c) + FldFunc(DecSt_RegSintVecMvdFifo, Data, 0, 32) +RegFunc(DecodeSint, 0xC00, RegSintVecRegend, 0x7F, DecSt_RegSintVecRegend, 0xc7f) +RegFunc(DecodeSint, 0xC00, RegSintCtl, 0x80, DecSt_RegSintCtl, 0xc80) + FldFunc(DecSt_RegSintCtl, Vc1, 31, 1) + + //---------------------------------------------------------------------- + // DecSt_RegSintCtl + //---------------------------------------------------------------------- + //#define SINT_VC1_PROFILE bit22..23 + FldFunc(DecSt_RegSintCtl, Profile, 22, 2) + + FldFunc(DecSt_RegSintCtl, Iwtpred, 21, 1) + FldFunc(DecSt_RegSintCtl, Wtpred, 20, 1) + FldFunc(DecSt_RegSintCtl, L1Eq2, 17, 1) + FldFunc(DecSt_RegSintCtl, L1Eq1, 16, 1) + FldFunc(DecSt_RegSintCtl, L0Eq2, 15, 1) + FldFunc(DecSt_RegSintCtl, L0Eq1, 14, 1) + FldFunc(DecSt_RegSintCtl, Dir8x8, 11, 1) + FldFunc(DecSt_RegSintCtl, SpaDir, 10, 1) + FldFunc(DecSt_RegSintCtl, Ptype, 8, 2) + FldFunc(DecSt_RegSintCtl, Mbaff, 7, 1) + FldFunc(DecSt_RegSintCtl, Tfld, 6, 1) + FldFunc(DecSt_RegSintCtl, Field, 5, 1) + FldFunc(DecSt_RegSintCtl, Cavlc, 4, 1) + FldFunc(DecSt_RegSintCtl, Uleft, 3, 1) + FldFunc(DecSt_RegSintCtl, Top, 2, 1) + FldFunc(DecSt_RegSintCtl, Left, 1, 1) + FldFunc(DecSt_RegSintCtl, Urtavail, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintVlcTopctx, 0x84, DecSt_RegSintVlcTopctx, 0xc84) + FldFunc(DecSt_RegSintVlcTopctx, V2, 28, 4) + FldFunc(DecSt_RegSintVlcTopctx, V3, 24, 4) + FldFunc(DecSt_RegSintVlcTopctx, U2, 20, 4) + FldFunc(DecSt_RegSintVlcTopctx, U3, 16, 4) + FldFunc(DecSt_RegSintVlcTopctx, Lum10, 12, 4) + FldFunc(DecSt_RegSintVlcTopctx, Lum11, 8, 4) + FldFunc(DecSt_RegSintVlcTopctx, Lum14, 4, 4) + FldFunc(DecSt_RegSintVlcTopctx, Lum15, 0, 4) +RegFunc(DecodeSint, 0xC00, RegSintSliceId, 0x88, DecSt_RegSintSliceId, 0xc88) + FldFunc(DecSt_RegSintSliceId, Sliceid, 0, 12) +RegFunc(DecodeSint, 0xC00, RegSintQp, 0x8C, DecSt_RegSintQp, 0xc8c) + FldFunc(DecSt_RegSintQp, Qp, 0, 6) +RegFunc(DecodeSint, 0xC00, RegSintTopBaseAddr, 0x90, DecSt_RegSintTopBaseAddr, 0xc90) + FldFunc(DecSt_RegSintTopBaseAddr, Addr, 0, 32) +RegFunc(DecodeSint, 0xC00, RegSintDirctxWrAddr, 0x94, DecSt_RegSintDirctxWrAddr, 0xc94) + FldFunc(DecSt_RegSintDirctxWrAddr, Addr, 0, 32) +RegFunc(DecodeSint, 0xC00, RegSintTopctxData, 0x98, DecSt_RegSintTopctxData, 0xc98) + FldFunc(DecSt_RegSintTopctxData, Data, 0, 32) +RegFunc(DecodeSint, 0xC00, RegSintXferSymb, 0x9C, DecSt_RegSintXferSymb, 0xc9c) + FldFunc(DecSt_RegSintXferSymb, Type, 8, 8) + FldFunc(DecSt_RegSintXferSymb, N, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintSmodeBase, 0xA0, DecSt_RegSintSmodeBase, 0xca0) +RegFunc(DecodeSint, 0xC00, RegSintSmodeEnd, 0xAC, DecSt_RegSintSmodeEnd, 0xcac) +RegFunc(DecodeSint, 0xC00, RegSintSmodeData, 0xA0, DecSt_RegSintSmodeData, 0xca0) + FldFunc(DecSt_RegSintSmodeData, Mode0, 28, 4) + FldFunc(DecSt_RegSintSmodeData, Mode1, 24, 4) + FldFunc(DecSt_RegSintSmodeData, Mode2, 20, 4) + FldFunc(DecSt_RegSintSmodeData, Mode3, 16, 4) + FldFunc(DecSt_RegSintSmodeData, Mode4, 12, 4) + FldFunc(DecSt_RegSintSmodeData, Mode5, 8, 4) + FldFunc(DecSt_RegSintSmodeData, Mode6, 4, 4) + FldFunc(DecSt_RegSintSmodeData, Mode7, 0, 4) +RegFunc(DecodeSint, 0xC00, RegSintSmodeLeft, 0xA4, DecSt_RegSintSmodeLeft, 0xca4) + FldFunc(DecSt_RegSintSmodeLeft, Leftmode5, 12, 4) + FldFunc(DecSt_RegSintSmodeLeft, Leftmode7, 8, 4) + FldFunc(DecSt_RegSintSmodeLeft, Leftmode13, 4, 4) + FldFunc(DecSt_RegSintSmodeLeft, Leftmode15, 0, 4) +RegFunc(DecodeSint, 0xC00, RegSintSmodeTop, 0xA8, DecSt_RegSintSmodeTop, 0xca8) + FldFunc(DecSt_RegSintSmodeTop, Topmode10, 12, 4) + FldFunc(DecSt_RegSintSmodeTop, Topmode11, 8, 4) + FldFunc(DecSt_RegSintSmodeTop, Topmode14, 4, 4) + FldFunc(DecSt_RegSintSmodeTop, Topmode15, 0, 4) +RegFunc(DecodeSint, 0xC00, RegSintCtxInit, 0xB0, DecSt_RegSintCtxInit, 0xcb0) + FldFunc(DecSt_RegSintCtxInit, Mbaff, 24, 1) + FldFunc(DecSt_RegSintCtxInit, Mbwidth, 16, 8) + FldFunc(DecSt_RegSintCtxInit, Ypos, 8, 8) + FldFunc(DecSt_RegSintCtxInit, Xpos, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintTopCtx, 0xB4, DecSt_RegSintTopCtx, 0xcb4) + FldFunc(DecSt_RegSintTopCtx, TopTop, 4, 1) + FldFunc(DecSt_RegSintTopCtx, RdOffset, 0, 4) +RegFunc(DecodeSint, 0xC00, RegSintVc1Tabsel, 0xB8, DecSt_RegSintVc1Tabsel, 0xcb8) + FldFunc(DecSt_RegSintVc1Tabsel, EscLvlSz, 23, 1) + FldFunc(DecSt_RegSintVc1Tabsel, Ttype, 21, 2) + FldFunc(DecSt_RegSintVc1Tabsel, InterAc, 19, 2) + FldFunc(DecSt_RegSintVc1Tabsel, YIntraAc, 17, 2) + FldFunc(DecSt_RegSintVc1Tabsel, Dctable, 16, 1) + FldFunc(DecSt_RegSintVc1Tabsel, Mbmode, 12, 3) + FldFunc(DecSt_RegSintVc1Tabsel, 2ref, 11, 1) + FldFunc(DecSt_RegSintVc1Tabsel, Cppcy, 4, 3) + FldFunc(DecSt_RegSintVc1Tabsel, 2mbPat, 2, 2) + FldFunc(DecSt_RegSintVc1Tabsel, 4mbPat, 0, 2) +RegFunc(DecodeSint, 0xC00, RegSintCnstIntra, 0xBC, DecSt_RegSintCnstIntra, 0xcbc) + FldFunc(DecSt_RegSintCnstIntra, Ulftavail, 3, 1) + FldFunc(DecSt_RegSintCnstIntra, Topavail, 2, 1) + FldFunc(DecSt_RegSintCnstIntra, Leftavail, 1, 1) + FldFunc(DecSt_RegSintCnstIntra, Urtavail, 0, 1) +RegFunc(DecodeSint, 0xC00, RegSintOpicMemBase, 0xC0, DecSt_RegSintOpicMemBase, 0xcc0) + FldFunc(DecSt_RegSintOpicMemBase, Outpic3, 24, 8) + FldFunc(DecSt_RegSintOpicMemBase, Outpic2, 16, 8) + FldFunc(DecSt_RegSintOpicMemBase, Outpic1, 8, 8) + FldFunc(DecSt_RegSintOpicMemBase, Outpic0, 0, 8) +RegFunc(DecodeSint, 0xC00, RegSintVecMemBase, 0x100, DecSt_RegSintVecMemBase, 0xd00) + FldFunc(DecSt_RegSintVecMemBase, VectorYDelta, 16, 16) + FldFunc(DecSt_RegSintVecMemBase, VectorXDelta, 0, 16) +RegFunc(DecodeSint, 0xC00, RegSintOpicMemEnd, 0xFF, DecSt_RegSintOpicMemEnd, 0xcff) +RegFunc(DecodeSint, 0xC00, RegSintVecMemEnd, 0x1FF, DecSt_RegSintVecMemEnd, 0xdff) + +RegAreaFunc(DecodeRvcBase, 0xE00, 0xEFF) +RegFunc(DecodeRvc, 0xE00, RegRvcCtl, 0x0, DecRc_RegRvcCtl, 0xe00) + FldFunc(DecRc_RegRvcCtl, Ena, 0, 1) +RegFunc(DecodeRvc, 0xE00, RegRvcPut, 0x4, DecRc_RegRvcPut, 0xe04) + FldFunc(DecRc_RegRvcPut, PutPtr, 0, 32) +RegFunc(DecodeRvc, 0xE00, RegRvcGet, 0x8, DecRc_RegRvcGet, 0xe08) + FldFunc(DecRc_RegRvcGet, GetPtr, 5, 23) +RegFunc(DecodeRvc, 0xE00, RegRvcBase, 0xC, DecRc_RegRvcBase, 0xe0c) + FldFunc(DecRc_RegRvcBase, BaseAddr, 20, 8) +RegFunc(DecodeRvc, 0xE00, RegRvcEnd, 0x10, DecRc_RegRvcEnd, 0xe10) + FldFunc(DecRc_RegRvcEnd, EndAddr, 20, 8) + +RegAreaFunc(DecodeCpuregsBase, 0xF00, 0xF7F) +RegFunc(DecodeCpuregs, 0xF00, RegHst2cpuMbx, 0x0, DecCs_RegHst2cpuMbx, 0xf00) + FldFunc(DecCs_RegHst2cpuMbx, Value, 0, 32) +RegFunc(DecodeCpuregs, 0xF00, RegCpu2hstMbx, 0x4, DecCs_RegCpu2hstMbx, 0xf04) + FldFunc(DecCs_RegCpu2hstMbx, Value, 0, 32) +RegFunc(DecodeCpuregs, 0xF00, RegMbxStat, 0x8, DecCs_RegMbxStat, 0xf08) + FldFunc(DecCs_RegMbxStat, C2h, 1, 1) + FldFunc(DecCs_RegMbxStat, H2c, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, RegCpuIntEna, 0x10, DecCs_RegCpuIntEna, 0xf10) + FldFunc(DecCs_RegCpuIntEna, Mbx, 31, 1) + FldFunc(DecCs_RegCpuIntEna, Com7, 23, 1) + FldFunc(DecCs_RegCpuIntEna, Com6, 22, 1) + FldFunc(DecCs_RegCpuIntEna, Com5, 21, 1) + FldFunc(DecCs_RegCpuIntEna, Com4, 20, 1) + FldFunc(DecCs_RegCpuIntEna, Com3, 19, 1) + FldFunc(DecCs_RegCpuIntEna, Com2, 18, 1) + FldFunc(DecCs_RegCpuIntEna, Com1, 17, 1) + FldFunc(DecCs_RegCpuIntEna, Com0, 16, 1) + FldFunc(DecCs_RegCpuIntEna, Hw7, 15, 1) + FldFunc(DecCs_RegCpuIntEna, Hw6, 14, 1) + FldFunc(DecCs_RegCpuIntEna, Hw5, 13, 1) + FldFunc(DecCs_RegCpuIntEna, Hw4, 12, 1) + FldFunc(DecCs_RegCpuIntEna, Hw3, 11, 1) + FldFunc(DecCs_RegCpuIntEna, Hw2, 10, 1) + FldFunc(DecCs_RegCpuIntEna, Hw1, 9, 1) + FldFunc(DecCs_RegCpuIntEna, Hw0, 8, 1) + FldFunc(DecCs_RegCpuIntEna, Db7, 7, 1) + FldFunc(DecCs_RegCpuIntEna, Db6, 6, 1) + FldFunc(DecCs_RegCpuIntEna, Db5, 5, 1) + FldFunc(DecCs_RegCpuIntEna, Db4, 4, 1) + FldFunc(DecCs_RegCpuIntEna, Db3, 3, 1) + FldFunc(DecCs_RegCpuIntEna, Db2, 2, 1) + FldFunc(DecCs_RegCpuIntEna, Db1, 1, 1) + FldFunc(DecCs_RegCpuIntEna, Db0, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, StreamCpuIntEna, 0x10, DecCs_StreamCpuIntEna, 0xf10) + FldFunc(DecCs_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(DecCs_StreamCpuIntEna, Dec, 18, 1) + FldFunc(DecCs_StreamCpuIntEna, Aud, 17, 1) + FldFunc(DecCs_StreamCpuIntEna, M2m, 15, 1) + FldFunc(DecCs_StreamCpuIntEna, Pci, 14, 1) + FldFunc(DecCs_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(DecCs_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(DecCs_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(DecCs_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(DecCs_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(DecCs_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(DecCs_StreamCpuIntEna, Rb, 1, 1) + FldFunc(DecCs_StreamCpuIntEna, Sd, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, Dec0CpuIntEna, 0x10, DecCs_Dec0CpuIntEna, 0xf10) + FldFunc(DecCs_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(DecCs_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(DecCs_Dec0CpuIntEna, Si, 8, 1) + FldFunc(DecCs_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(DecCs_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, Dec1CpuIntEna, 0x10, DecCs_Dec1CpuIntEna, 0xf10) + FldFunc(DecCs_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(DecCs_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(DecCs_Dec1CpuIntEna, Si, 8, 1) + FldFunc(DecCs_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(DecCs_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, RegCpuIntStat, 0x14, DecCs_RegCpuIntStat, 0xf14) + FldFunc(DecCs_RegCpuIntStat, Mbx, 31, 1) + FldFunc(DecCs_RegCpuIntStat, Com7, 23, 1) + FldFunc(DecCs_RegCpuIntStat, Com6, 22, 1) + FldFunc(DecCs_RegCpuIntStat, Com5, 21, 1) + FldFunc(DecCs_RegCpuIntStat, Com4, 20, 1) + FldFunc(DecCs_RegCpuIntStat, Com3, 19, 1) + FldFunc(DecCs_RegCpuIntStat, Com2, 18, 1) + FldFunc(DecCs_RegCpuIntStat, Com1, 17, 1) + FldFunc(DecCs_RegCpuIntStat, Com0, 16, 1) + FldFunc(DecCs_RegCpuIntStat, Hw7, 15, 1) + FldFunc(DecCs_RegCpuIntStat, Hw6, 14, 1) + FldFunc(DecCs_RegCpuIntStat, Hw5, 13, 1) + FldFunc(DecCs_RegCpuIntStat, Hw4, 12, 1) + FldFunc(DecCs_RegCpuIntStat, Hw3, 11, 1) + FldFunc(DecCs_RegCpuIntStat, Hw2, 10, 1) + FldFunc(DecCs_RegCpuIntStat, Hw1, 9, 1) + FldFunc(DecCs_RegCpuIntStat, Hw0, 8, 1) + FldFunc(DecCs_RegCpuIntStat, Db7, 7, 1) + FldFunc(DecCs_RegCpuIntStat, Db6, 6, 1) + FldFunc(DecCs_RegCpuIntStat, Db5, 5, 1) + FldFunc(DecCs_RegCpuIntStat, Db4, 4, 1) + FldFunc(DecCs_RegCpuIntStat, Db3, 3, 1) + FldFunc(DecCs_RegCpuIntStat, Db2, 2, 1) + FldFunc(DecCs_RegCpuIntStat, Db1, 1, 1) + FldFunc(DecCs_RegCpuIntStat, Db0, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, StreamCpuIntStat, 0x14, DecCs_StreamCpuIntStat, 0xf14) + FldFunc(DecCs_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(DecCs_StreamCpuIntStat, Dec, 18, 1) + FldFunc(DecCs_StreamCpuIntStat, Aud, 17, 1) + FldFunc(DecCs_StreamCpuIntStat, M2m, 15, 1) + FldFunc(DecCs_StreamCpuIntStat, Pci, 14, 1) + FldFunc(DecCs_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(DecCs_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(DecCs_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(DecCs_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(DecCs_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(DecCs_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(DecCs_StreamCpuIntStat, Rb, 1, 1) + FldFunc(DecCs_StreamCpuIntStat, Sd, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, Dec0CpuIntStat, 0x14, DecCs_Dec0CpuIntStat, 0xf14) + FldFunc(DecCs_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(DecCs_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(DecCs_Dec0CpuIntStat, Si, 8, 1) + FldFunc(DecCs_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(DecCs_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, Dec1CpuIntStat, 0x14, DecCs_Dec1CpuIntStat, 0xf14) + FldFunc(DecCs_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(DecCs_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(DecCs_Dec1CpuIntStat, Si, 8, 1) + FldFunc(DecCs_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(DecCs_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, RegHst2cpuStat, 0x18, DecCs_RegHst2cpuStat, 0xf18) + FldFunc(DecCs_RegHst2cpuStat, Value, 0, 32) +RegFunc(DecodeCpuregs, 0xF00, RegCpu2hstStat, 0x1C, DecCs_RegCpu2hstStat, 0xf1c) + FldFunc(DecCs_RegCpu2hstStat, Value, 0, 32) +RegFunc(DecodeCpuregs, 0xF00, RegCpuIntgenSet, 0x20, DecCs_RegCpuIntgenSet, 0xf20) + FldFunc(DecCs_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(DecCs_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, RegCpuIntgenClr, 0x24, DecCs_RegCpuIntgenClr, 0xf24) + FldFunc(DecCs_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) +// parameter REG_CPU_INTGEN_CLR_1__WATCHDOG_TIMER_WIDTH = 1; +// parameter REG_CPU_INTGEN_CLR_1__WATCHDOG_TIMER_MSB = 30; +// parameter REG_CPU_INTGEN_CLR_1__WATCHDOG_TIMER_LSB = 30; + FldFunc(DecCs_RegCpuIntgenClr, WatchdogTimer, 30, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(DecCs_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(DecodeCpuregs, 0xF00, RegCpuIcacheMiss, 0x28, DecCs_RegCpuIcacheMiss, 0xf28) + FldFunc(DecCs_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(DecodeCpuregs, 0xF00, RegCpuIntgenMask, 0x2C, DecCs_RegCpuIntgenMask, 0xf2c) + FldFunc(DecCs_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) +// parameter REG_CPU_INTGEN_MASK_1__WATCHDOG_TIMER_WIDTH = 1; +// parameter REG_CPU_INTGEN_MASK_1__WATCHDOG_TIMER_MSB = 30; +// parameter REG_CPU_INTGEN_MASK_1__WATCHDOG_TIMER_LSB = 30; + FldFunc(DecCs_RegCpuIntgenMask, WatchdogTimer, 30, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(DecCs_RegCpuIntgenMask, Int0, 0, 1) + +RegFunc(DecodeCpuregs, 0xF00, RegInstBase, 0x30, DecCs_RegInstBase, 0xf0c) + FldFunc(DecCs_RegInstBase, Instbase, 10, 22) + +RegFunc(DecodeCpuregs, 0xF00, RegEndOfCode, 0x34, DecCs_RegEndOfCode, 0xf34) + FldFunc(DecCs_RegEndOfCode, Endofcode, 10, 22) + +RegFunc(DecodeCpuregs, 0xF00, RegGlobalIoBase, 0x38, DecCs_RegGlobalIoBase, 0xf38) + FldFunc(DecCs_RegGlobalIoBase, Globaliobase, 10, 22) + +// parameter REG_WATCHDOG_TMR_LIMIT = 32'h48; +// parameter REG_WATCHDOG_TMR_LIMIT__VALUE_WIDTH = 32; +// parameter REG_WATCHDOG_TMR_LIMIT__VALUE_MSB = 31; +// parameter REG_WATCHDOG_TMR_LIMIT__VALUE_LSB = 0; +RegFunc(DecodeCpuregs, 0xF00, RegWatchdogTmrLimit, 0x48, DecCs_RegWatchdogTmrLimit, 0xf48) + FldFunc(DecCs_RegWatchdogTmrLimit, Value, 0, 32) +// parameter REG_WATCHDOG_TMR = 32'h4C; +// parameter REG_WATCHDOG_TMR__VALUE_WIDTH = 32; +// parameter REG_WATCHDOG_TMR__VALUE_MSB = 31; +// parameter REG_WATCHDOG_TMR__VALUE_LSB = 0; +RegFunc(DecodeCpuregs, 0xF00, RegWatchdogTmr, 0x4C, DecCs_RegWatchdogTmr, 0xf4c) + FldFunc(DecCs_RegWatchdogTmr, Value, 0, 32) +RegFunc(DecodeCpuregs, 0xF00, RegSdramStatus, 0x50, DecCs_RegSdramStatus, 0xf50) + FldFunc(DecCs_RegSdramStatus, Iswrite, 1, 1) + FldFunc(DecCs_RegSdramStatus, Busy, 0, 1) + +RegAreaFunc(DecodeCpuregs2Base, 0xF80, 0xFFF) +RegFunc(DecodeCpuregs2, 0xF80, RegHst2cpuMbx, 0x0, DecC2_RegHst2cpuMbx, 0xf80) + FldFunc(DecC2_RegHst2cpuMbx, Value, 0, 32) +RegFunc(DecodeCpuregs2, 0xF80, RegCpu2hstMbx, 0x4, DecC2_RegCpu2hstMbx, 0xf84) + FldFunc(DecC2_RegCpu2hstMbx, Value, 0, 32) +RegFunc(DecodeCpuregs2, 0xF80, RegMbxStat, 0x8, DecC2_RegMbxStat, 0xf88) + FldFunc(DecC2_RegMbxStat, C2h, 1, 1) + FldFunc(DecC2_RegMbxStat, H2c, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, RegCpuIntEna, 0x10, DecC2_RegCpuIntEna, 0xf90) + FldFunc(DecC2_RegCpuIntEna, Mbx, 31, 1) + FldFunc(DecC2_RegCpuIntEna, Com7, 23, 1) + FldFunc(DecC2_RegCpuIntEna, Com6, 22, 1) + FldFunc(DecC2_RegCpuIntEna, Com5, 21, 1) + FldFunc(DecC2_RegCpuIntEna, Com4, 20, 1) + FldFunc(DecC2_RegCpuIntEna, Com3, 19, 1) + FldFunc(DecC2_RegCpuIntEna, Com2, 18, 1) + FldFunc(DecC2_RegCpuIntEna, Com1, 17, 1) + FldFunc(DecC2_RegCpuIntEna, Com0, 16, 1) + FldFunc(DecC2_RegCpuIntEna, Hw7, 15, 1) + FldFunc(DecC2_RegCpuIntEna, Hw6, 14, 1) + FldFunc(DecC2_RegCpuIntEna, Hw5, 13, 1) + FldFunc(DecC2_RegCpuIntEna, Hw4, 12, 1) + FldFunc(DecC2_RegCpuIntEna, Hw3, 11, 1) + FldFunc(DecC2_RegCpuIntEna, Hw2, 10, 1) + FldFunc(DecC2_RegCpuIntEna, Hw1, 9, 1) + FldFunc(DecC2_RegCpuIntEna, Hw0, 8, 1) + FldFunc(DecC2_RegCpuIntEna, Db7, 7, 1) + FldFunc(DecC2_RegCpuIntEna, Db6, 6, 1) + FldFunc(DecC2_RegCpuIntEna, Db5, 5, 1) + FldFunc(DecC2_RegCpuIntEna, Db4, 4, 1) + FldFunc(DecC2_RegCpuIntEna, Db3, 3, 1) + FldFunc(DecC2_RegCpuIntEna, Db2, 2, 1) + FldFunc(DecC2_RegCpuIntEna, Db1, 1, 1) + FldFunc(DecC2_RegCpuIntEna, Db0, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, StreamCpuIntEna, 0x10, DecC2_StreamCpuIntEna, 0xf90) + FldFunc(DecC2_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(DecC2_StreamCpuIntEna, Dec, 18, 1) + FldFunc(DecC2_StreamCpuIntEna, Aud, 17, 1) + FldFunc(DecC2_StreamCpuIntEna, M2m, 15, 1) + FldFunc(DecC2_StreamCpuIntEna, Pci, 14, 1) + FldFunc(DecC2_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(DecC2_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(DecC2_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(DecC2_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(DecC2_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(DecC2_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(DecC2_StreamCpuIntEna, Rb, 1, 1) + FldFunc(DecC2_StreamCpuIntEna, Sd, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, Dec0CpuIntEna, 0x10, DecC2_Dec0CpuIntEna, 0xf90) + FldFunc(DecC2_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(DecC2_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(DecC2_Dec0CpuIntEna, Si, 8, 1) + FldFunc(DecC2_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(DecC2_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, Dec1CpuIntEna, 0x10, DecC2_Dec1CpuIntEna, 0xf90) + FldFunc(DecC2_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(DecC2_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(DecC2_Dec1CpuIntEna, Si, 8, 1) + FldFunc(DecC2_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(DecC2_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, RegCpuIntStat, 0x14, DecC2_RegCpuIntStat, 0xf94) + FldFunc(DecC2_RegCpuIntStat, Mbx, 31, 1) + FldFunc(DecC2_RegCpuIntStat, Com7, 23, 1) + FldFunc(DecC2_RegCpuIntStat, Com6, 22, 1) + FldFunc(DecC2_RegCpuIntStat, Com5, 21, 1) + FldFunc(DecC2_RegCpuIntStat, Com4, 20, 1) + FldFunc(DecC2_RegCpuIntStat, Com3, 19, 1) + FldFunc(DecC2_RegCpuIntStat, Com2, 18, 1) + FldFunc(DecC2_RegCpuIntStat, Com1, 17, 1) + FldFunc(DecC2_RegCpuIntStat, Com0, 16, 1) + FldFunc(DecC2_RegCpuIntStat, Hw7, 15, 1) + FldFunc(DecC2_RegCpuIntStat, Hw6, 14, 1) + FldFunc(DecC2_RegCpuIntStat, Hw5, 13, 1) + FldFunc(DecC2_RegCpuIntStat, Hw4, 12, 1) + FldFunc(DecC2_RegCpuIntStat, Hw3, 11, 1) + FldFunc(DecC2_RegCpuIntStat, Hw2, 10, 1) + FldFunc(DecC2_RegCpuIntStat, Hw1, 9, 1) + FldFunc(DecC2_RegCpuIntStat, Hw0, 8, 1) + FldFunc(DecC2_RegCpuIntStat, Db7, 7, 1) + FldFunc(DecC2_RegCpuIntStat, Db6, 6, 1) + FldFunc(DecC2_RegCpuIntStat, Db5, 5, 1) + FldFunc(DecC2_RegCpuIntStat, Db4, 4, 1) + FldFunc(DecC2_RegCpuIntStat, Db3, 3, 1) + FldFunc(DecC2_RegCpuIntStat, Db2, 2, 1) + FldFunc(DecC2_RegCpuIntStat, Db1, 1, 1) + FldFunc(DecC2_RegCpuIntStat, Db0, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, StreamCpuIntStat, 0x14, DecC2_StreamCpuIntStat, 0xf94) + FldFunc(DecC2_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(DecC2_StreamCpuIntStat, Dec, 18, 1) + FldFunc(DecC2_StreamCpuIntStat, Aud, 17, 1) + FldFunc(DecC2_StreamCpuIntStat, M2m, 15, 1) + FldFunc(DecC2_StreamCpuIntStat, Pci, 14, 1) + FldFunc(DecC2_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(DecC2_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(DecC2_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(DecC2_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(DecC2_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(DecC2_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(DecC2_StreamCpuIntStat, Rb, 1, 1) + FldFunc(DecC2_StreamCpuIntStat, Sd, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, Dec0CpuIntStat, 0x14, DecC2_Dec0CpuIntStat, 0xf94) + FldFunc(DecC2_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(DecC2_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(DecC2_Dec0CpuIntStat, Si, 8, 1) + FldFunc(DecC2_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(DecC2_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, Dec1CpuIntStat, 0x14, DecC2_Dec1CpuIntStat, 0xf94) + FldFunc(DecC2_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(DecC2_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(DecC2_Dec1CpuIntStat, Si, 8, 1) + FldFunc(DecC2_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(DecC2_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, RegHst2cpuStat, 0x18, DecC2_RegHst2cpuStat, 0xf98) + FldFunc(DecC2_RegHst2cpuStat, Value, 0, 32) +RegFunc(DecodeCpuregs2, 0xF80, RegCpu2hstStat, 0x1C, DecC2_RegCpu2hstStat, 0xf9c) + FldFunc(DecC2_RegCpu2hstStat, Value, 0, 32) +RegFunc(DecodeCpuregs2, 0xF80, RegCpuIntgenSet, 0x20, DecC2_RegCpuIntgenSet, 0xfa0) + FldFunc(DecC2_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(DecC2_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, RegCpuIntgenClr, 0x24, DecC2_RegCpuIntgenClr, 0xfa4) + FldFunc(DecC2_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(DecC2_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(DecodeCpuregs2, 0xF80, RegCpuIcacheMiss, 0x28, DecC2_RegCpuIcacheMiss, 0xfa8) + FldFunc(DecC2_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(DecodeCpuregs2, 0xF80, RegCpuIntgenMask, 0x2C, DecC2_RegCpuIntgenMask, 0xfac) + FldFunc(DecC2_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(DecC2_RegCpuIntgenMask, Int0, 0, 1) + +RegFunc(DecodeCpuregs2, 0xF80, RegInstBase, 0x30, DecC2_RegInstBase, 0xf8c) + FldFunc(DecC2_RegInstBase, Instbase, 10, 22) +RegFunc(DecodeCpuregs2, 0xF80, RegEndOfCode, 0x34, DecC2_RegEndOfCode, 0xfb4) + FldFunc(DecC2_RegEndOfCode, Endofcode, 10, 22) +RegFunc(DecodeCpuregs2, 0xF80, RegGlobalIoBase, 0x38, DecC2_RegGlobalIoBase, 0xfb8) + FldFunc(DecC2_RegGlobalIoBase, Globaliobase, 10, 22) + +// parameter REG_DEBUG_TRACE_FIFO_WR = 32'hBC; +// parameter REG_DEBUG_TRACE_FIFO_WR__VALUE_WIDTH = 8; +// parameter REG_DEBUG_TRACE_FIFO_WR__VALUE_MSB = 7; +// parameter REG_DEBUG_TRACE_FIFO_WR__VALUE_LSB = 0; +RegFunc(DecodeCpuregs2, 0xF80, RegDebugTraceFifoWr, 0x3C, DecC2_RegDebugTraceFifoWr, 0xfbc) + FldFunc(DecC2_RegDebugTraceFifoWr, Value, 0, 8) +// parameter REG_DEBUG_TRACE_FIFO_RD = 32'hC0; +// parameter REG_DEBUG_TRACE_FIFO_RD__VALUE_WIDTH = 8; +// parameter REG_DEBUG_TRACE_FIFO_RD__VALUE_MSB = 7; +// parameter REG_DEBUG_TRACE_FIFO_RD__VALUE_LSB = 0; +RegFunc(DecodeCpuregs2, 0xF80, RegDebugTraceFifoRd, 0x40, DecC2_RegDebugTraceFifoRd, 0xfc0) + FldFunc(DecC2_RegDebugTraceFifoRd, Value, 0, 8) +// parameter REG_DEBUG_TRACE_FIFO_CTL = 32'hC4; +// parameter REG_DEBUG_TRACE_FIFO_CTL__FREEZE_WIDTH = 1; +// parameter REG_DEBUG_TRACE_FIFO_CTL__FREEZE_MSB = 2; +// parameter REG_DEBUG_TRACE_FIFO_CTL__FREEZE_LSB = 2; +// parameter REG_DEBUG_TRACE_FIFO_CTL__START_READ_WIDTH = 1; +// parameter REG_DEBUG_TRACE_FIFO_CTL__START_READ_MSB = 1; +// parameter REG_DEBUG_TRACE_FIFO_CTL__START_READ_LSB = 1; +// parameter REG_DEBUG_TRACE_FIFO_CTL__CLEAR_WIDTH = 1; +// parameter REG_DEBUG_TRACE_FIFO_CTL__CLEAR_MSB = 0; +// parameter REG_DEBUG_TRACE_FIFO_CTL__CLEAR_LSB +RegFunc(DecodeCpuregs2, 0xF80, RegDebugTraceFifoCtl, 0x44, DecC2_RegDebugTraceFifoCtl, 0xfc4) + FldFunc(DecC2_RegDebugTraceFifoCtl, Freeze, 2, 1) + FldFunc(DecC2_RegDebugTraceFifoCtl, StartRead, 1, 1) + FldFunc(DecC2_RegDebugTraceFifoCtl, Clear, 0, 1) +// parameter REG_WATCHDOG_TMR_LIMIT_1 = 32'h48; +// parameter REG_WATCHDOG_TMR_LIMIT_1__VALUE_WIDTH = 32; +// parameter REG_WATCHDOG_TMR_LIMIT_1__VALUE_MSB = 31; +// parameter REG_WATCHDOG_TMR_LIMIT_1__VALUE_LSB = 0; +RegFunc(DecodeCpuregs2, 0xF80, RegWatchdogTmrLimit, 0x48, DecC2_RegWatchdogTmrLimit, 0xfc8) + FldFunc(DecC2_RegWatchdogTmrLimit, Value, 0, 32) +// parameter REG_WATCHDOG_TMR = 32'h4C; +// parameter REG_WATCHDOG_TMR__VALUE_WIDTH = 32; +// parameter REG_WATCHDOG_TMR__VALUE_MSB = 31; +// parameter REG_WATCHDOG_TMR__VALUE_LSB = 0; +RegFunc(DecodeCpuregs2, 0xF80, RegWatchdogTmr, 0x4C, DecC2_RegWatchdogTmr, 0xfcc) + FldFunc(DecC2_RegWatchdogTmr, Value, 0, 32) +RegFunc(DecodeCpuregs2, 0xF80, RegSdramStatus, 0x50, DecC2_RegSdramStatus, 0xfd0) + FldFunc(DecC2_RegSdramStatus, Iswrite, 1, 1) + FldFunc(DecC2_RegSdramStatus, Busy, 0, 1) + +/* +RegAreaFunc(DecodeCpudmaBase, 0x1800, 0x18FF) +RegFunc(DecodeCpudma, 0x1800, RegDma0SdAddr, 0x0, DecCa_RegDma0SdAddr, 0x1800) + FldFunc(DecCa_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma, 0x1800, RegDma0LclAddr, 0x4, DecCa_RegDma0LclAddr, 0x1804) + FldFunc(DecCa_RegDma0LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma, 0x1800, RegDma0Len, 0x8, DecCa_RegDma0Len, 0x1808) + FldFunc(DecCa_RegDma0Len, Length, 2, 9) +RegFunc(DecodeCpudma, 0x1800, RegDma1SdAddr, 0x10, DecCa_RegDma1SdAddr, 0x1810) + FldFunc(DecCa_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma, 0x1800, RegDma1LclAddr, 0x14, DecCa_RegDma1LclAddr, 0x1814) + FldFunc(DecCa_RegDma1LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma, 0x1800, RegDma1Len, 0x18, DecCa_RegDma1Len, 0x1818) + FldFunc(DecCa_RegDma1Len, Length, 2, 9) +RegFunc(DecodeCpudma, 0x1800, RegDma2SdAddr, 0x20, DecCa_RegDma2SdAddr, 0x1820) + FldFunc(DecCa_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma, 0x1800, RegDma2LclAddr, 0x24, DecCa_RegDma2LclAddr, 0x1824) + FldFunc(DecCa_RegDma2LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma, 0x1800, RegDma2Len, 0x28, DecCa_RegDma2Len, 0x1828) + FldFunc(DecCa_RegDma2Len, Length, 2, 9) +RegFunc(DecodeCpudma, 0x1800, RegDma3SdAddr, 0x30, DecCa_RegDma3SdAddr, 0x1830) + FldFunc(DecCa_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma, 0x1800, RegDma3LclAddr, 0x34, DecCa_RegDma3LclAddr, 0x1834) + FldFunc(DecCa_RegDma3LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma, 0x1800, RegDma3Len, 0x38, DecCa_RegDma3Len, 0x1838) + FldFunc(DecCa_RegDma3Len, Length, 2, 9) +RegFunc(DecodeCpudma, 0x1800, RegDmaStatus, 0x40, DecCa_RegDmaStatus, 0x1840) + FldFunc(DecCa_RegDmaStatus, Act3, 3, 1) + FldFunc(DecCa_RegDmaStatus, Act2, 2, 1) + FldFunc(DecCa_RegDmaStatus, Act1, 1, 1) + FldFunc(DecCa_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(DecodeDmamemBase, 0x1A00, 0x21FF) +RegFunc(DecodeDmamem, 0x1A00, DmaMem, 0x0, DecDm_DmaMem, 0x1a00) + FldFunc(DecDm_DmaMem, Data, 0, 32) + */ + +RegAreaFunc(RegCabac2bins2Base, 0x2400, 0x27FF) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdContextId, 0x178, RegC2_RegCabac2binsRdContextId, 0x2578) + FldFunc(RegC2_RegCabac2binsRdContextId, Id, 0, 6) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdBuffAddr, 0x188, RegC2_RegCabac2binsRdBuffAddr, 0x2588) + FldFunc(RegC2_RegCabac2binsRdBuffAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdBuffCtl, 0x18C, RegC2_RegCabac2binsRdBuffCtl, 0x258c) + FldFunc(RegC2_RegCabac2binsRdBuffCtl, AtMark, 4, 1) + FldFunc(RegC2_RegCabac2binsRdBuffCtl, NotRdy, 3, 1) + FldFunc(RegC2_RegCabac2binsRdBuffCtl, WrapEn, 2, 1) + FldFunc(RegC2_RegCabac2binsRdBuffCtl, Init, 1, 1) + FldFunc(RegC2_RegCabac2binsRdBuffCtl, BuffEn, 0, 1) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdBuffStartAddr, 0x194, RegC2_RegCabac2binsRdBuffStartAddr, 0x2594) + FldFunc(RegC2_RegCabac2binsRdBuffStartAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdBuffEndAddr, 0x198, RegC2_RegCabac2binsRdBuffEndAddr, 0x2598) + FldFunc(RegC2_RegCabac2binsRdBuffEndAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdBuffMarkAddr, 0x17C, RegC2_RegCabac2binsRdBuffMarkAddr, 0x257c) + FldFunc(RegC2_RegCabac2binsRdBuffMarkAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsRdBuffStallCnt, 0x19C, RegC2_RegCabac2binsRdBuffStallCnt, 0x259c) + FldFunc(RegC2_RegCabac2binsRdBuffStallCnt, Count, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrBuffStartAddr, 0x1A8, RegC2_RegCabac2binsWrBuffStartAddr, 0x25a8) + FldFunc(RegC2_RegCabac2binsWrBuffStartAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrBuffCtl, 0x1AC, RegC2_RegCabac2binsWrBuffCtl, 0x25ac) + FldFunc(RegC2_RegCabac2binsWrBuffCtl, BuffClose, 2, 1) + FldFunc(RegC2_RegCabac2binsWrBuffCtl, Init, 1, 1) + FldFunc(RegC2_RegCabac2binsWrBuffCtl, BuffEn, 0, 1) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrBuffEndAddr, 0x1B0, RegC2_RegCabac2binsWrBuffEndAddr, 0x25b0) + FldFunc(RegC2_RegCabac2binsWrBuffEndAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrBuffMarkAddr, 0x1B4, RegC2_RegCabac2binsWrBuffMarkAddr, 0x25b4) + FldFunc(RegC2_RegCabac2binsWrBuffMarkAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrBuffStallCnt, 0x1B8, RegC2_RegCabac2binsWrBuffStallCnt, 0x25b8) + FldFunc(RegC2_RegCabac2binsWrBuffStallCnt, Count, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrBuffAddr, 0x1BC, RegC2_RegCabac2binsWrBuffAddr, 0x25bc) + FldFunc(RegC2_RegCabac2binsWrBuffAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsWrContextId, 0x1C0, RegC2_RegCabac2binsWrContextId, 0x25c0) + FldFunc(RegC2_RegCabac2binsWrContextId, Id, 0, 6) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsNotIdleCycles, 0x220, RegC2_RegCabac2binsNotIdleCycles, 0x2620) + FldFunc(RegC2_RegCabac2binsNotIdleCycles, CycleCount, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsState0, 0x230, RegC2_RegCabac2binsState0, 0x2630) + FldFunc(RegC2_RegCabac2binsState0, State, 0, 11) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsState1, 0x234, RegC2_RegCabac2binsState1, 0x2634) + FldFunc(RegC2_RegCabac2binsState1, State, 0, 11) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsUpstripembBaseAddr, 0x300, RegC2_RegCabac2binsUpstripembBaseAddr, 0x2700) + FldFunc(RegC2_RegCabac2binsUpstripembBaseAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsCommandBufferAddr, 0x310, RegC2_RegCabac2binsCommandBufferAddr, 0x2710) + FldFunc(RegC2_RegCabac2binsCommandBufferAddr, Addr, 0, 32) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsCommandBufferCount, 0x314, RegC2_RegCabac2binsCommandBufferCount, 0x2714) + FldFunc(RegC2_RegCabac2binsCommandBufferCount, CommandBufferCount, 0, 11) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsCommandBufferLogSize, 0x318, RegC2_RegCabac2binsCommandBufferLogSize, 0x2718) + FldFunc(RegC2_RegCabac2binsCommandBufferLogSize, CommandBufferSize, 0, 5) +RegFunc(RegCabac2bins2, 0x2400, RegCabac2binsCtl, 0x32C, RegC2_RegCabac2binsCtl, 0x272c) + FldFunc(RegC2_RegCabac2binsCtl, Int, 11, 1) + FldFunc(RegC2_RegCabac2binsCtl, Busy, 10, 1) + FldFunc(RegC2_RegCabac2binsCtl, Wrnr, 9, 1) + FldFunc(RegC2_RegCabac2binsCtl, Rdnr, 8, 1) + FldFunc(RegC2_RegCabac2binsCtl, Wrmk, 7, 1) + FldFunc(RegC2_RegCabac2binsCtl, Rdmk, 6, 1) + FldFunc(RegC2_RegCabac2binsCtl, Sdpre, 5, 1) + FldFunc(RegC2_RegCabac2binsCtl, Sdq, 4, 1) + FldFunc(RegC2_RegCabac2binsCtl, Sdwr, 3, 1) + FldFunc(RegC2_RegCabac2binsCtl, Sdact, 2, 1) + FldFunc(RegC2_RegCabac2binsCtl, Sdreq, 1, 1) + FldFunc(RegC2_RegCabac2binsCtl, Reset, 0, 1) + +RegAreaFunc(DecodeWptblBase, 0x3000, 0x31FF) +RegFunc(DecodeWptbl, 0x3000, DecodeWptbl, 0x0, DecWl_DecodeWptbl, 0x3000) + +RegAreaFunc(DecodeSintOloopBase, 0xCC00, 0xCCFF) +RegFunc(DecodeSintOloop, 0xCC00, DecSintDmaAddr, 0x0, DecSOp_DecSintDmaAddr, 0xcc00) + FldFunc(DecSOp_DecSintDmaAddr, Addr, 5, 27) +RegFunc(DecodeSintOloop, 0xCC00, DecSintDmaLen, 0x4, DecSOp_DecSintDmaLen, 0xcc04) + FldFunc(DecSOp_DecSintDmaLen, Length, 5, 27) +RegFunc(DecodeSintOloop, 0xCC00, DecSintDmaBase, 0x8, DecSOp_DecSintDmaBase, 0xcc08) + FldFunc(DecSOp_DecSintDmaBase, Base, 6, 26) +RegFunc(DecodeSintOloop, 0xCC00, DecSintDmaEnd, 0xC, DecSOp_DecSintDmaEnd, 0xcc0c) + FldFunc(DecSOp_DecSintDmaEnd, End, 6, 26) +RegFunc(DecodeSintOloop, 0xCC00, DecSintStrmPos, 0x10, DecSOp_DecSintStrmPos, 0xcc10) + FldFunc(DecSOp_DecSintStrmPos, BitPos, 0, 32) +RegFunc(DecodeSintOloop, 0xCC00, DecSintStrmStat, 0x14, DecSOp_DecSintStrmStat, 0xcc14) + FldFunc(DecSOp_DecSintStrmStat, Rst, 16, 1) + FldFunc(DecSOp_DecSintStrmStat, Derr, 9, 1) + FldFunc(DecSOp_DecSintStrmStat, Serr, 8, 1) + FldFunc(DecSOp_DecSintStrmStat, Ccac, 6, 1) + FldFunc(DecSOp_DecSintStrmStat, Vcac, 5, 1) + FldFunc(DecSOp_DecSintStrmStat, Vact, 4, 1) + FldFunc(DecSOp_DecSintStrmStat, Dact, 3, 1) + FldFunc(DecSOp_DecSintStrmStat, Sact, 2, 1) + FldFunc(DecSOp_DecSintStrmStat, Cact, 1, 1) + FldFunc(DecSOp_DecSintStrmStat, Sval, 0, 1) +RegFunc(DecodeSintOloop, 0xCC00, DecSintIena, 0x18, DecSOp_DecSintIena, 0xcc18) + FldFunc(DecSOp_DecSintIena, Derr, 9, 1) + FldFunc(DecSOp_DecSintIena, Serr, 8, 1) +RegFunc(DecodeSintOloop, 0xCC00, DecSintStrmBits, 0x1C, DecSOp_DecSintStrmBits, 0xcc1c) + FldFunc(DecSOp_DecSintStrmBits, StreamBits, 0, 32) +RegFunc(DecodeSintOloop, 0xCC00, DecSintGetSymb, 0x20, DecSOp_DecSintGetSymb, 0xcc20) + FldFunc(DecSOp_DecSintGetSymb, Type, 12, 4) + FldFunc(DecSOp_DecSintGetSymb, Subtype, 8, 4) + FldFunc(DecSOp_DecSintGetSymb, N, 0, 8) + +RegAreaFunc(DecodeSdBase, 0x40800, 0x40FFF) +RegFunc(DecodeSd, 0x40800, RegSdParam, 0x4, DecSd_RegSdParam, 0x40804) + FldFunc(DecSd_RegSdParam, BstLow, 31, 1) + FldFunc(DecSd_RegSdParam, BstVidb, 30, 1) + FldFunc(DecSd_RegSdParam, BstVida, 29, 1) + FldFunc(DecSd_RegSdParam, BstMoCmp, 28, 1) + FldFunc(DecSd_RegSdParam, Rdwr, 26, 2) + FldFunc(DecSd_RegSdParam, ClkePin, 25, 1) + FldFunc(DecSd_RegSdParam, ColmBits, 23, 2) + FldFunc(DecSd_RegSdParam, Rfc, 19, 4) + FldFunc(DecSd_RegSdParam, Wtr, 16, 3) + FldFunc(DecSd_RegSdParam, Wr, 12, 3) + FldFunc(DecSd_RegSdParam, Rrd, 10, 2) + FldFunc(DecSd_RegSdParam, Rp, 7, 3) + FldFunc(DecSd_RegSdParam, Rcd, 4, 3) + FldFunc(DecSd_RegSdParam, Ras, 0, 4) +RegFunc(DecodeSd, 0x40800, RegSdRefresh, 0x8, DecSd_RegSdRefresh, 0x40808) + FldFunc(DecSd_RegSdRefresh, En, 12, 1) + FldFunc(DecSd_RegSdRefresh, Period, 0, 12) +RegFunc(DecodeSd, 0x40800, RegSdSemaphore0, 0xC, DecSd_RegSdSemaphore0, 0x4080c) + FldFunc(DecSd_RegSdSemaphore0, Tas, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdSemaphore1, 0x10, DecSd_RegSdSemaphore1, 0x40810) + FldFunc(DecSd_RegSdSemaphore1, Tas, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdSemaphore2, 0x14, DecSd_RegSdSemaphore2, 0x40814) + FldFunc(DecSd_RegSdSemaphore2, Tas, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdSemaphore3, 0x18, DecSd_RegSdSemaphore3, 0x40818) + FldFunc(DecSd_RegSdSemaphore3, Tas, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdScratch, 0x1C, DecSd_RegSdScratch, 0x4081c) + FldFunc(DecSd_RegSdScratch, Data, 0, 32) +RegFunc(DecodeSd, 0x40800, RegSdBoostPrio, 0x20, DecSd_RegSdBoostPrio, 0x40820) + FldFunc(DecSd_RegSdBoostPrio, Mask, 0, 32) +RegFunc(DecodeSd, 0x40800, RegSdDelayAck, 0x30, DecSd_RegSdDelayAck, 0x40830) + FldFunc(DecSd_RegSdDelayAck, Delaylo, 16, 3) + FldFunc(DecSd_RegSdDelayAck, Delayhi, 12, 3) + FldFunc(DecSd_RegSdDelayAck, Delayoff, 8, 4) + FldFunc(DecSd_RegSdDelayAck, Delayon, 4, 4) + FldFunc(DecSd_RegSdDelayAck, Ena, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdDelayRd1, 0x34, DecSd_RegSdDelayRd1, 0x40834) + FldFunc(DecSd_RegSdDelayRd1, Delaylo, 16, 3) + FldFunc(DecSd_RegSdDelayRd1, Delayhi, 12, 3) + FldFunc(DecSd_RegSdDelayRd1, Delayoff, 8, 4) + FldFunc(DecSd_RegSdDelayRd1, Delayon, 4, 4) + FldFunc(DecSd_RegSdDelayRd1, Ena, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdDelayRd2, 0x38, DecSd_RegSdDelayRd2, 0x40838) + FldFunc(DecSd_RegSdDelayRd2, Delaylo, 16, 3) + FldFunc(DecSd_RegSdDelayRd2, Delayhi, 12, 3) + FldFunc(DecSd_RegSdDelayRd2, Delayoff, 8, 4) + FldFunc(DecSd_RegSdDelayRd2, Delayon, 4, 4) + FldFunc(DecSd_RegSdDelayRd2, Ena, 0, 1) +RegFunc(DecodeSd, 0x40800, RegSdRefCmd, 0x90, DecSd_RegSdRefCmd, 0x40890) +RegFunc(DecodeSd, 0x40800, RegSdLdModeCmd, 0xa0, DecSd_RegSdLdModeCmd, 0x408a0) +RegFunc(DecodeSd, 0x40800, RegSdLdEmodeCmd, 0xA4, DecSd_RegSdLdEmodeCmd, 0x408a4) +RegFunc(DecodeSd, 0x40800, RegSdPrechCmd, 0xb0, DecSd_RegSdPrechCmd, 0x408b0) +RegFunc(DecodeSd, 0x40800, RegSdPictBaseNew, 0x400, DecSd_RegSdPictBaseNew, 0x40c00) + FldFunc(DecSd_RegSdPictBaseNew, Addr, 0, 20) +RegFunc(DecodeSd, 0x40800, RegSdStripeNew, 0x100, DecSd_RegSdStripeNew, 0x40900) + FldFunc(DecSd_RegSdStripeNew, Height, 2, 11) + FldFunc(DecSd_RegSdStripeNew, Width, 0, 2) + +RegAreaFunc(DecodeDqsCtlBase, 0x40700, 0x407FF) +RegFunc(DecodeDqsCtl, 0x40700, RegSdDqsCtl, 0x0, DecDCl_RegSdDqsCtl, 0x40700) + FldFunc(DecDCl_RegSdDqsCtl, ClIs2pt5, 26, 1) + FldFunc(DecDCl_RegSdDqsCtl, SampleEn, 25, 1) + FldFunc(DecDCl_RegSdDqsCtl, DqsDelayOverride, 24, 1) + FldFunc(DecDCl_RegSdDqsCtl, Mhz, 20, 4) + FldFunc(DecDCl_RegSdDqsCtl, PulseWidth, 16, 4) + FldFunc(DecDCl_RegSdDqsCtl, Dqs3Delay, 12, 4) + FldFunc(DecDCl_RegSdDqsCtl, Dqs2Delay, 8, 4) + FldFunc(DecDCl_RegSdDqsCtl, Dqs1Delay, 4, 4) + FldFunc(DecDCl_RegSdDqsCtl, Dqs0Delay, 0, 4) +RegFunc(DecodeDqsCtl, 0x40700, RegSdDdrDriverCtl , 0x4, DecDCl_RegSdDdrDriverCtl , 0x40704) + FldFunc(DecDCl_RegSdDdrDriverCtl , Class2Ctl, 12, 1) + FldFunc(DecDCl_RegSdDdrDriverCtl , SCtl, 10, 2) + FldFunc(DecDCl_RegSdDdrDriverCtl , DCtl, 8, 2) + FldFunc(DecDCl_RegSdDdrDriverCtl , Class2Dq, 4, 1) + FldFunc(DecDCl_RegSdDdrDriverCtl , SDq, 2, 2) + FldFunc(DecDCl_RegSdDdrDriverCtl , DDq, 0, 2) + +RegAreaFunc(DecodeIndSdramRegsBase, 0x41000, 0x4107F) +RegFunc(DecodeIndSdramRegs, 0x41000, RegSdramInc, 0x0, DecISRs_RegSdramInc, 0x41000) + FldFunc(DecISRs_RegSdramInc, Inc, 0, 1) +RegFunc(DecodeIndSdramRegs, 0x41000, RegSdramAddr, 0x4, DecISRs_RegSdramAddr, 0x41004) + FldFunc(DecISRs_RegSdramAddr, Addr, 0, 32) +RegFunc(DecodeIndSdramRegs, 0x41000, RegSdramData, 0x8, DecISRs_RegSdramData, 0x41008) + FldFunc(DecISRs_RegSdramData, Data, 0, 32) +RegFunc(DecodeIndSdramRegs, 0x41000, RegCpuDbg, 0x10, DecISRs_RegCpuDbg, 0x41010) + FldFunc(DecISRs_RegCpuDbg, Hst, 0, 1) + + //parameter REG_SDRAM_STAT = 32'h14; + // parameter REG_SDRAM_STAT__ISWRITE_WIDTH = 1; + // parameter REG_SDRAM_STAT__ISWRITE_MSB = 1; + // parameter REG_SDRAM_STAT__ISWRITE_LSB = 1; + // parameter REG_SDRAM_STAT__BUSY_WIDTH = 1; + // parameter REG_SDRAM_STAT__BUSY_MSB = 0; + // parameter REG_SDRAM_STAT__BUSY_LSB = 0; + //RegFunc(DecodeIndSdramRegs, 0x41000, RegSdramStat, 0x14, DecISRs_RegSdramStat, 0x41014) + //FldFunc(DecISRs_RegSdramStat, Iswrite, 1, 1) + //FldFunc(DecISRs_RegSdramStat, Busy, 0, 1) + +RegAreaFunc(DecodeCpucoreBase, 0x44000, 0x44FFF) +RegFunc(DecodeCpucore, 0x44000, CpucoreReg, 0x0, DecCe_CpucoreReg, 0x44000) + FldFunc(DecCe_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(DecodeCpuauxBase, 0x45000, 0x45FFF) +RegFunc(DecodeCpuaux, 0x45000, CpuauxReg, 0x0, DecCx_CpuauxReg, 0x45000) + FldFunc(DecCx_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(DecodeCpuimemBase, 0x46000, 0x47FFF) +RegFunc(DecodeCpuimem, 0x46000, CpuimemReg, 0x0, DecCm_CpuimemReg, 0x46000) + FldFunc(DecCm_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(DecodeCpudmemBase, 0x48000, 0x4FFFF) +RegFunc(DecodeCpudmem, 0x48000, CpudmemReg, 0x0, DecCm_CpudmemReg, 0x48000) + FldFunc(DecCm_CpudmemReg, Addr, 0, 32) + +RegAreaFunc(DecodeIndSdramRegs2Base, 0x51000, 0x5107F) +RegFunc(DecodeIndSdramRegs2, 0x51000, RegSdramInc, 0x0, DecISR2_RegSdramInc, 0x51000) + FldFunc(DecISR2_RegSdramInc, Inc, 0, 1) +RegFunc(DecodeIndSdramRegs2, 0x51000, RegSdramAddr, 0x4, DecISR2_RegSdramAddr, 0x51004) + FldFunc(DecISR2_RegSdramAddr, Addr, 0, 32) +RegFunc(DecodeIndSdramRegs2, 0x51000, RegSdramData, 0x8, DecISR2_RegSdramData, 0x51008) + FldFunc(DecISR2_RegSdramData, Data, 0, 32) +RegFunc(DecodeIndSdramRegs2, 0x51000, RegCpuDbg, 0x10, DecISR2_RegCpuDbg, 0x51010) + FldFunc(DecISR2_RegCpuDbg, Hst, 0, 1) + + //parameter REG_SDRAM_STAT_1 = 32'h14; + // parameter REG_SDRAM_STAT_1__ISWRITE_WIDTH = 1; + // parameter REG_SDRAM_STAT_1__ISWRITE_MSB = 1; + // parameter REG_SDRAM_STAT_1__ISWRITE_LSB = 1; + // parameter REG_SDRAM_STAT_1__BUSY_WIDTH = 1; + // parameter REG_SDRAM_STAT_1__BUSY_MSB = 0; + // parameter REG_SDRAM_STAT_1__BUSY_LSB = 0; + //RegFunc(DecodeIndSdramRegs2, 0x51000, RegSdramStat, 0x14, DecISR2_RegSdramStat, 0x51014) + //FldFunc(DecISR2_RegSdramStat, Iswrite, 1, 1) + //FldFunc(DecISR2_RegSdramStat, Busy, 0, 1) + +RegAreaFunc(DecodeCpudma2Base, 0x51800, 0x518FF) +RegFunc(DecodeCpudma2, 0x51800, RegDma0SdAddr, 0x0, DecC2_RegDma0SdAddr, 0x51800) + FldFunc(DecC2_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma2, 0x51800, RegDma0LclAddr, 0x4, DecC2_RegDma0LclAddr, 0x51804) + FldFunc(DecC2_RegDma0LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma2, 0x51800, RegDma0Len, 0x8, DecC2_RegDma0Len, 0x51808) + FldFunc(DecC2_RegDma0Len, Length, 2, 9) +RegFunc(DecodeCpudma2, 0x51800, RegDma1SdAddr, 0x10, DecC2_RegDma1SdAddr, 0x51810) + FldFunc(DecC2_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma2, 0x51800, RegDma1LclAddr, 0x14, DecC2_RegDma1LclAddr, 0x51814) + FldFunc(DecC2_RegDma1LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma2, 0x51800, RegDma1Len, 0x18, DecC2_RegDma1Len, 0x51818) + FldFunc(DecC2_RegDma1Len, Length, 2, 9) +RegFunc(DecodeCpudma2, 0x51800, RegDma2SdAddr, 0x20, DecC2_RegDma2SdAddr, 0x51820) + FldFunc(DecC2_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma2, 0x51800, RegDma2LclAddr, 0x24, DecC2_RegDma2LclAddr, 0x51824) + FldFunc(DecC2_RegDma2LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma2, 0x51800, RegDma2Len, 0x28, DecC2_RegDma2Len, 0x51828) + FldFunc(DecC2_RegDma2Len, Length, 2, 9) +RegFunc(DecodeCpudma2, 0x51800, RegDma3SdAddr, 0x30, DecC2_RegDma3SdAddr, 0x51830) + FldFunc(DecC2_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(DecodeCpudma2, 0x51800, RegDma3LclAddr, 0x34, DecC2_RegDma3LclAddr, 0x51834) + FldFunc(DecC2_RegDma3LclAddr, Addr, 2, 8) +RegFunc(DecodeCpudma2, 0x51800, RegDma3Len, 0x38, DecC2_RegDma3Len, 0x51838) + FldFunc(DecC2_RegDma3Len, Length, 2, 9) +RegFunc(DecodeCpudma2, 0x51800, RegDmaStatus, 0x40, DecC2_RegDmaStatus, 0x51840) + FldFunc(DecC2_RegDmaStatus, Act3, 3, 1) + FldFunc(DecC2_RegDmaStatus, Act2, 2, 1) + FldFunc(DecC2_RegDmaStatus, Act1, 1, 1) + FldFunc(DecC2_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(DecodeDmamem2Base, 0x51A00, 0x521FF) +RegFunc(DecodeDmamem2, 0x51A00, DmaMem, 0x0, DecD2_DmaMem, 0x51a00) + FldFunc(DecD2_DmaMem, Data, 0, 32) + +RegAreaFunc(DecodeCpucore2Base, 0x54000, 0x54FFF) +RegFunc(DecodeCpucore2, 0x54000, CpucoreReg, 0x0, DecC2_CpucoreReg, 0x54000) + FldFunc(DecC2_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(DecodeCpuaux2Base, 0x55000, 0x55FFF) +RegFunc(DecodeCpuaux2, 0x55000, CpuauxReg, 0x0, DecC2_CpuauxReg, 0x55000) + FldFunc(DecC2_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(DecodeCpuimem2Base, 0x56000, 0x57FFF) +RegFunc(DecodeCpuimem2, 0x56000, CpuimemReg, 0x0, DecC2_CpuimemReg, 0x56000) + FldFunc(DecC2_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(DecodeCpudmem2Base, 0x58000, 0x5FFFF) +RegFunc(DecodeCpudmem2, 0x58000, CpudmemReg, 0x0, DecC2_CpudmemReg, 0x58000) + FldFunc(DecC2_CpudmemReg, Addr, 0, 32) + +#endif + + +//****************************************************************************** +// +// Stream Processor Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_STREAM_PROCESSOR + +RegAreaFunc(StreamRbnodeRegsBase, 0x100000, 0x10007F) +RegFunc(StreamRbnodeRegs, 0x100000, RbConfig , 0x0, StrRRs_RbConfig , 0x100000) + FldFunc(StrRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(StrRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(StreamRbnodeRegs, 0x100000, RbStickyError, 0x4, StrRRs_RbStickyError, 0x100004) + FldFunc(StrRRs_RbStickyError, Node, 1, 1) + FldFunc(StrRRs_RbStickyError, Tgt, 0, 1) +RegFunc(StreamRbnodeRegs, 0x100000, RbCurrentError, 0x8, StrRRs_RbCurrentError, 0x100008) + FldFunc(StrRRs_RbCurrentError, Node, 1, 1) + FldFunc(StrRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(StreamRbnodeRegs, 0x100000, RbReadData, 0xC, StrRRs_RbReadData, 0x10000c) + FldFunc(StrRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(StreamRingbusDebugRegsBase, 0x100080, 0x1000FF) +RegFunc(StreamRingbusDebugRegs, 0x100080, RbDebugConfig, 0x0, StrRDRs_RbDebugConfig, 0x100080) + FldFunc(StrRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(StrRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(StreamRingbusDebugRegs, 0x100080, RbDebugReg0Addr, 0x4, StrRDRs_RbDebugReg0Addr, 0x100084) + FldFunc(StrRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(StreamRingbusDebugRegs, 0x100080, RbDebugReg1Addr, 0x8, StrRDRs_RbDebugReg1Addr, 0x100088) + FldFunc(StrRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(StreamRingbusDebugRegs, 0x100080, RbDebugReg2Addr, 0xC, StrRDRs_RbDebugReg2Addr, 0x10008c) + FldFunc(StrRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(StreamRingbusDebugRegs, 0x100080, RbDebugReg3Addr, 0x10, StrRDRs_RbDebugReg3Addr, 0x100090) + FldFunc(StrRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(StreamRingbusDebugRegs, 0x100080, RbDebugOutputReg, 0x14, StrRDRs_RbDebugOutputReg, 0x100094) + FldFunc(StrRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(StrRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(StreamTsRegsABase, 0x100400, 0x1005FF) +RegFunc(StreamTsRegsA, 0x100400, TsCtl, 0x0, StrTRA_TsCtl, 0x100400) + FldFunc(StrTRA_TsCtl, Aao, 22, 1) + FldFunc(StrTRA_TsCtl, Dcd, 21, 1) + FldFunc(StrTRA_TsCtl, Rtsu, 20, 1) + FldFunc(StrTRA_TsCtl, Rte, 19, 1) + FldFunc(StrTRA_TsCtl, Efs, 18, 1) + FldFunc(StrTRA_TsCtl, Via, 17, 1) + FldFunc(StrTRA_TsCtl, Spi, 16, 1) + FldFunc(StrTRA_TsCtl, Udtaf, 15, 1) + FldFunc(StrTRA_TsCtl, Dd, 14, 1) + FldFunc(StrTRA_TsCtl, Rde, 12, 1) + FldFunc(StrTRA_TsCtl, Rse, 11, 1) + FldFunc(StrTRA_TsCtl, Im, 10, 1) + FldFunc(StrTRA_TsCtl, Serm, 9, 1) + FldFunc(StrTRA_TsCtl, Syncm, 8, 1) + FldFunc(StrTRA_TsCtl, Tsm, 7, 1) + FldFunc(StrTRA_TsCtl, Tsdm, 6, 1) + FldFunc(StrTRA_TsCtl, Pcru, 5, 1) + FldFunc(StrTRA_TsCtl, Vm, 4, 1) + FldFunc(StrTRA_TsCtl, Psm, 3, 1) + FldFunc(StrTRA_TsCtl, Sync, 2, 1) + FldFunc(StrTRA_TsCtl, Ss, 1, 1) + FldFunc(StrTRA_TsCtl, Byps, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsPcrRx0, 0x4, StrTRA_TsPcrRx0, 0x100404) + FldFunc(StrTRA_TsPcrRx0, Rpcrb, 16, 16) + FldFunc(StrTRA_TsPcrRx0, Rpcre, 0, 9) +RegFunc(StreamTsRegsA, 0x100400, TsPcrRx1, 0x8, StrTRA_TsPcrRx1, 0x100408) + FldFunc(StrTRA_TsPcrRx1, Rpcrb, 0, 17) +RegFunc(StreamTsRegsA, 0x100400, TsStcCntr0, 0xC, StrTRA_TsStcCntr0, 0x10040c) + FldFunc(StrTRA_TsStcCntr0, Ppcrb, 16, 16) + FldFunc(StrTRA_TsStcCntr0, Ppcre, 0, 5) +RegFunc(StreamTsRegsA, 0x100400, TsStcCntr1, 0x10, StrTRA_TsStcCntr1, 0x100410) + FldFunc(StrTRA_TsStcCntr1, Ppcrb, 0, 17) +RegFunc(StreamTsRegsA, 0x100400, TsPidVid, 0x14, StrTRA_TsPidVid, 0x100414) + FldFunc(StrTRA_TsPidVid, Siee, 26, 1) + FldFunc(StrTRA_TsPidVid, Sube, 25, 1) + FldFunc(StrTRA_TsPidVid, Priv, 23, 2) + FldFunc(StrTRA_TsPidVid, Typ, 22, 1) + FldFunc(StrTRA_TsPidVid, Piu, 21, 1) + FldFunc(StrTRA_TsPidVid, Si, 13, 8) + FldFunc(StrTRA_TsPidVid, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidPcr, 0x18, StrTRA_TsPidPcr, 0x100418) + FldFunc(StrTRA_TsPidPcr, Piu, 21, 1) + FldFunc(StrTRA_TsPidPcr, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUpdate0, 0x1C, StrTRA_TsUpdate0, 0x10041c) + FldFunc(StrTRA_TsUpdate0, Cpcrb, 16, 16) + FldFunc(StrTRA_TsUpdate0, Cpcre, 0, 9) +RegFunc(StreamTsRegsA, 0x100400, TsUpdate1, 0x20, StrTRA_TsUpdate1, 0x100420) + FldFunc(StrTRA_TsUpdate1, Cpcrb, 0, 17) +RegFunc(StreamTsRegsA, 0x100400, TsRefCnt, 0x24, StrTRA_TsRefCnt, 0x100424) + FldFunc(StrTRA_TsRefCnt, Rfcnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsPidAud0, 0x28, StrTRA_TsPidAud0, 0x100428) + FldFunc(StrTRA_TsPidAud0, Siee, 26, 1) + FldFunc(StrTRA_TsPidAud0, Sube, 25, 1) + FldFunc(StrTRA_TsPidAud0, Priv, 23, 2) + FldFunc(StrTRA_TsPidAud0, Typ, 22, 1) + FldFunc(StrTRA_TsPidAud0, Piu, 21, 1) + FldFunc(StrTRA_TsPidAud0, Si, 13, 8) + FldFunc(StrTRA_TsPidAud0, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidAud1, 0x2C, StrTRA_TsPidAud1, 0x10042c) + FldFunc(StrTRA_TsPidAud1, Siee, 26, 1) + FldFunc(StrTRA_TsPidAud1, Sube, 25, 1) + FldFunc(StrTRA_TsPidAud1, Priv, 23, 2) + FldFunc(StrTRA_TsPidAud1, Typ, 22, 1) + FldFunc(StrTRA_TsPidAud1, Piu, 21, 1) + FldFunc(StrTRA_TsPidAud1, Si, 13, 8) + FldFunc(StrTRA_TsPidAud1, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidAud2, 0x30, StrTRA_TsPidAud2, 0x100430) + FldFunc(StrTRA_TsPidAud2, Siee, 26, 1) + FldFunc(StrTRA_TsPidAud2, Sube, 25, 1) + FldFunc(StrTRA_TsPidAud2, Priv, 23, 2) + FldFunc(StrTRA_TsPidAud2, Typ, 22, 1) + FldFunc(StrTRA_TsPidAud2, Piu, 21, 1) + FldFunc(StrTRA_TsPidAud2, Si, 13, 8) + FldFunc(StrTRA_TsPidAud2, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidUser0, 0x34, StrTRA_TsPidUser0, 0x100434) + FldFunc(StrTRA_TsPidUser0, Piu, 21, 1) + FldFunc(StrTRA_TsPidUser0, Si, 13, 8) + FldFunc(StrTRA_TsPidUser0, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidUser1, 0x38, StrTRA_TsPidUser1, 0x100438) + FldFunc(StrTRA_TsPidUser1, Piu, 21, 1) + FldFunc(StrTRA_TsPidUser1, Si, 13, 8) + FldFunc(StrTRA_TsPidUser1, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidUser2, 0x3C, StrTRA_TsPidUser2, 0x10043c) + FldFunc(StrTRA_TsPidUser2, Piu, 21, 1) + FldFunc(StrTRA_TsPidUser2, Si, 13, 8) + FldFunc(StrTRA_TsPidUser2, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidUser3, 0x40, StrTRA_TsPidUser3, 0x100440) + FldFunc(StrTRA_TsPidUser3, Piu, 21, 1) + FldFunc(StrTRA_TsPidUser3, Si, 13, 8) + FldFunc(StrTRA_TsPidUser3, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPidUser4, 0x44, StrTRA_TsPidUser4, 0x100444) + FldFunc(StrTRA_TsPidUser4, Piu, 21, 1) + FldFunc(StrTRA_TsPidUser4, Si, 13, 8) + FldFunc(StrTRA_TsPidUser4, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPcrChanged, 0x48, StrTRA_TsPcrChanged, 0x100448) + FldFunc(StrTRA_TsPcrChanged, Pcrc, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsFifoStatus, 0x4C, StrTRA_TsFifoStatus, 0x10044c) + FldFunc(StrTRA_TsFifoStatus, Ue, 20, 1) + FldFunc(StrTRA_TsFifoStatus, Uaf, 19, 1) + FldFunc(StrTRA_TsFifoStatus, Dfaf, 16, 1) + FldFunc(StrTRA_TsFifoStatus, Dfe, 15, 1) + FldFunc(StrTRA_TsFifoStatus, Vaf, 13, 1) + FldFunc(StrTRA_TsFifoStatus, De, 12, 1) + FldFunc(StrTRA_TsFifoStatus, Daf, 11, 1) + FldFunc(StrTRA_TsFifoStatus, Pe, 10, 1) + FldFunc(StrTRA_TsFifoStatus, Paf, 9, 1) + FldFunc(StrTRA_TsFifoStatus, Hfo, 8, 1) + FldFunc(StrTRA_TsFifoStatus, Hfhe, 7, 1) + FldFunc(StrTRA_TsFifoStatus, Hfe, 6, 1) + FldFunc(StrTRA_TsFifoStatus, Hfaf, 5, 1) + FldFunc(StrTRA_TsFifoStatus, Efo, 4, 1) + FldFunc(StrTRA_TsFifoStatus, Efhe, 3, 1) + FldFunc(StrTRA_TsFifoStatus, Efe, 2, 1) + FldFunc(StrTRA_TsFifoStatus, Efaf, 1, 1) + FldFunc(StrTRA_TsFifoStatus, Eff, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsSoftReset, 0x50, StrTRA_TsSoftReset, 0x100450) + FldFunc(StrTRA_TsSoftReset, Srst, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsOosCnt, 0x54, StrTRA_TsOosCnt, 0x100454) + FldFunc(StrTRA_TsOosCnt, Oosc, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsDiscontCnt, 0x58, StrTRA_TsDiscontCnt, 0x100458) + FldFunc(StrTRA_TsDiscontCnt, Dc, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsSpmresyncCnt, 0x5C, StrTRA_TsSpmresyncCnt, 0x10045c) + FldFunc(StrTRA_TsSpmresyncCnt, Spmrc, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUserOflwDone, 0x60, StrTRA_TsUserOflwDone, 0x100460) + FldFunc(StrTRA_TsUserOflwDone, U4d, 4, 1) + FldFunc(StrTRA_TsUserOflwDone, U3d, 3, 1) + FldFunc(StrTRA_TsUserOflwDone, U2d, 2, 1) + FldFunc(StrTRA_TsUserOflwDone, U1d, 1, 1) + FldFunc(StrTRA_TsUserOflwDone, U0d, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser0Base, 0x64, StrTRA_TsUser0Base, 0x100464) + FldFunc(StrTRA_TsUser0Base, Base, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser0Rptr, 0x68, StrTRA_TsUser0Rptr, 0x100468) + FldFunc(StrTRA_TsUser0Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser0Wrptr, 0x6C, StrTRA_TsUser0Wrptr, 0x10046c) + FldFunc(StrTRA_TsUser0Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser0Len, 0x70, StrTRA_TsUser0Len, 0x100470) + FldFunc(StrTRA_TsUser0Len, Len, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser0End, 0x74, StrTRA_TsUser0End, 0x100474) + FldFunc(StrTRA_TsUser0End, End, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser0Empty, 0x78, StrTRA_TsUser0Empty, 0x100478) + FldFunc(StrTRA_TsUser0Empty, E, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser1Base, 0x7C, StrTRA_TsUser1Base, 0x10047c) + FldFunc(StrTRA_TsUser1Base, Base, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser1Rptr, 0x80, StrTRA_TsUser1Rptr, 0x100480) + FldFunc(StrTRA_TsUser1Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser1Wrptr, 0x84, StrTRA_TsUser1Wrptr, 0x100484) + FldFunc(StrTRA_TsUser1Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser1Len, 0x88, StrTRA_TsUser1Len, 0x100488) + FldFunc(StrTRA_TsUser1Len, Len, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser1End, 0x8C, StrTRA_TsUser1End, 0x10048c) + FldFunc(StrTRA_TsUser1End, End, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser1Empty, 0x90, StrTRA_TsUser1Empty, 0x100490) + FldFunc(StrTRA_TsUser1Empty, E, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser2Base, 0x94, StrTRA_TsUser2Base, 0x100494) + FldFunc(StrTRA_TsUser2Base, Base, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser2Rptr, 0x98, StrTRA_TsUser2Rptr, 0x100498) + FldFunc(StrTRA_TsUser2Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser2Wrptr, 0x9C, StrTRA_TsUser2Wrptr, 0x10049c) + FldFunc(StrTRA_TsUser2Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser2Len, 0xA0, StrTRA_TsUser2Len, 0x1004a0) + FldFunc(StrTRA_TsUser2Len, Len, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser2End, 0xA4, StrTRA_TsUser2End, 0x1004a4) + FldFunc(StrTRA_TsUser2End, End, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser2Empty, 0xA8, StrTRA_TsUser2Empty, 0x1004a8) + FldFunc(StrTRA_TsUser2Empty, E, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser3Base, 0xAC, StrTRA_TsUser3Base, 0x1004ac) + FldFunc(StrTRA_TsUser3Base, Base, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser3Rptr, 0xB0, StrTRA_TsUser3Rptr, 0x1004b0) + FldFunc(StrTRA_TsUser3Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser3Wrptr, 0xB4, StrTRA_TsUser3Wrptr, 0x1004b4) + FldFunc(StrTRA_TsUser3Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser3Len, 0xB8, StrTRA_TsUser3Len, 0x1004b8) + FldFunc(StrTRA_TsUser3Len, Len, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser3End, 0xBC, StrTRA_TsUser3End, 0x1004bc) + FldFunc(StrTRA_TsUser3End, End, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser3Empty, 0xC0, StrTRA_TsUser3Empty, 0x1004c0) + FldFunc(StrTRA_TsUser3Empty, E, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser4Base, 0xC4, StrTRA_TsUser4Base, 0x1004c4) + FldFunc(StrTRA_TsUser4Base, Base, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser4Rptr, 0xC8, StrTRA_TsUser4Rptr, 0x1004c8) + FldFunc(StrTRA_TsUser4Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser4Wrptr, 0xCC, StrTRA_TsUser4Wrptr, 0x1004cc) + FldFunc(StrTRA_TsUser4Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser4Len, 0xD0, StrTRA_TsUser4Len, 0x1004d0) + FldFunc(StrTRA_TsUser4Len, Len, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser4End, 0xD4, StrTRA_TsUser4End, 0x1004d4) + FldFunc(StrTRA_TsUser4End, End, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUser4Empty, 0xD8, StrTRA_TsUser4Empty, 0x1004d8) + FldFunc(StrTRA_TsUser4Empty, E, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsPktDropCnt, 0xDC, StrTRA_TsPktDropCnt, 0x1004dc) + FldFunc(StrTRA_TsPktDropCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsPktErrCnt, 0xE0, StrTRA_TsPktErrCnt, 0x1004e0) + FldFunc(StrTRA_TsPktErrCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsVidPktCnt, 0xE4, StrTRA_TsVidPktCnt, 0x1004e4) + FldFunc(StrTRA_TsVidPktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsAud0PktCnt, 0xE8, StrTRA_TsAud0PktCnt, 0x1004e8) + FldFunc(StrTRA_TsAud0PktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsAud1PktCnt, 0xEC, StrTRA_TsAud1PktCnt, 0x1004ec) + FldFunc(StrTRA_TsAud1PktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsAud2PktCnt, 0xF0, StrTRA_TsAud2PktCnt, 0x1004f0) + FldFunc(StrTRA_TsAud2PktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUserPktCnt, 0xF4, StrTRA_TsUserPktCnt, 0x1004f4) + FldFunc(StrTRA_TsUserPktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsDescramCtl, 0xF8, StrTRA_TsDescramCtl, 0x1004f8) + FldFunc(StrTRA_TsDescramCtl, Drph, 11, 1) + FldFunc(StrTRA_TsDescramCtl, Pkt, 10, 1) + FldFunc(StrTRA_TsDescramCtl, Est, 8, 2) + FldFunc(StrTRA_TsDescramCtl, Ost, 6, 2) + FldFunc(StrTRA_TsDescramCtl, Usc, 5, 1) + FldFunc(StrTRA_TsDescramCtl, Scctl, 4, 1) + FldFunc(StrTRA_TsDescramCtl, Scmod, 3, 1) + FldFunc(StrTRA_TsDescramCtl, Trmtyp, 2, 1) + FldFunc(StrTRA_TsDescramCtl, Type, 1, 1) + FldFunc(StrTRA_TsDescramCtl, En, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsKeyEven0, 0xFC, StrTRA_TsKeyEven0, 0x1004fc) + FldFunc(StrTRA_TsKeyEven0, Key310, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyEven1, 0x100, StrTRA_TsKeyEven1, 0x100500) + FldFunc(StrTRA_TsKeyEven1, Key6332, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyEven2, 0x104, StrTRA_TsKeyEven2, 0x100504) + FldFunc(StrTRA_TsKeyEven2, Key9564, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyEven3, 0x108, StrTRA_TsKeyEven3, 0x100508) + FldFunc(StrTRA_TsKeyEven3, Key12796, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyOdd0, 0x10C, StrTRA_TsKeyOdd0, 0x10050c) + FldFunc(StrTRA_TsKeyOdd0, Key310, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyOdd1, 0x110, StrTRA_TsKeyOdd1, 0x100510) + FldFunc(StrTRA_TsKeyOdd1, Key6332, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyOdd2, 0x114, StrTRA_TsKeyOdd2, 0x100514) + FldFunc(StrTRA_TsKeyOdd2, Key9564, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsKeyOdd3, 0x118, StrTRA_TsKeyOdd3, 0x100518) + FldFunc(StrTRA_TsKeyOdd3, Key12796, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsStcIsCrap, 0x11C, StrTRA_TsStcIsCrap, 0x10051c) + FldFunc(StrTRA_TsStcIsCrap, Typ, 1, 1) + FldFunc(StrTRA_TsStcIsCrap, Sic, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsTsdAdconfig, 0x120, StrTRA_TsTsdAdconfig, 0x100520) + FldFunc(StrTRA_TsTsdAdconfig, Rs, 12, 1) + FldFunc(StrTRA_TsTsdAdconfig, Pnty, 8, 4) + FldFunc(StrTRA_TsTsdAdconfig, Ost, 4, 4) + FldFunc(StrTRA_TsTsdAdconfig, Ist, 0, 4) +RegFunc(StreamTsRegsA, 0x100400, TsStcref900, 0x124, StrTRA_TsStcref900, 0x100524) + FldFunc(StrTRA_TsStcref900, Ppcrb, 31, 1) + FldFunc(StrTRA_TsStcref900, Ppcre, 0, 9) +RegFunc(StreamTsRegsA, 0x100400, TsStcref901, 0x128, StrTRA_TsStcref901, 0x100528) + FldFunc(StrTRA_TsStcref901, Ppcrb, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsRtsUpdate, 0x12C, StrTRA_TsRtsUpdate, 0x10052c) + FldFunc(StrTRA_TsRtsUpdate, Rtsu, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsStcref27, 0x130, StrTRA_TsStcref27, 0x100530) + FldFunc(StrTRA_TsStcref27, Stc27, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsRtsChanged, 0x134, StrTRA_TsRtsChanged, 0x100534) + FldFunc(StrTRA_TsRtsChanged, Rc, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsRtsRx, 0x138, StrTRA_TsRtsRx, 0x100538) + FldFunc(StrTRA_TsRtsRx, Rtsrx, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsRefcntSave, 0x13C, StrTRA_TsRefcntSave, 0x10053c) + FldFunc(StrTRA_TsRefcntSave, Ref, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsTsmConfig, 0x140, StrTRA_TsTsmConfig, 0x100540) + FldFunc(StrTRA_TsTsmConfig, Sras, 28, 1) + FldFunc(StrTRA_TsTsmConfig, Zvrc, 27, 1) + FldFunc(StrTRA_TsTsmConfig, Cs27, 26, 1) + FldFunc(StrTRA_TsTsmConfig, Cs90, 25, 1) + FldFunc(StrTRA_TsTsmConfig, Ppu, 24, 1) + FldFunc(StrTRA_TsTsmConfig, Spi, 23, 1) + FldFunc(StrTRA_TsTsmConfig, Un, 2, 1) + FldFunc(StrTRA_TsTsmConfig, Udm, 1, 1) + FldFunc(StrTRA_TsTsmConfig, Os, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsPcrTrigger, 0x144, StrTRA_TsPcrTrigger, 0x100544) + FldFunc(StrTRA_TsPcrTrigger, Pt, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsIntStat, 0x148, StrTRA_TsIntStat, 0x100548) + FldFunc(StrTRA_TsIntStat, U4o, 25, 1) + FldFunc(StrTRA_TsIntStat, U3o, 24, 1) + FldFunc(StrTRA_TsIntStat, U2o, 23, 1) + FldFunc(StrTRA_TsIntStat, U1o, 22, 1) + FldFunc(StrTRA_TsIntStat, U0o, 21, 1) + FldFunc(StrTRA_TsIntStat, U4sp, 20, 1) + FldFunc(StrTRA_TsIntStat, U3sp, 19, 1) + FldFunc(StrTRA_TsIntStat, U2sp, 18, 1) + FldFunc(StrTRA_TsIntStat, U1sp, 17, 1) + FldFunc(StrTRA_TsIntStat, U0sp, 16, 1) + FldFunc(StrTRA_TsIntStat, Psp, 15, 1) + FldFunc(StrTRA_TsIntStat, A2sp, 14, 1) + FldFunc(StrTRA_TsIntStat, A1sp, 13, 1) + FldFunc(StrTRA_TsIntStat, A0sp, 12, 1) + FldFunc(StrTRA_TsIntStat, Vsp, 11, 1) + FldFunc(StrTRA_TsIntStat, Va, 10, 1) + FldFunc(StrTRA_TsIntStat, I2o, 9, 1) + FldFunc(StrTRA_TsIntStat, I1o, 8, 1) + FldFunc(StrTRA_TsIntStat, I0o, 7, 1) + FldFunc(StrTRA_TsIntStat, C2o, 6, 1) + FldFunc(StrTRA_TsIntStat, C1o, 5, 1) + FldFunc(StrTRA_TsIntStat, C0o, 4, 1) + FldFunc(StrTRA_TsIntStat, Uf, 3, 1) + FldFunc(StrTRA_TsIntStat, Ho, 1, 1) + FldFunc(StrTRA_TsIntStat, Eo, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsIntMask, 0x14C, StrTRA_TsIntMask, 0x10054c) + FldFunc(StrTRA_TsIntMask, U4o, 25, 1) + FldFunc(StrTRA_TsIntMask, U3o, 24, 1) + FldFunc(StrTRA_TsIntMask, U2o, 23, 1) + FldFunc(StrTRA_TsIntMask, U1o, 22, 1) + FldFunc(StrTRA_TsIntMask, U0o, 21, 1) + FldFunc(StrTRA_TsIntMask, U4sp, 20, 1) + FldFunc(StrTRA_TsIntMask, U3sp, 19, 1) + FldFunc(StrTRA_TsIntMask, U2sp, 18, 1) + FldFunc(StrTRA_TsIntMask, U1sp, 17, 1) + FldFunc(StrTRA_TsIntMask, U0sp, 16, 1) + FldFunc(StrTRA_TsIntMask, Psp, 15, 1) + FldFunc(StrTRA_TsIntMask, A2sp, 14, 1) + FldFunc(StrTRA_TsIntMask, A1sp, 13, 1) + FldFunc(StrTRA_TsIntMask, A0sp, 12, 1) + FldFunc(StrTRA_TsIntMask, Vsp, 11, 1) + FldFunc(StrTRA_TsIntMask, Eva, 10, 1) + FldFunc(StrTRA_TsIntMask, Ei2o, 9, 1) + FldFunc(StrTRA_TsIntMask, Ei1o, 8, 1) + FldFunc(StrTRA_TsIntMask, Ei0o, 7, 1) + FldFunc(StrTRA_TsIntMask, Ec2o, 6, 1) + FldFunc(StrTRA_TsIntMask, Ec1o, 5, 1) + FldFunc(StrTRA_TsIntMask, Ec0o, 4, 1) + FldFunc(StrTRA_TsIntMask, Euf, 3, 1) + FldFunc(StrTRA_TsIntMask, Eho, 1, 1) + FldFunc(StrTRA_TsIntMask, Eeo, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsBtpCtl, 0x150, StrTRA_TsBtpCtl, 0x100550) + FldFunc(StrTRA_TsBtpCtl, Ebpc, 1, 1) + FldFunc(StrTRA_TsBtpCtl, Ebo, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsTsfifoByteCnt, 0x154, StrTRA_TsTsfifoByteCnt, 0x100554) + FldFunc(StrTRA_TsTsfifoByteCnt, Tfbc, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsPktbuffByteCnt, 0x158, StrTRA_TsPktbuffByteCnt, 0x100558) + FldFunc(StrTRA_TsPktbuffByteCnt, Pbc, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsSpliceEn, 0x15C, StrTRA_TsSpliceEn, 0x10055c) + FldFunc(StrTRA_TsSpliceEn, A2se, 13, 1) + FldFunc(StrTRA_TsSpliceEn, A1se, 12, 1) + FldFunc(StrTRA_TsSpliceEn, A0se, 11, 1) + FldFunc(StrTRA_TsSpliceEn, Vse, 10, 1) + FldFunc(StrTRA_TsSpliceEn, U4en, 9, 1) + FldFunc(StrTRA_TsSpliceEn, U3en, 8, 1) + FldFunc(StrTRA_TsSpliceEn, U2en, 7, 1) + FldFunc(StrTRA_TsSpliceEn, U1en, 6, 1) + FldFunc(StrTRA_TsSpliceEn, U0en, 5, 1) + FldFunc(StrTRA_TsSpliceEn, Pen, 4, 1) + FldFunc(StrTRA_TsSpliceEn, A2en, 3, 1) + FldFunc(StrTRA_TsSpliceEn, A1en, 2, 1) + FldFunc(StrTRA_TsSpliceEn, A0en, 1, 1) + FldFunc(StrTRA_TsSpliceEn, Ven, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsVidspliceBuf, 0x160, StrTRA_TsVidspliceBuf, 0x100560) + FldFunc(StrTRA_TsVidspliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsVidspliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsVidspliceBuf, Se, 13, 2) + FldFunc(StrTRA_TsVidspliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsAud0spliceBuf, 0x164, StrTRA_TsAud0spliceBuf, 0x100564) + FldFunc(StrTRA_TsAud0spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsAud0spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsAud0spliceBuf, Se, 13, 2) + FldFunc(StrTRA_TsAud0spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsAud1spliceBuf, 0x168, StrTRA_TsAud1spliceBuf, 0x100568) + FldFunc(StrTRA_TsAud1spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsAud1spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsAud1spliceBuf, Se, 13, 2) + FldFunc(StrTRA_TsAud1spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsAud2spliceBuf, 0x16C, StrTRA_TsAud2spliceBuf, 0x10056c) + FldFunc(StrTRA_TsAud2spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsAud2spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsAud2spliceBuf, Se, 13, 2) + FldFunc(StrTRA_TsAud2spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsPcrspliceBuf, 0x170, StrTRA_TsPcrspliceBuf, 0x100570) + FldFunc(StrTRA_TsPcrspliceBuf, Ne, 14, 1) + FldFunc(StrTRA_TsPcrspliceBuf, Full, 13, 1) + FldFunc(StrTRA_TsPcrspliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUnmarkedThresh, 0x174, StrTRA_TsUnmarkedThresh, 0x100574) + FldFunc(StrTRA_TsUnmarkedThresh, Ut, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsVidspliceCnt, 0x178, StrTRA_TsVidspliceCnt, 0x100578) + FldFunc(StrTRA_TsVidspliceCnt, Act, 8, 1) + FldFunc(StrTRA_TsVidspliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsAud0spliceCnt, 0x17C, StrTRA_TsAud0spliceCnt, 0x10057c) + FldFunc(StrTRA_TsAud0spliceCnt, Act, 8, 1) + FldFunc(StrTRA_TsAud0spliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsAud1spliceCnt, 0x180, StrTRA_TsAud1spliceCnt, 0x100580) + FldFunc(StrTRA_TsAud1spliceCnt, Act, 8, 1) + FldFunc(StrTRA_TsAud1spliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsAud2spliceCnt, 0x184, StrTRA_TsAud2spliceCnt, 0x100584) + FldFunc(StrTRA_TsAud2spliceCnt, Act, 8, 1) + FldFunc(StrTRA_TsAud2spliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPcrspliceCnt, 0x188, StrTRA_TsPcrspliceCnt, 0x100588) + FldFunc(StrTRA_TsPcrspliceCnt, Act, 8, 1) + FldFunc(StrTRA_TsPcrspliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesStrmidRange, 0x18C, StrTRA_TsPesStrmidRange, 0x10058c) + FldFunc(StrTRA_TsPesStrmidRange, Hi, 8, 8) + FldFunc(StrTRA_TsPesStrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsVidStrmidRange, 0x190, StrTRA_TsVidStrmidRange, 0x100590) + FldFunc(StrTRA_TsVidStrmidRange, Hi, 8, 8) + FldFunc(StrTRA_TsVidStrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsAud0StrmidRange, 0x194, StrTRA_TsAud0StrmidRange, 0x100594) + FldFunc(StrTRA_TsAud0StrmidRange, Hi, 8, 8) + FldFunc(StrTRA_TsAud0StrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsAud1StrmidRange, 0x198, StrTRA_TsAud1StrmidRange, 0x100598) + FldFunc(StrTRA_TsAud1StrmidRange, Hi, 8, 8) + FldFunc(StrTRA_TsAud1StrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsAud2StrmidRange, 0x19C, StrTRA_TsAud2StrmidRange, 0x10059c) + FldFunc(StrTRA_TsAud2StrmidRange, Hi, 8, 8) + FldFunc(StrTRA_TsAud2StrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesNoext0, 0x1A0, StrTRA_TsPesNoext0, 0x1005a0) + FldFunc(StrTRA_TsPesNoext0, En2, 26, 1) + FldFunc(StrTRA_TsPesNoext0, En1, 25, 1) + FldFunc(StrTRA_TsPesNoext0, En0, 24, 1) + FldFunc(StrTRA_TsPesNoext0, Ext2, 16, 8) + FldFunc(StrTRA_TsPesNoext0, Ext1, 8, 8) + FldFunc(StrTRA_TsPesNoext0, Ext0, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesNoext1, 0x1A4, StrTRA_TsPesNoext1, 0x1005a4) + FldFunc(StrTRA_TsPesNoext1, En2, 26, 1) + FldFunc(StrTRA_TsPesNoext1, En1, 25, 1) + FldFunc(StrTRA_TsPesNoext1, En0, 24, 1) + FldFunc(StrTRA_TsPesNoext1, Ext2, 16, 8) + FldFunc(StrTRA_TsPesNoext1, Ext1, 8, 8) + FldFunc(StrTRA_TsPesNoext1, Ext0, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesNoext2, 0x1A8, StrTRA_TsPesNoext2, 0x1005a8) + FldFunc(StrTRA_TsPesNoext2, En2, 26, 1) + FldFunc(StrTRA_TsPesNoext2, En1, 25, 1) + FldFunc(StrTRA_TsPesNoext2, En0, 24, 1) + FldFunc(StrTRA_TsPesNoext2, Ext2, 16, 8) + FldFunc(StrTRA_TsPesNoext2, Ext1, 8, 8) + FldFunc(StrTRA_TsPesNoext2, Ext0, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesNoext3, 0x1AC, StrTRA_TsPesNoext3, 0x1005ac) + FldFunc(StrTRA_TsPesNoext3, En2, 26, 1) + FldFunc(StrTRA_TsPesNoext3, En1, 25, 1) + FldFunc(StrTRA_TsPesNoext3, En0, 24, 1) + FldFunc(StrTRA_TsPesNoext3, Ext2, 16, 8) + FldFunc(StrTRA_TsPesNoext3, Ext1, 8, 8) + FldFunc(StrTRA_TsPesNoext3, Ext0, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesNoext4, 0x1B0, StrTRA_TsPesNoext4, 0x1005b0) + FldFunc(StrTRA_TsPesNoext4, En2, 26, 1) + FldFunc(StrTRA_TsPesNoext4, En1, 25, 1) + FldFunc(StrTRA_TsPesNoext4, En0, 24, 1) + FldFunc(StrTRA_TsPesNoext4, Ext2, 16, 8) + FldFunc(StrTRA_TsPesNoext4, Ext1, 8, 8) + FldFunc(StrTRA_TsPesNoext4, Ext0, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsPesNoext5, 0x1B4, StrTRA_TsPesNoext5, 0x1005b4) + FldFunc(StrTRA_TsPesNoext5, En2, 26, 1) + FldFunc(StrTRA_TsPesNoext5, En1, 25, 1) + FldFunc(StrTRA_TsPesNoext5, En0, 24, 1) + FldFunc(StrTRA_TsPesNoext5, Ext2, 16, 8) + FldFunc(StrTRA_TsPesNoext5, Ext1, 8, 8) + FldFunc(StrTRA_TsPesNoext5, Ext0, 0, 8) +RegFunc(StreamTsRegsA, 0x100400, TsUser0spliceCnt, 0x1B8, StrTRA_TsUser0spliceCnt, 0x1005b8) + FldFunc(StrTRA_TsUser0spliceCnt, Cnt, 1, 8) + FldFunc(StrTRA_TsUser0spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser1spliceCnt, 0x1BC, StrTRA_TsUser1spliceCnt, 0x1005bc) + FldFunc(StrTRA_TsUser1spliceCnt, Cnt, 1, 8) + FldFunc(StrTRA_TsUser1spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser2spliceCnt, 0x1C0, StrTRA_TsUser2spliceCnt, 0x1005c0) + FldFunc(StrTRA_TsUser2spliceCnt, Cnt, 1, 8) + FldFunc(StrTRA_TsUser2spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser3spliceCnt, 0x1C4, StrTRA_TsUser3spliceCnt, 0x1005c4) + FldFunc(StrTRA_TsUser3spliceCnt, Cnt, 1, 8) + FldFunc(StrTRA_TsUser3spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser4spliceCnt, 0x1C8, StrTRA_TsUser4spliceCnt, 0x1005c8) + FldFunc(StrTRA_TsUser4spliceCnt, Cnt, 1, 8) + FldFunc(StrTRA_TsUser4spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsUser0spliceBuf, 0x1CC, StrTRA_TsUser0spliceBuf, 0x1005cc) + FldFunc(StrTRA_TsUser0spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsUser0spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsUser0spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUser1spliceBuf, 0x1D0, StrTRA_TsUser1spliceBuf, 0x1005d0) + FldFunc(StrTRA_TsUser1spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsUser1spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsUser1spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUser2spliceBuf, 0x1D4, StrTRA_TsUser2spliceBuf, 0x1005d4) + FldFunc(StrTRA_TsUser2spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsUser2spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsUser2spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUser3spliceBuf, 0x1D8, StrTRA_TsUser3spliceBuf, 0x1005d8) + FldFunc(StrTRA_TsUser3spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsUser3spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsUser3spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUser4spliceBuf, 0x1DC, StrTRA_TsUser4spliceBuf, 0x1005dc) + FldFunc(StrTRA_TsUser4spliceBuf, Ne, 16, 1) + FldFunc(StrTRA_TsUser4spliceBuf, Full, 15, 1) + FldFunc(StrTRA_TsUser4spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsA, 0x100400, TsUpdWaiting, 0x1E0, StrTRA_TsUpdWaiting, 0x1005e0) + FldFunc(StrTRA_TsUpdWaiting, Ruw, 1, 1) + FldFunc(StrTRA_TsUpdWaiting, Puw, 0, 1) +RegFunc(StreamTsRegsA, 0x100400, TsAud0Extid, 0x1E4, StrTRA_TsAud0Extid, 0x1005e4) + FldFunc(StrTRA_TsAud0Extid, Eidv, 15, 1) + FldFunc(StrTRA_TsAud0Extid, Eid, 8, 7) + FldFunc(StrTRA_TsAud0Extid, Cidv, 7, 1) + FldFunc(StrTRA_TsAud0Extid, Cid, 0, 7) +RegFunc(StreamTsRegsA, 0x100400, TsAud1Extid, 0x1E8, StrTRA_TsAud1Extid, 0x1005e8) + FldFunc(StrTRA_TsAud1Extid, Eidv, 15, 1) + FldFunc(StrTRA_TsAud1Extid, Eid, 8, 7) + FldFunc(StrTRA_TsAud1Extid, Cidv, 7, 1) + FldFunc(StrTRA_TsAud1Extid, Cid, 0, 7) +RegFunc(StreamTsRegsA, 0x100400, TsAud2Extid, 0x1EC, StrTRA_TsAud2Extid, 0x1005ec) + FldFunc(StrTRA_TsAud2Extid, Eidv, 15, 1) + FldFunc(StrTRA_TsAud2Extid, Eid, 8, 7) + FldFunc(StrTRA_TsAud2Extid, Cidv, 7, 1) + FldFunc(StrTRA_TsAud2Extid, Cid, 0, 7) +RegFunc(StreamTsRegsA, 0x100400, TsPcrOffset, 0x1F0, StrTRA_TsPcrOffset, 0x1005f0) + FldFunc(StrTRA_TsPcrOffset, Pcro, 0, 32) +RegFunc(StreamTsRegsA, 0x100400, TsUsePusi, 0x1F4, StrTRA_TsUsePusi, 0x1005f4) + FldFunc(StrTRA_TsUsePusi, A2up, 3, 1) + FldFunc(StrTRA_TsUsePusi, A1up, 2, 1) + FldFunc(StrTRA_TsUsePusi, A0up, 1, 1) + FldFunc(StrTRA_TsUsePusi, Vup, 0, 1) + +RegAreaFunc(StreamTsRegsBBase, 0x100800, 0x1009FF) +RegFunc(StreamTsRegsB, 0x100800, TsCtl, 0x0, StrTRB_TsCtl, 0x100800) + FldFunc(StrTRB_TsCtl, Aao, 22, 1) + FldFunc(StrTRB_TsCtl, Dcd, 21, 1) + FldFunc(StrTRB_TsCtl, Rtsu, 20, 1) + FldFunc(StrTRB_TsCtl, Rte, 19, 1) + FldFunc(StrTRB_TsCtl, Efs, 18, 1) + FldFunc(StrTRB_TsCtl, Via, 17, 1) + FldFunc(StrTRB_TsCtl, Spi, 16, 1) + FldFunc(StrTRB_TsCtl, Udtaf, 15, 1) + FldFunc(StrTRB_TsCtl, Dd, 14, 1) + FldFunc(StrTRB_TsCtl, Rde, 12, 1) + FldFunc(StrTRB_TsCtl, Rse, 11, 1) + FldFunc(StrTRB_TsCtl, Im, 10, 1) + FldFunc(StrTRB_TsCtl, Serm, 9, 1) + FldFunc(StrTRB_TsCtl, Syncm, 8, 1) + FldFunc(StrTRB_TsCtl, Tsm, 7, 1) + FldFunc(StrTRB_TsCtl, Tsdm, 6, 1) + FldFunc(StrTRB_TsCtl, Pcru, 5, 1) + FldFunc(StrTRB_TsCtl, Vm, 4, 1) + FldFunc(StrTRB_TsCtl, Psm, 3, 1) + FldFunc(StrTRB_TsCtl, Sync, 2, 1) + FldFunc(StrTRB_TsCtl, Ss, 1, 1) + FldFunc(StrTRB_TsCtl, Byps, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsPcrRx0, 0x4, StrTRB_TsPcrRx0, 0x100804) + FldFunc(StrTRB_TsPcrRx0, Rpcrb, 16, 16) + FldFunc(StrTRB_TsPcrRx0, Rpcre, 0, 9) +RegFunc(StreamTsRegsB, 0x100800, TsPcrRx1, 0x8, StrTRB_TsPcrRx1, 0x100808) + FldFunc(StrTRB_TsPcrRx1, Rpcrb, 0, 17) +RegFunc(StreamTsRegsB, 0x100800, TsStcCntr0, 0xC, StrTRB_TsStcCntr0, 0x10080c) + FldFunc(StrTRB_TsStcCntr0, Ppcrb, 16, 16) + FldFunc(StrTRB_TsStcCntr0, Ppcre, 0, 5) +RegFunc(StreamTsRegsB, 0x100800, TsStcCntr1, 0x10, StrTRB_TsStcCntr1, 0x100810) + FldFunc(StrTRB_TsStcCntr1, Ppcrb, 0, 17) +RegFunc(StreamTsRegsB, 0x100800, TsPidVid, 0x14, StrTRB_TsPidVid, 0x100814) + FldFunc(StrTRB_TsPidVid, Siee, 26, 1) + FldFunc(StrTRB_TsPidVid, Sube, 25, 1) + FldFunc(StrTRB_TsPidVid, Priv, 23, 2) + FldFunc(StrTRB_TsPidVid, Typ, 22, 1) + FldFunc(StrTRB_TsPidVid, Piu, 21, 1) + FldFunc(StrTRB_TsPidVid, Si, 13, 8) + FldFunc(StrTRB_TsPidVid, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidPcr, 0x18, StrTRB_TsPidPcr, 0x100818) + FldFunc(StrTRB_TsPidPcr, Piu, 21, 1) + FldFunc(StrTRB_TsPidPcr, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUpdate0, 0x1C, StrTRB_TsUpdate0, 0x10081c) + FldFunc(StrTRB_TsUpdate0, Cpcrb, 16, 16) + FldFunc(StrTRB_TsUpdate0, Cpcre, 0, 9) +RegFunc(StreamTsRegsB, 0x100800, TsUpdate1, 0x20, StrTRB_TsUpdate1, 0x100820) + FldFunc(StrTRB_TsUpdate1, Cpcrb, 0, 17) +RegFunc(StreamTsRegsB, 0x100800, TsRefCnt, 0x24, StrTRB_TsRefCnt, 0x100824) + FldFunc(StrTRB_TsRefCnt, Rfcnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsPidAud0, 0x28, StrTRB_TsPidAud0, 0x100828) + FldFunc(StrTRB_TsPidAud0, Siee, 26, 1) + FldFunc(StrTRB_TsPidAud0, Sube, 25, 1) + FldFunc(StrTRB_TsPidAud0, Priv, 23, 2) + FldFunc(StrTRB_TsPidAud0, Typ, 22, 1) + FldFunc(StrTRB_TsPidAud0, Piu, 21, 1) + FldFunc(StrTRB_TsPidAud0, Si, 13, 8) + FldFunc(StrTRB_TsPidAud0, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidAud1, 0x2C, StrTRB_TsPidAud1, 0x10082c) + FldFunc(StrTRB_TsPidAud1, Siee, 26, 1) + FldFunc(StrTRB_TsPidAud1, Sube, 25, 1) + FldFunc(StrTRB_TsPidAud1, Priv, 23, 2) + FldFunc(StrTRB_TsPidAud1, Typ, 22, 1) + FldFunc(StrTRB_TsPidAud1, Piu, 21, 1) + FldFunc(StrTRB_TsPidAud1, Si, 13, 8) + FldFunc(StrTRB_TsPidAud1, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidAud2, 0x30, StrTRB_TsPidAud2, 0x100830) + FldFunc(StrTRB_TsPidAud2, Siee, 26, 1) + FldFunc(StrTRB_TsPidAud2, Sube, 25, 1) + FldFunc(StrTRB_TsPidAud2, Priv, 23, 2) + FldFunc(StrTRB_TsPidAud2, Typ, 22, 1) + FldFunc(StrTRB_TsPidAud2, Piu, 21, 1) + FldFunc(StrTRB_TsPidAud2, Si, 13, 8) + FldFunc(StrTRB_TsPidAud2, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidUser0, 0x34, StrTRB_TsPidUser0, 0x100834) + FldFunc(StrTRB_TsPidUser0, Piu, 21, 1) + FldFunc(StrTRB_TsPidUser0, Si, 13, 8) + FldFunc(StrTRB_TsPidUser0, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidUser1, 0x38, StrTRB_TsPidUser1, 0x100838) + FldFunc(StrTRB_TsPidUser1, Piu, 21, 1) + FldFunc(StrTRB_TsPidUser1, Si, 13, 8) + FldFunc(StrTRB_TsPidUser1, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidUser2, 0x3C, StrTRB_TsPidUser2, 0x10083c) + FldFunc(StrTRB_TsPidUser2, Piu, 21, 1) + FldFunc(StrTRB_TsPidUser2, Si, 13, 8) + FldFunc(StrTRB_TsPidUser2, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidUser3, 0x40, StrTRB_TsPidUser3, 0x100840) + FldFunc(StrTRB_TsPidUser3, Piu, 21, 1) + FldFunc(StrTRB_TsPidUser3, Si, 13, 8) + FldFunc(StrTRB_TsPidUser3, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPidUser4, 0x44, StrTRB_TsPidUser4, 0x100844) + FldFunc(StrTRB_TsPidUser4, Piu, 21, 1) + FldFunc(StrTRB_TsPidUser4, Si, 13, 8) + FldFunc(StrTRB_TsPidUser4, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPcrChanged, 0x48, StrTRB_TsPcrChanged, 0x100848) + FldFunc(StrTRB_TsPcrChanged, Pcrc, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsFifoStatus, 0x4C, StrTRB_TsFifoStatus, 0x10084c) + FldFunc(StrTRB_TsFifoStatus, Ue, 20, 1) + FldFunc(StrTRB_TsFifoStatus, Uaf, 19, 1) + FldFunc(StrTRB_TsFifoStatus, Dfaf, 16, 1) + FldFunc(StrTRB_TsFifoStatus, Dfe, 15, 1) + FldFunc(StrTRB_TsFifoStatus, Vaf, 13, 1) + FldFunc(StrTRB_TsFifoStatus, De, 12, 1) + FldFunc(StrTRB_TsFifoStatus, Daf, 11, 1) + FldFunc(StrTRB_TsFifoStatus, Pe, 10, 1) + FldFunc(StrTRB_TsFifoStatus, Paf, 9, 1) + FldFunc(StrTRB_TsFifoStatus, Hfo, 8, 1) + FldFunc(StrTRB_TsFifoStatus, Hfhe, 7, 1) + FldFunc(StrTRB_TsFifoStatus, Hfe, 6, 1) + FldFunc(StrTRB_TsFifoStatus, Hfaf, 5, 1) + FldFunc(StrTRB_TsFifoStatus, Efo, 4, 1) + FldFunc(StrTRB_TsFifoStatus, Efhe, 3, 1) + FldFunc(StrTRB_TsFifoStatus, Efe, 2, 1) + FldFunc(StrTRB_TsFifoStatus, Efaf, 1, 1) + FldFunc(StrTRB_TsFifoStatus, Eff, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsSoftReset, 0x50, StrTRB_TsSoftReset, 0x100850) + FldFunc(StrTRB_TsSoftReset, Srst, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsOosCnt, 0x54, StrTRB_TsOosCnt, 0x100854) + FldFunc(StrTRB_TsOosCnt, Oosc, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsDiscontCnt, 0x58, StrTRB_TsDiscontCnt, 0x100858) + FldFunc(StrTRB_TsDiscontCnt, Dc, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsSpmresyncCnt, 0x5C, StrTRB_TsSpmresyncCnt, 0x10085c) + FldFunc(StrTRB_TsSpmresyncCnt, Spmrc, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUserOflwDone, 0x60, StrTRB_TsUserOflwDone, 0x100860) + FldFunc(StrTRB_TsUserOflwDone, U4d, 4, 1) + FldFunc(StrTRB_TsUserOflwDone, U3d, 3, 1) + FldFunc(StrTRB_TsUserOflwDone, U2d, 2, 1) + FldFunc(StrTRB_TsUserOflwDone, U1d, 1, 1) + FldFunc(StrTRB_TsUserOflwDone, U0d, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser0Base, 0x64, StrTRB_TsUser0Base, 0x100864) + FldFunc(StrTRB_TsUser0Base, Base, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser0Rptr, 0x68, StrTRB_TsUser0Rptr, 0x100868) + FldFunc(StrTRB_TsUser0Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser0Wrptr, 0x6C, StrTRB_TsUser0Wrptr, 0x10086c) + FldFunc(StrTRB_TsUser0Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser0Len, 0x70, StrTRB_TsUser0Len, 0x100870) + FldFunc(StrTRB_TsUser0Len, Len, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser0End, 0x74, StrTRB_TsUser0End, 0x100874) + FldFunc(StrTRB_TsUser0End, End, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser0Empty, 0x78, StrTRB_TsUser0Empty, 0x100878) + FldFunc(StrTRB_TsUser0Empty, E, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser1Base, 0x7C, StrTRB_TsUser1Base, 0x10087c) + FldFunc(StrTRB_TsUser1Base, Base, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser1Rptr, 0x80, StrTRB_TsUser1Rptr, 0x100880) + FldFunc(StrTRB_TsUser1Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser1Wrptr, 0x84, StrTRB_TsUser1Wrptr, 0x100884) + FldFunc(StrTRB_TsUser1Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser1Len, 0x88, StrTRB_TsUser1Len, 0x100888) + FldFunc(StrTRB_TsUser1Len, Len, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser1End, 0x8C, StrTRB_TsUser1End, 0x10088c) + FldFunc(StrTRB_TsUser1End, End, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser1Empty, 0x90, StrTRB_TsUser1Empty, 0x100890) + FldFunc(StrTRB_TsUser1Empty, E, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser2Base, 0x94, StrTRB_TsUser2Base, 0x100894) + FldFunc(StrTRB_TsUser2Base, Base, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser2Rptr, 0x98, StrTRB_TsUser2Rptr, 0x100898) + FldFunc(StrTRB_TsUser2Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser2Wrptr, 0x9C, StrTRB_TsUser2Wrptr, 0x10089c) + FldFunc(StrTRB_TsUser2Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser2Len, 0xA0, StrTRB_TsUser2Len, 0x1008a0) + FldFunc(StrTRB_TsUser2Len, Len, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser2End, 0xA4, StrTRB_TsUser2End, 0x1008a4) + FldFunc(StrTRB_TsUser2End, End, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser2Empty, 0xA8, StrTRB_TsUser2Empty, 0x1008a8) + FldFunc(StrTRB_TsUser2Empty, E, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser3Base, 0xAC, StrTRB_TsUser3Base, 0x1008ac) + FldFunc(StrTRB_TsUser3Base, Base, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser3Rptr, 0xB0, StrTRB_TsUser3Rptr, 0x1008b0) + FldFunc(StrTRB_TsUser3Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser3Wrptr, 0xB4, StrTRB_TsUser3Wrptr, 0x1008b4) + FldFunc(StrTRB_TsUser3Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser3Len, 0xB8, StrTRB_TsUser3Len, 0x1008b8) + FldFunc(StrTRB_TsUser3Len, Len, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser3End, 0xBC, StrTRB_TsUser3End, 0x1008bc) + FldFunc(StrTRB_TsUser3End, End, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser3Empty, 0xC0, StrTRB_TsUser3Empty, 0x1008c0) + FldFunc(StrTRB_TsUser3Empty, E, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser4Base, 0xC4, StrTRB_TsUser4Base, 0x1008c4) + FldFunc(StrTRB_TsUser4Base, Base, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser4Rptr, 0xC8, StrTRB_TsUser4Rptr, 0x1008c8) + FldFunc(StrTRB_TsUser4Rptr, Rptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser4Wrptr, 0xCC, StrTRB_TsUser4Wrptr, 0x1008cc) + FldFunc(StrTRB_TsUser4Wrptr, Wrptr, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser4Len, 0xD0, StrTRB_TsUser4Len, 0x1008d0) + FldFunc(StrTRB_TsUser4Len, Len, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser4End, 0xD4, StrTRB_TsUser4End, 0x1008d4) + FldFunc(StrTRB_TsUser4End, End, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUser4Empty, 0xD8, StrTRB_TsUser4Empty, 0x1008d8) + FldFunc(StrTRB_TsUser4Empty, E, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsPktDropCnt, 0xDC, StrTRB_TsPktDropCnt, 0x1008dc) + FldFunc(StrTRB_TsPktDropCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsPktErrCnt, 0xE0, StrTRB_TsPktErrCnt, 0x1008e0) + FldFunc(StrTRB_TsPktErrCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsVidPktCnt, 0xE4, StrTRB_TsVidPktCnt, 0x1008e4) + FldFunc(StrTRB_TsVidPktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsAud0PktCnt, 0xE8, StrTRB_TsAud0PktCnt, 0x1008e8) + FldFunc(StrTRB_TsAud0PktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsAud1PktCnt, 0xEC, StrTRB_TsAud1PktCnt, 0x1008ec) + FldFunc(StrTRB_TsAud1PktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsAud2PktCnt, 0xF0, StrTRB_TsAud2PktCnt, 0x1008f0) + FldFunc(StrTRB_TsAud2PktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUserPktCnt, 0xF4, StrTRB_TsUserPktCnt, 0x1008f4) + FldFunc(StrTRB_TsUserPktCnt, Cnt, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsDescramCtl, 0xF8, StrTRB_TsDescramCtl, 0x1008f8) + FldFunc(StrTRB_TsDescramCtl, Drph, 11, 1) + FldFunc(StrTRB_TsDescramCtl, Pkt, 10, 1) + FldFunc(StrTRB_TsDescramCtl, Est, 8, 2) + FldFunc(StrTRB_TsDescramCtl, Ost, 6, 2) + FldFunc(StrTRB_TsDescramCtl, Usc, 5, 1) + FldFunc(StrTRB_TsDescramCtl, Scctl, 4, 1) + FldFunc(StrTRB_TsDescramCtl, Scmod, 3, 1) + FldFunc(StrTRB_TsDescramCtl, Trmtyp, 2, 1) + FldFunc(StrTRB_TsDescramCtl, Type, 1, 1) + FldFunc(StrTRB_TsDescramCtl, En, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsKeyEven0, 0xFC, StrTRB_TsKeyEven0, 0x1008fc) + FldFunc(StrTRB_TsKeyEven0, Key310, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyEven1, 0x100, StrTRB_TsKeyEven1, 0x100900) + FldFunc(StrTRB_TsKeyEven1, Key6332, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyEven2, 0x104, StrTRB_TsKeyEven2, 0x100904) + FldFunc(StrTRB_TsKeyEven2, Key9564, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyEven3, 0x108, StrTRB_TsKeyEven3, 0x100908) + FldFunc(StrTRB_TsKeyEven3, Key12796, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyOdd0, 0x10C, StrTRB_TsKeyOdd0, 0x10090c) + FldFunc(StrTRB_TsKeyOdd0, Key310, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyOdd1, 0x110, StrTRB_TsKeyOdd1, 0x100910) + FldFunc(StrTRB_TsKeyOdd1, Key6332, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyOdd2, 0x114, StrTRB_TsKeyOdd2, 0x100914) + FldFunc(StrTRB_TsKeyOdd2, Key9564, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsKeyOdd3, 0x118, StrTRB_TsKeyOdd3, 0x100918) + FldFunc(StrTRB_TsKeyOdd3, Key12796, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsStcIsCrap, 0x11C, StrTRB_TsStcIsCrap, 0x10091c) + FldFunc(StrTRB_TsStcIsCrap, Typ, 1, 1) + FldFunc(StrTRB_TsStcIsCrap, Sic, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsTsdAdconfig, 0x120, StrTRB_TsTsdAdconfig, 0x100920) + FldFunc(StrTRB_TsTsdAdconfig, Rs, 12, 1) + FldFunc(StrTRB_TsTsdAdconfig, Pnty, 8, 4) + FldFunc(StrTRB_TsTsdAdconfig, Ost, 4, 4) + FldFunc(StrTRB_TsTsdAdconfig, Ist, 0, 4) +RegFunc(StreamTsRegsB, 0x100800, TsStcref900, 0x124, StrTRB_TsStcref900, 0x100924) + FldFunc(StrTRB_TsStcref900, Ppcrb, 31, 1) + FldFunc(StrTRB_TsStcref900, Ppcre, 0, 9) +RegFunc(StreamTsRegsB, 0x100800, TsStcref901, 0x128, StrTRB_TsStcref901, 0x100928) + FldFunc(StrTRB_TsStcref901, Ppcrb, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsRtsUpdate, 0x12C, StrTRB_TsRtsUpdate, 0x10092c) + FldFunc(StrTRB_TsRtsUpdate, Rtsu, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsStcref27, 0x130, StrTRB_TsStcref27, 0x100930) + FldFunc(StrTRB_TsStcref27, Stc27, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsRtsChanged, 0x134, StrTRB_TsRtsChanged, 0x100934) + FldFunc(StrTRB_TsRtsChanged, Rc, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsRtsRx, 0x138, StrTRB_TsRtsRx, 0x100938) + FldFunc(StrTRB_TsRtsRx, Rtsrx, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsRefcntSave, 0x13C, StrTRB_TsRefcntSave, 0x10093c) + FldFunc(StrTRB_TsRefcntSave, Ref, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsTsmConfig, 0x140, StrTRB_TsTsmConfig, 0x100940) + FldFunc(StrTRB_TsTsmConfig, Sras, 28, 1) + FldFunc(StrTRB_TsTsmConfig, Zvrc, 27, 1) + FldFunc(StrTRB_TsTsmConfig, Cs27, 26, 1) + FldFunc(StrTRB_TsTsmConfig, Cs90, 25, 1) + FldFunc(StrTRB_TsTsmConfig, Ppu, 24, 1) + FldFunc(StrTRB_TsTsmConfig, Spi, 23, 1) + FldFunc(StrTRB_TsTsmConfig, Un, 2, 1) + FldFunc(StrTRB_TsTsmConfig, Udm, 1, 1) + FldFunc(StrTRB_TsTsmConfig, Os, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsPcrTrigger, 0x144, StrTRB_TsPcrTrigger, 0x100944) + FldFunc(StrTRB_TsPcrTrigger, Pt, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsIntStat, 0x148, StrTRB_TsIntStat, 0x100948) + FldFunc(StrTRB_TsIntStat, U4o, 25, 1) + FldFunc(StrTRB_TsIntStat, U3o, 24, 1) + FldFunc(StrTRB_TsIntStat, U2o, 23, 1) + FldFunc(StrTRB_TsIntStat, U1o, 22, 1) + FldFunc(StrTRB_TsIntStat, U0o, 21, 1) + FldFunc(StrTRB_TsIntStat, U4sp, 20, 1) + FldFunc(StrTRB_TsIntStat, U3sp, 19, 1) + FldFunc(StrTRB_TsIntStat, U2sp, 18, 1) + FldFunc(StrTRB_TsIntStat, U1sp, 17, 1) + FldFunc(StrTRB_TsIntStat, U0sp, 16, 1) + FldFunc(StrTRB_TsIntStat, Psp, 15, 1) + FldFunc(StrTRB_TsIntStat, A2sp, 14, 1) + FldFunc(StrTRB_TsIntStat, A1sp, 13, 1) + FldFunc(StrTRB_TsIntStat, A0sp, 12, 1) + FldFunc(StrTRB_TsIntStat, Vsp, 11, 1) + FldFunc(StrTRB_TsIntStat, Va, 10, 1) + FldFunc(StrTRB_TsIntStat, I2o, 9, 1) + FldFunc(StrTRB_TsIntStat, I1o, 8, 1) + FldFunc(StrTRB_TsIntStat, I0o, 7, 1) + FldFunc(StrTRB_TsIntStat, C2o, 6, 1) + FldFunc(StrTRB_TsIntStat, C1o, 5, 1) + FldFunc(StrTRB_TsIntStat, C0o, 4, 1) + FldFunc(StrTRB_TsIntStat, Uf, 3, 1) + FldFunc(StrTRB_TsIntStat, Ho, 1, 1) + FldFunc(StrTRB_TsIntStat, Eo, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsIntMask, 0x14C, StrTRB_TsIntMask, 0x10094c) + FldFunc(StrTRB_TsIntMask, U4o, 25, 1) + FldFunc(StrTRB_TsIntMask, U3o, 24, 1) + FldFunc(StrTRB_TsIntMask, U2o, 23, 1) + FldFunc(StrTRB_TsIntMask, U1o, 22, 1) + FldFunc(StrTRB_TsIntMask, U0o, 21, 1) + FldFunc(StrTRB_TsIntMask, U4sp, 20, 1) + FldFunc(StrTRB_TsIntMask, U3sp, 19, 1) + FldFunc(StrTRB_TsIntMask, U2sp, 18, 1) + FldFunc(StrTRB_TsIntMask, U1sp, 17, 1) + FldFunc(StrTRB_TsIntMask, U0sp, 16, 1) + FldFunc(StrTRB_TsIntMask, Psp, 15, 1) + FldFunc(StrTRB_TsIntMask, A2sp, 14, 1) + FldFunc(StrTRB_TsIntMask, A1sp, 13, 1) + FldFunc(StrTRB_TsIntMask, A0sp, 12, 1) + FldFunc(StrTRB_TsIntMask, Vsp, 11, 1) + FldFunc(StrTRB_TsIntMask, Eva, 10, 1) + FldFunc(StrTRB_TsIntMask, Ei2o, 9, 1) + FldFunc(StrTRB_TsIntMask, Ei1o, 8, 1) + FldFunc(StrTRB_TsIntMask, Ei0o, 7, 1) + FldFunc(StrTRB_TsIntMask, Ec2o, 6, 1) + FldFunc(StrTRB_TsIntMask, Ec1o, 5, 1) + FldFunc(StrTRB_TsIntMask, Ec0o, 4, 1) + FldFunc(StrTRB_TsIntMask, Euf, 3, 1) + FldFunc(StrTRB_TsIntMask, Eho, 1, 1) + FldFunc(StrTRB_TsIntMask, Eeo, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsBtpCtl, 0x150, StrTRB_TsBtpCtl, 0x100950) + FldFunc(StrTRB_TsBtpCtl, Ebpc, 1, 1) + FldFunc(StrTRB_TsBtpCtl, Ebo, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsTsfifoByteCnt, 0x154, StrTRB_TsTsfifoByteCnt, 0x100954) + FldFunc(StrTRB_TsTsfifoByteCnt, Tfbc, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsPktbuffByteCnt, 0x158, StrTRB_TsPktbuffByteCnt, 0x100958) + FldFunc(StrTRB_TsPktbuffByteCnt, Pbc, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsSpliceEn, 0x15C, StrTRB_TsSpliceEn, 0x10095c) + FldFunc(StrTRB_TsSpliceEn, A2se, 13, 1) + FldFunc(StrTRB_TsSpliceEn, A1se, 12, 1) + FldFunc(StrTRB_TsSpliceEn, A0se, 11, 1) + FldFunc(StrTRB_TsSpliceEn, Vse, 10, 1) + FldFunc(StrTRB_TsSpliceEn, U4en, 9, 1) + FldFunc(StrTRB_TsSpliceEn, U3en, 8, 1) + FldFunc(StrTRB_TsSpliceEn, U2en, 7, 1) + FldFunc(StrTRB_TsSpliceEn, U1en, 6, 1) + FldFunc(StrTRB_TsSpliceEn, U0en, 5, 1) + FldFunc(StrTRB_TsSpliceEn, Pen, 4, 1) + FldFunc(StrTRB_TsSpliceEn, A2en, 3, 1) + FldFunc(StrTRB_TsSpliceEn, A1en, 2, 1) + FldFunc(StrTRB_TsSpliceEn, A0en, 1, 1) + FldFunc(StrTRB_TsSpliceEn, Ven, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsVidspliceBuf, 0x160, StrTRB_TsVidspliceBuf, 0x100960) + FldFunc(StrTRB_TsVidspliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsVidspliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsVidspliceBuf, Se, 13, 2) + FldFunc(StrTRB_TsVidspliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsAud0spliceBuf, 0x164, StrTRB_TsAud0spliceBuf, 0x100964) + FldFunc(StrTRB_TsAud0spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsAud0spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsAud0spliceBuf, Se, 13, 2) + FldFunc(StrTRB_TsAud0spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsAud1spliceBuf, 0x168, StrTRB_TsAud1spliceBuf, 0x100968) + FldFunc(StrTRB_TsAud1spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsAud1spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsAud1spliceBuf, Se, 13, 2) + FldFunc(StrTRB_TsAud1spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsAud2spliceBuf, 0x16C, StrTRB_TsAud2spliceBuf, 0x10096c) + FldFunc(StrTRB_TsAud2spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsAud2spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsAud2spliceBuf, Se, 13, 2) + FldFunc(StrTRB_TsAud2spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsPcrspliceBuf, 0x170, StrTRB_TsPcrspliceBuf, 0x100970) + FldFunc(StrTRB_TsPcrspliceBuf, Ne, 14, 1) + FldFunc(StrTRB_TsPcrspliceBuf, Full, 13, 1) + FldFunc(StrTRB_TsPcrspliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUnmarkedThresh, 0x174, StrTRB_TsUnmarkedThresh, 0x100974) + FldFunc(StrTRB_TsUnmarkedThresh, Ut, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsVidspliceCnt, 0x178, StrTRB_TsVidspliceCnt, 0x100978) + FldFunc(StrTRB_TsVidspliceCnt, Act, 8, 1) + FldFunc(StrTRB_TsVidspliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsAud0spliceCnt, 0x17C, StrTRB_TsAud0spliceCnt, 0x10097c) + FldFunc(StrTRB_TsAud0spliceCnt, Act, 8, 1) + FldFunc(StrTRB_TsAud0spliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsAud1spliceCnt, 0x180, StrTRB_TsAud1spliceCnt, 0x100980) + FldFunc(StrTRB_TsAud1spliceCnt, Act, 8, 1) + FldFunc(StrTRB_TsAud1spliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsAud2spliceCnt, 0x184, StrTRB_TsAud2spliceCnt, 0x100984) + FldFunc(StrTRB_TsAud2spliceCnt, Act, 8, 1) + FldFunc(StrTRB_TsAud2spliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPcrspliceCnt, 0x188, StrTRB_TsPcrspliceCnt, 0x100988) + FldFunc(StrTRB_TsPcrspliceCnt, Act, 8, 1) + FldFunc(StrTRB_TsPcrspliceCnt, Cnt, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesStrmidRange, 0x18C, StrTRB_TsPesStrmidRange, 0x10098c) + FldFunc(StrTRB_TsPesStrmidRange, Hi, 8, 8) + FldFunc(StrTRB_TsPesStrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsVidStrmidRange, 0x190, StrTRB_TsVidStrmidRange, 0x100990) + FldFunc(StrTRB_TsVidStrmidRange, Hi, 8, 8) + FldFunc(StrTRB_TsVidStrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsAud0StrmidRange, 0x194, StrTRB_TsAud0StrmidRange, 0x100994) + FldFunc(StrTRB_TsAud0StrmidRange, Hi, 8, 8) + FldFunc(StrTRB_TsAud0StrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsAud1StrmidRange, 0x198, StrTRB_TsAud1StrmidRange, 0x100998) + FldFunc(StrTRB_TsAud1StrmidRange, Hi, 8, 8) + FldFunc(StrTRB_TsAud1StrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsAud2StrmidRange, 0x19C, StrTRB_TsAud2StrmidRange, 0x10099c) + FldFunc(StrTRB_TsAud2StrmidRange, Hi, 8, 8) + FldFunc(StrTRB_TsAud2StrmidRange, Lo, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesNoext0, 0x1A0, StrTRB_TsPesNoext0, 0x1009a0) + FldFunc(StrTRB_TsPesNoext0, En2, 26, 1) + FldFunc(StrTRB_TsPesNoext0, En1, 25, 1) + FldFunc(StrTRB_TsPesNoext0, En0, 24, 1) + FldFunc(StrTRB_TsPesNoext0, Ext2, 16, 8) + FldFunc(StrTRB_TsPesNoext0, Ext1, 8, 8) + FldFunc(StrTRB_TsPesNoext0, Ext0, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesNoext1, 0x1A4, StrTRB_TsPesNoext1, 0x1009a4) + FldFunc(StrTRB_TsPesNoext1, En2, 26, 1) + FldFunc(StrTRB_TsPesNoext1, En1, 25, 1) + FldFunc(StrTRB_TsPesNoext1, En0, 24, 1) + FldFunc(StrTRB_TsPesNoext1, Ext2, 16, 8) + FldFunc(StrTRB_TsPesNoext1, Ext1, 8, 8) + FldFunc(StrTRB_TsPesNoext1, Ext0, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesNoext2, 0x1A8, StrTRB_TsPesNoext2, 0x1009a8) + FldFunc(StrTRB_TsPesNoext2, En2, 26, 1) + FldFunc(StrTRB_TsPesNoext2, En1, 25, 1) + FldFunc(StrTRB_TsPesNoext2, En0, 24, 1) + FldFunc(StrTRB_TsPesNoext2, Ext2, 16, 8) + FldFunc(StrTRB_TsPesNoext2, Ext1, 8, 8) + FldFunc(StrTRB_TsPesNoext2, Ext0, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesNoext3, 0x1AC, StrTRB_TsPesNoext3, 0x1009ac) + FldFunc(StrTRB_TsPesNoext3, En2, 26, 1) + FldFunc(StrTRB_TsPesNoext3, En1, 25, 1) + FldFunc(StrTRB_TsPesNoext3, En0, 24, 1) + FldFunc(StrTRB_TsPesNoext3, Ext2, 16, 8) + FldFunc(StrTRB_TsPesNoext3, Ext1, 8, 8) + FldFunc(StrTRB_TsPesNoext3, Ext0, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesNoext4, 0x1B0, StrTRB_TsPesNoext4, 0x1009b0) + FldFunc(StrTRB_TsPesNoext4, En2, 26, 1) + FldFunc(StrTRB_TsPesNoext4, En1, 25, 1) + FldFunc(StrTRB_TsPesNoext4, En0, 24, 1) + FldFunc(StrTRB_TsPesNoext4, Ext2, 16, 8) + FldFunc(StrTRB_TsPesNoext4, Ext1, 8, 8) + FldFunc(StrTRB_TsPesNoext4, Ext0, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsPesNoext5, 0x1B4, StrTRB_TsPesNoext5, 0x1009b4) + FldFunc(StrTRB_TsPesNoext5, En2, 26, 1) + FldFunc(StrTRB_TsPesNoext5, En1, 25, 1) + FldFunc(StrTRB_TsPesNoext5, En0, 24, 1) + FldFunc(StrTRB_TsPesNoext5, Ext2, 16, 8) + FldFunc(StrTRB_TsPesNoext5, Ext1, 8, 8) + FldFunc(StrTRB_TsPesNoext5, Ext0, 0, 8) +RegFunc(StreamTsRegsB, 0x100800, TsUser0spliceCnt, 0x1B8, StrTRB_TsUser0spliceCnt, 0x1009b8) + FldFunc(StrTRB_TsUser0spliceCnt, Cnt, 1, 8) + FldFunc(StrTRB_TsUser0spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser1spliceCnt, 0x1BC, StrTRB_TsUser1spliceCnt, 0x1009bc) + FldFunc(StrTRB_TsUser1spliceCnt, Cnt, 1, 8) + FldFunc(StrTRB_TsUser1spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser2spliceCnt, 0x1C0, StrTRB_TsUser2spliceCnt, 0x1009c0) + FldFunc(StrTRB_TsUser2spliceCnt, Cnt, 1, 8) + FldFunc(StrTRB_TsUser2spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser3spliceCnt, 0x1C4, StrTRB_TsUser3spliceCnt, 0x1009c4) + FldFunc(StrTRB_TsUser3spliceCnt, Cnt, 1, 8) + FldFunc(StrTRB_TsUser3spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser4spliceCnt, 0x1C8, StrTRB_TsUser4spliceCnt, 0x1009c8) + FldFunc(StrTRB_TsUser4spliceCnt, Cnt, 1, 8) + FldFunc(StrTRB_TsUser4spliceCnt, Act, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsUser0spliceBuf, 0x1CC, StrTRB_TsUser0spliceBuf, 0x1009cc) + FldFunc(StrTRB_TsUser0spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsUser0spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsUser0spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUser1spliceBuf, 0x1D0, StrTRB_TsUser1spliceBuf, 0x1009d0) + FldFunc(StrTRB_TsUser1spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsUser1spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsUser1spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUser2spliceBuf, 0x1D4, StrTRB_TsUser2spliceBuf, 0x1009d4) + FldFunc(StrTRB_TsUser2spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsUser2spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsUser2spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUser3spliceBuf, 0x1D8, StrTRB_TsUser3spliceBuf, 0x1009d8) + FldFunc(StrTRB_TsUser3spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsUser3spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsUser3spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUser4spliceBuf, 0x1DC, StrTRB_TsUser4spliceBuf, 0x1009dc) + FldFunc(StrTRB_TsUser4spliceBuf, Ne, 16, 1) + FldFunc(StrTRB_TsUser4spliceBuf, Full, 15, 1) + FldFunc(StrTRB_TsUser4spliceBuf, Pid, 0, 13) +RegFunc(StreamTsRegsB, 0x100800, TsUpdWaiting, 0x1E0, StrTRB_TsUpdWaiting, 0x1009e0) + FldFunc(StrTRB_TsUpdWaiting, Ruw, 1, 1) + FldFunc(StrTRB_TsUpdWaiting, Puw, 0, 1) +RegFunc(StreamTsRegsB, 0x100800, TsAud0Extid, 0x1E4, StrTRB_TsAud0Extid, 0x1009e4) + FldFunc(StrTRB_TsAud0Extid, Eidv, 15, 1) + FldFunc(StrTRB_TsAud0Extid, Eid, 8, 7) + FldFunc(StrTRB_TsAud0Extid, Cidv, 7, 1) + FldFunc(StrTRB_TsAud0Extid, Cid, 0, 7) +RegFunc(StreamTsRegsB, 0x100800, TsAud1Extid, 0x1E8, StrTRB_TsAud1Extid, 0x1009e8) + FldFunc(StrTRB_TsAud1Extid, Eidv, 15, 1) + FldFunc(StrTRB_TsAud1Extid, Eid, 8, 7) + FldFunc(StrTRB_TsAud1Extid, Cidv, 7, 1) + FldFunc(StrTRB_TsAud1Extid, Cid, 0, 7) +RegFunc(StreamTsRegsB, 0x100800, TsAud2Extid, 0x1EC, StrTRB_TsAud2Extid, 0x1009ec) + FldFunc(StrTRB_TsAud2Extid, Eidv, 15, 1) + FldFunc(StrTRB_TsAud2Extid, Eid, 8, 7) + FldFunc(StrTRB_TsAud2Extid, Cidv, 7, 1) + FldFunc(StrTRB_TsAud2Extid, Cid, 0, 7) +RegFunc(StreamTsRegsB, 0x100800, TsPcrOffset, 0x1F0, StrTRB_TsPcrOffset, 0x1009f0) + FldFunc(StrTRB_TsPcrOffset, Pcro, 0, 32) +RegFunc(StreamTsRegsB, 0x100800, TsUsePusi, 0x1F4, StrTRB_TsUsePusi, 0x1009f4) + FldFunc(StrTRB_TsUsePusi, A2up, 3, 1) + FldFunc(StrTRB_TsUsePusi, A1up, 2, 1) + FldFunc(StrTRB_TsUsePusi, A0up, 1, 1) + FldFunc(StrTRB_TsUsePusi, Vup, 0, 1) + +RegAreaFunc(StreamMiscBase, 0x100300, 0x1003FE) +RegFunc(StreamMisc, 0x100300, UartSelectA, 0x0, StrMc_UartSelectA, 0x100300) + FldFunc(StrMc_UartSelectA, Us, 0, 4) +RegFunc(StreamMisc, 0x100300, UartSelectB, 0x4, StrMc_UartSelectB, 0x100304) + FldFunc(StrMc_UartSelectB, Us, 0, 4) +RegFunc(StreamMisc, 0x100300, CsSelect, 0x8, StrMc_CsSelect, 0x100308) + FldFunc(StrMc_CsSelect, Sel, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAudcdb0Base, 0xC, StrMc_TsAudcdb0Base, 0x10030c) + FldFunc(StrMc_TsAudcdb0Base, Base, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAudcdb0End, 0x10, StrMc_TsAudcdb0End, 0x100310) + FldFunc(StrMc_TsAudcdb0End, End, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAudcdb0Wrptr, 0x14, StrMc_TsAudcdb0Wrptr, 0x100314) + FldFunc(StrMc_TsAudcdb0Wrptr, Wrptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb0Rdptr, 0x18, StrMc_TsAudcdb0Rdptr, 0x100318) + FldFunc(StrMc_TsAudcdb0Rdptr, Rdptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb0Empty, 0x1C, StrMc_TsAudcdb0Empty, 0x10031c) + FldFunc(StrMc_TsAudcdb0Empty, Em, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAudcdb0WrapPtr, 0x20, StrMc_TsAudcdb0WrapPtr, 0x100320) + FldFunc(StrMc_TsAudcdb0WrapPtr, Wrap, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb0Base, 0x24, StrMc_TsAuditb0Base, 0x100324) + FldFunc(StrMc_TsAuditb0Base, Base, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAuditb0End, 0x28, StrMc_TsAuditb0End, 0x100328) + FldFunc(StrMc_TsAuditb0End, End, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAuditb0Wrptr, 0x2C, StrMc_TsAuditb0Wrptr, 0x10032c) + FldFunc(StrMc_TsAuditb0Wrptr, Wrptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb0Rdptr, 0x30, StrMc_TsAuditb0Rdptr, 0x100330) + FldFunc(StrMc_TsAuditb0Rdptr, Rdptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb0Empty, 0x34, StrMc_TsAuditb0Empty, 0x100334) + FldFunc(StrMc_TsAuditb0Empty, Em, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAuditb0WrapPtr, 0x38, StrMc_TsAuditb0WrapPtr, 0x100338) + FldFunc(StrMc_TsAuditb0WrapPtr, Wrap, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb1Base, 0x3C, StrMc_TsAudcdb1Base, 0x10033c) + FldFunc(StrMc_TsAudcdb1Base, Base, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAudcdb1End, 0x40, StrMc_TsAudcdb1End, 0x100340) + FldFunc(StrMc_TsAudcdb1End, End, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAudcdb1Wrptr, 0x44, StrMc_TsAudcdb1Wrptr, 0x100344) + FldFunc(StrMc_TsAudcdb1Wrptr, Wrptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb1Rdptr, 0x48, StrMc_TsAudcdb1Rdptr, 0x100348) + FldFunc(StrMc_TsAudcdb1Rdptr, Rdptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb1Empty, 0x4C, StrMc_TsAudcdb1Empty, 0x10034c) + FldFunc(StrMc_TsAudcdb1Empty, Em, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAudcdb1WrapPtr, 0x50, StrMc_TsAudcdb1WrapPtr, 0x100350) + FldFunc(StrMc_TsAudcdb1WrapPtr, Wrap, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb1Base, 0x54, StrMc_TsAuditb1Base, 0x100354) + FldFunc(StrMc_TsAuditb1Base, Base, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAuditb1End, 0x58, StrMc_TsAuditb1End, 0x100358) + FldFunc(StrMc_TsAuditb1End, End, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAuditb1Wrptr, 0x5C, StrMc_TsAuditb1Wrptr, 0x10035c) + FldFunc(StrMc_TsAuditb1Wrptr, Wrptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb1Rdptr, 0x60, StrMc_TsAuditb1Rdptr, 0x100360) + FldFunc(StrMc_TsAuditb1Rdptr, Rdptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb1Empty, 0x64, StrMc_TsAuditb1Empty, 0x100364) + FldFunc(StrMc_TsAuditb1Empty, Em, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAuditb1WrapPtr, 0x68, StrMc_TsAuditb1WrapPtr, 0x100368) + FldFunc(StrMc_TsAuditb1WrapPtr, Wrap, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb2Base, 0x6C, StrMc_TsAudcdb2Base, 0x10036c) + FldFunc(StrMc_TsAudcdb2Base, Base, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAudcdb2End, 0x70, StrMc_TsAudcdb2End, 0x100370) + FldFunc(StrMc_TsAudcdb2End, End, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAudcdb2Wrptr, 0x74, StrMc_TsAudcdb2Wrptr, 0x100374) + FldFunc(StrMc_TsAudcdb2Wrptr, Wrptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb2Rdptr, 0x78, StrMc_TsAudcdb2Rdptr, 0x100378) + FldFunc(StrMc_TsAudcdb2Rdptr, Rdptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAudcdb2Empty, 0x7C, StrMc_TsAudcdb2Empty, 0x10037c) + FldFunc(StrMc_TsAudcdb2Empty, Em, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAudcdb2WrapPtr, 0x80, StrMc_TsAudcdb2WrapPtr, 0x100380) + FldFunc(StrMc_TsAudcdb2WrapPtr, Wrap, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb2Base, 0x84, StrMc_TsAuditb2Base, 0x100384) + FldFunc(StrMc_TsAuditb2Base, Base, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAuditb2End, 0x88, StrMc_TsAuditb2End, 0x100388) + FldFunc(StrMc_TsAuditb2End, End, 6, 26) +RegFunc(StreamMisc, 0x100300, TsAuditb2Wrptr, 0x8C, StrMc_TsAuditb2Wrptr, 0x10038c) + FldFunc(StrMc_TsAuditb2Wrptr, Wrptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb2Rdptr, 0x90, StrMc_TsAuditb2Rdptr, 0x100390) + FldFunc(StrMc_TsAuditb2Rdptr, Rdptr, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAuditb2Empty, 0x94, StrMc_TsAuditb2Empty, 0x100394) + FldFunc(StrMc_TsAuditb2Empty, Em, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAuditb2WrapPtr, 0x98, StrMc_TsAuditb2WrapPtr, 0x100398) + FldFunc(StrMc_TsAuditb2WrapPtr, Wrap, 0, 32) +RegFunc(StreamMisc, 0x100300, TsAud0SoftReset, 0x9C, StrMc_TsAud0SoftReset, 0x10039c) + FldFunc(StrMc_TsAud0SoftReset, Sr, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAud1SoftReset, 0xA0, StrMc_TsAud1SoftReset, 0x1003a0) + FldFunc(StrMc_TsAud1SoftReset, Sr, 0, 1) +RegFunc(StreamMisc, 0x100300, TsAud2SoftReset, 0xA4, StrMc_TsAud2SoftReset, 0x1003a4) + FldFunc(StrMc_TsAud2SoftReset, Sr, 0, 1) +RegFunc(StreamMisc, 0x100300, TsCdbitbDtaif0, 0xA8, StrMc_TsCdbitbDtaif0, 0x1003a8) + FldFunc(StrMc_TsCdbitbDtaif0, Dt, 0, 1) +RegFunc(StreamMisc, 0x100300, TsCdbitbDtaif1, 0xAC, StrMc_TsCdbitbDtaif1, 0x1003ac) + FldFunc(StrMc_TsCdbitbDtaif1, Dt, 0, 1) +RegFunc(StreamMisc, 0x100300, TsCdbitbDtaif2, 0xB0, StrMc_TsCdbitbDtaif2, 0x1003b0) + FldFunc(StrMc_TsCdbitbDtaif2, Dt, 0, 1) +RegFunc(StreamMisc, 0x100300, TsCdbitbSel0, 0xB4, StrMc_TsCdbitbSel0, 0x1003b4) + FldFunc(StrMc_TsCdbitbSel0, Sel, 0, 1) +RegFunc(StreamMisc, 0x100300, TsCdbitbSel1, 0xB8, StrMc_TsCdbitbSel1, 0x1003b8) + FldFunc(StrMc_TsCdbitbSel1, Sel, 0, 2) +RegFunc(StreamMisc, 0x100300, TsCdbitbSel2, 0xBC, StrMc_TsCdbitbSel2, 0x1003bc) + FldFunc(StrMc_TsCdbitbSel2, Sel, 0, 1) +RegFunc(StreamMisc, 0x100300, TsCdbitbThresh, 0xC0, StrMc_TsCdbitbThresh, 0x1003c0) + FldFunc(StrMc_TsCdbitbThresh, Thr, 0, 4) + +RegAreaFunc(GpioBase, 0x103000, 0x1031FF) +RegFunc(Gpio, 0x103000, GpioCtl, 0x0, Gpio_GpioCtl, 0x103000) + FldFunc(Gpio_GpioCtl, Rddata, 16, 8) + FldFunc(Gpio_GpioCtl, Gpioen, 8, 8) + FldFunc(Gpio_GpioCtl, Wrdata, 0, 8) +RegFunc(Gpio, 0x103000, GpioChipRev, 0x4, Gpio_GpioChipRev, 0x103004) +RegFunc(Gpio, 0x103000, GpioPinMon0, 0x8, Gpio_GpioPinMon0, 0x103008) +RegFunc(Gpio, 0x103000, GpioPinMon1, 0xC, Gpio_GpioPinMon1, 0x10300c) +RegFunc(Gpio, 0x103000, GpioPinMon2, 0x10, Gpio_GpioPinMon2, 0x103010) +RegFunc(Gpio, 0x103000, GpioPinMon3, 0x14, Gpio_GpioPinMon3, 0x103014) +RegFunc(Gpio, 0x103000, GpioPinMonSelect, 0x18, Gpio_GpioPinMonSelect, 0x103018) + FldFunc(Gpio_GpioPinMonSelect, Block, 8, 3) + FldFunc(Gpio_GpioPinMonSelect, Group, 0, 8) +RegFunc(Gpio, 0x103000, GpioIntCtl, 0x1C, Gpio_GpioIntCtl, 0x10301c) + FldFunc(Gpio_GpioIntCtl, LoMsk, 8, 8) + FldFunc(Gpio_GpioIntCtl, HiMsk, 0, 8) + +RegAreaFunc(StreamVcxoBase, 0x100100, 0x1002FF) +RegFunc(StreamVcxo, 0x100100, VcxoCtrlA, 0x0, StrVo_VcxoCtrlA, 0x100100) + FldFunc(StrVo_VcxoCtrlA, Dutycycle, 0, 16) +RegFunc(StreamVcxo, 0x100100, VcxoCtrlB, 0x4, StrVo_VcxoCtrlB, 0x100104) + FldFunc(StrVo_VcxoCtrlB, Dutycycle, 0, 16) + +RegAreaFunc(StreamCpuregsBase, 0x100F00, 0x100F7F) +RegFunc(StreamCpuregs, 0x100F00, RegHst2cpuMbx, 0x0, StrCs_RegHst2cpuMbx, 0x100f00) + FldFunc(StrCs_RegHst2cpuMbx, Value, 0, 32) +RegFunc(StreamCpuregs, 0x100F00, RegCpu2hstMbx, 0x4, StrCs_RegCpu2hstMbx, 0x100f04) + FldFunc(StrCs_RegCpu2hstMbx, Value, 0, 32) +RegFunc(StreamCpuregs, 0x100F00, RegMbxStat, 0x8, StrCs_RegMbxStat, 0x100f08) + FldFunc(StrCs_RegMbxStat, C2h, 1, 1) + FldFunc(StrCs_RegMbxStat, H2c, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIntBase, 0xC, StrCs_RegCpuIntBase, 0x100f0c) + FldFunc(StrCs_RegCpuIntBase, Addr, 8, 24) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIntEna, 0x10, StrCs_RegCpuIntEna, 0x100f10) + FldFunc(StrCs_RegCpuIntEna, Mbx, 31, 1) + FldFunc(StrCs_RegCpuIntEna, Com7, 23, 1) + FldFunc(StrCs_RegCpuIntEna, Com6, 22, 1) + FldFunc(StrCs_RegCpuIntEna, Com5, 21, 1) + FldFunc(StrCs_RegCpuIntEna, Com4, 20, 1) + FldFunc(StrCs_RegCpuIntEna, Com3, 19, 1) + FldFunc(StrCs_RegCpuIntEna, Com2, 18, 1) + FldFunc(StrCs_RegCpuIntEna, Com1, 17, 1) + FldFunc(StrCs_RegCpuIntEna, Com0, 16, 1) + FldFunc(StrCs_RegCpuIntEna, Hw7, 15, 1) + FldFunc(StrCs_RegCpuIntEna, Hw6, 14, 1) + FldFunc(StrCs_RegCpuIntEna, Hw5, 13, 1) + FldFunc(StrCs_RegCpuIntEna, Hw4, 12, 1) + FldFunc(StrCs_RegCpuIntEna, Hw3, 11, 1) + FldFunc(StrCs_RegCpuIntEna, Hw2, 10, 1) + FldFunc(StrCs_RegCpuIntEna, Hw1, 9, 1) + FldFunc(StrCs_RegCpuIntEna, Hw0, 8, 1) + FldFunc(StrCs_RegCpuIntEna, Db7, 7, 1) + FldFunc(StrCs_RegCpuIntEna, Db6, 6, 1) + FldFunc(StrCs_RegCpuIntEna, Db5, 5, 1) + FldFunc(StrCs_RegCpuIntEna, Db4, 4, 1) + FldFunc(StrCs_RegCpuIntEna, Db3, 3, 1) + FldFunc(StrCs_RegCpuIntEna, Db2, 2, 1) + FldFunc(StrCs_RegCpuIntEna, Db1, 1, 1) + FldFunc(StrCs_RegCpuIntEna, Db0, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, StreamCpuIntEna, 0x10, StrCs_StreamCpuIntEna, 0x100f10) + FldFunc(StrCs_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(StrCs_StreamCpuIntEna, Dec, 18, 1) + FldFunc(StrCs_StreamCpuIntEna, Aud, 17, 1) + FldFunc(StrCs_StreamCpuIntEna, M2m, 15, 1) + FldFunc(StrCs_StreamCpuIntEna, Pci, 14, 1) + FldFunc(StrCs_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(StrCs_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(StrCs_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(StrCs_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(StrCs_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(StrCs_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(StrCs_StreamCpuIntEna, Rb, 1, 1) + FldFunc(StrCs_StreamCpuIntEna, Sd, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, Dec0CpuIntEna, 0x10, StrCs_Dec0CpuIntEna, 0x100f10) + FldFunc(StrCs_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(StrCs_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(StrCs_Dec0CpuIntEna, Si, 8, 1) + FldFunc(StrCs_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(StrCs_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, Dec1CpuIntEna, 0x10, StrCs_Dec1CpuIntEna, 0x100f10) + FldFunc(StrCs_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(StrCs_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(StrCs_Dec1CpuIntEna, Si, 8, 1) + FldFunc(StrCs_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(StrCs_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIntStat, 0x14, StrCs_RegCpuIntStat, 0x100f14) + FldFunc(StrCs_RegCpuIntStat, Mbx, 31, 1) + FldFunc(StrCs_RegCpuIntStat, Com7, 23, 1) + FldFunc(StrCs_RegCpuIntStat, Com6, 22, 1) + FldFunc(StrCs_RegCpuIntStat, Com5, 21, 1) + FldFunc(StrCs_RegCpuIntStat, Com4, 20, 1) + FldFunc(StrCs_RegCpuIntStat, Com3, 19, 1) + FldFunc(StrCs_RegCpuIntStat, Com2, 18, 1) + FldFunc(StrCs_RegCpuIntStat, Com1, 17, 1) + FldFunc(StrCs_RegCpuIntStat, Com0, 16, 1) + FldFunc(StrCs_RegCpuIntStat, Hw7, 15, 1) + FldFunc(StrCs_RegCpuIntStat, Hw6, 14, 1) + FldFunc(StrCs_RegCpuIntStat, Hw5, 13, 1) + FldFunc(StrCs_RegCpuIntStat, Hw4, 12, 1) + FldFunc(StrCs_RegCpuIntStat, Hw3, 11, 1) + FldFunc(StrCs_RegCpuIntStat, Hw2, 10, 1) + FldFunc(StrCs_RegCpuIntStat, Hw1, 9, 1) + FldFunc(StrCs_RegCpuIntStat, Hw0, 8, 1) + FldFunc(StrCs_RegCpuIntStat, Db7, 7, 1) + FldFunc(StrCs_RegCpuIntStat, Db6, 6, 1) + FldFunc(StrCs_RegCpuIntStat, Db5, 5, 1) + FldFunc(StrCs_RegCpuIntStat, Db4, 4, 1) + FldFunc(StrCs_RegCpuIntStat, Db3, 3, 1) + FldFunc(StrCs_RegCpuIntStat, Db2, 2, 1) + FldFunc(StrCs_RegCpuIntStat, Db1, 1, 1) + FldFunc(StrCs_RegCpuIntStat, Db0, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, StreamCpuIntStat, 0x14, StrCs_StreamCpuIntStat, 0x100f14) + FldFunc(StrCs_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(StrCs_StreamCpuIntStat, Dec, 18, 1) + FldFunc(StrCs_StreamCpuIntStat, Aud, 17, 1) + FldFunc(StrCs_StreamCpuIntStat, M2m, 15, 1) + FldFunc(StrCs_StreamCpuIntStat, Pci, 14, 1) + FldFunc(StrCs_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(StrCs_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(StrCs_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(StrCs_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(StrCs_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(StrCs_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(StrCs_StreamCpuIntStat, Rb, 1, 1) + FldFunc(StrCs_StreamCpuIntStat, Sd, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, Dec0CpuIntStat, 0x14, StrCs_Dec0CpuIntStat, 0x100f14) + FldFunc(StrCs_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(StrCs_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(StrCs_Dec0CpuIntStat, Si, 8, 1) + FldFunc(StrCs_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(StrCs_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, Dec1CpuIntStat, 0x14, StrCs_Dec1CpuIntStat, 0x100f14) + FldFunc(StrCs_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(StrCs_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(StrCs_Dec1CpuIntStat, Si, 8, 1) + FldFunc(StrCs_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(StrCs_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, RegHst2cpuStat, 0x18, StrCs_RegHst2cpuStat, 0x100f18) + FldFunc(StrCs_RegHst2cpuStat, Value, 0, 32) +RegFunc(StreamCpuregs, 0x100F00, RegCpu2hstStat, 0x1C, StrCs_RegCpu2hstStat, 0x100f1c) + FldFunc(StrCs_RegCpu2hstStat, Value, 0, 32) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIntgenSet, 0x20, StrCs_RegCpuIntgenSet, 0x100f20) + FldFunc(StrCs_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(StrCs_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIntgenClr, 0x24, StrCs_RegCpuIntgenClr, 0x100f24) + FldFunc(StrCs_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) +// parameter REG_CPU_INTGEN_CLR__WATCHDOG_TIMER_WIDTH = 1; +// parameter REG_CPU_INTGEN_CLR__WATCHDOG_TIMER_MSB = 30; +// parameter REG_CPU_INTGEN_CLR__WATCHDOG_TIMER_LSB = 30; + FldFunc(StrCs_RegCpuIntgenClr, WatchdogTimer, 30, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(StrCs_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIcacheMiss, 0x28, StrCs_RegCpuIcacheMiss, 0x100f28) + FldFunc(StrCs_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(StreamCpuregs, 0x100F00, RegCpuIntgenMask, 0x2C, StrCs_RegCpuIntgenMask, 0x100f2c) + FldFunc(StrCs_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) +// parameter REG_CPU_INTGEN_MASK__WATCHDOG_TIMER_WIDTH = 1; +// parameter REG_CPU_INTGEN_MASK__WATCHDOG_TIMER_MSB = 30; +// parameter REG_CPU_INTGEN_MASK__WATCHDOG_TIMER_LSB = 30; + FldFunc(StrCs_RegCpuIntgenMask, WatchdogTimer, 30, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(StrCs_RegCpuIntgenMask, Int0, 0, 1) + +RegAreaFunc(StreamM2mBase, 0x101000, 0x1010FF) +RegFunc(StreamM2m, 0x101000, M2mRevision, 0x0, StrMm_M2mRevision, 0x101000) + FldFunc(StrMm_M2mRevision, Major, 8, 8) + FldFunc(StrMm_M2mRevision, Minor, 0, 8) +RegFunc(StreamM2m, 0x101000, M2mFirstDesc, 0x4, StrMm_M2mFirstDesc, 0x101004) + FldFunc(StrMm_M2mFirstDesc, Addr, 0, 28) +RegFunc(StreamM2m, 0x101000, M2mCtrl, 0x8, StrMm_M2mCtrl, 0x101008) + FldFunc(StrMm_M2mCtrl, Run, 0, 1) +RegFunc(StreamM2m, 0x101000, M2mWakeCtrl, 0xC, StrMm_M2mWakeCtrl, 0x10100c) + FldFunc(StrMm_M2mWakeCtrl, WakeMode, 1, 1) + FldFunc(StrMm_M2mWakeCtrl, Wake, 0, 1) +RegFunc(StreamM2m, 0x101000, M2mStatus, 0x14, StrMm_M2mStatus, 0x101014) + FldFunc(StrMm_M2mStatus, DmaStatus, 0, 2) +RegFunc(StreamM2m, 0x101000, M2mCurDesc, 0x18, StrMm_M2mCurDesc, 0x101018) + FldFunc(StrMm_M2mCurDesc, Addr, 0, 28) +RegFunc(StreamM2m, 0x101000, M2mCurByte, 0x1C, StrMm_M2mCurByte, 0x10101c) + FldFunc(StrMm_M2mCurByte, Count, 0, 25) +RegFunc(StreamM2m, 0x101000, M2mScratch, 0x24, StrMm_M2mScratch, 0x101024) + FldFunc(StrMm_M2mScratch, ScratchBit, 0, 32) + +RegAreaFunc(StreamM2mKeysBase, 0x101100, 0x1011FF) +RegFunc(StreamM2mKeys, 0x101100, M2mKey0Lo, 0x0, StrMKs_M2mKey0Lo, 0x101100) + FldFunc(StrMKs_M2mKey0Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey0Hi, 0x4, StrMKs_M2mKey0Hi, 0x101104) + FldFunc(StrMKs_M2mKey0Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey1Lo, 0x8, StrMKs_M2mKey1Lo, 0x101108) + FldFunc(StrMKs_M2mKey1Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey1Hi, 0xC, StrMKs_M2mKey1Hi, 0x10110c) + FldFunc(StrMKs_M2mKey1Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey2Lo, 0x10, StrMKs_M2mKey2Lo, 0x101110) + FldFunc(StrMKs_M2mKey2Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey2Hi, 0x14, StrMKs_M2mKey2Hi, 0x101114) + FldFunc(StrMKs_M2mKey2Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey3Lo, 0x18, StrMKs_M2mKey3Lo, 0x101118) + FldFunc(StrMKs_M2mKey3Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey3Hi, 0x1C, StrMKs_M2mKey3Hi, 0x10111c) + FldFunc(StrMKs_M2mKey3Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey4Lo, 0x20, StrMKs_M2mKey4Lo, 0x101120) + FldFunc(StrMKs_M2mKey4Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey4Hi, 0x24, StrMKs_M2mKey4Hi, 0x101124) + FldFunc(StrMKs_M2mKey4Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey5Lo, 0x28, StrMKs_M2mKey5Lo, 0x101128) + FldFunc(StrMKs_M2mKey5Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey5Hi, 0x2C, StrMKs_M2mKey5Hi, 0x10112c) + FldFunc(StrMKs_M2mKey5Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey6Lo, 0x30, StrMKs_M2mKey6Lo, 0x101130) + FldFunc(StrMKs_M2mKey6Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey6Hi, 0x34, StrMKs_M2mKey6Hi, 0x101134) + FldFunc(StrMKs_M2mKey6Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey7Lo, 0x38, StrMKs_M2mKey7Lo, 0x101138) + FldFunc(StrMKs_M2mKey7Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey7Hi, 0x3C, StrMKs_M2mKey7Hi, 0x10113c) + FldFunc(StrMKs_M2mKey7Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey8Lo, 0x40, StrMKs_M2mKey8Lo, 0x101140) + FldFunc(StrMKs_M2mKey8Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey8Hi, 0x44, StrMKs_M2mKey8Hi, 0x101144) + FldFunc(StrMKs_M2mKey8Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey9Lo, 0x48, StrMKs_M2mKey9Lo, 0x101148) + FldFunc(StrMKs_M2mKey9Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey9Hi, 0x4C, StrMKs_M2mKey9Hi, 0x10114c) + FldFunc(StrMKs_M2mKey9Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey10Lo, 0x50, StrMKs_M2mKey10Lo, 0x101150) + FldFunc(StrMKs_M2mKey10Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey10Hi, 0x54, StrMKs_M2mKey10Hi, 0x101154) + FldFunc(StrMKs_M2mKey10Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey11Lo, 0x58, StrMKs_M2mKey11Lo, 0x101158) + FldFunc(StrMKs_M2mKey11Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey11Hi, 0x5C, StrMKs_M2mKey11Hi, 0x10115c) + FldFunc(StrMKs_M2mKey11Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey12Lo, 0x60, StrMKs_M2mKey12Lo, 0x101160) + FldFunc(StrMKs_M2mKey12Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey12Hi, 0x64, StrMKs_M2mKey12Hi, 0x101164) + FldFunc(StrMKs_M2mKey12Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey13Lo, 0x68, StrMKs_M2mKey13Lo, 0x101168) + FldFunc(StrMKs_M2mKey13Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey13Hi, 0x6C, StrMKs_M2mKey13Hi, 0x10116c) + FldFunc(StrMKs_M2mKey13Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey14Lo, 0x70, StrMKs_M2mKey14Lo, 0x101170) + FldFunc(StrMKs_M2mKey14Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey14Hi, 0x74, StrMKs_M2mKey14Hi, 0x101174) + FldFunc(StrMKs_M2mKey14Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey15Lo, 0x78, StrMKs_M2mKey15Lo, 0x101178) + FldFunc(StrMKs_M2mKey15Lo, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mKey15Hi, 0x7C, StrMKs_M2mKey15Hi, 0x10117c) + FldFunc(StrMKs_M2mKey15Hi, Key, 0, 32) +RegFunc(StreamM2mKeys, 0x101100, M2mIntStat, 0x80, StrMKs_M2mIntStat, 0x101180) + FldFunc(StrMKs_M2mIntStat, Doc, 0, 1) +RegFunc(StreamM2mKeys, 0x101100, M2mIntMask, 0x84, StrMKs_M2mIntMask, 0x101184) + FldFunc(StrMKs_M2mIntMask, Doc, 0, 1) + +RegAreaFunc(StreamCpudmaBase, 0x101800, 0x1018FF) +RegFunc(StreamCpudma, 0x101800, RegDma0SdAddr, 0x0, StrCa_RegDma0SdAddr, 0x101800) + FldFunc(StrCa_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(StreamCpudma, 0x101800, RegDma0LclAddr, 0x4, StrCa_RegDma0LclAddr, 0x101804) + FldFunc(StrCa_RegDma0LclAddr, Addr, 2, 7) +RegFunc(StreamCpudma, 0x101800, RegDma0Len, 0x8, StrCa_RegDma0Len, 0x101808) + FldFunc(StrCa_RegDma0Len, Length, 2, 8) +RegFunc(StreamCpudma, 0x101800, RegDma1SdAddr, 0x10, StrCa_RegDma1SdAddr, 0x101810) + FldFunc(StrCa_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(StreamCpudma, 0x101800, RegDma1LclAddr, 0x14, StrCa_RegDma1LclAddr, 0x101814) + FldFunc(StrCa_RegDma1LclAddr, Addr, 2, 7) +RegFunc(StreamCpudma, 0x101800, RegDma1Len, 0x18, StrCa_RegDma1Len, 0x101818) + FldFunc(StrCa_RegDma1Len, Length, 2, 8) +RegFunc(StreamCpudma, 0x101800, RegDma2SdAddr, 0x20, StrCa_RegDma2SdAddr, 0x101820) + FldFunc(StrCa_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(StreamCpudma, 0x101800, RegDma2LclAddr, 0x24, StrCa_RegDma2LclAddr, 0x101824) + FldFunc(StrCa_RegDma2LclAddr, Addr, 2, 7) +RegFunc(StreamCpudma, 0x101800, RegDma2Len, 0x28, StrCa_RegDma2Len, 0x101828) + FldFunc(StrCa_RegDma2Len, Length, 2, 8) +RegFunc(StreamCpudma, 0x101800, RegDma3SdAddr, 0x30, StrCa_RegDma3SdAddr, 0x101830) + FldFunc(StrCa_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(StreamCpudma, 0x101800, RegDma3LclAddr, 0x34, StrCa_RegDma3LclAddr, 0x101834) + FldFunc(StrCa_RegDma3LclAddr, Addr, 2, 7) +RegFunc(StreamCpudma, 0x101800, RegDma3Len, 0x38, StrCa_RegDma3Len, 0x101838) + FldFunc(StrCa_RegDma3Len, Length, 2, 8) +RegFunc(StreamCpudma, 0x101800, RegDmaStatus, 0x40, StrCa_RegDmaStatus, 0x101840) + FldFunc(StrCa_RegDmaStatus, Act3, 3, 1) + FldFunc(StrCa_RegDmaStatus, Act2, 2, 1) + FldFunc(StrCa_RegDmaStatus, Act1, 1, 1) + FldFunc(StrCa_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(StreamDmamemBase, 0x101A00, 0x1021FF) +RegFunc(StreamDmamem, 0x101A00, DmaMem, 0x0, StrDm_DmaMem, 0x101a00) + FldFunc(StrDm_DmaMem, Data, 0, 32) + +RegAreaFunc(StreamIndSdramRegsBase, 0x141000, 0x14107F) +RegFunc(StreamIndSdramRegs, 0x141000, RegSdramInc, 0x0, StrISRs_RegSdramInc, 0x141000) + FldFunc(StrISRs_RegSdramInc, Inc, 0, 1) +RegFunc(StreamIndSdramRegs, 0x141000, RegSdramAddr, 0x4, StrISRs_RegSdramAddr, 0x141004) + FldFunc(StrISRs_RegSdramAddr, Addr, 0, 32) +RegFunc(StreamIndSdramRegs, 0x141000, RegSdramData, 0x8, StrISRs_RegSdramData, 0x141008) + FldFunc(StrISRs_RegSdramData, Data, 0, 32) +RegFunc(StreamIndSdramRegs, 0x141000, RegCpuDbg, 0x10, StrISRs_RegCpuDbg, 0x141010) + FldFunc(StrISRs_RegCpuDbg, Hst, 0, 1) + +RegAreaFunc(StreamCpucoreBase, 0x144000, 0x144FFF) +RegFunc(StreamCpucore, 0x144000, CpucoreReg, 0x0, StrCe_CpucoreReg, 0x144000) + FldFunc(StrCe_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(StreamCpuauxBase, 0x145000, 0x145FFF) +RegFunc(StreamCpuaux, 0x145000, CpuauxReg, 0x0, StrCx_CpuauxReg, 0x145000) + FldFunc(StrCx_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(StreamCpuimemBase, 0x146000, 0x147FFF) +RegFunc(StreamCpuimem, 0x146000, CpuimemReg, 0x0, StrCm_CpuimemReg, 0x146000) + FldFunc(StrCm_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(StreamCpudmemBase, 0x148000, 0x14FFFF) +RegFunc(StreamCpudmem, 0x148000, CpudmemReg, 0x0, StrCm_CpudmemReg, 0x148000) + FldFunc(StrCm_CpudmemReg, Addr, 0, 32) + +#endif + + +//****************************************************************************** +// +// Audio Processor Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_AUDIO_PROCESSOR + +RegAreaFunc(RaptorRbnodeRegsBase, 0x200000, 0x20007F) +RegFunc(RaptorRbnodeRegs, 0x200000, RbConfig , 0x0, RapRRs_RbConfig , 0x200000) + FldFunc(RapRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(RapRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(RaptorRbnodeRegs, 0x200000, RbStickyError, 0x4, RapRRs_RbStickyError, 0x200004) + FldFunc(RapRRs_RbStickyError, Node, 1, 1) + FldFunc(RapRRs_RbStickyError, Tgt, 0, 1) +RegFunc(RaptorRbnodeRegs, 0x200000, RbCurrentError, 0x8, RapRRs_RbCurrentError, 0x200008) + FldFunc(RapRRs_RbCurrentError, Node, 1, 1) + FldFunc(RapRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(RaptorRbnodeRegs, 0x200000, RbReadData, 0xC, RapRRs_RbReadData, 0x20000c) + FldFunc(RapRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(RaptorRingbusDebugRegs0Base, 0x200080, 0x2000FF) +RegFunc(RaptorRingbusDebugRegs0, 0x200080, RbDebugConfig, 0x0, RapRDR0_RbDebugConfig, 0x200080) + FldFunc(RapRDR0_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(RapRDR0_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(RaptorRingbusDebugRegs0, 0x200080, RbDebugReg0Addr, 0x4, RapRDR0_RbDebugReg0Addr, 0x200084) + FldFunc(RapRDR0_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs0, 0x200080, RbDebugReg1Addr, 0x8, RapRDR0_RbDebugReg1Addr, 0x200088) + FldFunc(RapRDR0_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs0, 0x200080, RbDebugReg2Addr, 0xC, RapRDR0_RbDebugReg2Addr, 0x20008c) + FldFunc(RapRDR0_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs0, 0x200080, RbDebugReg3Addr, 0x10, RapRDR0_RbDebugReg3Addr, 0x200090) + FldFunc(RapRDR0_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs0, 0x200080, RbDebugOutputReg, 0x14, RapRDR0_RbDebugOutputReg, 0x200094) + FldFunc(RapRDR0_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(RapRDR0_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(RaptorRingbusDebugRegs1Base, 0x200100, 0x20017F) +RegFunc(RaptorRingbusDebugRegs1, 0x200100, RbDebugConfig, 0x0, RapRDR1_RbDebugConfig, 0x200100) + FldFunc(RapRDR1_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(RapRDR1_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(RaptorRingbusDebugRegs1, 0x200100, RbDebugReg0Addr, 0x4, RapRDR1_RbDebugReg0Addr, 0x200104) + FldFunc(RapRDR1_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs1, 0x200100, RbDebugReg1Addr, 0x8, RapRDR1_RbDebugReg1Addr, 0x200108) + FldFunc(RapRDR1_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs1, 0x200100, RbDebugReg2Addr, 0xC, RapRDR1_RbDebugReg2Addr, 0x20010c) + FldFunc(RapRDR1_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs1, 0x200100, RbDebugReg3Addr, 0x10, RapRDR1_RbDebugReg3Addr, 0x200110) + FldFunc(RapRDR1_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(RaptorRingbusDebugRegs1, 0x200100, RbDebugOutputReg, 0x14, RapRDR1_RbDebugOutputReg, 0x200114) + FldFunc(RapRDR1_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(RapRDR1_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(AUD_DSP_MISC_BASE, 0x00240100, 0x0024011c) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_REVISION, 0x0, AUD_DSP_MISC_REVISION, 0x240100) + FldFunc(AUD_DSP_MISC_REVISION, MAJOR, 8, 8) + FldFunc(AUD_DSP_MISC_REVISION, MINOR, 0, 8) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_SOFT_RESET, 0x4, AUD_DSP_MISC_SOFT_RESET, 0x240104) + FldFunc(AUD_DSP_MISC_SOFT_RESET, RESET_SCBDMA0_B, 2, 1) + FldFunc(AUD_DSP_MISC_SOFT_RESET, RESET_PROC0_B, 1, 1) + FldFunc(AUD_DSP_MISC_SOFT_RESET, RESET0_B, 0, 1) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_SCB_BLOCKOUT_CTRL, 0xc, AUD_DSP_MISC_SCB_BLOCKOUT_CTRL, 0x24010c) + FldFunc(AUD_DSP_MISC_SCB_BLOCKOUT_CTRL, SCB_CLIENT1_BLOCKOUT, 8, 8) + FldFunc(AUD_DSP_MISC_SCB_BLOCKOUT_CTRL, SCB_CLIENT0_BLOCKOUT, 0, 8) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_SCB_BRIDGE0_STATUS, 0x10, AUD_DSP_MISC_SCB_BRIDGE0_STATUS, 0x240110) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, MV_RD_PENDING, 11, 1) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, FLOW_TO_DMA, 10, 1) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, CMD_RD_PTR, 9, 1) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, CMD_WR_PTR, 8, 1) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, BB_RD_PTR, 7, 1) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, BB_WR_PTR, 6, 1) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, BB_RD_CNT, 4, 2) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, BB_WR_CNT, 2, 2) + FldFunc(AUD_DSP_MISC_SCB_BRIDGE0_STATUS, SCB_REQ_CNT, 0, 2) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_SCB_MONITOR_CTRL, 0x14, AUD_DSP_MISC_SCB_MONITOR_CTRL, 0x240114) + FldFunc(AUD_DSP_MISC_SCB_MONITOR_CTRL, SCB_MONITOR_SELECT, 12, 2) + FldFunc(AUD_DSP_MISC_SCB_MONITOR_CTRL, SCB_LATENCY_LIMIT, 0, 12) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_SCB_MONITOR_CLEAR, 0x18, AUD_DSP_MISC_SCB_MONITOR_CLEAR, 0x240118) + FldFunc(AUD_DSP_MISC_SCB_MONITOR_CLEAR, SCB_CLEAR_MAX_LATENCY, 0, 1) +RegFunc(AUD_DSP_MISC, 0x00240100, AUD_DSP_MISC_SCB_MONITOR_STATUS, 0x1c, AUD_DSP_MISC_SCB_MONITOR_STATUS, 0x24011c) + FldFunc(AUD_DSP_MISC_SCB_MONITOR_STATUS, SCB_MAX_LATENCY, 0, 12) + +RegAreaFunc(AUD_DSP_CTRL0_BASE, 0x00242000, 0x002421a4) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_CORE_ID, 0x0, AUD_DSP_CTRL0_CORE_ID, 0x242000) + FldFunc(AUD_DSP_CTRL0_CORE_ID, ID, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_CORE_BOOT_CONFIG, 0x4, AUD_DSP_CTRL0_CORE_BOOT_CONFIG, 0x242004) + FldFunc(AUD_DSP_CTRL0_CORE_BOOT_CONFIG, BOOT_CODE_SELDS, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_CORE_IBOOT, 0x8, AUD_DSP_CTRL0_CORE_IBOOT, 0x242008) + FldFunc(AUD_DSP_CTRL0_CORE_IBOOT, IBOOT, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE0, 0x10, AUD_DSP_CTRL0_SEMAPHORE0, 0x242010) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE0, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE1, 0x14, AUD_DSP_CTRL0_SEMAPHORE1, 0x242014) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE1, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE2, 0x18, AUD_DSP_CTRL0_SEMAPHORE2, 0x242018) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE2, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE3, 0x1c, AUD_DSP_CTRL0_SEMAPHORE3, 0x24201c) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE3, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE4, 0x20, AUD_DSP_CTRL0_SEMAPHORE4, 0x242020) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE4, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE5, 0x24, AUD_DSP_CTRL0_SEMAPHORE5, 0x242024) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE5, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE6, 0x28, AUD_DSP_CTRL0_SEMAPHORE6, 0x242028) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE6, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_SEMAPHORE7, 0x2c, AUD_DSP_CTRL0_SEMAPHORE7, 0x24202c) + FldFunc(AUD_DSP_CTRL0_SEMAPHORE7, STATUS, 0, 8) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX0, 0x30, AUD_DSP_CTRL0_MAILBOX0, 0x242030) + FldFunc(AUD_DSP_CTRL0_MAILBOX0, MPEG1_LAYER1, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX1, 0x34, AUD_DSP_CTRL0_MAILBOX1, 0x242034) + FldFunc(AUD_DSP_CTRL0_MAILBOX1, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX2, 0x38, AUD_DSP_CTRL0_MAILBOX2, 0x242038) + FldFunc(AUD_DSP_CTRL0_MAILBOX2, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX3, 0x3c, AUD_DSP_CTRL0_MAILBOX3, 0x24203c) + FldFunc(AUD_DSP_CTRL0_MAILBOX3, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX4, 0x40, AUD_DSP_CTRL0_MAILBOX4, 0x242040) + FldFunc(AUD_DSP_CTRL0_MAILBOX4, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX5, 0x44, AUD_DSP_CTRL0_MAILBOX5, 0x242044) + FldFunc(AUD_DSP_CTRL0_MAILBOX5, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX6, 0x48, AUD_DSP_CTRL0_MAILBOX6, 0x242048) + FldFunc(AUD_DSP_CTRL0_MAILBOX6, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_MAILBOX7, 0x4c, AUD_DSP_CTRL0_MAILBOX7, 0x24204c) + FldFunc(AUD_DSP_CTRL0_MAILBOX7, MAIL3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_EXT_TIMER, 0x50, AUD_DSP_CTRL0_EXT_TIMER, 0x242050) + FldFunc(AUD_DSP_CTRL0_EXT_TIMER, ET, 31, 1) + FldFunc(AUD_DSP_CTRL0_EXT_TIMER, CM, 30, 1) + FldFunc(AUD_DSP_CTRL0_EXT_TIMER, COUNT, 0, 30) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_EXT_TIMERVALUE, 0x54, AUD_DSP_CTRL0_EXT_TIMERVALUE, 0x242054) + FldFunc(AUD_DSP_CTRL0_EXT_TIMERVALUE, TIME, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_WATCHDOG_TIMER, 0x58, AUD_DSP_CTRL0_WATCHDOG_TIMER, 0x242058) + FldFunc(AUD_DSP_CTRL0_WATCHDOG_TIMER, ET, 31, 1) + FldFunc(AUD_DSP_CTRL0_WATCHDOG_TIMER, CM, 30, 1) + FldFunc(AUD_DSP_CTRL0_WATCHDOG_TIMER, COUNT, 0, 30) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_WDOG_TIMERVALUE, 0x5c, AUD_DSP_CTRL0_WDOG_TIMERVALUE, 0x24205c) + FldFunc(AUD_DSP_CTRL0_WDOG_TIMERVALUE, TIME, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR0, 0x80, AUD_DSP_CTRL0_RBASE_ADDR0, 0x242080) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR0, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR1, 0x84, AUD_DSP_CTRL0_RBASE_ADDR1, 0x242084) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR1, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR2, 0x88, AUD_DSP_CTRL0_RBASE_ADDR2, 0x242088) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR2, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR3, 0x8c, AUD_DSP_CTRL0_RBASE_ADDR3, 0x24208c) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR3, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR4, 0x90, AUD_DSP_CTRL0_RBASE_ADDR4, 0x242090) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR4, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR5, 0x94, AUD_DSP_CTRL0_RBASE_ADDR5, 0x242094) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR5, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR6, 0x98, AUD_DSP_CTRL0_RBASE_ADDR6, 0x242098) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR6, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR7, 0x9c, AUD_DSP_CTRL0_RBASE_ADDR7, 0x24209c) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR7, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR8, 0xa0, AUD_DSP_CTRL0_RBASE_ADDR8, 0x2420a0) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR8, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR9, 0xa4, AUD_DSP_CTRL0_RBASE_ADDR9, 0x2420a4) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR9, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR10, 0xa8, AUD_DSP_CTRL0_RBASE_ADDR10, 0x2420a8) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR10, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_RBASE_ADDR11, 0xac, AUD_DSP_CTRL0_RBASE_ADDR11, 0x2420ac) + FldFunc(AUD_DSP_CTRL0_RBASE_ADDR11, ADDRESS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_XRI_SWAP, 0xb0, AUD_DSP_CTRL0_XRI_SWAP, 0x2420b0) + FldFunc(AUD_DSP_CTRL0_XRI_SWAP, RBUS2XRI, 2, 2) + FldFunc(AUD_DSP_CTRL0_XRI_SWAP, XRI2RBUS, 0, 2) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_XRI_TEST_STATUS, 0xb4, AUD_DSP_CTRL0_XRI_TEST_STATUS, 0x2420b4) + FldFunc(AUD_DSP_CTRL0_XRI_TEST_STATUS, TEST_STATUS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMEM_SPARE, 0xbc, AUD_DSP_CTRL0_DMEM_SPARE, 0x2420bc) + FldFunc(AUD_DSP_CTRL0_DMEM_SPARE, DATA3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F800, 0x100, AUD_DSP_CTRL0_JMEM_F800, 0x242100) + FldFunc(AUD_DSP_CTRL0_JMEM_F800, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F802, 0x104, AUD_DSP_CTRL0_JMEM_F802, 0x242104) + FldFunc(AUD_DSP_CTRL0_JMEM_F802, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F804, 0x108, AUD_DSP_CTRL0_JMEM_F804, 0x242108) + FldFunc(AUD_DSP_CTRL0_JMEM_F804, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F806, 0x10c, AUD_DSP_CTRL0_JMEM_F806, 0x24210c) + FldFunc(AUD_DSP_CTRL0_JMEM_F806, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F808, 0x110, AUD_DSP_CTRL0_JMEM_F808, 0x242110) + FldFunc(AUD_DSP_CTRL0_JMEM_F808, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F80A, 0x114, AUD_DSP_CTRL0_JMEM_F80A, 0x242114) + FldFunc(AUD_DSP_CTRL0_JMEM_F80A, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F80C, 0x118, AUD_DSP_CTRL0_JMEM_F80C, 0x242118) + FldFunc(AUD_DSP_CTRL0_JMEM_F80C, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F80E, 0x11c, AUD_DSP_CTRL0_JMEM_F80E, 0x24211c) + FldFunc(AUD_DSP_CTRL0_JMEM_F80E, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F810, 0x120, AUD_DSP_CTRL0_JMEM_F810, 0x242120) + FldFunc(AUD_DSP_CTRL0_JMEM_F810, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F812, 0x124, AUD_DSP_CTRL0_JMEM_F812, 0x242124) + FldFunc(AUD_DSP_CTRL0_JMEM_F812, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F814, 0x128, AUD_DSP_CTRL0_JMEM_F814, 0x242128) + FldFunc(AUD_DSP_CTRL0_JMEM_F814, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F816, 0x12c, AUD_DSP_CTRL0_JMEM_F816, 0x24212c) + FldFunc(AUD_DSP_CTRL0_JMEM_F816, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F818, 0x130, AUD_DSP_CTRL0_JMEM_F818, 0x242130) + FldFunc(AUD_DSP_CTRL0_JMEM_F818, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_JMEM_F81A_FFFF, 0x134, AUD_DSP_CTRL0_JMEM_F81A_FFFF, 0x242134) + FldFunc(AUD_DSP_CTRL0_JMEM_F81A_FFFF, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_EXT_IMEM0, 0x138, AUD_DSP_CTRL0_EXT_IMEM0, 0x242138) + FldFunc(AUD_DSP_CTRL0_EXT_IMEM0, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_EXT_IMEM1, 0x13c, AUD_DSP_CTRL0_EXT_IMEM1, 0x24213c) + FldFunc(AUD_DSP_CTRL0_EXT_IMEM1, INSTRUCTIONS, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_I2R_RDATA, 0x140, AUD_DSP_CTRL0_I2R_RDATA, 0x242140) + FldFunc(AUD_DSP_CTRL0_I2R_RDATA, DATA3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_R2I_WDATA, 0x144, AUD_DSP_CTRL0_R2I_WDATA, 0x242144) + FldFunc(AUD_DSP_CTRL0_R2I_WDATA, DATA3, 0, 32) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_R2I_CMD_ADDR, 0x148, AUD_DSP_CTRL0_R2I_CMD_ADDR, 0x242148) + FldFunc(AUD_DSP_CTRL0_R2I_CMD_ADDR, MEM, 19, 1) + FldFunc(AUD_DSP_CTRL0_R2I_CMD_ADDR, RD_WR_CMD, 16, 3) + FldFunc(AUD_DSP_CTRL0_R2I_CMD_ADDR, ADDRESS, 0, 16) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_IMC_STAT, 0x14c, AUD_DSP_CTRL0_IMC_STAT, 0x24214c) + FldFunc(AUD_DSP_CTRL0_IMC_STAT, RBUS_BUSY, 4, 1) + FldFunc(AUD_DSP_CTRL0_IMC_STAT, RBUS, 3, 1) + FldFunc(AUD_DSP_CTRL0_IMC_STAT, DMA, 2, 1) + FldFunc(AUD_DSP_CTRL0_IMC_STAT, DSP_IMEM, 1, 1) + FldFunc(AUD_DSP_CTRL0_IMC_STAT, DSP_DMEM, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_SRC_ADDR0, 0x180, AUD_DSP_CTRL0_DMA_SRC_ADDR0, 0x242180) + FldFunc(AUD_DSP_CTRL0_DMA_SRC_ADDR0, SRC_ADDR, 0, 28) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_DST_ADDR0, 0x184, AUD_DSP_CTRL0_DMA_DST_ADDR0, 0x242184) + FldFunc(AUD_DSP_CTRL0_DMA_DST_ADDR0, DST_ADDR, 0, 28) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_TRANSFER0, 0x188, AUD_DSP_CTRL0_DMA_TRANSFER0, 0x242188) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER0, MW_SWAP_TYPE, 30, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER0, DATA_TYPE, 28, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER0, SWAP_TYPE, 26, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER0, TRAN_TYPE, 24, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER0, NUM_BYTES, 0, 17) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_ABORT0, 0x18c, AUD_DSP_CTRL0_DMA_ABORT0, 0x24218c) + FldFunc(AUD_DSP_CTRL0_DMA_ABORT0, ABORTDM, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_SRC_ADDR1, 0x190, AUD_DSP_CTRL0_DMA_SRC_ADDR1, 0x242190) + FldFunc(AUD_DSP_CTRL0_DMA_SRC_ADDR1, SRC_ADDR, 0, 28) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_DST_ADDR1, 0x194, AUD_DSP_CTRL0_DMA_DST_ADDR1, 0x242194) + FldFunc(AUD_DSP_CTRL0_DMA_DST_ADDR1, DST_ADDR, 0, 28) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_TRANSFER1, 0x198, AUD_DSP_CTRL0_DMA_TRANSFER1, 0x242198) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER1, MW_SWAP_TYPE, 30, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER1, DATA_TYPE, 28, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER1, SWAP_TYPE, 26, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER1, TRAN_TYPE, 24, 2) + FldFunc(AUD_DSP_CTRL0_DMA_TRANSFER1, NUM_BYTES, 0, 17) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_ABORT1, 0x19c, AUD_DSP_CTRL0_DMA_ABORT1, 0x24219c) + FldFunc(AUD_DSP_CTRL0_DMA_ABORT1, ABORTDM, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_STATUS, 0x1a0, AUD_DSP_CTRL0_DMA_STATUS, 0x2421a0) + FldFunc(AUD_DSP_CTRL0_DMA_STATUS, ABORT1DM, 10, 1) + FldFunc(AUD_DSP_CTRL0_DMA_STATUS, FINISHED1DM, 9, 1) + FldFunc(AUD_DSP_CTRL0_DMA_STATUS, BUSY1DM, 8, 1) + FldFunc(AUD_DSP_CTRL0_DMA_STATUS, ABORT0DM, 2, 1) + FldFunc(AUD_DSP_CTRL0_DMA_STATUS, FINISHED0DM, 1, 1) + FldFunc(AUD_DSP_CTRL0_DMA_STATUS, BUSY0DM, 0, 1) +RegFunc(AUD_DSP_CTRL0, 0x00242000, AUD_DSP_CTRL0_DMA_TEST_STATUS, 0x1a4, AUD_DSP_CTRL0_DMA_TEST_STATUS, 0x2421a4) + FldFunc(AUD_DSP_CTRL0_DMA_TEST_STATUS, TEST_STATUS, 0, 32) + +RegAreaFunc(AUD_DSP_CFG0_BASE, 0x00242400, 0x002425fc) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_MASTER_IT_POINTER, 0x0, AUD_DSP_CFG0_MASTER_IT_POINTER, 0x242400) + FldFunc(AUD_DSP_CFG0_MASTER_IT_POINTER, MASTER_INDEX_TABLE_PTR, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STC_MASTER_SELECT, 0x4, AUD_DSP_CFG0_STC_MASTER_SELECT, 0x242404) + FldFunc(AUD_DSP_CFG0_STC_MASTER_SELECT, SW_UNDEFINED, 1, 31) + FldFunc(AUD_DSP_CFG0_STC_MASTER_SELECT, STC_SELECT, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SW_UNDEFINED_HOST, 0x8, AUD_DSP_CFG0_SW_UNDEFINED_HOST, 0x242408) + FldFunc(AUD_DSP_CFG0_SW_UNDEFINED_HOST, SW_UNDEFINED, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, 0x20, AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, 0x242420) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, SW_UNDEFINED, 16, 16) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, TIMEBASE_SEL, 12, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, RAVE_CTXT_SEL, 8, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, AUD_MODULE_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT0, AUD_INPUT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_AV_OFFSET_CXT0, 0x24, AUD_DSP_CFG0_AV_OFFSET_CXT0, 0x242424) + FldFunc(AUD_DSP_CFG0_AV_OFFSET_CXT0, AV_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PVR_OFFSET_CXT0, 0x28, AUD_DSP_CFG0_PVR_OFFSET_CXT0, 0x242428) + FldFunc(AUD_DSP_CFG0_PVR_OFFSET_CXT0, PVR_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_DECODE_OFFSET_CXT0, 0x2c, AUD_DSP_CFG0_DECODE_OFFSET_CXT0, 0x24242c) + FldFunc(AUD_DSP_CFG0_DECODE_OFFSET_CXT0, DECODE_OFFSET3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT0, 0x30, AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT0, 0x242430) + FldFunc(AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT0, TSM_UPPER_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT0, 0x34, AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT0, 0x242434) + FldFunc(AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT0, TSM_LOWER_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT0, 0x38, AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT0, 0x242438) + FldFunc(AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT0, TSM_DISCARD_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, 0x3c, AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, 0x24243c) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH2_BUF_ID, 28, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH2_SRC_ID, 25, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH2_EN, 24, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH1_BUF_ID, 20, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH1_SRC_ID, 17, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH1_EN, 16, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH0_BUF_ID, 12, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH0_SRC_ID, 9, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CH0_EN, 8, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CMP_BUF_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CMP_SRC_ID, 1, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT0, CMP_EN, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, 0x40, AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, 0x242440) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, SW_UNDEFINED, 24, 8) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH5_BUF_ID, 20, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH5_SRC_ID, 17, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH5_EN, 16, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH4_BUF_ID, 12, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH4_SRC_ID, 9, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH4_EN, 8, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH3_BUF_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH3_SRC_ID, 1, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT0, CH3_EN, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_DEST_CXT0, 0x44, AUD_DSP_CFG0_FMM_DEST_CXT0, 0x242444) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, SW_UNDEFINED, 8, 24) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, PLL3, 7, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, PLL2, 6, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, PLL1, 5, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, PLL0, 4, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, SPDIF1, 3, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, SPDIF0, 2, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, DAC1, 1, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT0, DAC0, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_ALGO_ID_CXT0, 0x48, AUD_DSP_CFG0_ALGO_ID_CXT0, 0x242448) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT0, SW_UNDEFINED, 8, 24) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT0, DECODE_MODE, 5, 3) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT0, ALGO_ID, 0, 5) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER0_CXT0, 0x4c, AUD_DSP_CFG0_CONTROL_REGISTER0_CXT0, 0x24244c) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER0_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER1_CXT0, 0x50, AUD_DSP_CFG0_CONTROL_REGISTER1_CXT0, 0x242450) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER1_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER2_CXT0, 0x54, AUD_DSP_CFG0_CONTROL_REGISTER2_CXT0, 0x242454) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER2_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER3_CXT0, 0x58, AUD_DSP_CFG0_CONTROL_REGISTER3_CXT0, 0x242458) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER3_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER4_CXT0, 0x5c, AUD_DSP_CFG0_CONTROL_REGISTER4_CXT0, 0x24245c) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER4_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_KARAOKE_CONFIG_CXT0, 0x60, AUD_DSP_CFG0_KARAOKE_CONFIG_CXT0, 0x242460) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT0, SW_UNDEFINED, 4, 28) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT0, KARAOKE_ALGO_TYPE, 2, 2) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT0, VOCAL_CHANNEL_VALUE, 0, 2) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT0, 0x64, AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT0, 0x242464) + FldFunc(AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT0, SW_UNDEFINED, 3, 29) + FldFunc(AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT0, DOWNMIX_MODE, 0, 3) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SRS_CONFIG_CXT0, 0x68, AUD_DSP_CFG0_SRS_CONFIG_CXT0, 0x242468) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT0, SW_UNDEFINED, 10, 22) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT0, SRS_SPEAKER_RESPONSE, 6, 4) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT0, SRS_MODE, 2, 4) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT0, SRS_, 1, 1) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT0, SRS_ENABLE, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SRC_CONFIG_CXT0, 0x6c, AUD_DSP_CFG0_SRC_CONFIG_CXT0, 0x24246c) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT0, SW_UNDEFINED, 6, 26) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT0, OUTPUT_SAMPLING_FREQUENCY, 4, 2) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT0, DECIMATION_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, 0x70, AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, 0x242470) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT0, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, 0x74, AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, 0x242474) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT0, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, 0x78, AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, 0x242478) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT0, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, 0x7c, AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, 0x24247c) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT0, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SW_UNDEFINED_HOST_CXT0, 0x80, AUD_DSP_CFG0_SW_UNDEFINED_HOST_CXT0, 0x242480) + FldFunc(AUD_DSP_CFG0_SW_UNDEFINED_HOST_CXT0, SW_UNDEFINED, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PTS_CXT0, 0x90, AUD_DSP_CFG0_PTS_CXT0, 0x242490) + FldFunc(AUD_DSP_CFG0_PTS_CXT0, PTS_VALUE3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STC_CXT0, 0x94, AUD_DSP_CFG0_STC_CXT0, 0x242494) + FldFunc(AUD_DSP_CFG0_STC_CXT0, STC_VALUE3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PCR_OFFSET_CXT0, 0x98, AUD_DSP_CFG0_PCR_OFFSET_CXT0, 0x242498) + FldFunc(AUD_DSP_CFG0_PCR_OFFSET_CXT0, PCR_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_STATUS_CXT0, 0x9c, AUD_DSP_CFG0_TSM_STATUS_CXT0, 0x24249c) + FldFunc(AUD_DSP_CFG0_TSM_STATUS_CXT0, TSM_STATUS3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT0, 0xa0, AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT0, 0x2424a0) + FldFunc(AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT0, TSM_WAIT_PERIOD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT0, 0xa4, AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT0, 0x2424a4) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT0, 0xa8, AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT0, 0x2424a8) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT0, 0xac, AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT0, 0x2424ac) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT0, 0xb0, AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT0, 0x2424b0) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT0, 0xb4, AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT0, 0x2424b4) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT0, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_HEARTBEAT_CXT0, 0xb8, AUD_DSP_CFG0_HEARTBEAT_CXT0, 0x2424b8) + FldFunc(AUD_DSP_CFG0_HEARTBEAT_CXT0, HEARTBEAT, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT0, 0xbc, AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT0, 0x2424bc) + FldFunc(AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT0, HOST_CONFIG_PARAMS_PTR, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, 0xc0, AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, 0x2424c0) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, SW_UNDEFINED, 16, 16) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, TIMEBASE_SEL, 12, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, RAVE_CTXT_SEL, 8, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, AUD_MODULE_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT1, AUD_INPUT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_AV_OFFSET_CXT1, 0xc4, AUD_DSP_CFG0_AV_OFFSET_CXT1, 0x2424c4) + FldFunc(AUD_DSP_CFG0_AV_OFFSET_CXT1, AV_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PVR_OFFSET_CXT1, 0xc8, AUD_DSP_CFG0_PVR_OFFSET_CXT1, 0x2424c8) + FldFunc(AUD_DSP_CFG0_PVR_OFFSET_CXT1, PVR_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_DECODE_OFFSET_CXT1, 0xcc, AUD_DSP_CFG0_DECODE_OFFSET_CXT1, 0x2424cc) + FldFunc(AUD_DSP_CFG0_DECODE_OFFSET_CXT1, DECODE_OFFSET3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT1, 0xd0, AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT1, 0x2424d0) + FldFunc(AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT1, TSM_UPPER_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT1, 0xd4, AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT1, 0x2424d4) + FldFunc(AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT1, TSM_LOWER_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT1, 0xd8, AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT1, 0x2424d8) + FldFunc(AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT1, TSM_DISCARD_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, 0xdc, AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, 0x2424dc) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH2_BUF_ID, 28, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH2_SRC_ID, 25, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH2_EN, 24, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH1_BUF_ID, 20, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH1_SRC_ID, 17, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH1_EN, 16, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH0_BUF_ID, 12, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH0_SRC_ID, 9, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CH0_EN, 8, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CMP_BUF_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CMP_SRC_ID, 1, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT1, CMP_EN, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, 0xe0, AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, 0x2424e0) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, SW_UNDEFINED, 24, 8) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH5_BUF_ID, 20, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH5_SRC_ID, 17, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH5_EN, 16, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH4_BUF_ID, 12, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH4_SRC_ID, 9, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH4_EN, 8, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH3_BUF_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH3_SRC_ID, 1, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT1, CH3_EN, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_DEST_CXT1, 0xe4, AUD_DSP_CFG0_FMM_DEST_CXT1, 0x2424e4) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, SW_UNDEFINED, 8, 24) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, PLL3, 7, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, PLL2, 6, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, PLL1, 5, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, PLL0, 4, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, SPDIF1, 3, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, SPDIF0, 2, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, DAC1, 1, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT1, DAC0, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_ALGO_ID_CXT1, 0xe8, AUD_DSP_CFG0_ALGO_ID_CXT1, 0x2424e8) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT1, SW_UNDEFINED, 8, 24) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT1, DECODE_MODE, 5, 3) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT1, ALGO_ID, 0, 5) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER0_CXT1, 0xec, AUD_DSP_CFG0_CONTROL_REGISTER0_CXT1, 0x2424ec) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER0_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER1_CXT1, 0xf0, AUD_DSP_CFG0_CONTROL_REGISTER1_CXT1, 0x2424f0) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER1_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER2_CXT1, 0xf4, AUD_DSP_CFG0_CONTROL_REGISTER2_CXT1, 0x2424f4) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER2_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER3_CXT1, 0xf8, AUD_DSP_CFG0_CONTROL_REGISTER3_CXT1, 0x2424f8) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER3_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER4_CXT1, 0xfc, AUD_DSP_CFG0_CONTROL_REGISTER4_CXT1, 0x2424fc) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER4_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_KARAOKE_CONFIG_CXT1, 0x100, AUD_DSP_CFG0_KARAOKE_CONFIG_CXT1, 0x242500) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT1, SW_UNDEFINED, 4, 28) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT1, KARAOKE_ALGO_TYPE, 2, 2) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT1, VOCAL_CHANNEL_VALUE, 0, 2) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT1, 0x104, AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT1, 0x242504) + FldFunc(AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT1, SW_UNDEFINED, 3, 29) + FldFunc(AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT1, DOWNMIX_MODE, 0, 3) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SRS_CONFIG_CXT1, 0x108, AUD_DSP_CFG0_SRS_CONFIG_CXT1, 0x242508) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT1, SW_UNDEFINED, 10, 22) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT1, SRS_SPEAKER_RESPONSE, 6, 4) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT1, SRS_MODE, 2, 4) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT1, SRS_, 1, 1) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT1, SRS_ENABLE, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SRC_CONFIG_CXT1, 0x10c, AUD_DSP_CFG0_SRC_CONFIG_CXT1, 0x24250c) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT1, SW_UNDEFINED, 6, 26) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT1, OUTPUT_SAMPLING_FREQUENCY, 4, 2) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT1, DECIMATION_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, 0x110, AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, 0x242510) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT1, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, 0x114, AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, 0x242514) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT1, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, 0x118, AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, 0x242518) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT1, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, 0x11c, AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, 0x24251c) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT1, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SW_UNDEFINED_HOST_CXT1, 0x120, AUD_DSP_CFG0_SW_UNDEFINED_HOST_CXT1, 0x242520) + FldFunc(AUD_DSP_CFG0_SW_UNDEFINED_HOST_CXT1, SW_UNDEFINED, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PTS_CXT1, 0x130, AUD_DSP_CFG0_PTS_CXT1, 0x242530) + FldFunc(AUD_DSP_CFG0_PTS_CXT1, PTS_VALUE3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STC_CXT1, 0x134, AUD_DSP_CFG0_STC_CXT1, 0x242534) + FldFunc(AUD_DSP_CFG0_STC_CXT1, STC_VALUE3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PCR_OFFSET_CXT1, 0x138, AUD_DSP_CFG0_PCR_OFFSET_CXT1, 0x242538) + FldFunc(AUD_DSP_CFG0_PCR_OFFSET_CXT1, PCR_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_STATUS_CXT1, 0x13c, AUD_DSP_CFG0_TSM_STATUS_CXT1, 0x24253c) + FldFunc(AUD_DSP_CFG0_TSM_STATUS_CXT1, TSM_STATUS3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT1, 0x140, AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT1, 0x242540) + FldFunc(AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT1, TSM_WAIT_PERIOD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT1, 0x144, AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT1, 0x242544) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT1, 0x148, AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT1, 0x242548) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT1, 0x14c, AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT1, 0x24254c) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT1, 0x150, AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT1, 0x242550) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT1, 0x154, AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT1, 0x242554) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT1, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_HEARTBEAT_CXT1, 0x158, AUD_DSP_CFG0_HEARTBEAT_CXT1, 0x242558) + FldFunc(AUD_DSP_CFG0_HEARTBEAT_CXT1, HEARTBEAT, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT1, 0x15c, AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT1, 0x24255c) + FldFunc(AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT1, HOST_CONFIG_PARAMS_PTR, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, 0x160, AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, 0x242560) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, SW_UNDEFINED, 16, 16) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, TIMEBASE_SEL, 12, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, RAVE_CTXT_SEL, 8, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, AUD_MODULE_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_RAVE_TIMEBASE_SEL_CXT2, AUD_INPUT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_AV_OFFSET_CXT2, 0x164, AUD_DSP_CFG0_AV_OFFSET_CXT2, 0x242564) + FldFunc(AUD_DSP_CFG0_AV_OFFSET_CXT2, AV_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PVR_OFFSET_CXT2, 0x168, AUD_DSP_CFG0_PVR_OFFSET_CXT2, 0x242568) + FldFunc(AUD_DSP_CFG0_PVR_OFFSET_CXT2, PVR_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_DECODE_OFFSET_CXT2, 0x16c, AUD_DSP_CFG0_DECODE_OFFSET_CXT2, 0x24256c) + FldFunc(AUD_DSP_CFG0_DECODE_OFFSET_CXT2, DECODE_OFFSET3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT2, 0x170, AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT2, 0x242570) + FldFunc(AUD_DSP_CFG0_TSM_UPPER_THRESHOLD_CXT2, TSM_UPPER_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT2, 0x174, AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT2, 0x242574) + FldFunc(AUD_DSP_CFG0_TSM_LOWER_THRESHOLD_CXT2, TSM_LOWER_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT2, 0x178, AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT2, 0x242578) + FldFunc(AUD_DSP_CFG0_TSM_DISCARD_THRESHOLD_CXT2, TSM_DISCARD_THRESHOLD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, 0x17c, AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, 0x24257c) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH2_BUF_ID, 28, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH2_SRC_ID, 25, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH2_EN, 24, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH1_BUF_ID, 20, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH1_SRC_ID, 17, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH1_EN, 16, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH0_BUF_ID, 12, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH0_SRC_ID, 9, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CH0_EN, 8, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CMP_BUF_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CMP_SRC_ID, 1, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG0_CXT2, CMP_EN, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, 0x180, AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, 0x242580) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, SW_UNDEFINED, 24, 8) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH5_BUF_ID, 20, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH5_SRC_ID, 17, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH5_EN, 16, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH4_BUF_ID, 12, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH4_SRC_ID, 9, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH4_EN, 8, 1) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH3_BUF_ID, 4, 4) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH3_SRC_ID, 1, 3) + FldFunc(AUD_DSP_CFG0_FMM_BUFF_CFG1_CXT2, CH3_EN, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_FMM_DEST_CXT2, 0x184, AUD_DSP_CFG0_FMM_DEST_CXT2, 0x242584) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, SW_UNDEFINED, 8, 24) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, PLL3, 7, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, PLL2, 6, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, PLL1, 5, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, PLL0, 4, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, SPDIF1, 3, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, SPDIF0, 2, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, DAC1, 1, 1) + FldFunc(AUD_DSP_CFG0_FMM_DEST_CXT2, DAC0, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_ALGO_ID_CXT2, 0x188, AUD_DSP_CFG0_ALGO_ID_CXT2, 0x242588) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT2, SW_UNDEFINED, 8, 24) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT2, DECODE_MODE, 5, 3) + FldFunc(AUD_DSP_CFG0_ALGO_ID_CXT2, ALGO_ID, 0, 5) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER0_CXT2, 0x18c, AUD_DSP_CFG0_CONTROL_REGISTER0_CXT2, 0x24258c) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER0_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER1_CXT2, 0x190, AUD_DSP_CFG0_CONTROL_REGISTER1_CXT2, 0x242590) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER1_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER2_CXT2, 0x194, AUD_DSP_CFG0_CONTROL_REGISTER2_CXT2, 0x242594) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER2_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER3_CXT2, 0x198, AUD_DSP_CFG0_CONTROL_REGISTER3_CXT2, 0x242598) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER3_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_CONTROL_REGISTER4_CXT2, 0x19c, AUD_DSP_CFG0_CONTROL_REGISTER4_CXT2, 0x24259c) + FldFunc(AUD_DSP_CFG0_CONTROL_REGISTER4_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_KARAOKE_CONFIG_CXT2, 0x1a0, AUD_DSP_CFG0_KARAOKE_CONFIG_CXT2, 0x2425a0) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT2, SW_UNDEFINED, 4, 28) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT2, KARAOKE_ALGO_TYPE, 2, 2) + FldFunc(AUD_DSP_CFG0_KARAOKE_CONFIG_CXT2, VOCAL_CHANNEL_VALUE, 0, 2) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT2, 0x1a4, AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT2, 0x2425a4) + FldFunc(AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT2, SW_UNDEFINED, 3, 29) + FldFunc(AUD_DSP_CFG0_DOWNMIX_CONFIG_CXT2, DOWNMIX_MODE, 0, 3) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SRS_CONFIG_CXT2, 0x1a8, AUD_DSP_CFG0_SRS_CONFIG_CXT2, 0x2425a8) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT2, SW_UNDEFINED, 10, 22) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT2, SRS_SPEAKER_RESPONSE, 6, 4) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT2, SRS_MODE, 2, 4) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT2, SRS_, 1, 1) + FldFunc(AUD_DSP_CFG0_SRS_CONFIG_CXT2, SRS_ENABLE, 0, 1) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SRC_CONFIG_CXT2, 0x1ac, AUD_DSP_CFG0_SRC_CONFIG_CXT2, 0x2425ac) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT2, SW_UNDEFINED, 6, 26) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT2, OUTPUT_SAMPLING_FREQUENCY, 4, 2) + FldFunc(AUD_DSP_CFG0_SRC_CONFIG_CXT2, DECIMATION_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, 0x1b0, AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, 0x2425b0) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH0_CXT2, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, 0x1b4, AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, 0x2425b4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH1_CXT2, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, 0x1b8, AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, 0x2425b8) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH2_CXT2, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, 0x1bc, AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, 0x2425bc) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE6, 28, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE5, 24, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE4, 20, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE3, 16, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE2, 12, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE1, 8, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, POST_PROCESSING_TYPE_STAGE0, 4, 4) + FldFunc(AUD_DSP_CFG0_POST_PROCESSING_BRANCH3_CXT2, OUTPUT_PORT_TYPE, 0, 4) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SW_UNDEFINED_HOST_CX20, 0x1c0, AUD_DSP_CFG0_SW_UNDEFINED_HOST_CX20, 0x2425c0) + FldFunc(AUD_DSP_CFG0_SW_UNDEFINED_HOST_CX20, SW_UNDEFINED, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PTS_CXT2, 0x1d0, AUD_DSP_CFG0_PTS_CXT2, 0x2425d0) + FldFunc(AUD_DSP_CFG0_PTS_CXT2, PTS_VALUE3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STC_CXT2, 0x1d4, AUD_DSP_CFG0_STC_CXT2, 0x2425d4) + FldFunc(AUD_DSP_CFG0_STC_CXT2, STC_VALUE3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_PCR_OFFSET_CXT2, 0x1d8, AUD_DSP_CFG0_PCR_OFFSET_CXT2, 0x2425d8) + FldFunc(AUD_DSP_CFG0_PCR_OFFSET_CXT2, PCR_OFFSET, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_STATUS_CXT2, 0x1dc, AUD_DSP_CFG0_TSM_STATUS_CXT2, 0x2425dc) + FldFunc(AUD_DSP_CFG0_TSM_STATUS_CXT2, TSM_STATUS3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT2, 0x1e0, AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT2, 0x2425e0) + FldFunc(AUD_DSP_CFG0_TSM_WAIT_PERIOD_CXT2, TSM_WAIT_PERIOD3, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT2, 0x1e4, AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT2, 0x2425e4) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER0_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT2, 0x1e8, AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT2, 0x2425e8) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER1_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT2, 0x1ec, AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT2, 0x2425ec) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER2_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT2, 0x1f0, AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT2, 0x2425f0) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER3_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT2, 0x1f4, AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT2, 0x2425f4) + FldFunc(AUD_DSP_CFG0_STREAM_INFO_REGISTER4_CXT2, AAC_LC, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_HEARTBEAT_CXT2, 0x1f8, AUD_DSP_CFG0_HEARTBEAT_CXT2, 0x2425f8) + FldFunc(AUD_DSP_CFG0_HEARTBEAT_CXT2, HEARTBEAT, 0, 32) +RegFunc(AUD_DSP_CFG0, 0x00242400, AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT2, 0x1fc, AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT2, 0x2425fc) + FldFunc(AUD_DSP_CFG0_SPDIF_PARSER_PTR_CXT2, HOST_CONFIG_PARAMS_PTR, 0, 32) + +RegAreaFunc(AUD_DSP_INTH0_BASE, 0x00242800, 0x0024282c) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_R5F_STATUS, 0x0, AUD_DSP_INTH0_R5F_STATUS, 0x242800) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI10_INTR, 10, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI09_INTR, 9, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI08_INTR, 8, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI05_INTRDS, 5, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI04_INTRDSP_HI0, 4, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI01_INTR, 1, 1) + FldFunc(AUD_DSP_INTH0_R5F_STATUS, DSP_HI00_INTR, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_R5F_SET, 0x4, AUD_DSP_INTH0_R5F_SET, 0x242804) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI10_INTR, 10, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI09_INTR, 9, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI08_INTR, 8, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI05_INTRDS, 5, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI04_INTRDSP_HI0, 4, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI01_INTR, 1, 1) + FldFunc(AUD_DSP_INTH0_R5F_SET, DSP_HI00_INTR, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_R5F_CLEAR, 0x8, AUD_DSP_INTH0_R5F_CLEAR, 0x242808) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI10_INTR, 10, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI09_INTR, 9, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI08_INTR, 8, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI05_INTRDS, 5, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI04_INTRDSP_HI0, 4, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI01_INTR, 1, 1) + FldFunc(AUD_DSP_INTH0_R5F_CLEAR, DSP_HI00_INTR, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_R5F_MASK_STATUS, 0xc, AUD_DSP_INTH0_R5F_MASK_STATUS, 0x24280c) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI10_MASK, 10, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI09_MASK, 9, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI08_MASK, 8, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI07_MASK, 7, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI06_MASK, 6, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI05_MASK, 5, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI04_MASK, 4, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI03_MASK, 3, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI02_MASK, 2, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI01_MASK, 1, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_STATUS, DSP_HI00_MASK, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_R5F_MASK_SET, 0x10, AUD_DSP_INTH0_R5F_MASK_SET, 0x242810) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI10_MASK, 10, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI09_MASK, 9, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI08_MASK, 8, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI07_MASK, 7, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI06_MASK, 6, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI05_MASK, 5, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI04_MASK, 4, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI03_MASK, 3, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI02_MASK, 2, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI01_MASK, 1, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_SET, DSP_HI00_MASK, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_R5F_MASK_CLEAR, 0x14, AUD_DSP_INTH0_R5F_MASK_CLEAR, 0x242814) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI10_MASK, 10, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI09_MASK, 9, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI08_MASK, 8, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI07_MASK, 7, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI06_MASK, 6, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI05_MASK, 5, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI04_MASK, 4, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI03_MASK, 3, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI02_MASK, 2, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI01_MASK, 1, 1) + FldFunc(AUD_DSP_INTH0_R5F_MASK_CLEAR, DSP_HI00_MASK, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_PCI_STATUS, 0x18, AUD_DSP_INTH0_PCI_STATUS, 0x242818) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI10_INTR, 10, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI09_INTR, 9, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI08_INTR, 8, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI05_INTRDS, 5, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI04_INTRDSP_HI0, 4, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI01_INTR, 1, 1) + FldFunc(AUD_DSP_INTH0_PCI_STATUS, DSP_HI00_INTR, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_PCI_SET, 0x1c, AUD_DSP_INTH0_PCI_SET, 0x24281c) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI10_INTR, 10, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI09_INTR, 9, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI08_INTR, 8, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI05_INTRDS, 5, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI04_INTRDSP_HI0, 4, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI01_INTR, 1, 1) + FldFunc(AUD_DSP_INTH0_PCI_SET, DSP_HI00_INTR, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_PCI_CLEAR, 0x20, AUD_DSP_INTH0_PCI_CLEAR, 0x242820) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI10_INTR, 10, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI09_INTR, 9, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI08_INTR, 8, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI05_INTRDS, 5, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI04_INTRDSP_HI0, 4, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI01_INTR, 1, 1) + FldFunc(AUD_DSP_INTH0_PCI_CLEAR, DSP_HI00_INTR, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_PCI_MASK_STATUS, 0x24, AUD_DSP_INTH0_PCI_MASK_STATUS, 0x242824) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI10_MASK, 10, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI09_MASK, 9, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI08_MASK, 8, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI07_MASK, 7, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI06_MASK, 6, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI05_MASK, 5, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI04_MASK, 4, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI03_MASK, 3, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI02_MASK, 2, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI01_MASK, 1, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_STATUS, DSP_HI00_MASK, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_PCI_MASK_SET, 0x28, AUD_DSP_INTH0_PCI_MASK_SET, 0x242828) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI10_MASK, 10, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI09_MASK, 9, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI08_MASK, 8, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI07_MASK, 7, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI06_MASK, 6, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI05_MASK, 5, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI04_MASK, 4, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI03_MASK, 3, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI02_MASK, 2, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI01_MASK, 1, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_SET, DSP_HI00_MASK, 0, 1) +RegFunc(AUD_DSP_INTH0, 0x00242800, AUD_DSP_INTH0_PCI_MASK_CLEAR, 0x2c, AUD_DSP_INTH0_PCI_MASK_CLEAR, 0x24282c) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI10_MASK, 10, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI09_MASK, 9, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI08_MASK, 8, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI07_MASK, 7, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI06_MASK, 6, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI05_MASK, 5, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI04_MASK, 4, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI03_MASK, 3, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI02_MASK, 2, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI01_MASK, 1, 1) + FldFunc(AUD_DSP_INTH0_PCI_MASK_CLEAR, DSP_HI00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_BE0_BASE, 0x00242a00, 0x00242a14) +RegFunc(AUD_DSP_ESR_BE0, 0x00242a00, AUD_DSP_ESR_BE0_INT_STATUS, 0x0, AUD_DSP_ESR_BE0_INT_STATUS, 0x242a00) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_STATUS, DSP_BE00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_BE0, 0x00242a00, AUD_DSP_ESR_BE0_INT_SET, 0x4, AUD_DSP_ESR_BE0_INT_SET, 0x242a04) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_SET, DSP_BE00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_BE0, 0x00242a00, AUD_DSP_ESR_BE0_INT_CLEAR, 0x8, AUD_DSP_ESR_BE0_INT_CLEAR, 0x242a08) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_BE0_INT_CLEAR, DSP_BE00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_BE0, 0x00242a00, AUD_DSP_ESR_BE0_MASK_STATUS, 0xc, AUD_DSP_ESR_BE0_MASK_STATUS, 0x242a0c) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_STATUS, DSP_BE00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_BE0, 0x00242a00, AUD_DSP_ESR_BE0_MASK_SET, 0x10, AUD_DSP_ESR_BE0_MASK_SET, 0x242a10) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_SET, DSP_BE00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_BE0, 0x00242a00, AUD_DSP_ESR_BE0_MASK_CLEAR, 0x14, AUD_DSP_ESR_BE0_MASK_CLEAR, 0x242a14) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_BE0_MASK_CLEAR, DSP_BE00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_PI0_BASE, 0x00242b00, 0x00242b14) +RegFunc(AUD_DSP_ESR_PI0, 0x00242b00, AUD_DSP_ESR_PI0_INT_STATUS, 0x0, AUD_DSP_ESR_PI0_INT_STATUS, 0x242b00) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI04_INTRDSP_PI0, 4, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_STATUS, DSP_PI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_PI0, 0x00242b00, AUD_DSP_ESR_PI0_INT_SET, 0x4, AUD_DSP_ESR_PI0_INT_SET, 0x242b04) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI04_INTRDSP_PI0, 4, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_SET, DSP_PI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_PI0, 0x00242b00, AUD_DSP_ESR_PI0_INT_CLEAR, 0x8, AUD_DSP_ESR_PI0_INT_CLEAR, 0x242b08) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI06_INTRDM, 6, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI04_INTRDSP_PI0, 4, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI03_INTRIM, 3, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI02_INTRDM, 2, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_PI0_INT_CLEAR, DSP_PI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_PI0, 0x00242b00, AUD_DSP_ESR_PI0_MASK_STATUS, 0xc, AUD_DSP_ESR_PI0_MASK_STATUS, 0x242b0c) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_STATUS, DSP_PI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_PI0, 0x00242b00, AUD_DSP_ESR_PI0_MASK_SET, 0x10, AUD_DSP_ESR_PI0_MASK_SET, 0x242b10) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_SET, DSP_PI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_PI0, 0x00242b00, AUD_DSP_ESR_PI0_MASK_CLEAR, 0x14, AUD_DSP_ESR_PI0_MASK_CLEAR, 0x242b14) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_PI0_MASK_CLEAR, DSP_PI00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_SI00_BASE, 0x00243000, 0x00243014) +RegFunc(AUD_DSP_ESR_SI00, 0x00243000, AUD_DSP_ESR_SI00_INT_STATUS, 0x0, AUD_DSP_ESR_SI00_INT_STATUS, 0x243000) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_STATUS, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI00, 0x00243000, AUD_DSP_ESR_SI00_INT_SET, 0x4, AUD_DSP_ESR_SI00_INT_SET, 0x243004) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_SET, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI00, 0x00243000, AUD_DSP_ESR_SI00_INT_CLEAR, 0x8, AUD_DSP_ESR_SI00_INT_CLEAR, 0x243008) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI00_INT_CLEAR, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI00, 0x00243000, AUD_DSP_ESR_SI00_MASK_STATUS, 0xc, AUD_DSP_ESR_SI00_MASK_STATUS, 0x24300c) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_STATUS, DSP_SI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SI00, 0x00243000, AUD_DSP_ESR_SI00_MASK_SET, 0x10, AUD_DSP_ESR_SI00_MASK_SET, 0x243010) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_SET, DSP_SI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SI00, 0x00243000, AUD_DSP_ESR_SI00_MASK_CLEAR, 0x14, AUD_DSP_ESR_SI00_MASK_CLEAR, 0x243014) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI00_MASK_CLEAR, DSP_SI00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_SI10_BASE, 0x00243100, 0x00243114) +RegFunc(AUD_DSP_ESR_SI10, 0x00243100, AUD_DSP_ESR_SI10_INT_STATUS, 0x0, AUD_DSP_ESR_SI10_INT_STATUS, 0x243100) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_STATUS, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI10, 0x00243100, AUD_DSP_ESR_SI10_INT_SET, 0x4, AUD_DSP_ESR_SI10_INT_SET, 0x243104) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_SET, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI10, 0x00243100, AUD_DSP_ESR_SI10_INT_CLEAR, 0x8, AUD_DSP_ESR_SI10_INT_CLEAR, 0x243108) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI10_INT_CLEAR, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI10, 0x00243100, AUD_DSP_ESR_SI10_MASK_STATUS, 0xc, AUD_DSP_ESR_SI10_MASK_STATUS, 0x24310c) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_STATUS, DSP_SI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SI10, 0x00243100, AUD_DSP_ESR_SI10_MASK_SET, 0x10, AUD_DSP_ESR_SI10_MASK_SET, 0x243110) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_SET, DSP_SI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SI10, 0x00243100, AUD_DSP_ESR_SI10_MASK_CLEAR, 0x14, AUD_DSP_ESR_SI10_MASK_CLEAR, 0x243114) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI10_MASK_CLEAR, DSP_SI00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_SI20_BASE, 0x00243200, 0x00243214) +RegFunc(AUD_DSP_ESR_SI20, 0x00243200, AUD_DSP_ESR_SI20_INT_STATUS, 0x0, AUD_DSP_ESR_SI20_INT_STATUS, 0x243200) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_STATUS, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI20, 0x00243200, AUD_DSP_ESR_SI20_INT_SET, 0x4, AUD_DSP_ESR_SI20_INT_SET, 0x243204) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_SET, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI20, 0x00243200, AUD_DSP_ESR_SI20_INT_CLEAR, 0x8, AUD_DSP_ESR_SI20_INT_CLEAR, 0x243208) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI31_INTR, 31, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI30_INTR, 30, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI29_INTR, 29, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI28_INTR, 28, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI27_INTR, 27, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI26_INTR, 26, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI25_INTR, 25, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI24_INTR, 24, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI23_INTR, 23, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI22_INTR, 22, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI21_INTR, 21, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI20_INTR, 20, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI19_INTR, 19, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI18_INTR, 18, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI17_INTR, 17, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI16_INTR, 16, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI15_INTR, 15, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI14_INTR, 14, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI13_INTR, 13, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI12_INTR, 12, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI11_INTR, 11, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI10_INTR, 10, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI09_INTR, 9, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI08_INTR, 8, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI07_INTR, 7, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI06_INTR, 6, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI05_INTR, 5, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI04_INTR, 4, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI03_INTR, 3, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI02_INTR, 2, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI01_INTR, 1, 1) + FldFunc(AUD_DSP_ESR_SI20_INT_CLEAR, DSP_SI00_INTR, 0, 1) +RegFunc(AUD_DSP_ESR_SI20, 0x00243200, AUD_DSP_ESR_SI20_MASK_STATUS, 0xc, AUD_DSP_ESR_SI20_MASK_STATUS, 0x24320c) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_STATUS, DSP_SI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SI20, 0x00243200, AUD_DSP_ESR_SI20_MASK_SET, 0x10, AUD_DSP_ESR_SI20_MASK_SET, 0x243210) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_SET, DSP_SI00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SI20, 0x00243200, AUD_DSP_ESR_SI20_MASK_CLEAR, 0x14, AUD_DSP_ESR_SI20_MASK_CLEAR, 0x243214) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SI20_MASK_CLEAR, DSP_SI00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_SO00_BASE, 0x00243400, 0x00243414) +RegFunc(AUD_DSP_ESR_SO00, 0x00243400, AUD_DSP_ESR_SO00_INT_STATUS, 0x0, AUD_DSP_ESR_SO00_INT_STATUS, 0x243400) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_STATUS, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO00, 0x00243400, AUD_DSP_ESR_SO00_INT_SET, 0x4, AUD_DSP_ESR_SO00_INT_SET, 0x243404) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_SET, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO00, 0x00243400, AUD_DSP_ESR_SO00_INT_CLEAR, 0x8, AUD_DSP_ESR_SO00_INT_CLEAR, 0x243408) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO00_INT_CLEAR, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO00, 0x00243400, AUD_DSP_ESR_SO00_MASK_STATUS, 0xc, AUD_DSP_ESR_SO00_MASK_STATUS, 0x24340c) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_STATUS, DSP_SO00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SO00, 0x00243400, AUD_DSP_ESR_SO00_MASK_SET, 0x10, AUD_DSP_ESR_SO00_MASK_SET, 0x243410) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_SET, DSP_SO00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SO00, 0x00243400, AUD_DSP_ESR_SO00_MASK_CLEAR, 0x14, AUD_DSP_ESR_SO00_MASK_CLEAR, 0x243414) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO00_MASK_CLEAR, DSP_SO00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_SO10_BASE, 0x00243500, 0x00243514) +RegFunc(AUD_DSP_ESR_SO10, 0x00243500, AUD_DSP_ESR_SO10_INT_STATUS, 0x0, AUD_DSP_ESR_SO10_INT_STATUS, 0x243500) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_STATUS, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO10, 0x00243500, AUD_DSP_ESR_SO10_INT_SET, 0x4, AUD_DSP_ESR_SO10_INT_SET, 0x243504) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_SET, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO10, 0x00243500, AUD_DSP_ESR_SO10_INT_CLEAR, 0x8, AUD_DSP_ESR_SO10_INT_CLEAR, 0x243508) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO10_INT_CLEAR, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO10, 0x00243500, AUD_DSP_ESR_SO10_MASK_STATUS, 0xc, AUD_DSP_ESR_SO10_MASK_STATUS, 0x24350c) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_STATUS, DSP_SO00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SO10, 0x00243500, AUD_DSP_ESR_SO10_MASK_SET, 0x10, AUD_DSP_ESR_SO10_MASK_SET, 0x243510) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_SET, DSP_SO00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SO10, 0x00243500, AUD_DSP_ESR_SO10_MASK_CLEAR, 0x14, AUD_DSP_ESR_SO10_MASK_CLEAR, 0x243514) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO10_MASK_CLEAR, DSP_SO00_MASK, 0, 1) + +RegAreaFunc(AUD_DSP_ESR_SO20_BASE, 0x00243600, 0x00243614) +RegFunc(AUD_DSP_ESR_SO20, 0x00243600, AUD_DSP_ESR_SO20_INT_STATUS, 0x0, AUD_DSP_ESR_SO20_INT_STATUS, 0x243600) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_STATUS, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO20, 0x00243600, AUD_DSP_ESR_SO20_INT_SET, 0x4, AUD_DSP_ESR_SO20_INT_SET, 0x243604) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_SET, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO20, 0x00243600, AUD_DSP_ESR_SO20_INT_CLEAR, 0x8, AUD_DSP_ESR_SO20_INT_CLEAR, 0x243608) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO31_INTRDS, 31, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO30_INTRDS, 30, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO29_INTRDS, 29, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO28_INTRDS, 28, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO27_INTRDS, 27, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO26_INTRDS, 26, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO25_INTRDS, 25, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO24_INTRDS, 24, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO23_INTRDS, 23, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO22_INTRDS, 22, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO21_INTRDS, 21, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO20_INTRDS, 20, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO19_INTRDS, 19, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO18_INTRDS, 18, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO17_INTRDS, 17, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO16_INTRDS, 16, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO15_INTRDS, 15, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO14_INTRDS, 14, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO13_INTRDS, 13, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO12_INTRDS, 12, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO11_INTRDS, 11, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO10_INTRDS, 10, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO09_INTRDS, 9, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO08_INTRDS, 8, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO07_INTRDS, 7, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO06_INTRDS, 6, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO05_INTRDS, 5, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO04_INTRDS, 4, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO03_INTRDS, 3, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO02_INTRDS, 2, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO01_INTRDS, 1, 1) + FldFunc(AUD_DSP_ESR_SO20_INT_CLEAR, DSP_SO00_INTRDS, 0, 1) +RegFunc(AUD_DSP_ESR_SO20, 0x00243600, AUD_DSP_ESR_SO20_MASK_STATUS, 0xc, AUD_DSP_ESR_SO20_MASK_STATUS, 0x24360c) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_STATUS, DSP_SO00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SO20, 0x00243600, AUD_DSP_ESR_SO20_MASK_SET, 0x10, AUD_DSP_ESR_SO20_MASK_SET, 0x243610) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_SET, DSP_SO00_MASK, 0, 1) +RegFunc(AUD_DSP_ESR_SO20, 0x00243600, AUD_DSP_ESR_SO20_MASK_CLEAR, 0x14, AUD_DSP_ESR_SO20_MASK_CLEAR, 0x243614) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO31_MASK, 31, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO30_MASK, 30, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO29_MASK, 29, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO28_MASK, 28, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO27_MASK, 27, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO26_MASK, 26, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO25_MASK, 25, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO24_MASK, 24, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO23_MASK, 23, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO22_MASK, 22, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO21_MASK, 21, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO20_MASK, 20, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO19_MASK, 19, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO18_MASK, 18, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO17_MASK, 17, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO16_MASK, 16, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO15_MASK, 15, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO14_MASK, 14, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO13_MASK, 13, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO12_MASK, 12, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO11_MASK, 11, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO10_MASK, 10, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO09_MASK, 9, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO08_MASK, 8, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO07_MASK, 7, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO06_MASK, 6, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO05_MASK, 5, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO04_MASK, 4, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO03_MASK, 3, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO02_MASK, 2, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO01_MASK, 1, 1) + FldFunc(AUD_DSP_ESR_SO20_MASK_CLEAR, DSP_SO00_MASK, 0, 1) + +RegAreaFunc(AIO_MISC_BASE, 0x00260000, 0x0026000c) +RegFunc(AIO_MISC, 0x00260000, AIO_MISC_REVISION, 0x0, AIO_MISC_REVISION, 0x260000) + FldFunc(AIO_MISC_REVISION, MAJOR, 8, 8) + FldFunc(AIO_MISC_REVISION, MINOR, 0, 8) +RegFunc(AIO_MISC, 0x00260000, AIO_MISC_RESET, 0x4, AIO_MISC_RESET, 0x260004) + FldFunc(AIO_MISC_RESET, RESET_FMM_B, 2, 1) +RegFunc(AIO_MISC, 0x00260000, AIO_MISC_TPMUX, 0x8, AIO_MISC_TPMUX, 0x260008) + +RegAreaFunc(AIO_INTH_BASE, 0x00260800, 0x0026082c) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_R5F_STATUS, 0x0, AIO_INTH_R5F_STATUS, 0x260800) + FldFunc(AIO_INTH_R5F_STATUS, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_R5F_STATUS, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_R5F_STATUS, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_R5F_STATUS, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_R5F_STATUS, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_R5F_SET, 0x4, AIO_INTH_R5F_SET, 0x260804) + FldFunc(AIO_INTH_R5F_SET, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_R5F_SET, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_R5F_SET, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_R5F_SET, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_R5F_SET, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_R5F_CLEAR, 0x8, AIO_INTH_R5F_CLEAR, 0x260808) + FldFunc(AIO_INTH_R5F_CLEAR, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_R5F_CLEAR, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_R5F_CLEAR, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_R5F_CLEAR, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_R5F_CLEAR, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_R5F_MASK_STATUS, 0xc, AIO_INTH_R5F_MASK_STATUS, 0x26080c) + FldFunc(AIO_INTH_R5F_MASK_STATUS, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_R5F_MASK_STATUS, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_R5F_MASK_STATUS, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_R5F_MASK_STATUS, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_R5F_MASK_STATUS, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_R5F_MASK_SET, 0x10, AIO_INTH_R5F_MASK_SET, 0x260810) + FldFunc(AIO_INTH_R5F_MASK_SET, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_R5F_MASK_SET, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_R5F_MASK_SET, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_R5F_MASK_SET, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_R5F_MASK_SET, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_R5F_MASK_CLEAR, 0x14, AIO_INTH_R5F_MASK_CLEAR, 0x260814) + FldFunc(AIO_INTH_R5F_MASK_CLEAR, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_R5F_MASK_CLEAR, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_R5F_MASK_CLEAR, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_R5F_MASK_CLEAR, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_R5F_MASK_CLEAR, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_PCI_STATUS, 0x18, AIO_INTH_PCI_STATUS, 0x260818) + FldFunc(AIO_INTH_PCI_STATUS, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_PCI_STATUS, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_PCI_STATUS, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_PCI_STATUS, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_PCI_STATUS, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_PCI_SET, 0x1c, AIO_INTH_PCI_SET, 0x26081c) + FldFunc(AIO_INTH_PCI_SET, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_PCI_SET, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_PCI_SET, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_PCI_SET, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_PCI_SET, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_PCI_CLEAR, 0x20, AIO_INTH_PCI_CLEAR, 0x260820) + FldFunc(AIO_INTH_PCI_CLEAR, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_PCI_CLEAR, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_PCI_CLEAR, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_PCI_CLEAR, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_PCI_CLEAR, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_PCI_MASK_STATUS, 0x24, AIO_INTH_PCI_MASK_STATUS, 0x260824) + FldFunc(AIO_INTH_PCI_MASK_STATUS, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_PCI_MASK_STATUS, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_PCI_MASK_STATUS, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_PCI_MASK_STATUS, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_PCI_MASK_STATUS, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_PCI_MASK_SET, 0x28, AIO_INTH_PCI_MASK_SET, 0x260828) + FldFunc(AIO_INTH_PCI_MASK_SET, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_PCI_MASK_SET, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_PCI_MASK_SET, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_PCI_MASK_SET, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_PCI_MASK_SET, FMM_OPFM, 0, 1) +RegFunc(AIO_INTH, 0x00260800, AIO_INTH_PCI_MASK_CLEAR, 0x2c, AIO_INTH_PCI_MASK_CLEAR, 0x26082c) + FldFunc(AIO_INTH_PCI_MASK_CLEAR, FMM_BFFM, 4, 1) + FldFunc(AIO_INTH_PCI_MASK_CLEAR, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTH_PCI_MASK_CLEAR, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTH_PCI_MASK_CLEAR, FMM_MSFM, 1, 1) + FldFunc(AIO_INTH_PCI_MASK_CLEAR, FMM_OPFM, 0, 1) + +RegAreaFunc(AIO_INTD0_BASE, 0x00260a00, 0x00260a14) +RegFunc(AIO_INTD0, 0x00260a00, AIO_INTD0_INT_STATUS, 0x0, AIO_INTD0_INT_STATUS, 0x260a00) + FldFunc(AIO_INTD0_INT_STATUS, FMM_BFFM, 4, 1) + FldFunc(AIO_INTD0_INT_STATUS, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTD0_INT_STATUS, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTD0_INT_STATUS, FMM_MSFM, 1, 1) + FldFunc(AIO_INTD0_INT_STATUS, FMM_OPFM, 0, 1) +RegFunc(AIO_INTD0, 0x00260a00, AIO_INTD0_INT_SET, 0x4, AIO_INTD0_INT_SET, 0x260a04) + FldFunc(AIO_INTD0_INT_SET, FMM_BFFM, 4, 1) + FldFunc(AIO_INTD0_INT_SET, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTD0_INT_SET, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTD0_INT_SET, FMM_MSFM, 1, 1) + FldFunc(AIO_INTD0_INT_SET, FMM_OPFM, 0, 1) +RegFunc(AIO_INTD0, 0x00260a00, AIO_INTD0_INT_CLEAR, 0x8, AIO_INTD0_INT_CLEAR, 0x260a08) + FldFunc(AIO_INTD0_INT_CLEAR, FMM_BFFM, 4, 1) + FldFunc(AIO_INTD0_INT_CLEAR, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTD0_INT_CLEAR, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTD0_INT_CLEAR, FMM_MSFM, 1, 1) + FldFunc(AIO_INTD0_INT_CLEAR, FMM_OPFM, 0, 1) +RegFunc(AIO_INTD0, 0x00260a00, AIO_INTD0_MASK_STATUS, 0xc, AIO_INTD0_MASK_STATUS, 0x260a0c) + FldFunc(AIO_INTD0_MASK_STATUS, FMM_BFFM, 4, 1) + FldFunc(AIO_INTD0_MASK_STATUS, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTD0_MASK_STATUS, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTD0_MASK_STATUS, FMM_MSFM, 1, 1) + FldFunc(AIO_INTD0_MASK_STATUS, FMM_OPFM, 0, 1) +RegFunc(AIO_INTD0, 0x00260a00, AIO_INTD0_MASK_SET, 0x10, AIO_INTD0_MASK_SET, 0x260a10) + FldFunc(AIO_INTD0_MASK_SET, FMM_BFFM, 4, 1) + FldFunc(AIO_INTD0_MASK_SET, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTD0_MASK_SET, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTD0_MASK_SET, FMM_MSFM, 1, 1) + FldFunc(AIO_INTD0_MASK_SET, FMM_OPFM, 0, 1) +RegFunc(AIO_INTD0, 0x00260a00, AIO_INTD0_MASK_CLEAR, 0x14, AIO_INTD0_MASK_CLEAR, 0x260a14) + FldFunc(AIO_INTD0_MASK_CLEAR, FMM_BFFM, 4, 1) + FldFunc(AIO_INTD0_MASK_CLEAR, FMM_DP0FM, 3, 1) + FldFunc(AIO_INTD0_MASK_CLEAR, FMM_DP1FM, 2, 1) + FldFunc(AIO_INTD0_MASK_CLEAR, FMM_MSFM, 1, 1) + FldFunc(AIO_INTD0_MASK_CLEAR, FMM_OPFM, 0, 1) + +RegAreaFunc(AUD_FMM_MISC_BASE, 0x00270000, 0x002700f8) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_REVISION, 0x0, AUD_FMM_MISC_REVISION, 0x270000) + FldFunc(AUD_FMM_MISC_REVISION, MAJOR, 8, 8) + FldFunc(AUD_FMM_MISC_REVISION, MINOR, 0, 8) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_RESET, 0x4, AUD_FMM_MISC_RESET, 0x270004) + FldFunc(AUD_FMM_MISC_RESET, FMM_MS_OPER_ENABLE, 26, 1) + FldFunc(AUD_FMM_MISC_RESET, FMM_DP_OPER_ENABLE, 25, 1) + FldFunc(AUD_FMM_MISC_RESET, FMM_BF_OPER_ENABLE, 24, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_TOP_LOGIC_B, 16, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_OP_LOGIC_B, 13, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_OP_REGS_B, 12, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_MS_PROC_B, 10, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_MS_LOGIC_B, 9, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_MS_REGS_B, 8, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_DP_LOGIC_B, 5, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_DP_REGS_B, 4, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_BF_LOGIC_B, 1, 1) + FldFunc(AUD_FMM_MISC_RESET, RESET_BF_REGS_B, 0, 1) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_TEST_CTRL, 0x8, AUD_FMM_MISC_TEST_CTRL, 0x270008) + FldFunc(AUD_FMM_MISC_TEST_CTRL, DP_ARB_SMD, 10, 2) + FldFunc(AUD_FMM_MISC_TEST_CTRL, RESET_DP_ARB_SM, 8, 1) + FldFunc(AUD_FMM_MISC_TEST_CTRL, DIAG_SEL, 0, 3) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_STC_UPPER, 0x80, AUD_FMM_MISC_STC_UPPER, 0x270080) + FldFunc(AUD_FMM_MISC_STC_UPPER, STC_COUNT_UPPER, 0, 32) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_SEROUT_SEL, 0xf0, AUD_FMM_MISC_SEROUT_SEL, 0x2700f0) + FldFunc(AUD_FMM_MISC_SEROUT_SEL, SHARED, 31, 1) + FldFunc(AUD_FMM_MISC_SEROUT_SEL, SEROUT3_SEL, 12, 2) + FldFunc(AUD_FMM_MISC_SEROUT_SEL, SEROUT2_SEL, 8, 2) + FldFunc(AUD_FMM_MISC_SEROUT_SEL, SEROUT1_SEL, 4, 2) + FldFunc(AUD_FMM_MISC_SEROUT_SEL, SEROUT0_SEL, 0, 2) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_SEROUT_OE, 0xf4, AUD_FMM_MISC_SEROUT_OE, 0x2700f4) + FldFunc(AUD_FMM_MISC_SEROUT_OE, LRCK3_OE, 14, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SCLK3_OE, 13, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SDAT3_OE, 12, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, LRCK2_OE, 10, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SCLK2_OE, 9, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SDAT2_OE, 8, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, LRCK1_OE, 6, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SCLK1_OE, 5, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SDAT1_OE, 4, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, LRCK0_OE, 2, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SCLK0_OE, 1, 1) + FldFunc(AUD_FMM_MISC_SEROUT_OE, SDAT0_OE, 0, 1) +RegFunc(AUD_FMM_MISC, 0x00270000, AUD_FMM_MISC_SERIN_SEL, 0xf8, AUD_FMM_MISC_SERIN_SEL, 0x2700f8) + FldFunc(AUD_FMM_MISC_SERIN_SEL, SOURCE1, 4, 3) + FldFunc(AUD_FMM_MISC_SERIN_SEL, SOURCE0, 0, 3) + +RegAreaFunc(AUD_FMM_BF_CTRL_BASE, 0x00271000, 0x0027157c) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_PROCSEQID_0_3, 0x0, AUD_FMM_BF_CTRL_PROCSEQID_0_3, 0x271000) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID3_VALID, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, BLOCKED_ACCESS_3_DISABLE, 30, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_ID3_HIGH, 29, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID_3, 24, 5) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID2_VALID, 23, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, BLOCKED_ACCESS_2_DISABLE, 22, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_ID2_HIGH, 21, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID_2, 16, 5) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID1_VALID, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, BLOCKED_ACCESS_1_DISABLE, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_ID1_HIGH, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID_1, 8, 5) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID0_VALID, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, BLOCKED_ACCESS_0_DISABLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_ID0_HIGH, 5, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_0_3, PROCESS_SEQ_ID_0, 0, 5) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_PROCSEQID_4_7, 0x4, AUD_FMM_BF_CTRL_PROCSEQID_4_7, 0x271004) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID7_VALID, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, BLOCKED_ACCESS_7_DISABLE, 30, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_ID7_HIGH, 29, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID_7, 24, 5) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID6_VALID, 23, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, BLOCKED_ACCESS_6_DISABLE, 22, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_ID6_HIGH, 21, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID_6, 16, 5) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID5_VALID, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, BLOCKED_ACCESS_5_DISABLE, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_ID5_HIGH, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID_5, 8, 5) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID4_VALID, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, BLOCKED_ACCESS_4_DISABLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_ID4_HIGH, 5, 1) + FldFunc(AUD_FMM_BF_CTRL_PROCSEQID_4_7, PROCESS_SEQ_ID_4, 0, 5) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_BLOCKCNT_RESET_PERIOD, 0x8, AUD_FMM_BF_CTRL_BLOCKCNT_RESET_PERIOD, 0x271008) + FldFunc(AUD_FMM_BF_CTRL_BLOCKCNT_RESET_PERIOD, BLOCKCNT_RESET_PERIOD, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, 0xc, AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, 0x27100c) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_7, 28, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_6, 24, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_5, 20, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_4, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_3, 12, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_2, 8, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_1, 4, 4) + FldFunc(AUD_FMM_BF_CTRL_DMA_BLOCK_CNT_0_7, DMA_BLOCK_CNT_0, 0, 4) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_0_CFG, 0x10, AUD_FMM_BF_CTRL_SOURCECH_0_CFG, 0x271010) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, REVERSE_ENDIAN, 25, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, BIT_RESOLUTION, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, SHARED_SBUF_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, SHARE_SBUF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, FLOWON_SFIFO_HALFFULL, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, DMA_READ_DISABLE, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, SAMPLE_REPEAT_ENABLE, 12, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, NOT_PAUSE_WHEN_EMPTY, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, STC_OFFSET_SELECT, 8, 3) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, STCSYNC_ENABLE, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, SOURCEFIFO_SIZE_DOUBLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, LR_DATA_CTRL, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, SAMPLE_CH_MODE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CFG, SOURCEFIFO_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_0_CTRL, 0x14, AUD_FMM_BF_CTRL_SOURCECH_0_CTRL, 0x271014) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CTRL, START_SELECTION, 1, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_0_CTRL, PLAY_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_1_CFG, 0x18, AUD_FMM_BF_CTRL_SOURCECH_1_CFG, 0x271018) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, REVERSE_ENDIAN, 25, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, BIT_RESOLUTION, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, SHARED_SBUF_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, SHARE_SBUF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, FLOWON_SFIFO_HALFFULL, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, DMA_READ_DISABLE, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, SAMPLE_REPEAT_ENABLE, 12, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, NOT_PAUSE_WHEN_EMPTY, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, STC_OFFSET_SELECT, 8, 3) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, STCSYNC_ENABLE, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, SOURCEFIFO_SIZE_DOUBLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, LR_DATA_CTRL, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, SAMPLE_CH_MODE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CFG, SOURCEFIFO_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_1_CTRL, 0x1c, AUD_FMM_BF_CTRL_SOURCECH_1_CTRL, 0x27101c) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CTRL, START_SELECTION, 1, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_1_CTRL, PLAY_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_2_CFG, 0x20, AUD_FMM_BF_CTRL_SOURCECH_2_CFG, 0x271020) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, REVERSE_ENDIAN, 25, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, BIT_RESOLUTION, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, SHARED_SBUF_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, SHARE_SBUF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, FLOWON_SFIFO_HALFFULL, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, DMA_READ_DISABLE, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, SAMPLE_REPEAT_ENABLE, 12, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, NOT_PAUSE_WHEN_EMPTY, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, STC_OFFSET_SELECT, 8, 3) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, STCSYNC_ENABLE, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, SOURCEFIFO_SIZE_DOUBLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, LR_DATA_CTRL, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, SAMPLE_CH_MODE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CFG, SOURCEFIFO_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_2_CTRL, 0x24, AUD_FMM_BF_CTRL_SOURCECH_2_CTRL, 0x271024) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CTRL, START_SELECTION, 1, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_2_CTRL, PLAY_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_3_CFG, 0x28, AUD_FMM_BF_CTRL_SOURCECH_3_CFG, 0x271028) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, REVERSE_ENDIAN, 25, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, BIT_RESOLUTION, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, SHARED_SBUF_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, SHARE_SBUF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, FLOWON_SFIFO_HALFFULL, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, DMA_READ_DISABLE, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, SAMPLE_REPEAT_ENABLE, 12, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, NOT_PAUSE_WHEN_EMPTY, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, STC_OFFSET_SELECT, 8, 3) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, STCSYNC_ENABLE, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, SOURCEFIFO_SIZE_DOUBLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, LR_DATA_CTRL, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, SAMPLE_CH_MODE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CFG, SOURCEFIFO_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_3_CTRL, 0x2c, AUD_FMM_BF_CTRL_SOURCECH_3_CTRL, 0x27102c) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CTRL, START_SELECTION, 1, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_3_CTRL, PLAY_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_4_CFG, 0x30, AUD_FMM_BF_CTRL_SOURCECH_4_CFG, 0x271030) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, REVERSE_ENDIAN, 25, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, BIT_RESOLUTION, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, SHARED_SBUF_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, SHARE_SBUF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, FLOWON_SFIFO_HALFFULL, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, DMA_READ_DISABLE, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, SAMPLE_REPEAT_ENABLE, 12, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, NOT_PAUSE_WHEN_EMPTY, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, STC_OFFSET_SELECT, 8, 3) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, STCSYNC_ENABLE, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, SOURCEFIFO_SIZE_DOUBLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, LR_DATA_CTRL, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, SAMPLE_CH_MODE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CFG, SOURCEFIFO_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_4_CTRL, 0x34, AUD_FMM_BF_CTRL_SOURCECH_4_CTRL, 0x271034) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CTRL, START_SELECTION, 1, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_4_CTRL, PLAY_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_5_CFG, 0x38, AUD_FMM_BF_CTRL_SOURCECH_5_CFG, 0x271038) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, REVERSE_ENDIAN, 25, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, BIT_RESOLUTION, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, SHARED_SBUF_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, SHARE_SBUF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, FLOWON_SFIFO_HALFFULL, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, DMA_READ_DISABLE, 13, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, SAMPLE_REPEAT_ENABLE, 12, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, NOT_PAUSE_WHEN_EMPTY, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, STC_OFFSET_SELECT, 8, 3) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, STCSYNC_ENABLE, 7, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, SOURCEFIFO_SIZE_DOUBLE, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, LR_DATA_CTRL, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, SAMPLE_CH_MODE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CFG, SOURCEFIFO_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCECH_5_CTRL, 0x3c, AUD_FMM_BF_CTRL_SOURCECH_5_CTRL, 0x27103c) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CTRL, START_SELECTION, 1, 2) + FldFunc(AUD_FMM_BF_CTRL_SOURCECH_5_CTRL, PLAY_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DESTCH_0_CFG, 0x40, AUD_FMM_BF_CTRL_DESTCH_0_CFG, 0x271040) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, I2S_BITS_PER_SAMPLE, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, I2S_DATA_JUSTIFICATION, 19, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, I2S_DATA_ALIGNMENT, 18, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, I2S_SCLK_POLARITY, 17, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, I2S_LRCK_POLARITY, 16, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, REVERSE_ENDIAN, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, I2S_MAI_SELI2, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, INPUT_PORT_SEL, 12, 2) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, NOT_PAUSE_WHEN_FULL, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, SOURCE_FIFO_ID, 7, 4) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, INPUT_FRM_SOURCEFIFO, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, CAPTURE_TO_SOURCEFIFO, 5, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, PLAY_FROM_CAPTURE, 4, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, DESTFIFO_SIZE_DOUBLE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CFG, CAPTURE_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DESTCH_0_CTRL, 0x44, AUD_FMM_BF_CTRL_DESTCH_0_CTRL, 0x271044) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_0_CTRL, CAPTURE_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DESTCH_1_CFG, 0x48, AUD_FMM_BF_CTRL_DESTCH_1_CFG, 0x271048) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, I2S_BITS_PER_SAMPLE, 20, 5) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, I2S_DATA_JUSTIFICATION, 19, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, I2S_DATA_ALIGNMENT, 18, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, I2S_SCLK_POLARITY, 17, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, I2S_LRCK_POLARITY, 16, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, REVERSE_ENDIAN, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, I2S_MAI_SELI2, 14, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, INPUT_PORT_SEL, 12, 2) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, NOT_PAUSE_WHEN_FULL, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, SOURCE_FIFO_ID, 7, 4) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, INPUT_FRM_SOURCEFIFO, 6, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, CAPTURE_TO_SOURCEFIFO, 5, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, PLAY_FROM_CAPTURE, 4, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, DESTFIFO_SIZE_DOUBLE, 3, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, BUFFER_PAIR_ENABLE, 2, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CFG, CAPTURE_ENABLE, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DESTCH_1_CTRL, 0x4c, AUD_FMM_BF_CTRL_DESTCH_1_CTRL, 0x27104c) + FldFunc(AUD_FMM_BF_CTRL_DESTCH_1_CTRL, CAPTURE_RUN, 0, 1) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_STCSYNC_CTRL, 0x50, AUD_FMM_BF_CTRL_STCSYNC_CTRL, 0x271050) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_3_ENABLE, 11, 1) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_2_ENABLE, 10, 1) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_1_ENABLE, 9, 1) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_0_ENABLE, 8, 1) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_3_SEL0, 6, 2) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_2_SEL0, 4, 2) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_1_SEL0, 2, 2) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_CTRL, STCSYNC_0_SEL0, 0, 2) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_0, 0x54, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_0, 0x271054) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_OFFSET_0, STCSYNC_OFFSET, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_1, 0x58, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_1, 0x271058) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_OFFSET_1, STCSYNC_OFFSET, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_2, 0x5c, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_2, 0x27105c) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_OFFSET_2, STCSYNC_OFFSET, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_3, 0x60, AUD_FMM_BF_CTRL_STCSYNC_OFFSET_3, 0x271060) + FldFunc(AUD_FMM_BF_CTRL_STCSYNC_OFFSET_3, STCSYNC_OFFSET, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_ADAPTRATE_0_CFG, 0x64, AUD_FMM_BF_CTRL_ADAPTRATE_0_CFG, 0x271064) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_0_CFG, ADAPTIVE_RATE_ENABLE, 23, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_0_CFG, ADAPTIVE_CAP_SEL, 20, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_0_CFG, ADAPTIVE_SFIFO_SEL, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_0_CFG, ADAPTIVE_RATE_THRESHOLD, 0, 16) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_ADAPTRATE_1_CFG, 0x68, AUD_FMM_BF_CTRL_ADAPTRATE_1_CFG, 0x271068) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_1_CFG, ADAPTIVE_RATE_ENABLE, 23, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_1_CFG, ADAPTIVE_CAP_SEL, 20, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_1_CFG, ADAPTIVE_SFIFO_SEL, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_1_CFG, ADAPTIVE_RATE_THRESHOLD, 0, 16) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_ADAPTRATE_2_CFG, 0x6c, AUD_FMM_BF_CTRL_ADAPTRATE_2_CFG, 0x27106c) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_2_CFG, ADAPTIVE_RATE_ENABLE, 23, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_2_CFG, ADAPTIVE_CAP_SEL, 20, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_2_CFG, ADAPTIVE_SFIFO_SEL, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_2_CFG, ADAPTIVE_RATE_THRESHOLD, 0, 16) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_ADAPTRATE_3_CFG, 0x70, AUD_FMM_BF_CTRL_ADAPTRATE_3_CFG, 0x271070) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_3_CFG, ADAPTIVE_RATE_ENABLE, 23, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_3_CFG, ADAPTIVE_CAP_SEL, 20, 1) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_3_CFG, ADAPTIVE_SFIFO_SEL, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_ADAPTRATE_3_CFG, ADAPTIVE_RATE_THRESHOLD, 0, 16) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCEFIFO_0_RWADDR, 0x74, AUD_FMM_BF_CTRL_SOURCEFIFO_0_RWADDR, 0x271074) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_0_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_0_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_0_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_0_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCEFIFO_1_RWADDR, 0x78, AUD_FMM_BF_CTRL_SOURCEFIFO_1_RWADDR, 0x271078) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_1_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_1_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_1_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_1_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCEFIFO_2_RWADDR, 0x7c, AUD_FMM_BF_CTRL_SOURCEFIFO_2_RWADDR, 0x27107c) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_2_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_2_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_2_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_2_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCEFIFO_3_RWADDR, 0x80, AUD_FMM_BF_CTRL_SOURCEFIFO_3_RWADDR, 0x271080) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_3_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_3_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_3_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_3_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCEFIFO_4_RWADDR, 0x84, AUD_FMM_BF_CTRL_SOURCEFIFO_4_RWADDR, 0x271084) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_4_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_4_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_4_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_4_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_SOURCEFIFO_5_RWADDR, 0x88, AUD_FMM_BF_CTRL_SOURCEFIFO_5_RWADDR, 0x271088) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_5_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_5_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_5_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_SOURCEFIFO_5_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DESTFIFO_0_RWADDR, 0x8c, AUD_FMM_BF_CTRL_DESTFIFO_0_RWADDR, 0x27108c) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_0_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_0_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_0_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_0_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_DESTFIFO_1_RWADDR, 0x90, AUD_FMM_BF_CTRL_DESTFIFO_1_RWADDR, 0x271090) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_1_RWADDR, FIFO_WRADDR_WRAPFIF, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_1_RWADDR, FIFO_WRADDRFIF, 16, 15) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_1_RWADDR, FIFO_RDADDR_WRAPFIF, 15, 1) + FldFunc(AUD_FMM_BF_CTRL_DESTFIFO_1_RWADDR, FIFO_RDADDRFIF, 0, 15) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RATECNT_SCH_0TO1, 0x94, AUD_FMM_BF_CTRL_RATECNT_SCH_0TO1, 0x271094) + FldFunc(AUD_FMM_BF_CTRL_RATECNT_SCH_0TO1, RATECNT_SOURCH_1, 16, 16) + FldFunc(AUD_FMM_BF_CTRL_RATECNT_SCH_0TO1, RATECNT_SOURCH_0, 0, 16) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RATECNT_SCH_2TO3, 0x98, AUD_FMM_BF_CTRL_RATECNT_SCH_2TO3, 0x271098) + FldFunc(AUD_FMM_BF_CTRL_RATECNT_SCH_2TO3, RATECNT_SOURCH_3, 16, 16) + FldFunc(AUD_FMM_BF_CTRL_RATECNT_SCH_2TO3, RATECNT_SOURCH_2, 0, 16) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FIFO_FLOWON_STAT, 0x9c, AUD_FMM_BF_CTRL_FIFO_FLOWON_STAT, 0x27109c) + FldFunc(AUD_FMM_BF_CTRL_FIFO_FLOWON_STAT, DEST_FIFO_FLOWON, 6, 2) + FldFunc(AUD_FMM_BF_CTRL_FIFO_FLOWON_STAT, SOURCE_FIFO_FLOWON, 0, 6) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_MAI_0_STAT, 0xa0, AUD_FMM_BF_CTRL_MAI_0_STAT, 0x2710a0) + FldFunc(AUD_FMM_BF_CTRL_MAI_0_STAT, AUD_SAMPLE_WIDTH, 24, 5) + FldFunc(AUD_FMM_BF_CTRL_MAI_0_STAT, AUD_VERSION, 20, 4) + FldFunc(AUD_FMM_BF_CTRL_MAI_0_STAT, AUD_STREAM_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_MAI_0_STAT, AUD_SAMPLING_RATE, 8, 8) + FldFunc(AUD_FMM_BF_CTRL_MAI_0_STAT, AUD_FORMAT, 0, 8) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_MAI_1_STAT, 0xa4, AUD_FMM_BF_CTRL_MAI_1_STAT, 0x2710a4) + FldFunc(AUD_FMM_BF_CTRL_MAI_1_STAT, AUD_SAMPLE_WIDTH, 24, 5) + FldFunc(AUD_FMM_BF_CTRL_MAI_1_STAT, AUD_VERSION, 20, 4) + FldFunc(AUD_FMM_BF_CTRL_MAI_1_STAT, AUD_STREAM_ID, 16, 4) + FldFunc(AUD_FMM_BF_CTRL_MAI_1_STAT, AUD_SAMPLING_RATE, 8, 8) + FldFunc(AUD_FMM_BF_CTRL_MAI_1_STAT, AUD_FORMAT, 0, 8) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_0_RDADDR, 0x400, AUD_FMM_BF_CTRL_RINGBUF_0_RDADDR, 0x271400) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_0_WRADDR, 0x404, AUD_FMM_BF_CTRL_RINGBUF_0_WRADDR, 0x271404) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_0_BASEADDR, 0x408, AUD_FMM_BF_CTRL_RINGBUF_0_BASEADDR, 0x271408) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_0_ENDADDR, 0x40c, AUD_FMM_BF_CTRL_RINGBUF_0_ENDADDR, 0x27140c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_0_FREEBYTE_MARK, 0x410, AUD_FMM_BF_CTRL_RINGBUF_0_FREEBYTE_MARK, 0x271410) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_0_START_WRPOINT, 0x414, AUD_FMM_BF_CTRL_RINGBUF_0_START_WRPOINT, 0x271414) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_0_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_1_RDADDR, 0x418, AUD_FMM_BF_CTRL_RINGBUF_1_RDADDR, 0x271418) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_1_WRADDR, 0x41c, AUD_FMM_BF_CTRL_RINGBUF_1_WRADDR, 0x27141c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_1_BASEADDR, 0x420, AUD_FMM_BF_CTRL_RINGBUF_1_BASEADDR, 0x271420) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_1_ENDADDR, 0x424, AUD_FMM_BF_CTRL_RINGBUF_1_ENDADDR, 0x271424) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_1_FREEBYTE_MARK, 0x428, AUD_FMM_BF_CTRL_RINGBUF_1_FREEBYTE_MARK, 0x271428) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_1_START_WRPOINT, 0x42c, AUD_FMM_BF_CTRL_RINGBUF_1_START_WRPOINT, 0x27142c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_1_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_2_RDADDR, 0x430, AUD_FMM_BF_CTRL_RINGBUF_2_RDADDR, 0x271430) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_2_WRADDR, 0x434, AUD_FMM_BF_CTRL_RINGBUF_2_WRADDR, 0x271434) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_2_BASEADDR, 0x438, AUD_FMM_BF_CTRL_RINGBUF_2_BASEADDR, 0x271438) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_2_ENDADDR, 0x43c, AUD_FMM_BF_CTRL_RINGBUF_2_ENDADDR, 0x27143c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_2_FREEBYTE_MARK, 0x440, AUD_FMM_BF_CTRL_RINGBUF_2_FREEBYTE_MARK, 0x271440) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_2_START_WRPOINT, 0x444, AUD_FMM_BF_CTRL_RINGBUF_2_START_WRPOINT, 0x271444) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_2_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_3_RDADDR, 0x448, AUD_FMM_BF_CTRL_RINGBUF_3_RDADDR, 0x271448) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_3_WRADDR, 0x44c, AUD_FMM_BF_CTRL_RINGBUF_3_WRADDR, 0x27144c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_3_BASEADDR, 0x450, AUD_FMM_BF_CTRL_RINGBUF_3_BASEADDR, 0x271450) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_3_ENDADDR, 0x454, AUD_FMM_BF_CTRL_RINGBUF_3_ENDADDR, 0x271454) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_3_FREEBYTE_MARK, 0x458, AUD_FMM_BF_CTRL_RINGBUF_3_FREEBYTE_MARK, 0x271458) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_3_START_WRPOINT, 0x45c, AUD_FMM_BF_CTRL_RINGBUF_3_START_WRPOINT, 0x27145c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_3_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_4_RDADDR, 0x460, AUD_FMM_BF_CTRL_RINGBUF_4_RDADDR, 0x271460) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_4_WRADDR, 0x464, AUD_FMM_BF_CTRL_RINGBUF_4_WRADDR, 0x271464) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_4_BASEADDR, 0x468, AUD_FMM_BF_CTRL_RINGBUF_4_BASEADDR, 0x271468) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_4_ENDADDR, 0x46c, AUD_FMM_BF_CTRL_RINGBUF_4_ENDADDR, 0x27146c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_4_FREEBYTE_MARK, 0x470, AUD_FMM_BF_CTRL_RINGBUF_4_FREEBYTE_MARK, 0x271470) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_4_START_WRPOINT, 0x474, AUD_FMM_BF_CTRL_RINGBUF_4_START_WRPOINT, 0x271474) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_4_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_5_RDADDR, 0x478, AUD_FMM_BF_CTRL_RINGBUF_5_RDADDR, 0x271478) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_5_WRADDR, 0x47c, AUD_FMM_BF_CTRL_RINGBUF_5_WRADDR, 0x27147c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_5_BASEADDR, 0x480, AUD_FMM_BF_CTRL_RINGBUF_5_BASEADDR, 0x271480) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_5_ENDADDR, 0x484, AUD_FMM_BF_CTRL_RINGBUF_5_ENDADDR, 0x271484) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_5_FREEBYTE_MARK, 0x488, AUD_FMM_BF_CTRL_RINGBUF_5_FREEBYTE_MARK, 0x271488) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_5_START_WRPOINT, 0x48c, AUD_FMM_BF_CTRL_RINGBUF_5_START_WRPOINT, 0x27148c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_5_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_6_RDADDR, 0x490, AUD_FMM_BF_CTRL_RINGBUF_6_RDADDR, 0x271490) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_RDADDR, DEST_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_RDADDR, DEST_RING_RDADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_6_WRADDR, 0x494, AUD_FMM_BF_CTRL_RINGBUF_6_WRADDR, 0x271494) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_WRADDR, DEST_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_WRADDR, DEST_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_6_BASEADDR, 0x498, AUD_FMM_BF_CTRL_RINGBUF_6_BASEADDR, 0x271498) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_BASEADDR, DEST_RINGBUF_BASEADDR, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_6_ENDADDR, 0x49c, AUD_FMM_BF_CTRL_RINGBUF_6_ENDADDR, 0x27149c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_ENDADDR, DEST_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_6_FULLBYTE_MARK, 0x4a0, AUD_FMM_BF_CTRL_RINGBUF_6_FULLBYTE_MARK, 0x2714a0) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_6_FULLBYTE_MARK, DEST_RINGBUF_FULLBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_0, 0x4a4, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_0, 0x2714a4) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_7_RDADDR, 0x4a8, AUD_FMM_BF_CTRL_RINGBUF_7_RDADDR, 0x2714a8) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_RDADDR, DEST_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_RDADDR, DEST_RING_RDADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_7_WRADDR, 0x4ac, AUD_FMM_BF_CTRL_RINGBUF_7_WRADDR, 0x2714ac) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_WRADDR, DEST_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_WRADDR, DEST_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_7_BASEADDR, 0x4b0, AUD_FMM_BF_CTRL_RINGBUF_7_BASEADDR, 0x2714b0) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_BASEADDR, DEST_RINGBUF_BASEADDR, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_7_ENDADDR, 0x4b4, AUD_FMM_BF_CTRL_RINGBUF_7_ENDADDR, 0x2714b4) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_ENDADDR, DEST_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_7_FULLBYTE_MARK, 0x4b8, AUD_FMM_BF_CTRL_RINGBUF_7_FULLBYTE_MARK, 0x2714b8) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_7_FULLBYTE_MARK, DEST_RINGBUF_FULLBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_1, 0x4bc, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_1, 0x2714bc) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_8_RDADDR, 0x4c0, AUD_FMM_BF_CTRL_RINGBUF_8_RDADDR, 0x2714c0) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_8_WRADDR, 0x4c4, AUD_FMM_BF_CTRL_RINGBUF_8_WRADDR, 0x2714c4) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_8_BASEADDR, 0x4c8, AUD_FMM_BF_CTRL_RINGBUF_8_BASEADDR, 0x2714c8) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_8_ENDADDR, 0x4cc, AUD_FMM_BF_CTRL_RINGBUF_8_ENDADDR, 0x2714cc) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_8_FREEBYTE_MARK, 0x4d0, AUD_FMM_BF_CTRL_RINGBUF_8_FREEBYTE_MARK, 0x2714d0) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_8_START_WRPOINT, 0x4d4, AUD_FMM_BF_CTRL_RINGBUF_8_START_WRPOINT, 0x2714d4) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_8_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_9_RDADDR, 0x4d8, AUD_FMM_BF_CTRL_RINGBUF_9_RDADDR, 0x2714d8) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_9_WRADDR, 0x4dc, AUD_FMM_BF_CTRL_RINGBUF_9_WRADDR, 0x2714dc) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_9_BASEADDR, 0x4e0, AUD_FMM_BF_CTRL_RINGBUF_9_BASEADDR, 0x2714e0) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_9_ENDADDR, 0x4e4, AUD_FMM_BF_CTRL_RINGBUF_9_ENDADDR, 0x2714e4) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_9_FREEBYTE_MARK, 0x4e8, AUD_FMM_BF_CTRL_RINGBUF_9_FREEBYTE_MARK, 0x2714e8) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_9_START_WRPOINT, 0x4ec, AUD_FMM_BF_CTRL_RINGBUF_9_START_WRPOINT, 0x2714ec) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_9_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_10_RDADDR, 0x4f0, AUD_FMM_BF_CTRL_RINGBUF_10_RDADDR, 0x2714f0) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_10_WRADDR, 0x4f4, AUD_FMM_BF_CTRL_RINGBUF_10_WRADDR, 0x2714f4) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_10_BASEADDR, 0x4f8, AUD_FMM_BF_CTRL_RINGBUF_10_BASEADDR, 0x2714f8) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_10_ENDADDR, 0x4fc, AUD_FMM_BF_CTRL_RINGBUF_10_ENDADDR, 0x2714fc) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_10_FREEBYTE_MARK, 0x500, AUD_FMM_BF_CTRL_RINGBUF_10_FREEBYTE_MARK, 0x271500) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_10_START_WRPOINT, 0x504, AUD_FMM_BF_CTRL_RINGBUF_10_START_WRPOINT, 0x271504) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_10_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_11_RDADDR, 0x508, AUD_FMM_BF_CTRL_RINGBUF_11_RDADDR, 0x271508) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_RDADDR, SOURCE_RING_RDADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_RDADDR, SRING_RDADD, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_11_WRADDR, 0x50c, AUD_FMM_BF_CTRL_RINGBUF_11_WRADDR, 0x27150c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_WRADDR, SOURCE_RING_WRADDR_WRAP, 31, 1) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_WRADDR, SOURCE_RING_WRADDR, 0, 31) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_11_BASEADDR, 0x510, AUD_FMM_BF_CTRL_RINGBUF_11_BASEADDR, 0x271510) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_BASEADDR, SOURCE_RINGBUF_BASEADD, 5, 27) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_11_ENDADDR, 0x514, AUD_FMM_BF_CTRL_RINGBUF_11_ENDADDR, 0x271514) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_ENDADDR, SOURCE_RINGBUF_ENDADDR, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_11_FREEBYTE_MARK, 0x518, AUD_FMM_BF_CTRL_RINGBUF_11_FREEBYTE_MARK, 0x271518) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_FREEBYTE_MARK, SOURCE_RINGBUF_FREEBYTE_MARK, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_RINGBUF_11_START_WRPOINT, 0x51c, AUD_FMM_BF_CTRL_RINGBUF_11_START_WRPOINT, 0x27151c) + FldFunc(AUD_FMM_BF_CTRL_RINGBUF_11_START_WRPOINT, SOURCE_RINGBUF_START_WRPOIN, 0, 32) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_2, 0x520, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_2, 0x271520) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_3, 0x524, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_3, 0x271524) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_4, 0x528, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_4, 0x271528) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_5, 0x52c, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_5, 0x27152c) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_6, 0x530, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_6, 0x271530) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_7, 0x534, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_7, 0x271534) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_8, 0x538, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_8, 0x271538) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_9, 0x53c, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_9, 0x27153c) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_10, 0x540, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_10, 0x271540) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_11, 0x544, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_11, 0x271544) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_12, 0x548, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_12, 0x271548) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_13, 0x54c, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_13, 0x27154c) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_14, 0x550, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_14, 0x271550) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_15, 0x554, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_15, 0x271554) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_16, 0x558, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_16, 0x271558) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_17, 0x55c, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_17, 0x27155c) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_18, 0x560, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_18, 0x271560) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_19, 0x564, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_19, 0x271564) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_20, 0x568, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_20, 0x271568) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_21, 0x56c, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_21, 0x27156c) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_22, 0x570, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_22, 0x271570) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_23, 0x574, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_23, 0x271574) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_24, 0x578, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_24, 0x271578) +RegFunc(AUD_FMM_BF_CTRL, 0x00271000, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_25, 0x57c, AUD_FMM_BF_CTRL_FMM_BF_RESERVE_ECO_25, 0x27157c) + +RegAreaFunc(AUD_FMM_BF_ESR0_BASE, 0x00271800, 0x00271814) +RegFunc(AUD_FMM_BF_ESR0, 0x00271800, AUD_FMM_BF_ESR0_STATUS, 0x0, AUD_FMM_BF_ESR0_STATUS, 0x271800) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_5_RD_REPEATORDRO, 29, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_4_RD_REPEATORDRO, 28, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_3_RD_REPEATORDRO, 27, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_2_RD_REPEATORDRO, 26, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_1_RD_REPEATORDRO, 25, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_0_RD_REPEATORDRO, 24, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, DEST_FIFO_1_OVERFLOW, 23, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, DEST_FIFO_0_OVERFLOW, 22, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_5_UNDERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_4_UNDERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, DEST_RINGBUF_1_OVERFLOW, 15, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, DEST_RINGBUF_0_OVERFLOW, 14, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_5_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_4_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, DEST_RINGBUF_1_EXCEED_FULLMARK, 7, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, DEST_RINGBUF_0_EXCEED_FULLMARK, 6, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_5_EXCEED_FREEMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_4_EXCEED_FREEMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR0, 0x00271800, AUD_FMM_BF_ESR0_STATUS_SET, 0x4, AUD_FMM_BF_ESR0_STATUS_SET, 0x271804) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_5_RD_REPEATORDRO, 29, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_4_RD_REPEATORDRO, 28, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_3_RD_REPEATORDRO, 27, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_2_RD_REPEATORDRO, 26, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_1_RD_REPEATORDRO, 25, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_0_RD_REPEATORDRO, 24, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, DEST_FIFO_1_OVERFLOW, 23, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, DEST_FIFO_0_OVERFLOW, 22, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_5_UNDERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_4_UNDERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, DEST_RINGBUF_1_OVERFLOW, 15, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, DEST_RINGBUF_0_OVERFLOW, 14, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_5_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_4_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, DEST_RINGBUF_1_EXCEED_FULLMARK, 7, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, DEST_RINGBUF_0_EXCEED_FULLMARK, 6, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_5_EXCEED_FREEMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_4_EXCEED_FREEMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_SET, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR0, 0x00271800, AUD_FMM_BF_ESR0_STATUS_CLEAR, 0x8, AUD_FMM_BF_ESR0_STATUS_CLEAR, 0x271808) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_5_RD_REPEATORDRO, 29, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_4_RD_REPEATORDRO, 28, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_3_RD_REPEATORDRO, 27, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_2_RD_REPEATORDRO, 26, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_1_RD_REPEATORDRO, 25, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_0_RD_REPEATORDRO, 24, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, DEST_FIFO_1_OVERFLOW, 23, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, DEST_FIFO_0_OVERFLOW, 22, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_5_UNDERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_4_UNDERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, DEST_RINGBUF_1_OVERFLOW, 15, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, DEST_RINGBUF_0_OVERFLOW, 14, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_5_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_4_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, DEST_RINGBUF_1_EXCEED_FULLMARK, 7, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, DEST_RINGBUF_0_EXCEED_FULLMARK, 6, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_5_EXCEED_FREEMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_4_EXCEED_FREEMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR0_STATUS_CLEAR, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR0, 0x00271800, AUD_FMM_BF_ESR0_MASK, 0xc, AUD_FMM_BF_ESR0_MASK, 0x27180c) + FldFunc(AUD_FMM_BF_ESR0_MASK, DEST_FIFO_1_OVERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, DEST_FIFO_0_OVERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, DEST_RINGBUF_1_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, DEST_RINGBUF_0_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, DEST_RINGBUF_1_EXCEED_FULLMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, DEST_RINGBUF_0_EXCEED_FULLMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR0, 0x00271800, AUD_FMM_BF_ESR0_MASK_SET, 0x10, AUD_FMM_BF_ESR0_MASK_SET, 0x271810) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, DEST_FIFO_1_OVERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, DEST_FIFO_0_OVERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, DEST_RINGBUF_1_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, DEST_RINGBUF_0_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, DEST_RINGBUF_1_EXCEED_FULLMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, DEST_RINGBUF_0_EXCEED_FULLMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_SET, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR0, 0x00271800, AUD_FMM_BF_ESR0_MASK_CLEAR, 0x14, AUD_FMM_BF_ESR0_MASK_CLEAR, 0x271814) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, DEST_FIFO_1_OVERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, DEST_FIFO_0_OVERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, DEST_RINGBUF_1_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, DEST_RINGBUF_0_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, DEST_RINGBUF_1_EXCEED_FULLMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, DEST_RINGBUF_0_EXCEED_FULLMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR0_MASK_CLEAR, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) + +RegAreaFunc(AUD_FMM_BF_ESR1_BASE, 0x00271840, 0x00271854) +RegFunc(AUD_FMM_BF_ESR1, 0x00271840, AUD_FMM_BF_ESR1_STATUS, 0x0, AUD_FMM_BF_ESR1_STATUS, 0x271840) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_5_RD_REPEATORDRO, 29, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_4_RD_REPEATORDRO, 28, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_3_RD_REPEATORDRO, 27, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_2_RD_REPEATORDRO, 26, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_1_RD_REPEATORDRO, 25, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_0_RD_REPEATORDRO, 24, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, DEST_FIFO_1_OVERFLOW, 23, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, DEST_FIFO_0_OVERFLOW, 22, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_5_UNDERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_4_UNDERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, DEST_RINGBUF_1_OVERFLOW, 15, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, DEST_RINGBUF_0_OVERFLOW, 14, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_5_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_4_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, DEST_RINGBUF_1_EXCEED_FULLMARK, 7, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, DEST_RINGBUF_0_EXCEED_FULLMARK, 6, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_5_EXCEED_FREEMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_4_EXCEED_FREEMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR1, 0x00271840, AUD_FMM_BF_ESR1_STATUS_SET, 0x4, AUD_FMM_BF_ESR1_STATUS_SET, 0x271844) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_5_RD_REPEATORDRO, 29, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_4_RD_REPEATORDRO, 28, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_3_RD_REPEATORDRO, 27, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_2_RD_REPEATORDRO, 26, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_1_RD_REPEATORDRO, 25, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_0_RD_REPEATORDRO, 24, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, DEST_FIFO_1_OVERFLOW, 23, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, DEST_FIFO_0_OVERFLOW, 22, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_5_UNDERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_4_UNDERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, DEST_RINGBUF_1_OVERFLOW, 15, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, DEST_RINGBUF_0_OVERFLOW, 14, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_5_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_4_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, DEST_RINGBUF_1_EXCEED_FULLMARK, 7, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, DEST_RINGBUF_0_EXCEED_FULLMARK, 6, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_5_EXCEED_FREEMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_4_EXCEED_FREEMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_SET, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR1, 0x00271840, AUD_FMM_BF_ESR1_STATUS_CLEAR, 0x8, AUD_FMM_BF_ESR1_STATUS_CLEAR, 0x271848) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_5_RD_REPEATORDRO, 29, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_4_RD_REPEATORDRO, 28, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_3_RD_REPEATORDRO, 27, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_2_RD_REPEATORDRO, 26, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_1_RD_REPEATORDRO, 25, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_0_RD_REPEATORDRO, 24, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, DEST_FIFO_1_OVERFLOW, 23, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, DEST_FIFO_0_OVERFLOW, 22, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_5_UNDERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_4_UNDERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, DEST_RINGBUF_1_OVERFLOW, 15, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, DEST_RINGBUF_0_OVERFLOW, 14, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_5_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_4_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, DEST_RINGBUF_1_EXCEED_FULLMARK, 7, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, DEST_RINGBUF_0_EXCEED_FULLMARK, 6, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_5_EXCEED_FREEMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_4_EXCEED_FREEMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR1_STATUS_CLEAR, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR1, 0x00271840, AUD_FMM_BF_ESR1_MASK, 0xc, AUD_FMM_BF_ESR1_MASK, 0x27184c) + FldFunc(AUD_FMM_BF_ESR1_MASK, DEST_FIFO_1_OVERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, DEST_FIFO_0_OVERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, DEST_RINGBUF_1_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, DEST_RINGBUF_0_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, DEST_RINGBUF_1_EXCEED_FULLMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, DEST_RINGBUF_0_EXCEED_FULLMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR1, 0x00271840, AUD_FMM_BF_ESR1_MASK_SET, 0x10, AUD_FMM_BF_ESR1_MASK_SET, 0x271850) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, DEST_FIFO_1_OVERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, DEST_FIFO_0_OVERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, DEST_RINGBUF_1_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, DEST_RINGBUF_0_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, DEST_RINGBUF_1_EXCEED_FULLMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, DEST_RINGBUF_0_EXCEED_FULLMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_SET, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) +RegFunc(AUD_FMM_BF_ESR1, 0x00271840, AUD_FMM_BF_ESR1_MASK_CLEAR, 0x14, AUD_FMM_BF_ESR1_MASK_CLEAR, 0x271854) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, DEST_FIFO_1_OVERFLOW, 21, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, DEST_FIFO_0_OVERFLOW, 20, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_FIFO_3_UNDERFLOW, 19, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_FIFO_2_UNDERFLOW, 18, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_FIFO_1_UNDERFLOW, 17, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_FIFO_0_UNDERFLOW, 16, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, DEST_RINGBUF_1_UNDERFLOW, 13, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, DEST_RINGBUF_0_UNDERFLOW, 12, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_3_UNDERFLOW, 11, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_2_UNDERFLOW, 10, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_1_UNDERFLOW, 9, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_0_UNDERFLOW, 8, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, DEST_RINGBUF_1_EXCEED_FULLMARK, 5, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, DEST_RINGBUF_0_EXCEED_FULLMARK, 4, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_3_EXCEED_FREEMARK, 3, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_2_EXCEED_FREEMARK, 2, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_1_EXCEED_FREEMARK, 1, 1) + FldFunc(AUD_FMM_BF_ESR1_MASK_CLEAR, SOURCE_RINGBUF_0_EXCEED_FREEMARK, 0, 1) + +RegAreaFunc(AUD_FMM_DP_CTRL0_BASE, 0x00274000, 0x002748fc) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_STRM_ENA, 0x0, AUD_FMM_DP_CTRL0_STRM_ENA, 0x274000) + FldFunc(AUD_FMM_DP_CTRL0_STRM_ENA, STREAM3_ENA, 3, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_ENA, STREAM2_ENA, 2, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_ENA, STREAM1_ENA, 1, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_ENA, STREAM0_ENA, 0, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_STRM_FORMAT, 0x4, AUD_FMM_DP_CTRL0_STRM_FORMAT, 0x274004) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM3_UNDERFLOW_PAUSE, 27, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM2_UNDERFLOW_PAUSE, 26, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM1_UNDERFLOW_PAUSE, 25, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM0_UNDERFLOW_PAUSE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM3_BIT_RESOLUTION, 12, 4) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM2_BIT_RESOLUTION, 8, 4) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM1_BIT_RESOLUTION, 4, 4) + FldFunc(AUD_FMM_DP_CTRL0_STRM_FORMAT, STREAM0_BIT_RESOLUTION, 0, 4) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MISC_CONFIG, 0x8, AUD_FMM_DP_CTRL0_MISC_CONFIG, 0x274008) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, DIAG_PORT_SEL, 28, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_DP_VOL_SM, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_DP_RAMP_SCALE_SM, 23, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_DP_SRC_SM, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_DP_CLIENT_SM, 21, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_DP_SM, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_CLIENT3_MS_IFACE_SM, 19, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_CLIENT2_MS_IFACE_SM, 18, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_CLIENT1_MS_IFACE_SM, 17, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, RESET_CLIENT0_MS_IFACE_SM, 16, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, GET_MAX_BB_ACK_CYCLE, 2, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, GET_CLIENT_MAX_CYCLE, 1, 1) + FldFunc(AUD_FMM_DP_CTRL0_MISC_CONFIG, GET_MAX_PROCESSING_CYCLE, 0, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_DP_STATUS, 0xc, AUD_FMM_DP_CTRL0_DP_STATUS, 0x27400c) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB3_MUTE_STATUS, 11, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB2_MUTE_STATUS, 10, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB1_MUTE_STATUS, 9, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB0_MUTE_STATUS, 8, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB3_FLOW_ON, 3, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB2_FLOW_ON, 2, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB1_FLOW_ON, 1, 1) + FldFunc(AUD_FMM_DP_CTRL0_DP_STATUS, PB0_FLOW_ON, 0, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_DP_SM, 0x10, AUD_FMM_DP_CTRL0_DP_SM, 0x274010) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM, DP_VOL_SM, 28, 4) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM, DP_SRAMP_SM, 20, 4) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM, DP_SRC_SMSR, 12, 5) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM, DP_CL_SMD, 4, 5) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM, DP_SM, 0, 2) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_DP_SM_DEBUG, 0x14, AUD_FMM_DP_CTRL0_DP_SM_DEBUG, 0x274014) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM_DEBUG, CLIENT3_MS_SM, 30, 2) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM_DEBUG, CLIENT2_MS_SM, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM_DEBUG, CLIENT1_MS_SM, 26, 2) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM_DEBUG, CLIENT0_MS_SM, 24, 2) + FldFunc(AUD_FMM_DP_CTRL0_DP_SM_DEBUG, MAX_PROCESSING_CYCLE, 0, 15) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_DP_DEBUG1, 0x18, AUD_FMM_DP_CTRL0_DP_DEBUG1, 0x274018) + FldFunc(AUD_FMM_DP_CTRL0_DP_DEBUG1, CLIENT_MAX_CYCLE_ID, 28, 3) + FldFunc(AUD_FMM_DP_CTRL0_DP_DEBUG1, CLIENT_PROCESSING_CYCLE, 16, 12) + FldFunc(AUD_FMM_DP_CTRL0_DP_DEBUG1, PLAYBACK_ID, 8, 3) + FldFunc(AUD_FMM_DP_CTRL0_DP_DEBUG1, BB_ACK_CYCLE, 0, 8) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT0_CONFIG, 0x400, AUD_FMM_DP_CTRL0_MS_CLIENT0_CONFIG, 0x274400) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT0_VOLUME, 0x404, AUD_FMM_DP_CTRL0_MS_CLIENT0_VOLUME, 0x274404) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, 0x408, AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, 0x274408) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK0_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, 0x40c, AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, 0x27440c) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, 0x410, AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, 0x274410) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, 0x414, AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, 0x274414) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT0_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_0, 0x418, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_0, 0x274418) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_1, 0x41c, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_1, 0x27441c) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT1_CONFIG, 0x420, AUD_FMM_DP_CTRL0_MS_CLIENT1_CONFIG, 0x274420) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT1_VOLUME, 0x424, AUD_FMM_DP_CTRL0_MS_CLIENT1_VOLUME, 0x274424) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, 0x428, AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, 0x274428) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK1_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, 0x42c, AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, 0x27442c) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, 0x430, AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, 0x274430) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, 0x434, AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, 0x274434) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT1_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_2, 0x438, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_2, 0x274438) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_3, 0x43c, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_3, 0x27443c) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT2_CONFIG, 0x440, AUD_FMM_DP_CTRL0_MS_CLIENT2_CONFIG, 0x274440) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT2_VOLUME, 0x444, AUD_FMM_DP_CTRL0_MS_CLIENT2_VOLUME, 0x274444) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, 0x448, AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, 0x274448) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK2_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, 0x44c, AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, 0x27444c) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, 0x450, AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, 0x274450) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, 0x454, AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, 0x274454) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT2_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_4, 0x458, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_4, 0x274458) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_5, 0x45c, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_5, 0x27445c) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT3_CONFIG, 0x460, AUD_FMM_DP_CTRL0_MS_CLIENT3_CONFIG, 0x274460) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT3_VOLUME, 0x464, AUD_FMM_DP_CTRL0_MS_CLIENT3_VOLUME, 0x274464) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, 0x468, AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, 0x274468) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL0_BB_PLAYBACK3_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, 0x46c, AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, 0x27446c) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, 0x470, AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, 0x274470) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, 0x474, AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, 0x274474) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL0_MS_CLIENT3_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_6, 0x478, AUD_FMM_DP_CTRL0_FMM_DP_C_RAM_RESERVE_ECO_6, 0x274478) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_SCALE_VOL_STEP, 0x47c, AUD_FMM_DP_CTRL0_FMM_SCALE_VOL_STEP, 0x27447c) + FldFunc(AUD_FMM_DP_CTRL0_FMM_SCALE_VOL_STEP, SCALE_RAMP_STEP_SIZE, 16, 16) + FldFunc(AUD_FMM_DP_CTRL0_FMM_SCALE_VOL_STEP, VOL_RAMP_STEP_SIZE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_C_RAM, 0x480, AUD_FMM_DP_CTRL0_C_RAM, 0x274480) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA0, 0x800, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA0, 0x274800) + FldFunc(AUD_FMM_DP_CTRL0_PB0_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA1, 0x804, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA1, 0x274804) + FldFunc(AUD_FMM_DP_CTRL0_PB0_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA2, 0x808, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA2, 0x274808) + FldFunc(AUD_FMM_DP_CTRL0_PB0_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA3, 0x80c, AUD_FMM_DP_CTRL0_PB0_FIFO_DATA3, 0x27480c) + FldFunc(AUD_FMM_DP_CTRL0_PB0_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA0, 0x810, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA0, 0x274810) + FldFunc(AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA1, 0x814, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA1, 0x274814) + FldFunc(AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA2, 0x818, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA2, 0x274818) + FldFunc(AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA3, 0x81c, AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA3, 0x27481c) + FldFunc(AUD_FMM_DP_CTRL0_PB0_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, 0x820, AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, 0x274820) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB0_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_SRC_DDA_DATA, 0x824, AUD_FMM_DP_CTRL0_PB0_SRC_DDA_DATA, 0x274824) + FldFunc(AUD_FMM_DP_CTRL0_PB0_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB0_CURRENT_SCALE, 0x828, AUD_FMM_DP_CTRL0_PB0_CURRENT_SCALE, 0x274828) + FldFunc(AUD_FMM_DP_CTRL0_PB0_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_PB0_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT0_CURRENT_LEFT_VOL, 0x82c, AUD_FMM_DP_CTRL0_CLNT0_CURRENT_LEFT_VOL, 0x27482c) + FldFunc(AUD_FMM_DP_CTRL0_CLNT0_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT0_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT0_CURRENT_RIGHT_VOL, 0x830, AUD_FMM_DP_CTRL0_CLNT0_CURRENT_RIGHT_VOL, 0x274830) + FldFunc(AUD_FMM_DP_CTRL0_CLNT0_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT0_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_0, 0x834, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_0, 0x274834) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_1, 0x838, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_1, 0x274838) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_2, 0x83c, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_2, 0x27483c) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA0, 0x840, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA0, 0x274840) + FldFunc(AUD_FMM_DP_CTRL0_PB1_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA1, 0x844, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA1, 0x274844) + FldFunc(AUD_FMM_DP_CTRL0_PB1_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA2, 0x848, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA2, 0x274848) + FldFunc(AUD_FMM_DP_CTRL0_PB1_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA3, 0x84c, AUD_FMM_DP_CTRL0_PB1_FIFO_DATA3, 0x27484c) + FldFunc(AUD_FMM_DP_CTRL0_PB1_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA0, 0x850, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA0, 0x274850) + FldFunc(AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA1, 0x854, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA1, 0x274854) + FldFunc(AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA2, 0x858, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA2, 0x274858) + FldFunc(AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA3, 0x85c, AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA3, 0x27485c) + FldFunc(AUD_FMM_DP_CTRL0_PB1_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, 0x860, AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, 0x274860) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB1_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_SRC_DDA_DATA, 0x864, AUD_FMM_DP_CTRL0_PB1_SRC_DDA_DATA, 0x274864) + FldFunc(AUD_FMM_DP_CTRL0_PB1_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB1_CURRENT_SCALE, 0x868, AUD_FMM_DP_CTRL0_PB1_CURRENT_SCALE, 0x274868) + FldFunc(AUD_FMM_DP_CTRL0_PB1_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_PB1_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT1_CURRENT_LEFT_VOL, 0x86c, AUD_FMM_DP_CTRL0_CLNT1_CURRENT_LEFT_VOL, 0x27486c) + FldFunc(AUD_FMM_DP_CTRL0_CLNT1_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT1_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT1_CURRENT_RIGHT_VOL, 0x870, AUD_FMM_DP_CTRL0_CLNT1_CURRENT_RIGHT_VOL, 0x274870) + FldFunc(AUD_FMM_DP_CTRL0_CLNT1_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT1_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_3, 0x874, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_3, 0x274874) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_4, 0x878, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_4, 0x274878) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_5, 0x87c, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_5, 0x27487c) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA0, 0x880, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA0, 0x274880) + FldFunc(AUD_FMM_DP_CTRL0_PB2_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA1, 0x884, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA1, 0x274884) + FldFunc(AUD_FMM_DP_CTRL0_PB2_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA2, 0x888, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA2, 0x274888) + FldFunc(AUD_FMM_DP_CTRL0_PB2_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA3, 0x88c, AUD_FMM_DP_CTRL0_PB2_FIFO_DATA3, 0x27488c) + FldFunc(AUD_FMM_DP_CTRL0_PB2_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA0, 0x890, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA0, 0x274890) + FldFunc(AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA1, 0x894, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA1, 0x274894) + FldFunc(AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA2, 0x898, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA2, 0x274898) + FldFunc(AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA3, 0x89c, AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA3, 0x27489c) + FldFunc(AUD_FMM_DP_CTRL0_PB2_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, 0x8a0, AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, 0x2748a0) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB2_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_SRC_DDA_DATA, 0x8a4, AUD_FMM_DP_CTRL0_PB2_SRC_DDA_DATA, 0x2748a4) + FldFunc(AUD_FMM_DP_CTRL0_PB2_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB2_CURRENT_SCALE, 0x8a8, AUD_FMM_DP_CTRL0_PB2_CURRENT_SCALE, 0x2748a8) + FldFunc(AUD_FMM_DP_CTRL0_PB2_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_PB2_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT2_CURRENT_LEFT_VOL, 0x8ac, AUD_FMM_DP_CTRL0_CLNT2_CURRENT_LEFT_VOL, 0x2748ac) + FldFunc(AUD_FMM_DP_CTRL0_CLNT2_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT2_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT2_CURRENT_RIGHT_VOL, 0x8b0, AUD_FMM_DP_CTRL0_CLNT2_CURRENT_RIGHT_VOL, 0x2748b0) + FldFunc(AUD_FMM_DP_CTRL0_CLNT2_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT2_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_6, 0x8b4, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_6, 0x2748b4) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_7, 0x8b8, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_7, 0x2748b8) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_8, 0x8bc, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_8, 0x2748bc) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA0, 0x8c0, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA0, 0x2748c0) + FldFunc(AUD_FMM_DP_CTRL0_PB3_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA1, 0x8c4, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA1, 0x2748c4) + FldFunc(AUD_FMM_DP_CTRL0_PB3_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA2, 0x8c8, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA2, 0x2748c8) + FldFunc(AUD_FMM_DP_CTRL0_PB3_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA3, 0x8cc, AUD_FMM_DP_CTRL0_PB3_FIFO_DATA3, 0x2748cc) + FldFunc(AUD_FMM_DP_CTRL0_PB3_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA0, 0x8d0, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA0, 0x2748d0) + FldFunc(AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA1, 0x8d4, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA1, 0x2748d4) + FldFunc(AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA2, 0x8d8, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA2, 0x2748d8) + FldFunc(AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA3, 0x8dc, AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA3, 0x2748dc) + FldFunc(AUD_FMM_DP_CTRL0_PB3_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, 0x8e0, AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, 0x2748e0) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL0_CLIENT_PB3_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_SRC_DDA_DATA, 0x8e4, AUD_FMM_DP_CTRL0_PB3_SRC_DDA_DATA, 0x2748e4) + FldFunc(AUD_FMM_DP_CTRL0_PB3_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_PB3_CURRENT_SCALE, 0x8e8, AUD_FMM_DP_CTRL0_PB3_CURRENT_SCALE, 0x2748e8) + FldFunc(AUD_FMM_DP_CTRL0_PB3_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_PB3_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT3_CURRENT_LEFT_VOL, 0x8ec, AUD_FMM_DP_CTRL0_CLNT3_CURRENT_LEFT_VOL, 0x2748ec) + FldFunc(AUD_FMM_DP_CTRL0_CLNT3_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT3_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_CLNT3_CURRENT_RIGHT_VOL, 0x8f0, AUD_FMM_DP_CTRL0_CLNT3_CURRENT_RIGHT_VOL, 0x2748f0) + FldFunc(AUD_FMM_DP_CTRL0_CLNT3_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL0_CLNT3_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_9, 0x8f4, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_9, 0x2748f4) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_10, 0x8f8, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_10, 0x2748f8) +RegFunc(AUD_FMM_DP_CTRL0, 0x00274000, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_11, 0x8fc, AUD_FMM_DP_CTRL0_FMM_DP_T_RAM_RESERVE_ECO_11, 0x2748fc) + +RegAreaFunc(AUD_FMM_DP_ESR0_BASE, 0x00275000, 0x00275014) +RegFunc(AUD_FMM_DP_ESR0, 0x00275000, AUD_FMM_DP_ESR0_STATUS, 0x0, AUD_FMM_DP_ESR0_STATUS, 0x275000) + FldFunc(AUD_FMM_DP_ESR0_STATUS, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR0, 0x00275000, AUD_FMM_DP_ESR0_STATUS_SET, 0x4, AUD_FMM_DP_ESR0_STATUS_SET, 0x275004) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_SET, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR0, 0x00275000, AUD_FMM_DP_ESR0_STATUS_CLEAR, 0x8, AUD_FMM_DP_ESR0_STATUS_CLEAR, 0x275008) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR0_STATUS_CLEAR, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR0, 0x00275000, AUD_FMM_DP_ESR0_MASK, 0xc, AUD_FMM_DP_ESR0_MASK, 0x27500c) + FldFunc(AUD_FMM_DP_ESR0_MASK, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR0, 0x00275000, AUD_FMM_DP_ESR0_MASK_SET, 0x10, AUD_FMM_DP_ESR0_MASK_SET, 0x275010) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_SET, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR0, 0x00275000, AUD_FMM_DP_ESR0_MASK_CLEAR, 0x14, AUD_FMM_DP_ESR0_MASK_CLEAR, 0x275014) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR0_MASK_CLEAR, UNDERFLOW0, 0, 1) + +RegAreaFunc(AUD_FMM_DP_CTRL1_BASE, 0x00276000, 0x002768fc) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_STRM_ENA, 0x0, AUD_FMM_DP_CTRL1_STRM_ENA, 0x276000) + FldFunc(AUD_FMM_DP_CTRL1_STRM_ENA, STREAM3_ENA, 3, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_ENA, STREAM2_ENA, 2, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_ENA, STREAM1_ENA, 1, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_ENA, STREAM0_ENA, 0, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_STRM_FORMAT, 0x4, AUD_FMM_DP_CTRL1_STRM_FORMAT, 0x276004) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM3_UNDERFLOW_PAUSE, 27, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM2_UNDERFLOW_PAUSE, 26, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM1_UNDERFLOW_PAUSE, 25, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM0_UNDERFLOW_PAUSE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM3_BIT_RESOLUTION, 12, 4) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM2_BIT_RESOLUTION, 8, 4) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM1_BIT_RESOLUTION, 4, 4) + FldFunc(AUD_FMM_DP_CTRL1_STRM_FORMAT, STREAM0_BIT_RESOLUTION, 0, 4) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MISC_CONFIG, 0x8, AUD_FMM_DP_CTRL1_MISC_CONFIG, 0x276008) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, DIAG_PORT_SEL, 28, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_DP_VOL_SM, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_DP_RAMP_SCALE_SM, 23, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_DP_SRC_SM, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_DP_CLIENT_SM, 21, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_DP_SM, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_CLIENT3_MS_IFACE_SM, 19, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_CLIENT2_MS_IFACE_SM, 18, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_CLIENT1_MS_IFACE_SM, 17, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, RESET_CLIENT0_MS_IFACE_SM, 16, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, GET_MAX_BB_ACK_CYCLE, 2, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, GET_CLIENT_MAX_CYCLE, 1, 1) + FldFunc(AUD_FMM_DP_CTRL1_MISC_CONFIG, GET_MAX_PROCESSING_CYCLE, 0, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_DP_STATUS, 0xc, AUD_FMM_DP_CTRL1_DP_STATUS, 0x27600c) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB3_MUTE_STATUS, 11, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB2_MUTE_STATUS, 10, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB1_MUTE_STATUS, 9, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB0_MUTE_STATUS, 8, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB3_FLOW_ON, 3, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB2_FLOW_ON, 2, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB1_FLOW_ON, 1, 1) + FldFunc(AUD_FMM_DP_CTRL1_DP_STATUS, PB0_FLOW_ON, 0, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_DP_SM, 0x10, AUD_FMM_DP_CTRL1_DP_SM, 0x276010) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM, DP_VOL_SM, 28, 4) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM, DP_SRAMP_SM, 20, 4) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM, DP_SRC_SMSR, 12, 5) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM, DP_CL_SMD, 4, 5) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM, DP_SM, 0, 2) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_DP_SM_DEBUG, 0x14, AUD_FMM_DP_CTRL1_DP_SM_DEBUG, 0x276014) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM_DEBUG, CLIENT3_MS_SM, 30, 2) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM_DEBUG, CLIENT2_MS_SM, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM_DEBUG, CLIENT1_MS_SM, 26, 2) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM_DEBUG, CLIENT0_MS_SM, 24, 2) + FldFunc(AUD_FMM_DP_CTRL1_DP_SM_DEBUG, MAX_PROCESSING_CYCLE, 0, 15) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_DP_DEBUG1, 0x18, AUD_FMM_DP_CTRL1_DP_DEBUG1, 0x276018) + FldFunc(AUD_FMM_DP_CTRL1_DP_DEBUG1, CLIENT_MAX_CYCLE_ID, 28, 3) + FldFunc(AUD_FMM_DP_CTRL1_DP_DEBUG1, CLIENT_PROCESSING_CYCLE, 16, 12) + FldFunc(AUD_FMM_DP_CTRL1_DP_DEBUG1, PLAYBACK_ID, 8, 3) + FldFunc(AUD_FMM_DP_CTRL1_DP_DEBUG1, BB_ACK_CYCLE, 0, 8) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT0_CONFIG, 0x400, AUD_FMM_DP_CTRL1_MS_CLIENT0_CONFIG, 0x276400) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT0_VOLUME, 0x404, AUD_FMM_DP_CTRL1_MS_CLIENT0_VOLUME, 0x276404) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, 0x408, AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, 0x276408) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK0_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, 0x40c, AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, 0x27640c) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, 0x410, AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, 0x276410) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, 0x414, AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, 0x276414) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT0_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_0, 0x418, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_0, 0x276418) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_1, 0x41c, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_1, 0x27641c) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT1_CONFIG, 0x420, AUD_FMM_DP_CTRL1_MS_CLIENT1_CONFIG, 0x276420) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT1_VOLUME, 0x424, AUD_FMM_DP_CTRL1_MS_CLIENT1_VOLUME, 0x276424) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, 0x428, AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, 0x276428) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK1_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, 0x42c, AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, 0x27642c) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, 0x430, AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, 0x276430) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, 0x434, AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, 0x276434) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT1_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_2, 0x438, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_2, 0x276438) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_3, 0x43c, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_3, 0x27643c) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT2_CONFIG, 0x440, AUD_FMM_DP_CTRL1_MS_CLIENT2_CONFIG, 0x276440) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT2_VOLUME, 0x444, AUD_FMM_DP_CTRL1_MS_CLIENT2_VOLUME, 0x276444) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, 0x448, AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, 0x276448) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK2_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, 0x44c, AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, 0x27644c) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, 0x450, AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, 0x276450) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, 0x454, AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, 0x276454) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT2_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_4, 0x458, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_4, 0x276458) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_5, 0x45c, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_5, 0x27645c) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT3_CONFIG, 0x460, AUD_FMM_DP_CTRL1_MS_CLIENT3_CONFIG, 0x276460) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_CONFIG, VOLUME_ENA, 31, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_CONFIG, VOLUME_MUTE_ENA, 30, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_CONFIG, VOLUME_RAMP_ENA, 29, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_CONFIG, VOLUME_STARTUP_RAMP_DIS, 28, 1) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT3_VOLUME, 0x464, AUD_FMM_DP_CTRL1_MS_CLIENT3_VOLUME, 0x276464) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_VOLUME, RIGHT_VOLUME_LEVEL, 16, 16) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_VOLUME, LEFT_VOLUME_LEVEL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, 0x468, AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, 0x276468) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, SRC_ENB, 28, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, SCALE_RAMP_ENA, 27, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, SCALE_MUTE_ENA, 26, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, SCALE_STARTUP_RAMP_ENB, 25, 1) + FldFunc(AUD_FMM_DP_CTRL1_BB_PLAYBACK3_SCALE_SRC_CONFIG, SRC_IOR, 0, 19) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, 0x46c, AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, 0x27646c) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX1_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, 0x470, AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, 0x276470) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX2_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, 0x474, AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, 0x276474) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, MONO_SEL, 28, 2) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, MIX_ENABLE, 24, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, MIX_SCALE_ENB, 20, 1) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, MIX_PB_ID, 16, 4) + FldFunc(AUD_FMM_DP_CTRL1_MS_CLIENT3_MIX3_CONFIG, MIX_SCALING_COEF, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_6, 0x478, AUD_FMM_DP_CTRL1_FMM_DP_C_RAM_RESERVE_ECO_6, 0x276478) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_SCALE_VOL_STEP, 0x47c, AUD_FMM_DP_CTRL1_FMM_SCALE_VOL_STEP, 0x27647c) + FldFunc(AUD_FMM_DP_CTRL1_FMM_SCALE_VOL_STEP, SCALE_RAMP_STEP_SIZE, 16, 16) + FldFunc(AUD_FMM_DP_CTRL1_FMM_SCALE_VOL_STEP, VOL_RAMP_STEP_SIZE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_C_RAM, 0x480, AUD_FMM_DP_CTRL1_C_RAM, 0x276480) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA0, 0x800, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA0, 0x276800) + FldFunc(AUD_FMM_DP_CTRL1_PB0_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA1, 0x804, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA1, 0x276804) + FldFunc(AUD_FMM_DP_CTRL1_PB0_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA2, 0x808, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA2, 0x276808) + FldFunc(AUD_FMM_DP_CTRL1_PB0_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA3, 0x80c, AUD_FMM_DP_CTRL1_PB0_FIFO_DATA3, 0x27680c) + FldFunc(AUD_FMM_DP_CTRL1_PB0_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA0, 0x810, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA0, 0x276810) + FldFunc(AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA1, 0x814, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA1, 0x276814) + FldFunc(AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA2, 0x818, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA2, 0x276818) + FldFunc(AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA3, 0x81c, AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA3, 0x27681c) + FldFunc(AUD_FMM_DP_CTRL1_PB0_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, 0x820, AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, 0x276820) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB0_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_SRC_DDA_DATA, 0x824, AUD_FMM_DP_CTRL1_PB0_SRC_DDA_DATA, 0x276824) + FldFunc(AUD_FMM_DP_CTRL1_PB0_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB0_CURRENT_SCALE, 0x828, AUD_FMM_DP_CTRL1_PB0_CURRENT_SCALE, 0x276828) + FldFunc(AUD_FMM_DP_CTRL1_PB0_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_PB0_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT0_CURRENT_LEFT_VOL, 0x82c, AUD_FMM_DP_CTRL1_CLNT0_CURRENT_LEFT_VOL, 0x27682c) + FldFunc(AUD_FMM_DP_CTRL1_CLNT0_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT0_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT0_CURRENT_RIGHT_VOL, 0x830, AUD_FMM_DP_CTRL1_CLNT0_CURRENT_RIGHT_VOL, 0x276830) + FldFunc(AUD_FMM_DP_CTRL1_CLNT0_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT0_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_0, 0x834, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_0, 0x276834) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_1, 0x838, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_1, 0x276838) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_2, 0x83c, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_2, 0x27683c) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA0, 0x840, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA0, 0x276840) + FldFunc(AUD_FMM_DP_CTRL1_PB1_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA1, 0x844, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA1, 0x276844) + FldFunc(AUD_FMM_DP_CTRL1_PB1_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA2, 0x848, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA2, 0x276848) + FldFunc(AUD_FMM_DP_CTRL1_PB1_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA3, 0x84c, AUD_FMM_DP_CTRL1_PB1_FIFO_DATA3, 0x27684c) + FldFunc(AUD_FMM_DP_CTRL1_PB1_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA0, 0x850, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA0, 0x276850) + FldFunc(AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA1, 0x854, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA1, 0x276854) + FldFunc(AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA2, 0x858, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA2, 0x276858) + FldFunc(AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA3, 0x85c, AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA3, 0x27685c) + FldFunc(AUD_FMM_DP_CTRL1_PB1_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, 0x860, AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, 0x276860) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB1_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_SRC_DDA_DATA, 0x864, AUD_FMM_DP_CTRL1_PB1_SRC_DDA_DATA, 0x276864) + FldFunc(AUD_FMM_DP_CTRL1_PB1_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB1_CURRENT_SCALE, 0x868, AUD_FMM_DP_CTRL1_PB1_CURRENT_SCALE, 0x276868) + FldFunc(AUD_FMM_DP_CTRL1_PB1_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_PB1_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT1_CURRENT_LEFT_VOL, 0x86c, AUD_FMM_DP_CTRL1_CLNT1_CURRENT_LEFT_VOL, 0x27686c) + FldFunc(AUD_FMM_DP_CTRL1_CLNT1_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT1_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT1_CURRENT_RIGHT_VOL, 0x870, AUD_FMM_DP_CTRL1_CLNT1_CURRENT_RIGHT_VOL, 0x276870) + FldFunc(AUD_FMM_DP_CTRL1_CLNT1_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT1_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_3, 0x874, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_3, 0x276874) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_4, 0x878, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_4, 0x276878) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_5, 0x87c, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_5, 0x27687c) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA0, 0x880, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA0, 0x276880) + FldFunc(AUD_FMM_DP_CTRL1_PB2_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA1, 0x884, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA1, 0x276884) + FldFunc(AUD_FMM_DP_CTRL1_PB2_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA2, 0x888, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA2, 0x276888) + FldFunc(AUD_FMM_DP_CTRL1_PB2_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA3, 0x88c, AUD_FMM_DP_CTRL1_PB2_FIFO_DATA3, 0x27688c) + FldFunc(AUD_FMM_DP_CTRL1_PB2_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA0, 0x890, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA0, 0x276890) + FldFunc(AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA1, 0x894, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA1, 0x276894) + FldFunc(AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA2, 0x898, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA2, 0x276898) + FldFunc(AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA3, 0x89c, AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA3, 0x27689c) + FldFunc(AUD_FMM_DP_CTRL1_PB2_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, 0x8a0, AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, 0x2768a0) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB2_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_SRC_DDA_DATA, 0x8a4, AUD_FMM_DP_CTRL1_PB2_SRC_DDA_DATA, 0x2768a4) + FldFunc(AUD_FMM_DP_CTRL1_PB2_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB2_CURRENT_SCALE, 0x8a8, AUD_FMM_DP_CTRL1_PB2_CURRENT_SCALE, 0x2768a8) + FldFunc(AUD_FMM_DP_CTRL1_PB2_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_PB2_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT2_CURRENT_LEFT_VOL, 0x8ac, AUD_FMM_DP_CTRL1_CLNT2_CURRENT_LEFT_VOL, 0x2768ac) + FldFunc(AUD_FMM_DP_CTRL1_CLNT2_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT2_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT2_CURRENT_RIGHT_VOL, 0x8b0, AUD_FMM_DP_CTRL1_CLNT2_CURRENT_RIGHT_VOL, 0x2768b0) + FldFunc(AUD_FMM_DP_CTRL1_CLNT2_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT2_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_6, 0x8b4, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_6, 0x2768b4) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_7, 0x8b8, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_7, 0x2768b8) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_8, 0x8bc, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_8, 0x2768bc) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA0, 0x8c0, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA0, 0x2768c0) + FldFunc(AUD_FMM_DP_CTRL1_PB3_FIFO_DATA0, PB_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA1, 0x8c4, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA1, 0x2768c4) + FldFunc(AUD_FMM_DP_CTRL1_PB3_FIFO_DATA1, PB_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA2, 0x8c8, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA2, 0x2768c8) + FldFunc(AUD_FMM_DP_CTRL1_PB3_FIFO_DATA2, PB_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA3, 0x8cc, AUD_FMM_DP_CTRL1_PB3_FIFO_DATA3, 0x2768cc) + FldFunc(AUD_FMM_DP_CTRL1_PB3_FIFO_DATA3, PB_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA0, 0x8d0, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA0, 0x2768d0) + FldFunc(AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA0, PB_SRC_FIFO_DATA0, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA1, 0x8d4, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA1, 0x2768d4) + FldFunc(AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA1, PB_SRC_FIFO_DATA1, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA2, 0x8d8, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA2, 0x2768d8) + FldFunc(AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA2, PB_SRC_FIFO_DATA2, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA3, 0x8dc, AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA3, 0x2768dc) + FldFunc(AUD_FMM_DP_CTRL1_PB3_SRC_FIFO_DATA3, PB_SRC_FIFO_DATA3, 0, 24) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, 0x8e0, AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, 0x2768e0) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, SRC_FIFO_POINTER, 22, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, PB_FIFO_POINTER, 20, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, CLNT3_PB_FIFO_POINTER, 18, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, CLNT2_PB_FIFO_POINTER, 16, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, CLNT1_PB_FIFO_POINTER, 14, 2) + FldFunc(AUD_FMM_DP_CTRL1_CLIENT_PB3_FIFO_POINTERS, CLNT0_PB_FIFO_POINTER, 12, 2) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_SRC_DDA_DATA, 0x8e4, AUD_FMM_DP_CTRL1_PB3_SRC_DDA_DATA, 0x2768e4) + FldFunc(AUD_FMM_DP_CTRL1_PB3_SRC_DDA_DATA, PB_SRC_DDA, 0, 18) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_PB3_CURRENT_SCALE, 0x8e8, AUD_FMM_DP_CTRL1_PB3_CURRENT_SCALE, 0x2768e8) + FldFunc(AUD_FMM_DP_CTRL1_PB3_CURRENT_SCALE, CURRENT_SCALE_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_PB3_CURRENT_SCALE, CURRENT_SCALE, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT3_CURRENT_LEFT_VOL, 0x8ec, AUD_FMM_DP_CTRL1_CLNT3_CURRENT_LEFT_VOL, 0x2768ec) + FldFunc(AUD_FMM_DP_CTRL1_CLNT3_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL_RAMPING, 22, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT3_CURRENT_LEFT_VOL, CURRENT_LEFT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_CLNT3_CURRENT_RIGHT_VOL, 0x8f0, AUD_FMM_DP_CTRL1_CLNT3_CURRENT_RIGHT_VOL, 0x2768f0) + FldFunc(AUD_FMM_DP_CTRL1_CLNT3_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL_RAMPING, 23, 1) + FldFunc(AUD_FMM_DP_CTRL1_CLNT3_CURRENT_RIGHT_VOL, CURRENT_RIGHT_VOL, 0, 16) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_9, 0x8f4, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_9, 0x2768f4) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_10, 0x8f8, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_10, 0x2768f8) +RegFunc(AUD_FMM_DP_CTRL1, 0x00276000, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_11, 0x8fc, AUD_FMM_DP_CTRL1_FMM_DP_T_RAM_RESERVE_ECO_11, 0x2768fc) + +RegAreaFunc(AUD_FMM_DP_ESR1_BASE, 0x00277000, 0x00277014) +RegFunc(AUD_FMM_DP_ESR1, 0x00277000, AUD_FMM_DP_ESR1_STATUS, 0x0, AUD_FMM_DP_ESR1_STATUS, 0x277000) + FldFunc(AUD_FMM_DP_ESR1_STATUS, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR1, 0x00277000, AUD_FMM_DP_ESR1_STATUS_SET, 0x4, AUD_FMM_DP_ESR1_STATUS_SET, 0x277004) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_SET, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR1, 0x00277000, AUD_FMM_DP_ESR1_STATUS_CLEAR, 0x8, AUD_FMM_DP_ESR1_STATUS_CLEAR, 0x277008) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR1_STATUS_CLEAR, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR1, 0x00277000, AUD_FMM_DP_ESR1_MASK, 0xc, AUD_FMM_DP_ESR1_MASK, 0x27700c) + FldFunc(AUD_FMM_DP_ESR1_MASK, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR1, 0x00277000, AUD_FMM_DP_ESR1_MASK_SET, 0x10, AUD_FMM_DP_ESR1_MASK_SET, 0x277010) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_SET, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_DP_ESR1, 0x00277000, AUD_FMM_DP_ESR1_MASK_CLEAR, 0x14, AUD_FMM_DP_ESR1_MASK_CLEAR, 0x277014) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, CLIENT3_RATE_ERR, 15, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, CLIENT2_RATE_ERR, 14, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, CLIENT1_RATE_ERR, 13, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, CLIENT0_RATE_ERR, 12, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, VOL_RAMP_DONE3, 11, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, VOL_RAMP_DONE2, 10, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, VOL_RAMP_DONE1, 9, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, VOL_RAMP_DONE0, 8, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, SCALE_RAMP_DONE3, 7, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, SCALE_RAMP_DONE2, 6, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, SCALE_RAMP_DONE1, 5, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, SCALE_RAMP_DONE0, 4, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_DP_ESR1_MASK_CLEAR, UNDERFLOW0, 0, 1) + +RegAreaFunc(AUD_FMM_MS_CTRL_BASE, 0x00278000, 0x00279bfc) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_STRM_ENA, 0x0, AUD_FMM_MS_CTRL_STRM_ENA, 0x278000) + FldFunc(AUD_FMM_MS_CTRL_STRM_ENA, STREAM1_ENA, 1, 1) + FldFunc(AUD_FMM_MS_CTRL_STRM_ENA, STREAM0_ENA, 0, 1) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_BYPASS, 0x4, AUD_FMM_MS_CTRL_USEQ_BYPASS, 0x278004) + FldFunc(AUD_FMM_MS_CTRL_USEQ_BYPASS, STREAM1, 1, 1) + FldFunc(AUD_FMM_MS_CTRL_USEQ_BYPASS, STREAM0, 0, 1) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_CTRL, 0x8, AUD_FMM_MS_CTRL_USEQ_CTRL, 0x278008) + FldFunc(AUD_FMM_MS_CTRL_USEQ_CTRL, WAKE, 4, 1) + FldFunc(AUD_FMM_MS_CTRL_USEQ_CTRL, CFG_CTRL, 0, 2) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_STATUS, 0xc, AUD_FMM_MS_CTRL_USEQ_STATUS, 0x27800c) + FldFunc(AUD_FMM_MS_CTRL_USEQ_STATUS, ILLEGAL_FLAG, 17, 1) + FldFunc(AUD_FMM_MS_CTRL_USEQ_STATUS, WAIT_FLAG, 16, 1) + FldFunc(AUD_FMM_MS_CTRL_USEQ_STATUS, PC, 0, 9) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_MSG, 0x10, AUD_FMM_MS_CTRL_USEQ_MSG, 0x278010) + FldFunc(AUD_FMM_MS_CTRL_USEQ_MSG, STREAM1, 8, 8) + FldFunc(AUD_FMM_MS_CTRL_USEQ_MSG, STREAM0, 0, 8) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_MSG_SET, 0x14, AUD_FMM_MS_CTRL_USEQ_MSG_SET, 0x278014) + FldFunc(AUD_FMM_MS_CTRL_USEQ_MSG_SET, STREAM1, 8, 8) + FldFunc(AUD_FMM_MS_CTRL_USEQ_MSG_SET, STREAM0, 0, 8) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_MSG_CLEAR, 0x18, AUD_FMM_MS_CTRL_USEQ_MSG_CLEAR, 0x278018) + FldFunc(AUD_FMM_MS_CTRL_USEQ_MSG_CLEAR, STREAM1, 8, 8) + FldFunc(AUD_FMM_MS_CTRL_USEQ_MSG_CLEAR, STREAM0, 0, 8) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_FLAGS, 0x1c, AUD_FMM_MS_CTRL_USEQ_FLAGS, 0x27801c) + FldFunc(AUD_FMM_MS_CTRL_USEQ_FLAGS, STREAM1, 8, 8) + FldFunc(AUD_FMM_MS_CTRL_USEQ_FLAGS, STREAM0, 0, 8) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, 0x800, AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, 0x278800) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, RESERVED, 9, 7) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, DITHER_ENA, 8, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, CHAN_OVERRIDE, 7, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, VALIDITYSPDI, 6, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, COMP_OR_LINEAR, 5, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, SPDIF_OR_PCM, 4, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, FLUSH_ON_UFLOW, 3, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, INSERT_ON_UFLOW, 2, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, INSERT_WHEN_DISA, 1, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_0, STREAM_ENA, 0, 1) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_RAMP_AMOUNT_0, 0x804, AUD_FMM_MS_CTRL_FW_RAMP_AMOUNT_0, 0x278804) + FldFunc(AUD_FMM_MS_CTRL_FW_RAMP_AMOUNT_0, STEPSIZE, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_CBIT_CTRL_0, 0x808, AUD_FMM_MS_CTRL_FW_CBIT_CTRL_0, 0x278808) + FldFunc(AUD_FMM_MS_CTRL_FW_CBIT_CTRL_0, CP_TOGGLE_RATE, 8, 8) + FldFunc(AUD_FMM_MS_CTRL_FW_CBIT_CTRL_0, OFFSET, 0, 8) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_RESERVED0_, 0x80c, AUD_FMM_MS_CTRL_FW_RESERVED0_, 0x27880c) + FldFunc(AUD_FMM_MS_CTRL_FW_RESERVED0_, RESERVED, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, 0x840, AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, 0x278840) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, RESERVED, 9, 7) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, DITHER_ENA, 8, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, CHAN_OVERRIDE, 7, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, VALIDITYSPDI, 6, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, COMP_OR_LINEAR, 5, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, SPDIF_OR_PCM, 4, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, FLUSH_ON_UFLOW, 3, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, INSERT_ON_UFLOW, 2, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, INSERT_WHEN_DISA, 1, 1) + FldFunc(AUD_FMM_MS_CTRL_FW_STREAM_CTRL_1, STREAM_ENA, 0, 1) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_RAMP_AMOUNT_1, 0x844, AUD_FMM_MS_CTRL_FW_RAMP_AMOUNT_1, 0x278844) + FldFunc(AUD_FMM_MS_CTRL_FW_RAMP_AMOUNT_1, STEPSIZE, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_CBIT_CTRL_1, 0x848, AUD_FMM_MS_CTRL_FW_CBIT_CTRL_1, 0x278848) + FldFunc(AUD_FMM_MS_CTRL_FW_CBIT_CTRL_1, CP_TOGGLE_RATE, 8, 8) + FldFunc(AUD_FMM_MS_CTRL_FW_CBIT_CTRL_1, OFFSET, 0, 8) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_RESERVED1_, 0x84c, AUD_FMM_MS_CTRL_FW_RESERVED1_, 0x27884c) + FldFunc(AUD_FMM_MS_CTRL_FW_RESERVED1_, RESERVED, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_RESERVED2, 0x880, AUD_FMM_MS_CTRL_FW_RESERVED2, 0x278880) + FldFunc(AUD_FMM_MS_CTRL_FW_RESERVED2, RESERVED, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_RESERVED3, 0x8c0, AUD_FMM_MS_CTRL_FW_RESERVED3, 0x2788c0) + FldFunc(AUD_FMM_MS_CTRL_FW_RESERVED3, RESERVED, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_SCRATCH, 0x900, AUD_FMM_MS_CTRL_FW_SCRATCH, 0x278900) + FldFunc(AUD_FMM_MS_CTRL_FW_SCRATCH, RESERVED, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_FW_CBITS, 0x940, AUD_FMM_MS_CTRL_FW_CBITS, 0x278940) + FldFunc(AUD_FMM_MS_CTRL_FW_CBITS, TWO_BYTES, 0, 16) +RegFunc(AUD_FMM_MS_CTRL, 0x00278000, AUD_FMM_MS_CTRL_USEQ_INST, 0x1000, AUD_FMM_MS_CTRL_USEQ_INST, 0x279000) + FldFunc(AUD_FMM_MS_CTRL_USEQ_INST, INST, 0, 16) + +RegAreaFunc(AUD_FMM_MS_ESR_BASE, 0x0027a000, 0x0027a014) +RegFunc(AUD_FMM_MS_ESR, 0x0027a000, AUD_FMM_MS_ESR_STATUS, 0x0, AUD_FMM_MS_ESR_STATUS, 0x27a000) + FldFunc(AUD_FMM_MS_ESR_STATUS, USEQ_SLEEP, 10, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, USEQ_ERROR1, 9, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, CBIT_PING_PONG1, 8, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, RAMP_DONE1, 7, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, FLOWON1, 6, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, UNDERFLOW1, 5, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, USEQ_ERROR0, 4, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, CBIT_PING_PONG0, 3, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, RAMP_DONE0, 2, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, FLOWON0, 1, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_MS_ESR, 0x0027a000, AUD_FMM_MS_ESR_STATUS_SET, 0x4, AUD_FMM_MS_ESR_STATUS_SET, 0x27a004) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, USEQ_SLEEP, 10, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, USEQ_ERROR1, 9, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, CBIT_PING_PONG1, 8, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, RAMP_DONE1, 7, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, FLOWON1, 6, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, UNDERFLOW1, 5, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, USEQ_ERROR0, 4, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, CBIT_PING_PONG0, 3, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, RAMP_DONE0, 2, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, FLOWON0, 1, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_SET, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_MS_ESR, 0x0027a000, AUD_FMM_MS_ESR_STATUS_CLEAR, 0x8, AUD_FMM_MS_ESR_STATUS_CLEAR, 0x27a008) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, USEQ_SLEEP, 10, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, USEQ_ERROR1, 9, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, CBIT_PING_PONG1, 8, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, RAMP_DONE1, 7, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, FLOWON1, 6, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, UNDERFLOW1, 5, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, USEQ_ERROR0, 4, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, CBIT_PING_PONG0, 3, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, RAMP_DONE0, 2, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, FLOWON0, 1, 1) + FldFunc(AUD_FMM_MS_ESR_STATUS_CLEAR, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_MS_ESR, 0x0027a000, AUD_FMM_MS_ESR_MASK, 0xc, AUD_FMM_MS_ESR_MASK, 0x27a00c) + FldFunc(AUD_FMM_MS_ESR_MASK, USEQ_SLEEP, 10, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, USEQ_ERROR1, 9, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, CBIT_PING_PONG1, 8, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, RAMP_DONE1, 7, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, FLOWON1, 6, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, UNDERFLOW1, 5, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, USEQ_ERROR0, 4, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, CBIT_PING_PONG0, 3, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, RAMP_DONE0, 2, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, FLOWON0, 1, 1) + FldFunc(AUD_FMM_MS_ESR_MASK, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_MS_ESR, 0x0027a000, AUD_FMM_MS_ESR_MASK_SET, 0x10, AUD_FMM_MS_ESR_MASK_SET, 0x27a010) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, USEQ_SLEEP, 10, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, USEQ_ERROR1, 9, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, CBIT_PING_PONG1, 8, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, RAMP_DONE1, 7, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, FLOWON1, 6, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, UNDERFLOW1, 5, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, USEQ_ERROR0, 4, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, CBIT_PING_PONG0, 3, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, RAMP_DONE0, 2, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, FLOWON0, 1, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_SET, UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_MS_ESR, 0x0027a000, AUD_FMM_MS_ESR_MASK_CLEAR, 0x14, AUD_FMM_MS_ESR_MASK_CLEAR, 0x27a014) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, USEQ_SLEEP, 10, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, USEQ_ERROR1, 9, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, CBIT_PING_PONG1, 8, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, RAMP_DONE1, 7, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, FLOWON1, 6, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, UNDERFLOW1, 5, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, USEQ_ERROR0, 4, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, CBIT_PING_PONG0, 3, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, RAMP_DONE0, 2, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, FLOWON0, 1, 1) + FldFunc(AUD_FMM_MS_ESR_MASK_CLEAR, UNDERFLOW0, 0, 1) + +RegAreaFunc(AUD_FMM_OP_CTRL_BASE, 0x0027c000, 0x0027c1fc) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_ENABLE_STATUS, 0x0, AUD_FMM_OP_CTRL_ENABLE_STATUS, 0x27c000) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, ALIGN_I2S_SAMPLES, 19, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, ALIGN_FLEX_SAMPLES, 18, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, I2S_LRCK_ENAI2, 17, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, FLEX_LRCK_ENA, 16, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, STREAM5_ENA, 5, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, STREAM4_ENA, 4, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, STREAM3_ENA, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, STREAM2_ENA, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, STREAM1_ENA, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_STATUS, STREAM0_ENA, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_ENABLE_SET, 0x4, AUD_FMM_OP_CTRL_ENABLE_SET, 0x27c004) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, ALIGN_I2S_SAMPLES, 19, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, ALIGN_FLEX_SAMPLES, 18, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, I2S_LRCK_ENAI2, 17, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, FLEX_LRCK_ENA, 16, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, STREAM5_ENA, 5, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, STREAM4_ENA, 4, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, STREAM3_ENA, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, STREAM2_ENA, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, STREAM1_ENA, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_SET, STREAM0_ENA, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_ENABLE_CLEAR, 0x8, AUD_FMM_OP_CTRL_ENABLE_CLEAR, 0x27c008) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, ALIGN_I2S_SAMPLES, 19, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, ALIGN_FLEX_SAMPLES, 18, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, I2S_LRCK_ENAI2, 17, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, FLEX_LRCK_ENA, 16, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, STREAM5_ENA, 5, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, STREAM4_ENA, 4, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, STREAM3_ENA, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, STREAM2_ENA, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, STREAM1_ENA, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_ENABLE_CLEAR, STREAM0_ENA, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_TIMING_INIT, 0x10, AUD_FMM_OP_CTRL_TIMING_INIT, 0x27c010) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, ALIGN_FS, 16, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, ALIGN_ENA_SPDIF, 12, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, ALIGN_ENA_FLEX, 11, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, ALIGN_ENA_I2S2, 10, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, ALIGN_ENA_I2S1, 9, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, ALIGN_ENA_I2S0, 8, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, INIT_FSCNT_SPDIF0, 4, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, INIT_FSCNT_FLEX, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, INIT_FSCNT_I2S2, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, INIT_FSCNT_I2S1, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_TIMING_INIT, INIT_FSCNT_I2S0, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_STREAM_CFG, 0x20, AUD_FMM_OP_CTRL_STREAM_CFG, 0x27c020) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, RFMOD_SEL, 28, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, MAI_SEL, 24, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, FLEX_USE_SPDIF, 22, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, FLEX_SEL, 20, 2) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, DAC0_USE_SPDIF, 18, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, DAC1_DRIVE_REQ, 17, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, DAC0_DRIVE_REQ, 16, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, WAIT_FOR_VALID5, 13, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, WAIT_FOR_VALID4, 12, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, WAIT_FOR_VALID3, 11, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, WAIT_FOR_VALID2, 10, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, WAIT_FOR_VALID1, 9, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, WAIT_FOR_VALID0, 8, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, IGNORE_FIRST_UNDERFLOW5, 5, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, IGNORE_FIRST_UNDERFLOW4, 4, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, IGNORE_FIRST_UNDERFLOW3, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, IGNORE_FIRST_UNDERFLOW2, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, IGNORE_FIRST_UNDERFLOW1, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_STREAM_CFG, IGNORE_FIRST_UNDERFLOW0, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_SPDIF_CFG_0, 0x30, AUD_FMM_OP_CTRL_SPDIF_CFG_0, 0x27c030) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, LR_SELECT, 24, 2) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, LIMIT_TO_16_BITS, 8, 1) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, MCLK_RATE, 4, 4) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, PREAM_POL, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, SOFT_PARITY, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, DATA_ENABLE, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_SPDIF_CFG_0, CLOCK_ENABLE, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_I2S_CFG_, 0x40, AUD_FMM_OP_CTRL_I2S_CFG_, 0x27c040) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, LR_SELECT, 24, 2) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, DATA_JUSTIFICATION, 23, 1) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, DATA_ALIGNMENT, 22, 1) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, SCLK_POLARITY, 21, 1) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, LRCK_POLARITY, 20, 1) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, SCLKS_PER_1FS_DIV32, 16, 4) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, BITS_PER_SAMPLE, 8, 5) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, MCLK_RATE, 4, 4) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, DATA_ENABLE, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_I2S_CFG_, CLOCK_ENABLE, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_FLEX_CFG1, 0x50, AUD_FMM_OP_CTRL_FLEX_CFG1, 0x27c050) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SLAVE_STREAM, 13, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, IGNORE_VALID, 12, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, REQUEST_LOW, 11, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, IGNORE_REQ_TO_SEND, 10, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, WORD_LENGTH, 8, 2) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, LSB_FIRST, 7, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SYNC_LOW, 6, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SYNC_FORMAT, 5, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SYNC_POSITION, 4, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SYNC_LENGTH, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SCLK_CON_GAP, 2, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, SCLK_PHASE, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG1, ENABLE, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_FLEX_CFG2, 0x54, AUD_FMM_OP_CTRL_FLEX_CFG2, 0x27c054) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, CLOCK_SEL, 28, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, CLOCK_RATE, 20, 8) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, M, 19, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, USE_STRM_BYTECNT, 18, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, BYTES_PER_FMM_REQ, 15, 3) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, BITS_PER_SAMPLE, 7, 5) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, DATA_JUSTIFICATION, 3, 1) + FldFunc(AUD_FMM_OP_CTRL_FLEX_CFG2, DATA_ENABLE, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, 0x58, AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, 0x27c058) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_0, 28, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_1, 24, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_2, 20, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_3, 16, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_4, 12, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_5, 8, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_6, 4, 4) + FldFunc(AUD_FMM_OP_CTRL_FLEX_BYTE_ORDER, BYTE_7, 0, 4) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_FLEX_THROTTLE, 0x5c, AUD_FMM_OP_CTRL_FLEX_THROTTLE, 0x27c05c) + FldFunc(AUD_FMM_OP_CTRL_FLEX_THROTTLE, THROTTLE, 0, 12) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_MAI_CFG, 0x70, AUD_FMM_OP_CTRL_MAI_CFG, 0x27c070) + FldFunc(AUD_FMM_OP_CTRL_MAI_CFG, LR_SELECT, 24, 2) + FldFunc(AUD_FMM_OP_CTRL_MAI_CFG, SPDIF_MODE, 1, 1) + FldFunc(AUD_FMM_OP_CTRL_MAI_CFG, ENABLE_MAI, 0, 1) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_MAI_FORMAT, 0x74, AUD_FMM_OP_CTRL_MAI_FORMAT, 0x27c074) + FldFunc(AUD_FMM_OP_CTRL_MAI_FORMAT, RESERVED, 29, 3) + FldFunc(AUD_FMM_OP_CTRL_MAI_FORMAT, SAMPLE_WIDTH, 24, 5) + FldFunc(AUD_FMM_OP_CTRL_MAI_FORMAT, AUDIO_FORMAT, 16, 8) + FldFunc(AUD_FMM_OP_CTRL_MAI_FORMAT, SAMPLE_RATE, 8, 8) + FldFunc(AUD_FMM_OP_CTRL_MAI_FORMAT, STREAM_ID, 4, 4) + FldFunc(AUD_FMM_OP_CTRL_MAI_FORMAT, MAI_VERSION, 0, 4) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_MCLK_CFG_SPDIF0, 0x100, AUD_FMM_OP_CTRL_MCLK_CFG_SPDIF0, 0x27c100) + FldFunc(AUD_FMM_OP_CTRL_MCLK_CFG_SPDIF0, PLLCLKSEL, 0, 3) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_MCLK_CFG_FLEX, 0x110, AUD_FMM_OP_CTRL_MCLK_CFG_FLEX, 0x27c110) + FldFunc(AUD_FMM_OP_CTRL_MCLK_CFG_FLEX, PLLCLKSEL, 0, 3) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_MCLK_CFG_I2S, 0x120, AUD_FMM_OP_CTRL_MCLK_CFG_I2S, 0x27c120) + FldFunc(AUD_FMM_OP_CTRL_MCLK_CFG_I2S, PLLCLKSEL, 0, 3) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_MCLK_CFG_EXT, 0x130, AUD_FMM_OP_CTRL_MCLK_CFG_EXT, 0x27c130) + FldFunc(AUD_FMM_OP_CTRL_MCLK_CFG_EXT, PLLCLKSEL, 0, 3) +RegFunc(AUD_FMM_OP_CTRL, 0x0027c000, AUD_FMM_OP_CTRL_DIAG_CFG, 0x1fc, AUD_FMM_OP_CTRL_DIAG_CFG, 0x27c1fc) + FldFunc(AUD_FMM_OP_CTRL_DIAG_CFG, SEL, 0, 3) + +RegAreaFunc(AUD_FMM_OP_ESR_BASE, 0x0027c400, 0x0027c414) +RegFunc(AUD_FMM_OP_ESR, 0x0027c400, AUD_FMM_OP_ESR_STATUS, 0x0, AUD_FMM_OP_ESR_STATUS, 0x27c400) + FldFunc(AUD_FMM_OP_ESR_STATUS, PLL2_LOCKPL, 9, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, PLL1_LOCKPL, 8, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, PLL0_LOCKPL, 7, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, MAI_TIMING_ERRORMA, 6, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, STREAM5_UNDERFLOW, 5, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, STREAM4_UNDERFLOW, 4, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, STREAM3_UNDERFLOW, 3, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, STREAM2_UNDERFLOW, 2, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, STREAM1_UNDERFLOW, 1, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS, STREAM0_UNDERFLOW, 0, 1) +RegFunc(AUD_FMM_OP_ESR, 0x0027c400, AUD_FMM_OP_ESR_STATUS_SET, 0x4, AUD_FMM_OP_ESR_STATUS_SET, 0x27c404) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, PLL2_LOCKPL, 9, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, PLL1_LOCKPL, 8, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, PLL0_LOCKPL, 7, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, MAI_TIMING_ERRORMA, 6, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, STREAM5_UNDERFLOW, 5, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, STREAM4_UNDERFLOW, 4, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, STREAM3_UNDERFLOW, 3, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, STREAM2_UNDERFLOW, 2, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, STREAM1_UNDERFLOW, 1, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_SET, STREAM0_UNDERFLOW, 0, 1) +RegFunc(AUD_FMM_OP_ESR, 0x0027c400, AUD_FMM_OP_ESR_STATUS_CLEAR, 0x8, AUD_FMM_OP_ESR_STATUS_CLEAR, 0x27c408) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, PLL2_LOCKPL, 9, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, PLL1_LOCKPL, 8, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, PLL0_LOCKPL, 7, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, MAI_TIMING_ERRORMA, 6, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, STREAM5_UNDERFLOW, 5, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, STREAM4_UNDERFLOW, 4, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, STREAM3_UNDERFLOW, 3, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, STREAM2_UNDERFLOW, 2, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, STREAM1_UNDERFLOW, 1, 1) + FldFunc(AUD_FMM_OP_ESR_STATUS_CLEAR, STREAM0_UNDERFLOW, 0, 1) +RegFunc(AUD_FMM_OP_ESR, 0x0027c400, AUD_FMM_OP_ESR_MASK, 0xc, AUD_FMM_OP_ESR_MASK, 0x27c40c) + FldFunc(AUD_FMM_OP_ESR_MASK, PLL2_LOCKPL, 9, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, PLL1_LOCKPL, 8, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, PLL0_LOCKPL, 7, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, MAI_TIMING_ERRORMA, 6, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, STREAM5_UNDERFLOW, 5, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, STREAM4_UNDERFLOW, 4, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, STREAM3_UNDERFLOW, 3, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, STREAM2_UNDERFLOW, 2, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, STREAM1_UNDERFLOW, 1, 1) + FldFunc(AUD_FMM_OP_ESR_MASK, STREAM0_UNDERFLOW, 0, 1) +RegFunc(AUD_FMM_OP_ESR, 0x0027c400, AUD_FMM_OP_ESR_MASK_SET, 0x10, AUD_FMM_OP_ESR_MASK_SET, 0x27c410) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, PLL2_LOCKPL, 9, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, PLL1_LOCKPL, 8, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, PLL0_LOCKPL, 7, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, MAI_TIMING_ERRORMA, 6, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, STREAM5_UNDERFLOW, 5, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, STREAM4_UNDERFLOW, 4, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, STREAM3_UNDERFLOW, 3, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, STREAM2_UNDERFLOW, 2, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, STREAM1_UNDERFLOW, 1, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_SET, STREAM0_UNDERFLOW, 0, 1) +RegFunc(AUD_FMM_OP_ESR, 0x0027c400, AUD_FMM_OP_ESR_MASK_CLEAR, 0x14, AUD_FMM_OP_ESR_MASK_CLEAR, 0x27c414) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, PLL2_LOCKPL, 9, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, PLL1_LOCKPL, 8, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, PLL0_LOCKPL, 7, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, MAI_TIMING_ERRORMA, 6, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, STREAM5_UNDERFLOW, 5, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, STREAM4_UNDERFLOW, 4, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, STREAM3_UNDERFLOW, 3, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, STREAM2_UNDERFLOW, 2, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, STREAM1_UNDERFLOW, 1, 1) + FldFunc(AUD_FMM_OP_ESR_MASK_CLEAR, STREAM0_UNDERFLOW, 0, 1) + +RegAreaFunc(AUD_FMM_PLL0_BASE, 0x0027c800, 0x0027c81c) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_MACRO, 0x0, AUD_FMM_PLL0_MACRO, 0x27c800) + FldFunc(AUD_FMM_PLL0_MACRO, MACRO_SELECT, 0, 3) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_STATUS, 0x4, AUD_FMM_PLL0_STATUS, 0x27c804) + FldFunc(AUD_FMM_PLL0_STATUS, PLL_FSM_STATE, 1, 2) + FldFunc(AUD_FMM_PLL0_STATUS, PLL_FSM_OUTPUT_ENA, 0, 1) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_CONTROL, 0x8, AUD_FMM_PLL0_CONTROL, 0x27c808) + FldFunc(AUD_FMM_PLL0_CONTROL, REFERENCE_SELECT, 4, 2) + FldFunc(AUD_FMM_PLL0_CONTROL, UPDATE_OVERRIDE, 3, 1) + FldFunc(AUD_FMM_PLL0_CONTROL, USER_UPDATE_DIVIDERS, 2, 1) + FldFunc(AUD_FMM_PLL0_CONTROL, OUTPUT_OVERRIDE, 1, 1) + FldFunc(AUD_FMM_PLL0_CONTROL, USER_OUTPUT_ENABLE, 0, 1) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_USER_DIV1, 0xc, AUD_FMM_PLL0_USER_DIV1, 0x27c80c) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_PLLBYP2, 26, 1) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_HGEAR2, 25, 1) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_FDIV2, 21, 4) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_FSEL2, 16, 5) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_PLLBYP1, 10, 1) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_HGEAR1, 9, 1) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_FDIV1, 5, 4) + FldFunc(AUD_FMM_PLL0_USER_DIV1, USER_FSEL1, 0, 5) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_USER_DIV2, 0x10, AUD_FMM_PLL0_USER_DIV2, 0x27c810) + FldFunc(AUD_FMM_PLL0_USER_DIV2, USER_HGEAR3, 9, 1) + FldFunc(AUD_FMM_PLL0_USER_DIV2, USER_FDIV3, 5, 4) + FldFunc(AUD_FMM_PLL0_USER_DIV2, USER_FSEL3, 0, 5) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_ACTIVE_DIV1, 0x14, AUD_FMM_PLL0_ACTIVE_DIV1, 0x27c814) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, PLLBYP2, 26, 1) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, HGEAR2, 25, 1) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, FDIV2, 21, 4) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, FSEL2, 16, 5) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, EXTCLKDIV, 11, 5) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, PLLBYP1, 10, 1) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, HGEAR1, 9, 1) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, FDIV1, 5, 4) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV1, FSEL1, 0, 5) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_ACTIVE_DIV2, 0x18, AUD_FMM_PLL0_ACTIVE_DIV2, 0x27c818) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV2, HGEAR3, 9, 1) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV2, FDIV3, 5, 4) + FldFunc(AUD_FMM_PLL0_ACTIVE_DIV2, FSEL3, 0, 5) +RegFunc(AUD_FMM_PLL0, 0x0027c800, AUD_FMM_PLL0_DIVIDER, 0x1c, AUD_FMM_PLL0_DIVIDER, 0x27c81c) + FldFunc(AUD_FMM_PLL0_DIVIDER, USERCLKDIV, 11, 5) + FldFunc(AUD_FMM_PLL0_DIVIDER, LOCK_TIMERPL, 0, 11) + +RegAreaFunc(AUD_FMM_PLL1_BASE, 0x0027c900, 0x0027c91c) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_MACRO, 0x0, AUD_FMM_PLL1_MACRO, 0x27c900) + FldFunc(AUD_FMM_PLL1_MACRO, MACRO_SELECT, 0, 3) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_STATUS, 0x4, AUD_FMM_PLL1_STATUS, 0x27c904) + FldFunc(AUD_FMM_PLL1_STATUS, PLL_FSM_STATE, 1, 2) + FldFunc(AUD_FMM_PLL1_STATUS, PLL_FSM_OUTPUT_ENA, 0, 1) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_CONTROL, 0x8, AUD_FMM_PLL1_CONTROL, 0x27c908) + FldFunc(AUD_FMM_PLL1_CONTROL, REFERENCE_SELECT, 4, 2) + FldFunc(AUD_FMM_PLL1_CONTROL, UPDATE_OVERRIDE, 3, 1) + FldFunc(AUD_FMM_PLL1_CONTROL, USER_UPDATE_DIVIDERS, 2, 1) + FldFunc(AUD_FMM_PLL1_CONTROL, OUTPUT_OVERRIDE, 1, 1) + FldFunc(AUD_FMM_PLL1_CONTROL, USER_OUTPUT_ENABLE, 0, 1) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_USER_DIV1, 0xc, AUD_FMM_PLL1_USER_DIV1, 0x27c90c) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_PLLBYP2, 26, 1) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_HGEAR2, 25, 1) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_FDIV2, 21, 4) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_FSEL2, 16, 5) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_PLLBYP1, 10, 1) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_HGEAR1, 9, 1) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_FDIV1, 5, 4) + FldFunc(AUD_FMM_PLL1_USER_DIV1, USER_FSEL1, 0, 5) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_USER_DIV2, 0x10, AUD_FMM_PLL1_USER_DIV2, 0x27c910) + FldFunc(AUD_FMM_PLL1_USER_DIV2, USER_HGEAR3, 9, 1) + FldFunc(AUD_FMM_PLL1_USER_DIV2, USER_FDIV3, 5, 4) + FldFunc(AUD_FMM_PLL1_USER_DIV2, USER_FSEL3, 0, 5) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_ACTIVE_DIV1, 0x14, AUD_FMM_PLL1_ACTIVE_DIV1, 0x27c914) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, PLLBYP2, 26, 1) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, HGEAR2, 25, 1) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, FDIV2, 21, 4) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, FSEL2, 16, 5) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, EXTCLKDIV, 11, 5) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, PLLBYP1, 10, 1) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, HGEAR1, 9, 1) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, FDIV1, 5, 4) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV1, FSEL1, 0, 5) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_ACTIVE_DIV2, 0x18, AUD_FMM_PLL1_ACTIVE_DIV2, 0x27c918) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV2, HGEAR3, 9, 1) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV2, FDIV3, 5, 4) + FldFunc(AUD_FMM_PLL1_ACTIVE_DIV2, FSEL3, 0, 5) +RegFunc(AUD_FMM_PLL1, 0x0027c900, AUD_FMM_PLL1_DIVIDER, 0x1c, AUD_FMM_PLL1_DIVIDER, 0x27c91c) + FldFunc(AUD_FMM_PLL1_DIVIDER, USERCLKDIV, 11, 5) + FldFunc(AUD_FMM_PLL1_DIVIDER, LOCK_TIMERPL, 0, 11) + +RegAreaFunc(AUD_FMM_PLL2_BASE, 0x0027ca00, 0x0027ca1c) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_MACRO, 0x0, AUD_FMM_PLL2_MACRO, 0x27ca00) + FldFunc(AUD_FMM_PLL2_MACRO, MACRO_SELECT, 0, 3) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_STATUS, 0x4, AUD_FMM_PLL2_STATUS, 0x27ca04) + FldFunc(AUD_FMM_PLL2_STATUS, PLL_FSM_STATE, 1, 2) + FldFunc(AUD_FMM_PLL2_STATUS, PLL_FSM_OUTPUT_ENA, 0, 1) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_CONTROL, 0x8, AUD_FMM_PLL2_CONTROL, 0x27ca08) + FldFunc(AUD_FMM_PLL2_CONTROL, REFERENCE_SELECT, 4, 2) + FldFunc(AUD_FMM_PLL2_CONTROL, UPDATE_OVERRIDE, 3, 1) + FldFunc(AUD_FMM_PLL2_CONTROL, USER_UPDATE_DIVIDERS, 2, 1) + FldFunc(AUD_FMM_PLL2_CONTROL, OUTPUT_OVERRIDE, 1, 1) + FldFunc(AUD_FMM_PLL2_CONTROL, USER_OUTPUT_ENABLE, 0, 1) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_USER_DIV1, 0xc, AUD_FMM_PLL2_USER_DIV1, 0x27ca0c) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_PLLBYP2, 26, 1) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_HGEAR2, 25, 1) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_FDIV2, 21, 4) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_FSEL2, 16, 5) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_PLLBYP1, 10, 1) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_HGEAR1, 9, 1) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_FDIV1, 5, 4) + FldFunc(AUD_FMM_PLL2_USER_DIV1, USER_FSEL1, 0, 5) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_USER_DIV2, 0x10, AUD_FMM_PLL2_USER_DIV2, 0x27ca10) + FldFunc(AUD_FMM_PLL2_USER_DIV2, USER_HGEAR3, 9, 1) + FldFunc(AUD_FMM_PLL2_USER_DIV2, USER_FDIV3, 5, 4) + FldFunc(AUD_FMM_PLL2_USER_DIV2, USER_FSEL3, 0, 5) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_ACTIVE_DIV1, 0x14, AUD_FMM_PLL2_ACTIVE_DIV1, 0x27ca14) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, PLLBYP2, 26, 1) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, HGEAR2, 25, 1) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, FDIV2, 21, 4) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, FSEL2, 16, 5) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, EXTCLKDIV, 11, 5) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, PLLBYP1, 10, 1) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, HGEAR1, 9, 1) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, FDIV1, 5, 4) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV1, FSEL1, 0, 5) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_ACTIVE_DIV2, 0x18, AUD_FMM_PLL2_ACTIVE_DIV2, 0x27ca18) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV2, HGEAR3, 9, 1) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV2, FDIV3, 5, 4) + FldFunc(AUD_FMM_PLL2_ACTIVE_DIV2, FSEL3, 0, 5) +RegFunc(AUD_FMM_PLL2, 0x0027ca00, AUD_FMM_PLL2_DIVIDER, 0x1c, AUD_FMM_PLL2_DIVIDER, 0x27ca1c) + FldFunc(AUD_FMM_PLL2_DIVIDER, USERCLKDIV, 11, 5) + FldFunc(AUD_FMM_PLL2_DIVIDER, LOCK_TIMERPL, 0, 11) + +RegAreaFunc(AUD_FMM_NCO_BASE, 0x0027d000, 0x0027d004) +RegFunc(AUD_FMM_NCO, 0x0027d000, AUD_FMM_NCO_FMM_NCO_CNTL0, 0x0, AUD_FMM_NCO_FMM_NCO_CNTL0, 0x27d000) + FldFunc(AUD_FMM_NCO_FMM_NCO_CNTL0, FMM_NCO_NUM, 16, 16) + FldFunc(AUD_FMM_NCO_FMM_NCO_CNTL0, FMM_NCO_INT, 0, 16) +RegFunc(AUD_FMM_NCO, 0x0027d000, AUD_FMM_NCO_FMM_NCO_CNTL1, 0x4, AUD_FMM_NCO_FMM_NCO_CNTL1, 0x27d004) + FldFunc(AUD_FMM_NCO_FMM_NCO_CNTL1, FMM_NCO_DEN, 0, 32) + +#endif + + +//****************************************************************************** +// +// Host Interfaces Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_HOST_INTERFACES + +RegAreaFunc(HostifRbnodeRegsBase, 0x300000, 0x30007F) +RegFunc(HostifRbnodeRegs, 0x300000, RbConfig , 0x0, HosRRs_RbConfig , 0x300000) + FldFunc(HosRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(HosRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(HostifRbnodeRegs, 0x300000, RbStickyError, 0x4, HosRRs_RbStickyError, 0x300004) + FldFunc(HosRRs_RbStickyError, Node, 1, 1) + FldFunc(HosRRs_RbStickyError, Tgt, 0, 1) +RegFunc(HostifRbnodeRegs, 0x300000, RbCurrentError, 0x8, HosRRs_RbCurrentError, 0x300008) + FldFunc(HosRRs_RbCurrentError, Node, 1, 1) + FldFunc(HosRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(HostifRbnodeRegs, 0x300000, RbReadData, 0xC, HosRRs_RbReadData, 0x30000c) + FldFunc(HosRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(HostifRingbusDebugRegs0Base, 0x300080, 0x3000FF) +RegFunc(HostifRingbusDebugRegs0, 0x300080, RbDebugConfig, 0x0, HosRDR0_RbDebugConfig, 0x300080) + FldFunc(HosRDR0_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(HosRDR0_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(HostifRingbusDebugRegs0, 0x300080, RbDebugReg0Addr, 0x4, HosRDR0_RbDebugReg0Addr, 0x300084) + FldFunc(HosRDR0_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs0, 0x300080, RbDebugReg1Addr, 0x8, HosRDR0_RbDebugReg1Addr, 0x300088) + FldFunc(HosRDR0_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs0, 0x300080, RbDebugReg2Addr, 0xC, HosRDR0_RbDebugReg2Addr, 0x30008c) + FldFunc(HosRDR0_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs0, 0x300080, RbDebugReg3Addr, 0x10, HosRDR0_RbDebugReg3Addr, 0x300090) + FldFunc(HosRDR0_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs0, 0x300080, RbDebugOutputReg, 0x14, HosRDR0_RbDebugOutputReg, 0x300094) + FldFunc(HosRDR0_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(HosRDR0_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(HostifRingbusDebugRegs1Base, 0x300100, 0x30017F) +RegFunc(HostifRingbusDebugRegs1, 0x300100, RbDebugConfig, 0x0, HosRDR1_RbDebugConfig, 0x300100) + FldFunc(HosRDR1_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(HosRDR1_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(HostifRingbusDebugRegs1, 0x300100, RbDebugReg0Addr, 0x4, HosRDR1_RbDebugReg0Addr, 0x300104) + FldFunc(HosRDR1_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs1, 0x300100, RbDebugReg1Addr, 0x8, HosRDR1_RbDebugReg1Addr, 0x300108) + FldFunc(HosRDR1_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs1, 0x300100, RbDebugReg2Addr, 0xC, HosRDR1_RbDebugReg2Addr, 0x30010c) + FldFunc(HosRDR1_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs1, 0x300100, RbDebugReg3Addr, 0x10, HosRDR1_RbDebugReg3Addr, 0x300110) + FldFunc(HosRDR1_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(HostifRingbusDebugRegs1, 0x300100, RbDebugOutputReg, 0x14, HosRDR1_RbDebugOutputReg, 0x300114) + FldFunc(HosRDR1_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(HosRDR1_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(DecodeHostBase, 0x340000, 0x3400FF) +RegFunc(DecodeHost, 0x340000, HostSwReset, 0x0, DecHt_HostSwReset, 0x340000) + FldFunc(DecHt_HostSwReset, Rst, 0, 1) +RegFunc(DecodeHost, 0x340000, HostIntmask, 0x4, DecHt_HostIntmask, 0x340004) + FldFunc(DecHt_HostIntmask, High, 2, 1) + FldFunc(DecHt_HostIntmask, Low, 1, 1) + FldFunc(DecHt_HostIntmask, Ext, 0, 1) +RegFunc(DecodeHost, 0x340000, HostJtagSel, 0x8, DecHt_HostJtagSel, 0x340008) + FldFunc(DecHt_HostJtagSel, MuxACtl, 3, 3) + FldFunc(DecHt_HostJtagSel, MuxBCtl, 0, 3) +RegFunc(DecodeHost, 0x340000, HostPllaCtl, 0xC, DecHt_HostPllaCtl, 0x34000c) + FldFunc(DecHt_HostPllaCtl, Lock, 17, 1) + FldFunc(DecHt_HostPllaCtl, Bypen, 16, 1) + FldFunc(DecHt_HostPllaCtl, Pdn, 15, 1) + FldFunc(DecHt_HostPllaCtl, Reset, 14, 1) + FldFunc(DecHt_HostPllaCtl, VcoMg, 12, 2) + FldFunc(DecHt_HostPllaCtl, M, 6, 6) + FldFunc(DecHt_HostPllaCtl, N, 0, 6) +RegFunc(DecodeHost, 0x340000, HostPllbCtl, 0x10, DecHt_HostPllbCtl, 0x340010) + FldFunc(DecHt_HostPllbCtl, Lock, 17, 1) + FldFunc(DecHt_HostPllbCtl, Bypen, 16, 1) + FldFunc(DecHt_HostPllbCtl, Pdn, 15, 1) + FldFunc(DecHt_HostPllbCtl, Reset, 14, 1) + FldFunc(DecHt_HostPllbCtl, VcoMg, 12, 2) + FldFunc(DecHt_HostPllbCtl, M, 6, 6) + FldFunc(DecHt_HostPllbCtl, N, 0, 6) +RegFunc(DecodeHost, 0x340000, HostPllcCtl, 0x14, DecHt_HostPllcCtl, 0x340014) + FldFunc(DecHt_HostPllcCtl, Lock, 17, 1) + FldFunc(DecHt_HostPllcCtl, Bypen, 16, 1) + FldFunc(DecHt_HostPllcCtl, Pdn, 15, 1) + FldFunc(DecHt_HostPllcCtl, Reset, 14, 1) + FldFunc(DecHt_HostPllcCtl, VcoMg, 12, 2) + FldFunc(DecHt_HostPllcCtl, M, 6, 6) + FldFunc(DecHt_HostPllcCtl, N, 0, 6) +RegFunc(DecodeHost, 0x340000, HostTsOutHalfFull, 0x18, DecHt_HostTsOutHalfFull, 0x340018) + FldFunc(DecHt_HostTsOutHalfFull, FifoNonEmpty, 1, 1) + FldFunc(DecHt_HostTsOutHalfFull, HalfFull, 0, 1) +RegFunc(DecodeHost, 0x340000, HostBondoutCode, 0x1C, DecHt_HostBondoutCode, 0x34001c) + FldFunc(DecHt_HostBondoutCode, BondoutValue, 0, 4) +RegFunc(DecodeHost, 0x340000, HostPciDramWindow, 0x20, DecHt_HostPciDramWindow, 0x340020) + FldFunc(DecHt_HostPciDramWindow, Window, 0, 13) +RegFunc(DecodeHost, 0x340000, HostH8Inc, 0x24, DecHt_HostH8Inc, 0x340024) + FldFunc(DecHt_HostH8Inc, Inc, 0, 1) +RegFunc(DecodeHost, 0x340000, HostSpiInc, 0x28, DecHt_HostSpiInc, 0x340028) + FldFunc(DecHt_HostSpiInc, Inc, 0, 1) +RegFunc(DecodeHost, 0x340000, HostStreamA, 0x2C, DecHt_HostStreamA, 0x34002c) + FldFunc(DecHt_HostStreamA, Data, 0, 32) +RegFunc(DecodeHost, 0x340000, HostStreamB, 0x30, DecHt_HostStreamB, 0x340030) + FldFunc(DecHt_HostStreamB, Data, 0, 32) +RegFunc(DecodeHost, 0x340000, HostPlldCtl, 0x34, DecHt_HostPlldCtl, 0x340034) + FldFunc(DecHt_HostPlldCtl, Lock, 17, 1) + FldFunc(DecHt_HostPlldCtl, Bypen, 16, 1) + FldFunc(DecHt_HostPlldCtl, Pdn, 15, 1) + FldFunc(DecHt_HostPlldCtl, Reset, 14, 1) + FldFunc(DecHt_HostPlldCtl, VcoMg, 12, 2) + FldFunc(DecHt_HostPlldCtl, M, 6, 6) + FldFunc(DecHt_HostPlldCtl, N, 0, 6) +RegFunc(DecodeHost, 0x340000, HostPlleCtl, 0x38, DecHt_HostPlleCtl, 0x340038) + FldFunc(DecHt_HostPlleCtl, Lock, 17, 1) + FldFunc(DecHt_HostPlleCtl, Bypen, 16, 1) + FldFunc(DecHt_HostPlleCtl, Pdn, 15, 1) + FldFunc(DecHt_HostPlleCtl, Reset, 14, 1) + FldFunc(DecHt_HostPlleCtl, VcoMg, 12, 2) + FldFunc(DecHt_HostPlleCtl, M, 6, 6) + FldFunc(DecHt_HostPlleCtl, N, 0, 6) +RegFunc(DecodeHost, 0x340000, HostSpiDramWindow, 0x3C, DecHt_HostSpiDramWindow, 0x34003c) + FldFunc(DecHt_HostSpiDramWindow, Window, 0, 13) +RegFunc(DecodeHost, 0x340000, HostStreamTimeout, 0x40, DecHt_HostStreamTimeout, 0x340040) + FldFunc(DecHt_HostStreamTimeout, Timeout, 0, 16) +RegFunc(DecodeHost, 0x340000, HostDramTimeout, 0x44, DecHt_HostDramTimeout, 0x340044) + FldFunc(DecHt_HostDramTimeout, Timeout, 0, 16) +RegFunc(DecodeHost, 0x340000, HostTimeoutStatus, 0x48, DecHt_HostTimeoutStatus, 0x340048) + FldFunc(DecHt_HostTimeoutStatus, CodeOut, 8, 1) + FldFunc(DecHt_HostTimeoutStatus, CodeIn, 7, 1) + FldFunc(DecHt_HostTimeoutStatus, DramRd, 6, 1) + FldFunc(DecHt_HostTimeoutStatus, DramWr, 5, 1) + FldFunc(DecHt_HostTimeoutStatus, RingBus, 4, 1) + FldFunc(DecHt_HostTimeoutStatus, TsAfullB, 3, 1) + FldFunc(DecHt_HostTimeoutStatus, TsAfullA, 2, 1) + FldFunc(DecHt_HostTimeoutStatus, TsHfullB, 1, 1) + FldFunc(DecHt_HostTimeoutStatus, TsHfullA, 0, 1) +RegFunc(DecodeHost, 0x340000, HostSelRefClk, 0x4C, DecHt_HostSelRefClk, 0x34004c) + FldFunc(DecHt_HostSelRefClk, Sel, 0, 1) + +RegAreaFunc(PciDmaRegBase, 0x340100, 0x3401FF) +RegFunc(PciDmaReg, 0x340100, PciDmaSrcAddr0, 0x0, PciDRg_PciDmaSrcAddr0, 0x340100) + FldFunc(PciDRg_PciDmaSrcAddr0, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaDstAddr0, 0x4, PciDRg_PciDmaDstAddr0, 0x340104) + FldFunc(PciDRg_PciDmaDstAddr0, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaCnt0, 0x8, PciDRg_PciDmaCnt0, 0x340108) + FldFunc(PciDRg_PciDmaCnt0, Active, 31, 1) + FldFunc(PciDRg_PciDmaCnt0, Error, 30, 1) + FldFunc(PciDRg_PciDmaCnt0, Int, 29, 1) + FldFunc(PciDRg_PciDmaCnt0, Sdram, 22, 1) + FldFunc(PciDRg_PciDmaCnt0, IncDst, 21, 1) + FldFunc(PciDRg_PciDmaCnt0, IncSrc, 20, 1) + FldFunc(PciDRg_PciDmaCnt0, XferCnt, 0, 20) +RegFunc(PciDmaReg, 0x340100, PciDmaSrcAddr1, 0x10, PciDRg_PciDmaSrcAddr1, 0x340110) + FldFunc(PciDRg_PciDmaSrcAddr1, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaDstAddr1, 0x14, PciDRg_PciDmaDstAddr1, 0x340114) + FldFunc(PciDRg_PciDmaDstAddr1, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaCnt1, 0x18, PciDRg_PciDmaCnt1, 0x340118) + FldFunc(PciDRg_PciDmaCnt1, Active, 31, 1) + FldFunc(PciDRg_PciDmaCnt1, Error, 30, 1) + FldFunc(PciDRg_PciDmaCnt1, Int, 29, 1) + FldFunc(PciDRg_PciDmaCnt1, Sdram, 22, 1) + FldFunc(PciDRg_PciDmaCnt1, IncDst, 21, 1) + FldFunc(PciDRg_PciDmaCnt1, IncSrc, 20, 1) + FldFunc(PciDRg_PciDmaCnt1, XferCnt, 0, 20) +RegFunc(PciDmaReg, 0x340100, PciDmaSrcAddr2, 0x20, PciDRg_PciDmaSrcAddr2, 0x340120) + FldFunc(PciDRg_PciDmaSrcAddr2, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaDstAddr2, 0x24, PciDRg_PciDmaDstAddr2, 0x340124) + FldFunc(PciDRg_PciDmaDstAddr2, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaCnt2, 0x28, PciDRg_PciDmaCnt2, 0x340128) + FldFunc(PciDRg_PciDmaCnt2, Active, 31, 1) + FldFunc(PciDRg_PciDmaCnt2, Error, 30, 1) + FldFunc(PciDRg_PciDmaCnt2, Int, 29, 1) + FldFunc(PciDRg_PciDmaCnt2, Sdram, 22, 1) + FldFunc(PciDRg_PciDmaCnt2, IncDst, 21, 1) + FldFunc(PciDRg_PciDmaCnt2, IncSrc, 20, 1) + FldFunc(PciDRg_PciDmaCnt2, XferCnt, 0, 20) +RegFunc(PciDmaReg, 0x340100, PciDmaSrcAddr3, 0x30, PciDRg_PciDmaSrcAddr3, 0x340130) + FldFunc(PciDRg_PciDmaSrcAddr3, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaDstAddr3, 0x34, PciDRg_PciDmaDstAddr3, 0x340134) + FldFunc(PciDRg_PciDmaDstAddr3, Addr, 0, 32) +RegFunc(PciDmaReg, 0x340100, PciDmaCnt3, 0x38, PciDRg_PciDmaCnt3, 0x340138) + FldFunc(PciDRg_PciDmaCnt3, Active, 31, 1) + FldFunc(PciDRg_PciDmaCnt3, Error, 30, 1) + FldFunc(PciDRg_PciDmaCnt3, Int, 29, 1) + FldFunc(PciDRg_PciDmaCnt3, Sdram, 22, 1) + FldFunc(PciDRg_PciDmaCnt3, IncDst, 21, 1) + FldFunc(PciDRg_PciDmaCnt3, IncSrc, 20, 1) + FldFunc(PciDRg_PciDmaCnt3, XferCnt, 0, 20) + +RegAreaFunc(HostStreamaWindowBase, 0x340200, 0x34023F) +RegFunc(HostStreamaWindow, 0x340200, HostStreamaWindow, 0x0, HosSWw_HostStreamaWindow, 0x340200) + FldFunc(HosSWw_HostStreamaWindow, Data, 0, 32) + +RegAreaFunc(HostStreambWindowBase, 0x340300, 0x34033F) +RegFunc(HostStreambWindow, 0x340300, HostStreambWindow, 0x0, HosSWw_HostStreambWindow, 0x340300) + FldFunc(HosSWw_HostStreambWindow, Data, 0, 32) + +#endif + + +//****************************************************************************** +// +// Encoder Pre Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_ENCODER_PRE + +RegAreaFunc(EncPreRbnodeRegsBase, 0x400000, 0x40007F) +RegFunc(EncPreRbnodeRegs, 0x400000, RbConfig , 0x0, EncPRRs_RbConfig , 0x400000) + FldFunc(EncPRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(EncPRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(EncPreRbnodeRegs, 0x400000, RbStickyError, 0x4, EncPRRs_RbStickyError, 0x400004) + FldFunc(EncPRRs_RbStickyError, Node, 1, 1) + FldFunc(EncPRRs_RbStickyError, Tgt, 0, 1) +RegFunc(EncPreRbnodeRegs, 0x400000, RbCurrentError, 0x8, EncPRRs_RbCurrentError, 0x400008) + FldFunc(EncPRRs_RbCurrentError, Node, 1, 1) + FldFunc(EncPRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(EncPreRbnodeRegs, 0x400000, RbReadData, 0xC, EncPRRs_RbReadData, 0x40000c) + FldFunc(EncPRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(EncPreRingbusDebugRegsBase, 0x400080, 0x4000FF) +RegFunc(EncPreRingbusDebugRegs, 0x400080, RbDebugConfig, 0x0, EncPRDRs_RbDebugConfig, 0x400080) + FldFunc(EncPRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(EncPRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(EncPreRingbusDebugRegs, 0x400080, RbDebugReg0Addr, 0x4, EncPRDRs_RbDebugReg0Addr, 0x400084) + FldFunc(EncPRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(EncPreRingbusDebugRegs, 0x400080, RbDebugReg1Addr, 0x8, EncPRDRs_RbDebugReg1Addr, 0x400088) + FldFunc(EncPRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(EncPreRingbusDebugRegs, 0x400080, RbDebugReg2Addr, 0xC, EncPRDRs_RbDebugReg2Addr, 0x40008c) + FldFunc(EncPRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(EncPreRingbusDebugRegs, 0x400080, RbDebugReg3Addr, 0x10, EncPRDRs_RbDebugReg3Addr, 0x400090) + FldFunc(EncPRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(EncPreRingbusDebugRegs, 0x400080, RbDebugOutputReg, 0x14, EncPRDRs_RbDebugOutputReg, 0x400094) + FldFunc(EncPRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(EncPRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(EncViBase, 0x400100, 0x40013F) +RegFunc(EncVi, 0x400100, EncViHostYuvFrameSize, 0x0, EncVi_EncViHostYuvFrameSize, 0x400100) + FldFunc(EncVi_EncViHostYuvFrameSize, Size, 0, 32) +RegFunc(EncVi, 0x400100, EncViHostYuvBase, 0x4, EncVi_EncViHostYuvBase, 0x400104) + FldFunc(EncVi_EncViHostYuvBase, BaseAddr, 0, 32) +RegFunc(EncVi, 0x400100, EncViHostCtl, 0x8, EncVi_EncViHostCtl, 0x400108) + FldFunc(EncVi_EncViHostCtl, FrDrpCnt, 16, 16) + FldFunc(EncVi_EncViHostCtl, IntMode, 3, 1) + FldFunc(EncVi_EncViHostCtl, FrmDne, 2, 1) + FldFunc(EncVi_EncViHostCtl, HostMode, 1, 1) + FldFunc(EncVi_EncViHostCtl, SftRst, 0, 1) +RegFunc(EncVi, 0x400100, EncViHostYuvBase1, 0xC, EncVi_EncViHostYuvBase1, 0x40010c) + FldFunc(EncVi_EncViHostYuvBase1, BaseAddr, 0, 32) + +RegAreaFunc(EncCmeBase, 0x400300, 0x4003FF) +#if 1 +RegFunc(EncCme, 0x400300, EncCmeCurY, 0x0, EncCe_EncCmeCurY, 0x400300) +RegFunc(EncCme, 0x400300, EncCmeCurC, 0x4, EncCe_EncCmeCurC, 0x400304) +RegFunc(EncCme, 0x400300, EncCmeRefY, 0x8, EncCe_EncCmeRefY, 0x400308) +RegFunc(EncCme, 0x400300, EncCmeRefC, 0xC, EncCe_EncCmeRefC, 0x40030C) +RegFunc(EncCme, 0x400300, EncCmeLoadCtrl, 0x10, EncCe_EncCmeLoadCtrl, 0x400310) + FldFunc(EncCe_EncCmeLoadCtrl, VCB, 30, 2) + FldFunc(EncCe_EncCmeLoadCtrl, HCB, 28, 2) + FldFunc(EncCe_EncCmeLoadCtrl, RefHPos, 26, 2) + FldFunc(EncCe_EncCmeLoadCtrl, RefVPos, 22, 4) + FldFunc(EncCe_EncCmeLoadCtrl, RefHeight, 18, 4) + FldFunc(EncCe_EncCmeLoadCtrl, CurHPos, 16, 2) + FldFunc(EncCe_EncCmeLoadCtrl, CurVPos, 12, 4) + FldFunc(EncCe_EncCmeLoadCtrl, CurHeight, 8, 4) + FldFunc(EncCe_EncCmeLoadCtrl, DoRefC, 7, 1) + FldFunc(EncCe_EncCmeLoadCtrl, DoRefY, 6, 1) + FldFunc(EncCe_EncCmeLoadCtrl, DoCurC, 5, 1) + FldFunc(EncCe_EncCmeLoadCtrl, DoCurY, 4, 1) + FldFunc(EncCe_EncCmeLoadCtrl, Pitch, 3, 1) + FldFunc(EncCe_EncCmeLoadCtrl, EI, 2, 1) + FldFunc(EncCe_EncCmeLoadCtrl, Busy, 1, 1) + FldFunc(EncCe_EncCmeLoadCtrl, Go, 0, 1) +RegFunc(EncCme, 0x400300, EncCmeSearchCtrl, 0x14, EncCe_EncCmeSearchCtrl, 0x400314) + FldFunc(EncCe_EncCmeSearchCtrl, VCB, 30, 2) + FldFunc(EncCe_EncCmeSearchCtrl, HCB, 28, 2) + FldFunc(EncCe_EncCmeSearchCtrl, AltCMB, 26, 2) + FldFunc(EncCe_EncCmeSearchCtrl, Enable, 25, 1) + FldFunc(EncCe_EncCmeSearchCtrl, IgnoreC, 24, 1) + FldFunc(EncCe_EncCmeSearchCtrl, Lambda, 16, 8) + FldFunc(EncCe_EncCmeSearchCtrl, VRadius, 14, 2) + FldFunc(EncCe_EncCmeSearchCtrl, HRadius, 12, 2) + FldFunc(EncCe_EncCmeSearchCtrl, VLimit, 9, 3) + FldFunc(EncCe_EncCmeSearchCtrl, HLimit, 6, 3) + FldFunc(EncCe_EncCmeSearchCtrl, Top, 5, 1) + FldFunc(EncCe_EncCmeSearchCtrl, Left, 4, 1) + FldFunc(EncCe_EncCmeSearchCtrl, WaitLoad, 3, 1) + FldFunc(EncCe_EncCmeSearchCtrl, EI, 2, 1) + FldFunc(EncCe_EncCmeSearchCtrl, Busy, 1, 1) + FldFunc(EncCe_EncCmeSearchCtrl, Go, 0, 1) +RegFunc(EncCme, 0x400300, EncCmeVersion, 0x3c, EncCe_EncCmeVersion, 0x40033c) +RegFunc(EncCme, 0x400300, EncCmeResults0, 0x40, EncCe_EncCmeResults0, 0x400340) + FldFunc(EncCe_EncCmeResults0, Invalid, 31, 1) + FldFunc(EncCe_EncCmeResults0, SAD, 16, 15) + FldFunc(EncCe_EncCmeResults0, Voff, 8, 8) + FldFunc(EncCe_EncCmeResults0, Hoff, 0, 8) +RegFunc(EncCme, 0x400300, EncCmeResults1, 0x44, EncCe_EncCmeResults1, 0x400344) +RegFunc(EncCme, 0x400300, EncCmeResults2, 0x48, EncCe_EncCmeResults2, 0x400348) +RegFunc(EncCme, 0x400300, EncCmeResults3, 0x4C, EncCe_EncCmeResults3, 0x40034C) +RegFunc(EncCme, 0x400300, EncCmeResults4, 0x50, EncCe_EncCmeResults4, 0x400350) +RegFunc(EncCme, 0x400300, EncCmeResults5, 0x54, EncCe_EncCmeResults5, 0x400354) +RegFunc(EncCme, 0x400300, EncCmeResults6, 0x58, EncCe_EncCmeResults6, 0x400358) +RegFunc(EncCme, 0x400300, EncCmeResults7, 0x5C, EncCe_EncCmeResults7, 0x40035C) +RegFunc(EncCme, 0x400300, EncCmeResults8, 0x60, EncCe_EncCmeResults8, 0x400360) +RegFunc(EncCme, 0x400300, EncCmeResults9, 0x64, EncCe_EncCmeResults9, 0x400364) +RegFunc(EncCme, 0x400300, EncCmeResults10, 0x68, EncCe_EncCmeResults10, 0x400368) +RegFunc(EncCme, 0x400300, EncCmeResults11, 0x6C, EncCe_EncCmeResults11, 0x40036C) +RegFunc(EncCme, 0x400300, EncCmeResults12, 0x70, EncCe_EncCmeResults12, 0x400370) +RegFunc(EncCme, 0x400300, EncCmeResults13, 0x74, EncCe_EncCmeResults13, 0x400374) +RegFunc(EncCme, 0x400300, EncCmeResults14, 0x78, EncCe_EncCmeResults14, 0x400378) +RegFunc(EncCme, 0x400300, EncCmeResults15, 0x7C, EncCe_EncCmeResults15, 0x40037C) +RegFunc(EncCme, 0x400300, EncCmeYXResults0, 0xC0, EncCe_EncCmeYXResults0, 0x4003C0) +RegFunc(EncCme, 0x400300, EncCmeYXResults1, 0xC4, EncCe_EncCmeYXResults1, 0x4003C4) +RegFunc(EncCme, 0x400300, EncCmeYXResults2, 0xC8, EncCe_EncCmeYXResults2, 0x4003C8) +RegFunc(EncCme, 0x400300, EncCmeYXResults3, 0xCC, EncCe_EncCmeYXResults3, 0x4003CC) +RegFunc(EncCme, 0x400300, EncCmeYXResults4, 0xD0, EncCe_EncCmeYXResults4, 0x4003D0) +RegFunc(EncCme, 0x400300, EncCmeYXResults5, 0xD4, EncCe_EncCmeYXResults5, 0x4003D4) +RegFunc(EncCme, 0x400300, EncCmeYXResults6, 0xD8, EncCe_EncCmeYXResults6, 0x4003D8) +RegFunc(EncCme, 0x400300, EncCmeYXResults7, 0xDC, EncCe_EncCmeYXResults7, 0x4003DC) +RegFunc(EncCme, 0x400300, EncCmeYXResults8, 0xE0, EncCe_EncCmeYXResults8, 0x4003E0) +RegFunc(EncCme, 0x400300, EncCmeYXResults9, 0xE4, EncCe_EncCmeYXResults9, 0x4003E4) +RegFunc(EncCme, 0x400300, EncCmeYXResults10, 0xE8, EncCe_EncCmeYXResults10, 0x4003E8) +RegFunc(EncCme, 0x400300, EncCmeYXResults11, 0xEC, EncCe_EncCmeYXResults11, 0x4003EC) +RegFunc(EncCme, 0x400300, EncCmeYXResults12, 0xF0, EncCe_EncCmeYXResults12, 0x4003F0) +RegFunc(EncCme, 0x400300, EncCmeYXResults13, 0xF4, EncCe_EncCmeYXResults13, 0x4003F4) +RegFunc(EncCme, 0x400300, EncCmeYXResults14, 0xF8, EncCe_EncCmeYXResults14, 0x4003F8) +RegFunc(EncCme, 0x400300, EncCmeYXResults15, 0xFC, EncCe_EncCmeYXResults15, 0x4003FC) +#endif +#if 0 // Old SV CME no longer in use +RegFunc(EncCme, 0x400300, EncCmeCtl, 0x0, EncCe_EncCmeCtl, 0x400300) + FldFunc(EncCe_EncCmeCtl, DmaIntEn, 23, 1) + FldFunc(EncCe_EncCmeCtl, SadIntEn, 22, 1) + FldFunc(EncCe_EncCmeCtl, Lambda, 10, 12) + FldFunc(EncCe_EncCmeCtl, FieldNum, 9, 1) + FldFunc(EncCe_EncCmeCtl, FieldMode, 8, 1) + FldFunc(EncCe_EncCmeCtl, Zigzagstate, 4, 4) + FldFunc(EncCe_EncCmeCtl, Offscreendis, 3, 1) + FldFunc(EncCe_EncCmeCtl, Vertdp, 2, 1) + FldFunc(EncCe_EncCmeCtl, Loadref, 1, 1) + FldFunc(EncCe_EncCmeCtl, Enable, 0, 1) +RegFunc(EncCme, 0x400300, EncCmeCur, 0x4, EncCe_EncCmeCur, 0x400304) + FldFunc(EncCe_EncCmeCur, Curnum, 24, 8) + FldFunc(EncCe_EncCmeCur, Cury, 12, 12) + FldFunc(EncCe_EncCmeCur, Curx, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeRef0, 0x8, EncCe_EncCmeRef0, 0x400308) + FldFunc(EncCe_EncCmeRef0, Refnum, 24, 8) + FldFunc(EncCe_EncCmeRef0, Refy, 12, 12) + FldFunc(EncCe_EncCmeRef0, Refx, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeRef1, 0xC, EncCe_EncCmeRef1, 0x40030c) + FldFunc(EncCe_EncCmeRef1, FieldNum, 25, 1) + FldFunc(EncCe_EncCmeRef1, FieldMode, 24, 1) + FldFunc(EncCe_EncCmeRef1, Ysize, 12, 12) + FldFunc(EncCe_EncCmeRef1, Xsize, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeSramwraddr, 0x10, EncCe_EncCmeSramwraddr, 0x400310) + FldFunc(EncCe_EncCmeSramwraddr, Uvwrptr, 16, 16) + FldFunc(EncCe_EncCmeSramwraddr, Ywrptr, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeSramrdaddr, 0x14, EncCe_EncCmeSramrdaddr, 0x400314) + FldFunc(EncCe_EncCmeSramrdaddr, Uvrdptr, 16, 16) + FldFunc(EncCe_EncCmeSramrdaddr, Yrdptr, 0, 16) +RegFunc(EncCme, 0x400300, EncCmePitch, 0x18, EncCe_EncCmePitch, 0x400318) + FldFunc(EncCe_EncCmePitch, Pitch, 0, 11) +RegFunc(EncCme, 0x400300, EncCmeDeltax, 0x1C, EncCe_EncCmeDeltax, 0x40031c) + FldFunc(EncCe_EncCmeDeltax, Posx, 16, 16) + FldFunc(EncCe_EncCmeDeltax, Negx, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeDeltay, 0x20, EncCe_EncCmeDeltay, 0x400320) + FldFunc(EncCe_EncCmeDeltay, Posy, 16, 16) + FldFunc(EncCe_EncCmeDeltay, Negy, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeCount, 0x24, EncCe_EncCmeCount, 0x400324) + FldFunc(EncCe_EncCmeCount, Mbcount, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeStatus, 0x28, EncCe_EncCmeStatus, 0x400328) + FldFunc(EncCe_EncCmeStatus, DmaDone, 1, 1) + FldFunc(EncCe_EncCmeStatus, Done, 0, 1) +RegFunc(EncCme, 0x400300, EncCmeImgsize, 0x2C, EncCe_EncCmeImgsize, 0x40032c) + FldFunc(EncCe_EncCmeImgsize, Ysize, 12, 12) + FldFunc(EncCe_EncCmeImgsize, Xsize, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeVecfrSad, 0x30, EncCe_EncCmeVecfrSad, 0x400330) + FldFunc(EncCe_EncCmeVecfrSad, Sad, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeVecfrLoc, 0x34, EncCe_EncCmeVecfrLoc, 0x400334) + FldFunc(EncCe_EncCmeVecfrLoc, X, 12, 12) + FldFunc(EncCe_EncCmeVecfrLoc, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeVecttSad, 0x38, EncCe_EncCmeVecttSad, 0x400338) + FldFunc(EncCe_EncCmeVecttSad, Sad, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeVecttLoc, 0x3C, EncCe_EncCmeVecttLoc, 0x40033c) + FldFunc(EncCe_EncCmeVecttLoc, X, 12, 12) + FldFunc(EncCe_EncCmeVecttLoc, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeVecbbSad, 0x40, EncCe_EncCmeVecbbSad, 0x400340) + FldFunc(EncCe_EncCmeVecbbSad, Sad, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeVecbbLoc, 0x44, EncCe_EncCmeVecbbLoc, 0x400344) + FldFunc(EncCe_EncCmeVecbbLoc, X, 12, 12) + FldFunc(EncCe_EncCmeVecbbLoc, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeVectbSad, 0x48, EncCe_EncCmeVectbSad, 0x400348) + FldFunc(EncCe_EncCmeVectbSad, Sad, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeVectbLoc, 0x4C, EncCe_EncCmeVectbLoc, 0x40034c) + FldFunc(EncCe_EncCmeVectbLoc, X, 12, 12) + FldFunc(EncCe_EncCmeVectbLoc, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmeVecbtSad, 0x50, EncCe_EncCmeVecbtSad, 0x400350) + FldFunc(EncCe_EncCmeVecbtSad, Sad, 0, 16) +RegFunc(EncCme, 0x400300, EncCmeVecbtLoc, 0x54, EncCe_EncCmeVecbtLoc, 0x400354) + FldFunc(EncCe_EncCmeVecbtLoc, X, 12, 12) + FldFunc(EncCe_EncCmeVecbtLoc, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmePrvecfr, 0x58, EncCe_EncCmePrvecfr, 0x400358) + FldFunc(EncCe_EncCmePrvecfr, X, 12, 12) + FldFunc(EncCe_EncCmePrvecfr, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmePrvectt, 0x5C, EncCe_EncCmePrvectt, 0x40035c) + FldFunc(EncCe_EncCmePrvectt, X, 12, 12) + FldFunc(EncCe_EncCmePrvectt, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmePrvecbb, 0x60, EncCe_EncCmePrvecbb, 0x400360) + FldFunc(EncCe_EncCmePrvecbb, X, 12, 12) + FldFunc(EncCe_EncCmePrvecbb, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmePrvectb, 0x64, EncCe_EncCmePrvectb, 0x400364) + FldFunc(EncCe_EncCmePrvectb, X, 12, 12) + FldFunc(EncCe_EncCmePrvectb, Y, 0, 12) +RegFunc(EncCme, 0x400300, EncCmePrvecbt, 0x68, EncCe_EncCmePrvecbt, 0x400368) + FldFunc(EncCe_EncCmePrvecbt, X, 12, 12) + FldFunc(EncCe_EncCmePrvecbt, Y, 0, 12) +#endif + +RegAreaFunc(EncPreCpuregsBase, 0x400F00, 0x400F7F) +RegFunc(EncPreCpuregs, 0x400F00, RegHst2cpuMbx, 0x0, EncPCs_RegHst2cpuMbx, 0x400f00) + FldFunc(EncPCs_RegHst2cpuMbx, Value, 0, 32) +RegFunc(EncPreCpuregs, 0x400F00, RegCpu2hstMbx, 0x4, EncPCs_RegCpu2hstMbx, 0x400f04) + FldFunc(EncPCs_RegCpu2hstMbx, Value, 0, 32) +RegFunc(EncPreCpuregs, 0x400F00, RegMbxStat, 0x8, EncPCs_RegMbxStat, 0x400f08) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIntBase, 0xC, EncPCs_RegCpuIntBase, 0x400f0c) + FldFunc(EncPCs_RegCpuIntBase, Addr, 8, 24) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIntEna, 0x10, EncPCs_RegCpuIntEna, 0x400f10) + FldFunc(EncPCs_RegCpuIntEna, Mbx, 31, 1) + FldFunc(EncPCs_RegCpuIntEna, Com7, 23, 1) + FldFunc(EncPCs_RegCpuIntEna, Com6, 22, 1) + FldFunc(EncPCs_RegCpuIntEna, Com5, 21, 1) + FldFunc(EncPCs_RegCpuIntEna, Com4, 20, 1) + FldFunc(EncPCs_RegCpuIntEna, Com3, 19, 1) + FldFunc(EncPCs_RegCpuIntEna, Com2, 18, 1) + FldFunc(EncPCs_RegCpuIntEna, Com1, 17, 1) + FldFunc(EncPCs_RegCpuIntEna, Com0, 16, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw7, 15, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw6, 14, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw5, 13, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw4, 12, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw3, 11, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw2, 10, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw1, 9, 1) + FldFunc(EncPCs_RegCpuIntEna, Hw0, 8, 1) + FldFunc(EncPCs_RegCpuIntEna, Db7, 7, 1) + FldFunc(EncPCs_RegCpuIntEna, Db6, 6, 1) + FldFunc(EncPCs_RegCpuIntEna, Db5, 5, 1) + FldFunc(EncPCs_RegCpuIntEna, Db4, 4, 1) + FldFunc(EncPCs_RegCpuIntEna, Db3, 3, 1) + FldFunc(EncPCs_RegCpuIntEna, Db2, 2, 1) + FldFunc(EncPCs_RegCpuIntEna, Db1, 1, 1) + FldFunc(EncPCs_RegCpuIntEna, Db0, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, StreamCpuIntEna, 0x10, EncPCs_StreamCpuIntEna, 0x400f10) + FldFunc(EncPCs_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(EncPCs_StreamCpuIntEna, Dec, 18, 1) + FldFunc(EncPCs_StreamCpuIntEna, Aud, 17, 1) + FldFunc(EncPCs_StreamCpuIntEna, M2m, 15, 1) + FldFunc(EncPCs_StreamCpuIntEna, Pci, 14, 1) + FldFunc(EncPCs_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(EncPCs_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(EncPCs_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(EncPCs_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(EncPCs_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(EncPCs_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(EncPCs_StreamCpuIntEna, Rb, 1, 1) + FldFunc(EncPCs_StreamCpuIntEna, Sd, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, Dec0CpuIntEna, 0x10, EncPCs_Dec0CpuIntEna, 0x400f10) + FldFunc(EncPCs_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(EncPCs_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(EncPCs_Dec0CpuIntEna, Si, 8, 1) + FldFunc(EncPCs_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(EncPCs_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, Dec1CpuIntEna, 0x10, EncPCs_Dec1CpuIntEna, 0x400f10) + FldFunc(EncPCs_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(EncPCs_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(EncPCs_Dec1CpuIntEna, Si, 8, 1) + FldFunc(EncPCs_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(EncPCs_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIntStat, 0x14, EncPCs_RegCpuIntStat, 0x400f14) + FldFunc(EncPCs_RegCpuIntStat, Mbx, 31, 1) + FldFunc(EncPCs_RegCpuIntStat, Com7, 23, 1) + FldFunc(EncPCs_RegCpuIntStat, Com6, 22, 1) + FldFunc(EncPCs_RegCpuIntStat, Com5, 21, 1) + FldFunc(EncPCs_RegCpuIntStat, Com4, 20, 1) + FldFunc(EncPCs_RegCpuIntStat, Com3, 19, 1) + FldFunc(EncPCs_RegCpuIntStat, Com2, 18, 1) + FldFunc(EncPCs_RegCpuIntStat, Com1, 17, 1) + FldFunc(EncPCs_RegCpuIntStat, Com0, 16, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw7, 15, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw6, 14, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw5, 13, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw4, 12, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw3, 11, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw2, 10, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw1, 9, 1) + FldFunc(EncPCs_RegCpuIntStat, Hw0, 8, 1) + FldFunc(EncPCs_RegCpuIntStat, Db7, 7, 1) + FldFunc(EncPCs_RegCpuIntStat, Db6, 6, 1) + FldFunc(EncPCs_RegCpuIntStat, Db5, 5, 1) + FldFunc(EncPCs_RegCpuIntStat, Db4, 4, 1) + FldFunc(EncPCs_RegCpuIntStat, Db3, 3, 1) + FldFunc(EncPCs_RegCpuIntStat, Db2, 2, 1) + FldFunc(EncPCs_RegCpuIntStat, Db1, 1, 1) + FldFunc(EncPCs_RegCpuIntStat, Db0, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, StreamCpuIntStat, 0x14, EncPCs_StreamCpuIntStat, 0x400f14) + FldFunc(EncPCs_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(EncPCs_StreamCpuIntStat, Dec, 18, 1) + FldFunc(EncPCs_StreamCpuIntStat, Aud, 17, 1) + FldFunc(EncPCs_StreamCpuIntStat, M2m, 15, 1) + FldFunc(EncPCs_StreamCpuIntStat, Pci, 14, 1) + FldFunc(EncPCs_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(EncPCs_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(EncPCs_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(EncPCs_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(EncPCs_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(EncPCs_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(EncPCs_StreamCpuIntStat, Rb, 1, 1) + FldFunc(EncPCs_StreamCpuIntStat, Sd, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, Dec0CpuIntStat, 0x14, EncPCs_Dec0CpuIntStat, 0x400f14) + FldFunc(EncPCs_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(EncPCs_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(EncPCs_Dec0CpuIntStat, Si, 8, 1) + FldFunc(EncPCs_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(EncPCs_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, Dec1CpuIntStat, 0x14, EncPCs_Dec1CpuIntStat, 0x400f14) + FldFunc(EncPCs_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(EncPCs_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(EncPCs_Dec1CpuIntStat, Si, 8, 1) + FldFunc(EncPCs_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(EncPCs_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, RegHst2cpuStat, 0x18, EncPCs_RegHst2cpuStat, 0x400f18) + FldFunc(EncPCs_RegHst2cpuStat, Value, 0, 32) +RegFunc(EncPreCpuregs, 0x400F00, RegCpu2hstStat, 0x1C, EncPCs_RegCpu2hstStat, 0x400f1c) + FldFunc(EncPCs_RegCpu2hstStat, Value, 0, 32) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIntgenSet, 0x20, EncPCs_RegCpuIntgenSet, 0x400f20) + FldFunc(EncPCs_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(EncPCs_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIntgenClr, 0x24, EncPCs_RegCpuIntgenClr, 0x400f24) + FldFunc(EncPCs_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(EncPCs_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIcacheMiss, 0x28, EncPCs_RegCpuIcacheMiss, 0x400f28) + FldFunc(EncPCs_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(EncPreCpuregs, 0x400F00, RegCpuIntgenMask, 0x2C, EncPCs_RegCpuIntgenMask, 0x400f2c) + FldFunc(EncPCs_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(EncPCs_RegCpuIntgenMask, Int0, 0, 1) + +RegAreaFunc(EncPreCpudmaBase, 0x401800, 0x4018FF) +RegFunc(EncPreCpudma, 0x401800, RegDma0SdAddr, 0x0, EncPCa_RegDma0SdAddr, 0x401800) + FldFunc(EncPCa_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(EncPreCpudma, 0x401800, RegDma0LclAddr, 0x4, EncPCa_RegDma0LclAddr, 0x401804) + FldFunc(EncPCa_RegDma0LclAddr, Addr, 2, 7) +RegFunc(EncPreCpudma, 0x401800, RegDma0Len, 0x8, EncPCa_RegDma0Len, 0x401808) + FldFunc(EncPCa_RegDma0Len, Length, 2, 8) +RegFunc(EncPreCpudma, 0x401800, RegDma1SdAddr, 0x10, EncPCa_RegDma1SdAddr, 0x401810) + FldFunc(EncPCa_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(EncPreCpudma, 0x401800, RegDma1LclAddr, 0x14, EncPCa_RegDma1LclAddr, 0x401814) + FldFunc(EncPCa_RegDma1LclAddr, Addr, 2, 7) +RegFunc(EncPreCpudma, 0x401800, RegDma1Len, 0x18, EncPCa_RegDma1Len, 0x401818) + FldFunc(EncPCa_RegDma1Len, Length, 2, 8) +RegFunc(EncPreCpudma, 0x401800, RegDma2SdAddr, 0x20, EncPCa_RegDma2SdAddr, 0x401820) + FldFunc(EncPCa_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(EncPreCpudma, 0x401800, RegDma2LclAddr, 0x24, EncPCa_RegDma2LclAddr, 0x401824) + FldFunc(EncPCa_RegDma2LclAddr, Addr, 2, 7) +RegFunc(EncPreCpudma, 0x401800, RegDma2Len, 0x28, EncPCa_RegDma2Len, 0x401828) + FldFunc(EncPCa_RegDma2Len, Length, 2, 8) +RegFunc(EncPreCpudma, 0x401800, RegDma3SdAddr, 0x30, EncPCa_RegDma3SdAddr, 0x401830) + FldFunc(EncPCa_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(EncPreCpudma, 0x401800, RegDma3LclAddr, 0x34, EncPCa_RegDma3LclAddr, 0x401834) + FldFunc(EncPCa_RegDma3LclAddr, Addr, 2, 7) +RegFunc(EncPreCpudma, 0x401800, RegDma3Len, 0x38, EncPCa_RegDma3Len, 0x401838) + FldFunc(EncPCa_RegDma3Len, Length, 2, 8) +RegFunc(EncPreCpudma, 0x401800, RegDmaStatus, 0x40, EncPCa_RegDmaStatus, 0x401840) + FldFunc(EncPCa_RegDmaStatus, Act3, 3, 1) + FldFunc(EncPCa_RegDmaStatus, Act2, 2, 1) + FldFunc(EncPCa_RegDmaStatus, Act1, 1, 1) + FldFunc(EncPCa_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(EncPreDmamemBase, 0x401A00, 0x4021FF) +RegFunc(EncPreDmamem, 0x401A00, DmaMem, 0x0, EncPDm_DmaMem, 0x401a00) + FldFunc(EncPDm_DmaMem, Data, 0, 32) + +RegAreaFunc(EncDsBase, 0x40A000, 0x40A0FF) +RegFunc(EncDs, 0x40A000, EncDsCtl, 0x0, EncDs_EncDsCtl, 0x40a000) +#ifdef VCMODS_REGMAP +FldFunc(EncDs_EncDsCtl, Rsv12, 12, 20) +FldFunc(EncDs_EncDsCtl, FieldDP, 11, 1) +FldFunc(EncDs_EncDsCtl, Interleaved, 10, 1) +FldFunc(EncDs_EncDsCtl, DSVShift, 8, 2) +FldFunc(EncDs_EncDsCtl, DSHshift, 7, 1) +FldFunc(EncDs_EncDsCtl, DPVert, 6, 1) +FldFunc(EncDs_EncDsCtl, DPDis, 5, 1) +FldFunc(EncDs_EncDsCtl, RegInfo, 4, 1) +FldFunc(EncDs_EncDsCtl, PicDPIntEn, 3, 1) +FldFunc(EncDs_EncDsCtl, PicDSIntEn, 2, 1) +FldFunc(EncDs_EncDsCtl, PktIntEn, 1, 1) +FldFunc(EncDs_EncDsCtl, Reset, 0, 1) +#else + FldFunc(EncDs_EncDsCtl, DpFieldDp, 10, 1) + FldFunc(EncDs_EncDsCtl, DsInterleaved, 9, 1) + FldFunc(EncDs_EncDsCtl, DsVshift, 8, 1) + FldFunc(EncDs_EncDsCtl, DsHshift, 7, 1) + FldFunc(EncDs_EncDsCtl, DpVert, 6, 1) + FldFunc(EncDs_EncDsCtl, DpDis, 5, 1) + FldFunc(EncDs_EncDsCtl, RegEn, 4, 1) + FldFunc(EncDs_EncDsCtl, DpIntEn, 3, 1) + FldFunc(EncDs_EncDsCtl, DsIntEn, 2, 1) + FldFunc(EncDs_EncDsCtl, PktIntEn, 1, 1) + FldFunc(EncDs_EncDsCtl, Rst, 0, 1) +#endif +RegFunc(EncDs, 0x40A000, EncDsWidth, 0x4, EncDs_EncDsWidth, 0x40a004) +#ifdef VCMODS_REGMAP +FldFunc(EncDs_EncDsWidth, YSize, 16, 16) +FldFunc(EncDs_EncDsWidth, XSize, 0, 16) +#else + FldFunc(EncDs_EncDsWidth, YWidth, 16, 12) + FldFunc(EncDs_EncDsWidth, XWidth, 0, 12) +#endif +RegFunc(EncDs, 0x40A000, EncDsPktAddr, 0x8, EncDs_EncDsPktAddr, 0x40a008) + FldFunc(EncDs_EncDsPktAddr, PacketBufferAddress, 0, 32) +RegFunc(EncDs, 0x40A000, EncDsPicAddr, 0xC, EncDs_EncDsPicAddr, 0x40a00c) +#ifdef VCMODS_REGMAP +FldFunc(EncDs_EncDsPicAddr, Rsv24, 24, 8) +FldFunc(EncDs_EncDsPicAddr, DPNumB, 16, 8) +FldFunc(EncDs_EncDsPicAddr, DPNum, 8, 8) +FldFunc(EncDs_EncDsPicAddr, DSNum, 0, 8) +#else + FldFunc(EncDs_EncDsPicAddr, DpPicNumB, 16, 8) + FldFunc(EncDs_EncDsPicAddr, DpPicNum, 8, 8) + FldFunc(EncDs_EncDsPicAddr, DsPicNum, 0, 8) +#endif +RegFunc(EncDs, 0x40A000, EncDsStatus, 0x10, EncDs_EncDsStatus, 0x40a010) +#ifdef VCMODS_REGMAP +FldFunc(EncDs_EncDsStatus, Rsv26, 26, 6) +FldFunc(EncDs_EncDsStatus, PicErr, 25, 1) +FldFunc(EncDs_EncDsStatus, PktErr, 24, 1) +FldFunc(EncDs_EncDsStatus, PicDPCnt, 16, 8) +FldFunc(EncDs_EncDsStatus, PicDSCnt, 8, 8) +FldFunc(EncDs_EncDsStatus, PktCnt, 0, 8) +#else + FldFunc(EncDs_EncDsStatus, PicErr, 25, 1) + FldFunc(EncDs_EncDsStatus, PktErr, 24, 1) + FldFunc(EncDs_EncDsStatus, DpCnt, 16, 3) + FldFunc(EncDs_EncDsStatus, DsCnt, 8, 3) + FldFunc(EncDs_EncDsStatus, PktCnt, 0, 3) +#endif +RegFunc(EncDs, 0x40A000, EncDsConfig, 0x14, EncDs_EncDsConfig, 0x40a014) +#ifdef VCMODS_REGMAP +FldFunc(EncDs_EncDsConfig, Rsv3, 3, 29) +FldFunc(EncDs_EncDsConfig, 422Mode, 2, 1) +FldFunc(EncDs_EncDsConfig, FldMode, 1, 1) +FldFunc(EncDs_EncDsConfig, FldID, 0, 1) +#else + FldFunc(EncDs_EncDsConfig, 422Md, 2, 1) + FldFunc(EncDs_EncDsConfig, FldMd, 1, 1) + FldFunc(EncDs_EncDsConfig, FldId, 0, 1) +#endif +RegFunc(EncDs, 0x40A000, EncDsIntStat, 0x18, EncDs_EncDsIntStat, 0x40a018) + FldFunc(EncDs_EncDsIntStat, DpEop, 1, 1) + FldFunc(EncDs_EncDsIntStat, DsEop, 0, 1) +RegFunc(EncDs, 0x40A000, EncDsStat, 0x1C, EncDs_EncDsStat, 0x40a01c) + FldFunc(EncDs_EncDsStat, Done, 8, 1) + FldFunc(EncDs_EncDsStat, AveDiff, 0, 8) +RegFunc(EncDs, 0x40A000, EncDsStatCtl, 0x20, EncDs_EncDsStatCtl, 0x40a020) + FldFunc(EncDs_EncDsStatCtl, Pict, 24, 8) + FldFunc(EncDs_EncDsStatCtl, Fnum, 23, 1) + FldFunc(EncDs_EncDsStatCtl, Field, 22, 1) + FldFunc(EncDs_EncDsStatCtl, Y, 11, 11) + FldFunc(EncDs_EncDsStatCtl, X, 0, 11) +RegFunc(EncDs, 0x40A000, EncDsAbsdiffSum, 0x24, EncDs_EncDsAbsdiffSum, 0x40a024) + FldFunc(EncDs_EncDsAbsdiffSum, Done, 31, 1) + FldFunc(EncDs_EncDsAbsdiffSum, Val, 0, 30) + +RegAreaFunc(EncPreIndSdramRegsBase, 0x441000, 0x44107F) +RegFunc(EncPreIndSdramRegs, 0x441000, RegSdramInc, 0x0, EncPISRs_RegSdramInc, 0x441000) + FldFunc(EncPISRs_RegSdramInc, Inc, 0, 1) +RegFunc(EncPreIndSdramRegs, 0x441000, RegSdramAddr, 0x4, EncPISRs_RegSdramAddr, 0x441004) + FldFunc(EncPISRs_RegSdramAddr, Addr, 0, 32) +RegFunc(EncPreIndSdramRegs, 0x441000, RegSdramData, 0x8, EncPISRs_RegSdramData, 0x441008) + FldFunc(EncPISRs_RegSdramData, Data, 0, 32) +RegFunc(EncPreIndSdramRegs, 0x441000, RegCpuDbg, 0x10, EncPISRs_RegCpuDbg, 0x441010) + FldFunc(EncPISRs_RegCpuDbg, Hst, 0, 1) + +RegAreaFunc(EncPreCpucoreBase, 0x444000, 0x444FFF) +RegFunc(EncPreCpucore, 0x444000, CpucoreReg, 0x0, EncPCe_CpucoreReg, 0x444000) + FldFunc(EncPCe_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(EncPreCpuauxBase, 0x445000, 0x445FFF) +RegFunc(EncPreCpuaux, 0x445000, CpuauxReg, 0x0, EncPCx_CpuauxReg, 0x445000) + FldFunc(EncPCx_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(EncPreCpuimemBase, 0x446000, 0x447FFF) +RegFunc(EncPreCpuimem, 0x446000, CpuimemReg, 0x0, EncPCm_CpuimemReg, 0x446000) + FldFunc(EncPCm_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(EncPreCpudmemBase, 0x448000, 0x44FFFF) +RegFunc(EncPreCpudmem, 0x448000, CpudmemReg, 0x0, EncPCm_CpudmemReg, 0x448000) + FldFunc(EncPCm_CpudmemReg, Addr, 0, 32) + +#endif + + +//****************************************************************************** +// +// Encoder Mid Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_ENCODER_MID + +RegAreaFunc(EncMidRbnodeRegsBase, 0x500000, 0x50007F) +RegFunc(EncMidRbnodeRegs, 0x500000, RbConfig , 0x0, EncMRRs_RbConfig , 0x500000) + FldFunc(EncMRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(EncMRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(EncMidRbnodeRegs, 0x500000, RbStickyError, 0x4, EncMRRs_RbStickyError, 0x500004) + FldFunc(EncMRRs_RbStickyError, Node, 1, 1) + FldFunc(EncMRRs_RbStickyError, Tgt, 0, 1) +RegFunc(EncMidRbnodeRegs, 0x500000, RbCurrentError, 0x8, EncMRRs_RbCurrentError, 0x500008) + FldFunc(EncMRRs_RbCurrentError, Node, 1, 1) + FldFunc(EncMRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(EncMidRbnodeRegs, 0x500000, RbReadData, 0xC, EncMRRs_RbReadData, 0x50000c) + FldFunc(EncMRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(EncMidRingbusDebugRegsBase, 0x500080, 0x5000FF) +RegFunc(EncMidRingbusDebugRegs, 0x500080, RbDebugConfig, 0x0, EncMRDRs_RbDebugConfig, 0x500080) + FldFunc(EncMRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(EncMRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(EncMidRingbusDebugRegs, 0x500080, RbDebugReg0Addr, 0x4, EncMRDRs_RbDebugReg0Addr, 0x500084) + FldFunc(EncMRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(EncMidRingbusDebugRegs, 0x500080, RbDebugReg1Addr, 0x8, EncMRDRs_RbDebugReg1Addr, 0x500088) + FldFunc(EncMRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(EncMidRingbusDebugRegs, 0x500080, RbDebugReg2Addr, 0xC, EncMRDRs_RbDebugReg2Addr, 0x50008c) + FldFunc(EncMRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(EncMidRingbusDebugRegs, 0x500080, RbDebugReg3Addr, 0x10, EncMRDRs_RbDebugReg3Addr, 0x500090) + FldFunc(EncMRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(EncMidRingbusDebugRegs, 0x500080, RbDebugOutputReg, 0x14, EncMRDRs_RbDebugOutputReg, 0x500094) + FldFunc(EncMRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(EncMRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(EncWprdBase, 0x500340, 0x50035F) +RegFunc(EncWprd, 0x500340, RegWprdCtl, 0x0, EncWd_RegWprdCtl, 0x500340) + FldFunc(EncWd_RegWprdCtl, Chromadenom, 12, 3) + FldFunc(EncWd_RegWprdCtl, Lumdenom, 8, 3) + FldFunc(EncWd_RegWprdCtl, Predtype, 0, 2) + +RegAreaFunc(EncMidCpudmaBase, 0x501800, 0x5018FF) +RegFunc(EncMidCpudma, 0x501800, RegDma0SdAddr, 0x0, EncMCa_RegDma0SdAddr, 0x501800) + FldFunc(EncMCa_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(EncMidCpudma, 0x501800, RegDma0LclAddr, 0x4, EncMCa_RegDma0LclAddr, 0x501804) + FldFunc(EncMCa_RegDma0LclAddr, Addr, 2, 7) +RegFunc(EncMidCpudma, 0x501800, RegDma0Len, 0x8, EncMCa_RegDma0Len, 0x501808) + FldFunc(EncMCa_RegDma0Len, Length, 2, 8) +RegFunc(EncMidCpudma, 0x501800, RegDma1SdAddr, 0x10, EncMCa_RegDma1SdAddr, 0x501810) + FldFunc(EncMCa_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(EncMidCpudma, 0x501800, RegDma1LclAddr, 0x14, EncMCa_RegDma1LclAddr, 0x501814) + FldFunc(EncMCa_RegDma1LclAddr, Addr, 2, 7) +RegFunc(EncMidCpudma, 0x501800, RegDma1Len, 0x18, EncMCa_RegDma1Len, 0x501818) + FldFunc(EncMCa_RegDma1Len, Length, 2, 8) +RegFunc(EncMidCpudma, 0x501800, RegDma2SdAddr, 0x20, EncMCa_RegDma2SdAddr, 0x501820) + FldFunc(EncMCa_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(EncMidCpudma, 0x501800, RegDma2LclAddr, 0x24, EncMCa_RegDma2LclAddr, 0x501824) + FldFunc(EncMCa_RegDma2LclAddr, Addr, 2, 7) +RegFunc(EncMidCpudma, 0x501800, RegDma2Len, 0x28, EncMCa_RegDma2Len, 0x501828) + FldFunc(EncMCa_RegDma2Len, Length, 2, 8) +RegFunc(EncMidCpudma, 0x501800, RegDma3SdAddr, 0x30, EncMCa_RegDma3SdAddr, 0x501830) + FldFunc(EncMCa_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(EncMidCpudma, 0x501800, RegDma3LclAddr, 0x34, EncMCa_RegDma3LclAddr, 0x501834) + FldFunc(EncMCa_RegDma3LclAddr, Addr, 2, 7) +RegFunc(EncMidCpudma, 0x501800, RegDma3Len, 0x38, EncMCa_RegDma3Len, 0x501838) + FldFunc(EncMCa_RegDma3Len, Length, 2, 8) +RegFunc(EncMidCpudma, 0x501800, RegDmaStatus, 0x40, EncMCa_RegDmaStatus, 0x501840) + FldFunc(EncMCa_RegDmaStatus, Act3, 3, 1) + FldFunc(EncMCa_RegDmaStatus, Act2, 2, 1) + FldFunc(EncMCa_RegDmaStatus, Act1, 1, 1) + FldFunc(EncMCa_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(EncMidDmaMemBase, 0x501A00, 0x5021FF) +RegFunc(EncMidDmaMem, 0x501A00, DmaMem, 0x0, EncMDMm_DmaMem, 0x501a00) + FldFunc(EncMDMm_DmaMem, Data, 0, 32) + +RegAreaFunc(EncSpBase, 0x504000, 0x504FFF) +RegFunc(EncSp, 0x504000, EncSpStart, 0x0, EncSp_EncSpStart, 0x504000) +#ifdef VCMODS_REGMAP +// +// WARNING: This register has different layouts for read and writing. +// + +// Read +FldFunc(EncSp_EncSpStart, Rsv6, 6, 26) +FldFunc(EncSp_EncSpStart, Done8x8, 5, 1) // read only +FldFunc(EncSp_EncSpStart, Idle8x8, 4, 1) // read only +FldFunc(EncSp_EncSpStart, Done16x16, 3, 1) // read only +FldFunc(EncSp_EncSpStart, Done4x4, 2, 1) // read only +FldFunc(EncSp_EncSpStart, Idle16x16, 1, 1) // read only +FldFunc(EncSp_EncSpStart, Idle4x4, 0, 1) // read only + +// Write +FldFunc(EncSp_EncSpStart, Rsv3, 3, 29) +FldFunc(EncSp_EncSpStart, Start8x8, 2, 1) // write only +FldFunc(EncSp_EncSpStart, Start16x16, 1, 1) // write only +FldFunc(EncSp_EncSpStart, Start4x4, 0, 1) // write only +FldFunc(EncSp_EncSpStart, Start, 0, 3) // aggregated field +#else + FldFunc(EncSp_EncSpStart, Start, 0, 2) +#endif +RegFunc(EncSp, 0x504000, EncSpMbaddr, 0x4, EncSp_EncSpMbaddr, 0x504004) +#ifdef VCMODS_REGMAP +FldFunc(EncSp_EncSpMbaddr, Rsv18, 18, 15) +FldFunc(EncSp_EncSpMbaddr, LeftIsIntra16x16, 17, 1) +FldFunc(EncSp_EncSpMbaddr, TopIsIntra16x16, 16, 1) +FldFunc(EncSp_EncSpMbaddr, Rsv15, 15, 1) +FldFunc(EncSp_EncSpMbaddr, XPos, 8, 7) +FldFunc(EncSp_EncSpMbaddr, SadCosting, 7, 1) +FldFunc(EncSp_EncSpMbaddr, FollowChroma, 6, 1) +FldFunc(EncSp_EncSpMbaddr, LeftIsInter, 5, 1) +FldFunc(EncSp_EncSpMbaddr, TopIsInter, 4, 1) +FldFunc(EncSp_EncSpMbaddr, TLAvail, 3, 1) +FldFunc(EncSp_EncSpMbaddr, LeftAvail, 2, 1) +FldFunc(EncSp_EncSpMbaddr, TopAvail, 1, 1) +FldFunc(EncSp_EncSpMbaddr, TRAvail, 0, 1) +FldFunc(EncSp_EncSpMbaddr, Avail, 0, 4) // aggregated field +#else + FldFunc(EncSp_EncSpMbaddr, MbXaddr, 8, 7) + FldFunc(EncSp_EncSpMbaddr, LeftIsInter, 5, 1) + FldFunc(EncSp_EncSpMbaddr, TopIsInter, 4, 1) + FldFunc(EncSp_EncSpMbaddr, TopLeftValid, 3, 1) + FldFunc(EncSp_EncSpMbaddr, LeftValid, 2, 1) + FldFunc(EncSp_EncSpMbaddr, TopValid, 1, 1) + FldFunc(EncSp_EncSpMbaddr, RightValid, 0, 1) +#endif +RegFunc(EncSp, 0x504000, EncSpMode4x4l, 0x8, EncSp_EncSpMode4x4l, 0x504008) + FldFunc(EncSp_EncSpMode4x4l, Mode4x4l, 0, 32) +RegFunc(EncSp, 0x504000, EncSpMode4x4h, 0xC, EncSp_EncSpMode4x4h, 0x50400c) + FldFunc(EncSp_EncSpMode4x4h, Mode4x4h, 0, 32) +RegFunc(EncSp, 0x504000, EncSpMode16x16, 0x10, EncSp_EncSpMode16x16, 0x504010) + FldFunc(EncSp_EncSpMode16x16, Mode16x16, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumatl, 0x14, EncSp_EncSpLumatl, 0x504014) + FldFunc(EncSp_EncSpLumatl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumatopl, 0x18, EncSp_EncSpLumatopl, 0x504018) + FldFunc(EncSp_EncSpLumatopl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumatoplm, 0x1C, EncSp_EncSpLumatoplm, 0x50401c) + FldFunc(EncSp_EncSpLumatoplm, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumatopmh, 0x20, EncSp_EncSpLumatopmh, 0x504020) + FldFunc(EncSp_EncSpLumatopmh, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumatoph, 0x24, EncSp_EncSpLumatoph, 0x504024) + FldFunc(EncSp_EncSpLumatoph, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumaleftl, 0x28, EncSp_EncSpLumaleftl, 0x504028) + FldFunc(EncSp_EncSpLumaleftl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumaleftlm, 0x2C, EncSp_EncSpLumaleftlm, 0x50402c) + FldFunc(EncSp_EncSpLumaleftlm, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumaleftmh, 0x30, EncSp_EncSpLumaleftmh, 0x504030) + FldFunc(EncSp_EncSpLumaleftmh, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumalefth, 0x34, EncSp_EncSpLumalefth, 0x504034) + FldFunc(EncSp_EncSpLumalefth, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLumaext, 0x38, EncSp_EncSpLumaext, 0x504038) + FldFunc(EncSp_EncSpLumaext, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCatl, 0x3C, EncSp_EncSpCatl, 0x50403c) + FldFunc(EncSp_EncSpCatl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCatopl, 0x40, EncSp_EncSpCatopl, 0x504040) + FldFunc(EncSp_EncSpCatopl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCatoph, 0x44, EncSp_EncSpCatoph, 0x504044) + FldFunc(EncSp_EncSpCatoph, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCaleftl, 0x48, EncSp_EncSpCaleftl, 0x504048) + FldFunc(EncSp_EncSpCaleftl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCalefth, 0x4C, EncSp_EncSpCalefth, 0x50404c) + FldFunc(EncSp_EncSpCalefth, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCbtl, 0x50, EncSp_EncSpCbtl, 0x504050) + FldFunc(EncSp_EncSpCbtl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCbtopl, 0x54, EncSp_EncSpCbtopl, 0x504054) + FldFunc(EncSp_EncSpCbtopl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCbtoph, 0x58, EncSp_EncSpCbtoph, 0x504058) + FldFunc(EncSp_EncSpCbtoph, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCbleftl, 0x5C, EncSp_EncSpCbleftl, 0x50405c) + FldFunc(EncSp_EncSpCbleftl, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCblefth, 0x60, EncSp_EncSpCblefth, 0x504060) + FldFunc(EncSp_EncSpCblefth, Edgeval, 0, 32) +RegFunc(EncSp, 0x504000, EncSpQp, 0x64, EncSp_EncSpQp, 0x504064) +#ifdef VCMODS_REGMAP +FldFunc(EncSp_EncSpQp, Qp8x8, 8, 6) +FldFunc(EncSp_EncSpQp, Rsv7, 7, 1) +FldFunc(EncSp_EncSpQp, IFrame, 6, 1) +FldFunc(EncSp_EncSpQp, QP, 0, 6) +#else + FldFunc(EncSp_EncSpQp, Qp8x8, 8, 6) + FldFunc(EncSp_EncSpQp, IfraMe, 6, 1) + FldFunc(EncSp_EncSpQp, Op, 0, 6) +#endif +RegFunc(EncSp, 0x504000, EncSpLambda, 0x68, EncSp_EncSpLambda, 0x504068) + FldFunc(EncSp_EncSpLambda, Lambda, 0, 16) +RegFunc(EncSp, 0x504000, EncSpCost4x4, 0x6c, EncSp_EncSpCost4x4, 0x50406c) + FldFunc(EncSp_EncSpCost4x4, Cost4x4, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCost16x16, 0x70, EncSp_EncSpCost16x16, 0x504070) + FldFunc(EncSp_EncSpCost16x16, Cost16x16, 0, 32) +RegFunc(EncSp, 0x504000, EncSpCost8x8, 0x74, EncSp_EncSpCost8x8, 0x504074) + FldFunc(EncSp_EncSpCost8x8, Cost8x8, 0, 32) +RegFunc(EncSp, 0x504000, EncSpTimer, 0x78, EncSp_EncSpTimer, 0x504078) + FldFunc(EncSp_EncSpTimer, Ovf, 16, 1) + FldFunc(EncSp_EncSpTimer, Timer, 0, 16) +#ifdef VCMODS_REGMAP +RegFunc(EncSp, 0x504000, EncSpTopmode, 0x7c, EncSp_EncSpTopmode, 0x50407c) +#endif +RegFunc(EncSp, 0x504000, EncSpBestmodeLuma4x4, 0x80, EncSp_EncSpBestmodeLuma4x4, 0x504080) + FldFunc(EncSp_EncSpBestmodeLuma4x4, Mode, 0, 4) +RegFunc(EncSp, 0x504000, EncSpBestmodeLuma16x16, 0xc0, EncSp_EncSpBestmodeLuma16x16, 0x5040c0) + FldFunc(EncSp_EncSpBestmodeLuma16x16, Mode, 0, 2) +RegFunc(EncSp, 0x504000, EncSpBestmodeChroma, 0xc4, EncSp_EncSpBestmodeChroma, 0x5040c4) + FldFunc(EncSp_EncSpBestmodeChroma, Mode, 0, 2) +RegFunc(EncSp, 0x504000, EncSpBestpredLuma4x4, 0x600, EncSp_EncSpBestpredLuma4x4, 0x504600) + FldFunc(EncSp_EncSpBestpredLuma4x4, Prediction, 0, 32) +RegFunc(EncSp, 0x504000, EncSpBestpredLuma16x16, 0x800, EncSp_EncSpBestpredLuma16x16, 0x504800) + FldFunc(EncSp_EncSpBestpredLuma16x16, Prediction, 0, 32) +RegFunc(EncSp, 0x504000, EncSpBestpredCa8x8, 0xa00, EncSp_EncSpBestpredCa8x8, 0x504a00) + FldFunc(EncSp_EncSpBestpredCa8x8, Prediction, 0, 32) +RegFunc(EncSp, 0x504000, EncSpBestpredCb8x8, 0xa80, EncSp_EncSpBestpredCb8x8, 0x504a80) + FldFunc(EncSp_EncSpBestpredCb8x8, Prediction, 0, 32) +RegFunc(EncSp, 0x504000, EncSpLambda8x8, 0xb00, EncSp_EncSpLambda8x8, 0x504b00) + FldFunc(EncSp_EncSpLambda8x8, Lambda8x8, 0, 16) +RegFunc(EncSp, 0x504000, EncSpCostluma8x8, 0xB04, EncSp_EncSpCostluma8x8, 0x504b04) + FldFunc(EncSp_EncSpCostluma8x8, Costluma8x8, 0, 32) +RegFunc(EncSp, 0x504000, EncSpBestmodeLuma8x8, 0xB08, EncSp_EncSpBestmodeLuma8x8, 0x504b08) + FldFunc(EncSp_EncSpBestmodeLuma8x8, Mode, 0, 16) +RegFunc(EncSp, 0x504000, EncSpBestpredLuma8x8, 0xB0C, EncSp_EncSpBestpredLuma8x8, 0x504b0c) + FldFunc(EncSp_EncSpBestpredLuma8x8, Prediction, 0, 32) + +RegFunc(EncSp, 0x504000, EncSpBestmodeLuma4x4Pack0, 0xB10, EncSp_EncSpBestmodeLuma4x4Pack0, 0x504b10) +RegFunc(EncSp, 0x504000, EncSpBestmodeLuma4x4Pack1, 0xB14, EncSp_EncSpBestmodeLuma4x4Pack1, 0x504b14) + +RegAreaFunc(EncMcRegsBase, 0x506000, 0x5067FF) +RegFunc(EncMcRegs, 0x506000, EncMcStart, 0x0, EncMRs_EncMcStart, 0x506000) + FldFunc(EncMRs_EncMcStart, Mbaff, 18, 1) + FldFunc(EncMRs_EncMcStart, Topfield, 17, 1) + FldFunc(EncMRs_EncMcStart, Fieldmode, 16, 1) + FldFunc(EncMRs_EncMcStart, Mbaddry, 8, 7) + FldFunc(EncMRs_EncMcStart, Mbaddrx, 0, 7) +RegFunc(EncMcRegs, 0x506000, EncMcCost0, 0x4, EncMRs_EncMcCost0, 0x506004) + FldFunc(EncMRs_EncMcCost0, Cost, 0, 32) +RegFunc(EncMcRegs, 0x506000, EncMcCost1, 0x8, EncMRs_EncMcCost1, 0x506008) + FldFunc(EncMRs_EncMcCost1, Cost, 0, 32) +RegFunc(EncMcRegs, 0x506000, EncMcCost0Uv, 0xC, EncMRs_EncMcCost0Uv, 0x50600c) + FldFunc(EncMRs_EncMcCost0Uv, Cost, 0, 32) +RegFunc(EncMcRegs, 0x506000, EncMcCost1Uv, 0x10, EncMRs_EncMcCost1Uv, 0x506010) + FldFunc(EncMRs_EncMcCost1Uv, Cost, 0, 32) +RegFunc(EncMcRegs, 0x506000, EncMcPred0, 0x800, EncMRs_EncMcPred0, 0x506800) + FldFunc(EncMRs_EncMcPred0, Prediction, 0, 32) +RegFunc(EncMcRegs, 0x506000, EncMcPred1, 0xc00, EncMRs_EncMcPred1, 0x506c00) + FldFunc(EncMRs_EncMcPred1, Prediction, 0, 32) + +RegAreaFunc(EncMcBase, 0x506800, 0x50681F) +RegFunc(EncMc, 0x506800, RegMcomCtl, 0x0, EncMc_RegMcomCtl, 0x506800) + FldFunc(EncMc_RegMcomCtl, Bintl, 31, 1) + FldFunc(EncMc_RegMcomCtl, Bref, 24, 7) + FldFunc(EncMc_RegMcomCtl, Aintl, 23, 1) + FldFunc(EncMc_RegMcomCtl, Aref, 16, 7) + FldFunc(EncMc_RegMcomCtl, Subblock, 12, 4) + FldFunc(EncMc_RegMcomCtl, Bbot, 11, 1) + FldFunc(EncMc_RegMcomCtl, Bfld, 10, 1) + FldFunc(EncMc_RegMcomCtl, Abot, 9, 1) + FldFunc(EncMc_RegMcomCtl, Afld, 8, 1) + FldFunc(EncMc_RegMcomCtl, Ysize, 6, 2) + FldFunc(EncMc_RegMcomCtl, Xsize, 4, 2) + FldFunc(EncMc_RegMcomCtl, Luma, 3, 1) + FldFunc(EncMc_RegMcomCtl, Filter261, 2, 1) + FldFunc(EncMc_RegMcomCtl, Mde, 1, 1) + FldFunc(EncMc_RegMcomCtl, Back, 0, 1) +RegFunc(EncMc, 0x506800, RegMcomSrcA, 0x4, EncMc_RegMcomSrcA, 0x506804) + FldFunc(EncMc_RegMcomSrcA, Ysrc, 16, 16) + FldFunc(EncMc_RegMcomSrcA, Xsrc, 0, 16) +RegFunc(EncMc, 0x506800, RegMcomSrcB, 0x8, EncMc_RegMcomSrcB, 0x506808) + FldFunc(EncMc_RegMcomSrcB, Ysrc, 16, 16) + FldFunc(EncMc_RegMcomSrcB, Xsrc, 0, 16) +RegFunc(EncMc, 0x506800, RegWprdVc1Pic, 0xC, EncMc_RegWprdVc1Pic, 0x50680c) + FldFunc(EncMc_RegWprdVc1Pic, Shift2, 22, 7) + FldFunc(EncMc_RegWprdVc1Pic, Scale2, 16, 6) + FldFunc(EncMc_RegWprdVc1Pic, Shift1, 10, 6) + FldFunc(EncMc_RegWprdVc1Pic, Scale1, 4, 6) + FldFunc(EncMc_RegWprdVc1Pic, Bicubic, 1, 1) + FldFunc(EncMc_RegWprdVc1Pic, Rnd, 0, 1) +RegFunc(EncMc, 0x506800, RegWprdVc1BotPic, 0x10, EncMc_RegWprdVc1BotPic, 0x506810) + FldFunc(EncMc_RegWprdVc1BotPic, Shift2, 22, 7) + FldFunc(EncMc_RegWprdVc1BotPic, Scale2, 16, 6) + FldFunc(EncMc_RegWprdVc1BotPic, Shift1, 10, 6) + FldFunc(EncMc_RegWprdVc1BotPic, Scale1, 4, 6) +RegFunc(EncMc, 0x506800, RegWprdSel, 0x14, EncMc_RegWprdSel, 0x506814) + FldFunc(EncMc_RegWprdSel, Wt0, 31, 1) + FldFunc(EncMc_RegWprdSel, A0l1, 30, 1) + FldFunc(EncMc_RegWprdSel, Vecawtsel0, 25, 5) + FldFunc(EncMc_RegWprdSel, Vecbwtsel0, 16, 9) + FldFunc(EncMc_RegWprdSel, Wt1, 15, 1) + FldFunc(EncMc_RegWprdSel, A1l1, 14, 1) + FldFunc(EncMc_RegWprdSel, Vecawtsel1, 9, 5) + FldFunc(EncMc_RegWprdSel, Vecbwtsel1, 0, 9) +RegFunc(EncMc, 0x506800, RegWprdVc1BackPic, 0x18, EncMc_RegWprdVc1BackPic, 0x506818) + FldFunc(EncMc_RegWprdVc1BackPic, Shift1, 10, 6) + FldFunc(EncMc_RegWprdVc1BackPic, Scale1, 4, 6) + FldFunc(EncMc_RegWprdVc1BackPic, Bot, 0, 1) + +RegAreaFunc(EncMbmuxBase, 0x508000, 0x508FFF) +RegFunc(EncMbmux, 0x508000, EncMbmuxQp, 0x0, EncMx_EncMbmuxQp, 0x508000) +#ifdef VCMODS_REGMAP +FldFunc(EncMx_EncMbmuxQp, Rsv7, 7, 25) +FldFunc(EncMx_EncMbmuxQp, IFrame, 6, 1) +FldFunc(EncMx_EncMbmuxQp, QP, 0, 6) +#else + FldFunc(EncMx_EncMbmuxQp, QpvOffset, 13, 5) + FldFunc(EncMx_EncMbmuxQp, QpuOffset, 8, 5) + FldFunc(EncMx_EncMbmuxQp, IfraMe, 6, 1) + FldFunc(EncMx_EncMbmuxQp, Op, 0, 6) + #endif +RegFunc(EncMbmux, 0x508000, EncMbmuxMbmode, 0x4, EncMx_EncMbmuxMbmode, 0x508004) +#ifdef VCMODS_REGMAP +FldFunc(EncMx_EncMbmuxMbmode, xform8x8, 31, 1) +FldFunc(EncMx_EncMbmuxMbmode, Rsv21, 21, 10) +FldFunc(EncMx_EncMbmuxMbmode, SP8x8Ena, 20, 1) +FldFunc(EncMx_EncMbmuxMbmode, MCPass1Ena, 19, 1) +FldFunc(EncMx_EncMbmuxMbmode, MCPass0Ena, 18, 1) +FldFunc(EncMx_EncMbmuxMbmode, SP16x16Ena, 17, 1) +FldFunc(EncMx_EncMbmuxMbmode, SP4x4Ena, 16, 1) +FldFunc(EncMx_EncMbmuxMbmode, ModeEna, 16, 5) // aggregated field +FldFunc(EncMx_EncMbmuxMbmode, Rsv9, 9, 7) +FldFunc(EncMx_EncMbmuxMbmode, HWReady, 8, 1) +FldFunc(EncMx_EncMbmuxMbmode, Rsv5, 5, 3) +FldFunc(EncMx_EncMbmuxMbmode, SP8x8, 4, 1) +FldFunc(EncMx_EncMbmuxMbmode, MCPass1, 3, 1) +FldFunc(EncMx_EncMbmuxMbmode, MCPass0, 2, 1) +FldFunc(EncMx_EncMbmuxMbmode, SP16x16, 1, 1) +FldFunc(EncMx_EncMbmuxMbmode, SP4x4, 0, 1) +FldFunc(EncMx_EncMbmuxMbmode, Mode, 0, 5) // aggregated field +#else + FldFunc(EncMx_EncMbmuxMbmode, FrextMode, 31, 1) + FldFunc(EncMx_EncMbmuxMbmode, ModeEnb, 16, 4) + FldFunc(EncMx_EncMbmuxMbmode, Rdy, 8, 1) + FldFunc(EncMx_EncMbmuxMbmode, SwMode, 0, 4) +#endif +RegFunc(EncMbmux, 0x508000, EncMbmuxCbf, 0x8, EncMx_EncMbmuxCbf, 0x508008) +#ifdef VCMODS_REGMAP +FldFunc(EncMx_EncMbmuxCbf, UDC, 28, 4) +FldFunc(EncMx_EncMbmuxCbf, VDC, 24, 4) +FldFunc(EncMx_EncMbmuxCbf, ChromaDC, 24, 8) // aggregated field +FldFunc(EncMx_EncMbmuxCbf, UAC, 20, 4) +FldFunc(EncMx_EncMbmuxCbf, VAC, 16, 4) +FldFunc(EncMx_EncMbmuxCbf, ChromaAC, 16, 8) // aggregated field +FldFunc(EncMx_EncMbmuxCbf, Luma, 0, 16) +#else + FldFunc(EncMx_EncMbmuxCbf, Udc, 28, 4) + FldFunc(EncMx_EncMbmuxCbf, Vdc, 24, 4) + FldFunc(EncMx_EncMbmuxCbf, Uac, 20, 4) + FldFunc(EncMx_EncMbmuxCbf, Vac, 16, 4) + FldFunc(EncMx_EncMbmuxCbf, Luma, 0, 16) +#endif +RegFunc(EncMbmux, 0x508000, EncMbmuxFinalcoeffLuma, 0x400, EncMx_EncMbmuxFinalcoeffLuma, 0x508400) + FldFunc(EncMx_EncMbmuxFinalcoeffLuma, Coeff, 0, 32) +RegFunc(EncMbmux, 0x508000, EncMbmuxFinalcoeffCa, 0x600, EncMx_EncMbmuxFinalcoeffCa, 0x508600) + FldFunc(EncMx_EncMbmuxFinalcoeffCa, Coeff, 0, 32) +RegFunc(EncMbmux, 0x508000, EncMbmuxFinalcoeffCb, 0x680, EncMx_EncMbmuxFinalcoeffCb, 0x508680) + FldFunc(EncMx_EncMbmuxFinalcoeffCb, Coeff, 0, 32) +RegFunc(EncMbmux, 0x508000, EncMbmuxDeltarLuma, 0x400, EncMx_EncMbmuxDeltarLuma, 0x508400) + FldFunc(EncMx_EncMbmuxDeltarLuma, DeltaR, 0, 32) +RegFunc(EncMbmux, 0x508000, EncMbmuxDeltarCa, 0x600, EncMx_EncMbmuxDeltarCa, 0x508600) + FldFunc(EncMx_EncMbmuxDeltarCa, DeltaR, 0, 32) +RegFunc(EncMbmux, 0x508000, EncMbmuxDeltarCb, 0x680, EncMx_EncMbmuxDeltarCb, 0x508680) + FldFunc(EncMx_EncMbmuxDeltarCb, DeltaR, 0, 32) + +RegAreaFunc(EncSg2Base, 0x5F0000, 0x5FFFFF) + +#ifdef VCMODS_REGMAP +#if 1 // Moved mvd in verilog (for encoder only) +RegAreaFunc(EncSintBase, 0x008000, 0x0080FF) +RegFunc(EncSint, 0x008000, EncSintDmaAddr, 0x0, EncSt_EncSintDmaAddr, 0x008000) + FldFunc(EncSt_EncSintDmaAddr, Addr, 5, 27) +RegFunc(EncSint, 0x008000, EncSintDmaLen, 0x4, EncSt_EncSintDmaLen, 0x008004) + FldFunc(EncSt_EncSintDmaLen, Length, 5, 27) +RegFunc(EncSint, 0x008000, EncSintDmaBase, 0x8, EncSt_EncSintDmaBase, 0x008008) + FldFunc(EncSt_EncSintDmaBase, Base, 6, 26) +RegFunc(EncSint, 0x008000, EncSintDmaEnd, 0xC, EncSt_EncSintDmaEnd, 0x008080) + FldFunc(EncSt_EncSintDmaEnd, End, 6, 26) +RegFunc(EncSint, 0x008000, EncSintStrmPos, 0x10, EncSt_EncSintStrmPos, 0x008010) + FldFunc(EncSt_EncSintStrmPos, BitPos, 0, 32) +RegFunc(EncSint, 0x580000, EncSintStrmStat, 0x14, EncSt_EncSintStrmStat, 0x008014) + FldFunc(EncSt_EncSintStrmStat, Rst, 16, 1) + FldFunc(EncSt_EncSintStrmStat, Derr, 9, 1) + FldFunc(EncSt_EncSintStrmStat, Serr, 8, 1) + FldFunc(EncSt_EncSintStrmStat, Ccac, 6, 1) + FldFunc(EncSt_EncSintStrmStat, Vcac, 5, 1) + FldFunc(EncSt_EncSintStrmStat, Vact, 4, 1) + FldFunc(EncSt_EncSintStrmStat, Dact, 3, 1) + FldFunc(EncSt_EncSintStrmStat, Sact, 2, 1) + FldFunc(EncSt_EncSintStrmStat, Cact, 1, 1) + FldFunc(EncSt_EncSintStrmStat, Sval, 0, 1) +RegFunc(EncSint, 0x008000, EncSintIena, 0x18, EncSt_EncSintIena, 0x008018) + FldFunc(EncSt_EncSintIena, Derr, 9, 1) + FldFunc(EncSt_EncSintIena, Serr, 8, 1) +RegFunc(EncSint, 0x008000, EncSintStrmBits, 0x1C, EncSt_EncSintStrmBits, 0x00801c) + FldFunc(EncSt_EncSintStrmBits, StreamBits, 0, 32) +RegFunc(EncSint, 0x008000, EncSintGetSymb, 0x20, EncSt_EncSintGetSymb, 0x008020) + FldFunc(EncSt_EncSintGetSymb, Type, 12, 4) + FldFunc(EncSt_EncSintGetSymb, Subtype, 8, 4) + FldFunc(EncSt_EncSintGetSymb, N, 0, 8) +RegFunc(EncSint, 0x008000, EncSintVecMbtype, 0x24, EncSt_EncSintVecMbtype, 0x008030) + FldFunc(EncSt_EncSintVecMbtype, Submbtype3, 21, 4) + FldFunc(EncSt_EncSintVecMbtype, Submbtype2, 16, 4) + FldFunc(EncSt_EncSintVecMbtype, Submbtype1, 11, 4) + FldFunc(EncSt_EncSintVecMbtype, Submbtype0, 6, 4) + FldFunc(EncSt_EncSintVecMbtype, Mbtype, 1, 5) + FldFunc(EncSt_EncSintVecMbtype, Isb, 0, 1) +//RegFunc(EncSint, 0x008000, EncSintVecRegstart, 0x30, EncSt_EncSintVecRegstart, 0x008030) +RegFunc(EncSint, 0x008000, EncSintVecResid, 0x28, EncSt_EncSintVecResid, 0x008034) + FldFunc(EncSt_EncSintVecResid, YResidual, 16, 16) + FldFunc(EncSt_EncSintVecResid, XResidual, 0, 16) +//RegFunc(EncSint, 0x008000, EncSintVecDmode, 0x2C, EncSt_EncSintVecDmode, 0x00802c) + FldFunc(EncSt_EncSintVecDmode, Dmode, 0, 4) +//RegFunc(EncSint, 0x008000, EncSintVecTopLd, 0x30, EncSt_EncSintVecTopLd, 0x008030) + FldFunc(EncSt_EncSintVecTopLd, TopRow, 30, 2) + FldFunc(EncSt_EncSintVecTopLd, TtropOffset, 16, 8) + FldFunc(EncSt_EncSintVecTopLd, UrtOffset, 8, 8) + FldFunc(EncSt_EncSintVecTopLd, TopOffest, 0, 8) +RegFunc(EncSint, 0x008000, EncSintVecDoConst, 0x40, EncSt_EncSintVecDoConst, 0x008040) + FldFunc(EncSt_EncSintVecDoConst, Mvdiff, 9, 1) + FldFunc(EncSt_EncSintVecDoConst, Rolt, 8, 1) + FldFunc(EncSt_EncSintVecDoConst, Lcpy, 7, 1) + FldFunc(EncSt_EncSintVecDoConst, Ulfld, 6, 1) + FldFunc(EncSt_EncSintVecDoConst, Pskip, 5, 1) + FldFunc(EncSt_EncSintVecDoConst, Intra, 4, 1) +RegFunc(EncSint, 0x008000, EncSintVecMvdiff, 0x44, EncSt_EncSintVecMvdiff, 0x008044) + FldFunc(EncSt_EncSintVecMvdiff, V15, 31, 1) + FldFunc(EncSt_EncSintVecMvdiff, V14, 30, 1) + FldFunc(EncSt_EncSintVecMvdiff, V13, 29, 1) + FldFunc(EncSt_EncSintVecMvdiff, V12, 28, 1) + FldFunc(EncSt_EncSintVecMvdiff, V11, 27, 1) + FldFunc(EncSt_EncSintVecMvdiff, V10, 26, 1) + FldFunc(EncSt_EncSintVecMvdiff, V9, 25, 1) + FldFunc(EncSt_EncSintVecMvdiff, V8, 24, 1) + FldFunc(EncSt_EncSintVecMvdiff, V7, 23, 1) + FldFunc(EncSt_EncSintVecMvdiff, V6, 22, 1) + FldFunc(EncSt_EncSintVecMvdiff, V5, 21, 1) + FldFunc(EncSt_EncSintVecMvdiff, V4, 20, 1) + FldFunc(EncSt_EncSintVecMvdiff, V3, 19, 1) + FldFunc(EncSt_EncSintVecMvdiff, V2, 18, 1) + FldFunc(EncSt_EncSintVecMvdiff, V1, 17, 1) + FldFunc(EncSt_EncSintVecMvdiff, V0, 16, 1) + FldFunc(EncSt_EncSintVecMvdiff, H15, 15, 1) + FldFunc(EncSt_EncSintVecMvdiff, H14, 14, 1) + FldFunc(EncSt_EncSintVecMvdiff, H13, 13, 1) + FldFunc(EncSt_EncSintVecMvdiff, H12, 12, 1) + FldFunc(EncSt_EncSintVecMvdiff, H11, 11, 1) + FldFunc(EncSt_EncSintVecMvdiff, H10, 10, 1) + FldFunc(EncSt_EncSintVecMvdiff, H9, 9, 1) + FldFunc(EncSt_EncSintVecMvdiff, H8, 8, 1) + FldFunc(EncSt_EncSintVecMvdiff, H7, 7, 1) + FldFunc(EncSt_EncSintVecMvdiff, H6, 6, 1) + FldFunc(EncSt_EncSintVecMvdiff, H5, 5, 1) + FldFunc(EncSt_EncSintVecMvdiff, H4, 4, 1) + FldFunc(EncSt_EncSintVecMvdiff, H3, 3, 1) + FldFunc(EncSt_EncSintVecMvdiff, H2, 2, 1) + FldFunc(EncSt_EncSintVecMvdiff, H1, 1, 1) + FldFunc(EncSt_EncSintVecMvdiff, H0, 0, 1) +RegFunc(EncSint, 0x008000, EncSintVecRefidx, 0x48, EncSt_EncSintVecRefidx, 0x008048) + FldFunc(EncSt_EncSintVecRefidx, Refidx3, 24, 6) + FldFunc(EncSt_EncSintVecRefidx, Refidx2, 16, 6) + FldFunc(EncSt_EncSintVecRefidx, Refidx1, 8, 6) + FldFunc(EncSt_EncSintVecRefidx, Refidx0, 0, 6) +RegFunc(EncSint, 0x008000, EncSintVecTopref, 0x4C, EncSt_EncSintVecTopref, 0x00804c) + FldFunc(EncSt_EncSintVecTopref, L1refb1, 24, 8) + FldFunc(EncSt_EncSintVecTopref, L1refb0, 16, 8) + FldFunc(EncSt_EncSintVecTopref, L0refb1, 8, 8) + FldFunc(EncSt_EncSintVecTopref, L0refb0, 0, 8) +RegFunc(EncSint, 0x008000, EncSintVecToppic, 0x80, EncSt_EncSintVecToppic, 0x00805c) + FldFunc(EncSt_EncSintVecToppic, L1picb1, 24, 8) + FldFunc(EncSt_EncSintVecToppic, L1picb0, 16, 8) + FldFunc(EncSt_EncSintVecToppic, L0picb1, 8, 8) + FldFunc(EncSt_EncSintVecToppic, L0picb0, 0, 8) +RegFunc(EncSint, 0x008000, EncSintVecToptopref, 0x00, EncSt_EncSintVecToptopref, 0x008050) + FldFunc(EncSt_EncSintVecToptopref, L1picb1, 24, 8) + FldFunc(EncSt_EncSintVecToptopref, L0picb1, 8, 8) +RegFunc(EncSint, 0x008000, EncSintVecColType, 0x54, EncSt_EncSintVecColType, 0x008054) + FldFunc(EncSt_EncSintVecColType, Mbaff, 31, 1) + FldFunc(EncSt_EncSintVecColType, Tfld, 30, 1) + FldFunc(EncSt_EncSintVecColType, Field, 29, 1) + FldFunc(EncSt_EncSintVecColType, Sub3, 8, 2) + FldFunc(EncSt_EncSintVecColType, Sub2, 6, 2) + FldFunc(EncSt_EncSintVecColType, Sub1, 4, 2) + FldFunc(EncSt_EncSintVecColType, Sub0, 2, 2) + FldFunc(EncSt_EncSintVecColType, Type, 0, 2) +RegFunc(EncSint, 0x008000, EncSintVecColRefid, 0x58, EncSt_EncSintVecColRefid, 0x008058) + FldFunc(EncSt_EncSintVecColRefid, Refidx3, 24, 5) + FldFunc(EncSt_EncSintVecColRefid, Refidx2, 16, 5) + FldFunc(EncSt_EncSintVecColRefid, Refidx1, 8, 5) + FldFunc(EncSt_EncSintVecColRefid, Refidx0, 0, 5) + +RegFunc(EncSint, 0x008000, EncSintVecRefpic, 0x64, EncSt_EncSintVecRefpic, 0x8064) + FldFunc(EncSt_EncSintVecRefpic, Hwimpiwt, 2, 1) + FldFunc(EncSt_EncSintVecRefpic, Userrev, 1, 1) + FldFunc(EncSt_EncSintVecRefpic, Ramsel, 0, 1) + +RegFunc(EncSint, 0x580000, EncSintVecMvdFifo, 0x60, EncSt_EncSintVecMvdFifo, 0x806C) +RegFunc(EncSint, 0x008000, EncSintVecRegend, 0x7F, EncSt_EncSintVecRegend, 0x00807f) + +RegFunc(EncSint, 0x580000, EncSintCtl, 0x80, EncSt_RegSintCtl, 0x8080) + FldFunc(EncSt_RegSintCtl, Vc1, 31, 1) + +RegFunc(EncSint, 0x008000, EncSintOpicMemBase, 0xC0, EncSt_EncSintOpicMemBase, 0x80c0) +RegFunc(EncSint, 0x008000, EncSintOpicMemEnd, 0xFF, EncSt_EncSintOpicMemEnd, 0x80ff) + +RegFunc(EncSint, 0x008000, EncSintVecMemBase, 0x100, EncSt_EncSintVecMemBase, 0x008100) + FldFunc(EncSt_EncSintVecMemBase, VectorYDelta, 16, 16) + FldFunc(EncSt_EncSintVecMemBase, VectorXDelta, 0, 16) +RegFunc(EncSint, 0x008000, EncSintVecMemEnd, 0x1FF, EncSt_EncSintVecMemEnd, 0x0081ff) +#endif +#endif + +RegAreaFunc(EncReconBase, 0x503000, 0x503FFF) +RegFunc(EncRecon, 0x503000, EncReconMbaddr, 0x0, EncRn_EncReconMbaddr, 0x503000) +FldFunc(EncRn_EncReconMbaddr, YPos, 8, 8) +FldFunc(EncRn_EncReconMbaddr, XPos, 0, 8) +RegFunc(EncRecon, 0x503000, EncReconDone, 0x4, EncRn_EncReconDone, 0x503004) +#ifdef VCMODS_REGMAP + +FldFunc(EncRn_EncReconDone, Rsv1, 1, 31) +FldFunc(EncRn_EncReconDone, Done, 0, 1) +#else + FldFunc(EncRn_EncReconDone, Done, 0, 1) +#endif + +// On final chips always have shared deblocker nowadays. +#define VCMODS_SHAREDDEBLOCKER +#ifdef VCMODS_SHAREDDEBLOCKER + +RegAreaFunc(EncDblkBase, 0x00720, 0x0073F) +RegFunc(EncDblk, 0x00720, RegDblkCtl, 0x0, EncDk_RegDblkCtl, 0x00720) +#ifdef VCMODS_REGMAP +FldFunc(EncDk_RegDblkCtl, Rsv8, 8, 24) +FldFunc(EncDk_RegDblkCtl, H2648x8, 7, 1) +FldFunc(EncDk_RegDblkCtl, Rsv6, 6, 1) +FldFunc(EncDk_RegDblkCtl, IsLast, 5, 1) +FldFunc(EncDk_RegDblkCtl, IsIntra, 4, 1) +FldFunc(EncDk_RegDblkCtl, FLeft, 3, 1) +FldFunc(EncDk_RegDblkCtl, FTop, 2, 1) +FldFunc(EncDk_RegDblkCtl, FInt, 1, 1) +FldFunc(EncDk_RegDblkCtl, CES, 0, 1) +#else + FldFunc(EncDk_RegDblkCtl, Mpeg, 8, 1) + FldFunc(EncDk_RegDblkCtl, H2648x8, 7, 1) + FldFunc(EncDk_RegDblkCtl, Mono, 6, 1) + FldFunc(EncDk_RegDblkCtl, IsLast, 5, 1) + FldFunc(EncDk_RegDblkCtl, Intra, 4, 1) + FldFunc(EncDk_RegDblkCtl, Fleft, 3, 1) + FldFunc(EncDk_RegDblkCtl, Ftop, 2, 1) + FldFunc(EncDk_RegDblkCtl, Fint, 1, 1) + FldFunc(EncDk_RegDblkCtl, Ces, 0, 1) +#endif +RegFunc(EncDblk, 0x00720, RegDblkOut, 0x4, EncDk_RegDblkOut, 0x00724) + FldFunc(EncDk_RegDblkOut, Out2, 16, 1) + FldFunc(EncDk_RegDblkOut, Picnum2, 8, 8) + FldFunc(EncDk_RegDblkOut, Picnum, 0, 8) +RegFunc(EncDblk, 0x00720, RegOlapXform, 0x8, EncDk_RegOlapXform, 0x00728) + FldFunc(EncDk_RegOlapXform, Topvintra, 29, 1) + FldFunc(EncDk_RegOlapXform, Topuintra, 28, 1) + FldFunc(EncDk_RegOlapXform, Toplintra, 24, 4) + FldFunc(EncDk_RegOlapXform, Vintra, 21, 1) + FldFunc(EncDk_RegOlapXform, Uintra, 20, 1) + FldFunc(EncDk_RegOlapXform, Lumaintra, 16, 4) + FldFunc(EncDk_RegOlapXform, Vv, 11, 1) + FldFunc(EncDk_RegOlapXform, Vh, 10, 1) + FldFunc(EncDk_RegOlapXform, Uv, 9, 1) + FldFunc(EncDk_RegOlapXform, Uh, 8, 1) + FldFunc(EncDk_RegOlapXform, Lumavert, 4, 4) + FldFunc(EncDk_RegOlapXform, Lumahoriz, 0, 4) +RegFunc(EncDblk, 0x00720, RegDblkQnt, 0xC, EncDk_RegDblkQnt, 0x0072c) +#ifdef VCMODS_REGMAP +FldFunc(EncDk_RegDblkQnt, Rsv24, 24, 8) +FldFunc(EncDk_RegDblkQnt, QpyTopTop, 16, 8) +FldFunc(EncDk_RegDblkQnt, QpyTop, 8, 8) +FldFunc(EncDk_RegDblkQnt, Qpy, 0, 8) +#else + FldFunc(EncDk_RegDblkQnt, Opvtoptop, 16, 8) + FldFunc(EncDk_RegDblkQnt, Opvtop, 8, 8) + FldFunc(EncDk_RegDblkQnt, Opv, 0, 8) +#endif +RegFunc(EncDblk, 0x00720, RegDblkOffset, 0x10, EncDk_RegDblkOffset, 0x00730) + FldFunc(EncDk_RegDblkOffset, Offsetb, 8, 8) + FldFunc(EncDk_RegDblkOffset, Offseta, 0, 8) +RegFunc(EncDblk, 0x00720, RegDblkTopCtx, 0x14, EncDk_RegDblkTopCtx, 0x00734) +#ifdef VCMODS_REGMAP +FldFunc(EncDk_RegDblkTopCtx, Rsv22, 22, 10) +FldFunc(EncDk_RegDblkTopCtx, TB15, 21, 1) +FldFunc(EncDk_RegDblkTopCtx, TB14, 20, 1) +FldFunc(EncDk_RegDblkTopCtx, TB11, 19, 1) +FldFunc(EncDk_RegDblkTopCtx, TB10, 18, 1) +FldFunc(EncDk_RegDblkTopCtx, Rcv17, 17, 1) +FldFunc(EncDk_RegDblkTopCtx, TIsIntra, 16, 1) +FldFunc(EncDk_RegDblkTopCtx, Rsv6, 6, 10) +FldFunc(EncDk_RegDblkTopCtx, B15, 5, 1) +FldFunc(EncDk_RegDblkTopCtx, B14, 4, 1) +FldFunc(EncDk_RegDblkTopCtx, B11, 3, 1) +FldFunc(EncDk_RegDblkTopCtx, B10, 2, 1) +FldFunc(EncDk_RegDblkTopCtx, IsField, 1, 1) +FldFunc(EncDk_RegDblkTopCtx, IsIntra, 0, 1) +#else + FldFunc(EncDk_RegDblkTopCtx, Tb15, 21, 1) + FldFunc(EncDk_RegDblkTopCtx, Tb14, 20, 1) + FldFunc(EncDk_RegDblkTopCtx, Tb11, 19, 1) + FldFunc(EncDk_RegDblkTopCtx, Tb10, 18, 1) + FldFunc(EncDk_RegDblkTopCtx, Tintra, 16, 1) + FldFunc(EncDk_RegDblkTopCtx, B15, 5, 1) + FldFunc(EncDk_RegDblkTopCtx, B14, 4, 1) + FldFunc(EncDk_RegDblkTopCtx, B11, 3, 1) + FldFunc(EncDk_RegDblkTopCtx, B10, 2, 1) + FldFunc(EncDk_RegDblkTopCtx, Field, 1, 1) + FldFunc(EncDk_RegDblkTopCtx, Intra, 0, 1) +#endif +RegFunc(EncDblk, 0x00720, RegDblkXzero, 0x18, EncDk_RegDblkXzero, 0x00738) + FldFunc(EncDk_RegDblkXzero, B15, 15, 1) + FldFunc(EncDk_RegDblkXzero, B14, 14, 1) + FldFunc(EncDk_RegDblkXzero, B13, 13, 1) + FldFunc(EncDk_RegDblkXzero, B12, 12, 1) + FldFunc(EncDk_RegDblkXzero, B11, 11, 1) + FldFunc(EncDk_RegDblkXzero, B10, 10, 1) + FldFunc(EncDk_RegDblkXzero, B9, 9, 1) + FldFunc(EncDk_RegDblkXzero, B8, 8, 1) + FldFunc(EncDk_RegDblkXzero, B7, 7, 1) + FldFunc(EncDk_RegDblkXzero, B6, 6, 1) + FldFunc(EncDk_RegDblkXzero, B5, 5, 1) + FldFunc(EncDk_RegDblkXzero, B4, 4, 1) + FldFunc(EncDk_RegDblkXzero, B3, 3, 1) + FldFunc(EncDk_RegDblkXzero, B2, 2, 1) + FldFunc(EncDk_RegDblkXzero, B1, 1, 1) + FldFunc(EncDk_RegDblkXzero, B0, 0, 1) +RegFunc(EncDblk, 0x00720, RegDblkMvdiff, 0x1C, EncDk_RegDblkMvdiff, 0x0073c) + FldFunc(EncDk_RegDblkMvdiff, V15, 31, 1) + FldFunc(EncDk_RegDblkMvdiff, V14, 30, 1) + FldFunc(EncDk_RegDblkMvdiff, V13, 29, 1) + FldFunc(EncDk_RegDblkMvdiff, V12, 28, 1) + FldFunc(EncDk_RegDblkMvdiff, V11, 27, 1) + FldFunc(EncDk_RegDblkMvdiff, V10, 26, 1) + FldFunc(EncDk_RegDblkMvdiff, V9, 25, 1) + FldFunc(EncDk_RegDblkMvdiff, V8, 24, 1) + FldFunc(EncDk_RegDblkMvdiff, V7, 23, 1) + FldFunc(EncDk_RegDblkMvdiff, V6, 22, 1) + FldFunc(EncDk_RegDblkMvdiff, V5, 21, 1) + FldFunc(EncDk_RegDblkMvdiff, V4, 20, 1) + FldFunc(EncDk_RegDblkMvdiff, V3, 19, 1) + FldFunc(EncDk_RegDblkMvdiff, V2, 18, 1) + FldFunc(EncDk_RegDblkMvdiff, V1, 17, 1) + FldFunc(EncDk_RegDblkMvdiff, V0, 16, 1) + FldFunc(EncDk_RegDblkMvdiff, H15, 15, 1) + FldFunc(EncDk_RegDblkMvdiff, H14, 14, 1) + FldFunc(EncDk_RegDblkMvdiff, H13, 13, 1) + FldFunc(EncDk_RegDblkMvdiff, H12, 12, 1) + FldFunc(EncDk_RegDblkMvdiff, H11, 11, 1) + FldFunc(EncDk_RegDblkMvdiff, H10, 10, 1) + FldFunc(EncDk_RegDblkMvdiff, H9, 9, 1) + FldFunc(EncDk_RegDblkMvdiff, H8, 8, 1) + FldFunc(EncDk_RegDblkMvdiff, H7, 7, 1) + FldFunc(EncDk_RegDblkMvdiff, H6, 6, 1) + FldFunc(EncDk_RegDblkMvdiff, H5, 5, 1) + FldFunc(EncDk_RegDblkMvdiff, H4, 4, 1) + FldFunc(EncDk_RegDblkMvdiff, H3, 3, 1) + FldFunc(EncDk_RegDblkMvdiff, H2, 2, 1) + FldFunc(EncDk_RegDblkMvdiff, H1, 1, 1) + FldFunc(EncDk_RegDblkMvdiff, H0, 0, 1) + + RegAreaFunc(EncMbCtlBase, 0x000740, 0x00075F) +RegFunc(EncMbCtl, 0x000740, RegMbCtl, 0x0, EncMCl_RegMbCtl, 0x000740) +#ifdef VCMODS_REGMAP +FldFunc(EncMCl_RegMbCtl, Rsv18, 19, 13) +FldFunc(EncMCl_RegMbCtl, MBAFF, 18, 1) +FldFunc(EncMCl_RegMbCtl, TopField, 17, 1) +FldFunc(EncMCl_RegMbCtl, FieldMode, 16, 1) +FldFunc(EncMCl_RegMbCtl, Rsv15, 15, 1) +FldFunc(EncMCl_RegMbCtl, YDestMB, 8, 7) +FldFunc(EncMCl_RegMbCtl, Rsv7, 7, 1) +FldFunc(EncMCl_RegMbCtl, XDestMB, 0, 7) +#else + FldFunc(EncMCl_RegMbCtl, Fcm, 26, 2) + FldFunc(EncMCl_RegMbCtl, Type, 24, 2) + FldFunc(EncMCl_RegMbCtl, Mbaff, 18, 1) + FldFunc(EncMCl_RegMbCtl, Top, 17, 1) + FldFunc(EncMCl_RegMbCtl, Fld, 16, 1) + FldFunc(EncMCl_RegMbCtl, Ydestmb, 8, 7) + FldFunc(EncMCl_RegMbCtl, Rv, 7, 1) + FldFunc(EncMCl_RegMbCtl, Xdestmb, 0, 7) +#endif + + + +#else + +//#error Separate deblockers, probably wrong + +RegAreaFunc(EncDblkBase, 0x500720, 0x50073F) +RegFunc(EncDblk, 0x500720, RegDblkCtl, 0x0, EncDk_RegDblkCtl, 0x500720) +#ifdef VCMODS_REGMAP +FldFunc(EncDk_RegDblkCtl, Rsv8, 8, 24) +FldFunc(EncDk_RegDblkCtl, H2648x8, 7, 1) +FldFunc(EncDk_RegDblkCtl, Rsv6, 6, 1) +FldFunc(EncDk_RegDblkCtl, IsLast, 5, 1) +FldFunc(EncDk_RegDblkCtl, IsIntra, 4, 1) +FldFunc(EncDk_RegDblkCtl, FLeft, 3, 1) +FldFunc(EncDk_RegDblkCtl, FTop, 2, 1) +FldFunc(EncDk_RegDblkCtl, FInt, 1, 1) +FldFunc(EncDk_RegDblkCtl, CES, 0, 1) +#else + FldFunc(EncDk_RegDblkCtl, Mpeg, 8, 1) + FldFunc(EncDk_RegDblkCtl, H2648x8, 7, 1) + FldFunc(EncDk_RegDblkCtl, Mono, 6, 1) + FldFunc(EncDk_RegDblkCtl, IsLast, 5, 1) + FldFunc(EncDk_RegDblkCtl, Intra, 4, 1) + FldFunc(EncDk_RegDblkCtl, Fleft, 3, 1) + FldFunc(EncDk_RegDblkCtl, Ftop, 2, 1) + FldFunc(EncDk_RegDblkCtl, Fint, 1, 1) + FldFunc(EncDk_RegDblkCtl, Ces, 0, 1) +#endif +RegFunc(EncDblk, 0x500720, RegDblkOut, 0x4, EncDk_RegDblkOut, 0x500724) + FldFunc(EncDk_RegDblkOut, Out2, 16, 1) + FldFunc(EncDk_RegDblkOut, Picnum2, 8, 8) + FldFunc(EncDk_RegDblkOut, Picnum, 0, 8) +RegFunc(EncDblk, 0x500720, RegOlapXform, 0x8, EncDk_RegOlapXform, 0x500728) + FldFunc(EncDk_RegOlapXform, Topvintra, 29, 1) + FldFunc(EncDk_RegOlapXform, Topuintra, 28, 1) + FldFunc(EncDk_RegOlapXform, Toplintra, 24, 4) + FldFunc(EncDk_RegOlapXform, Vintra, 21, 1) + FldFunc(EncDk_RegOlapXform, Uintra, 20, 1) + FldFunc(EncDk_RegOlapXform, Lumaintra, 16, 4) + FldFunc(EncDk_RegOlapXform, Vv, 11, 1) + FldFunc(EncDk_RegOlapXform, Vh, 10, 1) + FldFunc(EncDk_RegOlapXform, Uv, 9, 1) + FldFunc(EncDk_RegOlapXform, Uh, 8, 1) + FldFunc(EncDk_RegOlapXform, Lumavert, 4, 4) + FldFunc(EncDk_RegOlapXform, Lumahoriz, 0, 4) +RegFunc(EncDblk, 0x500720, RegDblkQnt, 0xC, EncDk_RegDblkQnt, 0x50072c) +#ifdef VCMODS_REGMAP +FldFunc(EncDk_RegDblkQnt, Rsv24, 24, 8) +FldFunc(EncDk_RegDblkQnt, QpyTopTop, 16, 8) +FldFunc(EncDk_RegDblkQnt, QpyTop, 8, 8) +FldFunc(EncDk_RegDblkQnt, Qpy, 0, 8) +#else + FldFunc(EncDk_RegDblkQnt, Opvtoptop, 16, 8) + FldFunc(EncDk_RegDblkQnt, Opvtop, 8, 8) + FldFunc(EncDk_RegDblkQnt, Opv, 0, 8) +#endif +RegFunc(EncDblk, 0x500720, RegDblkOffset, 0x10, EncDk_RegDblkOffset, 0x500730) + FldFunc(EncDk_RegDblkOffset, Offsetb, 8, 8) + FldFunc(EncDk_RegDblkOffset, Offseta, 0, 8) +RegFunc(EncDblk, 0x500720, RegDblkTopCtx, 0x14, EncDk_RegDblkTopCtx, 0x500734) +#ifdef VCMODS_REGMAP +FldFunc(EncDk_RegDblkTopCtx, Rsv22, 22, 10) +FldFunc(EncDk_RegDblkTopCtx, TB15, 21, 1) +FldFunc(EncDk_RegDblkTopCtx, TB14, 20, 1) +FldFunc(EncDk_RegDblkTopCtx, TB11, 19, 1) +FldFunc(EncDk_RegDblkTopCtx, TB10, 18, 1) +FldFunc(EncDk_RegDblkTopCtx, Rcv17, 17, 1) +FldFunc(EncDk_RegDblkTopCtx, TIsIntra, 16, 1) +FldFunc(EncDk_RegDblkTopCtx, Rsv6, 6, 10) +FldFunc(EncDk_RegDblkTopCtx, B15, 5, 1) +FldFunc(EncDk_RegDblkTopCtx, B14, 4, 1) +FldFunc(EncDk_RegDblkTopCtx, B11, 3, 1) +FldFunc(EncDk_RegDblkTopCtx, B10, 2, 1) +FldFunc(EncDk_RegDblkTopCtx, IsField, 1, 1) +FldFunc(EncDk_RegDblkTopCtx, IsIntra, 0, 1) +#else + FldFunc(EncDk_RegDblkTopCtx, Tb15, 21, 1) + FldFunc(EncDk_RegDblkTopCtx, Tb14, 20, 1) + FldFunc(EncDk_RegDblkTopCtx, Tb11, 19, 1) + FldFunc(EncDk_RegDblkTopCtx, Tb10, 18, 1) + FldFunc(EncDk_RegDblkTopCtx, Tintra, 16, 1) + FldFunc(EncDk_RegDblkTopCtx, B15, 5, 1) + FldFunc(EncDk_RegDblkTopCtx, B14, 4, 1) + FldFunc(EncDk_RegDblkTopCtx, B11, 3, 1) + FldFunc(EncDk_RegDblkTopCtx, B10, 2, 1) + FldFunc(EncDk_RegDblkTopCtx, Field, 1, 1) + FldFunc(EncDk_RegDblkTopCtx, Intra, 0, 1) +#endif +RegFunc(EncDblk, 0x500720, RegDblkXzero, 0x18, EncDk_RegDblkXzero, 0x500738) + FldFunc(EncDk_RegDblkXzero, B15, 15, 1) + FldFunc(EncDk_RegDblkXzero, B14, 14, 1) + FldFunc(EncDk_RegDblkXzero, B13, 13, 1) + FldFunc(EncDk_RegDblkXzero, B12, 12, 1) + FldFunc(EncDk_RegDblkXzero, B11, 11, 1) + FldFunc(EncDk_RegDblkXzero, B10, 10, 1) + FldFunc(EncDk_RegDblkXzero, B9, 9, 1) + FldFunc(EncDk_RegDblkXzero, B8, 8, 1) + FldFunc(EncDk_RegDblkXzero, B7, 7, 1) + FldFunc(EncDk_RegDblkXzero, B6, 6, 1) + FldFunc(EncDk_RegDblkXzero, B5, 5, 1) + FldFunc(EncDk_RegDblkXzero, B4, 4, 1) + FldFunc(EncDk_RegDblkXzero, B3, 3, 1) + FldFunc(EncDk_RegDblkXzero, B2, 2, 1) + FldFunc(EncDk_RegDblkXzero, B1, 1, 1) + FldFunc(EncDk_RegDblkXzero, B0, 0, 1) +RegFunc(EncDblk, 0x500720, RegDblkMvdiff, 0x1C, EncDk_RegDblkMvdiff, 0x50073c) + FldFunc(EncDk_RegDblkMvdiff, V15, 31, 1) + FldFunc(EncDk_RegDblkMvdiff, V14, 30, 1) + FldFunc(EncDk_RegDblkMvdiff, V13, 29, 1) + FldFunc(EncDk_RegDblkMvdiff, V12, 28, 1) + FldFunc(EncDk_RegDblkMvdiff, V11, 27, 1) + FldFunc(EncDk_RegDblkMvdiff, V10, 26, 1) + FldFunc(EncDk_RegDblkMvdiff, V9, 25, 1) + FldFunc(EncDk_RegDblkMvdiff, V8, 24, 1) + FldFunc(EncDk_RegDblkMvdiff, V7, 23, 1) + FldFunc(EncDk_RegDblkMvdiff, V6, 22, 1) + FldFunc(EncDk_RegDblkMvdiff, V5, 21, 1) + FldFunc(EncDk_RegDblkMvdiff, V4, 20, 1) + FldFunc(EncDk_RegDblkMvdiff, V3, 19, 1) + FldFunc(EncDk_RegDblkMvdiff, V2, 18, 1) + FldFunc(EncDk_RegDblkMvdiff, V1, 17, 1) + FldFunc(EncDk_RegDblkMvdiff, V0, 16, 1) + FldFunc(EncDk_RegDblkMvdiff, H15, 15, 1) + FldFunc(EncDk_RegDblkMvdiff, H14, 14, 1) + FldFunc(EncDk_RegDblkMvdiff, H13, 13, 1) + FldFunc(EncDk_RegDblkMvdiff, H12, 12, 1) + FldFunc(EncDk_RegDblkMvdiff, H11, 11, 1) + FldFunc(EncDk_RegDblkMvdiff, H10, 10, 1) + FldFunc(EncDk_RegDblkMvdiff, H9, 9, 1) + FldFunc(EncDk_RegDblkMvdiff, H8, 8, 1) + FldFunc(EncDk_RegDblkMvdiff, H7, 7, 1) + FldFunc(EncDk_RegDblkMvdiff, H6, 6, 1) + FldFunc(EncDk_RegDblkMvdiff, H5, 5, 1) + FldFunc(EncDk_RegDblkMvdiff, H4, 4, 1) + FldFunc(EncDk_RegDblkMvdiff, H3, 3, 1) + FldFunc(EncDk_RegDblkMvdiff, H2, 2, 1) + FldFunc(EncDk_RegDblkMvdiff, H1, 1, 1) + FldFunc(EncDk_RegDblkMvdiff, H0, 0, 1) + +RegAreaFunc(EncMbCtlBase, 0x500740, 0x50075F) +RegFunc(EncMbCtl, 0x500740, RegMbCtl, 0x0, EncMCl_RegMbCtl, 0x500740) +#ifdef VCMODS_REGMAP +FldFunc(EncMCl_RegMbCtl, Rsv18, 19, 13) +FldFunc(EncMCl_RegMbCtl, MBAFF, 18, 1) +FldFunc(EncMCl_RegMbCtl, TopField, 17, 1) +FldFunc(EncMCl_RegMbCtl, FieldMode, 16, 1) +FldFunc(EncMCl_RegMbCtl, Rsv15, 15, 1) +FldFunc(EncMCl_RegMbCtl, YDestMB, 8, 7) +FldFunc(EncMCl_RegMbCtl, Rsv7, 7, 1) +FldFunc(EncMCl_RegMbCtl, XDestMB, 0, 7) +#else + FldFunc(EncMCl_RegMbCtl, Fcm, 26, 2) + FldFunc(EncMCl_RegMbCtl, Type, 24, 2) + FldFunc(EncMCl_RegMbCtl, Mbaff, 18, 1) + FldFunc(EncMCl_RegMbCtl, Top, 17, 1) + FldFunc(EncMCl_RegMbCtl, Fld, 16, 1) + FldFunc(EncMCl_RegMbCtl, Ydestmb, 8, 7) + FldFunc(EncMCl_RegMbCtl, Rv, 7, 1) + FldFunc(EncMCl_RegMbCtl, Xdestmb, 0, 7) +#endif + +#endif + + + +RegAreaFunc(EncCmbBase, 0x505000, 0x505FFF) +RegFunc(EncCmb, 0x505000, EncCmbMbaddr, 0x0, EncCb_EncCmbMbaddr, 0x505000) +#ifdef VCMODS_REGMAP +FldFunc(EncCb_EncCmbMbaddr, YPos, 8, 8) +FldFunc(EncCb_EncCmbMbaddr, XPos, 0, 8) +#else + FldFunc(EncCb_EncCmbMbaddr, Ypos, 8, 8) + FldFunc(EncCb_EncCmbMbaddr, Xpos, 0, 8) +#endif +RegFunc(EncCmb, 0x505000, EncCmbPict, 0x4, EncCb_EncCmbPict, 0x505004) + FldFunc(EncCb_EncCmbPict, BotField, 9, 1) + FldFunc(EncCb_EncCmbPict, TopField, 8, 1) + FldFunc(EncCb_EncCmbPict, Pict, 0, 8) +RegFunc(EncCmb, 0x505000, EncCmbDone, 0x8, EncCb_EncCmbDone, 0x505008) + FldFunc(EncCb_EncCmbDone, Done, 0, 1) +RegFunc(EncCmb, 0x505000, EncCmbTrafficKnob, 0x10, EncCb_EncCmbTrafficKnob, 0x505010) + FldFunc(EncCb_EncCmbTrafficKnob, NumCycles, 0, 32) +RegFunc(EncCmb, 0x505000, EncCmbLuma, 0x200, EncCb_EncCmbLuma, 0x505200) +RegFunc(EncCmb, 0x505000, EncCmbCa, 0x300, EncCb_EncCmbCa, 0x505300) +RegFunc(EncCmb, 0x505000, EncCmbCb, 0x340, EncCb_EncCmbCb, 0x505340) + +RegAreaFunc(EncMvdBase, 0x50C000, 0x50C0FF) + +RegAreaFunc(EncIframeCtlBase, 0x500100, 0x5001FF) +RegFunc(EncIframeCtl, 0x500100, EncIframeCtl, 0x0, EncICl_EncIframeCtl, 0x500100) +#ifdef VCMODS_REGMAP +FldFunc(EncICl_EncIframeCtl, DBReady, 30, 1) // read-only +FldFunc(EncICl_EncIframeCtl, Rsv27, 27, 3) +FldFunc(EncICl_EncIframeCtl, ImgHeight, 16, 11) // write_only +FldFunc(EncICl_EncIframeCtl, Rsv11, 11, 5) +FldFunc(EncICl_EncIframeCtl, ImgWidth, 0, 11) // write-only +#else + FldFunc(EncICl_EncIframeCtl, EncStd, 27, 3) + FldFunc(EncICl_EncIframeCtl, Lines, 16, 11) + FldFunc(EncICl_EncIframeCtl, Width, 0, 11) +#endif +RegFunc(EncIframeCtl, 0x500100, EncIframeMpeg, 0x4, EncICl_EncIframeMpeg, 0x500104) + FldFunc(EncICl_EncIframeMpeg, CmbMpegMode, 2, 1) + FldFunc(EncICl_EncIframeMpeg, ReconMpegMode, 1, 1) + FldFunc(EncICl_EncIframeMpeg, MpegMode, 0, 1) + +RegAreaFunc(EncSe2binBase, 0x500E00, 0x500E7F) +RegFunc(EncSe2bin, 0x500E00, EncSe2binPutsym, 0x0, EncSn_EncSe2binPutsym, 0x500e00) +#ifdef VCMODS_REGMAP + FldFunc(EncSn_EncSe2binPutsym, Rsv16, 16, 16) + FldFunc(EncSn_EncSe2binPutsym, Type, 12, 4) + FldFunc(EncSn_EncSe2binPutsym, SubType, 8, 4) + FldFunc(EncSn_EncSe2binPutsym, N, 0, 8) +#else + FldFunc(EncSn_EncSe2binPutsym, Type, 12, 4) + FldFunc(EncSn_EncSe2binPutsym, SubType, 7, 5) + FldFunc(EncSn_EncSe2binPutsym, N, 0, 7) +#endif +RegFunc(EncSe2bin, 0x500E00, EncSe2binSymbol, 0x4, EncSn_EncSe2binSymbol, 0x500e04) + FldFunc(EncSn_EncSe2binSymbol, Symbol, 0, 32) +RegFunc(EncSe2bin, 0x500E00, EncSe2binBufAddr, 0x8, EncSn_EncSe2binBufAddr, 0x500e08) + FldFunc(EncSn_EncSe2binBufAddr, BufferAddress, 0, 32) +RegFunc(EncSe2bin, 0x500E00, EncSe2binBufStartAddr, 0xC, EncSn_EncSe2binBufStartAddr, 0x500e0c) + FldFunc(EncSn_EncSe2binBufStartAddr, BufferStartAddress, 0, 32) +RegFunc(EncSe2bin, 0x500E00, EncSe2binBufEndAddr, 0x10, EncSn_EncSe2binBufEndAddr, 0x500e10) + FldFunc(EncSn_EncSe2binBufEndAddr, BufferEndAddress, 0, 32) +RegFunc(EncSe2bin, 0x500E00, EncSe2binBufMarkAddr, 0x14, EncSn_EncSe2binBufMarkAddr, 0x500e14) + FldFunc(EncSn_EncSe2binBufMarkAddr, BufferMarkAddress, 0, 32) +RegFunc(EncSe2bin, 0x500E00, EncSe2binDoResid, 0x18, EncSn_EncSe2binDoResid, 0x500e18) +#ifdef VCMODS_REGMAP +FldFunc(EncSn_EncSe2binDoResid, Rsv17, 17, 15) +FldFunc(EncSn_EncSe2binDoResid, I8x8, 16, 1) +FldFunc(EncSn_EncSe2binDoResid, Type, 14, 2) +FldFunc(EncSn_EncSe2binDoResid, Rsv10, 10, 4) +FldFunc(EncSn_EncSe2binDoResid, TopAvail, 9, 1) +FldFunc(EncSn_EncSe2binDoResid, LeftAvail, 8, 1) +FldFunc(EncSn_EncSe2binDoResid, Busy, 7, 1) +FldFunc(EncSn_EncSe2binDoResid, I16, 6, 1) +FldFunc(EncSn_EncSe2binDoResid, CBP, 0, 6) +FldFunc(EncSn_EncSe2binDoResid, CbpChr, 4, 2) +FldFunc(EncSn_EncSe2binDoResid, CbpLum, 0, 4) +#else + FldFunc(EncSn_EncSe2binDoResid, Type, 14, 2) + FldFunc(EncSn_EncSe2binDoResid, Busy, 7, 1) + FldFunc(EncSn_EncSe2binDoResid, I16, 6, 1) + FldFunc(EncSn_EncSe2binDoResid, Cbp, 0, 6) +#endif +RegFunc(EncSe2bin, 0x500E00, EncSe2binBufStallCount, 0x1C, EncSn_EncSe2binBufStallCount, 0x500e1c) +RegFunc(EncSe2bin, 0x500E00, EncSe2binBufBitsWritten, 0x20, EncSn_EncSe2binBufBitsWritten, 0x500e20) +RegFunc(EncSe2bin, 0x500E00, EncSe2binTopCtx, 0x24, EncSn_EncSe2binTopCtx, 0x500e24) +#ifdef VCMODS_REGMAP +RegFunc(EncSe2bin, 0x500E00, EncSe2binFastputsym, 0x28, EncSn_EncSe2binFastputsym, 0x500e28) +FldFunc(EncSn_EncSe2binFastputsym, Type, 28, 4) +FldFunc(EncSn_EncSe2binFastputsym, SubType, 25, 3) +FldFunc(EncSn_EncSe2binFastputsym, N, 19, 6) +FldFunc(EncSn_EncSe2binFastputsym, Symbol, 0, 19) +#endif + +RegAreaFunc(EncMidCpuregsBase, 0x500F00, 0x500F7F) +RegFunc(EncMidCpuregs, 0x500F00, RegHst2cpuMbx, 0x0, EncMCs_RegHst2cpuMbx, 0x500f00) + FldFunc(EncMCs_RegHst2cpuMbx, Value, 0, 32) +RegFunc(EncMidCpuregs, 0x500F00, RegCpu2hstMbx, 0x4, EncMCs_RegCpu2hstMbx, 0x500f04) + FldFunc(EncMCs_RegCpu2hstMbx, Value, 0, 32) +RegFunc(EncMidCpuregs, 0x500F00, RegMbxStat, 0x8, EncMCs_RegMbxStat, 0x500f08) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIntBase, 0xC, EncMCs_RegCpuIntBase, 0x500f0c) + FldFunc(EncMCs_RegCpuIntBase, Addr, 8, 24) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIntEna, 0x10, EncMCs_RegCpuIntEna, 0x500f10) + FldFunc(EncMCs_RegCpuIntEna, Mbx, 31, 1) + FldFunc(EncMCs_RegCpuIntEna, Com7, 23, 1) + FldFunc(EncMCs_RegCpuIntEna, Com6, 22, 1) + FldFunc(EncMCs_RegCpuIntEna, Com5, 21, 1) + FldFunc(EncMCs_RegCpuIntEna, Com4, 20, 1) + FldFunc(EncMCs_RegCpuIntEna, Com3, 19, 1) + FldFunc(EncMCs_RegCpuIntEna, Com2, 18, 1) + FldFunc(EncMCs_RegCpuIntEna, Com1, 17, 1) + FldFunc(EncMCs_RegCpuIntEna, Com0, 16, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw7, 15, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw6, 14, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw5, 13, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw4, 12, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw3, 11, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw2, 10, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw1, 9, 1) + FldFunc(EncMCs_RegCpuIntEna, Hw0, 8, 1) + FldFunc(EncMCs_RegCpuIntEna, Db7, 7, 1) + FldFunc(EncMCs_RegCpuIntEna, Db6, 6, 1) + FldFunc(EncMCs_RegCpuIntEna, Db5, 5, 1) + FldFunc(EncMCs_RegCpuIntEna, Db4, 4, 1) + FldFunc(EncMCs_RegCpuIntEna, Db3, 3, 1) + FldFunc(EncMCs_RegCpuIntEna, Db2, 2, 1) + FldFunc(EncMCs_RegCpuIntEna, Db1, 1, 1) + FldFunc(EncMCs_RegCpuIntEna, Db0, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, StreamCpuIntEna, 0x10, EncMCs_StreamCpuIntEna, 0x500f10) + FldFunc(EncMCs_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(EncMCs_StreamCpuIntEna, Dec, 18, 1) + FldFunc(EncMCs_StreamCpuIntEna, Aud, 17, 1) + FldFunc(EncMCs_StreamCpuIntEna, M2m, 15, 1) + FldFunc(EncMCs_StreamCpuIntEna, Pci, 14, 1) + FldFunc(EncMCs_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(EncMCs_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(EncMCs_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(EncMCs_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(EncMCs_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(EncMCs_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(EncMCs_StreamCpuIntEna, Rb, 1, 1) + FldFunc(EncMCs_StreamCpuIntEna, Sd, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, Dec0CpuIntEna, 0x10, EncMCs_Dec0CpuIntEna, 0x500f10) + FldFunc(EncMCs_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(EncMCs_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(EncMCs_Dec0CpuIntEna, Si, 8, 1) + FldFunc(EncMCs_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(EncMCs_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, Dec1CpuIntEna, 0x10, EncMCs_Dec1CpuIntEna, 0x500f10) + FldFunc(EncMCs_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(EncMCs_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(EncMCs_Dec1CpuIntEna, Si, 8, 1) + FldFunc(EncMCs_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(EncMCs_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIntStat, 0x14, EncMCs_RegCpuIntStat, 0x500f14) + FldFunc(EncMCs_RegCpuIntStat, Mbx, 31, 1) + FldFunc(EncMCs_RegCpuIntStat, Com7, 23, 1) + FldFunc(EncMCs_RegCpuIntStat, Com6, 22, 1) + FldFunc(EncMCs_RegCpuIntStat, Com5, 21, 1) + FldFunc(EncMCs_RegCpuIntStat, Com4, 20, 1) + FldFunc(EncMCs_RegCpuIntStat, Com3, 19, 1) + FldFunc(EncMCs_RegCpuIntStat, Com2, 18, 1) + FldFunc(EncMCs_RegCpuIntStat, Com1, 17, 1) + FldFunc(EncMCs_RegCpuIntStat, Com0, 16, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw7, 15, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw6, 14, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw5, 13, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw4, 12, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw3, 11, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw2, 10, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw1, 9, 1) + FldFunc(EncMCs_RegCpuIntStat, Hw0, 8, 1) + FldFunc(EncMCs_RegCpuIntStat, Db7, 7, 1) + FldFunc(EncMCs_RegCpuIntStat, Db6, 6, 1) + FldFunc(EncMCs_RegCpuIntStat, Db5, 5, 1) + FldFunc(EncMCs_RegCpuIntStat, Db4, 4, 1) + FldFunc(EncMCs_RegCpuIntStat, Db3, 3, 1) + FldFunc(EncMCs_RegCpuIntStat, Db2, 2, 1) + FldFunc(EncMCs_RegCpuIntStat, Db1, 1, 1) + FldFunc(EncMCs_RegCpuIntStat, Db0, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, StreamCpuIntStat, 0x14, EncMCs_StreamCpuIntStat, 0x500f14) + FldFunc(EncMCs_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(EncMCs_StreamCpuIntStat, Dec, 18, 1) + FldFunc(EncMCs_StreamCpuIntStat, Aud, 17, 1) + FldFunc(EncMCs_StreamCpuIntStat, M2m, 15, 1) + FldFunc(EncMCs_StreamCpuIntStat, Pci, 14, 1) + FldFunc(EncMCs_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(EncMCs_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(EncMCs_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(EncMCs_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(EncMCs_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(EncMCs_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(EncMCs_StreamCpuIntStat, Rb, 1, 1) + FldFunc(EncMCs_StreamCpuIntStat, Sd, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, Dec0CpuIntStat, 0x14, EncMCs_Dec0CpuIntStat, 0x500f14) + FldFunc(EncMCs_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(EncMCs_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(EncMCs_Dec0CpuIntStat, Si, 8, 1) + FldFunc(EncMCs_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(EncMCs_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, Dec1CpuIntStat, 0x14, EncMCs_Dec1CpuIntStat, 0x500f14) + FldFunc(EncMCs_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(EncMCs_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(EncMCs_Dec1CpuIntStat, Si, 8, 1) + FldFunc(EncMCs_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(EncMCs_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, RegHst2cpuStat, 0x18, EncMCs_RegHst2cpuStat, 0x500f18) + FldFunc(EncMCs_RegHst2cpuStat, Value, 0, 32) +RegFunc(EncMidCpuregs, 0x500F00, RegCpu2hstStat, 0x1C, EncMCs_RegCpu2hstStat, 0x500f1c) + FldFunc(EncMCs_RegCpu2hstStat, Value, 0, 32) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIntgenSet, 0x20, EncMCs_RegCpuIntgenSet, 0x500f20) + FldFunc(EncMCs_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(EncMCs_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIntgenClr, 0x24, EncMCs_RegCpuIntgenClr, 0x500f24) + FldFunc(EncMCs_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(EncMCs_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIcacheMiss, 0x28, EncMCs_RegCpuIcacheMiss, 0x500f28) + FldFunc(EncMCs_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(EncMidCpuregs, 0x500F00, RegCpuIntgenMask, 0x2C, EncMCs_RegCpuIntgenMask, 0x500f2c) + FldFunc(EncMCs_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(EncMCs_RegCpuIntgenMask, Int0, 0, 1) + +RegAreaFunc(EncCabac2binsBase, 0x500B00, 0x500BFF) +RegFunc(EncCabac2bins, 0x500B00, RegCabac2binsImgCtxLast, 0xBC, EncCs_RegCabac2binsImgCtxLast, 0x500bbc) + FldFunc(EncCs_RegCabac2binsImgCtxLast, Ctxlast, 0, 9) +RegFunc(EncCabac2bins, 0x500B00, RegCabac2binsRdContextBaseAddr, 0xD0, EncCs_RegCabac2binsRdContextBaseAddr, 0x500bd0) + FldFunc(EncCs_RegCabac2binsRdContextBaseAddr, Addr, 0, 32) +RegFunc(EncCabac2bins, 0x500B00, RegCabac2binsWrContextBaseAddr, 0xD4, EncCs_RegCabac2binsWrContextBaseAddr, 0x500bd4) + FldFunc(EncCs_RegCabac2binsWrContextBaseAddr, Addr, 0, 32) + +RegAreaFunc(EncCabac2bins2Base, 0x507400, 0x5077FF) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdContextId, 0x178, EncC2_RegCabac2binsRdContextId, 0x507578) + FldFunc(EncC2_RegCabac2binsRdContextId, Id, 0, 6) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdBuffAddr, 0x188, EncC2_RegCabac2binsRdBuffAddr, 0x507588) + FldFunc(EncC2_RegCabac2binsRdBuffAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdBuffCtl, 0x18C, EncC2_RegCabac2binsRdBuffCtl, 0x50758c) + FldFunc(EncC2_RegCabac2binsRdBuffCtl, AtMark, 4, 1) + FldFunc(EncC2_RegCabac2binsRdBuffCtl, NotRdy, 3, 1) + FldFunc(EncC2_RegCabac2binsRdBuffCtl, WrapEn, 2, 1) + FldFunc(EncC2_RegCabac2binsRdBuffCtl, Init, 1, 1) + FldFunc(EncC2_RegCabac2binsRdBuffCtl, BuffEn, 0, 1) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdBuffStartAddr, 0x194, EncC2_RegCabac2binsRdBuffStartAddr, 0x507594) + FldFunc(EncC2_RegCabac2binsRdBuffStartAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdBuffEndAddr, 0x198, EncC2_RegCabac2binsRdBuffEndAddr, 0x507598) + FldFunc(EncC2_RegCabac2binsRdBuffEndAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdBuffMarkAddr, 0x17C, EncC2_RegCabac2binsRdBuffMarkAddr, 0x50757c) + FldFunc(EncC2_RegCabac2binsRdBuffMarkAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsRdBuffStallCnt, 0x19C, EncC2_RegCabac2binsRdBuffStallCnt, 0x50759c) + FldFunc(EncC2_RegCabac2binsRdBuffStallCnt, Count, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrBuffStartAddr, 0x1A8, EncC2_RegCabac2binsWrBuffStartAddr, 0x5075a8) + FldFunc(EncC2_RegCabac2binsWrBuffStartAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrBuffCtl, 0x1AC, EncC2_RegCabac2binsWrBuffCtl, 0x5075ac) + FldFunc(EncC2_RegCabac2binsWrBuffCtl, BuffClose, 2, 1) + FldFunc(EncC2_RegCabac2binsWrBuffCtl, Init, 1, 1) + FldFunc(EncC2_RegCabac2binsWrBuffCtl, BuffEn, 0, 1) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrBuffEndAddr, 0x1B0, EncC2_RegCabac2binsWrBuffEndAddr, 0x5075b0) + FldFunc(EncC2_RegCabac2binsWrBuffEndAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrBuffMarkAddr, 0x1B4, EncC2_RegCabac2binsWrBuffMarkAddr, 0x5075b4) + FldFunc(EncC2_RegCabac2binsWrBuffMarkAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrBuffStallCnt, 0x1B8, EncC2_RegCabac2binsWrBuffStallCnt, 0x5075b8) + FldFunc(EncC2_RegCabac2binsWrBuffStallCnt, Count, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrBuffAddr, 0x1BC, EncC2_RegCabac2binsWrBuffAddr, 0x5075bc) + FldFunc(EncC2_RegCabac2binsWrBuffAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsWrContextId, 0x1C0, EncC2_RegCabac2binsWrContextId, 0x5075c0) + FldFunc(EncC2_RegCabac2binsWrContextId, Id, 0, 6) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsNotIdleCycles, 0x220, EncC2_RegCabac2binsNotIdleCycles, 0x507620) + FldFunc(EncC2_RegCabac2binsNotIdleCycles, CycleCount, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsState0, 0x230, EncC2_RegCabac2binsState0, 0x507630) + FldFunc(EncC2_RegCabac2binsState0, State, 0, 11) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsState1, 0x234, EncC2_RegCabac2binsState1, 0x507634) + FldFunc(EncC2_RegCabac2binsState1, State, 0, 11) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsUpstripembBaseAddr, 0x300, EncC2_RegCabac2binsUpstripembBaseAddr, 0x507700) + FldFunc(EncC2_RegCabac2binsUpstripembBaseAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsCommandBufferAddr, 0x310, EncC2_RegCabac2binsCommandBufferAddr, 0x507710) + FldFunc(EncC2_RegCabac2binsCommandBufferAddr, Addr, 0, 32) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsCommandBufferCount, 0x314, EncC2_RegCabac2binsCommandBufferCount, 0x507714) + FldFunc(EncC2_RegCabac2binsCommandBufferCount, CommandBufferCount, 0, 11) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsCommandBufferLogSize, 0x318, EncC2_RegCabac2binsCommandBufferLogSize, 0x507718) + FldFunc(EncC2_RegCabac2binsCommandBufferLogSize, CommandBufferSize, 0, 5) +RegFunc(EncCabac2bins2, 0x507400, RegCabac2binsCtl, 0x32C, EncC2_RegCabac2binsCtl, 0x50772c) + FldFunc(EncC2_RegCabac2binsCtl, Int, 11, 1) + FldFunc(EncC2_RegCabac2binsCtl, Busy, 10, 1) + FldFunc(EncC2_RegCabac2binsCtl, Wrnr, 9, 1) + FldFunc(EncC2_RegCabac2binsCtl, Rdnr, 8, 1) + FldFunc(EncC2_RegCabac2binsCtl, Wrmk, 7, 1) + FldFunc(EncC2_RegCabac2binsCtl, Rdmk, 6, 1) + FldFunc(EncC2_RegCabac2binsCtl, Sdpre, 5, 1) + FldFunc(EncC2_RegCabac2binsCtl, Sdq, 4, 1) + FldFunc(EncC2_RegCabac2binsCtl, Sdwr, 3, 1) + FldFunc(EncC2_RegCabac2binsCtl, Sdact, 2, 1) + FldFunc(EncC2_RegCabac2binsCtl, Sdreq, 1, 1) + FldFunc(EncC2_RegCabac2binsCtl, Reset, 0, 1) + +RegAreaFunc(EncCodeOutABase, 0x500E80, 0x500EBF) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffAddr, 0x0, EncCOA_RegCodeOutRdBuffAddr, 0x500e80) + FldFunc(EncCOA_RegCodeOutRdBuffAddr, Addr, 0, 28) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffStartAddr, 0x4, EncCOA_RegCodeOutRdBuffStartAddr, 0x500e84) + FldFunc(EncCOA_RegCodeOutRdBuffStartAddr, Addr, 0, 28) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffEndAddr, 0x8, EncCOA_RegCodeOutRdBuffEndAddr, 0x500e88) + FldFunc(EncCOA_RegCodeOutRdBuffEndAddr, Addr, 0, 28) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffMarkAddr, 0xC, EncCOA_RegCodeOutRdBuffMarkAddr, 0x500e8c) + FldFunc(EncCOA_RegCodeOutRdBuffMarkAddr, Addr, 0, 28) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffCtl, 0x10, EncCOA_RegCodeOutRdBuffCtl, 0x500e90) + FldFunc(EncCOA_RegCodeOutRdBuffCtl, UseMark, 8, 1) + FldFunc(EncCOA_RegCodeOutRdBuffCtl, Id, 4, 4) + FldFunc(EncCOA_RegCodeOutRdBuffCtl, ByteMode, 3, 1) + FldFunc(EncCOA_RegCodeOutRdBuffCtl, WrapEn, 2, 1) + FldFunc(EncCOA_RegCodeOutRdBuffCtl, Init, 1, 1) + FldFunc(EncCOA_RegCodeOutRdBuffCtl, En, 0, 1) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffStallCnt, 0x14, EncCOA_RegCodeOutRdBuffStallCnt, 0x500e94) + FldFunc(EncCOA_RegCodeOutRdBuffStallCnt, Cnt, 0, 32) +RegFunc(EncCodeOutA, 0x500E80, RegCodeOutRdBuffBytesSent, 0x18, EncCOA_RegCodeOutRdBuffBytesSent, 0x500e98) + FldFunc(EncCOA_RegCodeOutRdBuffBytesSent, NumBytes, 0, 32) + +RegAreaFunc(EncCodeOutBBase, 0x500EC0, 0x500EFF) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffAddr, 0x0, EncCOB_RegCodeOutRdBuffAddr, 0x500ec0) + FldFunc(EncCOB_RegCodeOutRdBuffAddr, Addr, 0, 28) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffStartAddr, 0x4, EncCOB_RegCodeOutRdBuffStartAddr, 0x500ec4) + FldFunc(EncCOB_RegCodeOutRdBuffStartAddr, Addr, 0, 28) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffEndAddr, 0x8, EncCOB_RegCodeOutRdBuffEndAddr, 0x500ec8) + FldFunc(EncCOB_RegCodeOutRdBuffEndAddr, Addr, 0, 28) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffMarkAddr, 0xC, EncCOB_RegCodeOutRdBuffMarkAddr, 0x500ecc) + FldFunc(EncCOB_RegCodeOutRdBuffMarkAddr, Addr, 0, 28) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffCtl, 0x10, EncCOB_RegCodeOutRdBuffCtl, 0x500ed0) + FldFunc(EncCOB_RegCodeOutRdBuffCtl, UseMark, 8, 1) + FldFunc(EncCOB_RegCodeOutRdBuffCtl, Id, 4, 4) + FldFunc(EncCOB_RegCodeOutRdBuffCtl, ByteMode, 3, 1) + FldFunc(EncCOB_RegCodeOutRdBuffCtl, WrapEn, 2, 1) + FldFunc(EncCOB_RegCodeOutRdBuffCtl, Init, 1, 1) + FldFunc(EncCOB_RegCodeOutRdBuffCtl, En, 0, 1) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffStallCnt, 0x14, EncCOB_RegCodeOutRdBuffStallCnt, 0x500ed4) + FldFunc(EncCOB_RegCodeOutRdBuffStallCnt, Cnt, 0, 32) +RegFunc(EncCodeOutB, 0x500EC0, RegCodeOutRdBuffBytesSent, 0x18, EncCOB_RegCodeOutRdBuffBytesSent, 0x500ed8) + FldFunc(EncCOB_RegCodeOutRdBuffBytesSent, NumBytes, 0, 32) + +RegAreaFunc(EncMidIndSdramRegsBase, 0x541000, 0x54107F) +RegFunc(EncMidIndSdramRegs, 0x541000, RegSdramInc, 0x0, EncMISRs_RegSdramInc, 0x541000) + FldFunc(EncMISRs_RegSdramInc, Inc, 0, 1) +RegFunc(EncMidIndSdramRegs, 0x541000, RegSdramAddr, 0x4, EncMISRs_RegSdramAddr, 0x541004) + FldFunc(EncMISRs_RegSdramAddr, Addr, 0, 32) +RegFunc(EncMidIndSdramRegs, 0x541000, RegSdramData, 0x8, EncMISRs_RegSdramData, 0x541008) + FldFunc(EncMISRs_RegSdramData, Data, 0, 32) +RegFunc(EncMidIndSdramRegs, 0x541000, RegCpuDbg, 0x10, EncMISRs_RegCpuDbg, 0x541010) + FldFunc(EncMISRs_RegCpuDbg, Hst, 0, 1) + +RegAreaFunc(EncMidCpucoreBase, 0x544000, 0x544FFF) +RegFunc(EncMidCpucore, 0x544000, CpucoreReg, 0x0, EncMCe_CpucoreReg, 0x544000) + FldFunc(EncMCe_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(EncMidCpuauxBase, 0x545000, 0x545FFF) +RegFunc(EncMidCpuaux, 0x545000, CpuauxReg, 0x0, EncMCx_CpuauxReg, 0x545000) + FldFunc(EncMCx_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(EncMidCpuimemBase, 0x546000, 0x547FFF) +RegFunc(EncMidCpuimem, 0x546000, CpuimemReg, 0x0, EncMCm_CpuimemReg, 0x546000) + FldFunc(EncMCm_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(EncMidCpudmemBase, 0x548000, 0x54FFFF) +RegFunc(EncMidCpudmem, 0x548000, CpudmemReg, 0x0, EncMCm_CpudmemReg, 0x548000) + FldFunc(EncMCm_CpudmemReg, Addr, 0, 32) + +RegAreaFunc(EncDctBase, 0x5E0000, 0x5EFFFF) +RegFunc(EncDct, 0x5E0000, DspRegistersUnitExecFlag, 0x0, EncDt_DspRegistersUnitExecFlag, 0x5e0000) + FldFunc(EncDt_DspRegistersUnitExecFlag, UnitExec, 0, 1) +RegFunc(EncDct, 0x5E0000, DspRegistersUnitProgramCounter, 0x4, EncDt_DspRegistersUnitProgramCounter, 0x5e0004) + FldFunc(EncDt_DspRegistersUnitProgramCounter, UnitPc, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersDctBlocksCbp, 0x8, EncDt_DspRegistersDctBlocksCbp, 0x5e0008) + FldFunc(EncDt_DspRegistersDctBlocksCbp, Cbp5, 5, 1) + FldFunc(EncDt_DspRegistersDctBlocksCbp, Cbp4, 4, 1) + FldFunc(EncDt_DspRegistersDctBlocksCbp, Cbp3, 3, 1) + FldFunc(EncDt_DspRegistersDctBlocksCbp, Cbp2, 2, 1) + FldFunc(EncDt_DspRegistersDctBlocksCbp, Cbp1, 1, 1) + FldFunc(EncDt_DspRegistersDctBlocksCbp, Cbp0, 0, 1) +RegFunc(EncDct, 0x5E0000, DspRegistersNumOfDct0Coeff, 0xC, EncDt_DspRegistersNumOfDct0Coeff, 0x5e000c) + FldFunc(EncDt_DspRegistersNumOfDct0Coeff, NumOfCoeff, 0, 7) +RegFunc(EncDct, 0x5E0000, DspRegistersNumOfDct1Coeff, 0x10, EncDt_DspRegistersNumOfDct1Coeff, 0x5e0010) + FldFunc(EncDt_DspRegistersNumOfDct1Coeff, NumOfCoeff, 0, 7) +RegFunc(EncDct, 0x5E0000, DspRegistersNumOfDct2Coeff, 0x14, EncDt_DspRegistersNumOfDct2Coeff, 0x5e0014) + FldFunc(EncDt_DspRegistersNumOfDct2Coeff, NumOfCoeff, 0, 7) +RegFunc(EncDct, 0x5E0000, DspRegistersNumOfDct3Coeff, 0x18, EncDt_DspRegistersNumOfDct3Coeff, 0x5e0018) + FldFunc(EncDt_DspRegistersNumOfDct3Coeff, NumOfCoeff, 0, 7) +RegFunc(EncDct, 0x5E0000, DspRegistersNumOfDct4Coeff, 0x1C, EncDt_DspRegistersNumOfDct4Coeff, 0x5e001c) + FldFunc(EncDt_DspRegistersNumOfDct4Coeff, NumOfCoeff, 0, 7) +RegFunc(EncDct, 0x5E0000, DspRegistersNumOfDct5Coeff, 0x20, EncDt_DspRegistersNumOfDct5Coeff, 0x5e0020) + FldFunc(EncDt_DspRegistersNumOfDct5Coeff, NumOfCoeff, 0, 7) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegbDct0, 0x24, EncDt_DspRegistersSumOfRegbDct0, 0x5e0024) + FldFunc(EncDt_DspRegistersSumOfRegbDct0, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegcDct0, 0x28, EncDt_DspRegistersSumOfRegcDct0, 0x5e0028) + FldFunc(EncDt_DspRegistersSumOfRegcDct0, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegbDct1, 0x2C, EncDt_DspRegistersSumOfRegbDct1, 0x5e002c) + FldFunc(EncDt_DspRegistersSumOfRegbDct1, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegcDct1, 0x30, EncDt_DspRegistersSumOfRegcDct1, 0x5e0030) + FldFunc(EncDt_DspRegistersSumOfRegcDct1, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegbDct2, 0x34, EncDt_DspRegistersSumOfRegbDct2, 0x5e0034) + FldFunc(EncDt_DspRegistersSumOfRegbDct2, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegcDct2, 0x38, EncDt_DspRegistersSumOfRegcDct2, 0x5e0038) + FldFunc(EncDt_DspRegistersSumOfRegcDct2, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegbDct3, 0x3C, EncDt_DspRegistersSumOfRegbDct3, 0x5e003c) + FldFunc(EncDt_DspRegistersSumOfRegbDct3, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegcDct3, 0x40, EncDt_DspRegistersSumOfRegcDct3, 0x5e0040) + FldFunc(EncDt_DspRegistersSumOfRegcDct3, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegbDct4, 0x44, EncDt_DspRegistersSumOfRegbDct4, 0x5e0044) + FldFunc(EncDt_DspRegistersSumOfRegbDct4, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegcDct4, 0x48, EncDt_DspRegistersSumOfRegcDct4, 0x5e0048) + FldFunc(EncDt_DspRegistersSumOfRegcDct4, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegbDct5, 0x4C, EncDt_DspRegistersSumOfRegbDct5, 0x5e004c) + FldFunc(EncDt_DspRegistersSumOfRegbDct5, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersSumOfRegcDct5, 0x50, EncDt_DspRegistersSumOfRegcDct5, 0x5e0050) + FldFunc(EncDt_DspRegistersSumOfRegcDct5, SumOfRegb, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersMinMaxPixelDct0, 0x54, EncDt_DspRegistersMinMaxPixelDct0, 0x5e0054) + FldFunc(EncDt_DspRegistersMinMaxPixelDct0, MinPixel, 9, 9) + FldFunc(EncDt_DspRegistersMinMaxPixelDct0, MaxPixel, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersMinMaxPixelDct1, 0x58, EncDt_DspRegistersMinMaxPixelDct1, 0x5e0058) + FldFunc(EncDt_DspRegistersMinMaxPixelDct1, MinPixel, 9, 9) + FldFunc(EncDt_DspRegistersMinMaxPixelDct1, MaxPixel, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersMinMaxPixelDct2, 0x5C, EncDt_DspRegistersMinMaxPixelDct2, 0x5e005c) + FldFunc(EncDt_DspRegistersMinMaxPixelDct2, MinPixel, 9, 9) + FldFunc(EncDt_DspRegistersMinMaxPixelDct2, MaxPixel, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersMinMaxPixelDct3, 0x60, EncDt_DspRegistersMinMaxPixelDct3, 0x5e0060) + FldFunc(EncDt_DspRegistersMinMaxPixelDct3, MinPixel, 9, 9) + FldFunc(EncDt_DspRegistersMinMaxPixelDct3, MaxPixel, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersMinMaxPixelDct4, 0x64, EncDt_DspRegistersMinMaxPixelDct4, 0x5e0064) + FldFunc(EncDt_DspRegistersMinMaxPixelDct4, MinPixel, 9, 9) + FldFunc(EncDt_DspRegistersMinMaxPixelDct4, MaxPixel, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersMinMaxPixelDct5, 0x68, EncDt_DspRegistersMinMaxPixelDct5, 0x5e0068) + FldFunc(EncDt_DspRegistersMinMaxPixelDct5, MinPixel, 9, 9) + FldFunc(EncDt_DspRegistersMinMaxPixelDct5, MaxPixel, 0, 9) +RegFunc(EncDct, 0x5E0000, DspRegistersRegisterR0, 0x6C, EncDt_DspRegistersRegisterR0, 0x5e006c) + FldFunc(EncDt_DspRegistersRegisterR0, RegR0, 0, 32) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters41, 0x70, EncDt_DspRegistersLoadParameters41, 0x5e0070) + FldFunc(EncDt_DspRegistersLoadParameters41, LoadNextDesc, 24, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, BusTransaction, 18, 6) + FldFunc(EncDt_DspRegistersLoadParameters41, BusWidth, 16, 2) + FldFunc(EncDt_DspRegistersLoadParameters41, Cr, 15, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, Cb, 14, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, ReconInvrData, 13, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, QFlag, 12, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, InvrFlag, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, RFlag, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, CmbFlag, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters41, MemWa, 6, 3) + FldFunc(EncDt_DspRegistersLoadParameters41, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters41, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters42, 0x74, EncDt_DspRegistersLoadParameters42, 0x5e0074) + FldFunc(EncDt_DspRegistersLoadParameters42, LoadNextDesc, 24, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, BusTransaction, 18, 6) + FldFunc(EncDt_DspRegistersLoadParameters42, BusWidth, 16, 2) + FldFunc(EncDt_DspRegistersLoadParameters42, Cr, 15, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, Cb, 14, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, ReconInvrData, 13, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, QFlag, 12, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, InvrFlag, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, RFlag, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, CmbFlag, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters42, MemWa, 6, 3) + FldFunc(EncDt_DspRegistersLoadParameters42, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters42, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters43, 0x78, EncDt_DspRegistersLoadParameters43, 0x5e0078) + FldFunc(EncDt_DspRegistersLoadParameters43, LoadNextDesc, 24, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, BusTransaction, 18, 6) + FldFunc(EncDt_DspRegistersLoadParameters43, BusWidth, 16, 2) + FldFunc(EncDt_DspRegistersLoadParameters43, Cr, 15, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, Cb, 14, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, ReconInvrData, 13, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, QFlag, 12, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, InvrFlag, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, RFlag, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, CmbFlag, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters43, MemWa, 6, 3) + FldFunc(EncDt_DspRegistersLoadParameters43, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters43, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters44, 0x7C, EncDt_DspRegistersLoadParameters44, 0x5e007c) + FldFunc(EncDt_DspRegistersLoadParameters44, LoadNextDesc, 24, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, BusTransaction, 18, 6) + FldFunc(EncDt_DspRegistersLoadParameters44, BusWidth, 16, 2) + FldFunc(EncDt_DspRegistersLoadParameters44, Cr, 15, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, Cb, 14, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, ReconInvrData, 13, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, QFlag, 12, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, InvrFlag, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, RFlag, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, CmbFlag, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters44, MemWa, 6, 3) + FldFunc(EncDt_DspRegistersLoadParameters44, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters44, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters45, 0x80, EncDt_DspRegistersLoadParameters45, 0x5e0080) + FldFunc(EncDt_DspRegistersLoadParameters45, LoadNextDesc, 24, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, BusTransaction, 18, 6) + FldFunc(EncDt_DspRegistersLoadParameters45, BusWidth, 16, 2) + FldFunc(EncDt_DspRegistersLoadParameters45, Cr, 15, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, Cb, 14, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, ReconInvrData, 13, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, QFlag, 12, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, InvrFlag, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, RFlag, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, CmbFlag, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters45, MemWa, 6, 3) + FldFunc(EncDt_DspRegistersLoadParameters45, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters45, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersInterrupt, 0x84, EncDt_DspRegistersInterrupt, 0x5e0084) + FldFunc(EncDt_DspRegistersInterrupt, ErrorMcromAdd, 7, 1) + FldFunc(EncDt_DspRegistersInterrupt, ErrorMcromAck, 6, 1) + FldFunc(EncDt_DspRegistersInterrupt, ErrorCromAdd, 5, 1) + FldFunc(EncDt_DspRegistersInterrupt, ErrorCromAck, 4, 1) + FldFunc(EncDt_DspRegistersInterrupt, ErrorBankAdd, 3, 1) + FldFunc(EncDt_DspRegistersInterrupt, ErrorBankAck, 2, 1) + FldFunc(EncDt_DspRegistersInterrupt, BankError, 1, 1) + FldFunc(EncDt_DspRegistersInterrupt, Exec, 0, 1) +RegFunc(EncDct, 0x5E0000, DspRegistersMaskInterrupt, 0x88, EncDt_DspRegistersMaskInterrupt, 0x5e0088) + FldFunc(EncDt_DspRegistersMaskInterrupt, Mask, 0, 8) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters0, 0x8C, EncDt_DspRegistersLoadParameters0, 0x5e008c) + FldFunc(EncDt_DspRegistersLoadParameters0, ChooseClipPair, 12, 2) + FldFunc(EncDt_DspRegistersLoadParameters0, Clip, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters0, MemWa, 8, 3) + FldFunc(EncDt_DspRegistersLoadParameters0, IncMemRa, 6, 2) + FldFunc(EncDt_DspRegistersLoadParameters0, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters0, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters1, 0x90, EncDt_DspRegistersLoadParameters1, 0x5e0090) + FldFunc(EncDt_DspRegistersLoadParameters1, RegaMux, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters1, IncMemWa, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters1, Field, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters1, CromInc, 8, 1) + FldFunc(EncDt_DspRegistersLoadParameters1, Iquant, 7, 1) + FldFunc(EncDt_DspRegistersLoadParameters1, RoundRegLeftScale, 3, 4) + FldFunc(EncDt_DspRegistersLoadParameters1, ChooseRoundQuartet, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters2, 0x94, EncDt_DspRegistersLoadParameters2, 0x5e0094) + FldFunc(EncDt_DspRegistersLoadParameters2, RegisterType, 10, 2) + FldFunc(EncDt_DspRegistersLoadParameters2, RegisterGroup, 6, 4) + FldFunc(EncDt_DspRegistersLoadParameters2, Load, 4, 2) + FldFunc(EncDt_DspRegistersLoadParameters2, CbpCont, 2, 2) + FldFunc(EncDt_DspRegistersLoadParameters2, Mpeg4, 1, 1) + FldFunc(EncDt_DspRegistersLoadParameters2, Mpeg1, 0, 1) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters3, 0x98, EncDt_DspRegistersLoadParameters3, 0x5e0098) + FldFunc(EncDt_DspRegistersLoadParameters3, MemWa, 1, 6) + FldFunc(EncDt_DspRegistersLoadParameters3, MemRaSel, 0, 1) +RegFunc(EncDct, 0x5E0000, DspRegistersLoadParameters4, 0x9C, EncDt_DspRegistersLoadParameters4, 0x5e009c) + FldFunc(EncDt_DspRegistersLoadParameters4, LoadNextDesc, 24, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, BusTransaction, 18, 6) + FldFunc(EncDt_DspRegistersLoadParameters4, BusWidth, 16, 2) + FldFunc(EncDt_DspRegistersLoadParameters4, Cr, 15, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, Cb, 14, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, ReconInvrData, 13, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, QFlag, 12, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, InvrFlag, 11, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, RFlag, 10, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, CmbFlag, 9, 1) + FldFunc(EncDt_DspRegistersLoadParameters4, MemWa, 6, 3) + FldFunc(EncDt_DspRegistersLoadParameters4, MemRa1, 3, 3) + FldFunc(EncDt_DspRegistersLoadParameters4, MemRa0, 0, 3) +RegFunc(EncDct, 0x5E0000, DspRegistersStartUnitPc, 0xA0, EncDt_DspRegistersStartUnitPc, 0x5e00a0) + FldFunc(EncDt_DspRegistersStartUnitPc, ProgramCounter, 0, 9) +RegFunc(EncDct, 0x5E0000, Bank00Dct0Pixels, 0xC, EncDt_Bank00Dct0Pixels, 0x5e000c) + FldFunc(EncDt_Bank00Dct0Pixels, Data, 0, 20) +RegFunc(EncDct, 0x5E0000, Bank01Dct1Pixels, 0xC, EncDt_Bank01Dct1Pixels, 0x5e000c) + FldFunc(EncDt_Bank01Dct1Pixels, Data, 0, 20) +RegFunc(EncDct, 0x5E0000, Bank10Dct2Pixels, 0xC, EncDt_Bank10Dct2Pixels, 0x5e000c) + FldFunc(EncDt_Bank10Dct2Pixels, Data, 0, 20) +RegFunc(EncDct, 0x5E0000, Bank11Dct3Pixels, 0xC, EncDt_Bank11Dct3Pixels, 0x5e000c) + FldFunc(EncDt_Bank11Dct3Pixels, Data, 0, 20) +RegFunc(EncDct, 0x5E0000, Bank20Dct4Pixels, 0xC, EncDt_Bank20Dct4Pixels, 0x5e000c) + FldFunc(EncDt_Bank20Dct4Pixels, Data, 0, 20) +RegFunc(EncDct, 0x5E0000, Bank21Dct5Pixels, 0xC, EncDt_Bank21Dct5Pixels, 0x5e000c) + FldFunc(EncDt_Bank21Dct5Pixels, Data, 0, 20) +RegFunc(EncDct, 0x5E0000, DspMcromMicrocode, 0xC, EncDt_DspMcromMicrocode, 0x5e000c) + FldFunc(EncDt_DspMcromMicrocode, Data, 0, 32) +RegFunc(EncDct, 0x5E0000, DspCromVariables, 0xC, EncDt_DspCromVariables, 0x5e000c) + FldFunc(EncDt_DspCromVariables, Data, 0, 20) + +#endif + + +//****************************************************************************** +// +// Encoder FME Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_ENCODER_FME + +RegAreaFunc(EncFmeRbnodeRegsBase, 0x600000, 0x60007F) +RegFunc(EncFmeRbnodeRegs, 0x600000, RbConfig , 0x0, EncFRRs_RbConfig , 0x600000) + FldFunc(EncFRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(EncFRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(EncFmeRbnodeRegs, 0x600000, RbStickyError, 0x4, EncFRRs_RbStickyError, 0x600004) + FldFunc(EncFRRs_RbStickyError, Node, 1, 1) + FldFunc(EncFRRs_RbStickyError, Tgt, 0, 1) +RegFunc(EncFmeRbnodeRegs, 0x600000, RbCurrentError, 0x8, EncFRRs_RbCurrentError, 0x600008) + FldFunc(EncFRRs_RbCurrentError, Node, 1, 1) + FldFunc(EncFRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(EncFmeRbnodeRegs, 0x600000, RbReadData, 0xC, EncFRRs_RbReadData, 0x60000c) + FldFunc(EncFRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(EncFmeRingbusDebugRegsBase, 0x600080, 0x6000FF) +RegFunc(EncFmeRingbusDebugRegs, 0x600080, RbDebugConfig, 0x0, EncFRDRs_RbDebugConfig, 0x600080) + FldFunc(EncFRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(EncFRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(EncFmeRingbusDebugRegs, 0x600080, RbDebugReg0Addr, 0x4, EncFRDRs_RbDebugReg0Addr, 0x600084) + FldFunc(EncFRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(EncFmeRingbusDebugRegs, 0x600080, RbDebugReg1Addr, 0x8, EncFRDRs_RbDebugReg1Addr, 0x600088) + FldFunc(EncFRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(EncFmeRingbusDebugRegs, 0x600080, RbDebugReg2Addr, 0xC, EncFRDRs_RbDebugReg2Addr, 0x60008c) + FldFunc(EncFRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(EncFmeRingbusDebugRegs, 0x600080, RbDebugReg3Addr, 0x10, EncFRDRs_RbDebugReg3Addr, 0x600090) + FldFunc(EncFRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(EncFmeRingbusDebugRegs, 0x600080, RbDebugOutputReg, 0x14, EncFRDRs_RbDebugOutputReg, 0x600094) + FldFunc(EncFRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(EncFRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +#if 1 // New fme +RegFunc( a,b,c,d, REGOFFSET_FMEVECTOR_L0_0, 0x600430 ) // 16x16 mode vec for fme vec context +RegFunc( a,b,c,d, REGOFFSET_MVPAUTOCTL, 0x600568 ) // trigger auto (try all partititions, return single best) + FldFunc(REGOFFSET_MVPAUTOCTL, EnableSubmodes, 4, 1) // Allow subpartitions of 8x8 partitions. + FldFunc(REGOFFSET_MVPAUTOCTL, l11, 3, 1) + FldFunc(REGOFFSET_MVPAUTOCTL, l10, 2, 1) + FldFunc(REGOFFSET_MVPAUTOCTL, l01, 1, 1) + FldFunc(REGOFFSET_MVPAUTOCTL, l00, 0, 1) // Do list 0, ref 0 (only one used currently) +RegFunc( a,b,c,d, REGOFFSET_MVPAUTORESULT, 0x60056C ) + FldFunc(REGOFFSET_MVPAUTORESULT, busy ,31, 1) + FldFunc(REGOFFSET_MVPAUTORESULT, rsv ,18, 13) + FldFunc(REGOFFSET_MVPAUTORESULT, bestmode ,16, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestsubmode11,14, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestsubmode10,12, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestsubmode01,10, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestsubmode00, 8, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestsubmode , 8, 8) + FldFunc(REGOFFSET_MVPAUTORESULT, bestlistref11, 6, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestlistref10, 4, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestlistref01, 2, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestlistref00, 0, 2) + FldFunc(REGOFFSET_MVPAUTORESULT, bestlistref , 0, 8) + +RegFunc( a,b,c,d, REGOFFSET_MVPAUTOIDXCOST_00, 0x600570 ) +RegFunc( a,b,c,d, REGOFFSET_MVPAUTOSUBMODECOST_0_00, 0x600580 ) +RegFunc( a,b,c,d, REGOFFSET_MVPAUTOSUBMODECOST_0_01, 0x600584 ) +RegFunc( a,b,c,d, REGOFFSET_MVPAUTOSUBMODECOST_0_10, 0x600588 ) +RegFunc( a,b,c,d, REGOFFSET_MVPAUTOSUBMODECOST_0_11, 0x60058C ) +#endif + +RegAreaFunc(EncFmeMainBase, 0x600400, 0x6004FF) +RegFunc(EncFmeMain, 0x600400, EncFmeCtl, 0x0, EncFMn_EncFmeCtl, 0x600400) + FldFunc(EncFMn_EncFmeCtl, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeCur, 0x4, EncFMn_EncFmeCur, 0x600404) + FldFunc(EncFMn_EncFmeCur, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeRefindex, 0x8, EncFMn_EncFmeRefindex, 0x600408) + FldFunc(EncFMn_EncFmeRefindex, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeRefvector, 0xC, EncFMn_EncFmeRefvector, 0x60040c) + FldFunc(EncFMn_EncFmeRefvector, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeMvpa, 0x10, EncFMn_EncFmeMvpa, 0x600410) + FldFunc(EncFMn_EncFmeMvpa, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeMvpb, 0x14, EncFMn_EncFmeMvpb, 0x600414) + FldFunc(EncFMn_EncFmeMvpb, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeMvpc, 0x18, EncFMn_EncFmeMvpc, 0x600418) + FldFunc(EncFMn_EncFmeMvpc, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeLambda, 0x1C, EncFMn_EncFmeLambda, 0x60041c) + FldFunc(EncFMn_EncFmeLambda, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeImgsize, 0x20, EncFMn_EncFmeImgsize, 0x600420) + FldFunc(EncFMn_EncFmeImgsize, NoInfo, 0, 32) +RegFunc(EncFmeMain, 0x600400, EncFmeSearchsize, 0x24, EncFMn_EncFmeSearchsize, 0x600424) + FldFunc(EncFMn_EncFmeSearchsize, NoInfo, 0, 32) /* By analogy with the above: note "size" is not capitalized */ +RegFunc(EncFmeMain, 0x600400, EncFmeStatus, 0x28, EncFMn_EncFmeStatus, 0x600428) + FldFunc(EncFMn_EncFmeStatus, NoInfo, 0, 32) + + + +RegAreaFunc(EncFmeMvpBase, 0x600500, 0x6005FF) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpArefindex, 0x0, EncFMp_EncFmeMvpArefindex, 0x600500) + FldFunc(EncFMp_EncFmeMvpArefindex, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta00, 0x4, EncFMp_EncFmeMvpVecta00, 0x600504) + FldFunc(EncFMp_EncFmeMvpVecta00, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta01, 0x8, EncFMp_EncFmeMvpVecta01, 0x600508) + FldFunc(EncFMp_EncFmeMvpVecta01, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta10, 0xC, EncFMp_EncFmeMvpVecta10, 0x60050c) + FldFunc(EncFMp_EncFmeMvpVecta10, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta11, 0x10, EncFMp_EncFmeMvpVecta11, 0x600510) + FldFunc(EncFMp_EncFmeMvpVecta11, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta20, 0x14, EncFMp_EncFmeMvpVecta20, 0x600514) + FldFunc(EncFMp_EncFmeMvpVecta20, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta21, 0x18, EncFMp_EncFmeMvpVecta21, 0x600518) + FldFunc(EncFMp_EncFmeMvpVecta21, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta30, 0x1C, EncFMp_EncFmeMvpVecta30, 0x60051c) + FldFunc(EncFMp_EncFmeMvpVecta30, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVecta31, 0x20, EncFMp_EncFmeMvpVecta31, 0x600520) + FldFunc(EncFMp_EncFmeMvpVecta31, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpBrefindex, 0x24, EncFMp_EncFmeMvpBrefindex, 0x600524) + FldFunc(EncFMp_EncFmeMvpBrefindex, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb00, 0x28, EncFMp_EncFmeMvpVectb00, 0x600528) + FldFunc(EncFMp_EncFmeMvpVectb00, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb01, 0x2C, EncFMp_EncFmeMvpVectb01, 0x60052c) + FldFunc(EncFMp_EncFmeMvpVectb01, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb10, 0x30, EncFMp_EncFmeMvpVectb10, 0x600530) + FldFunc(EncFMp_EncFmeMvpVectb10, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb11, 0x34, EncFMp_EncFmeMvpVectb11, 0x600534) + FldFunc(EncFMp_EncFmeMvpVectb11, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb20, 0x38, EncFMp_EncFmeMvpVectb20, 0x600538) + FldFunc(EncFMp_EncFmeMvpVectb20, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb21, 0x3C, EncFMp_EncFmeMvpVectb21, 0x60053c) + FldFunc(EncFMp_EncFmeMvpVectb21, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb30, 0x40, EncFMp_EncFmeMvpVectb30, 0x600540) + FldFunc(EncFMp_EncFmeMvpVectb30, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectb31, 0x44, EncFMp_EncFmeMvpVectb31, 0x600544) + FldFunc(EncFMp_EncFmeMvpVectb31, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpCrefindex, 0x48, EncFMp_EncFmeMvpCrefindex, 0x600548) + FldFunc(EncFMp_EncFmeMvpCrefindex, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectc00, 0x4C, EncFMp_EncFmeMvpVectc00, 0x60054c) + FldFunc(EncFMp_EncFmeMvpVectc00, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpVectc01, 0x50, EncFMp_EncFmeMvpVectc01, 0x600550) + FldFunc(EncFMp_EncFmeMvpVectc01, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpMode, 0x54, EncFMp_EncFmeMvpMode, 0x600554) + FldFunc(EncFMp_EncFmeMvpMode, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpCurpar, 0x58, EncFMp_EncFmeMvpCurpar, 0x600558) + FldFunc(EncFMp_EncFmeMvpCurpar, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpMvp, 0x5C, EncFMp_EncFmeMvpMvp, 0x60055c) + FldFunc(EncFMp_EncFmeMvpMvp, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpMvd, 0x60, EncFMp_EncFmeMvpMvd, 0x600560) + FldFunc(EncFMp_EncFmeMvpMvd, NoInfo, 0, 32) +RegFunc(EncFmeMvp, 0x600500, EncFmeMvpCost, 0x64, EncFMp_EncFmeMvpCost, 0x600564) + FldFunc(EncFMp_EncFmeMvpCost, NoInfo, 0, 32) + +RegAreaFunc(EncFmeMebBase, 0x600600, 0x6006FF) + +RegAreaFunc(EncVmeVectbaseBase, 0x600800, 0x600BFF) + +RegAreaFunc(EncFmeCpuregsBase, 0x600F00, 0x600F7F) +RegFunc(EncFmeCpuregs, 0x600F00, RegHst2cpuMbx, 0x0, EncFCs_RegHst2cpuMbx, 0x600f00) + FldFunc(EncFCs_RegHst2cpuMbx, Value, 0, 32) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpu2hstMbx, 0x4, EncFCs_RegCpu2hstMbx, 0x600f04) + FldFunc(EncFCs_RegCpu2hstMbx, Value, 0, 32) +RegFunc(EncFmeCpuregs, 0x600F00, RegMbxStat, 0x8, EncFCs_RegMbxStat, 0x600f08) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIntBase, 0xC, EncFCs_RegCpuIntBase, 0x600f0c) + FldFunc(EncFCs_RegCpuIntBase, Addr, 8, 24) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIntEna, 0x10, EncFCs_RegCpuIntEna, 0x600f10) + FldFunc(EncFCs_RegCpuIntEna, Mbx, 31, 1) + FldFunc(EncFCs_RegCpuIntEna, Com7, 23, 1) + FldFunc(EncFCs_RegCpuIntEna, Com6, 22, 1) + FldFunc(EncFCs_RegCpuIntEna, Com5, 21, 1) + FldFunc(EncFCs_RegCpuIntEna, Com4, 20, 1) + FldFunc(EncFCs_RegCpuIntEna, Com3, 19, 1) + FldFunc(EncFCs_RegCpuIntEna, Com2, 18, 1) + FldFunc(EncFCs_RegCpuIntEna, Com1, 17, 1) + FldFunc(EncFCs_RegCpuIntEna, Com0, 16, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw7, 15, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw6, 14, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw5, 13, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw4, 12, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw3, 11, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw2, 10, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw1, 9, 1) + FldFunc(EncFCs_RegCpuIntEna, Hw0, 8, 1) + FldFunc(EncFCs_RegCpuIntEna, Db7, 7, 1) + FldFunc(EncFCs_RegCpuIntEna, Db6, 6, 1) + FldFunc(EncFCs_RegCpuIntEna, Db5, 5, 1) + FldFunc(EncFCs_RegCpuIntEna, Db4, 4, 1) + FldFunc(EncFCs_RegCpuIntEna, Db3, 3, 1) + FldFunc(EncFCs_RegCpuIntEna, Db2, 2, 1) + FldFunc(EncFCs_RegCpuIntEna, Db1, 1, 1) + FldFunc(EncFCs_RegCpuIntEna, Db0, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, StreamCpuIntEna, 0x10, EncFCs_StreamCpuIntEna, 0x600f10) + FldFunc(EncFCs_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(EncFCs_StreamCpuIntEna, Dec, 18, 1) + FldFunc(EncFCs_StreamCpuIntEna, Aud, 17, 1) + FldFunc(EncFCs_StreamCpuIntEna, M2m, 15, 1) + FldFunc(EncFCs_StreamCpuIntEna, Pci, 14, 1) + FldFunc(EncFCs_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(EncFCs_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(EncFCs_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(EncFCs_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(EncFCs_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(EncFCs_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(EncFCs_StreamCpuIntEna, Rb, 1, 1) + FldFunc(EncFCs_StreamCpuIntEna, Sd, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, Dec0CpuIntEna, 0x10, EncFCs_Dec0CpuIntEna, 0x600f10) + FldFunc(EncFCs_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(EncFCs_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(EncFCs_Dec0CpuIntEna, Si, 8, 1) + FldFunc(EncFCs_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(EncFCs_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, Dec1CpuIntEna, 0x10, EncFCs_Dec1CpuIntEna, 0x600f10) + FldFunc(EncFCs_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(EncFCs_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(EncFCs_Dec1CpuIntEna, Si, 8, 1) + FldFunc(EncFCs_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(EncFCs_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIntStat, 0x14, EncFCs_RegCpuIntStat, 0x600f14) + FldFunc(EncFCs_RegCpuIntStat, Mbx, 31, 1) + FldFunc(EncFCs_RegCpuIntStat, Com7, 23, 1) + FldFunc(EncFCs_RegCpuIntStat, Com6, 22, 1) + FldFunc(EncFCs_RegCpuIntStat, Com5, 21, 1) + FldFunc(EncFCs_RegCpuIntStat, Com4, 20, 1) + FldFunc(EncFCs_RegCpuIntStat, Com3, 19, 1) + FldFunc(EncFCs_RegCpuIntStat, Com2, 18, 1) + FldFunc(EncFCs_RegCpuIntStat, Com1, 17, 1) + FldFunc(EncFCs_RegCpuIntStat, Com0, 16, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw7, 15, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw6, 14, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw5, 13, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw4, 12, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw3, 11, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw2, 10, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw1, 9, 1) + FldFunc(EncFCs_RegCpuIntStat, Hw0, 8, 1) + FldFunc(EncFCs_RegCpuIntStat, Db7, 7, 1) + FldFunc(EncFCs_RegCpuIntStat, Db6, 6, 1) + FldFunc(EncFCs_RegCpuIntStat, Db5, 5, 1) + FldFunc(EncFCs_RegCpuIntStat, Db4, 4, 1) + FldFunc(EncFCs_RegCpuIntStat, Db3, 3, 1) + FldFunc(EncFCs_RegCpuIntStat, Db2, 2, 1) + FldFunc(EncFCs_RegCpuIntStat, Db1, 1, 1) + FldFunc(EncFCs_RegCpuIntStat, Db0, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, StreamCpuIntStat, 0x14, EncFCs_StreamCpuIntStat, 0x600f14) + FldFunc(EncFCs_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(EncFCs_StreamCpuIntStat, Dec, 18, 1) + FldFunc(EncFCs_StreamCpuIntStat, Aud, 17, 1) + FldFunc(EncFCs_StreamCpuIntStat, M2m, 15, 1) + FldFunc(EncFCs_StreamCpuIntStat, Pci, 14, 1) + FldFunc(EncFCs_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(EncFCs_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(EncFCs_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(EncFCs_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(EncFCs_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(EncFCs_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(EncFCs_StreamCpuIntStat, Rb, 1, 1) + FldFunc(EncFCs_StreamCpuIntStat, Sd, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, Dec0CpuIntStat, 0x14, EncFCs_Dec0CpuIntStat, 0x600f14) + FldFunc(EncFCs_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(EncFCs_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(EncFCs_Dec0CpuIntStat, Si, 8, 1) + FldFunc(EncFCs_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(EncFCs_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, Dec1CpuIntStat, 0x14, EncFCs_Dec1CpuIntStat, 0x600f14) + FldFunc(EncFCs_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(EncFCs_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(EncFCs_Dec1CpuIntStat, Si, 8, 1) + FldFunc(EncFCs_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(EncFCs_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, RegHst2cpuStat, 0x18, EncFCs_RegHst2cpuStat, 0x600f18) + FldFunc(EncFCs_RegHst2cpuStat, Value, 0, 32) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpu2hstStat, 0x1C, EncFCs_RegCpu2hstStat, 0x600f1c) + FldFunc(EncFCs_RegCpu2hstStat, Value, 0, 32) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIntgenSet, 0x20, EncFCs_RegCpuIntgenSet, 0x600f20) + FldFunc(EncFCs_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(EncFCs_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIntgenClr, 0x24, EncFCs_RegCpuIntgenClr, 0x600f24) + FldFunc(EncFCs_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(EncFCs_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIcacheMiss, 0x28, EncFCs_RegCpuIcacheMiss, 0x600f28) + FldFunc(EncFCs_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(EncFmeCpuregs, 0x600F00, RegCpuIntgenMask, 0x2C, EncFCs_RegCpuIntgenMask, 0x600f2c) + FldFunc(EncFCs_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(EncFCs_RegCpuIntgenMask, Int0, 0, 1) + +RegAreaFunc(EncFmeCpudmaBase, 0x601800, 0x6018FF) +RegFunc(EncFmeCpudma, 0x601800, RegDma0SdAddr, 0x0, EncFCa_RegDma0SdAddr, 0x601800) + FldFunc(EncFCa_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(EncFmeCpudma, 0x601800, RegDma0LclAddr, 0x4, EncFCa_RegDma0LclAddr, 0x601804) + FldFunc(EncFCa_RegDma0LclAddr, Addr, 2, 7) +RegFunc(EncFmeCpudma, 0x601800, RegDma0Len, 0x8, EncFCa_RegDma0Len, 0x601808) + FldFunc(EncFCa_RegDma0Len, Length, 2, 8) +RegFunc(EncFmeCpudma, 0x601800, RegDma1SdAddr, 0x10, EncFCa_RegDma1SdAddr, 0x601810) + FldFunc(EncFCa_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(EncFmeCpudma, 0x601800, RegDma1LclAddr, 0x14, EncFCa_RegDma1LclAddr, 0x601814) + FldFunc(EncFCa_RegDma1LclAddr, Addr, 2, 7) +RegFunc(EncFmeCpudma, 0x601800, RegDma1Len, 0x18, EncFCa_RegDma1Len, 0x601818) + FldFunc(EncFCa_RegDma1Len, Length, 2, 8) +RegFunc(EncFmeCpudma, 0x601800, RegDma2SdAddr, 0x20, EncFCa_RegDma2SdAddr, 0x601820) + FldFunc(EncFCa_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(EncFmeCpudma, 0x601800, RegDma2LclAddr, 0x24, EncFCa_RegDma2LclAddr, 0x601824) + FldFunc(EncFCa_RegDma2LclAddr, Addr, 2, 7) +RegFunc(EncFmeCpudma, 0x601800, RegDma2Len, 0x28, EncFCa_RegDma2Len, 0x601828) + FldFunc(EncFCa_RegDma2Len, Length, 2, 8) +RegFunc(EncFmeCpudma, 0x601800, RegDma3SdAddr, 0x30, EncFCa_RegDma3SdAddr, 0x601830) + FldFunc(EncFCa_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(EncFmeCpudma, 0x601800, RegDma3LclAddr, 0x34, EncFCa_RegDma3LclAddr, 0x601834) + FldFunc(EncFCa_RegDma3LclAddr, Addr, 2, 7) +RegFunc(EncFmeCpudma, 0x601800, RegDma3Len, 0x38, EncFCa_RegDma3Len, 0x601838) + FldFunc(EncFCa_RegDma3Len, Length, 2, 8) +RegFunc(EncFmeCpudma, 0x601800, RegDmaStatus, 0x40, EncFCa_RegDmaStatus, 0x601840) + FldFunc(EncFCa_RegDmaStatus, Act3, 3, 1) + FldFunc(EncFCa_RegDmaStatus, Act2, 2, 1) + FldFunc(EncFCa_RegDmaStatus, Act1, 1, 1) + FldFunc(EncFCa_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(EncFmeDmamemBase, 0x601A00, 0x6021FF) +RegFunc(EncFmeDmamem, 0x601A00, DmaMem, 0x0, EncFDm_DmaMem, 0x601a00) + FldFunc(EncFDm_DmaMem, Data, 0, 32) + +RegAreaFunc(EncFmeIndSdramRegsBase, 0x641000, 0x64107F) +RegFunc(EncFmeIndSdramRegs, 0x641000, RegSdramInc, 0x0, EncFISRs_RegSdramInc, 0x641000) + FldFunc(EncFISRs_RegSdramInc, Inc, 0, 1) +RegFunc(EncFmeIndSdramRegs, 0x641000, RegSdramAddr, 0x4, EncFISRs_RegSdramAddr, 0x641004) + FldFunc(EncFISRs_RegSdramAddr, Addr, 0, 32) +RegFunc(EncFmeIndSdramRegs, 0x641000, RegSdramData, 0x8, EncFISRs_RegSdramData, 0x641008) + FldFunc(EncFISRs_RegSdramData, Data, 0, 32) +RegFunc(EncFmeIndSdramRegs, 0x641000, RegCpuDbg, 0x10, EncFISRs_RegCpuDbg, 0x641010) + FldFunc(EncFISRs_RegCpuDbg, Hst, 0, 1) + +RegAreaFunc(EncFmeCpucoreBase, 0x644000, 0x644FFF) +RegFunc(EncFmeCpucore, 0x644000, CpucoreReg, 0x0, EncFCe_CpucoreReg, 0x644000) + FldFunc(EncFCe_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(EncFmeCpuauxBase, 0x645000, 0x645FFF) +RegFunc(EncFmeCpuaux, 0x645000, CpuauxReg, 0x0, EncFCx_CpuauxReg, 0x645000) + FldFunc(EncFCx_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(EncFmeCpuimemBase, 0x646000, 0x647FFF) +RegFunc(EncFmeCpuimem, 0x646000, CpuimemReg, 0x0, EncFCm_CpuimemReg, 0x646000) + FldFunc(EncFCm_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(EncFmeCpudmemBase, 0x648000, 0x64FFFF) +RegFunc(EncFmeCpudmem, 0x648000, CpudmemReg, 0x0, EncFCm_CpudmemReg, 0x648000) + FldFunc(EncFCm_CpudmemReg, Addr, 0, 32) + +#endif + + +//****************************************************************************** +// +// PostProc Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_POSTPROC + +RegAreaFunc(PostProcRegsBase, 0x700000, 0x70007F) +RegFunc(PostProcRegs, 0x700000, RbConfig , 0x0, PosPRs_RbConfig , 0x700000) + FldFunc(PosPRs_RbConfig , RdPostEna, 1, 1) + FldFunc(PosPRs_RbConfig , RdBypEna, 0, 1) +RegFunc(PostProcRegs, 0x700000, RbStickyError, 0x4, PosPRs_RbStickyError, 0x700004) + FldFunc(PosPRs_RbStickyError, Node, 1, 1) + FldFunc(PosPRs_RbStickyError, Tgt, 0, 1) +RegFunc(PostProcRegs, 0x700000, RbCurrentError, 0x8, PosPRs_RbCurrentError, 0x700008) + FldFunc(PosPRs_RbCurrentError, Node, 1, 1) + FldFunc(PosPRs_RbCurrentError, Tgt, 0, 1) +RegFunc(PostProcRegs, 0x700000, RbReadData, 0xC, PosPRs_RbReadData, 0x70000c) + FldFunc(PosPRs_RbReadData, Data, 0, 32) + +RegAreaFunc(PostProcRingbusDebugRegsBase, 0x700080, 0x7000FF) +RegFunc(PostProcRingbusDebugRegs, 0x700080, RbDebugConfig, 0x0, PosPRDRs_RbDebugConfig, 0x700080) + FldFunc(PosPRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(PosPRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(PostProcRingbusDebugRegs, 0x700080, RbDebugReg0Addr, 0x4, PosPRDRs_RbDebugReg0Addr, 0x700084) + FldFunc(PosPRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(PostProcRingbusDebugRegs, 0x700080, RbDebugReg1Addr, 0x8, PosPRDRs_RbDebugReg1Addr, 0x700088) + FldFunc(PosPRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(PostProcRingbusDebugRegs, 0x700080, RbDebugReg2Addr, 0xC, PosPRDRs_RbDebugReg2Addr, 0x70008c) + FldFunc(PosPRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(PostProcRingbusDebugRegs, 0x700080, RbDebugReg3Addr, 0x10, PosPRDRs_RbDebugReg3Addr, 0x700090) + FldFunc(PosPRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(PostProcRingbusDebugRegs, 0x700080, RbDebugOutputReg, 0x14, PosPRDRs_RbDebugOutputReg, 0x700094) + FldFunc(PosPRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(PosPRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(DecodeFgtBase, 0x700600, 0x7007FF) +RegFunc(DecodeFgt, 0x700600, RegFgInorg, 0x0, DecFt_RegFgInorg, 0x700600) + FldFunc(DecFt_RegFgInorg, StartLinNum, 16, 11) + FldFunc(DecFt_RegFgInorg, StartPixNum, 0, 11) +RegFunc(DecodeFgt, 0x700600, RegFgInsize, 0x4, DecFt_RegFgInsize, 0x700604) + FldFunc(DecFt_RegFgInsize, NumLines, 16, 11) + FldFunc(DecFt_RegFgInsize, NumPix, 0, 11) +RegFunc(DecodeFgt, 0x700600, RegFgCtl, 0x8, DecFt_RegFgCtl, 0x700608) + FldFunc(DecFt_RegFgCtl, WritePicid, 16, 8) + FldFunc(DecFt_RegFgCtl, ReadPicid, 8, 8) + FldFunc(DecFt_RegFgCtl, Wrbot1top0, 6, 1) + FldFunc(DecFt_RegFgCtl, Wrfield1frame0, 5, 1) + FldFunc(DecFt_RegFgCtl, Rdbot1top0, 4, 1) + FldFunc(DecFt_RegFgCtl, Rdfield1frame0, 3, 1) + FldFunc(DecFt_RegFgCtl, Reset, 2, 1) + FldFunc(DecFt_RegFgCtl, DisWb, 1, 1) + FldFunc(DecFt_RegFgCtl, Load, 0, 1) +RegFunc(DecodeFgt, 0x700600, RegFgStart, 0xC, DecFt_RegFgStart, 0x70060c) + FldFunc(DecFt_RegFgStart, Start, 0, 1) +RegFunc(DecodeFgt, 0x700600, RegFgInsei, 0x10, DecFt_RegFgInsei, 0x700610) + FldFunc(DecFt_RegFgInsei, DbOffset, 8, 10) + FldFunc(DecFt_RegFgInsei, Newsei, 4, 1) + FldFunc(DecFt_RegFgInsei, Shift, 0, 4) +RegFunc(DecodeFgt, 0x700600, RegFgInyseed, 0x14, DecFt_RegFgInyseed, 0x700614) + FldFunc(DecFt_RegFgInyseed, Seed, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgInuseed, 0x18, DecFt_RegFgInuseed, 0x700618) + FldFunc(DecFt_RegFgInuseed, Seed, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgInvseed, 0x1C, DecFt_RegFgInvseed, 0x70061c) + FldFunc(DecFt_RegFgInvseed, Seed, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgInylut, 0x20, DecFt_RegFgInylut, 0x700620) + FldFunc(DecFt_RegFgInylut, LutAddr, 24, 7) + FldFunc(DecFt_RegFgInylut, BaVal1, 20, 4) + FldFunc(DecFt_RegFgInylut, CompModelVal1, 12, 8) + FldFunc(DecFt_RegFgInylut, BaVal0, 8, 4) + FldFunc(DecFt_RegFgInylut, CompModelVal0, 0, 8) +RegFunc(DecodeFgt, 0x700600, RegFgInulut, 0x24, DecFt_RegFgInulut, 0x700624) + FldFunc(DecFt_RegFgInulut, LutAddr, 24, 7) + FldFunc(DecFt_RegFgInulut, BaVal1, 20, 4) + FldFunc(DecFt_RegFgInulut, CompModelVal1, 12, 8) + FldFunc(DecFt_RegFgInulut, BaVal0, 8, 4) + FldFunc(DecFt_RegFgInulut, CompModelVal0, 0, 8) +RegFunc(DecodeFgt, 0x700600, RegFgInvlut, 0x28, DecFt_RegFgInvlut, 0x700628) + FldFunc(DecFt_RegFgInvlut, LutAddr, 24, 7) + FldFunc(DecFt_RegFgInvlut, BaVal1, 20, 4) + FldFunc(DecFt_RegFgInvlut, CompModelVal1, 12, 8) + FldFunc(DecFt_RegFgInvlut, BaVal0, 8, 4) + FldFunc(DecFt_RegFgInvlut, CompModelVal0, 0, 8) +RegFunc(DecodeFgt, 0x700600, RegFgInlutRaddr, 0x2C, DecFt_RegFgInlutRaddr, 0x70062c) + FldFunc(DecFt_RegFgInlutRaddr, VlutRdAddr, 16, 7) + FldFunc(DecFt_RegFgInlutRaddr, UlutRdAddr, 8, 7) + FldFunc(DecFt_RegFgInlutRaddr, YlutRdAddr, 0, 7) +RegFunc(DecodeFgt, 0x700600, RegFgIncache1, 0x30, DecFt_RegFgIncache1, 0x700630) + FldFunc(DecFt_RegFgIncache1, PatVal3, 24, 8) + FldFunc(DecFt_RegFgIncache1, PatVal2, 16, 8) + FldFunc(DecFt_RegFgIncache1, PatVal1, 8, 8) + FldFunc(DecFt_RegFgIncache1, PatVal0, 0, 8) +RegFunc(DecodeFgt, 0x700600, RegFgIncache2, 0x34, DecFt_RegFgIncache2, 0x700634) + FldFunc(DecFt_RegFgIncache2, PatVal3, 24, 8) + FldFunc(DecFt_RegFgIncache2, PatVal2, 16, 8) + FldFunc(DecFt_RegFgIncache2, PatVal1, 8, 8) + FldFunc(DecFt_RegFgIncache2, PatVal0, 0, 8) +RegFunc(DecodeFgt, 0x700600, RegFgIncache3, 0x38, DecFt_RegFgIncache3, 0x700638) + FldFunc(DecFt_RegFgIncache3, PatVal1, 8, 8) + FldFunc(DecFt_RegFgIncache3, PatVal0, 0, 8) +RegFunc(DecodeFgt, 0x700600, RegFgInbase, 0x3C, DecFt_RegFgInbase, 0x70063c) + FldFunc(DecFt_RegFgInbase, Addr, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgInal, 0x40, DecFt_RegFgInal, 0x700640) + FldFunc(DecFt_RegFgInal, NumLuma, 0, 11) +RegFunc(DecodeFgt, 0x700600, RegFgMint, 0x44, DecFt_RegFgMint, 0x700644) + FldFunc(DecFt_RegFgMint, FgAlmostDoneMask, 1, 1) + FldFunc(DecFt_RegFgMint, FgMask, 0, 1) +RegFunc(DecodeFgt, 0x700600, RegFgOycrc, 0x48, DecFt_RegFgOycrc, 0x700648) + FldFunc(DecFt_RegFgOycrc, Crc, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgOucrc, 0x4C, DecFt_RegFgOucrc, 0x70064c) + FldFunc(DecFt_RegFgOucrc, Crc, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgOvcrc, 0x50, DecFt_RegFgOvcrc, 0x700650) + FldFunc(DecFt_RegFgOvcrc, Crc, 0, 32) +RegFunc(DecodeFgt, 0x700600, RegFgStatus, 0x54, DecFt_RegFgStatus, 0x700654) + FldFunc(DecFt_RegFgStatus, Id, 28, 4) + FldFunc(DecFt_RegFgStatus, WrBusy, 8, 1) + FldFunc(DecFt_RegFgStatus, DblkBusy, 7, 1) + FldFunc(DecFt_RegFgStatus, CompBusy, 6, 1) + FldFunc(DecFt_RegFgStatus, BagBusy, 5, 1) + FldFunc(DecFt_RegFgStatus, DmaBusy, 4, 1) + FldFunc(DecFt_RegFgStatus, HwBusy, 3, 1) + FldFunc(DecFt_RegFgStatus, ResetActive, 2, 1) + FldFunc(DecFt_RegFgStatus, WrDone, 1, 1) + FldFunc(DecFt_RegFgStatus, Done, 0, 1) + +RegAreaFunc(DecodeVoutaBase, 0x700800, 0x70087F) +RegFunc(DecodeVouta, 0x700800, RegVppCtl, 0x0, DecVa_RegVppCtl, 0x700800) + FldFunc(DecVa_RegVppCtl, Start, 31, 1) + FldFunc(DecVa_RegVppCtl, Loop, 30, 1) + FldFunc(DecVa_RegVppCtl, Rst, 29, 1) + FldFunc(DecVa_RegVppCtl, Vifrst, 28, 1) + FldFunc(DecVa_RegVppCtl, DiagLoad, 27, 1) + FldFunc(DecVa_RegVppCtl, Outfield, 19, 1) + FldFunc(DecVa_RegVppCtl, Outbot, 18, 1) + FldFunc(DecVa_RegVppCtl, Field, 17, 1) + FldFunc(DecVa_RegVppCtl, Bot, 16, 1) + FldFunc(DecVa_RegVppCtl, OppPicid, 8, 8) + FldFunc(DecVa_RegVppCtl, RefPicid, 0, 8) +RegFunc(DecodeVouta, 0x700800, RegVppMode, 0x4, DecVa_RegVppMode, 0x700804) + FldFunc(DecVa_RegVppMode, CrcRange, 31, 1) + FldFunc(DecVa_RegVppMode, CrcBlack, 30, 1) + FldFunc(DecVa_RegVppMode, Opt656Dis, 29, 1) + FldFunc(DecVa_RegVppMode, OptmemEna, 28, 1) + FldFunc(DecVa_RegVppMode, ClipEna, 27, 1) + FldFunc(DecVa_RegVppMode, FiltFld, 25, 1) + FldFunc(DecVa_RegVppMode, OsdFull, 24, 1) + FldFunc(DecVa_RegVppMode, OsdEna, 23, 1) + FldFunc(DecVa_RegVppMode, DeintEna, 22, 1) + FldFunc(DecVa_RegVppMode, Clip601, 20, 1) + FldFunc(DecVa_RegVppMode, IntFilt, 19, 1) + FldFunc(DecVa_RegVppMode, CscEna, 18, 1) + FldFunc(DecVa_RegVppMode, ChrLeft, 17, 1) + FldFunc(DecVa_RegVppMode, ChrUp, 16, 1) + FldFunc(DecVa_RegVppMode, Yfen, 15, 1) + FldFunc(DecVa_RegVppMode, YfNumphs, 8, 4) + FldFunc(DecVa_RegVppMode, Xfen, 7, 1) + FldFunc(DecVa_RegVppMode, XfNumphs, 0, 4) +RegFunc(DecodeVouta, 0x700800, RegVppInorg, 0x8, DecVa_RegVppInorg, 0x700808) + FldFunc(DecVa_RegVppInorg, Inyorg, 16, 12) + FldFunc(DecVa_RegVppInorg, Inxorg, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppInsize, 0xC, DecVa_RegVppInsize, 0x70080c) + FldFunc(DecVa_RegVppInsize, Inysize, 16, 12) + FldFunc(DecVa_RegVppInsize, Inxsize, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppIntctl, 0x10, DecVa_RegVppIntctl, 0x700810) + FldFunc(DecVa_RegVppIntctl, AlmostDoneLineNumber, 16, 12) + FldFunc(DecVa_RegVppIntctl, QintMode, 15, 1) + FldFunc(DecVa_RegVppIntctl, EnaVifUnderflow, 4, 1) + FldFunc(DecVa_RegVppIntctl, EnaVifad, 3, 1) + FldFunc(DecVa_RegVppIntctl, EnaVifeof, 2, 1) + FldFunc(DecVa_RegVppIntctl, EnaAd, 1, 1) + FldFunc(DecVa_RegVppIntctl, EnaEof, 0, 1) +RegFunc(DecodeVouta, 0x700800, RegVppIntstat, 0x14, DecVa_RegVppIntstat, 0x700814) + FldFunc(DecVa_RegVppIntstat, Queuecount, 28, 4) + FldFunc(DecVa_RegVppIntstat, Revid, 24, 4) + FldFunc(DecVa_RegVppIntstat, EofOpt, 23, 1) + FldFunc(DecVa_RegVppIntstat, EofOsd, 22, 1) + FldFunc(DecVa_RegVppIntstat, EofFch, 21, 1) + FldFunc(DecVa_RegVppIntstat, EofDnt, 20, 1) + FldFunc(DecVa_RegVppIntstat, EofScx, 19, 1) + FldFunc(DecVa_RegVppIntstat, EofScy, 18, 1) + FldFunc(DecVa_RegVppIntstat, EofChr, 17, 1) + FldFunc(DecVa_RegVppIntstat, EofFmt, 16, 1) + FldFunc(DecVa_RegVppIntstat, Debug, 8, 8) + FldFunc(DecVa_RegVppIntstat, Run, 7, 1) + FldFunc(DecVa_RegVppIntstat, Rstact, 6, 1) + FldFunc(DecVa_RegVppIntstat, VifUnderflow, 4, 1) + FldFunc(DecVa_RegVppIntstat, Vifad, 3, 1) + FldFunc(DecVa_RegVppIntstat, Vifeof, 2, 1) + FldFunc(DecVa_RegVppIntstat, Ad, 1, 1) + FldFunc(DecVa_RegVppIntstat, Eof, 0, 1) +RegFunc(DecodeVouta, 0x700800, RegVppFilttap, 0x18, DecVa_RegVppFilttap, 0x700818) + FldFunc(DecVa_RegVppFilttap, Coefa, 24, 8) + FldFunc(DecVa_RegVppFilttap, Coefb, 16, 8) + FldFunc(DecVa_RegVppFilttap, Coefc, 8, 8) + FldFunc(DecVa_RegVppFilttap, Coefd, 0, 8) +RegFunc(DecodeVouta, 0x700800, RegVppFiltctl, 0x1C, DecVa_RegVppFiltctl, 0x70081c) + FldFunc(DecVa_RegVppFiltctl, Readback, 13, 1) + FldFunc(DecVa_RegVppFiltctl, BotFld, 12, 1) + FldFunc(DecVa_RegVppFiltctl, Yf, 11, 1) + FldFunc(DecVa_RegVppFiltctl, Xf, 10, 1) + FldFunc(DecVa_RegVppFiltctl, Ln, 9, 1) + FldFunc(DecVa_RegVppFiltctl, Cn, 8, 1) + FldFunc(DecVa_RegVppFiltctl, Inc, 4, 4) + FldFunc(DecVa_RegVppFiltctl, Phase, 0, 4) +RegFunc(DecodeVouta, 0x700800, RegVppOutsize, 0x20, DecVa_RegVppOutsize, 0x700820) + FldFunc(DecVa_RegVppOutsize, Outysize, 16, 12) + FldFunc(DecVa_RegVppOutsize, Outxsize, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppOutyedge, 0x24, DecVa_RegVppOutyedge, 0x700824) + FldFunc(DecVa_RegVppOutyedge, Crop, 31, 1) + FldFunc(DecVa_RegVppOutyedge, Counttop, 16, 12) + FldFunc(DecVa_RegVppOutyedge, Countbottom, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppOutxedge, 0x28, DecVa_RegVppOutxedge, 0x700828) + FldFunc(DecVa_RegVppOutxedge, Crop, 31, 1) + FldFunc(DecVa_RegVppOutxedge, Countleft, 16, 12) + FldFunc(DecVa_RegVppOutxedge, Countright, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppOsd, 0x2C, DecVa_RegVppOsd, 0x70082c) + FldFunc(DecVa_RegVppOsd, Addr, 0, 32) +RegFunc(DecodeVouta, 0x700800, RegVppInoffset, 0x30, DecVa_RegVppInoffset, 0x700830) + FldFunc(DecVa_RegVppInoffset, Toplum, 24, 8) + FldFunc(DecVa_RegVppInoffset, Topchr, 16, 8) + FldFunc(DecVa_RegVppInoffset, Botlum, 8, 8) + FldFunc(DecVa_RegVppInoffset, Botchr, 0, 8) +RegFunc(DecodeVouta, 0x700800, RegVppRammon, 0x34, DecVa_RegVppRammon, 0x700834) + FldFunc(DecVa_RegVppRammon, Osddry, 24, 8) + FldFunc(DecVa_RegVppRammon, Fchdry, 16, 8) + FldFunc(DecVa_RegVppRammon, Latency, 0, 16) +RegFunc(DecodeVouta, 0x700800, RegVppPadvalue, 0x38, DecVa_RegVppPadvalue, 0x700838) + FldFunc(DecVa_RegVppPadvalue, Padinsp, 31, 1) + FldFunc(DecVa_RegVppPadvalue, Padlum, 16, 8) + FldFunc(DecVa_RegVppPadvalue, Padchru, 8, 8) + FldFunc(DecVa_RegVppPadvalue, Padchrv, 0, 8) +RegFunc(DecodeVouta, 0x700800, RegVppOpt, 0x3C, DecVa_RegVppOpt, 0x70083c) + FldFunc(DecVa_RegVppOpt, Addr, 0, 32) +RegFunc(DecodeVouta, 0x700800, RegVppCrclum, 0x40, DecVa_RegVppCrclum, 0x700840) + FldFunc(DecVa_RegVppCrclum, Crc, 0, 32) +RegFunc(DecodeVouta, 0x700800, RegVppCrcchr, 0x44, DecVa_RegVppCrcchr, 0x700844) + FldFunc(DecVa_RegVppCrcchr, Crc, 0, 32) +RegFunc(DecodeVouta, 0x700800, RegVppCrccolor, 0x48, DecVa_RegVppCrccolor, 0x700848) + FldFunc(DecVa_RegVppCrccolor, Lum, 16, 8) + FldFunc(DecVa_RegVppCrccolor, Chru, 8, 8) + FldFunc(DecVa_RegVppCrccolor, Chrv, 0, 8) +RegFunc(DecodeVouta, 0x700800, RegVppChecksum, 0x4C, DecVa_RegVppChecksum, 0x70084c) + FldFunc(DecVa_RegVppChecksum, Sum, 0, 32) +RegFunc(DecodeVouta, 0x700800, RegVppRange, 0x50, DecVa_RegVppRange, 0x700850) + FldFunc(DecVa_RegVppRange, Main, 31, 1) + FldFunc(DecVa_RegVppRange, LumEn, 15, 1) + FldFunc(DecVa_RegVppRange, Lum, 8, 3) + FldFunc(DecVa_RegVppRange, ChrEn, 7, 1) + FldFunc(DecVa_RegVppRange, Chr, 0, 3) +RegFunc(DecodeVouta, 0x700800, RegVppColorcvt, 0x54, DecVa_RegVppColorcvt, 0x700854) + FldFunc(DecVa_RegVppColorcvt, Coef1, 16, 12) + FldFunc(DecVa_RegVppColorcvt, Coef0, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppDecimate, 0x58, DecVa_RegVppDecimate, 0x700858) + FldFunc(DecVa_RegVppDecimate, YEn, 31, 1) + FldFunc(DecVa_RegVppDecimate, YM, 24, 7) + FldFunc(DecVa_RegVppDecimate, YN, 16, 7) + FldFunc(DecVa_RegVppDecimate, XEn, 15, 1) + FldFunc(DecVa_RegVppDecimate, XM, 8, 7) + FldFunc(DecVa_RegVppDecimate, XN, 0, 7) +RegFunc(DecodeVouta, 0x700800, RegVppDecisize, 0x5C, DecVa_RegVppDecisize, 0x70085c) + FldFunc(DecVa_RegVppDecisize, YSize, 16, 12) + FldFunc(DecVa_RegVppDecisize, XSize, 0, 12) +RegFunc(DecodeVouta, 0x700800, RegVppDecivec, 0x60, DecVa_RegVppDecivec, 0x700860) + FldFunc(DecVa_RegVppDecivec, Selects, 0, 32) + +RegAreaFunc(DecodeV656aBase, 0x700880, 0x7008FF) +RegFunc(DecodeV656a, 0x700880, VidCtlReg, 0x0, DecVa_VidCtlReg, 0x700880) + FldFunc(DecVa_VidCtlReg, ResetVidout, 14, 1) + FldFunc(DecVa_VidCtlReg, DiagLoad, 13, 1) + FldFunc(DecVa_VidCtlReg, ClkOpp, 12, 1) + FldFunc(DecVa_VidCtlReg, SdSel, 11, 1) + FldFunc(DecVa_VidCtlReg, SdDvi, 10, 1) + FldFunc(DecVa_VidCtlReg, Oe, 9, 1) + FldFunc(DecVa_VidCtlReg, UnSw, 8, 1) + FldFunc(DecVa_VidCtlReg, Nrt, 7, 1) + FldFunc(DecVa_VidCtlReg, ClipDis, 6, 1) + FldFunc(DecVa_VidCtlReg, InvertSync, 5, 1) + FldFunc(DecVa_VidCtlReg, DviMode, 4, 1) + FldFunc(DecVa_VidCtlReg, Vsynen, 3, 1) + FldFunc(DecVa_VidCtlReg, Wm, 2, 1) + FldFunc(DecVa_VidCtlReg, Pro, 1, 1) + FldFunc(DecVa_VidCtlReg, En, 0, 1) +RegFunc(DecodeV656a, 0x700880, VidSpl, 0x4, DecVa_VidSpl, 0x700884) + FldFunc(DecVa_VidSpl, SamplesPerLine, 0, 13) +RegFunc(DecodeV656a, 0x700880, VidSpal, 0x8, DecVa_VidSpal, 0x700888) + FldFunc(DecVa_VidSpal, SamplesPerActiveLine, 0, 13) +RegFunc(DecodeV656a, 0x700880, EToE, 0xC, DecVa_EToE, 0x70088c) + FldFunc(DecVa_EToE, EndOfLineToEndOfLine, 0, 13) +RegFunc(DecodeV656a, 0x700880, Lpf, 0x10, DecVa_Lpf, 0x700890) + FldFunc(DecVa_Lpf, LinePerFrame, 0, 13) +RegFunc(DecodeV656a, 0x700880, Vlpf, 0x14, DecVa_Vlpf, 0x700894) + FldFunc(DecVa_Vlpf, VideoLinesPerFrame, 0, 13) +RegFunc(DecodeV656a, 0x700880, Vbsf1, 0x18, DecVa_Vbsf1, 0x700898) + FldFunc(DecVa_Vbsf1, VideoBlankingStartField1, 0, 13) +RegFunc(DecodeV656a, 0x700880, Vbff1, 0x1C, DecVa_Vbff1, 0x70089c) + FldFunc(DecVa_Vbff1, VideoBlankingFinishField1, 0, 13) +RegFunc(DecodeV656a, 0x700880, Vbsf2, 0x20, DecVa_Vbsf2, 0x7008a0) + FldFunc(DecVa_Vbsf2, VideoBlankingStartField2, 0, 13) +RegFunc(DecodeV656a, 0x700880, Vbff2, 0x24, DecVa_Vbff2, 0x7008a4) + FldFunc(DecVa_Vbff2, VideoBlankingFinishField2, 0, 13) +RegFunc(DecodeV656a, 0x700880, F1id, 0x28, DecVa_F1id, 0x7008a8) + FldFunc(DecVa_F1id, Field1Id, 0, 13) +RegFunc(DecodeV656a, 0x700880, F2id, 0x2C, DecVa_F2id, 0x7008ac) + FldFunc(DecVa_F2id, Field2Id, 0, 13) +RegFunc(DecodeV656a, 0x700880, Vcurfld, 0x30, DecVa_Vcurfld, 0x7008b0) + FldFunc(DecVa_Vcurfld, CcBufOcc, 8, 2) + FldFunc(DecVa_Vcurfld, 656BufOcc, 4, 2) + FldFunc(DecVa_Vcurfld, VdUnd, 3, 1) + FldFunc(DecVa_Vcurfld, VsynErr, 2, 1) + FldFunc(DecVa_Vcurfld, FldIn, 1, 1) + FldFunc(DecVa_Vcurfld, 656Fld, 0, 1) +RegFunc(DecodeV656a, 0x700880, VsdF0, 0x34, DecVa_VsdF0, 0x7008b4) + FldFunc(DecVa_VsdF0, F0dist, 0, 22) +RegFunc(DecodeV656a, 0x700880, VsdF1, 0x38, DecVa_VsdF1, 0x7008b8) + FldFunc(DecVa_VsdF1, F1dist, 0, 22) +RegFunc(DecodeV656a, 0x700880, Vsw, 0x3C, DecVa_Vsw, 0x7008bc) + FldFunc(DecVa_Vsw, Gbndsize, 0, 7) +RegFunc(DecodeV656a, 0x700880, HdDviHsyncStart, 0x40, DecVa_HdDviHsyncStart, 0x7008c0) + FldFunc(DecVa_HdDviHsyncStart, Addr, 0, 22) +RegFunc(DecodeV656a, 0x700880, HdDviHsyncSize, 0x44, DecVa_HdDviHsyncSize, 0x7008c4) + FldFunc(DecVa_HdDviHsyncSize, Size, 0, 22) +RegFunc(DecodeV656a, 0x700880, HdDviVsyncF1Start, 0x48, DecVa_HdDviVsyncF1Start, 0x7008c8) + FldFunc(DecVa_HdDviVsyncF1Start, Addr, 0, 22) +RegFunc(DecodeV656a, 0x700880, HdDviVsyncF1Size, 0x4C, DecVa_HdDviVsyncF1Size, 0x7008cc) + FldFunc(DecVa_HdDviVsyncF1Size, Size, 0, 22) +RegFunc(DecodeV656a, 0x700880, HdDviVsyncF2Start, 0x50, DecVa_HdDviVsyncF2Start, 0x7008d0) + FldFunc(DecVa_HdDviVsyncF2Start, Addr, 0, 22) +RegFunc(DecodeV656a, 0x700880, HdDviVsyncF2Size, 0x54, DecVa_HdDviVsyncF2Size, 0x7008d4) + FldFunc(DecVa_HdDviVsyncF2Size, Size, 0, 22) +RegFunc(DecodeV656a, 0x700880, BkF1, 0x58, DecVa_BkF1, 0x7008d8) + FldFunc(DecVa_BkF1, Bk, 0, 12) +RegFunc(DecodeV656a, 0x700880, BkF2, 0x5C, DecVa_BkF2, 0x7008dc) + FldFunc(DecVa_BkF2, Bk, 0, 12) +RegFunc(DecodeV656a, 0x700880, Adl656, 0x60, DecVa_Adl656, 0x7008e0) + FldFunc(DecVa_Adl656, AlmostDoneInt, 0, 13) +RegFunc(DecodeV656a, 0x700880, CcBufAddr, 0x64, DecVa_CcBufAddr, 0x7008e4) + FldFunc(DecVa_CcBufAddr, CcEnable, 31, 1) + FldFunc(DecVa_CcBufAddr, BufferAddr, 0, 31) +RegFunc(DecodeV656a, 0x700880, CcStrt, 0x68, DecVa_CcStrt, 0x7008e8) + FldFunc(DecVa_CcStrt, CcLineStartF2, 16, 13) + FldFunc(DecVa_CcStrt, CcLineStartF1, 0, 13) +RegFunc(DecodeV656a, 0x700880, CcLines, 0x6C, DecVa_CcLines, 0x7008ec) + FldFunc(DecVa_CcLines, CcNumLinesF2, 16, 13) + FldFunc(DecVa_CcLines, CcNumLinesF1, 0, 13) +RegFunc(DecodeV656a, 0x700880, ClkmuxCtrl, 0x70, DecVa_ClkmuxCtrl, 0x7008f0) + FldFunc(DecVa_ClkmuxCtrl, ResetClkmux, 8, 1) + FldFunc(DecVa_ClkmuxCtrl, ClkmuxDelay, 0, 8) + +RegAreaFunc(DecodeVoutbBase, 0x700900, 0x70097F) +RegFunc(DecodeVoutb, 0x700900, RegVppCtl, 0x0, DecVb_RegVppCtl, 0x700900) + FldFunc(DecVb_RegVppCtl, Start, 31, 1) + FldFunc(DecVb_RegVppCtl, Loop, 30, 1) + FldFunc(DecVb_RegVppCtl, Rst, 29, 1) + FldFunc(DecVb_RegVppCtl, Vifrst, 28, 1) + FldFunc(DecVb_RegVppCtl, DiagLoad, 27, 1) + FldFunc(DecVb_RegVppCtl, Outfield, 19, 1) + FldFunc(DecVb_RegVppCtl, Outbot, 18, 1) + FldFunc(DecVb_RegVppCtl, Field, 17, 1) + FldFunc(DecVb_RegVppCtl, Bot, 16, 1) + FldFunc(DecVb_RegVppCtl, OppPicid, 8, 8) + FldFunc(DecVb_RegVppCtl, RefPicid, 0, 8) +RegFunc(DecodeVoutb, 0x700900, RegVppMode, 0x4, DecVb_RegVppMode, 0x700904) + FldFunc(DecVb_RegVppMode, CrcRange, 31, 1) + FldFunc(DecVb_RegVppMode, CrcBlack, 30, 1) + FldFunc(DecVb_RegVppMode, Opt656Dis, 29, 1) + FldFunc(DecVb_RegVppMode, OptmemEna, 28, 1) + FldFunc(DecVb_RegVppMode, ClipEna, 27, 1) + FldFunc(DecVb_RegVppMode, FiltFld, 25, 1) + FldFunc(DecVb_RegVppMode, OsdFull, 24, 1) + FldFunc(DecVb_RegVppMode, OsdEna, 23, 1) + FldFunc(DecVb_RegVppMode, DeintEna, 22, 1) + FldFunc(DecVb_RegVppMode, Clip601, 20, 1) + FldFunc(DecVb_RegVppMode, IntFilt, 19, 1) + FldFunc(DecVb_RegVppMode, CscEna, 18, 1) + FldFunc(DecVb_RegVppMode, ChrLeft, 17, 1) + FldFunc(DecVb_RegVppMode, ChrUp, 16, 1) + FldFunc(DecVb_RegVppMode, Yfen, 15, 1) + FldFunc(DecVb_RegVppMode, YfNumphs, 8, 4) + FldFunc(DecVb_RegVppMode, Xfen, 7, 1) + FldFunc(DecVb_RegVppMode, XfNumphs, 0, 4) +RegFunc(DecodeVoutb, 0x700900, RegVppInorg, 0x8, DecVb_RegVppInorg, 0x700908) + FldFunc(DecVb_RegVppInorg, Inyorg, 16, 12) + FldFunc(DecVb_RegVppInorg, Inxorg, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppInsize, 0xC, DecVb_RegVppInsize, 0x70090c) + FldFunc(DecVb_RegVppInsize, Inysize, 16, 12) + FldFunc(DecVb_RegVppInsize, Inxsize, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppIntctl, 0x10, DecVb_RegVppIntctl, 0x700910) + FldFunc(DecVb_RegVppIntctl, AlmostDoneLineNumber, 16, 12) + FldFunc(DecVb_RegVppIntctl, QintMode, 15, 1) + FldFunc(DecVb_RegVppIntctl, EnaVifUnderflow, 4, 1) + FldFunc(DecVb_RegVppIntctl, EnaVifad, 3, 1) + FldFunc(DecVb_RegVppIntctl, EnaVifeof, 2, 1) + FldFunc(DecVb_RegVppIntctl, EnaAd, 1, 1) + FldFunc(DecVb_RegVppIntctl, EnaEof, 0, 1) +RegFunc(DecodeVoutb, 0x700900, RegVppIntstat, 0x14, DecVb_RegVppIntstat, 0x700914) + FldFunc(DecVb_RegVppIntstat, Queuecount, 28, 4) + FldFunc(DecVb_RegVppIntstat, Revid, 24, 4) + FldFunc(DecVb_RegVppIntstat, EofOpt, 23, 1) + FldFunc(DecVb_RegVppIntstat, EofOsd, 22, 1) + FldFunc(DecVb_RegVppIntstat, EofFch, 21, 1) + FldFunc(DecVb_RegVppIntstat, EofDnt, 20, 1) + FldFunc(DecVb_RegVppIntstat, EofScx, 19, 1) + FldFunc(DecVb_RegVppIntstat, EofScy, 18, 1) + FldFunc(DecVb_RegVppIntstat, EofChr, 17, 1) + FldFunc(DecVb_RegVppIntstat, EofFmt, 16, 1) + FldFunc(DecVb_RegVppIntstat, Debug, 8, 8) + FldFunc(DecVb_RegVppIntstat, Run, 7, 1) + FldFunc(DecVb_RegVppIntstat, Rstact, 6, 1) + FldFunc(DecVb_RegVppIntstat, VifUnderflow, 4, 1) + FldFunc(DecVb_RegVppIntstat, Vifad, 3, 1) + FldFunc(DecVb_RegVppIntstat, Vifeof, 2, 1) + FldFunc(DecVb_RegVppIntstat, Ad, 1, 1) + FldFunc(DecVb_RegVppIntstat, Eof, 0, 1) +RegFunc(DecodeVoutb, 0x700900, RegVppFilttap, 0x18, DecVb_RegVppFilttap, 0x700918) + FldFunc(DecVb_RegVppFilttap, Coefa, 24, 8) + FldFunc(DecVb_RegVppFilttap, Coefb, 16, 8) + FldFunc(DecVb_RegVppFilttap, Coefc, 8, 8) + FldFunc(DecVb_RegVppFilttap, Coefd, 0, 8) +RegFunc(DecodeVoutb, 0x700900, RegVppFiltctl, 0x1C, DecVb_RegVppFiltctl, 0x70091c) + FldFunc(DecVb_RegVppFiltctl, Readback, 13, 1) + FldFunc(DecVb_RegVppFiltctl, BotFld, 12, 1) + FldFunc(DecVb_RegVppFiltctl, Yf, 11, 1) + FldFunc(DecVb_RegVppFiltctl, Xf, 10, 1) + FldFunc(DecVb_RegVppFiltctl, Ln, 9, 1) + FldFunc(DecVb_RegVppFiltctl, Cn, 8, 1) + FldFunc(DecVb_RegVppFiltctl, Inc, 4, 4) + FldFunc(DecVb_RegVppFiltctl, Phase, 0, 4) +RegFunc(DecodeVoutb, 0x700900, RegVppOutsize, 0x20, DecVb_RegVppOutsize, 0x700920) + FldFunc(DecVb_RegVppOutsize, Outysize, 16, 12) + FldFunc(DecVb_RegVppOutsize, Outxsize, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppOutyedge, 0x24, DecVb_RegVppOutyedge, 0x700924) + FldFunc(DecVb_RegVppOutyedge, Crop, 31, 1) + FldFunc(DecVb_RegVppOutyedge, Counttop, 16, 12) + FldFunc(DecVb_RegVppOutyedge, Countbottom, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppOutxedge, 0x28, DecVb_RegVppOutxedge, 0x700928) + FldFunc(DecVb_RegVppOutxedge, Crop, 31, 1) + FldFunc(DecVb_RegVppOutxedge, Countleft, 16, 12) + FldFunc(DecVb_RegVppOutxedge, Countright, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppOsd, 0x2C, DecVb_RegVppOsd, 0x70092c) + FldFunc(DecVb_RegVppOsd, Addr, 0, 32) +RegFunc(DecodeVoutb, 0x700900, RegVppInoffset, 0x30, DecVb_RegVppInoffset, 0x700930) + FldFunc(DecVb_RegVppInoffset, Toplum, 24, 8) + FldFunc(DecVb_RegVppInoffset, Topchr, 16, 8) + FldFunc(DecVb_RegVppInoffset, Botlum, 8, 8) + FldFunc(DecVb_RegVppInoffset, Botchr, 0, 8) +RegFunc(DecodeVoutb, 0x700900, RegVppRammon, 0x34, DecVb_RegVppRammon, 0x700934) + FldFunc(DecVb_RegVppRammon, Osddry, 24, 8) + FldFunc(DecVb_RegVppRammon, Fchdry, 16, 8) + FldFunc(DecVb_RegVppRammon, Latency, 0, 16) +RegFunc(DecodeVoutb, 0x700900, RegVppPadvalue, 0x38, DecVb_RegVppPadvalue, 0x700938) + FldFunc(DecVb_RegVppPadvalue, Padinsp, 31, 1) + FldFunc(DecVb_RegVppPadvalue, Padlum, 16, 8) + FldFunc(DecVb_RegVppPadvalue, Padchru, 8, 8) + FldFunc(DecVb_RegVppPadvalue, Padchrv, 0, 8) +RegFunc(DecodeVoutb, 0x700900, RegVppOpt, 0x3C, DecVb_RegVppOpt, 0x70093c) + FldFunc(DecVb_RegVppOpt, Addr, 0, 32) +RegFunc(DecodeVoutb, 0x700900, RegVppCrclum, 0x40, DecVb_RegVppCrclum, 0x700940) + FldFunc(DecVb_RegVppCrclum, Crc, 0, 32) +RegFunc(DecodeVoutb, 0x700900, RegVppCrcchr, 0x44, DecVb_RegVppCrcchr, 0x700944) + FldFunc(DecVb_RegVppCrcchr, Crc, 0, 32) +RegFunc(DecodeVoutb, 0x700900, RegVppCrccolor, 0x48, DecVb_RegVppCrccolor, 0x700948) + FldFunc(DecVb_RegVppCrccolor, Lum, 16, 8) + FldFunc(DecVb_RegVppCrccolor, Chru, 8, 8) + FldFunc(DecVb_RegVppCrccolor, Chrv, 0, 8) +RegFunc(DecodeVoutb, 0x700900, RegVppChecksum, 0x4C, DecVb_RegVppChecksum, 0x70094c) + FldFunc(DecVb_RegVppChecksum, Sum, 0, 32) +RegFunc(DecodeVoutb, 0x700900, RegVppRange, 0x50, DecVb_RegVppRange, 0x700950) + FldFunc(DecVb_RegVppRange, Main, 31, 1) + FldFunc(DecVb_RegVppRange, LumEn, 15, 1) + FldFunc(DecVb_RegVppRange, Lum, 8, 3) + FldFunc(DecVb_RegVppRange, ChrEn, 7, 1) + FldFunc(DecVb_RegVppRange, Chr, 0, 3) +RegFunc(DecodeVoutb, 0x700900, RegVppColorcvt, 0x54, DecVb_RegVppColorcvt, 0x700954) + FldFunc(DecVb_RegVppColorcvt, Coef1, 16, 12) + FldFunc(DecVb_RegVppColorcvt, Coef0, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppDecimate, 0x58, DecVb_RegVppDecimate, 0x700958) + FldFunc(DecVb_RegVppDecimate, YEn, 31, 1) + FldFunc(DecVb_RegVppDecimate, YM, 24, 7) + FldFunc(DecVb_RegVppDecimate, YN, 16, 7) + FldFunc(DecVb_RegVppDecimate, XEn, 15, 1) + FldFunc(DecVb_RegVppDecimate, XM, 8, 7) + FldFunc(DecVb_RegVppDecimate, XN, 0, 7) +RegFunc(DecodeVoutb, 0x700900, RegVppDecisize, 0x5C, DecVb_RegVppDecisize, 0x70095c) + FldFunc(DecVb_RegVppDecisize, YSize, 16, 12) + FldFunc(DecVb_RegVppDecisize, XSize, 0, 12) +RegFunc(DecodeVoutb, 0x700900, RegVppDecivec, 0x60, DecVb_RegVppDecivec, 0x700960) + FldFunc(DecVb_RegVppDecivec, Selects, 0, 32) + +RegAreaFunc(DecodeV656bBase, 0x700980, 0x7009FF) +RegFunc(DecodeV656b, 0x700980, VidCtlReg, 0x0, DecVb_VidCtlReg, 0x700980) + FldFunc(DecVb_VidCtlReg, ResetVidout, 14, 1) + FldFunc(DecVb_VidCtlReg, DiagLoad, 13, 1) + FldFunc(DecVb_VidCtlReg, ClkOpp, 12, 1) + FldFunc(DecVb_VidCtlReg, SdSel, 11, 1) + FldFunc(DecVb_VidCtlReg, SdDvi, 10, 1) + FldFunc(DecVb_VidCtlReg, Oe, 9, 1) + FldFunc(DecVb_VidCtlReg, UnSw, 8, 1) + FldFunc(DecVb_VidCtlReg, Nrt, 7, 1) + FldFunc(DecVb_VidCtlReg, ClipDis, 6, 1) + FldFunc(DecVb_VidCtlReg, InvertSync, 5, 1) + FldFunc(DecVb_VidCtlReg, DviMode, 4, 1) + FldFunc(DecVb_VidCtlReg, Vsynen, 3, 1) + FldFunc(DecVb_VidCtlReg, Wm, 2, 1) + FldFunc(DecVb_VidCtlReg, Pro, 1, 1) + FldFunc(DecVb_VidCtlReg, En, 0, 1) +RegFunc(DecodeV656b, 0x700980, VidSpl, 0x4, DecVb_VidSpl, 0x700984) + FldFunc(DecVb_VidSpl, SamplesPerLine, 0, 13) +RegFunc(DecodeV656b, 0x700980, VidSpal, 0x8, DecVb_VidSpal, 0x700988) + FldFunc(DecVb_VidSpal, SamplesPerActiveLine, 0, 13) +RegFunc(DecodeV656b, 0x700980, EToE, 0xC, DecVb_EToE, 0x70098c) + FldFunc(DecVb_EToE, EndOfLineToEndOfLine, 0, 13) +RegFunc(DecodeV656b, 0x700980, Lpf, 0x10, DecVb_Lpf, 0x700990) + FldFunc(DecVb_Lpf, LinePerFrame, 0, 13) +RegFunc(DecodeV656b, 0x700980, Vlpf, 0x14, DecVb_Vlpf, 0x700994) + FldFunc(DecVb_Vlpf, VideoLinesPerFrame, 0, 13) +RegFunc(DecodeV656b, 0x700980, Vbsf1, 0x18, DecVb_Vbsf1, 0x700998) + FldFunc(DecVb_Vbsf1, VideoBlankingStartField1, 0, 13) +RegFunc(DecodeV656b, 0x700980, Vbff1, 0x1C, DecVb_Vbff1, 0x70099c) + FldFunc(DecVb_Vbff1, VideoBlankingFinishField1, 0, 13) +RegFunc(DecodeV656b, 0x700980, Vbsf2, 0x20, DecVb_Vbsf2, 0x7009a0) + FldFunc(DecVb_Vbsf2, VideoBlankingStartField2, 0, 13) +RegFunc(DecodeV656b, 0x700980, Vbff2, 0x24, DecVb_Vbff2, 0x7009a4) + FldFunc(DecVb_Vbff2, VideoBlankingFinishField2, 0, 13) +RegFunc(DecodeV656b, 0x700980, F1id, 0x28, DecVb_F1id, 0x7009a8) + FldFunc(DecVb_F1id, Field1Id, 0, 13) +RegFunc(DecodeV656b, 0x700980, F2id, 0x2C, DecVb_F2id, 0x7009ac) + FldFunc(DecVb_F2id, Field2Id, 0, 13) +RegFunc(DecodeV656b, 0x700980, Vcurfld, 0x30, DecVb_Vcurfld, 0x7009b0) + FldFunc(DecVb_Vcurfld, CcBufOcc, 8, 2) + FldFunc(DecVb_Vcurfld, 656BufOcc, 4, 2) + FldFunc(DecVb_Vcurfld, VdUnd, 3, 1) + FldFunc(DecVb_Vcurfld, VsynErr, 2, 1) + FldFunc(DecVb_Vcurfld, FldIn, 1, 1) + FldFunc(DecVb_Vcurfld, 656Fld, 0, 1) +RegFunc(DecodeV656b, 0x700980, VsdF0, 0x34, DecVb_VsdF0, 0x7009b4) + FldFunc(DecVb_VsdF0, F0dist, 0, 22) +RegFunc(DecodeV656b, 0x700980, VsdF1, 0x38, DecVb_VsdF1, 0x7009b8) + FldFunc(DecVb_VsdF1, F1dist, 0, 22) +RegFunc(DecodeV656b, 0x700980, Vsw, 0x3C, DecVb_Vsw, 0x7009bc) + FldFunc(DecVb_Vsw, Gbndsize, 0, 7) +RegFunc(DecodeV656b, 0x700980, HdDviHsyncStart, 0x40, DecVb_HdDviHsyncStart, 0x7009c0) + FldFunc(DecVb_HdDviHsyncStart, Addr, 0, 22) +RegFunc(DecodeV656b, 0x700980, HdDviHsyncSize, 0x44, DecVb_HdDviHsyncSize, 0x7009c4) + FldFunc(DecVb_HdDviHsyncSize, Size, 0, 22) +RegFunc(DecodeV656b, 0x700980, HdDviVsyncF1Start, 0x48, DecVb_HdDviVsyncF1Start, 0x7009c8) + FldFunc(DecVb_HdDviVsyncF1Start, Addr, 0, 22) +RegFunc(DecodeV656b, 0x700980, HdDviVsyncF1Size, 0x4C, DecVb_HdDviVsyncF1Size, 0x7009cc) + FldFunc(DecVb_HdDviVsyncF1Size, Size, 0, 22) +RegFunc(DecodeV656b, 0x700980, HdDviVsyncF2Start, 0x50, DecVb_HdDviVsyncF2Start, 0x7009d0) + FldFunc(DecVb_HdDviVsyncF2Start, Addr, 0, 22) +RegFunc(DecodeV656b, 0x700980, HdDviVsyncF2Size, 0x54, DecVb_HdDviVsyncF2Size, 0x7009d4) + FldFunc(DecVb_HdDviVsyncF2Size, Size, 0, 22) +RegFunc(DecodeV656b, 0x700980, BkF1, 0x58, DecVb_BkF1, 0x7009d8) + FldFunc(DecVb_BkF1, Bk, 0, 12) +RegFunc(DecodeV656b, 0x700980, BkF2, 0x5C, DecVb_BkF2, 0x7009dc) + FldFunc(DecVb_BkF2, Bk, 0, 12) +RegFunc(DecodeV656b, 0x700980, Adl656, 0x60, DecVb_Adl656, 0x7009e0) + FldFunc(DecVb_Adl656, AlmostDoneInt, 0, 13) +RegFunc(DecodeV656b, 0x700980, CcBufAddr, 0x64, DecVb_CcBufAddr, 0x7009e4) + FldFunc(DecVb_CcBufAddr, CcEnable, 31, 1) + FldFunc(DecVb_CcBufAddr, BufferAddr, 0, 31) +RegFunc(DecodeV656b, 0x700980, CcStrt, 0x68, DecVb_CcStrt, 0x7009e8) + FldFunc(DecVb_CcStrt, CcLineStartF2, 16, 13) + FldFunc(DecVb_CcStrt, CcLineStartF1, 0, 13) +RegFunc(DecodeV656b, 0x700980, CcLines, 0x6C, DecVb_CcLines, 0x7009ec) + FldFunc(DecVb_CcLines, CcNumLinesF2, 16, 13) + FldFunc(DecVb_CcLines, CcNumLinesF1, 0, 13) +RegFunc(DecodeV656b, 0x700980, ClkmuxCtrl, 0x70, DecVb_ClkmuxCtrl, 0x7009f0) + FldFunc(DecVb_ClkmuxCtrl, ResetClkmux, 8, 1) + FldFunc(DecVb_ClkmuxCtrl, ClkmuxDelay, 0, 8) + +#endif + + +//****************************************************************************** +// +// Encoder VIP Ring Bus Node +// +//****************************************************************************** +#ifndef EXCLUDE_ENCODER_VIP + +RegAreaFunc(EncVipRbnodeRegsBase, 0x800000, 0x80007F) +RegFunc(EncVipRbnodeRegs, 0x800000, RbConfig , 0x0, EncVRRs_RbConfig , 0x800000) + FldFunc(EncVRRs_RbConfig , RdPostEna, 1, 1) + FldFunc(EncVRRs_RbConfig , RdBypEna, 0, 1) +RegFunc(EncVipRbnodeRegs, 0x800000, RbStickyError, 0x4, EncVRRs_RbStickyError, 0x800004) + FldFunc(EncVRRs_RbStickyError, Node, 1, 1) + FldFunc(EncVRRs_RbStickyError, Tgt, 0, 1) +RegFunc(EncVipRbnodeRegs, 0x800000, RbCurrentError, 0x8, EncVRRs_RbCurrentError, 0x800008) + FldFunc(EncVRRs_RbCurrentError, Node, 1, 1) + FldFunc(EncVRRs_RbCurrentError, Tgt, 0, 1) +RegFunc(EncVipRbnodeRegs, 0x800000, RbReadData, 0xC, EncVRRs_RbReadData, 0x80000c) + FldFunc(EncVRRs_RbReadData, Data, 0, 32) + +RegAreaFunc(EncVipRingbusDebugRegsBase, 0x800080, 0x8000FF) +RegFunc(EncVipRingbusDebugRegs, 0x800080, RbDebugConfig, 0x0, EncVRDRs_RbDebugConfig, 0x800080) + FldFunc(EncVRDRs_RbDebugConfig, Addr3WrStat, 15, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr2WrStat, 14, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr1WrStat, 13, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr0WrStat, 12, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr3RdStat, 11, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr2RdStat, 10, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr1RdStat, 9, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr0RdStat, 8, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr3WrEna, 7, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr2WrEna, 6, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr1WrEna, 5, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr0WrEna, 4, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr3RdEna, 3, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr2RdEna, 2, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr1RdEna, 1, 1) + FldFunc(EncVRDRs_RbDebugConfig, Addr0RdEna, 0, 1) +RegFunc(EncVipRingbusDebugRegs, 0x800080, RbDebugReg0Addr, 0x4, EncVRDRs_RbDebugReg0Addr, 0x800084) + FldFunc(EncVRDRs_RbDebugReg0Addr, Addr, 0, 16) +RegFunc(EncVipRingbusDebugRegs, 0x800080, RbDebugReg1Addr, 0x8, EncVRDRs_RbDebugReg1Addr, 0x800088) + FldFunc(EncVRDRs_RbDebugReg1Addr, Addr, 0, 16) +RegFunc(EncVipRingbusDebugRegs, 0x800080, RbDebugReg2Addr, 0xC, EncVRDRs_RbDebugReg2Addr, 0x80008c) + FldFunc(EncVRDRs_RbDebugReg2Addr, Addr, 0, 16) +RegFunc(EncVipRingbusDebugRegs, 0x800080, RbDebugReg3Addr, 0x10, EncVRDRs_RbDebugReg3Addr, 0x800090) + FldFunc(EncVRDRs_RbDebugReg3Addr, Addr, 0, 16) +RegFunc(EncVipRingbusDebugRegs, 0x800080, RbDebugOutputReg, 0x14, EncVRDRs_RbDebugOutputReg, 0x800094) + FldFunc(EncVRDRs_RbDebugOutputReg, DspRst, 1, 1) + FldFunc(EncVRDRs_RbDebugOutputReg, FmmRst, 0, 1) + +RegAreaFunc(EncVipCpuregsBase, 0x800F00, 0x800F7F) +RegFunc(EncVipCpuregs, 0x800F00, RegHst2cpuMbx, 0x0, EncVCs_RegHst2cpuMbx, 0x800f00) + FldFunc(EncVCs_RegHst2cpuMbx, Value, 0, 32) +RegFunc(EncVipCpuregs, 0x800F00, RegCpu2hstMbx, 0x4, EncVCs_RegCpu2hstMbx, 0x800f04) + FldFunc(EncVCs_RegCpu2hstMbx, Value, 0, 32) +RegFunc(EncVipCpuregs, 0x800F00, RegMbxStat, 0x8, EncVCs_RegMbxStat, 0x800f08) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIntBase, 0xC, EncVCs_RegCpuIntBase, 0x800f0c) + FldFunc(EncVCs_RegCpuIntBase, Addr, 8, 24) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIntEna, 0x10, EncVCs_RegCpuIntEna, 0x800f10) + FldFunc(EncVCs_RegCpuIntEna, Mbx, 31, 1) + FldFunc(EncVCs_RegCpuIntEna, Com7, 23, 1) + FldFunc(EncVCs_RegCpuIntEna, Com6, 22, 1) + FldFunc(EncVCs_RegCpuIntEna, Com5, 21, 1) + FldFunc(EncVCs_RegCpuIntEna, Com4, 20, 1) + FldFunc(EncVCs_RegCpuIntEna, Com3, 19, 1) + FldFunc(EncVCs_RegCpuIntEna, Com2, 18, 1) + FldFunc(EncVCs_RegCpuIntEna, Com1, 17, 1) + FldFunc(EncVCs_RegCpuIntEna, Com0, 16, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw7, 15, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw6, 14, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw5, 13, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw4, 12, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw3, 11, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw2, 10, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw1, 9, 1) + FldFunc(EncVCs_RegCpuIntEna, Hw0, 8, 1) + FldFunc(EncVCs_RegCpuIntEna, Db7, 7, 1) + FldFunc(EncVCs_RegCpuIntEna, Db6, 6, 1) + FldFunc(EncVCs_RegCpuIntEna, Db5, 5, 1) + FldFunc(EncVCs_RegCpuIntEna, Db4, 4, 1) + FldFunc(EncVCs_RegCpuIntEna, Db3, 3, 1) + FldFunc(EncVCs_RegCpuIntEna, Db2, 2, 1) + FldFunc(EncVCs_RegCpuIntEna, Db1, 1, 1) + FldFunc(EncVCs_RegCpuIntEna, Db0, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, StreamCpuIntEna, 0x10, EncVCs_StreamCpuIntEna, 0x800f10) + FldFunc(EncVCs_StreamCpuIntEna, Mbx, 31, 1) + FldFunc(EncVCs_StreamCpuIntEna, Dec, 18, 1) + FldFunc(EncVCs_StreamCpuIntEna, Aud, 17, 1) + FldFunc(EncVCs_StreamCpuIntEna, M2m, 15, 1) + FldFunc(EncVCs_StreamCpuIntEna, Pci, 14, 1) + FldFunc(EncVCs_StreamCpuIntEna, Ts1, 13, 1) + FldFunc(EncVCs_StreamCpuIntEna, Ts0, 12, 1) + FldFunc(EncVCs_StreamCpuIntEna, GpioHi, 11, 1) + FldFunc(EncVCs_StreamCpuIntEna, GpioLo, 10, 1) + FldFunc(EncVCs_StreamCpuIntEna, Vpp1, 9, 1) + FldFunc(EncVCs_StreamCpuIntEna, Vpp0, 8, 1) + FldFunc(EncVCs_StreamCpuIntEna, Rb, 1, 1) + FldFunc(EncVCs_StreamCpuIntEna, Sd, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, Dec0CpuIntEna, 0x10, EncVCs_Dec0CpuIntEna, 0x800f10) + FldFunc(EncVCs_Dec0CpuIntEna, Mbx, 31, 1) + FldFunc(EncVCs_Dec0CpuIntEna, Dec, 16, 1) + FldFunc(EncVCs_Dec0CpuIntEna, Si, 8, 1) + FldFunc(EncVCs_Dec0CpuIntEna, Rb, 1, 1) + FldFunc(EncVCs_Dec0CpuIntEna, Sd, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, Dec1CpuIntEna, 0x10, EncVCs_Dec1CpuIntEna, 0x800f10) + FldFunc(EncVCs_Dec1CpuIntEna, Mbx, 31, 1) + FldFunc(EncVCs_Dec1CpuIntEna, Cab, 9, 1) + FldFunc(EncVCs_Dec1CpuIntEna, Si, 8, 1) + FldFunc(EncVCs_Dec1CpuIntEna, Rb, 1, 1) + FldFunc(EncVCs_Dec1CpuIntEna, Sd, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIntStat, 0x14, EncVCs_RegCpuIntStat, 0x800f14) + FldFunc(EncVCs_RegCpuIntStat, Mbx, 31, 1) + FldFunc(EncVCs_RegCpuIntStat, Com7, 23, 1) + FldFunc(EncVCs_RegCpuIntStat, Com6, 22, 1) + FldFunc(EncVCs_RegCpuIntStat, Com5, 21, 1) + FldFunc(EncVCs_RegCpuIntStat, Com4, 20, 1) + FldFunc(EncVCs_RegCpuIntStat, Com3, 19, 1) + FldFunc(EncVCs_RegCpuIntStat, Com2, 18, 1) + FldFunc(EncVCs_RegCpuIntStat, Com1, 17, 1) + FldFunc(EncVCs_RegCpuIntStat, Com0, 16, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw7, 15, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw6, 14, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw5, 13, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw4, 12, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw3, 11, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw2, 10, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw1, 9, 1) + FldFunc(EncVCs_RegCpuIntStat, Hw0, 8, 1) + FldFunc(EncVCs_RegCpuIntStat, Db7, 7, 1) + FldFunc(EncVCs_RegCpuIntStat, Db6, 6, 1) + FldFunc(EncVCs_RegCpuIntStat, Db5, 5, 1) + FldFunc(EncVCs_RegCpuIntStat, Db4, 4, 1) + FldFunc(EncVCs_RegCpuIntStat, Db3, 3, 1) + FldFunc(EncVCs_RegCpuIntStat, Db2, 2, 1) + FldFunc(EncVCs_RegCpuIntStat, Db1, 1, 1) + FldFunc(EncVCs_RegCpuIntStat, Db0, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, StreamCpuIntStat, 0x14, EncVCs_StreamCpuIntStat, 0x800f14) + FldFunc(EncVCs_StreamCpuIntStat, Mbx, 31, 1) + FldFunc(EncVCs_StreamCpuIntStat, Dec, 18, 1) + FldFunc(EncVCs_StreamCpuIntStat, Aud, 17, 1) + FldFunc(EncVCs_StreamCpuIntStat, M2m, 15, 1) + FldFunc(EncVCs_StreamCpuIntStat, Pci, 14, 1) + FldFunc(EncVCs_StreamCpuIntStat, Ts1, 13, 1) + FldFunc(EncVCs_StreamCpuIntStat, Ts0, 12, 1) + FldFunc(EncVCs_StreamCpuIntStat, GpioHi, 11, 1) + FldFunc(EncVCs_StreamCpuIntStat, GpioLo, 10, 1) + FldFunc(EncVCs_StreamCpuIntStat, Vpp1, 9, 1) + FldFunc(EncVCs_StreamCpuIntStat, Vpp0, 8, 1) + FldFunc(EncVCs_StreamCpuIntStat, Rb, 1, 1) + FldFunc(EncVCs_StreamCpuIntStat, Sd, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, Dec0CpuIntStat, 0x14, EncVCs_Dec0CpuIntStat, 0x800f14) + FldFunc(EncVCs_Dec0CpuIntStat, Mbx, 31, 1) + FldFunc(EncVCs_Dec0CpuIntStat, Dec, 16, 1) + FldFunc(EncVCs_Dec0CpuIntStat, Si, 8, 1) + FldFunc(EncVCs_Dec0CpuIntStat, Rb, 1, 1) + FldFunc(EncVCs_Dec0CpuIntStat, Sd, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, Dec1CpuIntStat, 0x14, EncVCs_Dec1CpuIntStat, 0x800f14) + FldFunc(EncVCs_Dec1CpuIntStat, Mbx, 31, 1) + FldFunc(EncVCs_Dec1CpuIntStat, Cab, 9, 1) + FldFunc(EncVCs_Dec1CpuIntStat, Si, 8, 1) + FldFunc(EncVCs_Dec1CpuIntStat, Rb, 1, 1) + FldFunc(EncVCs_Dec1CpuIntStat, Sd, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, RegHst2cpuStat, 0x18, EncVCs_RegHst2cpuStat, 0x800f18) + FldFunc(EncVCs_RegHst2cpuStat, Value, 0, 32) +RegFunc(EncVipCpuregs, 0x800F00, RegCpu2hstStat, 0x1C, EncVCs_RegCpu2hstStat, 0x800f1c) + FldFunc(EncVCs_RegCpu2hstStat, Value, 0, 32) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIntgenSet, 0x20, EncVCs_RegCpuIntgenSet, 0x800f20) + FldFunc(EncVCs_RegCpuIntgenSet, Cpu2HstMbx, 31, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int15, 15, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int14, 14, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int13, 13, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int12, 12, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int11, 11, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int10, 10, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int9, 9, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int8, 8, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int7, 7, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int6, 6, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int5, 5, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int4, 4, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int3, 3, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int2, 2, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int1, 1, 1) + FldFunc(EncVCs_RegCpuIntgenSet, Int0, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIntgenClr, 0x24, EncVCs_RegCpuIntgenClr, 0x800f24) + FldFunc(EncVCs_RegCpuIntgenClr, Cpu2HstMbx, 31, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int15, 15, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int14, 14, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int13, 13, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int12, 12, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int11, 11, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int10, 10, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int9, 9, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int8, 8, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int7, 7, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int6, 6, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int5, 5, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int4, 4, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int3, 3, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int2, 2, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int1, 1, 1) + FldFunc(EncVCs_RegCpuIntgenClr, Int0, 0, 1) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIcacheMiss, 0x28, EncVCs_RegCpuIcacheMiss, 0x800f28) + FldFunc(EncVCs_RegCpuIcacheMiss, Count, 0, 32) +RegFunc(EncVipCpuregs, 0x800F00, RegCpuIntgenMask, 0x2C, EncVCs_RegCpuIntgenMask, 0x800f2c) + FldFunc(EncVCs_RegCpuIntgenMask, Cpu2HstMbx, 31, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int15, 15, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int14, 14, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int13, 13, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int12, 12, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int11, 11, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int10, 10, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int9, 9, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int8, 8, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int7, 7, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int6, 6, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int5, 5, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int4, 4, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int3, 3, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int2, 2, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int1, 1, 1) + FldFunc(EncVCs_RegCpuIntgenMask, Int0, 0, 1) + +RegAreaFunc(EncVipCpudmaBase, 0x801800, 0x8018FF) +RegFunc(EncVipCpudma, 0x801800, RegDma0SdAddr, 0x0, EncVCa_RegDma0SdAddr, 0x801800) + FldFunc(EncVCa_RegDma0SdAddr, SdAddr, 0, 32) +RegFunc(EncVipCpudma, 0x801800, RegDma0LclAddr, 0x4, EncVCa_RegDma0LclAddr, 0x801804) + FldFunc(EncVCa_RegDma0LclAddr, Addr, 2, 7) +RegFunc(EncVipCpudma, 0x801800, RegDma0Len, 0x8, EncVCa_RegDma0Len, 0x801808) + FldFunc(EncVCa_RegDma0Len, Length, 2, 8) +RegFunc(EncVipCpudma, 0x801800, RegDma1SdAddr, 0x10, EncVCa_RegDma1SdAddr, 0x801810) + FldFunc(EncVCa_RegDma1SdAddr, SdAddr, 0, 32) +RegFunc(EncVipCpudma, 0x801800, RegDma1LclAddr, 0x14, EncVCa_RegDma1LclAddr, 0x801814) + FldFunc(EncVCa_RegDma1LclAddr, Addr, 2, 7) +RegFunc(EncVipCpudma, 0x801800, RegDma1Len, 0x18, EncVCa_RegDma1Len, 0x801818) + FldFunc(EncVCa_RegDma1Len, Length, 2, 8) +RegFunc(EncVipCpudma, 0x801800, RegDma2SdAddr, 0x20, EncVCa_RegDma2SdAddr, 0x801820) + FldFunc(EncVCa_RegDma2SdAddr, SdAddr, 0, 32) +RegFunc(EncVipCpudma, 0x801800, RegDma2LclAddr, 0x24, EncVCa_RegDma2LclAddr, 0x801824) + FldFunc(EncVCa_RegDma2LclAddr, Addr, 2, 7) +RegFunc(EncVipCpudma, 0x801800, RegDma2Len, 0x28, EncVCa_RegDma2Len, 0x801828) + FldFunc(EncVCa_RegDma2Len, Length, 2, 8) +RegFunc(EncVipCpudma, 0x801800, RegDma3SdAddr, 0x30, EncVCa_RegDma3SdAddr, 0x801830) + FldFunc(EncVCa_RegDma3SdAddr, SdAddr, 0, 32) +RegFunc(EncVipCpudma, 0x801800, RegDma3LclAddr, 0x34, EncVCa_RegDma3LclAddr, 0x801834) + FldFunc(EncVCa_RegDma3LclAddr, Addr, 2, 7) +RegFunc(EncVipCpudma, 0x801800, RegDma3Len, 0x38, EncVCa_RegDma3Len, 0x801838) + FldFunc(EncVCa_RegDma3Len, Length, 2, 8) +RegFunc(EncVipCpudma, 0x801800, RegDmaStatus, 0x40, EncVCa_RegDmaStatus, 0x801840) + FldFunc(EncVCa_RegDmaStatus, Act3, 3, 1) + FldFunc(EncVCa_RegDmaStatus, Act2, 2, 1) + FldFunc(EncVCa_RegDmaStatus, Act1, 1, 1) + FldFunc(EncVCa_RegDmaStatus, Act0, 0, 1) + +RegAreaFunc(EncVipDmamemBase, 0x801A00, 0x8021FF) +RegFunc(EncVipDmamem, 0x801A00, DmaMem, 0x0, EncVDm_DmaMem, 0x801a00) + FldFunc(EncVDm_DmaMem, Data, 0, 32) + +RegAreaFunc(EncVipIndSdramRegsBase, 0x841000, 0x84107F) +RegFunc(EncVipIndSdramRegs, 0x841000, RegSdramInc, 0x0, EncVISRs_RegSdramInc, 0x841000) + FldFunc(EncVISRs_RegSdramInc, Inc, 0, 1) +RegFunc(EncVipIndSdramRegs, 0x841000, RegSdramAddr, 0x4, EncVISRs_RegSdramAddr, 0x841004) + FldFunc(EncVISRs_RegSdramAddr, Addr, 0, 32) +RegFunc(EncVipIndSdramRegs, 0x841000, RegSdramData, 0x8, EncVISRs_RegSdramData, 0x841008) + FldFunc(EncVISRs_RegSdramData, Data, 0, 32) +RegFunc(EncVipIndSdramRegs, 0x841000, RegCpuDbg, 0x10, EncVISRs_RegCpuDbg, 0x841010) + FldFunc(EncVISRs_RegCpuDbg, Hst, 0, 1) + +RegAreaFunc(EncVipCpucoreBase, 0x844000, 0x844FFF) +RegFunc(EncVipCpucore, 0x844000, CpucoreReg, 0x0, EncVCe_CpucoreReg, 0x844000) + FldFunc(EncVCe_CpucoreReg, Addr, 0, 32) + +RegAreaFunc(EncVipCpuauxBase, 0x845000, 0x845FFF) +RegFunc(EncVipCpuaux, 0x845000, CpuauxReg, 0x0, EncVCx_CpuauxReg, 0x845000) + FldFunc(EncVCx_CpuauxReg, Addr, 0, 32) + +RegAreaFunc(EncVipCpuimemBase, 0x846000, 0x847FFF) +RegFunc(EncVipCpuimem, 0x846000, CpuimemReg, 0x0, EncVCm_CpuimemReg, 0x846000) + FldFunc(EncVCm_CpuimemReg, Addr, 0, 32) + +RegAreaFunc(EncVipCpudmemBase, 0x848000, 0x84FFFF) +RegFunc(EncVipCpudmem, 0x848000, CpudmemReg, 0x0, EncVCm_CpudmemReg, 0x848000) + FldFunc(EncVCm_CpudmemReg, Addr, 0, 32) + +RegAreaFunc(EncVppBase, 0x8E0000, 0x8FFFFF) + +#endif + + +#if defined(FldEnum) + +// One FldEnum macro (must be defined external to file) call per register field enum. +// register, field, name, value + +FldEnum(EncSn_EncSe2binPutsym, Type, NBits, 0) +FldEnum(EncSn_EncSe2binPutsym, Type, ExpGolomb, 1) +FldEnum(EncSn_EncSe2binPutsym, Type, MPEGInfo, 2) +FldEnum(EncSn_EncSe2binPutsym, Type, MPEGCoef, 3) +FldEnum(EncSn_EncSe2binPutsym, Type, H264Info, 4) +FldEnum(EncSn_EncSe2binPutsym, Type, H264Coef, 5) +FldEnum(EncSn_EncSe2binPutsym, Type, SP4x4Mode, 6) +FldEnum(EncSn_EncSe2binPutsym, Type, Reset, 7) +FldEnum(EncSn_EncSe2binPutsym, Type, Flush, 8) + +FldEnum(EncSn_EncSe2binPutsym, SubType, NBits_NA, 0) + +FldEnum(EncSn_EncSe2binPutsym, SubType, ExpGolomb_Unsigned, 0) +FldEnum(EncSn_EncSe2binPutsym, SubType, ExpGolomb_Signed, 1) + +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_MBTypeIFrame, 0) +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_MBTypePFrame, 1) +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_MBTypeBFrame, 2) +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_MBAddr, 3) +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_CBP, 4) +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_MotionCode, 5) +FldEnum(EncSn_EncSe2binPutsym, SubType, MPEGInfo_DMVector, 6) + +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_MBTypeI, 0) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_MBTypeP, 1) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_MBTypeB, 2) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_SubMBTypeP, 3) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_SubMBTypeB, 4) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_MVD, 5) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_TU, 6) +FldEnum(EncSn_EncSe2binPutsym, SubType, H264Info_CBP, 7) + +FldEnum(EncSn_EncSe2binPutsym, SubType, SP4x4Mode_CAVLC, 0) +FldEnum(EncSn_EncSe2binPutsym, SubType, SP4x4Mode_CABAC, 1) + +FldEnum(EncSn_EncSe2binDoResid, Type, Type_CAVLC, 1) +FldEnum(EncSn_EncSe2binDoResid, Type, Type_CABAC, 2) + +#endif//defined(FldEnum) + +// Field defines with no real registers associated +FldFunc(C2BCnvtCmdW0, RdAddr, 0, 32) + +FldFunc(C2BCnvtCmdW1, MaxBits, 0, 32) + +FldFunc(C2BCnvtCmdW2, StartMBY, 24, 8) +FldFunc(C2BCnvtCmdW2, StartMBX, 16, 8) +FldFunc(C2BCnvtCmdW2, NumRefIdxL1, 10, 6) +FldFunc(C2BCnvtCmdW2, NumRefIdxL0, 4, 6) +FldFunc(C2BCnvtCmdW2, Struct, 2, 2) +FldFunc(C2BCnvtCmdW2, Type, 0, 2) + +FldFunc(C2BCnvtCmdW3, Width, 24, 8) +FldFunc(C2BCnvtCmdW3, Enc, 23, 1) +FldFunc(C2BCnvtCmdW3, 8x8MF, 22, 1) +FldFunc(C2BCnvtCmdW3, EPMode, 20, 2) +FldFunc(C2BCnvtCmdW3, D8x8IF, 19, 1) +FldFunc(C2BCnvtCmdW3, ChromaFactor, 17, 2) +FldFunc(C2BCnvtCmdW3, Align64, 16, 1) +FldFunc(C2BCnvtCmdW3, WrCtxId, 10, 6) +FldFunc(C2BCnvtCmdW3, RdCtxId, 4, 6) +FldFunc(C2BCnvtCmdW3, Cmd, 0, 4) + +FldFunc(C2BInitCmdW0, RdAddr, 0, 32) + +FldFunc(C2BInitCmdW3, Rsv10, 10, 22) +FldFunc(C2BInitCmdW3, QP, 4, 6) +FldFunc(C2BInitCmdW3, Cmd, 0, 4) + +FldFunc(C2BCopyCmdW0, RdAddr, 0, 32) + +FldFunc(C2BCopyCmdW1, CopyBits, 0, 32) + +FldFunc(C2BCopyCmdW3, Rsv24, 24, 8) +FldFunc(C2BCopyCmdW3, Enc, 23, 1) +FldFunc(C2BCopyCmdW3, Rsv22, 22, 1) +FldFunc(C2BCopyCmdW3, EPMode, 20, 2) +FldFunc(C2BCopyCmdW3, Rsv17, 17, 3) +FldFunc(C2BCopyCmdW3, Align64, 16, 1) +FldFunc(C2BCopyCmdW3, WrCtxId, 10, 6) +FldFunc(C2BCopyCmdW3, RdCtxId, 4, 6) +FldFunc(C2BCopyCmdW3, Cmd, 0, 4) + +FldFunc(C2BRdCtxW0, BaseAddr, 0, 32) + +FldFunc(C2BRdCtxW1, EndAddr, 0, 32) + +FldFunc(C2BRdCtxW2, MarkAddr, 0, 32) + +FldFunc(C2BWrCtxW0, BaseAddr, 0, 32) + +FldFunc(C2BWrCtxW1, EndAddr, 0, 32) + +FldFunc(C2BWrCtxW2, MarkAddr, 0, 32) +FldFunc(C2BWrCtxW2, NewFmt, 31, 1) + +FldFunc(C2BWrCtxW3, Rsv2, 2, 30) +FldFunc(C2BWrCtxW3, SMb, 1, 1) +FldFunc(C2BWrCtxW3, SMa, 0, 1) + +FldFunc(C2BWrCtxW4, Rsv6, 6, 26) +FldFunc(C2BWrCtxW4, WrPtr, 0, 6) + +FldFunc(C2BWrCtxW5, Rsv6, 6, 26) +FldFunc(C2BWrCtxW5, RdPtr, 0, 6) + +FldFunc(C2BWrCtxWx, Err, 31, 1) +FldFunc(C2BWrCtxWx, Done, 30, 1) +FldFunc(C2BWrCtxWx, SliceStart, 0, 30) + + +RegFunc(Mef, 0x00600400, FmeCtl, 0x00, Meff_FmeCtl, 0x00600400) +FldFunc(FmeCtl, RefIdx, 5, 1) +FldFunc(FmeCtl, ListIdx, 4, 1) +FldFunc(FmeCtl, HostRam, 3, 1) +FldFunc(FmeCtl, Rsv2, 2, 1) +FldFunc(FmeCtl, Enable, 1, 1) +FldFunc(FmeCtl, SADClr, 0, 1) +RegFunc(Mef, 0x00600400, FmeCurr, 0x04, Meff_FmeCurr, 0x00600404) +FldFunc(FmeCurr, FrameId, 24, 8) +FldFunc(FmeCurr, YPos, 12, 12) +FldFunc(FmeCurr, XPos, 0, 12) +RegFunc(Mef, 0x00600400, FmeRefId, 0x08, Meff_FmeRefId, 0x00600408) +RegFunc(Mef, 0x00600400, FmeRefVec, 0x0C, Meff_FmeRefVec, 0x0060040C) +FldFunc(FmeRefVec, YVec, 16, 16) // // Actually truncated to 12 bits in hw, but will be written as 16 bits of signed int +FldFunc(FmeRefVec, XVec, 0, 16) + + +RegFunc(Mef, 0x00600400, FmeMVPA, 0x10, Meff_FmeMVPA, 0x00600410) +FldFunc(FmeMVP, YVec, 16, 16) +FldFunc(FmeMVP, XVec, 0, 16) +RegFunc(Mef, 0x00600400, FmeMVPB, 0x14, Meff_FmeMVPB, 0x00600414) +RegFunc(Mef, 0x00600400, FmeMVPC, 0x18, Meff_FmeMVPC, 0x00600418) +RegFunc(Mef, 0x00600400, FmeLambda, 0x1c, Meff_FmeLambda, 0x0060041c) +FldFunc(FmeLambda, Rsv16, 16, 16) +FldFunc(FmeLambda, Val, 0, 16) + +RegFunc(Mef, 0x00600400, FmeImgSize, 0x20, Meff_FmeImgSize, 0x00600420) +FldFunc(FmeImgSize, YSize, 16, 16) +FldFunc(FmeImgSize, XSize, 0, 16) + +RegFunc(Mef, 0x00600400, FmeSearchSize, 0x24, Meff_FmeSearchSize, 0x00600424) /* By analogy with the above, note the MixedCase */ + +RegFunc(Mef, 0x00600400, FmeStatus, 0x28, Meff_FmeStatus, 0x00600428) +FldFunc(FmeStatus, OutRdy, 1, 1) +FldFunc(FmeStatus, InRdy, 0, 1) + + + +RegFunc(Mef, 0x00600400, BiPredCtl, 0x40, Meff_BiPredCtl, 0x00600440) + +RegFunc(Mef,0x00600500, MvpRefIdxA, 0x100, Meff_MvpRefIdxA, 0x00600500) +FldFunc(MvpRefIdxA, L1RefA1, 24, 8) +FldFunc(MvpRefIdxA, L0RefA1, 16, 8) +FldFunc(MvpRefIdxA, L1RefA0, 8, 8) +FldFunc(MvpRefIdxA, L0RefA0, 0, 8) + +RegFunc(Mef,0x00600500, MvpVecA00, 0x104, Meff_MvpVecA00, 0x00600504) +RegFunc(Mef,0x00600500, MvpVecA01, 0x108, Meff_MvpVecA01, 0x00600508) +RegFunc(Mef,0x00600500, MvpVecA10, 0x10c, Meff_MvpVecA10, 0x0060050c) +RegFunc(Mef,0x00600500, MvpVecA11, 0x110, Meff_MvpVecA11, 0x00600510) +RegFunc(Mef,0x00600500, MvpVecA20, 0x114, Meff_MvpVecA20, 0x00600514) +RegFunc(Mef,0x00600500, MvpVecA21, 0x118, Meff_MvpVecA21, 0x00600518) +RegFunc(Mef,0x00600500, MvpVecA30, 0x11c, Meff_MvpVecA30, 0x0060051c) +RegFunc(Mef,0x00600500, MvpVecA31, 0x120, Meff_MvpVecA31, 0x00600520) + +RegFunc(Mef,0x00600500, MvpRefIdxB, 0x124, Meff_MvpRefIdxB, 0x00600524) +FldFunc(MvpRefIdxB, L1RefB1, 24, 8) +FldFunc(MvpRefIdxB, L0RefB1, 16, 8) +FldFunc(MvpRefIdxB, L1RefB0, 8, 8) +FldFunc(MvpRefIdxB, L0RefB0, 0, 8) + + +RegFunc(Mef,0x00600500, MvpVecB00, 0x128, Meff_MvpVecB00, 0x00600528) +RegFunc(Mef,0x00600500, MvpVecB01, 0x12c, Meff_MvpVecB01, 0x0060052c) +RegFunc(Mef,0x00600500, MvpVecB10, 0x130, Meff_MvpVecB10, 0x00600530) +RegFunc(Mef,0x00600500, MvpVecB11, 0x134, Meff_MvpVecB11, 0x00600534) +RegFunc(Mef,0x00600500, MvpVecB20, 0x138, Meff_MvpVecB20, 0x00600538) +RegFunc(Mef,0x00600500, MvpVecB21, 0x13c, Meff_MvpVecB21, 0x0060053c) +RegFunc(Mef,0x00600500, MvpVecB30, 0x140, Meff_MvpVecB30, 0x00600540) +RegFunc(Mef,0x00600500, MvpVecB31, 0x144, Meff_MvpVecB31, 0x00600544) + +RegFunc(Mef,0x00600500, MvpRefIdxCAndEdge,0x148, Meff_MvpRefIdxCAndEdge, 0x00600548) +FldFunc(MvpRefIdxCAndEdge, TopEdge, 11, 1) +FldFunc(MvpRefIdxCAndEdge, RightEdge, 10, 1) +FldFunc(MvpRefIdxCAndEdge, LeftEdge, 9, 1) +FldFunc(MvpRefIdxCAndEdge, L1RefC0, 8, 8) +FldFunc(MvpRefIdxCAndEdge, L0RefC0, 0, 8) + +RegFunc(Mef,0x00600500, MvpVecC00, 0x14c, Meff_MvpVecC00, 0x0060054c) +RegFunc(Mef,0x00600500, MvpVecC01, 0x150, Meff_MvpVecC01, 0x00600550) + +RegFunc(Mef,0x00600500, MvpCurrMode, 0x154, Meff_MvpCurrMode, 0x00600554) + +FldFunc(MvpCurrMode, MbMode, 14, 2) +FldFunc(MvpCurrMode, PartIdx, 12, 2) +FldFunc(MvpCurrMode, SubMode, 10, 2) +FldFunc(MvpCurrMode, ListIdx, 8, 2) +FldFunc(MvpCurrMode, RefIdx, 0, 8) + +RegFunc(Mef,0x00600500, MvpResultMode, 0x158, Meff_MvpResultMode, 0x00600558) +FldFunc(MvpResultMode, SubMode, 16, 2) +FldFunc(MvpResultMode, Refidx1, 8, 8) +FldFunc(MvpResultMode, Refidx0, 0, 8) + +RegFunc(Mef,0x00600500, MvpMVP, 0x15c, Meff_MvpMVP, 0x0060055c) +RegFunc(Mef,0x00600500, MvpMVD, 0x160, Meff_MvpMVD, 0x00600560) +RegFunc(Mef,0x00600500, MvpCost, 0x164, Meff_MvpCost, 0x00600564) + + +FldFunc(Meff_FmeCtl, RefIdx, 5, 1) +FldFunc(Meff_FmeCtl, ListIdx, 4, 1) +FldFunc(Meff_FmeCtl, HostRam, 3, 1) +FldFunc(Meff_FmeCtl, Rsv2, 2, 1) +FldFunc(Meff_FmeCtl, Enable, 1, 1) +FldFunc(Meff_FmeCtl, SADClr, 0, 1) + +FldFunc(Meff_FmeCurr, FrameId, 24, 8) +FldFunc(Meff_FmeCurr, YPos, 12, 12) +FldFunc(Meff_FmeCurr, XPos, 0, 12) + +FldFunc(Meff_FmeRefVec, YVec, 16, 16) // Actually truncated to 12 bits in hw, but will be written as 16 bits of signed int +FldFunc(Meff_FmeRefVec, XVec, 0, 16) + +FldFunc(Meff_FmeMVP, YVec, 16, 16) +FldFunc(Meff_FmeMVP, XVec, 0, 16) + +FldFunc(Meff_FmeLambda, Rsv16, 16, 16) +FldFunc(Meff_FmeLambda, Val, 0, 16) + +FldFunc(Meff_FmeImgSize, YSize, 16, 16) +FldFunc(Meff_FmeImgSize, XSize, 0, 16) + +FldFunc(Meff_FmeStatus, l00, 3, 1) // vector l0 r0 ready to read +FldFunc(Meff_FmeStatus, BidirRdy, 2, 1) +FldFunc(Meff_FmeStatus, OutRdy, 1, 1) +FldFunc(Meff_FmeStatus, InRdy, 0, 1) + +FldFunc(Meff_MvpRefIdxA, L1RefA1, 24, 8) +FldFunc(Meff_MvpRefIdxA, L0RefA1, 16, 8) +FldFunc(Meff_MvpRefIdxA, L1RefA0, 8, 8) +FldFunc(Meff_MvpRefIdxA, L0RefA0, 0, 8) + +FldFunc(Meff_MvpRefIdxB, L1RefB1, 24, 8) +FldFunc(Meff_MvpRefIdxB, L0RefB1, 16, 8) +FldFunc(Meff_MvpRefIdxB, L1RefB0, 8, 8) +FldFunc(Meff_MvpRefIdxB, L0RefB0, 0, 8) + +FldFunc(Meff_MvpRefIdxCAndEdge, TopEdge, 11, 1) +FldFunc(Meff_MvpRefIdxCAndEdge, RightEdge, 10, 1) +FldFunc(Meff_MvpRefIdxCAndEdge, LeftEdge, 9, 1) +FldFunc(Meff_MvpRefIdxCAndEdge, L1RefC0, 8, 8) +FldFunc(Meff_MvpRefIdxCAndEdge, L0RefC0, 0, 8) + +FldFunc(Meff_MvpCurrMode, MbMode, 14, 2) +FldFunc(Meff_MvpCurrMode, PartIdx, 12, 2) +FldFunc(Meff_MvpCurrMode, SubMode, 10, 2) +FldFunc(Meff_MvpCurrMode, ListIdx, 8, 2) +FldFunc(Meff_MvpCurrMode, RefIdx, 0, 8) + +FldFunc(Meff_MvpResultMode, SubMode, 16, 2) +FldFunc(Meff_MvpResultMode, Refidx1, 8, 8) +FldFunc(Meff_MvpResultMode, Refidx0, 0, 8) + +FldFunc(Meff_EncFCs_RegMbxStat, Rsv2, 2, 30) +FldFunc(Meff_EncFCs_RegMbxStat, C2H, 1, 1) +FldFunc(Meff_EncFCs_RegMbxStat, H2C, 0, 1) + +#ifdef VCMODS_REGMAP +// PFCD not sure why these two areafuncs conflict, change to one common area + +RegAreaFunc(MefBase, 0x600600, 0x600AFF) +RegFunc(Mef,0x00600600, BiPredSad, 0x0, Meff_BiPredSad, 0x00600600) +//RegAreaFunc(MefBase, 0x600800, 0x600AFF) +RegFunc(Mef,0x00600800, FmeVec, 0x0, Meff_FmeVec, 0x00600800) + +#else +RegAreaFunc(MefBase, 0x600600, 0x6007FF) +RegFunc(Mef,0x00600600, BiPredSad, 0x0, Meff_BiPredSad, 0x00600600) +RegAreaFunc(MefBase, 0x600800, 0x600AFF) +RegFunc(Mef,0x00600800, FmeVec, 0x0, Meff_FmeVec, 0x00600800) +#endif + diff --git a/bcm2708_chip/system_arbiter_ctrl.h b/bcm2708_chip/system_arbiter_ctrl.h new file mode 100755 index 0000000..5f63955 --- /dev/null +++ b/bcm2708_chip/system_arbiter_ctrl.h @@ -0,0 +1,437 @@ +// This file was generated by the create_regs script +#define SYSAC_BASE 0x7e009000 +#define SYSAC_APB_ID 0x4152424d +#define SYSAC_HOST_PRIORITY HW_REGISTER_RW( 0x7e009000 ) + #define SYSAC_HOST_PRIORITY_MASK 0x0000000f + #define SYSAC_HOST_PRIORITY_WIDTH 4 + #define SYSAC_HOST_PRIORITY_RESET 0000000000 + #define SYSAC_HOST_PRIORITY_PRIORITY_BITS 3:0 + #define SYSAC_HOST_PRIORITY_PRIORITY_SET 0x0000000f + #define SYSAC_HOST_PRIORITY_PRIORITY_CLR 0xfffffff0 + #define SYSAC_HOST_PRIORITY_PRIORITY_MSB 3 + #define SYSAC_HOST_PRIORITY_PRIORITY_LSB 0 + #define SYSAC_HOST_PRIORITY_PRIORITY_RESET 0x0 +#define SYSAC_DBG_PRIORITY HW_REGISTER_RW( 0x7e009004 ) + #define SYSAC_DBG_PRIORITY_MASK 0x0000000f + #define SYSAC_DBG_PRIORITY_WIDTH 4 + #define SYSAC_DBG_PRIORITY_RESET 0000000000 + #define SYSAC_DBG_PRIORITY_PRIORITY_BITS 3:0 + #define SYSAC_DBG_PRIORITY_PRIORITY_SET 0x0000000f + #define SYSAC_DBG_PRIORITY_PRIORITY_CLR 0xfffffff0 + #define SYSAC_DBG_PRIORITY_PRIORITY_MSB 3 + #define SYSAC_DBG_PRIORITY_PRIORITY_LSB 0 + #define SYSAC_DBG_PRIORITY_PRIORITY_RESET 0x0 +#define SYSAC_HVSM_PRIORITY HW_REGISTER_RW( 0x7e009008 ) + #define SYSAC_HVSM_PRIORITY_MASK 0x000000ff + #define SYSAC_HVSM_PRIORITY_WIDTH 8 + #define SYSAC_HVSM_PRIORITY_RESET 0000000000 + #define SYSAC_HVSM_PRIORITY_P_PRIORITY_BITS 7:4 + #define SYSAC_HVSM_PRIORITY_P_PRIORITY_SET 0x000000f0 + #define SYSAC_HVSM_PRIORITY_P_PRIORITY_CLR 0xffffff0f + #define SYSAC_HVSM_PRIORITY_P_PRIORITY_MSB 7 + #define SYSAC_HVSM_PRIORITY_P_PRIORITY_LSB 4 + #define SYSAC_HVSM_PRIORITY_P_PRIORITY_RESET 0x0 + #define SYSAC_HVSM_PRIORITY_N_PRIORITY_BITS 3:0 + #define SYSAC_HVSM_PRIORITY_N_PRIORITY_SET 0x0000000f + #define SYSAC_HVSM_PRIORITY_N_PRIORITY_CLR 0xfffffff0 + #define SYSAC_HVSM_PRIORITY_N_PRIORITY_MSB 3 + #define SYSAC_HVSM_PRIORITY_N_PRIORITY_LSB 0 + #define SYSAC_HVSM_PRIORITY_N_PRIORITY_RESET 0x0 +#define SYSAC_V3D_PRIORITY HW_REGISTER_RW( 0x7e00900c ) + #define SYSAC_V3D_PRIORITY_MASK 0x0000000f + #define SYSAC_V3D_PRIORITY_WIDTH 4 + #define SYSAC_V3D_PRIORITY_RESET 0000000000 + #define SYSAC_V3D_PRIORITY_PRIORITY_BITS 3:0 + #define SYSAC_V3D_PRIORITY_PRIORITY_SET 0x0000000f + #define SYSAC_V3D_PRIORITY_PRIORITY_CLR 0xfffffff0 + #define SYSAC_V3D_PRIORITY_PRIORITY_MSB 3 + #define SYSAC_V3D_PRIORITY_PRIORITY_LSB 0 + #define SYSAC_V3D_PRIORITY_PRIORITY_RESET 0x0 +#define SYSAC_H264_PRIORITY HW_REGISTER_RW( 0x7e009010 ) + #define SYSAC_H264_PRIORITY_MASK 0x0000000f + #define SYSAC_H264_PRIORITY_WIDTH 4 + #define SYSAC_H264_PRIORITY_RESET 0000000000 + #define SYSAC_H264_PRIORITY_PRIORITY_BITS 3:0 + #define SYSAC_H264_PRIORITY_PRIORITY_SET 0x0000000f + #define SYSAC_H264_PRIORITY_PRIORITY_CLR 0xfffffff0 + #define SYSAC_H264_PRIORITY_PRIORITY_MSB 3 + #define SYSAC_H264_PRIORITY_PRIORITY_LSB 0 + #define SYSAC_H264_PRIORITY_PRIORITY_RESET 0x0 +#define SYSAC_JPEG_PRIORITY HW_REGISTER_RW( 0x7e009014 ) + #define SYSAC_JPEG_PRIORITY_MASK 0x000000ff + #define SYSAC_JPEG_PRIORITY_WIDTH 8 + #define SYSAC_JPEG_PRIORITY_RESET 0000000000 + #define SYSAC_JPEG_PRIORITY_P_PRIORITY_BITS 7:4 + #define SYSAC_JPEG_PRIORITY_P_PRIORITY_SET 0x000000f0 + #define SYSAC_JPEG_PRIORITY_P_PRIORITY_CLR 0xffffff0f + #define SYSAC_JPEG_PRIORITY_P_PRIORITY_MSB 7 + #define SYSAC_JPEG_PRIORITY_P_PRIORITY_LSB 4 + #define SYSAC_JPEG_PRIORITY_P_PRIORITY_RESET 0x0 + #define SYSAC_JPEG_PRIORITY_N_PRIORITY_BITS 3:0 + #define SYSAC_JPEG_PRIORITY_N_PRIORITY_SET 0x0000000f + #define SYSAC_JPEG_PRIORITY_N_PRIORITY_CLR 0xfffffff0 + #define SYSAC_JPEG_PRIORITY_N_PRIORITY_MSB 3 + #define SYSAC_JPEG_PRIORITY_N_PRIORITY_LSB 0 + #define SYSAC_JPEG_PRIORITY_N_PRIORITY_RESET 0x0 +#define SYSAC_TRANS_PRIORITY HW_REGISTER_RW( 0x7e009018 ) + #define SYSAC_TRANS_PRIORITY_MASK 0x000000ff + #define SYSAC_TRANS_PRIORITY_WIDTH 8 + #define SYSAC_TRANS_PRIORITY_RESET 0000000000 + #define SYSAC_TRANS_PRIORITY_P_PRIORITY_BITS 7:4 + #define SYSAC_TRANS_PRIORITY_P_PRIORITY_SET 0x000000f0 + #define SYSAC_TRANS_PRIORITY_P_PRIORITY_CLR 0xffffff0f + #define SYSAC_TRANS_PRIORITY_P_PRIORITY_MSB 7 + #define SYSAC_TRANS_PRIORITY_P_PRIORITY_LSB 4 + #define SYSAC_TRANS_PRIORITY_P_PRIORITY_RESET 0x0 + #define SYSAC_TRANS_PRIORITY_N_PRIORITY_BITS 3:0 + #define SYSAC_TRANS_PRIORITY_N_PRIORITY_SET 0x0000000f + #define SYSAC_TRANS_PRIORITY_N_PRIORITY_CLR 0xfffffff0 + #define SYSAC_TRANS_PRIORITY_N_PRIORITY_MSB 3 + #define SYSAC_TRANS_PRIORITY_N_PRIORITY_LSB 0 + #define SYSAC_TRANS_PRIORITY_N_PRIORITY_RESET 0x0 +#define SYSAC_ISP_PRIORITY HW_REGISTER_RW( 0x7e00901c ) + #define SYSAC_ISP_PRIORITY_MASK 0x0000000f + #define SYSAC_ISP_PRIORITY_WIDTH 4 + #define SYSAC_ISP_PRIORITY_RESET 0000000000 + #define SYSAC_ISP_PRIORITY_PRIORITY_BITS 3:0 + #define SYSAC_ISP_PRIORITY_PRIORITY_SET 0x0000000f + #define SYSAC_ISP_PRIORITY_PRIORITY_CLR 0xfffffff0 + #define SYSAC_ISP_PRIORITY_PRIORITY_MSB 3 + #define SYSAC_ISP_PRIORITY_PRIORITY_LSB 0 + #define SYSAC_ISP_PRIORITY_PRIORITY_RESET 0x0 +#define SYSAC_USB_PRIORITY HW_REGISTER_RW( 0x7e009020 ) + #define SYSAC_USB_PRIORITY_MASK 0x0000000f + #define SYSAC_USB_PRIORITY_WIDTH 4 + #define SYSAC_USB_PRIORITY_RESET 0000000000 + #define SYSAC_USB_PRIORITY_PRIORITY_BITS 3:0 + #define SYSAC_USB_PRIORITY_PRIORITY_SET 0x0000000f + #define SYSAC_USB_PRIORITY_PRIORITY_CLR 0xfffffff0 + #define SYSAC_USB_PRIORITY_PRIORITY_MSB 3 + #define SYSAC_USB_PRIORITY_PRIORITY_LSB 0 + #define SYSAC_USB_PRIORITY_PRIORITY_RESET 0x0 +#define SYSAC_L2_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009040 ) + #define SYSAC_L2_ARBITER_CONTROL_MASK 0x0000ffff + #define SYSAC_L2_ARBITER_CONTROL_WIDTH 16 + #define SYSAC_L2_ARBITER_CONTROL_RESET 0000000000 + #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15 + #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8 + #define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0 + #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_BITS 7:6 + #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0 + #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f + #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_MSB 7 + #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_LSB 6 + #define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_RESET 0x0 + #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_BITS 5:4 + #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_SET 0x00000030 + #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf + #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_MSB 5 + #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_LSB 4 + #define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_RESET 0x0 + #define SYSAC_L2_ARBITER_CONTROL_DELAY_BITS 3:2 + #define SYSAC_L2_ARBITER_CONTROL_DELAY_SET 0x0000000c + #define SYSAC_L2_ARBITER_CONTROL_DELAY_CLR 0xfffffff3 + #define SYSAC_L2_ARBITER_CONTROL_DELAY_MSB 3 + #define SYSAC_L2_ARBITER_CONTROL_DELAY_LSB 2 + #define SYSAC_L2_ARBITER_CONTROL_DELAY_RESET 0x0 + #define SYSAC_L2_ARBITER_CONTROL_LIMIT_BITS 1:0 + #define SYSAC_L2_ARBITER_CONTROL_LIMIT_SET 0x00000003 + #define SYSAC_L2_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc + #define SYSAC_L2_ARBITER_CONTROL_LIMIT_MSB 1 + #define SYSAC_L2_ARBITER_CONTROL_LIMIT_LSB 0 + #define SYSAC_L2_ARBITER_CONTROL_LIMIT_RESET 0x0 +#define SYSAC_UC_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009044 ) + #define SYSAC_UC_ARBITER_CONTROL_MASK 0x0000ffff + #define SYSAC_UC_ARBITER_CONTROL_WIDTH 16 + #define SYSAC_UC_ARBITER_CONTROL_RESET 0000000000 + #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15 + #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8 + #define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0 + #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_BITS 7:6 + #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0 + #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f + #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_MSB 7 + #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_LSB 6 + #define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_RESET 0x0 + #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_BITS 5:4 + #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030 + #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf + #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_MSB 5 + #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_LSB 4 + #define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_RESET 0x0 + #define SYSAC_UC_ARBITER_CONTROL_DELAY_BITS 3:2 + #define SYSAC_UC_ARBITER_CONTROL_DELAY_SET 0x0000000c + #define SYSAC_UC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3 + #define SYSAC_UC_ARBITER_CONTROL_DELAY_MSB 3 + #define SYSAC_UC_ARBITER_CONTROL_DELAY_LSB 2 + #define SYSAC_UC_ARBITER_CONTROL_DELAY_RESET 0x0 + #define SYSAC_UC_ARBITER_CONTROL_LIMIT_BITS 1:0 + #define SYSAC_UC_ARBITER_CONTROL_LIMIT_SET 0x00000003 + #define SYSAC_UC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc + #define SYSAC_UC_ARBITER_CONTROL_LIMIT_MSB 1 + #define SYSAC_UC_ARBITER_CONTROL_LIMIT_LSB 0 + #define SYSAC_UC_ARBITER_CONTROL_LIMIT_RESET 0x0 +#define SYSAC_SRC_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009048 ) + #define SYSAC_SRC_ARBITER_CONTROL_MASK 0x0000ffff + #define SYSAC_SRC_ARBITER_CONTROL_WIDTH 16 + #define SYSAC_SRC_ARBITER_CONTROL_RESET 0000000000 + #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15 + #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8 + #define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0 + #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_BITS 7:6 + #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0 + #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f + #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_MSB 7 + #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_LSB 6 + #define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_RESET 0x0 + #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_BITS 5:4 + #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030 + #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf + #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_MSB 5 + #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_LSB 4 + #define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_RESET 0x0 + #define SYSAC_SRC_ARBITER_CONTROL_DELAY_BITS 3:2 + #define SYSAC_SRC_ARBITER_CONTROL_DELAY_SET 0x0000000c + #define SYSAC_SRC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3 + #define SYSAC_SRC_ARBITER_CONTROL_DELAY_MSB 3 + #define SYSAC_SRC_ARBITER_CONTROL_DELAY_LSB 2 + #define SYSAC_SRC_ARBITER_CONTROL_DELAY_RESET 0x0 + #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_BITS 1:0 + #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_SET 0x00000003 + #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc + #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_MSB 1 + #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_LSB 0 + #define SYSAC_SRC_ARBITER_CONTROL_LIMIT_RESET 0x0 +#define SYSAC_PERI_ARBITER_CONTROL HW_REGISTER_RW( 0x7e00904c ) + #define SYSAC_PERI_ARBITER_CONTROL_MASK 0x0000ffff + #define SYSAC_PERI_ARBITER_CONTROL_WIDTH 16 + #define SYSAC_PERI_ARBITER_CONTROL_RESET 0000000000 + #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15 + #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8 + #define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0 + #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_BITS 7:6 + #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0 + #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f + #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_MSB 7 + #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_LSB 6 + #define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_RESET 0x0 + #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_BITS 5:4 + #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_SET 0x00000030 + #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf + #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_MSB 5 + #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_LSB 4 + #define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_RESET 0x0 + #define SYSAC_PERI_ARBITER_CONTROL_DELAY_BITS 3:2 + #define SYSAC_PERI_ARBITER_CONTROL_DELAY_SET 0x0000000c + #define SYSAC_PERI_ARBITER_CONTROL_DELAY_CLR 0xfffffff3 + #define SYSAC_PERI_ARBITER_CONTROL_DELAY_MSB 3 + #define SYSAC_PERI_ARBITER_CONTROL_DELAY_LSB 2 + #define SYSAC_PERI_ARBITER_CONTROL_DELAY_RESET 0x0 + #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_BITS 1:0 + #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_SET 0x00000003 + #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc + #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_MSB 1 + #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_LSB 0 + #define SYSAC_PERI_ARBITER_CONTROL_LIMIT_RESET 0x0 +#define SYSAC_DMA_ARBITER_CONTROL_UC HW_REGISTER_RW( 0x7e009050 ) + #define SYSAC_DMA_ARBITER_CONTROL_UC_MASK 0x0000ffff + #define SYSAC_DMA_ARBITER_CONTROL_UC_WIDTH 16 + #define SYSAC_DMA_ARBITER_CONTROL_UC_RESET 0000000000 + #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_MSB 15 + #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_LSB 8 + #define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_BITS 7:6 + #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_SET 0x000000c0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_CLR 0xffffff3f + #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_MSB 7 + #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_LSB 6 + #define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_BITS 5:4 + #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_SET 0x00000030 + #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_CLR 0xffffffcf + #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_MSB 5 + #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_LSB 4 + #define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_BITS 3:2 + #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_SET 0x0000000c + #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_CLR 0xfffffff3 + #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_MSB 3 + #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_LSB 2 + #define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_BITS 1:0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_SET 0x00000003 + #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_CLR 0xfffffffc + #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_MSB 1 + #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_LSB 0 + #define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_RESET 0x0 +#define SYSAC_DMA_ARBITER_CONTROL_L2 HW_REGISTER_RW( 0x7e009054 ) + #define SYSAC_DMA_ARBITER_CONTROL_L2_MASK 0x0000ffff + #define SYSAC_DMA_ARBITER_CONTROL_L2_WIDTH 16 + #define SYSAC_DMA_ARBITER_CONTROL_L2_RESET 0000000000 + #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_BITS 7:6 + #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_SET 0x000000c0 + #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_CLR 0xffffff3f + #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_MSB 7 + #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_LSB 6 + #define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_BITS 5:4 + #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_SET 0x00000030 + #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_CLR 0xffffffcf + #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_MSB 5 + #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_LSB 4 + #define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_BITS 3:2 + #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_SET 0x0000000c + #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_CLR 0xfffffff3 + #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_MSB 3 + #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_LSB 2 + #define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_BITS 1:0 + #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_SET 0x00000003 + #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_CLR 0xfffffffc + #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_MSB 1 + #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_LSB 0 + #define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_RESET 0x0 +#define SYSAC_DMA_ARBITER_CONTROL_PER HW_REGISTER_RW( 0x7e009058 ) + #define SYSAC_DMA_ARBITER_CONTROL_PER_MASK 0x0000ffff + #define SYSAC_DMA_ARBITER_CONTROL_PER_WIDTH 16 + #define SYSAC_DMA_ARBITER_CONTROL_PER_RESET 0000000000 + #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_MSB 15 + #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_LSB 8 + #define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_BITS 7:6 + #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_SET 0x000000c0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_CLR 0xffffff3f + #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_MSB 7 + #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_LSB 6 + #define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_BITS 5:4 + #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_SET 0x00000030 + #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_CLR 0xffffffcf + #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_MSB 5 + #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_LSB 4 + #define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_BITS 3:2 + #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_SET 0x0000000c + #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_CLR 0xfffffff3 + #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_MSB 3 + #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_LSB 2 + #define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_BITS 1:0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_SET 0x00000003 + #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_CLR 0xfffffffc + #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_MSB 1 + #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_LSB 0 + #define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_RESET 0x0 +#define SYSAC_DMA_ARBITER_CONTROL_LITE HW_REGISTER_RW( 0x7e00905c ) + #define SYSAC_DMA_ARBITER_CONTROL_LITE_MASK 0x0000ffff + #define SYSAC_DMA_ARBITER_CONTROL_LITE_WIDTH 16 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_RESET 0000000000 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_BITS 15:8 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_SET 0x0000ff00 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_CLR 0xffff00ff + #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_MSB 15 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_LSB 8 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_RESET0x0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_BITS 7:6 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_SET 0x000000c0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_CLR 0xffffff3f + #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_MSB 7 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_LSB 6 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_BITS 5:4 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_SET 0x00000030 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_CLR 0xffffffcf + #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_MSB 5 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_LSB 4 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_BITS 3:2 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_SET 0x0000000c + #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_CLR 0xfffffff3 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_MSB 3 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_LSB 2 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_RESET 0x0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_BITS 1:0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_SET 0x00000003 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_CLR 0xfffffffc + #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_MSB 1 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_LSB 0 + #define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_RESET 0x0 +#define SYSAC_DUMMY_STATUS HW_REGISTER_RW( 0x7e009060 ) + #define SYSAC_DUMMY_STATUS_MASK 0x00000001 + #define SYSAC_DUMMY_STATUS_WIDTH 1 + #define SYSAC_DUMMY_STATUS_RESET 0000000000 + #define SYSAC_DUMMY_STATUS_IDLE_BITS 0:0 + #define SYSAC_DUMMY_STATUS_IDLE_SET 0x00000001 + #define SYSAC_DUMMY_STATUS_IDLE_CLR 0xfffffffe + #define SYSAC_DUMMY_STATUS_IDLE_MSB 0 + #define SYSAC_DUMMY_STATUS_IDLE_LSB 0 + #define SYSAC_DUMMY_STATUS_IDLE_RESET 0x0 +#define SYSAC_DMA_DREQ_CONTROL HW_REGISTER_RW( 0x7e009064 ) + #define SYSAC_DMA_DREQ_CONTROL_MASK 0x0000000f + #define SYSAC_DMA_DREQ_CONTROL_WIDTH 4 + #define SYSAC_DMA_DREQ_CONTROL_RESET 0000000000 + #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_BITS 2:0 + #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_SET 0x00000007 + #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_CLR 0xfffffff8 + #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_MSB 2 + #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_LSB 0 + #define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_RESET 0x0 + #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_BITS 3:3 + #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_SET 0x00000008 + #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_CLR 0xfffffff7 + #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_MSB 3 + #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_LSB 3 + #define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_RESET 0x0 +#define SYSAC_V3D_LIMITER HW_REGISTER_RW( 0x7e009068 ) + #define SYSAC_V3D_LIMITER_MASK 0x00000fff + #define SYSAC_V3D_LIMITER_WIDTH 12 + #define SYSAC_V3D_LIMITER_RESET 0000000000 + #define SYSAC_V3D_LIMITER_ENABLE_BITS 0:0 + #define SYSAC_V3D_LIMITER_ENABLE_SET 0x00000001 + #define SYSAC_V3D_LIMITER_ENABLE_CLR 0xfffffffe + #define SYSAC_V3D_LIMITER_ENABLE_MSB 0 + #define SYSAC_V3D_LIMITER_ENABLE_LSB 0 + #define SYSAC_V3D_LIMITER_ENABLE_RESET 0x0 + #define SYSAC_V3D_LIMITER_SPARE_BITS 3:1 + #define SYSAC_V3D_LIMITER_SPARE_SET 0x0000000e + #define SYSAC_V3D_LIMITER_SPARE_CLR 0xfffffff1 + #define SYSAC_V3D_LIMITER_SPARE_MSB 3 + #define SYSAC_V3D_LIMITER_SPARE_LSB 1 + #define SYSAC_V3D_LIMITER_SPARE_RESET 0x0 + #define SYSAC_V3D_LIMITER_MAX_PRIORITY_BITS 7:3 + #define SYSAC_V3D_LIMITER_MAX_PRIORITY_SET 0x000000f8 + #define SYSAC_V3D_LIMITER_MAX_PRIORITY_CLR 0xffffff07 + #define SYSAC_V3D_LIMITER_MAX_PRIORITY_MSB 7 + #define SYSAC_V3D_LIMITER_MAX_PRIORITY_LSB 3 + #define SYSAC_V3D_LIMITER_MAX_PRIORITY_RESET 0x0 + #define SYSAC_V3D_LIMITER_INCREMENT_BITS 0:0 + #define SYSAC_V3D_LIMITER_INCREMENT_SET 0x00000001 + #define SYSAC_V3D_LIMITER_INCREMENT_CLR 0xfffffffe + #define SYSAC_V3D_LIMITER_INCREMENT_MSB 0 + #define SYSAC_V3D_LIMITER_INCREMENT_LSB 0 + #define SYSAC_V3D_LIMITER_INCREMENT_RESET 0x0 + #define SYSAC_V3D_LIMITER_HOLDOFF_BITS 0:0 + #define SYSAC_V3D_LIMITER_HOLDOFF_SET 0x00000001 + #define SYSAC_V3D_LIMITER_HOLDOFF_CLR 0xfffffffe + #define SYSAC_V3D_LIMITER_HOLDOFF_MSB 0 + #define SYSAC_V3D_LIMITER_HOLDOFF_LSB 0 + #define SYSAC_V3D_LIMITER_HOLDOFF_RESET 0x0 diff --git a/bcm2708_chip/tectl.h b/bcm2708_chip/tectl.h new file mode 100755 index 0000000..6481a49 --- /dev/null +++ b/bcm2708_chip/tectl.h @@ -0,0 +1,30 @@ +// This file was generated by the create_regs script +#define TE_BASE 0x7e20e000 +#define TE_APB_ID 0x00746563 +#define TE_0C HW_REGISTER_RW( 0x7e20e000 ) + #define TE_0C_MASK 0xffffffff + #define TE_0C_WIDTH 32 +#define TE_0VSWIDTH HW_REGISTER_RW( 0x7e20e004 ) + #define TE_0VSWIDTH_MASK 0xffffffff + #define TE_0VSWIDTH_WIDTH 32 +#define TE_0TIMER HW_REGISTER_RW( 0x7e20e008 ) + #define TE_0TIMER_MASK 0xffffffff + #define TE_0TIMER_WIDTH 32 +#define TE_1C HW_REGISTER_RW( 0x7e20e00c ) + #define TE_1C_MASK 0xffffffff + #define TE_1C_WIDTH 32 +#define TE_1VSWIDTH HW_REGISTER_RW( 0x7e20e010 ) + #define TE_1VSWIDTH_MASK 0xffffffff + #define TE_1VSWIDTH_WIDTH 32 +#define TE_1TIMER HW_REGISTER_RW( 0x7e20e014 ) + #define TE_1TIMER_MASK 0xffffffff + #define TE_1TIMER_WIDTH 32 +#define TE_2C HW_REGISTER_RW( 0x7e20e018 ) + #define TE_2C_MASK 0xffffffff + #define TE_2C_WIDTH 32 +#define TE_2VSWIDTH HW_REGISTER_RW( 0x7e20e01c ) + #define TE_2VSWIDTH_MASK 0xffffffff + #define TE_2VSWIDTH_WIDTH 32 +#define TE_2TIMER HW_REGISTER_RW( 0x7e20e020 ) + #define TE_2TIMER_MASK 0xffffffff + #define TE_2TIMER_WIDTH 32 diff --git a/bcm2708_chip/tectl_a0.h b/bcm2708_chip/tectl_a0.h new file mode 100755 index 0000000..394c876 --- /dev/null +++ b/bcm2708_chip/tectl_a0.h @@ -0,0 +1,21 @@ +// This file was generated by the create_regs script +#define TE_BASE 0x7e20e000 +#define TE_APB_ID 0x00746563 +#define TE_0C HW_REGISTER_RW( 0x7e20e000 ) + #define TE_0C_MASK 0xffffffff + #define TE_0C_WIDTH 32 +#define TE_0VSWIDTH HW_REGISTER_RW( 0x7e20e004 ) + #define TE_0VSWIDTH_MASK 0xffffffff + #define TE_0VSWIDTH_WIDTH 32 +#define TE_1C HW_REGISTER_RW( 0x7e20e008 ) + #define TE_1C_MASK 0xffffffff + #define TE_1C_WIDTH 32 +#define TE_1VSWIDTH HW_REGISTER_RW( 0x7e20e00c ) + #define TE_1VSWIDTH_MASK 0xffffffff + #define TE_1VSWIDTH_WIDTH 32 +#define TE_2C HW_REGISTER_RW( 0x7e20e010 ) + #define TE_2C_MASK 0xffffffff + #define TE_2C_WIDTH 32 +#define TE_2VSWIDTH HW_REGISTER_RW( 0x7e20e014 ) + #define TE_2VSWIDTH_MASK 0xffffffff + #define TE_2VSWIDTH_WIDTH 32 diff --git a/bcm2708_chip/tempsens.h b/bcm2708_chip/tempsens.h new file mode 100755 index 0000000..886f776 --- /dev/null +++ b/bcm2708_chip/tempsens.h @@ -0,0 +1,71 @@ +// This file was generated by the create_regs script +#define TS_BASE 0x7e212000 +#define TS_APB_ID 0x7473656e +#define TS_TSENSCTL HW_REGISTER_RW( 0x7e212000 ) + #define TS_TSENSCTL_MASK 0x07ffffff + #define TS_TSENSCTL_WIDTH 27 + #define TS_TSENSCTL_RESET 0000000000 + #define TS_TSENSCTL_PRWDW_BITS 0:0 + #define TS_TSENSCTL_PRWDW_SET 0x00000001 + #define TS_TSENSCTL_PRWDW_CLR 0xfffffffe + #define TS_TSENSCTL_PRWDW_MSB 0 + #define TS_TSENSCTL_PRWDW_LSB 0 + #define TS_TSENSCTL_RSTB_BITS 1:1 + #define TS_TSENSCTL_RSTB_SET 0x00000002 + #define TS_TSENSCTL_RSTB_CLR 0xfffffffd + #define TS_TSENSCTL_RSTB_MSB 1 + #define TS_TSENSCTL_RSTB_LSB 1 + #define TS_TSENSCTL_CTRL_BITS 4:2 + #define TS_TSENSCTL_CTRL_SET 0x0000001c + #define TS_TSENSCTL_CTRL_CLR 0xffffffe3 + #define TS_TSENSCTL_CTRL_MSB 4 + #define TS_TSENSCTL_CTRL_LSB 2 + #define TS_TSENSCTL_EN_INT_BITS 5:5 + #define TS_TSENSCTL_EN_INT_SET 0x00000020 + #define TS_TSENSCTL_EN_INT_CLR 0xffffffdf + #define TS_TSENSCTL_EN_INT_MSB 5 + #define TS_TSENSCTL_EN_INT_LSB 5 + #define TS_TSENSCTL_DIRECT_BITS 6:6 + #define TS_TSENSCTL_DIRECT_SET 0x00000040 + #define TS_TSENSCTL_DIRECT_CLR 0xffffffbf + #define TS_TSENSCTL_DIRECT_MSB 6 + #define TS_TSENSCTL_DIRECT_LSB 6 + #define TS_TSENSCTL_CLR_INT_BITS 7:7 + #define TS_TSENSCTL_CLR_INT_SET 0x00000080 + #define TS_TSENSCTL_CLR_INT_CLR 0xffffff7f + #define TS_TSENSCTL_CLR_INT_MSB 7 + #define TS_TSENSCTL_CLR_INT_LSB 7 + #define TS_TSENSCTL_THOLD_BITS 17:8 + #define TS_TSENSCTL_THOLD_SET 0x0003ff00 + #define TS_TSENSCTL_THOLD_CLR 0xfffc00ff + #define TS_TSENSCTL_THOLD_MSB 17 + #define TS_TSENSCTL_THOLD_LSB 8 + #define TS_TSENSCTL_RSTDELAY_BITS 25:18 + #define TS_TSENSCTL_RSTDELAY_SET 0x03fc0000 + #define TS_TSENSCTL_RSTDELAY_CLR 0xfc03ffff + #define TS_TSENSCTL_RSTDELAY_MSB 25 + #define TS_TSENSCTL_RSTDELAY_LSB 18 + #define TS_TSENSCTL_REGULEN_BITS 26:26 + #define TS_TSENSCTL_REGULEN_SET 0x04000000 + #define TS_TSENSCTL_REGULEN_CLR 0xfbffffff + #define TS_TSENSCTL_REGULEN_MSB 26 + #define TS_TSENSCTL_REGULEN_LSB 26 +#define TS_TSENSSTAT HW_REGISTER_RW( 0x7e212004 ) + #define TS_TSENSSTAT_MASK 0x00000fff + #define TS_TSENSSTAT_WIDTH 12 + #define TS_TSENSSTAT_RESET 0000000000 + #define TS_TSENSSTAT_DATA_BITS 9:0 + #define TS_TSENSSTAT_DATA_SET 0x000003ff + #define TS_TSENSSTAT_DATA_CLR 0xfffffc00 + #define TS_TSENSSTAT_DATA_MSB 9 + #define TS_TSENSSTAT_DATA_LSB 0 + #define TS_TSENSSTAT_VALID_BITS 10:10 + #define TS_TSENSSTAT_VALID_SET 0x00000400 + #define TS_TSENSSTAT_VALID_CLR 0xfffffbff + #define TS_TSENSSTAT_VALID_MSB 10 + #define TS_TSENSSTAT_VALID_LSB 10 + #define TS_TSENSSTAT_INTERUPT_BITS 11:11 + #define TS_TSENSSTAT_INTERUPT_SET 0x00000800 + #define TS_TSENSSTAT_INTERUPT_CLR 0xfffff7ff + #define TS_TSENSSTAT_INTERUPT_MSB 11 + #define TS_TSENSSTAT_INTERUPT_LSB 11 diff --git a/bcm2708_chip/testbus.h b/bcm2708_chip/testbus.h new file mode 100755 index 0000000..9245135 --- /dev/null +++ b/bcm2708_chip/testbus.h @@ -0,0 +1,219 @@ +// This file was generated by the create_regs script +#define TB_BASE 0x7e20b000 +#define TB_ADDR HW_REGISTER_RW( 0x7e20b000 ) + #define TB_ADDR_MASK 0xffffffff + #define TB_ADDR_WIDTH 32 +#define TB_TASK HW_REGISTER_RW( 0x7e20b000 ) + #define TB_TASK_MASK 0x0001ffff + #define TB_TASK_WIDTH 17 + #define TB_TASK_NUM_BITS 15:0 + #define TB_TASK_NUM_SET 0x0000ffff + #define TB_TASK_NUM_CLR 0xffff0000 + #define TB_TASK_NUM_MSB 15 + #define TB_TASK_NUM_LSB 0 + #define TB_TASK_TEXT_FLAG_BITS 16:16 + #define TB_TASK_TEXT_FLAG_SET 0x00010000 + #define TB_TASK_TEXT_FLAG_CLR 0xfffeffff + #define TB_TASK_TEXT_FLAG_MSB 16 + #define TB_TASK_TEXT_FLAG_LSB 16 +#define TB_TASK_PARAM1 HW_REGISTER_RW( 0x7e20b004 ) + #define TB_TASK_PARAM1_MASK 0xffffffff + #define TB_TASK_PARAM1_WIDTH 32 +#define TB_TASK_PARAM2 HW_REGISTER_RW( 0x7e20b008 ) + #define TB_TASK_PARAM2_MASK 0xffffffff + #define TB_TASK_PARAM2_WIDTH 32 +#define TB_TASK_PARAM3 HW_REGISTER_RW( 0x7e20b00c ) + #define TB_TASK_PARAM3_MASK 0xffffffff + #define TB_TASK_PARAM3_WIDTH 32 +#define TB_TASK_STATUS HW_REGISTER_RW( 0x7e20b080 ) + #define TB_TASK_STATUS_MASK 0xffffffff + #define TB_TASK_STATUS_WIDTH 32 +#define TB_TASK_RXDATA1 HW_REGISTER_RW( 0x7e20b084 ) + #define TB_TASK_RXDATA1_MASK 0xffffffff + #define TB_TASK_RXDATA1_WIDTH 32 +#define TB_TASK_RXDATA2 HW_REGISTER_RW( 0x7e20b088 ) + #define TB_TASK_RXDATA2_MASK 0xffffffff + #define TB_TASK_RXDATA2_WIDTH 32 +#define TB_TASK_TXTCLR HW_REGISTER_RW( 0x7e20b0f0 ) + #define TB_TASK_TXTCLR_MASK 0xffffffff + #define TB_TASK_TXTCLR_WIDTH 32 +#define TB_HDMI HW_REGISTER_RW( 0x7e20b100 ) + #define TB_HDMI_MASK 0xffffffff + #define TB_HDMI_WIDTH 32 +#define TB_PCM HW_REGISTER_RW( 0x7e20b200 ) + #define TB_PCM_MASK 0xffffffff + #define TB_PCM_WIDTH 32 +#define TB_HOST HW_REGISTER_RW( 0x7e20b300 ) + #define TB_HOST_MASK 0xffffffff + #define TB_HOST_WIDTH 32 +#define TB_PRINTER_CTRL HW_REGISTER_RW( 0x7e20b400 ) + #define TB_PRINTER_CTRL_MASK 0x0000fff3 + #define TB_PRINTER_CTRL_WIDTH 16 + #define TB_PRINTER_CTRL_TASKNO_BITS 15:4 + #define TB_PRINTER_CTRL_TASKNO_SET 0x0000fff0 + #define TB_PRINTER_CTRL_TASKNO_CLR 0xffff000f + #define TB_PRINTER_CTRL_TASKNO_MSB 15 + #define TB_PRINTER_CTRL_TASKNO_LSB 4 + #define TB_PRINTER_CTRL_OFFSET_BITS 1:0 + #define TB_PRINTER_CTRL_OFFSET_SET 0x00000003 + #define TB_PRINTER_CTRL_OFFSET_CLR 0xfffffffc + #define TB_PRINTER_CTRL_OFFSET_MSB 1 + #define TB_PRINTER_CTRL_OFFSET_LSB 0 +#define TB_PRINTER_DATA HW_REGISTER_RW( 0x7e20b404 ) + #define TB_PRINTER_DATA_MASK 0xffffffff + #define TB_PRINTER_DATA_WIDTH 32 +#define TB_BOOT_ADDR HW_REGISTER_RW( 0x7e20b500 ) + #define TB_BOOT_ADDR_MASK 0xffffffff + #define TB_BOOT_ADDR_WIDTH 32 +#define TB_BOOT_OPT HW_REGISTER_RW( 0x7e20b504 ) + #define TB_BOOT_OPT_MASK 0x800007ff + #define TB_BOOT_OPT_WIDTH 32 + #define TB_BOOT_OPT_FAST_OPT_BITS 0:0 + #define TB_BOOT_OPT_FAST_OPT_SET 0x00000001 + #define TB_BOOT_OPT_FAST_OPT_CLR 0xfffffffe + #define TB_BOOT_OPT_FAST_OPT_MSB 0 + #define TB_BOOT_OPT_FAST_OPT_LSB 0 + #define TB_BOOT_OPT_EIGHT_BANK_BITS 1:1 + #define TB_BOOT_OPT_EIGHT_BANK_SET 0x00000002 + #define TB_BOOT_OPT_EIGHT_BANK_CLR 0xfffffffd + #define TB_BOOT_OPT_EIGHT_BANK_MSB 1 + #define TB_BOOT_OPT_EIGHT_BANK_LSB 1 + #define TB_BOOT_OPT_FPGA_BITS 2:2 + #define TB_BOOT_OPT_FPGA_SET 0x00000004 + #define TB_BOOT_OPT_FPGA_CLR 0xfffffffb + #define TB_BOOT_OPT_FPGA_MSB 2 + #define TB_BOOT_OPT_FPGA_LSB 2 + #define TB_BOOT_OPT_TCL_SIM_BITS 3:3 + #define TB_BOOT_OPT_TCL_SIM_SET 0x00000008 + #define TB_BOOT_OPT_TCL_SIM_CLR 0xfffffff7 + #define TB_BOOT_OPT_TCL_SIM_MSB 3 + #define TB_BOOT_OPT_TCL_SIM_LSB 3 + #define TB_BOOT_OPT_ELPIDA_BITS 4:4 + #define TB_BOOT_OPT_ELPIDA_SET 0x00000010 + #define TB_BOOT_OPT_ELPIDA_CLR 0xffffffef + #define TB_BOOT_OPT_ELPIDA_MSB 4 + #define TB_BOOT_OPT_ELPIDA_LSB 4 + #define TB_BOOT_OPT_SDC_BEHAV_PHY_BITS 5:5 + #define TB_BOOT_OPT_SDC_BEHAV_PHY_SET 0x00000020 + #define TB_BOOT_OPT_SDC_BEHAV_PHY_CLR 0xffffffdf + #define TB_BOOT_OPT_SDC_BEHAV_PHY_MSB 5 + #define TB_BOOT_OPT_SDC_BEHAV_PHY_LSB 5 + #define TB_BOOT_OPT_NO_PRINT_BITS 6:6 + #define TB_BOOT_OPT_NO_PRINT_SET 0x00000040 + #define TB_BOOT_OPT_NO_PRINT_CLR 0xffffffbf + #define TB_BOOT_OPT_NO_PRINT_MSB 6 + #define TB_BOOT_OPT_NO_PRINT_LSB 6 + #define TB_BOOT_OPT_BOOT_HALT_BITS 7:7 + #define TB_BOOT_OPT_BOOT_HALT_SET 0x00000080 + #define TB_BOOT_OPT_BOOT_HALT_CLR 0xffffff7f + #define TB_BOOT_OPT_BOOT_HALT_MSB 7 + #define TB_BOOT_OPT_BOOT_HALT_LSB 7 + #define TB_BOOT_OPT_BANK_MODE_BITS 9:8 + #define TB_BOOT_OPT_BANK_MODE_SET 0x00000300 + #define TB_BOOT_OPT_BANK_MODE_CLR 0xfffffcff + #define TB_BOOT_OPT_BANK_MODE_MSB 9 + #define TB_BOOT_OPT_BANK_MODE_LSB 8 + #define TB_BOOT_OPT_DONT_SET_VPU_CLK_BITS 10:10 + #define TB_BOOT_OPT_DONT_SET_VPU_CLK_SET 0x00000400 + #define TB_BOOT_OPT_DONT_SET_VPU_CLK_CLR 0xfffffbff + #define TB_BOOT_OPT_DONT_SET_VPU_CLK_MSB 10 + #define TB_BOOT_OPT_DONT_SET_VPU_CLK_LSB 10 + #define TB_BOOT_OPT_TB_PRESENT_BITS 31:31 + #define TB_BOOT_OPT_TB_PRESENT_SET 0x80000000 + #define TB_BOOT_OPT_TB_PRESENT_CLR 0x7fffffff + #define TB_BOOT_OPT_TB_PRESENT_MSB 31 + #define TB_BOOT_OPT_TB_PRESENT_LSB 31 +#define TB_BOOT_SECURE_MODE HW_REGISTER_RW( 0x7e20b508 ) + #define TB_BOOT_SECURE_MODE_MASK 0x00000003 + #define TB_BOOT_SECURE_MODE_WIDTH 2 + #define TB_BOOT_SECURE_MODE_JTAG_SECURE_BITS 1:0 + #define TB_BOOT_SECURE_MODE_JTAG_SECURE_SET 0x00000003 + #define TB_BOOT_SECURE_MODE_JTAG_SECURE_CLR 0xfffffffc + #define TB_BOOT_SECURE_MODE_JTAG_SECURE_MSB 1 + #define TB_BOOT_SECURE_MODE_JTAG_SECURE_LSB 0 +#define TB_BOOT_STATUS HW_REGISTER_RW( 0x7e20b50c ) + #define TB_BOOT_STATUS_MASK 0x00000001 + #define TB_BOOT_STATUS_WIDTH 1 + #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_BITS 0:0 + #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_SET 0x00000001 + #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_CLR 0xfffffffe + #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_MSB 0 + #define TB_BOOT_STATUS_CPRMAN_PROGRAMMED_LSB 0 +#define TB_JTB_CONFIG HW_REGISTER_RW( 0x7e20b800 ) + #define TB_JTB_CONFIG_MASK 0xbfffffff + #define TB_JTB_CONFIG_WIDTH 32 + #define TB_JTB_CONFIG_SBITS_BITS 4:0 + #define TB_JTB_CONFIG_SBITS_SET 0x0000001f + #define TB_JTB_CONFIG_SBITS_CLR 0xffffffe0 + #define TB_JTB_CONFIG_SBITS_MSB 4 + #define TB_JTB_CONFIG_SBITS_LSB 0 + #define TB_JTB_CONFIG_OUT_MS_BITS 6:6 + #define TB_JTB_CONFIG_OUT_MS_SET 0x00000040 + #define TB_JTB_CONFIG_OUT_MS_CLR 0xffffffbf + #define TB_JTB_CONFIG_OUT_MS_MSB 6 + #define TB_JTB_CONFIG_OUT_MS_LSB 6 + #define TB_JTB_CONFIG_INV_CLK_BITS 7:7 + #define TB_JTB_CONFIG_INV_CLK_SET 0x00000080 + #define TB_JTB_CONFIG_INV_CLK_CLR 0xffffff7f + #define TB_JTB_CONFIG_INV_CLK_MSB 7 + #define TB_JTB_CONFIG_INV_CLK_LSB 7 + #define TB_JTB_CONFIG_TMS_RISE_BITS 8:8 + #define TB_JTB_CONFIG_TMS_RISE_SET 0x00000100 + #define TB_JTB_CONFIG_TMS_RISE_CLR 0xfffffeff + #define TB_JTB_CONFIG_TMS_RISE_MSB 8 + #define TB_JTB_CONFIG_TMS_RISE_LSB 8 + #define TB_JTB_CONFIG_TDI_RISE_BITS 9:9 + #define TB_JTB_CONFIG_TDI_RISE_SET 0x00000200 + #define TB_JTB_CONFIG_TDI_RISE_CLR 0xfffffdff + #define TB_JTB_CONFIG_TDI_RISE_MSB 9 + #define TB_JTB_CONFIG_TDI_RISE_LSB 9 + #define TB_JTB_CONFIG_TDO_RISE_BITS 10:10 + #define TB_JTB_CONFIG_TDO_RISE_SET 0x00000400 + #define TB_JTB_CONFIG_TDO_RISE_CLR 0xfffffbff + #define TB_JTB_CONFIG_TDO_RISE_MSB 10 + #define TB_JTB_CONFIG_TDO_RISE_LSB 10 + #define TB_JTB_CONFIG_ENABLE_BITS 11:11 + #define TB_JTB_CONFIG_ENABLE_SET 0x00000800 + #define TB_JTB_CONFIG_ENABLE_CLR 0xfffff7ff + #define TB_JTB_CONFIG_ENABLE_MSB 11 + #define TB_JTB_CONFIG_ENABLE_LSB 11 + #define TB_JTB_CONFIG_D_HOLD_BITS 13:12 + #define TB_JTB_CONFIG_D_HOLD_SET 0x00003000 + #define TB_JTB_CONFIG_D_HOLD_CLR 0xffffcfff + #define TB_JTB_CONFIG_D_HOLD_MSB 13 + #define TB_JTB_CONFIG_D_HOLD_LSB 12 + #define TB_JTB_CONFIG_TRSTN_BITS 14:14 + #define TB_JTB_CONFIG_TRSTN_SET 0x00004000 + #define TB_JTB_CONFIG_TRSTN_CLR 0xffffbfff + #define TB_JTB_CONFIG_TRSTN_MSB 14 + #define TB_JTB_CONFIG_TRSTN_LSB 14 + #define TB_JTB_CONFIG_SPEED_BITS 23:16 + #define TB_JTB_CONFIG_SPEED_SET 0x00ff0000 + #define TB_JTB_CONFIG_SPEED_CLR 0xff00ffff + #define TB_JTB_CONFIG_SPEED_MSB 23 + #define TB_JTB_CONFIG_SPEED_LSB 16 + #define TB_JTB_CONFIG_BITCNT_BITS 29:23 + #define TB_JTB_CONFIG_BITCNT_SET 0x3f800000 + #define TB_JTB_CONFIG_BITCNT_CLR 0xc07fffff + #define TB_JTB_CONFIG_BITCNT_MSB 29 + #define TB_JTB_CONFIG_BITCNT_LSB 23 + #define TB_JTB_CONFIG_BUSY_BITS 31:31 + #define TB_JTB_CONFIG_BUSY_SET 0x80000000 + #define TB_JTB_CONFIG_BUSY_CLR 0x7fffffff + #define TB_JTB_CONFIG_BUSY_MSB 31 + #define TB_JTB_CONFIG_BUSY_LSB 31 +#define TB_JTB_TMS HW_REGISTER_RW( 0x7e20b804 ) + #define TB_JTB_TMS_MASK 0xffffffff + #define TB_JTB_TMS_WIDTH 32 +#define TB_JTB_TDI HW_REGISTER_RW( 0x7e20b808 ) + #define TB_JTB_TDI_MASK 0xffffffff + #define TB_JTB_TDI_WIDTH 32 +#define TB_JTB_TDO HW_REGISTER_RO( 0x7e20b80c ) + #define TB_JTB_TDO_MASK 0xffffffff + #define TB_JTB_TDO_WIDTH 32 +#define TB_JTB_BITCNT HW_REGISTER_RW( 0x7e20b810 ) + #define TB_JTB_BITCNT_MASK 0x0000003f + #define TB_JTB_BITCNT_WIDTH 6 +#define TB_JTB_PORTEN HW_REGISTER_RW( 0x7e20b814 ) + #define TB_JTB_PORTEN_MASK 0x000000ff + #define TB_JTB_PORTEN_WIDTH 8 diff --git a/bcm2708_chip/thread_ctrl.h b/bcm2708_chip/thread_ctrl.h new file mode 100755 index 0000000..49f7955 --- /dev/null +++ b/bcm2708_chip/thread_ctrl.h @@ -0,0 +1,119 @@ +// This file was generated by the create_regs script +#define TH_BASE 0x18e00000 +#define TH_APB_ID 0x74687265 +#define TH_XCS HW_REGISTER_RW( 0x18e00000 ) + #define TH_XCS__MASK 0xfffffffc + #define TH_XCS__WIDTH 32 + #define TH_XCS__RESET 0x0155cb00 + #define TH_XCS_THR_READIES_MSB 31 + #define TH_XCS_THR_READIES_LSB 28 + #define TH_XCS_PREV_FIRST_S_MSB 27 + #define TH_XCS_PREV_FIRST_S_LSB 27 + #define TH_XCS_MODE_2STAGE_MSB 26 + #define TH_XCS_MODE_2STAGE_LSB 26 + #define TH_XCS_FLUSH_2STAGE_MSB 25 + #define TH_XCS_FLUSH_2STAGE_LSB 25 + #define TH_XCS_STARTUP_MSB 24 + #define TH_XCS_STARTUP_LSB 24 + #define TH_XCS_THR_STATE3_MSB 23 + #define TH_XCS_THR_STATE3_LSB 22 + #define TH_XCS_THR_STATE2_MSB 21 + #define TH_XCS_THR_STATE2_LSB 20 + #define TH_XCS_THR_STATE1_MSB 19 + #define TH_XCS_THR_STATE1_LSB 18 + #define TH_XCS_THR_STATE0_MSB 17 + #define TH_XCS_THR_STATE0_LSB 16 + #define TH_XCS_SYS_STATE_MSB 15 + #define TH_XCS_SYS_STATE_LSB 14 + #define TH_XCS_NEXT_READY_MSB 13 + #define TH_XCS_NEXT_READY_LSB 12 + #define TH_XCS_PREV_SYS_MSB 11 + #define TH_XCS_PREV_SYS_LSB 11 + #define TH_XCS_PREV_IDLE_MSB 10 + #define TH_XCS_PREV_IDLE_LSB 10 + #define TH_XCS_PREV_THREAD_MSB 9 + #define TH_XCS_PREV_THREAD_LSB 8 + #define TH_XCS_THREAD_HWEN_MSB 7 + #define TH_XCS_THREAD_HWEN_LSB 4 + #define TH_XCS_THREAD_SYSFL_MSB 3 + #define TH_XCS_THREAD_SYSFL_LSB 3 + #define TH_XCS_THREAD_SYSIN_MSB 2 + #define TH_XCS_THREAD_SYSIN_LSB 2 +#define TH_XCFG HW_REGISTER_RW( 0x18e00004 ) + #define TH_XCFG__MASK 0xffffffff + #define TH_XCFG__WIDTH 32 + #define TH_XCFG__RESET 0000000000 + #define TH_XCFG_SW_ENS_MSB 11 + #define TH_XCFG_SW_ENS_LSB 8 + #define TH_XCFG_SW_SYSFLUSH_MSB 7 + #define TH_XCFG_SW_SYSFLUSH_LSB 7 + #define TH_XCFG_SW_SYSINTR_MSB 6 + #define TH_XCFG_SW_SYSINTR_LSB 6 + #define TH_XCFG_SW_EN_SEL_MSB 4 + #define TH_XCFG_SW_EN_SEL_LSB 4 + #define TH_XCFG_SW_FLUSH_SEL_MSB 3 + #define TH_XCFG_SW_FLUSH_SEL_LSB 3 + #define TH_XCFG_SW_INTR_SEL_MSB 2 + #define TH_XCFG_SW_INTR_SEL_LSB 2 + #define TH_XCFG_THR_EN_MSB 0 + #define TH_XCFG_THR_EN_LSB 0 +#define TH_XSTPC HW_REGISTER_RW( 0x18e00008 ) + #define TH_XSTPC__MASK 0xfffffffe + #define TH_XSTPC__WIDTH 32 + #define TH_XSTPC__RESET 0000000000 + #define TH_XSTPC__MSB 31 + #define TH_XSTPC__LSB 1 +#define TH_XITPC HW_REGISTER_RW( 0x18e0000c ) + #define TH_XITPC__MASK 0xfffffffe + #define TH_XITPC__WIDTH 32 + #define TH_XITPC__RESET 0000000000 + #define TH_XITPC__MSB 31 + #define TH_XITPC__LSB 1 +#define TH_XT0PC HW_REGISTER_RW( 0x18e00010 ) + #define TH_XT0PC__MASK 0xfffffffe + #define TH_XT0PC__WIDTH 32 + #define TH_XT0PC__RESET 0000000000 + #define TH_XT0PC__MSB 31 + #define TH_XT0PC__LSB 1 +#define TH_XT0UD HW_REGISTER_RW( 0x18e00014 ) + #define TH_XT0UD__MASK 0xffffffff + #define TH_XT0UD__WIDTH 32 + #define TH_XT0UD__RESET 0000000000 + #define TH_XT0UD__MSB 31 + #define TH_XT0UD__LSB 0 +#define TH_XT1PC HW_REGISTER_RW( 0x18e00018 ) + #define TH_XT1PC__MASK 0xfffffffe + #define TH_XT1PC__WIDTH 32 + #define TH_XT1PC__RESET 0000000000 + #define TH_XT1PC__MSB 31 + #define TH_XT1PC__LSB 1 +#define TH_XT1UD HW_REGISTER_RW( 0x18e0001c ) + #define TH_XT1UD__MASK 0xffffffff + #define TH_XT1UD__WIDTH 32 + #define TH_XT1UD__RESET 0000000000 + #define TH_XT1UD__MSB 31 + #define TH_XT1UD__LSB 0 +#define TH_XT2PC HW_REGISTER_RW( 0x18e00020 ) + #define TH_XT2PC__MASK 0xfffffffe + #define TH_XT2PC__WIDTH 32 + #define TH_XT2PC__RESET 0000000000 + #define TH_XT2PC__MSB 31 + #define TH_XT2PC__LSB 1 +#define TH_XT2UD HW_REGISTER_RW( 0x18e00024 ) + #define TH_XT2UD__MASK 0xffffffff + #define TH_XT2UD__WIDTH 32 + #define TH_XT2UD__RESET 0000000000 + #define TH_XT2UD__MSB 31 + #define TH_XT2UD__LSB 0 +#define TH_XT3PC HW_REGISTER_RW( 0x18e00028 ) + #define TH_XT3PC__MASK 0xfffffffe + #define TH_XT3PC__WIDTH 32 + #define TH_XT3PC__RESET 0000000000 + #define TH_XT3PC__MSB 31 + #define TH_XT3PC__LSB 1 +#define TH_XT3UD HW_REGISTER_RW( 0x18e0002c ) + #define TH_XT3UD__MASK 0xffffffff + #define TH_XT3UD__WIDTH 32 + #define TH_XT3UD__RESET 0000000000 + #define TH_XT3UD__MSB 31 + #define TH_XT3UD__LSB 0 diff --git a/bcm2708_chip/timer.h b/bcm2708_chip/timer.h new file mode 100755 index 0000000..ae2ef0d --- /dev/null +++ b/bcm2708_chip/timer.h @@ -0,0 +1,32 @@ +// This file was generated by the create_regs script +#define ST_BASE 0x7e003000 +#define ST_CS HW_REGISTER_RW( 0x7e003000 ) + #define ST_CS_MASK 0xffffffff + #define ST_CS_WIDTH 32 + #define ST_CS_RESET 0000000000 +#if defined(__CC_ARM) +#define ST_CLO vcos_getmicrosecs() +#else +#define ST_CLO HW_REGISTER_RO( 0x7e003004 ) +#endif + #define ST_CLO_MASK 0xffffffff + #define ST_CLO_WIDTH 32 +#define ST_CHI HW_REGISTER_RO( 0x7e003008 ) + #define ST_CHI_MASK 0xffffffff + #define ST_CHI_WIDTH 32 +#define ST_C0 HW_REGISTER_RW( 0x7e00300c ) + #define ST_C0_MASK 0xffffffff + #define ST_C0_WIDTH 32 + #define ST_C0_RESET 0000000000 +#define ST_C1 HW_REGISTER_RW( 0x7e003010 ) + #define ST_C1_MASK 0xffffffff + #define ST_C1_WIDTH 32 + #define ST_C1_RESET 0000000000 +#define ST_C2 HW_REGISTER_RW( 0x7e003014 ) + #define ST_C2_MASK 0xffffffff + #define ST_C2_WIDTH 32 + #define ST_C2_RESET 0000000000 +#define ST_C3 HW_REGISTER_RW( 0x7e003018 ) + #define ST_C3_MASK 0xffffffff + #define ST_C3_WIDTH 32 + #define ST_C3_RESET 0000000000 diff --git a/bcm2708_chip/txp.h b/bcm2708_chip/txp.h new file mode 100755 index 0000000..0bedda4 --- /dev/null +++ b/bcm2708_chip/txp.h @@ -0,0 +1,137 @@ +// This file was generated by the create_regs script +#define TXP_BASE 0x7e004000 +#define TXP_APB_ID 0x20763374 +#define TXP_DST_PTR HW_REGISTER_RW( 0x7e004000 ) + #define TXP_DST_PTR_MASK 0xfffffffe + #define TXP_DST_PTR_WIDTH 32 +#define TXP_DST_PITCH HW_REGISTER_RW( 0x7e004004 ) + #define TXP_DST_PITCH_MASK 0xfffffff0 + #define TXP_DST_PITCH_WIDTH 32 +#define TXP_DIM HW_REGISTER_RW( 0x7e004008 ) + #define TXP_DIM_MASK 0x0fff0fff + #define TXP_DIM_WIDTH 28 + #define TXP_DIM_HEIGHT_BITS 27:16 + #define TXP_DIM_HEIGHT_SET 0x0fff0000 + #define TXP_DIM_HEIGHT_CLR 0xf000ffff + #define TXP_DIM_HEIGHT_MSB 27 + #define TXP_DIM_HEIGHT_LSB 16 + #define TXP_DIM_HEIGHT_RESET 0x0 + #define TXP_DIM_WIDTH_BITS 11:0 + #define TXP_DIM_WIDTH_SET 0x00000fff + #define TXP_DIM_WIDTH_CLR 0xfffff000 + #define TXP_DIM_WIDTH_MSB 11 + #define TXP_DIM_WIDTH_LSB 0 + #define TXP_DIM_WIDTH_RESET 0x0 +#define TXP_CTRL HW_REGISTER_RW( 0x7e00400c ) + #define TXP_CTRL_MASK 0xffffffff + #define TXP_CTRL_WIDTH 32 + #define TXP_CTRL_PILOT_BITS 31:24 + #define TXP_CTRL_PILOT_SET 0xff000000 + #define TXP_CTRL_PILOT_CLR 0x00ffffff + #define TXP_CTRL_PILOT_MSB 31 + #define TXP_CTRL_PILOT_LSB 24 + #define TXP_CTRL_PILOT_RESET 0x54 + #define TXP_CTRL_VERSION_BITS 23:22 + #define TXP_CTRL_VERSION_SET 0x00c00000 + #define TXP_CTRL_VERSION_CLR 0xff3fffff + #define TXP_CTRL_VERSION_MSB 23 + #define TXP_CTRL_VERSION_LSB 22 + #define TXP_CTRL_VERSION_RESET 0x1 + #define TXP_CTRL_POWERDOWN_BITS 21:21 + #define TXP_CTRL_POWERDOWN_SET 0x00200000 + #define TXP_CTRL_POWERDOWN_CLR 0xffdfffff + #define TXP_CTRL_POWERDOWN_MSB 21 + #define TXP_CTRL_POWERDOWN_LSB 21 + #define TXP_CTRL_POWERDOWN_RESET 0x0 + #define TXP_CTRL_ALPHA_ENABLE_BITS 20:20 + #define TXP_CTRL_ALPHA_ENABLE_SET 0x00100000 + #define TXP_CTRL_ALPHA_ENABLE_CLR 0xffefffff + #define TXP_CTRL_ALPHA_ENABLE_MSB 20 + #define TXP_CTRL_ALPHA_ENABLE_LSB 20 + #define TXP_CTRL_BWE_BITS 19:16 + #define TXP_CTRL_BWE_SET 0x000f0000 + #define TXP_CTRL_BWE_CLR 0xfff0ffff + #define TXP_CTRL_BWE_MSB 19 + #define TXP_CTRL_BWE_LSB 16 + #define TXP_CTRL_BWE_RESET 0xf + #define TXP_CTRL_VSTART_AT_EOF_BITS 15:15 + #define TXP_CTRL_VSTART_AT_EOF_SET 0x00008000 + #define TXP_CTRL_VSTART_AT_EOF_CLR 0xffff7fff + #define TXP_CTRL_VSTART_AT_EOF_MSB 15 + #define TXP_CTRL_VSTART_AT_EOF_LSB 15 + #define TXP_CTRL_ABORT_BITS 14:14 + #define TXP_CTRL_ABORT_SET 0x00004000 + #define TXP_CTRL_ABORT_CLR 0xffffbfff + #define TXP_CTRL_ABORT_MSB 14 + #define TXP_CTRL_ABORT_LSB 14 + #define TXP_CTRL_DITHER_BITS 13:13 + #define TXP_CTRL_DITHER_SET 0x00002000 + #define TXP_CTRL_DITHER_CLR 0xffffdfff + #define TXP_CTRL_DITHER_MSB 13 + #define TXP_CTRL_DITHER_LSB 13 + #define TXP_CTRL_ALPHA_INVERT_BITS 12:12 + #define TXP_CTRL_ALPHA_INVERT_SET 0x00001000 + #define TXP_CTRL_ALPHA_INVERT_CLR 0xffffefff + #define TXP_CTRL_ALPHA_INVERT_MSB 12 + #define TXP_CTRL_ALPHA_INVERT_LSB 12 + #define TXP_CTRL_FORMAT_BITS 11:8 + #define TXP_CTRL_FORMAT_SET 0x00000f00 + #define TXP_CTRL_FORMAT_CLR 0xfffff0ff + #define TXP_CTRL_FORMAT_MSB 11 + #define TXP_CTRL_FORMAT_LSB 8 + #define TXP_CTRL_LINEAR_UTILE_BITS 7:7 + #define TXP_CTRL_LINEAR_UTILE_SET 0x00000080 + #define TXP_CTRL_LINEAR_UTILE_CLR 0xffffff7f + #define TXP_CTRL_LINEAR_UTILE_MSB 7 + #define TXP_CTRL_LINEAR_UTILE_LSB 7 + #define TXP_CTRL_TRANSPOSE_BITS 6:6 + #define TXP_CTRL_TRANSPOSE_SET 0x00000040 + #define TXP_CTRL_TRANSPOSE_CLR 0xffffffbf + #define TXP_CTRL_TRANSPOSE_MSB 6 + #define TXP_CTRL_TRANSPOSE_LSB 6 + #define TXP_CTRL_TFORMAT_BITS 5:5 + #define TXP_CTRL_TFORMAT_SET 0x00000020 + #define TXP_CTRL_TFORMAT_CLR 0xffffffdf + #define TXP_CTRL_TFORMAT_MSB 5 + #define TXP_CTRL_TFORMAT_LSB 5 + #define TXP_CTRL_TEST_MODE_BITS 4:4 + #define TXP_CTRL_TEST_MODE_SET 0x00000010 + #define TXP_CTRL_TEST_MODE_CLR 0xffffffef + #define TXP_CTRL_TEST_MODE_MSB 4 + #define TXP_CTRL_TEST_MODE_LSB 4 + #define TXP_CTRL_FIELD_BITS 3:3 + #define TXP_CTRL_FIELD_SET 0x00000008 + #define TXP_CTRL_FIELD_CLR 0xfffffff7 + #define TXP_CTRL_FIELD_MSB 3 + #define TXP_CTRL_FIELD_LSB 3 + #define TXP_CTRL_EI_BITS 2:2 + #define TXP_CTRL_EI_SET 0x00000004 + #define TXP_CTRL_EI_CLR 0xfffffffb + #define TXP_CTRL_EI_MSB 2 + #define TXP_CTRL_EI_LSB 2 + #define TXP_CTRL_BUSY_BITS 1:1 + #define TXP_CTRL_BUSY_SET 0x00000002 + #define TXP_CTRL_BUSY_CLR 0xfffffffd + #define TXP_CTRL_BUSY_MSB 1 + #define TXP_CTRL_BUSY_LSB 1 + #define TXP_CTRL_GO_BITS 0:0 + #define TXP_CTRL_GO_SET 0x00000001 + #define TXP_CTRL_GO_CLR 0xfffffffe + #define TXP_CTRL_GO_MSB 0 + #define TXP_CTRL_GO_LSB 0 +#define TXP_PROGRESS HW_REGISTER_RO( 0x7e004010 ) + #define TXP_PROGRESS_MASK 0x00000fff + #define TXP_PROGRESS_WIDTH 12 + #define TXP_PROGRESS_LINES_BITS 11:0 + #define TXP_PROGRESS_LINES_SET 0x00000fff + #define TXP_PROGRESS_LINES_CLR 0xfffff000 + #define TXP_PROGRESS_LINES_MSB 11 + #define TXP_PROGRESS_LINES_LSB 0 +#define TXP_XTRA HW_REGISTER_RW( 0x7e004018 ) + #define TXP_XTRA_MASK 0x00000001 + #define TXP_XTRA_WIDTH 1 + #define TXP_XTRA_NOSTBY_BITS 0:0 + #define TXP_XTRA_NOSTBY_SET 0x00000001 + #define TXP_XTRA_NOSTBY_CLR 0xfffffffe + #define TXP_XTRA_NOSTBY_MSB 0 + #define TXP_XTRA_NOSTBY_LSB 0 diff --git a/bcm2708_chip/uart.h b/bcm2708_chip/uart.h new file mode 100755 index 0000000..878036d --- /dev/null +++ b/bcm2708_chip/uart.h @@ -0,0 +1,169 @@ +// This file was generated by the create_regs script +#define UART_BASE 0x7e201000 +#define UART_RBRTHRDLL HW_REGISTER_RW( 0x7e201000 ) +#define UART_IERDLM HW_REGISTER_RW( 0x7e201004 ) +#define UART_IIR_FCR HW_REGISTER_RW( 0x7e201008 ) +#define UART_LCR HW_REGISTER_RW( 0x7e20100c ) + #define UART_LCR_MASK 0x000000ff + #define UART_LCR_WIDTH 8 + #define UART_LCR_RESET 0000000000 + #define UART_LCR_DLAB_BITS 7:7 + #define UART_LCR_DLAB_SET 0x00000080 + #define UART_LCR_DLAB_CLR 0xffffff7f + #define UART_LCR_DLAB_MSB 7 + #define UART_LCR_DLAB_LSB 7 + #define UART_LCR_SBC_BITS 6:6 + #define UART_LCR_SBC_SET 0x00000040 + #define UART_LCR_SBC_CLR 0xffffffbf + #define UART_LCR_SBC_MSB 6 + #define UART_LCR_SBC_LSB 6 + #define UART_LCR_SP_BITS 5:5 + #define UART_LCR_SP_SET 0x00000020 + #define UART_LCR_SP_CLR 0xffffffdf + #define UART_LCR_SP_MSB 5 + #define UART_LCR_SP_LSB 5 + #define UART_LCR_EPS_BITS 4:4 + #define UART_LCR_EPS_SET 0x00000010 + #define UART_LCR_EPS_CLR 0xffffffef + #define UART_LCR_EPS_MSB 4 + #define UART_LCR_EPS_LSB 4 + #define UART_LCR_PEN_BITS 3:3 + #define UART_LCR_PEN_SET 0x00000008 + #define UART_LCR_PEN_CLR 0xfffffff7 + #define UART_LCR_PEN_MSB 3 + #define UART_LCR_PEN_LSB 3 + #define UART_LCR_STB_BITS 2:2 + #define UART_LCR_STB_SET 0x00000004 + #define UART_LCR_STB_CLR 0xfffffffb + #define UART_LCR_STB_MSB 2 + #define UART_LCR_STB_LSB 2 + #define UART_LCR_WLS_BITS 1:0 + #define UART_LCR_WLS_SET 0x00000003 + #define UART_LCR_WLS_CLR 0xfffffffc + #define UART_LCR_WLS_MSB 1 + #define UART_LCR_WLS_LSB 0 + #define UART_LCR_LOOP_BITS 4:4 + #define UART_LCR_LOOP_SET 0x00000010 + #define UART_LCR_LOOP_CLR 0xffffffef + #define UART_LCR_LOOP_MSB 4 + #define UART_LCR_LOOP_LSB 4 + #define UART_LCR_OUT2_BITS 3:3 + #define UART_LCR_OUT2_SET 0x00000008 + #define UART_LCR_OUT2_CLR 0xfffffff7 + #define UART_LCR_OUT2_MSB 3 + #define UART_LCR_OUT2_LSB 3 + #define UART_LCR_OUT1_BITS 2:2 + #define UART_LCR_OUT1_SET 0x00000004 + #define UART_LCR_OUT1_CLR 0xfffffffb + #define UART_LCR_OUT1_MSB 2 + #define UART_LCR_OUT1_LSB 2 + #define UART_LCR_RTS_BITS 1:1 + #define UART_LCR_RTS_SET 0x00000002 + #define UART_LCR_RTS_CLR 0xfffffffd + #define UART_LCR_RTS_MSB 1 + #define UART_LCR_RTS_LSB 1 + #define UART_LCR_DTR_BITS 0:0 + #define UART_LCR_DTR_SET 0x00000001 + #define UART_LCR_DTR_CLR 0xfffffffe + #define UART_LCR_DTR_MSB 0 + #define UART_LCR_DTR_LSB 0 +#define UART_MCR HW_REGISTER_RW( 0x7e201010 ) + #define UART_MCR_MASK 0x0000001f + #define UART_MCR_WIDTH 5 + #define UART_MCR_RESET 0000000000 +#define UART_LSR HW_REGISTER_RW( 0x7e201014 ) + #define UART_LSR_MASK 0x000000ff + #define UART_LSR_WIDTH 8 + #define UART_LSR_RESET 0000000000 + #define UART_LSR_RFE_BITS 7:7 + #define UART_LSR_RFE_SET 0x00000080 + #define UART_LSR_RFE_CLR 0xffffff7f + #define UART_LSR_RFE_MSB 7 + #define UART_LSR_RFE_LSB 7 + #define UART_LSR_TEMT_BITS 6:6 + #define UART_LSR_TEMT_SET 0x00000040 + #define UART_LSR_TEMT_CLR 0xffffffbf + #define UART_LSR_TEMT_MSB 6 + #define UART_LSR_TEMT_LSB 6 + #define UART_LSR_THRE_BITS 5:5 + #define UART_LSR_THRE_SET 0x00000020 + #define UART_LSR_THRE_CLR 0xffffffdf + #define UART_LSR_THRE_MSB 5 + #define UART_LSR_THRE_LSB 5 + #define UART_LSR_BI_BITS 4:4 + #define UART_LSR_BI_SET 0x00000010 + #define UART_LSR_BI_CLR 0xffffffef + #define UART_LSR_BI_MSB 4 + #define UART_LSR_BI_LSB 4 + #define UART_LSR_FE_BITS 3:3 + #define UART_LSR_FE_SET 0x00000008 + #define UART_LSR_FE_CLR 0xfffffff7 + #define UART_LSR_FE_MSB 3 + #define UART_LSR_FE_LSB 3 + #define UART_LSR_PE_BITS 2:2 + #define UART_LSR_PE_SET 0x00000004 + #define UART_LSR_PE_CLR 0xfffffffb + #define UART_LSR_PE_MSB 2 + #define UART_LSR_PE_LSB 2 + #define UART_LSR_OE_BITS 1:1 + #define UART_LSR_OE_SET 0x00000002 + #define UART_LSR_OE_CLR 0xfffffffd + #define UART_LSR_OE_MSB 1 + #define UART_LSR_OE_LSB 1 + #define UART_LSR_DR_BITS 0:0 + #define UART_LSR_DR_SET 0x00000001 + #define UART_LSR_DR_CLR 0xfffffffe + #define UART_LSR_DR_MSB 0 + #define UART_LSR_DR_LSB 0 +#define UART_MSR HW_REGISTER_RW( 0x7e201018 ) + #define UART_MSR_MASK 0x000000ff + #define UART_MSR_WIDTH 8 + #define UART_MSR_RESET 0000000000 + #define UART_MSR_DCD_BITS 7:7 + #define UART_MSR_DCD_SET 0x00000080 + #define UART_MSR_DCD_CLR 0xffffff7f + #define UART_MSR_DCD_MSB 7 + #define UART_MSR_DCD_LSB 7 + #define UART_MSR_RI_BITS 6:6 + #define UART_MSR_RI_SET 0x00000040 + #define UART_MSR_RI_CLR 0xffffffbf + #define UART_MSR_RI_MSB 6 + #define UART_MSR_RI_LSB 6 + #define UART_MSR_DSR_BITS 5:5 + #define UART_MSR_DSR_SET 0x00000020 + #define UART_MSR_DSR_CLR 0xffffffdf + #define UART_MSR_DSR_MSB 5 + #define UART_MSR_DSR_LSB 5 + #define UART_MSR_CTS_BITS 4:4 + #define UART_MSR_CTS_SET 0x00000010 + #define UART_MSR_CTS_CLR 0xffffffef + #define UART_MSR_CTS_MSB 4 + #define UART_MSR_CTS_LSB 4 + #define UART_MSR_DDCD_BITS 3:3 + #define UART_MSR_DDCD_SET 0x00000008 + #define UART_MSR_DDCD_CLR 0xfffffff7 + #define UART_MSR_DDCD_MSB 3 + #define UART_MSR_DDCD_LSB 3 + #define UART_MSR_TERI_BITS 2:2 + #define UART_MSR_TERI_SET 0x00000004 + #define UART_MSR_TERI_CLR 0xfffffffb + #define UART_MSR_TERI_MSB 2 + #define UART_MSR_TERI_LSB 2 + #define UART_MSR_DDSR_BITS 1:1 + #define UART_MSR_DDSR_SET 0x00000002 + #define UART_MSR_DDSR_CLR 0xfffffffd + #define UART_MSR_DDSR_MSB 1 + #define UART_MSR_DDSR_LSB 1 + #define UART_MSR_DCTS_BITS 0:0 + #define UART_MSR_DCTS_SET 0x00000001 + #define UART_MSR_DCTS_CLR 0xfffffffe + #define UART_MSR_DCTS_MSB 0 + #define UART_MSR_DCTS_LSB 0 +#define UART_SCR HW_REGISTER_RW( 0x7e20101c ) + #define UART_SCR_MASK 0x000000ff + #define UART_SCR_WIDTH 8 + #define UART_SCR_RESET 0000000000 +#define UART_EN HW_REGISTER_RW( 0x7e201020 ) + #define UART_EN_MASK 0x00000002 + #define UART_EN_WIDTH 2 + #define UART_EN_RESET 0000000000 diff --git a/bcm2708_chip/usb.h b/bcm2708_chip/usb.h new file mode 100755 index 0000000..8dec742 --- /dev/null +++ b/bcm2708_chip/usb.h @@ -0,0 +1,2889 @@ +// This file was generated by the create_regs script +#define USB_BASE 0x7e980000 +#define USB_APB_ID 0x75736230 +#define USB_GOTGCTL HW_REGISTER_RW( 0x7e980000 ) + #define USB_GOTGCTL_MASK 0x000f0f03 + #define USB_GOTGCTL_WIDTH 20 + #define USB_GOTGCTL_B_SES_VLD_BITS 19:19 + #define USB_GOTGCTL_B_SES_VLD_SET 0x00080000 + #define USB_GOTGCTL_B_SES_VLD_CLR 0xfff7ffff + #define USB_GOTGCTL_B_SES_VLD_MSB 19 + #define USB_GOTGCTL_B_SES_VLD_LSB 19 + #define USB_GOTGCTL_B_SES_VLD_RESET 0x0 + #define USB_GOTGCTL_A_SES_VLD_BITS 18:18 + #define USB_GOTGCTL_A_SES_VLD_SET 0x00040000 + #define USB_GOTGCTL_A_SES_VLD_CLR 0xfffbffff + #define USB_GOTGCTL_A_SES_VLD_MSB 18 + #define USB_GOTGCTL_A_SES_VLD_LSB 18 + #define USB_GOTGCTL_A_SES_VLD_RESET 0x0 + #define USB_GOTGCTL_DBNC_TIME_BITS 17:17 + #define USB_GOTGCTL_DBNC_TIME_SET 0x00020000 + #define USB_GOTGCTL_DBNC_TIME_CLR 0xfffdffff + #define USB_GOTGCTL_DBNC_TIME_MSB 17 + #define USB_GOTGCTL_DBNC_TIME_LSB 17 + #define USB_GOTGCTL_DBNC_TIME_RESET 0x0 + #define USB_GOTGCTL_CON_ID_STS_BITS 16:16 + #define USB_GOTGCTL_CON_ID_STS_SET 0x00010000 + #define USB_GOTGCTL_CON_ID_STS_CLR 0xfffeffff + #define USB_GOTGCTL_CON_ID_STS_MSB 16 + #define USB_GOTGCTL_CON_ID_STS_LSB 16 + #define USB_GOTGCTL_CON_ID_STS_RESET 0x0 + #define USB_GOTGCTL_DEV_HNP_EN_BITS 11:11 + #define USB_GOTGCTL_DEV_HNP_EN_SET 0x00000800 + #define USB_GOTGCTL_DEV_HNP_EN_CLR 0xfffff7ff + #define USB_GOTGCTL_DEV_HNP_EN_MSB 11 + #define USB_GOTGCTL_DEV_HNP_EN_LSB 11 + #define USB_GOTGCTL_DEV_HNP_EN_RESET 0x0 + #define USB_GOTGCTL_HST_SET_HNP_EN_BITS 10:10 + #define USB_GOTGCTL_HST_SET_HNP_EN_SET 0x00000400 + #define USB_GOTGCTL_HST_SET_HNP_EN_CLR 0xfffffbff + #define USB_GOTGCTL_HST_SET_HNP_EN_MSB 10 + #define USB_GOTGCTL_HST_SET_HNP_EN_LSB 10 + #define USB_GOTGCTL_HST_SET_HNP_EN_RESET 0x0 + #define USB_GOTGCTL_HNP_REQ_BITS 9:9 + #define USB_GOTGCTL_HNP_REQ_SET 0x00000200 + #define USB_GOTGCTL_HNP_REQ_CLR 0xfffffdff + #define USB_GOTGCTL_HNP_REQ_MSB 9 + #define USB_GOTGCTL_HNP_REQ_LSB 9 + #define USB_GOTGCTL_HNP_REQ_RESET 0x0 + #define USB_GOTGCTL_HST_NEG_SCS_BITS 8:8 + #define USB_GOTGCTL_HST_NEG_SCS_SET 0x00000100 + #define USB_GOTGCTL_HST_NEG_SCS_CLR 0xfffffeff + #define USB_GOTGCTL_HST_NEG_SCS_MSB 8 + #define USB_GOTGCTL_HST_NEG_SCS_LSB 8 + #define USB_GOTGCTL_HST_NEG_SCS_RESET 0x0 + #define USB_GOTGCTL_SES_REQ_BITS 1:1 + #define USB_GOTGCTL_SES_REQ_SET 0x00000002 + #define USB_GOTGCTL_SES_REQ_CLR 0xfffffffd + #define USB_GOTGCTL_SES_REQ_MSB 1 + #define USB_GOTGCTL_SES_REQ_LSB 1 + #define USB_GOTGCTL_SES_REQ_RESET 0x0 + #define USB_GOTGCTL_SES_REQ_SCS_BITS 0:0 + #define USB_GOTGCTL_SES_REQ_SCS_SET 0x00000001 + #define USB_GOTGCTL_SES_REQ_SCS_CLR 0xfffffffe + #define USB_GOTGCTL_SES_REQ_SCS_MSB 0 + #define USB_GOTGCTL_SES_REQ_SCS_LSB 0 + #define USB_GOTGCTL_SES_REQ_SCS_RESET 0x0 +#define USB_GOTGINT HW_REGISTER_RW( 0x7e980004 ) + #define USB_GOTGINT_MASK 0x000e0304 + #define USB_GOTGINT_WIDTH 20 + #define USB_GOTGINT_DBNCE_DONE_BITS 19:19 + #define USB_GOTGINT_DBNCE_DONE_SET 0x00080000 + #define USB_GOTGINT_DBNCE_DONE_CLR 0xfff7ffff + #define USB_GOTGINT_DBNCE_DONE_MSB 19 + #define USB_GOTGINT_DBNCE_DONE_LSB 19 + #define USB_GOTGINT_DBNCE_DONE_RESET 0x0 + #define USB_GOTGINT_A_DEV_TOUT_CHG_BITS 18:18 + #define USB_GOTGINT_A_DEV_TOUT_CHG_SET 0x00040000 + #define USB_GOTGINT_A_DEV_TOUT_CHG_CLR 0xfffbffff + #define USB_GOTGINT_A_DEV_TOUT_CHG_MSB 18 + #define USB_GOTGINT_A_DEV_TOUT_CHG_LSB 18 + #define USB_GOTGINT_A_DEV_TOUT_CHG_RESET 0x0 + #define USB_GOTGINT_HST_NEG_DET_BITS 17:17 + #define USB_GOTGINT_HST_NEG_DET_SET 0x00020000 + #define USB_GOTGINT_HST_NEG_DET_CLR 0xfffdffff + #define USB_GOTGINT_HST_NEG_DET_MSB 17 + #define USB_GOTGINT_HST_NEG_DET_LSB 17 + #define USB_GOTGINT_HST_NEG_DET_RESET 0x0 + #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_BITS 9:9 + #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_SET 0x00000200 + #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_CLR 0xfffffdff + #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_MSB 9 + #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_LSB 9 + #define USB_GOTGINT_HST_NEG_SUC_STS_CHG_RESET 0x0 + #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_BITS 8:8 + #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_SET 0x00000100 + #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_CLR 0xfffffeff + #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_MSB 8 + #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_LSB 8 + #define USB_GOTGINT_SES_REQ_SUC_STS_CHG_RESET 0x0 + #define USB_GOTGINT_SES_END_DET_BITS 2:2 + #define USB_GOTGINT_SES_END_DET_SET 0x00000004 + #define USB_GOTGINT_SES_END_DET_CLR 0xfffffffb + #define USB_GOTGINT_SES_END_DET_MSB 2 + #define USB_GOTGINT_SES_END_DET_LSB 2 + #define USB_GOTGINT_SES_END_DET_RESET 0x0 +#define USB_GAHBCFG HW_REGISTER_RW( 0x7e980008 ) + #define USB_GAHBCFG_MASK 0x000001bf + #define USB_GAHBCFG_WIDTH 9 + #define USB_GAHBCFG_P_TXF_EMP_LVL_BITS 8:8 + #define USB_GAHBCFG_P_TXF_EMP_LVL_SET 0x00000100 + #define USB_GAHBCFG_P_TXF_EMP_LVL_CLR 0xfffffeff + #define USB_GAHBCFG_P_TXF_EMP_LVL_MSB 8 + #define USB_GAHBCFG_P_TXF_EMP_LVL_LSB 8 + #define USB_GAHBCFG_P_TXF_EMP_LVL_RESET 0x0 + #define USB_GAHBCFG_NP_TXF_EMP_LVL_BITS 7:7 + #define USB_GAHBCFG_NP_TXF_EMP_LVL_SET 0x00000080 + #define USB_GAHBCFG_NP_TXF_EMP_LVL_CLR 0xffffff7f + #define USB_GAHBCFG_NP_TXF_EMP_LVL_MSB 7 + #define USB_GAHBCFG_NP_TXF_EMP_LVL_LSB 7 + #define USB_GAHBCFG_NP_TXF_EMP_LVL_RESET 0x0 + #define USB_GAHBCFG_DMA_EN_BITS 5:5 + #define USB_GAHBCFG_DMA_EN_SET 0x00000020 + #define USB_GAHBCFG_DMA_EN_CLR 0xffffffdf + #define USB_GAHBCFG_DMA_EN_MSB 5 + #define USB_GAHBCFG_DMA_EN_LSB 5 + #define USB_GAHBCFG_DMA_EN_RESET 0x0 + #define USB_GAHBCFG_H_BST_LEN_BITS 4:1 + #define USB_GAHBCFG_H_BST_LEN_SET 0x0000001e + #define USB_GAHBCFG_H_BST_LEN_CLR 0xffffffe1 + #define USB_GAHBCFG_H_BST_LEN_MSB 4 + #define USB_GAHBCFG_H_BST_LEN_LSB 1 + #define USB_GAHBCFG_H_BST_LEN_RESET 0x0 + #define USB_GAHBCFG_GLBL_INTR_MSK_BITS 0:0 + #define USB_GAHBCFG_GLBL_INTR_MSK_SET 0x00000001 + #define USB_GAHBCFG_GLBL_INTR_MSK_CLR 0xfffffffe + #define USB_GAHBCFG_GLBL_INTR_MSK_MSB 0 + #define USB_GAHBCFG_GLBL_INTR_MSK_LSB 0 + #define USB_GAHBCFG_GLBL_INTR_MSK_RESET 0x0 +#define USB_GUSBCFG HW_REGISTER_RW( 0x7e98000c ) + #define USB_GUSBCFG_MASK 0xe3ffbfff + #define USB_GUSBCFG_WIDTH 32 + #define USB_GUSBCFG_CORRUPT_TX_BITS 31:31 + #define USB_GUSBCFG_CORRUPT_TX_SET 0x80000000 + #define USB_GUSBCFG_CORRUPT_TX_CLR 0x7fffffff + #define USB_GUSBCFG_CORRUPT_TX_MSB 31 + #define USB_GUSBCFG_CORRUPT_TX_LSB 31 + #define USB_GUSBCFG_CORRUPT_TX_RESET 0x0 + #define USB_GUSBCFG_FORCE_DEV_MODE_BITS 30:30 + #define USB_GUSBCFG_FORCE_DEV_MODE_SET 0x40000000 + #define USB_GUSBCFG_FORCE_DEV_MODE_CLR 0xbfffffff + #define USB_GUSBCFG_FORCE_DEV_MODE_MSB 30 + #define USB_GUSBCFG_FORCE_DEV_MODE_LSB 30 + #define USB_GUSBCFG_FORCE_DEV_MODE_RESET 0x0 + #define USB_GUSBCFG_FORCE_HST_MODE_BITS 29:29 + #define USB_GUSBCFG_FORCE_HST_MODE_SET 0x20000000 + #define USB_GUSBCFG_FORCE_HST_MODE_CLR 0xdfffffff + #define USB_GUSBCFG_FORCE_HST_MODE_MSB 29 + #define USB_GUSBCFG_FORCE_HST_MODE_LSB 29 + #define USB_GUSBCFG_FORCE_HST_MODE_RESET 0x0 + #define USB_GUSBCFG_ULPI_IF_PROT_DIS_BITS 25:25 + #define USB_GUSBCFG_ULPI_IF_PROT_DIS_SET 0x02000000 + #define USB_GUSBCFG_ULPI_IF_PROT_DIS_CLR 0xfdffffff + #define USB_GUSBCFG_ULPI_IF_PROT_DIS_MSB 25 + #define USB_GUSBCFG_ULPI_IF_PROT_DIS_LSB 25 + #define USB_GUSBCFG_ULPI_IF_PROT_DIS_RESET 0x0 + #define USB_GUSBCFG_IND_PASS_THRU_BITS 24:24 + #define USB_GUSBCFG_IND_PASS_THRU_SET 0x01000000 + #define USB_GUSBCFG_IND_PASS_THRU_CLR 0xfeffffff + #define USB_GUSBCFG_IND_PASS_THRU_MSB 24 + #define USB_GUSBCFG_IND_PASS_THRU_LSB 24 + #define USB_GUSBCFG_IND_PASS_THRU_RESET 0x0 + #define USB_GUSBCFG_IND_COMP_BITS 23:23 + #define USB_GUSBCFG_IND_COMP_SET 0x00800000 + #define USB_GUSBCFG_IND_COMP_CLR 0xff7fffff + #define USB_GUSBCFG_IND_COMP_MSB 23 + #define USB_GUSBCFG_IND_COMP_LSB 23 + #define USB_GUSBCFG_IND_COMP_RESET 0x0 + #define USB_GUSBCFG_TERM_SEL_DL_PULSE_BITS 22:22 + #define USB_GUSBCFG_TERM_SEL_DL_PULSE_SET 0x00400000 + #define USB_GUSBCFG_TERM_SEL_DL_PULSE_CLR 0xffbfffff + #define USB_GUSBCFG_TERM_SEL_DL_PULSE_MSB 22 + #define USB_GUSBCFG_TERM_SEL_DL_PULSE_LSB 22 + #define USB_GUSBCFG_TERM_SEL_DL_PULSE_RESET 0x0 + #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_BITS 21:21 + #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_SET 0x00200000 + #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_CLR 0xffdfffff + #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_MSB 21 + #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_LSB 21 + #define USB_GUSBCFG_ULPI_EXT_VBUS_IND_RESET 0x0 + #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_BITS 20:20 + #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_SET 0x00100000 + #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_CLR 0xffefffff + #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_MSB 20 + #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_LSB 20 + #define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_RESET 0x0 + #define USB_GUSBCFG_ULPI_CLK_SUS_M_BITS 19:19 + #define USB_GUSBCFG_ULPI_CLK_SUS_M_SET 0x00080000 + #define USB_GUSBCFG_ULPI_CLK_SUS_M_CLR 0xfff7ffff + #define USB_GUSBCFG_ULPI_CLK_SUS_M_MSB 19 + #define USB_GUSBCFG_ULPI_CLK_SUS_M_LSB 19 + #define USB_GUSBCFG_ULPI_CLK_SUS_M_RESET 0x0 + #define USB_GUSBCFG_ULPI_AUTO_RES_BITS 18:18 + #define USB_GUSBCFG_ULPI_AUTO_RES_SET 0x00040000 + #define USB_GUSBCFG_ULPI_AUTO_RES_CLR 0xfffbffff + #define USB_GUSBCFG_ULPI_AUTO_RES_MSB 18 + #define USB_GUSBCFG_ULPI_AUTO_RES_LSB 18 + #define USB_GUSBCFG_ULPI_AUTO_RES_RESET 0x0 + #define USB_GUSBCFG_ULPI_FS_LS_BITS 17:17 + #define USB_GUSBCFG_ULPI_FS_LS_SET 0x00020000 + #define USB_GUSBCFG_ULPI_FS_LS_CLR 0xfffdffff + #define USB_GUSBCFG_ULPI_FS_LS_MSB 17 + #define USB_GUSBCFG_ULPI_FS_LS_LSB 17 + #define USB_GUSBCFG_ULPI_FS_LS_RESET 0x0 + #define USB_GUSBCFG_OTG_I2C_SEL_BITS 16:16 + #define USB_GUSBCFG_OTG_I2C_SEL_SET 0x00010000 + #define USB_GUSBCFG_OTG_I2C_SEL_CLR 0xfffeffff + #define USB_GUSBCFG_OTG_I2C_SEL_MSB 16 + #define USB_GUSBCFG_OTG_I2C_SEL_LSB 16 + #define USB_GUSBCFG_OTG_I2C_SEL_RESET 0x0 + #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_BITS 15:15 + #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_SET 0x00008000 + #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_CLR 0xffff7fff + #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_MSB 15 + #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_LSB 15 + #define USB_GUSBCFG_PHY_LPWR_CLK_SEL_RESET 0x0 + #define USB_GUSBCFG_USB_TRD_TIM_BITS 13:10 + #define USB_GUSBCFG_USB_TRD_TIM_SET 0x00003c00 + #define USB_GUSBCFG_USB_TRD_TIM_CLR 0xffffc3ff + #define USB_GUSBCFG_USB_TRD_TIM_MSB 13 + #define USB_GUSBCFG_USB_TRD_TIM_LSB 10 + #define USB_GUSBCFG_USB_TRD_TIM_RESET 0x0 + #define USB_GUSBCFG_HNP_CAP_BITS 9:9 + #define USB_GUSBCFG_HNP_CAP_SET 0x00000200 + #define USB_GUSBCFG_HNP_CAP_CLR 0xfffffdff + #define USB_GUSBCFG_HNP_CAP_MSB 9 + #define USB_GUSBCFG_HNP_CAP_LSB 9 + #define USB_GUSBCFG_HNP_CAP_RESET 0x0 + #define USB_GUSBCFG_SRP_CAP_BITS 8:8 + #define USB_GUSBCFG_SRP_CAP_SET 0x00000100 + #define USB_GUSBCFG_SRP_CAP_CLR 0xfffffeff + #define USB_GUSBCFG_SRP_CAP_MSB 8 + #define USB_GUSBCFG_SRP_CAP_LSB 8 + #define USB_GUSBCFG_SRP_CAP_RESET 0x0 + #define USB_GUSBCFG_DDR_SEL_BITS 7:7 + #define USB_GUSBCFG_DDR_SEL_SET 0x00000080 + #define USB_GUSBCFG_DDR_SEL_CLR 0xffffff7f + #define USB_GUSBCFG_DDR_SEL_MSB 7 + #define USB_GUSBCFG_DDR_SEL_LSB 7 + #define USB_GUSBCFG_DDR_SEL_RESET 0x0 + #define USB_GUSBCFG_PHY_SEL_BITS 6:6 + #define USB_GUSBCFG_PHY_SEL_SET 0x00000040 + #define USB_GUSBCFG_PHY_SEL_CLR 0xffffffbf + #define USB_GUSBCFG_PHY_SEL_MSB 6 + #define USB_GUSBCFG_PHY_SEL_LSB 6 + #define USB_GUSBCFG_PHY_SEL_RESET 0x0 + #define USB_GUSBCFG_FS_INTF_BITS 5:5 + #define USB_GUSBCFG_FS_INTF_SET 0x00000020 + #define USB_GUSBCFG_FS_INTF_CLR 0xffffffdf + #define USB_GUSBCFG_FS_INTF_MSB 5 + #define USB_GUSBCFG_FS_INTF_LSB 5 + #define USB_GUSBCFG_FS_INTF_RESET 0x0 + #define USB_GUSBCFG_ULPI_UTMI_SEL_BITS 4:4 + #define USB_GUSBCFG_ULPI_UTMI_SEL_SET 0x00000010 + #define USB_GUSBCFG_ULPI_UTMI_SEL_CLR 0xffffffef + #define USB_GUSBCFG_ULPI_UTMI_SEL_MSB 4 + #define USB_GUSBCFG_ULPI_UTMI_SEL_LSB 4 + #define USB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x0 + #define USB_GUSBCFG_PHY_IF_BITS 3:3 + #define USB_GUSBCFG_PHY_IF_SET 0x00000008 + #define USB_GUSBCFG_PHY_IF_CLR 0xfffffff7 + #define USB_GUSBCFG_PHY_IF_MSB 3 + #define USB_GUSBCFG_PHY_IF_LSB 3 + #define USB_GUSBCFG_PHY_IF_RESET 0x0 + #define USB_GUSBCFG_TOUT_CAL_BITS 2:0 + #define USB_GUSBCFG_TOUT_CAL_SET 0x00000007 + #define USB_GUSBCFG_TOUT_CAL_CLR 0xfffffff8 + #define USB_GUSBCFG_TOUT_CAL_MSB 2 + #define USB_GUSBCFG_TOUT_CAL_LSB 0 + #define USB_GUSBCFG_TOUT_CAL_RESET 0x0 +#define USB_GRSTCTL HW_REGISTER_RW( 0x7e980010 ) + #define USB_GRSTCTL_MASK 0xc00007ff + #define USB_GRSTCTL_WIDTH 32 + #define USB_GRSTCTL_AHB_IDLE_BITS 31:31 + #define USB_GRSTCTL_AHB_IDLE_SET 0x80000000 + #define USB_GRSTCTL_AHB_IDLE_CLR 0x7fffffff + #define USB_GRSTCTL_AHB_IDLE_MSB 31 + #define USB_GRSTCTL_AHB_IDLE_LSB 31 + #define USB_GRSTCTL_AHB_IDLE_RESET 0x0 + #define USB_GRSTCTL_DMA_REQ_BITS 30:30 + #define USB_GRSTCTL_DMA_REQ_SET 0x40000000 + #define USB_GRSTCTL_DMA_REQ_CLR 0xbfffffff + #define USB_GRSTCTL_DMA_REQ_MSB 30 + #define USB_GRSTCTL_DMA_REQ_LSB 30 + #define USB_GRSTCTL_DMA_REQ_RESET 0x0 + #define USB_GRSTCTL_TXF_NUM_BITS 10:6 + #define USB_GRSTCTL_TXF_NUM_SET 0x000007c0 + #define USB_GRSTCTL_TXF_NUM_CLR 0xfffff83f + #define USB_GRSTCTL_TXF_NUM_MSB 10 + #define USB_GRSTCTL_TXF_NUM_LSB 6 + #define USB_GRSTCTL_TXF_NUM_RESET 0x0 + #define USB_GRSTCTL_TXF_FLSH_BITS 5:5 + #define USB_GRSTCTL_TXF_FLSH_SET 0x00000020 + #define USB_GRSTCTL_TXF_FLSH_CLR 0xffffffdf + #define USB_GRSTCTL_TXF_FLSH_MSB 5 + #define USB_GRSTCTL_TXF_FLSH_LSB 5 + #define USB_GRSTCTL_TXF_FLSH_RESET 0x0 + #define USB_GRSTCTL_RXF_FLSH_BITS 4:4 + #define USB_GRSTCTL_RXF_FLSH_SET 0x00000010 + #define USB_GRSTCTL_RXF_FLSH_CLR 0xffffffef + #define USB_GRSTCTL_RXF_FLSH_MSB 4 + #define USB_GRSTCTL_RXF_FLSH_LSB 4 + #define USB_GRSTCTL_RXF_FLSH_RESET 0x0 + #define USB_GRSTCTL_INT_TKN_Q_FLSH_BITS 3:3 + #define USB_GRSTCTL_INT_TKN_Q_FLSH_SET 0x00000008 + #define USB_GRSTCTL_INT_TKN_Q_FLSH_CLR 0xfffffff7 + #define USB_GRSTCTL_INT_TKN_Q_FLSH_MSB 3 + #define USB_GRSTCTL_INT_TKN_Q_FLSH_LSB 3 + #define USB_GRSTCTL_INT_TKN_Q_FLSH_RESET 0x0 + #define USB_GRSTCTL_FRM_CNTR_RST_BITS 2:2 + #define USB_GRSTCTL_FRM_CNTR_RST_SET 0x00000004 + #define USB_GRSTCTL_FRM_CNTR_RST_CLR 0xfffffffb + #define USB_GRSTCTL_FRM_CNTR_RST_MSB 2 + #define USB_GRSTCTL_FRM_CNTR_RST_LSB 2 + #define USB_GRSTCTL_FRM_CNTR_RST_RESET 0x0 + #define USB_GRSTCTL_H_SFT_RST_BITS 1:1 + #define USB_GRSTCTL_H_SFT_RST_SET 0x00000002 + #define USB_GRSTCTL_H_SFT_RST_CLR 0xfffffffd + #define USB_GRSTCTL_H_SFT_RST_MSB 1 + #define USB_GRSTCTL_H_SFT_RST_LSB 1 + #define USB_GRSTCTL_H_SFT_RST_RESET 0x0 + #define USB_GRSTCTL_C_SFT_RST_BITS 0:0 + #define USB_GRSTCTL_C_SFT_RST_SET 0x00000001 + #define USB_GRSTCTL_C_SFT_RST_CLR 0xfffffffe + #define USB_GRSTCTL_C_SFT_RST_MSB 0 + #define USB_GRSTCTL_C_SFT_RST_LSB 0 + #define USB_GRSTCTL_C_SFT_RST_RESET 0x0 +#define USB_GINTSTS HW_REGISTER_RW( 0x7e980014 ) + #define USB_GINTSTS_MASK 0xffffffff + #define USB_GINTSTS_WIDTH 32 +#define USB_GINTMSK HW_REGISTER_RW( 0x7e980018 ) + #define USB_GINTMSK_MASK 0xf77effff + #define USB_GINTMSK_WIDTH 32 + #define USB_GINTMSK_WK_UP_INT_BITS 31:31 + #define USB_GINTMSK_WK_UP_INT_SET 0x80000000 + #define USB_GINTMSK_WK_UP_INT_CLR 0x7fffffff + #define USB_GINTMSK_WK_UP_INT_MSB 31 + #define USB_GINTMSK_WK_UP_INT_LSB 31 + #define USB_GINTMSK_WK_UP_INT_RESET 0x0 + #define USB_GINTMSK_SESS_REQ_INT_BITS 30:30 + #define USB_GINTMSK_SESS_REQ_INT_SET 0x40000000 + #define USB_GINTMSK_SESS_REQ_INT_CLR 0xbfffffff + #define USB_GINTMSK_SESS_REQ_INT_MSB 30 + #define USB_GINTMSK_SESS_REQ_INT_LSB 30 + #define USB_GINTMSK_SESS_REQ_INT_RESET 0x0 + #define USB_GINTMSK_DISCONN_INT_BITS 29:29 + #define USB_GINTMSK_DISCONN_INT_SET 0x20000000 + #define USB_GINTMSK_DISCONN_INT_CLR 0xdfffffff + #define USB_GINTMSK_DISCONN_INT_MSB 29 + #define USB_GINTMSK_DISCONN_INT_LSB 29 + #define USB_GINTMSK_DISCONN_INT_RESET 0x0 + #define USB_GINTMSK_CON_ID_STS_CHNG_BITS 28:28 + #define USB_GINTMSK_CON_ID_STS_CHNG_SET 0x10000000 + #define USB_GINTMSK_CON_ID_STS_CHNG_CLR 0xefffffff + #define USB_GINTMSK_CON_ID_STS_CHNG_MSB 28 + #define USB_GINTMSK_CON_ID_STS_CHNG_LSB 28 + #define USB_GINTMSK_CON_ID_STS_CHNG_RESET 0x0 + #define USB_GINTMSK_P_TXF_EMP_BITS 26:26 + #define USB_GINTMSK_P_TXF_EMP_SET 0x04000000 + #define USB_GINTMSK_P_TXF_EMP_CLR 0xfbffffff + #define USB_GINTMSK_P_TXF_EMP_MSB 26 + #define USB_GINTMSK_P_TXF_EMP_LSB 26 + #define USB_GINTMSK_P_TXF_EMP_RESET 0x0 + #define USB_GINTMSK_HCH_INT_BITS 25:25 + #define USB_GINTMSK_HCH_INT_SET 0x02000000 + #define USB_GINTMSK_HCH_INT_CLR 0xfdffffff + #define USB_GINTMSK_HCH_INT_MSB 25 + #define USB_GINTMSK_HCH_INT_LSB 25 + #define USB_GINTMSK_HCH_INT_RESET 0x0 + #define USB_GINTMSK_PRT_INT_BITS 24:24 + #define USB_GINTMSK_PRT_INT_SET 0x01000000 + #define USB_GINTMSK_PRT_INT_CLR 0xfeffffff + #define USB_GINTMSK_PRT_INT_MSB 24 + #define USB_GINTMSK_PRT_INT_LSB 24 + #define USB_GINTMSK_PRT_INT_RESET 0x0 + #define USB_GINTMSK_FET_SUSP_BITS 22:22 + #define USB_GINTMSK_FET_SUSP_SET 0x00400000 + #define USB_GINTMSK_FET_SUSP_CLR 0xffbfffff + #define USB_GINTMSK_FET_SUSP_MSB 22 + #define USB_GINTMSK_FET_SUSP_LSB 22 + #define USB_GINTMSK_FET_SUSP_RESET 0x0 + #define USB_GINTMSK_INCOMPL_P_BITS 21:21 + #define USB_GINTMSK_INCOMPL_P_SET 0x00200000 + #define USB_GINTMSK_INCOMPL_P_CLR 0xffdfffff + #define USB_GINTMSK_INCOMPL_P_MSB 21 + #define USB_GINTMSK_INCOMPL_P_LSB 21 + #define USB_GINTMSK_INCOMPL_P_RESET 0x0 + #define USB_GINTMSK_INCOMPL_ISO_OUT_BITS 21:21 + #define USB_GINTMSK_INCOMPL_ISO_OUT_SET 0x00200000 + #define USB_GINTMSK_INCOMPL_ISO_OUT_CLR 0xffdfffff + #define USB_GINTMSK_INCOMPL_ISO_OUT_MSB 21 + #define USB_GINTMSK_INCOMPL_ISO_OUT_LSB 21 + #define USB_GINTMSK_INCOMPL_ISO_OUT_RESET 0x0 + #define USB_GINTMSK_INCOMPL_ISO_IN_BITS 20:20 + #define USB_GINTMSK_INCOMPL_ISO_IN_SET 0x00100000 + #define USB_GINTMSK_INCOMPL_ISO_IN_CLR 0xffefffff + #define USB_GINTMSK_INCOMPL_ISO_IN_MSB 20 + #define USB_GINTMSK_INCOMPL_ISO_IN_LSB 20 + #define USB_GINTMSK_INCOMPL_ISO_IN_RESET 0x0 + #define USB_GINTMSK_OEP_INT_BITS 19:19 + #define USB_GINTMSK_OEP_INT_SET 0x00080000 + #define USB_GINTMSK_OEP_INT_CLR 0xfff7ffff + #define USB_GINTMSK_OEP_INT_MSB 19 + #define USB_GINTMSK_OEP_INT_LSB 19 + #define USB_GINTMSK_OEP_INT_RESET 0x0 + #define USB_GINTMSK_IEP_INT_BITS 18:18 + #define USB_GINTMSK_IEP_INT_SET 0x00040000 + #define USB_GINTMSK_IEP_INT_CLR 0xfffbffff + #define USB_GINTMSK_IEP_INT_MSB 18 + #define USB_GINTMSK_IEP_INT_LSB 18 + #define USB_GINTMSK_IEP_INT_RESET 0x0 + #define USB_GINTMSK_EP_MIS_BITS 17:17 + #define USB_GINTMSK_EP_MIS_SET 0x00020000 + #define USB_GINTMSK_EP_MIS_CLR 0xfffdffff + #define USB_GINTMSK_EP_MIS_MSB 17 + #define USB_GINTMSK_EP_MIS_LSB 17 + #define USB_GINTMSK_EP_MIS_RESET 0x0 + #define USB_GINTMSK_EOPF_BITS 15:15 + #define USB_GINTMSK_EOPF_SET 0x00008000 + #define USB_GINTMSK_EOPF_CLR 0xffff7fff + #define USB_GINTMSK_EOPF_MSB 15 + #define USB_GINTMSK_EOPF_LSB 15 + #define USB_GINTMSK_EOPF_RESET 0x0 + #define USB_GINTMSK_ISO_OUT_DROP_BITS 14:14 + #define USB_GINTMSK_ISO_OUT_DROP_SET 0x00004000 + #define USB_GINTMSK_ISO_OUT_DROP_CLR 0xffffbfff + #define USB_GINTMSK_ISO_OUT_DROP_MSB 14 + #define USB_GINTMSK_ISO_OUT_DROP_LSB 14 + #define USB_GINTMSK_ISO_OUT_DROP_RESET 0x0 + #define USB_GINTMSK_ENUM_DONE_BITS 13:13 + #define USB_GINTMSK_ENUM_DONE_SET 0x00002000 + #define USB_GINTMSK_ENUM_DONE_CLR 0xffffdfff + #define USB_GINTMSK_ENUM_DONE_MSB 13 + #define USB_GINTMSK_ENUM_DONE_LSB 13 + #define USB_GINTMSK_ENUM_DONE_RESET 0x0 + #define USB_GINTMSK_USB_RST_BITS 12:12 + #define USB_GINTMSK_USB_RST_SET 0x00001000 + #define USB_GINTMSK_USB_RST_CLR 0xffffefff + #define USB_GINTMSK_USB_RST_MSB 12 + #define USB_GINTMSK_USB_RST_LSB 12 + #define USB_GINTMSK_USB_RST_RESET 0x0 + #define USB_GINTMSK_USB_SUSP_BITS 11:11 + #define USB_GINTMSK_USB_SUSP_SET 0x00000800 + #define USB_GINTMSK_USB_SUSP_CLR 0xfffff7ff + #define USB_GINTMSK_USB_SUSP_MSB 11 + #define USB_GINTMSK_USB_SUSP_LSB 11 + #define USB_GINTMSK_USB_SUSP_RESET 0x0 + #define USB_GINTMSK_ERLY_SUSP_BITS 10:10 + #define USB_GINTMSK_ERLY_SUSP_SET 0x00000400 + #define USB_GINTMSK_ERLY_SUSP_CLR 0xfffffbff + #define USB_GINTMSK_ERLY_SUSP_MSB 10 + #define USB_GINTMSK_ERLY_SUSP_LSB 10 + #define USB_GINTMSK_ERLY_SUSP_RESET 0x0 + #define USB_GINTMSK_I2C_INT_BITS 9:9 + #define USB_GINTMSK_I2C_INT_SET 0x00000200 + #define USB_GINTMSK_I2C_INT_CLR 0xfffffdff + #define USB_GINTMSK_I2C_INT_MSB 9 + #define USB_GINTMSK_I2C_INT_LSB 9 + #define USB_GINTMSK_I2C_INT_RESET 0x0 + #define USB_GINTMSK_ULPI_CK_INT_BITS 8:8 + #define USB_GINTMSK_ULPI_CK_INT_SET 0x00000100 + #define USB_GINTMSK_ULPI_CK_INT_CLR 0xfffffeff + #define USB_GINTMSK_ULPI_CK_INT_MSB 8 + #define USB_GINTMSK_ULPI_CK_INT_LSB 8 + #define USB_GINTMSK_ULPI_CK_INT_RESET 0x0 + #define USB_GINTMSK_GOUT_NAK_EFF_BITS 7:7 + #define USB_GINTMSK_GOUT_NAK_EFF_SET 0x00000080 + #define USB_GINTMSK_GOUT_NAK_EFF_CLR 0xffffff7f + #define USB_GINTMSK_GOUT_NAK_EFF_MSB 7 + #define USB_GINTMSK_GOUT_NAK_EFF_LSB 7 + #define USB_GINTMSK_GOUT_NAK_EFF_RESET 0x0 + #define USB_GINTMSK_GIN_N_NAK_EFF_BITS 6:6 + #define USB_GINTMSK_GIN_N_NAK_EFF_SET 0x00000040 + #define USB_GINTMSK_GIN_N_NAK_EFF_CLR 0xffffffbf + #define USB_GINTMSK_GIN_N_NAK_EFF_MSB 6 + #define USB_GINTMSK_GIN_N_NAK_EFF_LSB 6 + #define USB_GINTMSK_GIN_N_NAK_EFF_RESET 0x0 + #define USB_GINTMSK_NP_TXF_EMP_BITS 5:5 + #define USB_GINTMSK_NP_TXF_EMP_SET 0x00000020 + #define USB_GINTMSK_NP_TXF_EMP_CLR 0xffffffdf + #define USB_GINTMSK_NP_TXF_EMP_MSB 5 + #define USB_GINTMSK_NP_TXF_EMP_LSB 5 + #define USB_GINTMSK_NP_TXF_EMP_RESET 0x0 + #define USB_GINTMSK_RXF_LVL_BITS 4:4 + #define USB_GINTMSK_RXF_LVL_SET 0x00000010 + #define USB_GINTMSK_RXF_LVL_CLR 0xffffffef + #define USB_GINTMSK_RXF_LVL_MSB 4 + #define USB_GINTMSK_RXF_LVL_LSB 4 + #define USB_GINTMSK_RXF_LVL_RESET 0x0 + #define USB_GINTMSK_SOF_BITS 3:3 + #define USB_GINTMSK_SOF_SET 0x00000008 + #define USB_GINTMSK_SOF_CLR 0xfffffff7 + #define USB_GINTMSK_SOF_MSB 3 + #define USB_GINTMSK_SOF_LSB 3 + #define USB_GINTMSK_SOF_RESET 0x0 + #define USB_GINTMSK_OTG_INT_BITS 2:2 + #define USB_GINTMSK_OTG_INT_SET 0x00000004 + #define USB_GINTMSK_OTG_INT_CLR 0xfffffffb + #define USB_GINTMSK_OTG_INT_MSB 2 + #define USB_GINTMSK_OTG_INT_LSB 2 + #define USB_GINTMSK_OTG_INT_RESET 0x0 + #define USB_GINTMSK_MODE_MIS_BITS 1:1 + #define USB_GINTMSK_MODE_MIS_SET 0x00000002 + #define USB_GINTMSK_MODE_MIS_CLR 0xfffffffd + #define USB_GINTMSK_MODE_MIS_MSB 1 + #define USB_GINTMSK_MODE_MIS_LSB 1 + #define USB_GINTMSK_MODE_MIS_RESET 0x0 + #define USB_GINTMSK_CUR_MOD_BITS 0:0 + #define USB_GINTMSK_CUR_MOD_SET 0x00000001 + #define USB_GINTMSK_CUR_MOD_CLR 0xfffffffe + #define USB_GINTMSK_CUR_MOD_MSB 0 + #define USB_GINTMSK_CUR_MOD_LSB 0 + #define USB_GINTMSK_CUR_MOD_RESET 0x0 +#define USB_GRXSTSR HW_REGISTER_RW( 0x7e98001c ) + #define USB_GRXSTSR_MASK 0xffffffff + #define USB_GRXSTSR_WIDTH 32 +#define USB_GRXSTSP HW_REGISTER_RW( 0x7e980020 ) + #define USB_GRXSTSP_MASK 0x01ffffff + #define USB_GRXSTSP_WIDTH 25 + #define USB_GRXSTSP_HST_PKT_STS_BITS 20:17 + #define USB_GRXSTSP_HST_PKT_STS_SET 0x001e0000 + #define USB_GRXSTSP_HST_PKT_STS_CLR 0xffe1ffff + #define USB_GRXSTSP_HST_PKT_STS_MSB 20 + #define USB_GRXSTSP_HST_PKT_STS_LSB 17 + #define USB_GRXSTSP_HST_PKT_STS_RESET 0x0 + #define USB_GRXSTSP_HST_DPID_BITS 16:15 + #define USB_GRXSTSP_HST_DPID_SET 0x00018000 + #define USB_GRXSTSP_HST_DPID_CLR 0xfffe7fff + #define USB_GRXSTSP_HST_DPID_MSB 16 + #define USB_GRXSTSP_HST_DPID_LSB 15 + #define USB_GRXSTSP_HST_DPID_RESET 0x0 + #define USB_GRXSTSP_HST_BCNT_BITS 14:4 + #define USB_GRXSTSP_HST_BCNT_SET 0x00007ff0 + #define USB_GRXSTSP_HST_BCNT_CLR 0xffff800f + #define USB_GRXSTSP_HST_BCNT_MSB 14 + #define USB_GRXSTSP_HST_BCNT_LSB 4 + #define USB_GRXSTSP_HST_BCNT_RESET 0x0 + #define USB_GRXSTSP_HST_CH_NUM_BITS 3:0 + #define USB_GRXSTSP_HST_CH_NUM_SET 0x0000000f + #define USB_GRXSTSP_HST_CH_NUM_CLR 0xfffffff0 + #define USB_GRXSTSP_HST_CH_NUM_MSB 3 + #define USB_GRXSTSP_HST_CH_NUM_LSB 0 + #define USB_GRXSTSP_HST_CH_NUM_RESET 0x0 + #define USB_GRXSTSP_DEV_FN_BITS 24:21 + #define USB_GRXSTSP_DEV_FN_SET 0x01e00000 + #define USB_GRXSTSP_DEV_FN_CLR 0xfe1fffff + #define USB_GRXSTSP_DEV_FN_MSB 24 + #define USB_GRXSTSP_DEV_FN_LSB 21 + #define USB_GRXSTSP_DEV_FN_RESET 0x0 + #define USB_GRXSTSP_DEV_PKT_STS_BITS 20:17 + #define USB_GRXSTSP_DEV_PKT_STS_SET 0x001e0000 + #define USB_GRXSTSP_DEV_PKT_STS_CLR 0xffe1ffff + #define USB_GRXSTSP_DEV_PKT_STS_MSB 20 + #define USB_GRXSTSP_DEV_PKT_STS_LSB 17 + #define USB_GRXSTSP_DEV_PKT_STS_RESET 0x0 + #define USB_GRXSTSP_DEV_DPID_BITS 16:15 + #define USB_GRXSTSP_DEV_DPID_SET 0x00018000 + #define USB_GRXSTSP_DEV_DPID_CLR 0xfffe7fff + #define USB_GRXSTSP_DEV_DPID_MSB 16 + #define USB_GRXSTSP_DEV_DPID_LSB 15 + #define USB_GRXSTSP_DEV_DPID_RESET 0x0 + #define USB_GRXSTSP_DEV_BCNT_BITS 14:4 + #define USB_GRXSTSP_DEV_BCNT_SET 0x00007ff0 + #define USB_GRXSTSP_DEV_BCNT_CLR 0xffff800f + #define USB_GRXSTSP_DEV_BCNT_MSB 14 + #define USB_GRXSTSP_DEV_BCNT_LSB 4 + #define USB_GRXSTSP_DEV_BCNT_RESET 0x0 + #define USB_GRXSTSP_DEV_EP_NUM_BITS 3:0 + #define USB_GRXSTSP_DEV_EP_NUM_SET 0x0000000f + #define USB_GRXSTSP_DEV_EP_NUM_CLR 0xfffffff0 + #define USB_GRXSTSP_DEV_EP_NUM_MSB 3 + #define USB_GRXSTSP_DEV_EP_NUM_LSB 0 + #define USB_GRXSTSP_DEV_EP_NUM_RESET 0x0 +#define USB_GRXFSIZ HW_REGISTER_RW( 0x7e980024 ) + #define USB_GRXFSIZ_MASK 0x0000ffff + #define USB_GRXFSIZ_WIDTH 16 + #define USB_GRXFSIZ_GRXF_DEP_BITS 15:0 + #define USB_GRXFSIZ_GRXF_DEP_SET 0x0000ffff + #define USB_GRXFSIZ_GRXF_DEP_CLR 0xffff0000 + #define USB_GRXFSIZ_GRXF_DEP_MSB 15 + #define USB_GRXFSIZ_GRXF_DEP_LSB 0 + #define USB_GRXFSIZ_GRXF_DEP_RESET 0x0 +#define USB_GNPTXFSIZ HW_REGISTER_RW( 0x7e980028 ) + #define USB_GNPTXFSIZ_MASK 0xffffffff + #define USB_GNPTXFSIZ_WIDTH 32 + #define USB_GNPTXFSIZ_NP_TXF_DEP_BITS 31:16 + #define USB_GNPTXFSIZ_NP_TXF_DEP_SET 0xffff0000 + #define USB_GNPTXFSIZ_NP_TXF_DEP_CLR 0x0000ffff + #define USB_GNPTXFSIZ_NP_TXF_DEP_MSB 31 + #define USB_GNPTXFSIZ_NP_TXF_DEP_LSB 16 + #define USB_GNPTXFSIZ_NP_TXF_DEP_RESET 0x0 + #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_BITS 15:0 + #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_SET 0x0000ffff + #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_CLR 0xffff0000 + #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_MSB 15 + #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_LSB 0 + #define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_RESET 0x0 + #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_BITS 31:16 + #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_SET 0xffff0000 + #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_CLR 0x0000ffff + #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_MSB 31 + #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_LSB 16 + #define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_RESET 0x0 + #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_BITS 15:0 + #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_SET 0x0000ffff + #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_CLR 0xffff0000 + #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_MSB 15 + #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_LSB 0 + #define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_RESET 0x0 +#define USB_GNPTXSTS HW_REGISTER_RW( 0x7e98002c ) + #define USB_GNPTXSTS_MASK 0x7fffffff + #define USB_GNPTXSTS_WIDTH 31 + #define USB_GNPTXSTS_TX_Q_TOP_BITS 30:24 + #define USB_GNPTXSTS_TX_Q_TOP_SET 0x7f000000 + #define USB_GNPTXSTS_TX_Q_TOP_CLR 0x80ffffff + #define USB_GNPTXSTS_TX_Q_TOP_MSB 30 + #define USB_GNPTXSTS_TX_Q_TOP_LSB 24 + #define USB_GNPTXSTS_TX_Q_TOP_RESET 0x0 + #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_BITS 23:16 + #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_SET 0x00ff0000 + #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_CLR 0xff00ffff + #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_MSB 23 + #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_LSB 16 + #define USB_GNPTXSTS_TX_Q_SPC_AVAIL_RESET 0x0 + #define USB_GNPTXSTS_TXF_SPC_AVAIL_BITS 15:0 + #define USB_GNPTXSTS_TXF_SPC_AVAIL_SET 0x0000ffff + #define USB_GNPTXSTS_TXF_SPC_AVAIL_CLR 0xffff0000 + #define USB_GNPTXSTS_TXF_SPC_AVAIL_MSB 15 + #define USB_GNPTXSTS_TXF_SPC_AVAIL_LSB 0 + #define USB_GNPTXSTS_TXF_SPC_AVAIL_RESET 0x0 +#define USB_GI2CCTL HW_REGISTER_RW( 0x7e980030 ) + #define USB_GI2CCTL_MASK 0xdfffffff + #define USB_GI2CCTL_WIDTH 32 + #define USB_GI2CCTL_BSY_DNE_BITS 31:31 + #define USB_GI2CCTL_BSY_DNE_SET 0x80000000 + #define USB_GI2CCTL_BSY_DNE_CLR 0x7fffffff + #define USB_GI2CCTL_BSY_DNE_MSB 31 + #define USB_GI2CCTL_BSY_DNE_LSB 31 + #define USB_GI2CCTL_BSY_DNE_RESET 0x0 + #define USB_GI2CCTL_RW_BITS 30:30 + #define USB_GI2CCTL_RW_SET 0x40000000 + #define USB_GI2CCTL_RW_CLR 0xbfffffff + #define USB_GI2CCTL_RW_MSB 30 + #define USB_GI2CCTL_RW_LSB 30 + #define USB_GI2CCTL_RW_RESET 0x0 + #define USB_GI2CCTL_DAT_SE0_BITS 28:28 + #define USB_GI2CCTL_DAT_SE0_SET 0x10000000 + #define USB_GI2CCTL_DAT_SE0_CLR 0xefffffff + #define USB_GI2CCTL_DAT_SE0_MSB 28 + #define USB_GI2CCTL_DAT_SE0_LSB 28 + #define USB_GI2CCTL_DAT_SE0_RESET 0x0 + #define USB_GI2CCTL_DEV_ADR_BITS 27:26 + #define USB_GI2CCTL_DEV_ADR_SET 0x0c000000 + #define USB_GI2CCTL_DEV_ADR_CLR 0xf3ffffff + #define USB_GI2CCTL_DEV_ADR_MSB 27 + #define USB_GI2CCTL_DEV_ADR_LSB 26 + #define USB_GI2CCTL_DEV_ADR_RESET 0x0 + #define USB_GI2CCTL_SUSP_CTL_BITS 25:25 + #define USB_GI2CCTL_SUSP_CTL_SET 0x02000000 + #define USB_GI2CCTL_SUSP_CTL_CLR 0xfdffffff + #define USB_GI2CCTL_SUSP_CTL_MSB 25 + #define USB_GI2CCTL_SUSP_CTL_LSB 25 + #define USB_GI2CCTL_SUSP_CTL_RESET 0x0 + #define USB_GI2CCTL_EN_BITS 23:23 + #define USB_GI2CCTL_EN_SET 0x00800000 + #define USB_GI2CCTL_EN_CLR 0xff7fffff + #define USB_GI2CCTL_EN_MSB 23 + #define USB_GI2CCTL_EN_LSB 23 + #define USB_GI2CCTL_EN_RESET 0x0 + #define USB_GI2CCTL_ADDR_BITS 22:16 + #define USB_GI2CCTL_ADDR_SET 0x007f0000 + #define USB_GI2CCTL_ADDR_CLR 0xff80ffff + #define USB_GI2CCTL_ADDR_MSB 22 + #define USB_GI2CCTL_ADDR_LSB 16 + #define USB_GI2CCTL_ADDR_RESET 0x0 + #define USB_GI2CCTL_REG_ADDR_BITS 15:8 + #define USB_GI2CCTL_REG_ADDR_SET 0x0000ff00 + #define USB_GI2CCTL_REG_ADDR_CLR 0xffff00ff + #define USB_GI2CCTL_REG_ADDR_MSB 15 + #define USB_GI2CCTL_REG_ADDR_LSB 8 + #define USB_GI2CCTL_REG_ADDR_RESET 0x0 + #define USB_GI2CCTL_RW_DATA_BITS 7:0 + #define USB_GI2CCTL_RW_DATA_SET 0x000000ff + #define USB_GI2CCTL_RW_DATA_CLR 0xffffff00 + #define USB_GI2CCTL_RW_DATA_MSB 7 + #define USB_GI2CCTL_RW_DATA_LSB 0 + #define USB_GI2CCTL_RW_DATA_RESET 0x0 +#define USB_GPVNDCTL HW_REGISTER_RW( 0x7e980034 ) + #define USB_GPVNDCTL_MASK 0x8e7f3fff + #define USB_GPVNDCTL_WIDTH 32 + #define USB_GPVNDCTL_DIS_ULPI_DRVR_BITS 31:31 + #define USB_GPVNDCTL_DIS_ULPI_DRVR_SET 0x80000000 + #define USB_GPVNDCTL_DIS_ULPI_DRVR_CLR 0x7fffffff + #define USB_GPVNDCTL_DIS_ULPI_DRVR_MSB 31 + #define USB_GPVNDCTL_DIS_ULPI_DRVR_LSB 31 + #define USB_GPVNDCTL_DIS_ULPI_DRVR_RESET 0x0 + #define USB_GPVNDCTL_STS_DONE_BITS 27:27 + #define USB_GPVNDCTL_STS_DONE_SET 0x08000000 + #define USB_GPVNDCTL_STS_DONE_CLR 0xf7ffffff + #define USB_GPVNDCTL_STS_DONE_MSB 27 + #define USB_GPVNDCTL_STS_DONE_LSB 27 + #define USB_GPVNDCTL_STS_DONE_RESET 0x0 + #define USB_GPVNDCTL_STS_BSY_BITS 26:26 + #define USB_GPVNDCTL_STS_BSY_SET 0x04000000 + #define USB_GPVNDCTL_STS_BSY_CLR 0xfbffffff + #define USB_GPVNDCTL_STS_BSY_MSB 26 + #define USB_GPVNDCTL_STS_BSY_LSB 26 + #define USB_GPVNDCTL_STS_BSY_RESET 0x0 + #define USB_GPVNDCTL_NEW_REG_REQ_BITS 25:25 + #define USB_GPVNDCTL_NEW_REG_REQ_SET 0x02000000 + #define USB_GPVNDCTL_NEW_REG_REQ_CLR 0xfdffffff + #define USB_GPVNDCTL_NEW_REG_REQ_MSB 25 + #define USB_GPVNDCTL_NEW_REG_REQ_LSB 25 + #define USB_GPVNDCTL_NEW_REG_REQ_RESET 0x0 + #define USB_GPVNDCTL_REG_WR_BITS 22:22 + #define USB_GPVNDCTL_REG_WR_SET 0x00400000 + #define USB_GPVNDCTL_REG_WR_CLR 0xffbfffff + #define USB_GPVNDCTL_REG_WR_MSB 22 + #define USB_GPVNDCTL_REG_WR_LSB 22 + #define USB_GPVNDCTL_REG_WR_RESET 0x0 + #define USB_GPVNDCTL_REG_ADDR_BITS 21:16 + #define USB_GPVNDCTL_REG_ADDR_SET 0x003f0000 + #define USB_GPVNDCTL_REG_ADDR_CLR 0xffc0ffff + #define USB_GPVNDCTL_REG_ADDR_MSB 21 + #define USB_GPVNDCTL_REG_ADDR_LSB 16 + #define USB_GPVNDCTL_REG_ADDR_RESET 0x0 + #define USB_GPVNDCTL_CTRL_UTMI_BITS 11:8 + #define USB_GPVNDCTL_CTRL_UTMI_SET 0x00000f00 + #define USB_GPVNDCTL_CTRL_UTMI_CLR 0xfffff0ff + #define USB_GPVNDCTL_CTRL_UTMI_MSB 11 + #define USB_GPVNDCTL_CTRL_UTMI_LSB 8 + #define USB_GPVNDCTL_CTRL_UTMI_RESET 0x0 + #define USB_GPVNDCTL_CTRL_ULPI_BITS 13:8 + #define USB_GPVNDCTL_CTRL_ULPI_SET 0x00003f00 + #define USB_GPVNDCTL_CTRL_ULPI_CLR 0xffffc0ff + #define USB_GPVNDCTL_CTRL_ULPI_MSB 13 + #define USB_GPVNDCTL_CTRL_ULPI_LSB 8 + #define USB_GPVNDCTL_CTRL_ULPI_RESET 0x0 + #define USB_GPVNDCTL_REG_DATA_BITS 7:0 + #define USB_GPVNDCTL_REG_DATA_SET 0x000000ff + #define USB_GPVNDCTL_REG_DATA_CLR 0xffffff00 + #define USB_GPVNDCTL_REG_DATA_MSB 7 + #define USB_GPVNDCTL_REG_DATA_LSB 0 + #define USB_GPVNDCTL_REG_DATA_RESET 0x0 +#define USB_GGPIO HW_REGISTER_RW( 0x7e980038 ) + #define USB_GGPIO_MASK 0xffffffff + #define USB_GGPIO_WIDTH 32 + #define USB_GGPIO_GPO_BITS 31:16 + #define USB_GGPIO_GPO_SET 0xffff0000 + #define USB_GGPIO_GPO_CLR 0x0000ffff + #define USB_GGPIO_GPO_MSB 31 + #define USB_GGPIO_GPO_LSB 16 + #define USB_GGPIO_GPO_RESET 0x0 + #define USB_GGPIO_GPI_BITS 15:0 + #define USB_GGPIO_GPI_SET 0x0000ffff + #define USB_GGPIO_GPI_CLR 0xffff0000 + #define USB_GGPIO_GPI_MSB 15 + #define USB_GGPIO_GPI_LSB 0 + #define USB_GGPIO_GPI_RESET 0x0 +#define USB_GUID HW_REGISTER_RW( 0x7e98003c ) + #define USB_GUID_MASK 0xffffffff + #define USB_GUID_WIDTH 32 +#define USB_GSNPSID HW_REGISTER_RW( 0x7e980040 ) + #define USB_GSNPSID_MASK 0xffffffff + #define USB_GSNPSID_WIDTH 32 +#define USB_GHWCFG1 HW_REGISTER_RW( 0x7e980044 ) + #define USB_GHWCFG1_MASK 0xffffffff + #define USB_GHWCFG1_WIDTH 32 +#define USB_GHWCFG2 HW_REGISTER_RW( 0x7e980048 ) + #define USB_GHWCFG2_MASK 0x7fcfffff + #define USB_GHWCFG2_WIDTH 31 + #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_BITS 30:26 + #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_SET 0x7c000000 + #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_CLR 0x83ffffff + #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_MSB 30 + #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_LSB 26 + #define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_RESET 0x0 + #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_BITS 25:24 + #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_SET 0x03000000 + #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_CLR 0xfcffffff + #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_MSB 25 + #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_LSB 24 + #define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_RESET 0x0 + #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_BITS 23:22 + #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_SET 0x00c00000 + #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_CLR 0xff3fffff + #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_MSB 23 + #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_LSB 22 + #define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_RESET 0x0 + #define USB_GHWCFG2_DFIFO_DYNAMIC_BITS 19:19 + #define USB_GHWCFG2_DFIFO_DYNAMIC_SET 0x00080000 + #define USB_GHWCFG2_DFIFO_DYNAMIC_CLR 0xfff7ffff + #define USB_GHWCFG2_DFIFO_DYNAMIC_MSB 19 + #define USB_GHWCFG2_DFIFO_DYNAMIC_LSB 19 + #define USB_GHWCFG2_DFIFO_DYNAMIC_RESET 0x0 + #define USB_GHWCFG2_EN_PERIO_HOST_BITS 18:18 + #define USB_GHWCFG2_EN_PERIO_HOST_SET 0x00040000 + #define USB_GHWCFG2_EN_PERIO_HOST_CLR 0xfffbffff + #define USB_GHWCFG2_EN_PERIO_HOST_MSB 18 + #define USB_GHWCFG2_EN_PERIO_HOST_LSB 18 + #define USB_GHWCFG2_EN_PERIO_HOST_RESET 0x0 + #define USB_GHWCFG2_NUM_HOST_CHAN_BITS 14:17 + #define USB_GHWCFG2_NUM_HOST_CHAN_SET 0x0000000000 + #define USB_GHWCFG2_NUM_HOST_CHAN_CLR 0xffffffff11 + #define USB_GHWCFG2_NUM_HOST_CHAN_MSB 14 + #define USB_GHWCFG2_NUM_HOST_CHAN_LSB 17 + #define USB_GHWCFG2_NUM_HOST_CHAN_RESET 0x0 + #define USB_GHWCFG2_NUM_EPS_BITS 10:13 + #define USB_GHWCFG2_NUM_EPS_SET 0x0000000000 + #define USB_GHWCFG2_NUM_EPS_CLR 0xffffffff11 + #define USB_GHWCFG2_NUM_EPS_MSB 10 + #define USB_GHWCFG2_NUM_EPS_LSB 13 + #define USB_GHWCFG2_NUM_EPS_RESET 0x0 + #define USB_GHWCFG2_FSPHY_INTERFACE_BITS 9:8 + #define USB_GHWCFG2_FSPHY_INTERFACE_SET 0x00000300 + #define USB_GHWCFG2_FSPHY_INTERFACE_CLR 0xfffffcff + #define USB_GHWCFG2_FSPHY_INTERFACE_MSB 9 + #define USB_GHWCFG2_FSPHY_INTERFACE_LSB 8 + #define USB_GHWCFG2_FSPHY_INTERFACE_RESET 0x0 + #define USB_GHWCFG2_HSPHY_INTERFACE_BITS 7:6 + #define USB_GHWCFG2_HSPHY_INTERFACE_SET 0x000000c0 + #define USB_GHWCFG2_HSPHY_INTERFACE_CLR 0xffffff3f + #define USB_GHWCFG2_HSPHY_INTERFACE_MSB 7 + #define USB_GHWCFG2_HSPHY_INTERFACE_LSB 6 + #define USB_GHWCFG2_HSPHY_INTERFACE_RESET 0x0 + #define USB_GHWCFG2_SINGLE_POINT_BITS 5:5 + #define USB_GHWCFG2_SINGLE_POINT_SET 0x00000020 + #define USB_GHWCFG2_SINGLE_POINT_CLR 0xffffffdf + #define USB_GHWCFG2_SINGLE_POINT_MSB 5 + #define USB_GHWCFG2_SINGLE_POINT_LSB 5 + #define USB_GHWCFG2_SINGLE_POINT_RESET 0x0 + #define USB_GHWCFG2_ARCHITECTURE_BITS 4:3 + #define USB_GHWCFG2_ARCHITECTURE_SET 0x00000018 + #define USB_GHWCFG2_ARCHITECTURE_CLR 0xffffffe7 + #define USB_GHWCFG2_ARCHITECTURE_MSB 4 + #define USB_GHWCFG2_ARCHITECTURE_LSB 3 + #define USB_GHWCFG2_ARCHITECTURE_RESET 0x0 + #define USB_GHWCFG2_MODE_BITS 2:0 + #define USB_GHWCFG2_MODE_SET 0x00000007 + #define USB_GHWCFG2_MODE_CLR 0xfffffff8 + #define USB_GHWCFG2_MODE_MSB 2 + #define USB_GHWCFG2_MODE_LSB 0 + #define USB_GHWCFG2_MODE_RESET 0x0 +#define USB_GHWCFG3 HW_REGISTER_RW( 0x7e98004c ) + #define USB_GHWCFG3_MASK 0xffff0fff + #define USB_GHWCFG3_WIDTH 32 + #define USB_GHWCFG3_DFIFO_DEPTH_BITS 31:16 + #define USB_GHWCFG3_DFIFO_DEPTH_SET 0xffff0000 + #define USB_GHWCFG3_DFIFO_DEPTH_CLR 0x0000ffff + #define USB_GHWCFG3_DFIFO_DEPTH_MSB 31 + #define USB_GHWCFG3_DFIFO_DEPTH_LSB 16 + #define USB_GHWCFG3_DFIFO_DEPTH_RESET 0x0 + #define USB_GHWCFG3_SYNC_RESET_TYPE_BITS 11:11 + #define USB_GHWCFG3_SYNC_RESET_TYPE_SET 0x00000800 + #define USB_GHWCFG3_SYNC_RESET_TYPE_CLR 0xfffff7ff + #define USB_GHWCFG3_SYNC_RESET_TYPE_MSB 11 + #define USB_GHWCFG3_SYNC_RESET_TYPE_LSB 11 + #define USB_GHWCFG3_SYNC_RESET_TYPE_RESET 0x0 + #define USB_GHWCFG3_RM_OPT_FEATURES_BITS 10:10 + #define USB_GHWCFG3_RM_OPT_FEATURES_SET 0x00000400 + #define USB_GHWCFG3_RM_OPT_FEATURES_CLR 0xfffffbff + #define USB_GHWCFG3_RM_OPT_FEATURES_MSB 10 + #define USB_GHWCFG3_RM_OPT_FEATURES_LSB 10 + #define USB_GHWCFG3_RM_OPT_FEATURES_RESET 0x0 + #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_BITS 9:9 + #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_SET 0x00000200 + #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_CLR 0xfffffdff + #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_MSB 9 + #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_LSB 9 + #define USB_GHWCFG3_VENDOR_CTL_INTERFACE_RESET 0x0 + #define USB_GHWCFG3_I2C_INTERFACE_BITS 8:8 + #define USB_GHWCFG3_I2C_INTERFACE_SET 0x00000100 + #define USB_GHWCFG3_I2C_INTERFACE_CLR 0xfffffeff + #define USB_GHWCFG3_I2C_INTERFACE_MSB 8 + #define USB_GHWCFG3_I2C_INTERFACE_LSB 8 + #define USB_GHWCFG3_I2C_INTERFACE_RESET 0x0 + #define USB_GHWCFG3_MODE_BITS 7:7 + #define USB_GHWCFG3_MODE_SET 0x00000080 + #define USB_GHWCFG3_MODE_CLR 0xffffff7f + #define USB_GHWCFG3_MODE_MSB 7 + #define USB_GHWCFG3_MODE_LSB 7 + #define USB_GHWCFG3_MODE_RESET 0x0 + #define USB_GHWCFG3_PACKET_COUNT_WIDTH_BITS 6:4 + #define USB_GHWCFG3_PACKET_COUNT_WIDTH_SET 0x00000070 + #define USB_GHWCFG3_PACKET_COUNT_WIDTH_CLR 0xffffff8f + #define USB_GHWCFG3_PACKET_COUNT_WIDTH_MSB 6 + #define USB_GHWCFG3_PACKET_COUNT_WIDTH_LSB 4 + #define USB_GHWCFG3_PACKET_COUNT_WIDTH_RESET 0x0 + #define USB_GHWCFG3_TRANS_COUNT_WIDTH_BITS 3:0 + #define USB_GHWCFG3_TRANS_COUNT_WIDTH_SET 0x0000000f + #define USB_GHWCFG3_TRANS_COUNT_WIDTH_CLR 0xfffffff0 + #define USB_GHWCFG3_TRANS_COUNT_WIDTH_MSB 3 + #define USB_GHWCFG3_TRANS_COUNT_WIDTH_LSB 0 + #define USB_GHWCFG3_TRANS_COUNT_WIDTH_RESET 0x0 +#define USB_GHWCFG4 HW_REGISTER_RW( 0x7e980050 ) + #define USB_GHWCFG4_MASK 0xffffc03f + #define USB_GHWCFG4_WIDTH 32 + #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_BITS 31:31 + #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_SET 0x80000000 + #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_CLR 0x7fffffff + #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_MSB 31 + #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_LSB 31 + #define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_RESET 0x0 + #define USB_GHWCFG4_EN_DESC_DMA_BITS 30:30 + #define USB_GHWCFG4_EN_DESC_DMA_SET 0x40000000 + #define USB_GHWCFG4_EN_DESC_DMA_CLR 0xbfffffff + #define USB_GHWCFG4_EN_DESC_DMA_MSB 30 + #define USB_GHWCFG4_EN_DESC_DMA_LSB 30 + #define USB_GHWCFG4_EN_DESC_DMA_RESET 0x0 + #define USB_GHWCFG4_NUM_IN_EPS_BITS 27:26 + #define USB_GHWCFG4_NUM_IN_EPS_SET 0x0c000000 + #define USB_GHWCFG4_NUM_IN_EPS_CLR 0xf3ffffff + #define USB_GHWCFG4_NUM_IN_EPS_MSB 27 + #define USB_GHWCFG4_NUM_IN_EPS_LSB 26 + #define USB_GHWCFG4_NUM_IN_EPS_RESET 0x0 + #define USB_GHWCFG4_EN_DED_TX_FIFO_BITS 25:25 + #define USB_GHWCFG4_EN_DED_TX_FIFO_SET 0x02000000 + #define USB_GHWCFG4_EN_DED_TX_FIFO_CLR 0xfdffffff + #define USB_GHWCFG4_EN_DED_TX_FIFO_MSB 25 + #define USB_GHWCFG4_EN_DED_TX_FIFO_LSB 25 + #define USB_GHWCFG4_EN_DED_TX_FIFO_RESET 0x0 + #define USB_GHWCFG4_EN_SESSIONEND_FILTER_BITS 24:24 + #define USB_GHWCFG4_EN_SESSIONEND_FILTER_SET 0x01000000 + #define USB_GHWCFG4_EN_SESSIONEND_FILTER_CLR 0xfeffffff + #define USB_GHWCFG4_EN_SESSIONEND_FILTER_MSB 24 + #define USB_GHWCFG4_EN_SESSIONEND_FILTER_LSB 24 + #define USB_GHWCFG4_EN_SESSIONEND_FILTER_RESET 0x0 + #define USB_GHWCFG4_EN_B_VALID_FILTER_BITS 23:23 + #define USB_GHWCFG4_EN_B_VALID_FILTER_SET 0x00800000 + #define USB_GHWCFG4_EN_B_VALID_FILTER_CLR 0xff7fffff + #define USB_GHWCFG4_EN_B_VALID_FILTER_MSB 23 + #define USB_GHWCFG4_EN_B_VALID_FILTER_LSB 23 + #define USB_GHWCFG4_EN_B_VALID_FILTER_RESET 0x0 + #define USB_GHWCFG4_EN_A_VALID_FILTER_BITS 22:22 + #define USB_GHWCFG4_EN_A_VALID_FILTER_SET 0x00400000 + #define USB_GHWCFG4_EN_A_VALID_FILTER_CLR 0xffbfffff + #define USB_GHWCFG4_EN_A_VALID_FILTER_MSB 22 + #define USB_GHWCFG4_EN_A_VALID_FILTER_LSB 22 + #define USB_GHWCFG4_EN_A_VALID_FILTER_RESET 0x0 + #define USB_GHWCFG4_EN_VBUSVALID_FILTER_BITS 21:21 + #define USB_GHWCFG4_EN_VBUSVALID_FILTER_SET 0x00200000 + #define USB_GHWCFG4_EN_VBUSVALID_FILTER_CLR 0xffdfffff + #define USB_GHWCFG4_EN_VBUSVALID_FILTER_MSB 21 + #define USB_GHWCFG4_EN_VBUSVALID_FILTER_LSB 21 + #define USB_GHWCFG4_EN_VBUSVALID_FILTER_RESET 0x0 + #define USB_GHWCFG4_EN_IDDIG_FILTER_BITS 20:20 + #define USB_GHWCFG4_EN_IDDIG_FILTER_SET 0x00100000 + #define USB_GHWCFG4_EN_IDDIG_FILTER_CLR 0xffefffff + #define USB_GHWCFG4_EN_IDDIG_FILTER_MSB 20 + #define USB_GHWCFG4_EN_IDDIG_FILTER_LSB 20 + #define USB_GHWCFG4_EN_IDDIG_FILTER_RESET 0x0 + #define USB_GHWCFG4_NUM_CRL_EPS_BITS 19:16 + #define USB_GHWCFG4_NUM_CRL_EPS_SET 0x000f0000 + #define USB_GHWCFG4_NUM_CRL_EPS_CLR 0xfff0ffff + #define USB_GHWCFG4_NUM_CRL_EPS_MSB 19 + #define USB_GHWCFG4_NUM_CRL_EPS_LSB 16 + #define USB_GHWCFG4_NUM_CRL_EPS_RESET 0x0 + #define USB_GHWCFG4_HSPHY_DWIDTH_BITS 15:14 + #define USB_GHWCFG4_HSPHY_DWIDTH_SET 0x0000c000 + #define USB_GHWCFG4_HSPHY_DWIDTH_CLR 0xffff3fff + #define USB_GHWCFG4_HSPHY_DWIDTH_MSB 15 + #define USB_GHWCFG4_HSPHY_DWIDTH_LSB 14 + #define USB_GHWCFG4_HSPHY_DWIDTH_RESET 0x0 + #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_BITS 5:5 + #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_SET 0x00000020 + #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_CLR 0xffffffdf + #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_MSB 5 + #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_LSB 5 + #define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_RESET 0x0 + #define USB_GHWCFG4_EN_PWROPT_BITS 4:4 + #define USB_GHWCFG4_EN_PWROPT_SET 0x00000010 + #define USB_GHWCFG4_EN_PWROPT_CLR 0xffffffef + #define USB_GHWCFG4_EN_PWROPT_MSB 4 + #define USB_GHWCFG4_EN_PWROPT_LSB 4 + #define USB_GHWCFG4_EN_PWROPT_RESET 0x0 + #define USB_GHWCFG4_NUM_PERIO_EPS_BITS 3:0 + #define USB_GHWCFG4_NUM_PERIO_EPS_SET 0x0000000f + #define USB_GHWCFG4_NUM_PERIO_EPS_CLR 0xfffffff0 + #define USB_GHWCFG4_NUM_PERIO_EPS_MSB 3 + #define USB_GHWCFG4_NUM_PERIO_EPS_LSB 0 + #define USB_GHWCFG4_NUM_PERIO_EPS_RESET 0x0 +#define USB_GLPMCFG HW_REGISTER_RW( 0x7e980054 ) + #define USB_GLPMCFG_MASK 0xffffffff + #define USB_GLPMCFG_WIDTH 32 +#define USB_GAXIDEV HW_REGISTER_RW( 0x7e980054 ) + #define USB_GAXIDEV_MASK 0xffffffff + #define USB_GAXIDEV_WIDTH 32 +#define USB_GMDIOCSR HW_REGISTER_RW( 0x7e980080 ) + #define USB_GMDIOCSR_MASK 0x0000ffff + #define USB_GMDIOCSR_WIDTH 16 +#define USB_GMDIOGEN HW_REGISTER_RW( 0x7e980084 ) + #define USB_GMDIOGEN_MASK 0xffffffff + #define USB_GMDIOGEN_WIDTH 32 +#define USB_GVBUSDRV HW_REGISTER_RW( 0x7e980088 ) + #define USB_GVBUSDRV_MASK 0x0000ffff + #define USB_GVBUSDRV_WIDTH 16 +#define USB_HPTXFSIZ HW_REGISTER_RW( 0x7e980100 ) + #define USB_HPTXFSIZ_MASK 0xffffffff + #define USB_HPTXFSIZ_WIDTH 32 +#define USB_DPTXFSIZ1 HW_REGISTER_RW( 0x7e980104 ) + #define USB_DPTXFSIZ1_MASK 0xffffffff + #define USB_DPTXFSIZ1_WIDTH 32 +#define USB_DPTXFSIZ2 HW_REGISTER_RW( 0x7e980108 ) + #define USB_DPTXFSIZ2_MASK 0xffffffff + #define USB_DPTXFSIZ2_WIDTH 32 +#define USB_DPTXFSIZ3 HW_REGISTER_RW( 0x7e98010c ) + #define USB_DPTXFSIZ3_MASK 0xffffffff + #define USB_DPTXFSIZ3_WIDTH 32 +#define USB_DPTXFSIZ4 HW_REGISTER_RW( 0x7e980110 ) + #define USB_DPTXFSIZ4_MASK 0xffffffff + #define USB_DPTXFSIZ4_WIDTH 32 +#define USB_DPTXFSIZ5 HW_REGISTER_RW( 0x7e980114 ) + #define USB_DPTXFSIZ5_MASK 0xffffffff + #define USB_DPTXFSIZ5_WIDTH 32 +#define USB_DPTXFSIZ6 HW_REGISTER_RW( 0x7e980118 ) + #define USB_DPTXFSIZ6_MASK 0xffffffff + #define USB_DPTXFSIZ6_WIDTH 32 +#define USB_DPTXFSIZ7 HW_REGISTER_RW( 0x7e98011c ) + #define USB_DPTXFSIZ7_MASK 0xffffffff + #define USB_DPTXFSIZ7_WIDTH 32 +#define USB_DPTXFSIZ8 HW_REGISTER_RW( 0x7e980120 ) + #define USB_DPTXFSIZ8_MASK 0xffffffff + #define USB_DPTXFSIZ8_WIDTH 32 +#define USB_DPTXFSIZ9 HW_REGISTER_RW( 0x7e980124 ) + #define USB_DPTXFSIZ9_MASK 0xffffffff + #define USB_DPTXFSIZ9_WIDTH 32 +#define USB_DPTXFSIZ10 HW_REGISTER_RW( 0x7e980128 ) + #define USB_DPTXFSIZ10_MASK 0xffffffff + #define USB_DPTXFSIZ10_WIDTH 32 +#define USB_DPTXFSIZ11 HW_REGISTER_RW( 0x7e98012c ) + #define USB_DPTXFSIZ11_MASK 0xffffffff + #define USB_DPTXFSIZ11_WIDTH 32 +#define USB_DPTXFSIZ12 HW_REGISTER_RW( 0x7e980130 ) + #define USB_DPTXFSIZ12_MASK 0xffffffff + #define USB_DPTXFSIZ12_WIDTH 32 +#define USB_DPTXFSIZ13 HW_REGISTER_RW( 0x7e980134 ) + #define USB_DPTXFSIZ13_MASK 0xffffffff + #define USB_DPTXFSIZ13_WIDTH 32 +#define USB_DPTXFSIZ14 HW_REGISTER_RW( 0x7e980138 ) + #define USB_DPTXFSIZ14_MASK 0xffffffff + #define USB_DPTXFSIZ14_WIDTH 32 +#define USB_DPTXFSIZ15 HW_REGISTER_RW( 0x7e98013c ) + #define USB_DPTXFSIZ15_MASK 0xffffffff + #define USB_DPTXFSIZ15_WIDTH 32 +#define USB_DIEPTXF1 HW_REGISTER_RW( 0x7e980104 ) + #define USB_DIEPTXF1_MASK 0xffffffff + #define USB_DIEPTXF1_WIDTH 32 + #define USB_DIEPTXF1_FIFO_SIZE_BITS 31:16 + #define USB_DIEPTXF1_FIFO_SIZE_SET 0xffff0000 + #define USB_DIEPTXF1_FIFO_SIZE_CLR 0x0000ffff + #define USB_DIEPTXF1_FIFO_SIZE_MSB 31 + #define USB_DIEPTXF1_FIFO_SIZE_LSB 16 + #define USB_DIEPTXF1_FIFO_SIZE_RESET 0x0 + #define USB_DIEPTXF1_FIFO_STADDR_BITS 15:0 + #define USB_DIEPTXF1_FIFO_STADDR_SET 0x0000ffff + #define USB_DIEPTXF1_FIFO_STADDR_CLR 0xffff0000 + #define USB_DIEPTXF1_FIFO_STADDR_MSB 15 + #define USB_DIEPTXF1_FIFO_STADDR_LSB 0 + #define USB_DIEPTXF1_FIFO_STADDR_RESET 0x0 +#define USB_DIEPTXF2 HW_REGISTER_RW( 0x7e980108 ) + #define USB_DIEPTXF2_MASK 0xffffffff + #define USB_DIEPTXF2_WIDTH 32 +#define USB_DIEPTXF3 HW_REGISTER_RW( 0x7e98010c ) + #define USB_DIEPTXF3_MASK 0xffffffff + #define USB_DIEPTXF3_WIDTH 32 +#define USB_DIEPTXF4 HW_REGISTER_RW( 0x7e980110 ) + #define USB_DIEPTXF4_MASK 0xffffffff + #define USB_DIEPTXF4_WIDTH 32 +#define USB_DIEPTXF5 HW_REGISTER_RW( 0x7e980114 ) + #define USB_DIEPTXF5_MASK 0xffffffff + #define USB_DIEPTXF5_WIDTH 32 +#define USB_DIEPTXF6 HW_REGISTER_RW( 0x7e980118 ) + #define USB_DIEPTXF6_MASK 0xffffffff + #define USB_DIEPTXF6_WIDTH 32 +#define USB_DIEPTXF7 HW_REGISTER_RW( 0x7e98011c ) + #define USB_DIEPTXF7_MASK 0xffffffff + #define USB_DIEPTXF7_WIDTH 32 +#define USB_DIEPTXF8 HW_REGISTER_RW( 0x7e980120 ) + #define USB_DIEPTXF8_MASK 0xffffffff + #define USB_DIEPTXF8_WIDTH 32 +#define USB_DIEPTXF9 HW_REGISTER_RW( 0x7e980124 ) + #define USB_DIEPTXF9_MASK 0xffffffff + #define USB_DIEPTXF9_WIDTH 32 +#define USB_DIEPTXF10 HW_REGISTER_RW( 0x7e980128 ) + #define USB_DIEPTXF10_MASK 0xffffffff + #define USB_DIEPTXF10_WIDTH 32 +#define USB_DIEPTXF11 HW_REGISTER_RW( 0x7e98012c ) + #define USB_DIEPTXF11_MASK 0xffffffff + #define USB_DIEPTXF11_WIDTH 32 +#define USB_DIEPTXF12 HW_REGISTER_RW( 0x7e980130 ) + #define USB_DIEPTXF12_MASK 0xffffffff + #define USB_DIEPTXF12_WIDTH 32 +#define USB_DIEPTXF13 HW_REGISTER_RW( 0x7e980134 ) + #define USB_DIEPTXF13_MASK 0xffffffff + #define USB_DIEPTXF13_WIDTH 32 +#define USB_DIEPTXF14 HW_REGISTER_RW( 0x7e980138 ) + #define USB_DIEPTXF14_MASK 0xffffffff + #define USB_DIEPTXF14_WIDTH 32 +#define USB_DIEPTXF15 HW_REGISTER_RW( 0x7e98013c ) + #define USB_DIEPTXF15_MASK 0xffffffff + #define USB_DIEPTXF15_WIDTH 32 +#define USB_HCFG HW_REGISTER_RW( 0x7e980400 ) + #define USB_HCFG_MASK 0x00000007 + #define USB_HCFG_WIDTH 3 + #define USB_HCFG_LS_SUPP_BITS 2:2 + #define USB_HCFG_LS_SUPP_SET 0x00000004 + #define USB_HCFG_LS_SUPP_CLR 0xfffffffb + #define USB_HCFG_LS_SUPP_MSB 2 + #define USB_HCFG_LS_SUPP_LSB 2 + #define USB_HCFG_LS_SUPP_RESET 0x0 + #define USB_HCFG_LS_PHY_CLK_SEL_BITS 1:0 + #define USB_HCFG_LS_PHY_CLK_SEL_SET 0x00000003 + #define USB_HCFG_LS_PHY_CLK_SEL_CLR 0xfffffffc + #define USB_HCFG_LS_PHY_CLK_SEL_MSB 1 + #define USB_HCFG_LS_PHY_CLK_SEL_LSB 0 + #define USB_HCFG_LS_PHY_CLK_SEL_RESET 0x0 +#define USB_HFIR HW_REGISTER_RW( 0x7e980404 ) + #define USB_HFIR_MASK 0x0000ffff + #define USB_HFIR_WIDTH 16 + #define USB_HFIR_IN_BITS 15:0 + #define USB_HFIR_IN_SET 0x0000ffff + #define USB_HFIR_IN_CLR 0xffff0000 + #define USB_HFIR_IN_MSB 15 + #define USB_HFIR_IN_LSB 0 + #define USB_HFIR_IN_RESET 0x0 +#define USB_HFNUM HW_REGISTER_RW( 0x7e980408 ) + #define USB_HFNUM_MASK 0xffffffff + #define USB_HFNUM_WIDTH 32 + #define USB_HFNUM_REM_BITS 31:16 + #define USB_HFNUM_REM_SET 0xffff0000 + #define USB_HFNUM_REM_CLR 0x0000ffff + #define USB_HFNUM_REM_MSB 31 + #define USB_HFNUM_REM_LSB 16 + #define USB_HFNUM_REM_RESET 0x0 + #define USB_HFNUM_NUM_BITS 15:0 + #define USB_HFNUM_NUM_SET 0x0000ffff + #define USB_HFNUM_NUM_CLR 0xffff0000 + #define USB_HFNUM_NUM_MSB 15 + #define USB_HFNUM_NUM_LSB 0 + #define USB_HFNUM_NUM_RESET 0x0 +#define USB_HPTXSTS HW_REGISTER_RW( 0x7e980410 ) + #define USB_HPTXSTS_MASK 0xffffffff + #define USB_HPTXSTS_WIDTH 32 + #define USB_HPTXSTS_HPTXQTOP_BITS 31:24 + #define USB_HPTXSTS_HPTXQTOP_SET 0xff000000 + #define USB_HPTXSTS_HPTXQTOP_CLR 0x00ffffff + #define USB_HPTXSTS_HPTXQTOP_MSB 31 + #define USB_HPTXSTS_HPTXQTOP_LSB 24 + #define USB_HPTXSTS_HPTXQTOP_RESET 0x0 + #define USB_HPTXSTS_HPTXQSPCAVAIL_BITS 23:16 + #define USB_HPTXSTS_HPTXQSPCAVAIL_SET 0x00ff0000 + #define USB_HPTXSTS_HPTXQSPCAVAIL_CLR 0xff00ffff + #define USB_HPTXSTS_HPTXQSPCAVAIL_MSB 23 + #define USB_HPTXSTS_HPTXQSPCAVAIL_LSB 16 + #define USB_HPTXSTS_HPTXQSPCAVAIL_RESET 0x0 + #define USB_HPTXSTS_HPTXFSPCAVAIL_BITS 15:0 + #define USB_HPTXSTS_HPTXFSPCAVAIL_SET 0x0000ffff + #define USB_HPTXSTS_HPTXFSPCAVAIL_CLR 0xffff0000 + #define USB_HPTXSTS_HPTXFSPCAVAIL_MSB 15 + #define USB_HPTXSTS_HPTXFSPCAVAIL_LSB 0 + #define USB_HPTXSTS_HPTXFSPCAVAIL_RESET 0x0 +#define USB_HAINT HW_REGISTER_RW( 0x7e980414 ) + #define USB_HAINT_MASK 0xffffffff + #define USB_HAINT_WIDTH 32 +#define USB_HAINTMSK HW_REGISTER_RW( 0x7e980418 ) + #define USB_HAINTMSK_MASK 0xffffffff + #define USB_HAINTMSK_WIDTH 32 +#define USB_HPRT HW_REGISTER_RW( 0x7e980440 ) + #define USB_HPRT_MASK 0x0007fdff + #define USB_HPRT_WIDTH 19 + #define USB_HPRT_SPD_BITS 18:17 + #define USB_HPRT_SPD_SET 0x00060000 + #define USB_HPRT_SPD_CLR 0xfff9ffff + #define USB_HPRT_SPD_MSB 18 + #define USB_HPRT_SPD_LSB 17 + #define USB_HPRT_SPD_RESET 0x0 + #define USB_HPRT_TST_CTL_BITS 16:13 + #define USB_HPRT_TST_CTL_SET 0x0001e000 + #define USB_HPRT_TST_CTL_CLR 0xfffe1fff + #define USB_HPRT_TST_CTL_MSB 16 + #define USB_HPRT_TST_CTL_LSB 13 + #define USB_HPRT_TST_CTL_RESET 0x0 + #define USB_HPRT_PWR_BITS 12:12 + #define USB_HPRT_PWR_SET 0x00001000 + #define USB_HPRT_PWR_CLR 0xffffefff + #define USB_HPRT_PWR_MSB 12 + #define USB_HPRT_PWR_LSB 12 + #define USB_HPRT_PWR_RESET 0x0 + #define USB_HPRT_LN_STS_BITS 11:10 + #define USB_HPRT_LN_STS_SET 0x00000c00 + #define USB_HPRT_LN_STS_CLR 0xfffff3ff + #define USB_HPRT_LN_STS_MSB 11 + #define USB_HPRT_LN_STS_LSB 10 + #define USB_HPRT_LN_STS_RESET 0x0 + #define USB_HPRT_RST_BITS 8:8 + #define USB_HPRT_RST_SET 0x00000100 + #define USB_HPRT_RST_CLR 0xfffffeff + #define USB_HPRT_RST_MSB 8 + #define USB_HPRT_RST_LSB 8 + #define USB_HPRT_RST_RESET 0x0 + #define USB_HPRT_SUSP_BITS 7:7 + #define USB_HPRT_SUSP_SET 0x00000080 + #define USB_HPRT_SUSP_CLR 0xffffff7f + #define USB_HPRT_SUSP_MSB 7 + #define USB_HPRT_SUSP_LSB 7 + #define USB_HPRT_SUSP_RESET 0x0 + #define USB_HPRT_RES_BITS 6:6 + #define USB_HPRT_RES_SET 0x00000040 + #define USB_HPRT_RES_CLR 0xffffffbf + #define USB_HPRT_RES_MSB 6 + #define USB_HPRT_RES_LSB 6 + #define USB_HPRT_RES_RESET 0x0 + #define USB_HPRT_OVR_CURR_CHNG_BITS 5:5 + #define USB_HPRT_OVR_CURR_CHNG_SET 0x00000020 + #define USB_HPRT_OVR_CURR_CHNG_CLR 0xffffffdf + #define USB_HPRT_OVR_CURR_CHNG_MSB 5 + #define USB_HPRT_OVR_CURR_CHNG_LSB 5 + #define USB_HPRT_OVR_CURR_CHNG_RESET 0x0 + #define USB_HPRT_OVR_CURR_ACT_BITS 4:4 + #define USB_HPRT_OVR_CURR_ACT_SET 0x00000010 + #define USB_HPRT_OVR_CURR_ACT_CLR 0xffffffef + #define USB_HPRT_OVR_CURR_ACT_MSB 4 + #define USB_HPRT_OVR_CURR_ACT_LSB 4 + #define USB_HPRT_OVR_CURR_ACT_RESET 0x0 + #define USB_HPRT_EN_CHNG_BITS 3:3 + #define USB_HPRT_EN_CHNG_SET 0x00000008 + #define USB_HPRT_EN_CHNG_CLR 0xfffffff7 + #define USB_HPRT_EN_CHNG_MSB 3 + #define USB_HPRT_EN_CHNG_LSB 3 + #define USB_HPRT_EN_CHNG_RESET 0x0 + #define USB_HPRT_ENA_BITS 2:2 + #define USB_HPRT_ENA_SET 0x00000004 + #define USB_HPRT_ENA_CLR 0xfffffffb + #define USB_HPRT_ENA_MSB 2 + #define USB_HPRT_ENA_LSB 2 + #define USB_HPRT_ENA_RESET 0x0 + #define USB_HPRT_CONN_DET_BITS 1:1 + #define USB_HPRT_CONN_DET_SET 0x00000002 + #define USB_HPRT_CONN_DET_CLR 0xfffffffd + #define USB_HPRT_CONN_DET_MSB 1 + #define USB_HPRT_CONN_DET_LSB 1 + #define USB_HPRT_CONN_DET_RESET 0x0 + #define USB_HPRT_CONN_STS_BITS 0:0 + #define USB_HPRT_CONN_STS_SET 0x00000001 + #define USB_HPRT_CONN_STS_CLR 0xfffffffe + #define USB_HPRT_CONN_STS_MSB 0 + #define USB_HPRT_CONN_STS_LSB 0 + #define USB_HPRT_CONN_STS_RESET 0x0 +#define USB_HCCHAR0 HW_REGISTER_RW( 0x7e980500 ) + #define USB_HCCHAR0_MASK 0xffffffff + #define USB_HCCHAR0_WIDTH 32 + #define USB_HCCHAR0_CH_ENA_BITS 31:31 + #define USB_HCCHAR0_CH_ENA_SET 0x80000000 + #define USB_HCCHAR0_CH_ENA_CLR 0x7fffffff + #define USB_HCCHAR0_CH_ENA_MSB 31 + #define USB_HCCHAR0_CH_ENA_LSB 31 + #define USB_HCCHAR0_CH_ENA_RESET 0x0 + #define USB_HCCHAR0_CH_DIS_BITS 30:30 + #define USB_HCCHAR0_CH_DIS_SET 0x40000000 + #define USB_HCCHAR0_CH_DIS_CLR 0xbfffffff + #define USB_HCCHAR0_CH_DIS_MSB 30 + #define USB_HCCHAR0_CH_DIS_LSB 30 + #define USB_HCCHAR0_CH_DIS_RESET 0x0 + #define USB_HCCHAR0_ODD_FRM_BITS 29:29 + #define USB_HCCHAR0_ODD_FRM_SET 0x20000000 + #define USB_HCCHAR0_ODD_FRM_CLR 0xdfffffff + #define USB_HCCHAR0_ODD_FRM_MSB 29 + #define USB_HCCHAR0_ODD_FRM_LSB 29 + #define USB_HCCHAR0_ODD_FRM_RESET 0x0 + #define USB_HCCHAR0_DEV_ADDR_BITS 28:22 + #define USB_HCCHAR0_DEV_ADDR_SET 0x1fc00000 + #define USB_HCCHAR0_DEV_ADDR_CLR 0xe03fffff + #define USB_HCCHAR0_DEV_ADDR_MSB 28 + #define USB_HCCHAR0_DEV_ADDR_LSB 22 + #define USB_HCCHAR0_DEV_ADDR_RESET 0x0 + #define USB_HCCHAR0_MC_EC_BITS 21:20 + #define USB_HCCHAR0_MC_EC_SET 0x00300000 + #define USB_HCCHAR0_MC_EC_CLR 0xffcfffff + #define USB_HCCHAR0_MC_EC_MSB 21 + #define USB_HCCHAR0_MC_EC_LSB 20 + #define USB_HCCHAR0_MC_EC_RESET 0x0 + #define USB_HCCHAR0_EP_TYPE_BITS 19:18 + #define USB_HCCHAR0_EP_TYPE_SET 0x000c0000 + #define USB_HCCHAR0_EP_TYPE_CLR 0xfff3ffff + #define USB_HCCHAR0_EP_TYPE_MSB 19 + #define USB_HCCHAR0_EP_TYPE_LSB 18 + #define USB_HCCHAR0_EP_TYPE_RESET 0x0 + #define USB_HCCHAR0_LSPD_DEV_BITS 17:17 + #define USB_HCCHAR0_LSPD_DEV_SET 0x00020000 + #define USB_HCCHAR0_LSPD_DEV_CLR 0xfffdffff + #define USB_HCCHAR0_LSPD_DEV_MSB 17 + #define USB_HCCHAR0_LSPD_DEV_LSB 17 + #define USB_HCCHAR0_LSPD_DEV_RESET 0x0 + #define USB_HCCHAR0_EP_DIR_BITS 15:15 + #define USB_HCCHAR0_EP_DIR_SET 0x00008000 + #define USB_HCCHAR0_EP_DIR_CLR 0xffff7fff + #define USB_HCCHAR0_EP_DIR_MSB 15 + #define USB_HCCHAR0_EP_DIR_LSB 15 + #define USB_HCCHAR0_EP_DIR_RESET 0x0 + #define USB_HCCHAR0_EP_NUM_BITS 14:11 + #define USB_HCCHAR0_EP_NUM_SET 0x00007800 + #define USB_HCCHAR0_EP_NUM_CLR 0xffff87ff + #define USB_HCCHAR0_EP_NUM_MSB 14 + #define USB_HCCHAR0_EP_NUM_LSB 11 + #define USB_HCCHAR0_EP_NUM_RESET 0x0 + #define USB_HCCHAR0_MPS_BITS 10:0 + #define USB_HCCHAR0_MPS_SET 0x000007ff + #define USB_HCCHAR0_MPS_CLR 0xfffff800 + #define USB_HCCHAR0_MPS_MSB 10 + #define USB_HCCHAR0_MPS_LSB 0 + #define USB_HCCHAR0_MPS_RESET 0x0 +#define USB_HCSPLT0 HW_REGISTER_RW( 0x7e980504 ) + #define USB_HCSPLT0_MASK 0xffffffff + #define USB_HCSPLT0_WIDTH 32 + #define USB_HCSPLT0_SPLT_ENA_BITS 31:31 + #define USB_HCSPLT0_SPLT_ENA_SET 0x80000000 + #define USB_HCSPLT0_SPLT_ENA_CLR 0x7fffffff + #define USB_HCSPLT0_SPLT_ENA_MSB 31 + #define USB_HCSPLT0_SPLT_ENA_LSB 31 + #define USB_HCSPLT0_SPLT_ENA_RESET 0x0 + #define USB_HCSPLT0_COMP_SPLT_BITS 16:16 + #define USB_HCSPLT0_COMP_SPLT_SET 0x00010000 + #define USB_HCSPLT0_COMP_SPLT_CLR 0xfffeffff + #define USB_HCSPLT0_COMP_SPLT_MSB 16 + #define USB_HCSPLT0_COMP_SPLT_LSB 16 + #define USB_HCSPLT0_COMP_SPLT_RESET 0x0 + #define USB_HCSPLT0_XACT_POS_BITS 15:14 + #define USB_HCSPLT0_XACT_POS_SET 0x0000c000 + #define USB_HCSPLT0_XACT_POS_CLR 0xffff3fff + #define USB_HCSPLT0_XACT_POS_MSB 15 + #define USB_HCSPLT0_XACT_POS_LSB 14 + #define USB_HCSPLT0_XACT_POS_RESET 0x0 + #define USB_HCSPLT0_HUB_ADDR_BITS 13:7 + #define USB_HCSPLT0_HUB_ADDR_SET 0x00003f80 + #define USB_HCSPLT0_HUB_ADDR_CLR 0xffffc07f + #define USB_HCSPLT0_HUB_ADDR_MSB 13 + #define USB_HCSPLT0_HUB_ADDR_LSB 7 + #define USB_HCSPLT0_HUB_ADDR_RESET 0x0 + #define USB_HCSPLT0_PRT_ADDR_BITS 6:0 + #define USB_HCSPLT0_PRT_ADDR_SET 0x0000007f + #define USB_HCSPLT0_PRT_ADDR_CLR 0xffffff80 + #define USB_HCSPLT0_PRT_ADDR_MSB 6 + #define USB_HCSPLT0_PRT_ADDR_LSB 0 + #define USB_HCSPLT0_PRT_ADDR_RESET 0x0 +#define USB_HCINT0 HW_REGISTER_RW( 0x7e980508 ) + #define USB_HCINT0_MASK 0xffffffff + #define USB_HCINT0_WIDTH 32 + #define USB_HCINT0_DATA_TGL_ERR_BITS 10:10 + #define USB_HCINT0_DATA_TGL_ERR_SET 0x00000400 + #define USB_HCINT0_DATA_TGL_ERR_CLR 0xfffffbff + #define USB_HCINT0_DATA_TGL_ERR_MSB 10 + #define USB_HCINT0_DATA_TGL_ERR_LSB 10 + #define USB_HCINT0_DATA_TGL_ERR_RESET 0x0 + #define USB_HCINT0_FRM_OVRUN_BITS 9:9 + #define USB_HCINT0_FRM_OVRUN_SET 0x00000200 + #define USB_HCINT0_FRM_OVRUN_CLR 0xfffffdff + #define USB_HCINT0_FRM_OVRUN_MSB 9 + #define USB_HCINT0_FRM_OVRUN_LSB 9 + #define USB_HCINT0_FRM_OVRUN_RESET 0x0 + #define USB_HCINT0_BBL_ERR_BITS 8:8 + #define USB_HCINT0_BBL_ERR_SET 0x00000100 + #define USB_HCINT0_BBL_ERR_CLR 0xfffffeff + #define USB_HCINT0_BBL_ERR_MSB 8 + #define USB_HCINT0_BBL_ERR_LSB 8 + #define USB_HCINT0_BBL_ERR_RESET 0x0 + #define USB_HCINT0_XACT_ERR_BITS 7:7 + #define USB_HCINT0_XACT_ERR_SET 0x00000080 + #define USB_HCINT0_XACT_ERR_CLR 0xffffff7f + #define USB_HCINT0_XACT_ERR_MSB 7 + #define USB_HCINT0_XACT_ERR_LSB 7 + #define USB_HCINT0_XACT_ERR_RESET 0x0 + #define USB_HCINT0_NYET_BITS 6:6 + #define USB_HCINT0_NYET_SET 0x00000040 + #define USB_HCINT0_NYET_CLR 0xffffffbf + #define USB_HCINT0_NYET_MSB 6 + #define USB_HCINT0_NYET_LSB 6 + #define USB_HCINT0_NYET_RESET 0x0 + #define USB_HCINT0_ACK_BITS 5:5 + #define USB_HCINT0_ACK_SET 0x00000020 + #define USB_HCINT0_ACK_CLR 0xffffffdf + #define USB_HCINT0_ACK_MSB 5 + #define USB_HCINT0_ACK_LSB 5 + #define USB_HCINT0_ACK_RESET 0x0 + #define USB_HCINT0_NAK_BITS 4:4 + #define USB_HCINT0_NAK_SET 0x00000010 + #define USB_HCINT0_NAK_CLR 0xffffffef + #define USB_HCINT0_NAK_MSB 4 + #define USB_HCINT0_NAK_LSB 4 + #define USB_HCINT0_NAK_RESET 0x0 + #define USB_HCINT0_STALL_BITS 3:3 + #define USB_HCINT0_STALL_SET 0x00000008 + #define USB_HCINT0_STALL_CLR 0xfffffff7 + #define USB_HCINT0_STALL_MSB 3 + #define USB_HCINT0_STALL_LSB 3 + #define USB_HCINT0_STALL_RESET 0x0 + #define USB_HCINT0_AHB_ERR_BITS 2:2 + #define USB_HCINT0_AHB_ERR_SET 0x00000004 + #define USB_HCINT0_AHB_ERR_CLR 0xfffffffb + #define USB_HCINT0_AHB_ERR_MSB 2 + #define USB_HCINT0_AHB_ERR_LSB 2 + #define USB_HCINT0_AHB_ERR_RESET 0x0 + #define USB_HCINT0_CH_HLTD_BITS 1:1 + #define USB_HCINT0_CH_HLTD_SET 0x00000002 + #define USB_HCINT0_CH_HLTD_CLR 0xfffffffd + #define USB_HCINT0_CH_HLTD_MSB 1 + #define USB_HCINT0_CH_HLTD_LSB 1 + #define USB_HCINT0_CH_HLTD_RESET 0x0 + #define USB_HCINT0_XFER_COMPL_BITS 0:0 + #define USB_HCINT0_XFER_COMPL_SET 0x00000001 + #define USB_HCINT0_XFER_COMPL_CLR 0xfffffffe + #define USB_HCINT0_XFER_COMPL_MSB 0 + #define USB_HCINT0_XFER_COMPL_LSB 0 + #define USB_HCINT0_XFER_COMPL_RESET 0x0 +#define USB_HCINTMSK0 HW_REGISTER_RW( 0x7e98050c ) + #define USB_HCINTMSK0_MASK 0xffffffff + #define USB_HCINTMSK0_WIDTH 32 +#define USB_HCTSIZ0 HW_REGISTER_RW( 0x7e980510 ) + #define USB_HCTSIZ0_MASK 0xffffffff + #define USB_HCTSIZ0_WIDTH 32 + #define USB_HCTSIZ0_DO_PNG_BITS 31:31 + #define USB_HCTSIZ0_DO_PNG_SET 0x80000000 + #define USB_HCTSIZ0_DO_PNG_CLR 0x7fffffff + #define USB_HCTSIZ0_DO_PNG_MSB 31 + #define USB_HCTSIZ0_DO_PNG_LSB 31 + #define USB_HCTSIZ0_DO_PNG_RESET 0x0 + #define USB_HCTSIZ0_PID_BITS 30:29 + #define USB_HCTSIZ0_PID_SET 0x60000000 + #define USB_HCTSIZ0_PID_CLR 0x9fffffff + #define USB_HCTSIZ0_PID_MSB 30 + #define USB_HCTSIZ0_PID_LSB 29 + #define USB_HCTSIZ0_PID_RESET 0x0 + #define USB_HCTSIZ0_PKT_CNT_BITS 28:19 + #define USB_HCTSIZ0_PKT_CNT_SET 0x1ff80000 + #define USB_HCTSIZ0_PKT_CNT_CLR 0xe007ffff + #define USB_HCTSIZ0_PKT_CNT_MSB 28 + #define USB_HCTSIZ0_PKT_CNT_LSB 19 + #define USB_HCTSIZ0_PKT_CNT_RESET 0x0 + #define USB_HCTSIZ0_XFER_SIZE_BITS 18:0 + #define USB_HCTSIZ0_XFER_SIZE_SET 0x0007ffff + #define USB_HCTSIZ0_XFER_SIZE_CLR 0xfff80000 + #define USB_HCTSIZ0_XFER_SIZE_MSB 18 + #define USB_HCTSIZ0_XFER_SIZE_LSB 0 + #define USB_HCTSIZ0_XFER_SIZE_RESET 0x0 +#define USB_HCDMA0 HW_REGISTER_RW( 0x7e980514 ) + #define USB_HCDMA0_MASK 0xffffffff + #define USB_HCDMA0_WIDTH 32 +#define USB_HCCHAR1 HW_REGISTER_RW( 0x7e980520 ) + #define USB_HCCHAR1_MASK 0xffffffff + #define USB_HCCHAR1_WIDTH 32 +#define USB_HCSPLT1 HW_REGISTER_RW( 0x7e980524 ) + #define USB_HCSPLT1_MASK 0xffffffff + #define USB_HCSPLT1_WIDTH 32 +#define USB_HCINT1 HW_REGISTER_RW( 0x7e980528 ) + #define USB_HCINT1_MASK 0xffffffff + #define USB_HCINT1_WIDTH 32 +#define USB_HCINTMSK1 HW_REGISTER_RW( 0x7e98052c ) + #define USB_HCINTMSK1_MASK 0xffffffff + #define USB_HCINTMSK1_WIDTH 32 +#define USB_HCTSIZ1 HW_REGISTER_RW( 0x7e980530 ) + #define USB_HCTSIZ1_MASK 0xffffffff + #define USB_HCTSIZ1_WIDTH 32 +#define USB_HCDMA1 HW_REGISTER_RW( 0x7e980534 ) + #define USB_HCDMA1_MASK 0xffffffff + #define USB_HCDMA1_WIDTH 32 +#define USB_HCCHAR2 HW_REGISTER_RW( 0x7e980540 ) + #define USB_HCCHAR2_MASK 0xffffffff + #define USB_HCCHAR2_WIDTH 32 +#define USB_HCSPLT2 HW_REGISTER_RW( 0x7e980544 ) + #define USB_HCSPLT2_MASK 0xffffffff + #define USB_HCSPLT2_WIDTH 32 +#define USB_HCINT2 HW_REGISTER_RW( 0x7e980548 ) + #define USB_HCINT2_MASK 0xffffffff + #define USB_HCINT2_WIDTH 32 +#define USB_HCINTMSK2 HW_REGISTER_RW( 0x7e98054c ) + #define USB_HCINTMSK2_MASK 0xffffffff + #define USB_HCINTMSK2_WIDTH 32 +#define USB_HCTSIZ2 HW_REGISTER_RW( 0x7e980550 ) + #define USB_HCTSIZ2_MASK 0xffffffff + #define USB_HCTSIZ2_WIDTH 32 +#define USB_HCDMA2 HW_REGISTER_RW( 0x7e980554 ) + #define USB_HCDMA2_MASK 0xffffffff + #define USB_HCDMA2_WIDTH 32 +#define USB_HCCHAR3 HW_REGISTER_RW( 0x7e980560 ) + #define USB_HCCHAR3_MASK 0xffffffff + #define USB_HCCHAR3_WIDTH 32 +#define USB_HCSPLT3 HW_REGISTER_RW( 0x7e980564 ) + #define USB_HCSPLT3_MASK 0xffffffff + #define USB_HCSPLT3_WIDTH 32 +#define USB_HCINT3 HW_REGISTER_RW( 0x7e980568 ) + #define USB_HCINT3_MASK 0xffffffff + #define USB_HCINT3_WIDTH 32 +#define USB_HCINTMSK3 HW_REGISTER_RW( 0x7e98056c ) + #define USB_HCINTMSK3_MASK 0xffffffff + #define USB_HCINTMSK3_WIDTH 32 +#define USB_HCTSIZ3 HW_REGISTER_RW( 0x7e980570 ) + #define USB_HCTSIZ3_MASK 0xffffffff + #define USB_HCTSIZ3_WIDTH 32 +#define USB_HCDMA3 HW_REGISTER_RW( 0x7e980574 ) + #define USB_HCDMA3_MASK 0xffffffff + #define USB_HCDMA3_WIDTH 32 +#define USB_HCCHAR4 HW_REGISTER_RW( 0x7e980580 ) + #define USB_HCCHAR4_MASK 0xffffffff + #define USB_HCCHAR4_WIDTH 32 +#define USB_HCSPLT4 HW_REGISTER_RW( 0x7e980584 ) + #define USB_HCSPLT4_MASK 0xffffffff + #define USB_HCSPLT4_WIDTH 32 +#define USB_HCINT4 HW_REGISTER_RW( 0x7e980588 ) + #define USB_HCINT4_MASK 0xffffffff + #define USB_HCINT4_WIDTH 32 +#define USB_HCINTMSK4 HW_REGISTER_RW( 0x7e98058c ) + #define USB_HCINTMSK4_MASK 0xffffffff + #define USB_HCINTMSK4_WIDTH 32 +#define USB_HCTSIZ4 HW_REGISTER_RW( 0x7e980590 ) + #define USB_HCTSIZ4_MASK 0xffffffff + #define USB_HCTSIZ4_WIDTH 32 +#define USB_HCDMA4 HW_REGISTER_RW( 0x7e980594 ) + #define USB_HCDMA4_MASK 0xffffffff + #define USB_HCDMA4_WIDTH 32 +#define USB_HCCHAR5 HW_REGISTER_RW( 0x7e9805a0 ) + #define USB_HCCHAR5_MASK 0xffffffff + #define USB_HCCHAR5_WIDTH 32 +#define USB_HCSPLT5 HW_REGISTER_RW( 0x7e9805a4 ) + #define USB_HCSPLT5_MASK 0xffffffff + #define USB_HCSPLT5_WIDTH 32 +#define USB_HCINT5 HW_REGISTER_RW( 0x7e9805a8 ) + #define USB_HCINT5_MASK 0xffffffff + #define USB_HCINT5_WIDTH 32 +#define USB_HCINTMSK5 HW_REGISTER_RW( 0x7e9805ac ) + #define USB_HCINTMSK5_MASK 0xffffffff + #define USB_HCINTMSK5_WIDTH 32 +#define USB_HCTSIZ5 HW_REGISTER_RW( 0x7e9805b0 ) + #define USB_HCTSIZ5_MASK 0xffffffff + #define USB_HCTSIZ5_WIDTH 32 +#define USB_HCDMA5 HW_REGISTER_RW( 0x7e9805b4 ) + #define USB_HCDMA5_MASK 0xffffffff + #define USB_HCDMA5_WIDTH 32 +#define USB_HCCHAR6 HW_REGISTER_RW( 0x7e9805c0 ) + #define USB_HCCHAR6_MASK 0xffffffff + #define USB_HCCHAR6_WIDTH 32 +#define USB_HCSPLT6 HW_REGISTER_RW( 0x7e9805c4 ) + #define USB_HCSPLT6_MASK 0xffffffff + #define USB_HCSPLT6_WIDTH 32 +#define USB_HCINT6 HW_REGISTER_RW( 0x7e9805c8 ) + #define USB_HCINT6_MASK 0xffffffff + #define USB_HCINT6_WIDTH 32 +#define USB_HCINTMSK6 HW_REGISTER_RW( 0x7e9805cc ) + #define USB_HCINTMSK6_MASK 0xffffffff + #define USB_HCINTMSK6_WIDTH 32 +#define USB_HCTSIZ6 HW_REGISTER_RW( 0x7e9805d0 ) + #define USB_HCTSIZ6_MASK 0xffffffff + #define USB_HCTSIZ6_WIDTH 32 +#define USB_HCDMA6 HW_REGISTER_RW( 0x7e9805d4 ) + #define USB_HCDMA6_MASK 0xffffffff + #define USB_HCDMA6_WIDTH 32 +#define USB_HCCHAR7 HW_REGISTER_RW( 0x7e9805e0 ) + #define USB_HCCHAR7_MASK 0xffffffff + #define USB_HCCHAR7_WIDTH 32 +#define USB_HCSPLT7 HW_REGISTER_RW( 0x7e9805e4 ) + #define USB_HCSPLT7_MASK 0xffffffff + #define USB_HCSPLT7_WIDTH 32 +#define USB_HCINT7 HW_REGISTER_RW( 0x7e9805e8 ) + #define USB_HCINT7_MASK 0xffffffff + #define USB_HCINT7_WIDTH 32 +#define USB_HCINTMSK7 HW_REGISTER_RW( 0x7e9805ec ) + #define USB_HCINTMSK7_MASK 0xffffffff + #define USB_HCINTMSK7_WIDTH 32 +#define USB_HCTSIZ7 HW_REGISTER_RW( 0x7e9805f0 ) + #define USB_HCTSIZ7_MASK 0xffffffff + #define USB_HCTSIZ7_WIDTH 32 +#define USB_HCDMA7 HW_REGISTER_RW( 0x7e9805f4 ) + #define USB_HCDMA7_MASK 0xffffffff + #define USB_HCDMA7_WIDTH 32 +#define USB_DCFG HW_REGISTER_RW( 0x7e980800 ) + #define USB_DCFG_MASK 0x03fc1ff7 + #define USB_DCFG_WIDTH 26 + #define USB_DCFG_PER_SCH_INTV_BITS 25:24 + #define USB_DCFG_PER_SCH_INTV_SET 0x03000000 + #define USB_DCFG_PER_SCH_INTV_CLR 0xfcffffff + #define USB_DCFG_PER_SCH_INTV_MSB 25 + #define USB_DCFG_PER_SCH_INTV_LSB 24 + #define USB_DCFG_PER_SCH_INTV_RESET 0x0 + #define USB_DCFG_DESC_DMA_BITS 23:23 + #define USB_DCFG_DESC_DMA_SET 0x00800000 + #define USB_DCFG_DESC_DMA_CLR 0xff7fffff + #define USB_DCFG_DESC_DMA_MSB 23 + #define USB_DCFG_DESC_DMA_LSB 23 + #define USB_DCFG_DESC_DMA_RESET 0x0 + #define USB_DCFG_EP_MIS_CNT_BITS 22:18 + #define USB_DCFG_EP_MIS_CNT_SET 0x007c0000 + #define USB_DCFG_EP_MIS_CNT_CLR 0xff83ffff + #define USB_DCFG_EP_MIS_CNT_MSB 22 + #define USB_DCFG_EP_MIS_CNT_LSB 18 + #define USB_DCFG_EP_MIS_CNT_RESET 0x0 + #define USB_DCFG_PER_FR_INT_BITS 12:11 + #define USB_DCFG_PER_FR_INT_SET 0x00001800 + #define USB_DCFG_PER_FR_INT_CLR 0xffffe7ff + #define USB_DCFG_PER_FR_INT_MSB 12 + #define USB_DCFG_PER_FR_INT_LSB 11 + #define USB_DCFG_PER_FR_INT_RESET 0x0 + #define USB_DCFG_DEV_ADDR_BITS 10:4 + #define USB_DCFG_DEV_ADDR_SET 0x000007f0 + #define USB_DCFG_DEV_ADDR_CLR 0xfffff80f + #define USB_DCFG_DEV_ADDR_MSB 10 + #define USB_DCFG_DEV_ADDR_LSB 4 + #define USB_DCFG_DEV_ADDR_RESET 0x0 + #define USB_DCFG_NZ_STS_OUT_HSHK_BITS 2:2 + #define USB_DCFG_NZ_STS_OUT_HSHK_SET 0x00000004 + #define USB_DCFG_NZ_STS_OUT_HSHK_CLR 0xfffffffb + #define USB_DCFG_NZ_STS_OUT_HSHK_MSB 2 + #define USB_DCFG_NZ_STS_OUT_HSHK_LSB 2 + #define USB_DCFG_NZ_STS_OUT_HSHK_RESET 0x0 + #define USB_DCFG_DEV_SPD_BITS 1:0 + #define USB_DCFG_DEV_SPD_SET 0x00000003 + #define USB_DCFG_DEV_SPD_CLR 0xfffffffc + #define USB_DCFG_DEV_SPD_MSB 1 + #define USB_DCFG_DEV_SPD_LSB 0 + #define USB_DCFG_DEV_SPD_RESET 0x0 +#define USB_DCTL HW_REGISTER_RW( 0x7e980804 ) + #define USB_DCTL_MASK 0x0000efff + #define USB_DCTL_WIDTH 16 + #define USB_DCTL_IGN_FRM_NUM_BITS 15:15 + #define USB_DCTL_IGN_FRM_NUM_SET 0x00008000 + #define USB_DCTL_IGN_FRM_NUM_CLR 0xffff7fff + #define USB_DCTL_IGN_FRM_NUM_MSB 15 + #define USB_DCTL_IGN_FRM_NUM_LSB 15 + #define USB_DCTL_IGN_FRM_NUM_RESET 0x0 + #define USB_DCTL_GMC_BITS 14:13 + #define USB_DCTL_GMC_SET 0x00006000 + #define USB_DCTL_GMC_CLR 0xffff9fff + #define USB_DCTL_GMC_MSB 14 + #define USB_DCTL_GMC_LSB 13 + #define USB_DCTL_GMC_RESET 0x0 + #define USB_DCTL_PWRON_PRG_DONE_BITS 11:11 + #define USB_DCTL_PWRON_PRG_DONE_SET 0x00000800 + #define USB_DCTL_PWRON_PRG_DONE_CLR 0xfffff7ff + #define USB_DCTL_PWRON_PRG_DONE_MSB 11 + #define USB_DCTL_PWRON_PRG_DONE_LSB 11 + #define USB_DCTL_PWRON_PRG_DONE_RESET 0x0 + #define USB_DCTL_CGOUT_NAK_BITS 10:10 + #define USB_DCTL_CGOUT_NAK_SET 0x00000400 + #define USB_DCTL_CGOUT_NAK_CLR 0xfffffbff + #define USB_DCTL_CGOUT_NAK_MSB 10 + #define USB_DCTL_CGOUT_NAK_LSB 10 + #define USB_DCTL_CGOUT_NAK_RESET 0x0 + #define USB_DCTL_SGOUT_NAK_BITS 9:9 + #define USB_DCTL_SGOUT_NAK_SET 0x00000200 + #define USB_DCTL_SGOUT_NAK_CLR 0xfffffdff + #define USB_DCTL_SGOUT_NAK_MSB 9 + #define USB_DCTL_SGOUT_NAK_LSB 9 + #define USB_DCTL_SGOUT_NAK_RESET 0x0 + #define USB_DCTL_CGNP_IN_NAK_BITS 8:8 + #define USB_DCTL_CGNP_IN_NAK_SET 0x00000100 + #define USB_DCTL_CGNP_IN_NAK_CLR 0xfffffeff + #define USB_DCTL_CGNP_IN_NAK_MSB 8 + #define USB_DCTL_CGNP_IN_NAK_LSB 8 + #define USB_DCTL_CGNP_IN_NAK_RESET 0x0 + #define USB_DCTL_SGNP_IN_NAK_BITS 7:7 + #define USB_DCTL_SGNP_IN_NAK_SET 0x00000080 + #define USB_DCTL_SGNP_IN_NAK_CLR 0xffffff7f + #define USB_DCTL_SGNP_IN_NAK_MSB 7 + #define USB_DCTL_SGNP_IN_NAK_LSB 7 + #define USB_DCTL_SGNP_IN_NAK_RESET 0x0 + #define USB_DCTL_TST_CTL_BITS 6:4 + #define USB_DCTL_TST_CTL_SET 0x00000070 + #define USB_DCTL_TST_CTL_CLR 0xffffff8f + #define USB_DCTL_TST_CTL_MSB 6 + #define USB_DCTL_TST_CTL_LSB 4 + #define USB_DCTL_TST_CTL_RESET 0x0 + #define USB_DCTL_GOUT_NAK_STS_BITS 3:3 + #define USB_DCTL_GOUT_NAK_STS_SET 0x00000008 + #define USB_DCTL_GOUT_NAK_STS_CLR 0xfffffff7 + #define USB_DCTL_GOUT_NAK_STS_MSB 3 + #define USB_DCTL_GOUT_NAK_STS_LSB 3 + #define USB_DCTL_GOUT_NAK_STS_RESET 0x0 + #define USB_DCTL_GNP_IN_NAK_STS_BITS 2:2 + #define USB_DCTL_GNP_IN_NAK_STS_SET 0x00000004 + #define USB_DCTL_GNP_IN_NAK_STS_CLR 0xfffffffb + #define USB_DCTL_GNP_IN_NAK_STS_MSB 2 + #define USB_DCTL_GNP_IN_NAK_STS_LSB 2 + #define USB_DCTL_GNP_IN_NAK_STS_RESET 0x0 + #define USB_DCTL_SFT_DISCON_BITS 1:1 + #define USB_DCTL_SFT_DISCON_SET 0x00000002 + #define USB_DCTL_SFT_DISCON_CLR 0xfffffffd + #define USB_DCTL_SFT_DISCON_MSB 1 + #define USB_DCTL_SFT_DISCON_LSB 1 + #define USB_DCTL_SFT_DISCON_RESET 0x0 + #define USB_DCTL_RMT_WKUP_SIG_BITS 0:0 + #define USB_DCTL_RMT_WKUP_SIG_SET 0x00000001 + #define USB_DCTL_RMT_WKUP_SIG_CLR 0xfffffffe + #define USB_DCTL_RMT_WKUP_SIG_MSB 0 + #define USB_DCTL_RMT_WKUP_SIG_LSB 0 + #define USB_DCTL_RMT_WKUP_SIG_RESET 0x0 +#define USB_DSTS HW_REGISTER_RW( 0x7e980808 ) + #define USB_DSTS_MASK 0x003fff0f + #define USB_DSTS_WIDTH 22 + #define USB_DSTS_SOF_FN_BITS 21:8 + #define USB_DSTS_SOF_FN_SET 0x003fff00 + #define USB_DSTS_SOF_FN_CLR 0xffc000ff + #define USB_DSTS_SOF_FN_MSB 21 + #define USB_DSTS_SOF_FN_LSB 8 + #define USB_DSTS_SOF_FN_RESET 0x0 + #define USB_DSTS_ERRTIC_ERR_BITS 3:3 + #define USB_DSTS_ERRTIC_ERR_SET 0x00000008 + #define USB_DSTS_ERRTIC_ERR_CLR 0xfffffff7 + #define USB_DSTS_ERRTIC_ERR_MSB 3 + #define USB_DSTS_ERRTIC_ERR_LSB 3 + #define USB_DSTS_ERRTIC_ERR_RESET 0x0 + #define USB_DSTS_ENUM_SPD_BITS 2:1 + #define USB_DSTS_ENUM_SPD_SET 0x00000006 + #define USB_DSTS_ENUM_SPD_CLR 0xfffffff9 + #define USB_DSTS_ENUM_SPD_MSB 2 + #define USB_DSTS_ENUM_SPD_LSB 1 + #define USB_DSTS_ENUM_SPD_RESET 0x0 + #define USB_DSTS_SUSP_STS_BITS 0:0 + #define USB_DSTS_SUSP_STS_SET 0x00000001 + #define USB_DSTS_SUSP_STS_CLR 0xfffffffe + #define USB_DSTS_SUSP_STS_MSB 0 + #define USB_DSTS_SUSP_STS_LSB 0 + #define USB_DSTS_SUSP_STS_RESET 0x0 +#define USB_DIEPMSK HW_REGISTER_RW( 0x7e980810 ) + #define USB_DIEPMSK_MASK 0xffffffff + #define USB_DIEPMSK_WIDTH 32 +#define USB_DOEPMSK HW_REGISTER_RW( 0x7e980814 ) + #define USB_DOEPMSK_MASK 0xffffffff + #define USB_DOEPMSK_WIDTH 32 +#define USB_DAINT HW_REGISTER_RW( 0x7e980818 ) + #define USB_DAINT_MASK 0xffffffff + #define USB_DAINT_WIDTH 32 + #define USB_DAINT_OUT_EP_INT_BITS 31:16 + #define USB_DAINT_OUT_EP_INT_SET 0xffff0000 + #define USB_DAINT_OUT_EP_INT_CLR 0x0000ffff + #define USB_DAINT_OUT_EP_INT_MSB 31 + #define USB_DAINT_OUT_EP_INT_LSB 16 + #define USB_DAINT_OUT_EP_INT_RESET 0x0 + #define USB_DAINT_IN_EP_INT_BITS 15:0 + #define USB_DAINT_IN_EP_INT_SET 0x0000ffff + #define USB_DAINT_IN_EP_INT_CLR 0xffff0000 + #define USB_DAINT_IN_EP_INT_MSB 15 + #define USB_DAINT_IN_EP_INT_LSB 0 + #define USB_DAINT_IN_EP_INT_RESET 0x0 +#define USB_DAINTMSK HW_REGISTER_RW( 0x7e98081c ) + #define USB_DAINTMSK_MASK 0xffffffff + #define USB_DAINTMSK_WIDTH 32 +#define USB_DTKNQR1 HW_REGISTER_RW( 0x7e980820 ) + #define USB_DTKNQR1_MASK 0xffffffff + #define USB_DTKNQR1_WIDTH 32 +#define USB_DTKNQR2 HW_REGISTER_RW( 0x7e980824 ) + #define USB_DTKNQR2_MASK 0xffffffff + #define USB_DTKNQR2_WIDTH 32 +#define USB_DVBUSDIS HW_REGISTER_RW( 0x7e980828 ) + #define USB_DVBUSDIS_MASK 0x0000ffff + #define USB_DVBUSDIS_WIDTH 16 +#define USB_DVBUSPULSE HW_REGISTER_RW( 0x7e98082c ) + #define USB_DVBUSPULSE_MASK 0x00000fff + #define USB_DVBUSPULSE_WIDTH 12 + #define USB_DVBUSPULSE_PULSE_BITS 11:0 + #define USB_DVBUSPULSE_PULSE_SET 0x00000fff + #define USB_DVBUSPULSE_PULSE_CLR 0xfffff000 + #define USB_DVBUSPULSE_PULSE_MSB 11 + #define USB_DVBUSPULSE_PULSE_LSB 0 + #define USB_DVBUSPULSE_PULSE_RESET 0x0 +#define USB_DTKNQR3 HW_REGISTER_RW( 0x7e980830 ) + #define USB_DTKNQR3_MASK 0xffffffff + #define USB_DTKNQR3_WIDTH 32 +#define USB_DTKNQR4 HW_REGISTER_RW( 0x7e980834 ) + #define USB_DTKNQR4_MASK 0xffffffff + #define USB_DTKNQR4_WIDTH 32 +#define USB_DTHRCTL HW_REGISTER_RW( 0x7e980830 ) + #define USB_DTHRCTL_MASK 0x0fff0fff + #define USB_DTHRCTL_WIDTH 28 + #define USB_DTHRCTL_ARB_PRK_EN_BITS 27:27 + #define USB_DTHRCTL_ARB_PRK_EN_SET 0x08000000 + #define USB_DTHRCTL_ARB_PRK_EN_CLR 0xf7ffffff + #define USB_DTHRCTL_ARB_PRK_EN_MSB 27 + #define USB_DTHRCTL_ARB_PRK_EN_LSB 27 + #define USB_DTHRCTL_ARB_PRK_EN_RESET 0x0 + #define USB_DTHRCTL_RX_THR_LEN_BITS 26:17 + #define USB_DTHRCTL_RX_THR_LEN_SET 0x07fe0000 + #define USB_DTHRCTL_RX_THR_LEN_CLR 0xf801ffff + #define USB_DTHRCTL_RX_THR_LEN_MSB 26 + #define USB_DTHRCTL_RX_THR_LEN_LSB 17 + #define USB_DTHRCTL_RX_THR_LEN_RESET 0x0 + #define USB_DTHRCTL_RX_THR_EN_BITS 16:16 + #define USB_DTHRCTL_RX_THR_EN_SET 0x00010000 + #define USB_DTHRCTL_RX_THR_EN_CLR 0xfffeffff + #define USB_DTHRCTL_RX_THR_EN_MSB 16 + #define USB_DTHRCTL_RX_THR_EN_LSB 16 + #define USB_DTHRCTL_RX_THR_EN_RESET 0x0 + #define USB_DTHRCTL_TX_THR_LEN_BITS 10:2 + #define USB_DTHRCTL_TX_THR_LEN_SET 0x000007fc + #define USB_DTHRCTL_TX_THR_LEN_CLR 0xfffff803 + #define USB_DTHRCTL_TX_THR_LEN_MSB 10 + #define USB_DTHRCTL_TX_THR_LEN_LSB 2 + #define USB_DTHRCTL_TX_THR_LEN_RESET 0x0 + #define USB_DTHRCTL_ISO_THR_EN_BITS 1:1 + #define USB_DTHRCTL_ISO_THR_EN_SET 0x00000002 + #define USB_DTHRCTL_ISO_THR_EN_CLR 0xfffffffd + #define USB_DTHRCTL_ISO_THR_EN_MSB 1 + #define USB_DTHRCTL_ISO_THR_EN_LSB 1 + #define USB_DTHRCTL_ISO_THR_EN_RESET 0x0 + #define USB_DTHRCTL_NON_ISO_THR_EN_BITS 0:0 + #define USB_DTHRCTL_NON_ISO_THR_EN_SET 0x00000001 + #define USB_DTHRCTL_NON_ISO_THR_EN_CLR 0xfffffffe + #define USB_DTHRCTL_NON_ISO_THR_EN_MSB 0 + #define USB_DTHRCTL_NON_ISO_THR_EN_LSB 0 + #define USB_DTHRCTL_NON_ISO_THR_EN_RESET 0x0 +#define USB_DIEPEMPMSK HW_REGISTER_RW( 0x7e980834 ) + #define USB_DIEPEMPMSK_MASK 0x0000ffff + #define USB_DIEPEMPMSK_WIDTH 16 + #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_BITS 15:0 + #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_SET 0x0000ffff + #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_CLR 0xffff0000 + #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_MSB 15 + #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_LSB 0 + #define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_RESET 0x0 +#define USB_DIEPCTL0 HW_REGISTER_RW( 0x7e980900 ) + #define USB_DIEPCTL0_MASK 0xffffffff + #define USB_DIEPCTL0_WIDTH 32 + #define USB_DIEPCTL0_ENA_BITS 31:31 + #define USB_DIEPCTL0_ENA_SET 0x80000000 + #define USB_DIEPCTL0_ENA_CLR 0x7fffffff + #define USB_DIEPCTL0_ENA_MSB 31 + #define USB_DIEPCTL0_ENA_LSB 31 + #define USB_DIEPCTL0_ENA_RESET 0x0 + #define USB_DIEPCTL0_DIS_BITS 30:30 + #define USB_DIEPCTL0_DIS_SET 0x40000000 + #define USB_DIEPCTL0_DIS_CLR 0xbfffffff + #define USB_DIEPCTL0_DIS_MSB 30 + #define USB_DIEPCTL0_DIS_LSB 30 + #define USB_DIEPCTL0_DIS_RESET 0x0 + #define USB_DIEPCTL0_SET_D1_PID_BITS 29:29 + #define USB_DIEPCTL0_SET_D1_PID_SET 0x20000000 + #define USB_DIEPCTL0_SET_D1_PID_CLR 0xdfffffff + #define USB_DIEPCTL0_SET_D1_PID_MSB 29 + #define USB_DIEPCTL0_SET_D1_PID_LSB 29 + #define USB_DIEPCTL0_SET_D1_PID_RESET 0x0 + #define USB_DIEPCTL0_SET_ODD_FR_BITS 29:29 + #define USB_DIEPCTL0_SET_ODD_FR_SET 0x20000000 + #define USB_DIEPCTL0_SET_ODD_FR_CLR 0xdfffffff + #define USB_DIEPCTL0_SET_ODD_FR_MSB 29 + #define USB_DIEPCTL0_SET_ODD_FR_LSB 29 + #define USB_DIEPCTL0_SET_ODD_FR_RESET 0x0 + #define USB_DIEPCTL0_SET_D0_PID_BITS 28:28 + #define USB_DIEPCTL0_SET_D0_PID_SET 0x10000000 + #define USB_DIEPCTL0_SET_D0_PID_CLR 0xefffffff + #define USB_DIEPCTL0_SET_D0_PID_MSB 28 + #define USB_DIEPCTL0_SET_D0_PID_LSB 28 + #define USB_DIEPCTL0_SET_D0_PID_RESET 0x0 + #define USB_DIEPCTL0_SET_EVEN_FR_BITS 28:28 + #define USB_DIEPCTL0_SET_EVEN_FR_SET 0x10000000 + #define USB_DIEPCTL0_SET_EVEN_FR_CLR 0xefffffff + #define USB_DIEPCTL0_SET_EVEN_FR_MSB 28 + #define USB_DIEPCTL0_SET_EVEN_FR_LSB 28 + #define USB_DIEPCTL0_SET_EVEN_FR_RESET 0x0 + #define USB_DIEPCTL0_SNAK_BITS 27:27 + #define USB_DIEPCTL0_SNAK_SET 0x08000000 + #define USB_DIEPCTL0_SNAK_CLR 0xf7ffffff + #define USB_DIEPCTL0_SNAK_MSB 27 + #define USB_DIEPCTL0_SNAK_LSB 27 + #define USB_DIEPCTL0_SNAK_RESET 0x0 + #define USB_DIEPCTL0_CNAK_BITS 26:26 + #define USB_DIEPCTL0_CNAK_SET 0x04000000 + #define USB_DIEPCTL0_CNAK_CLR 0xfbffffff + #define USB_DIEPCTL0_CNAK_MSB 26 + #define USB_DIEPCTL0_CNAK_LSB 26 + #define USB_DIEPCTL0_CNAK_RESET 0x0 + #define USB_DIEPCTL0_TXF_NUM_BITS 25:22 + #define USB_DIEPCTL0_TXF_NUM_SET 0x03c00000 + #define USB_DIEPCTL0_TXF_NUM_CLR 0xfc3fffff + #define USB_DIEPCTL0_TXF_NUM_MSB 25 + #define USB_DIEPCTL0_TXF_NUM_LSB 22 + #define USB_DIEPCTL0_TXF_NUM_RESET 0x0 + #define USB_DIEPCTL0_STALL_BITS 21:21 + #define USB_DIEPCTL0_STALL_SET 0x00200000 + #define USB_DIEPCTL0_STALL_CLR 0xffdfffff + #define USB_DIEPCTL0_STALL_MSB 21 + #define USB_DIEPCTL0_STALL_LSB 21 + #define USB_DIEPCTL0_STALL_RESET 0x0 + #define USB_DIEPCTL0_SNP_BITS 20:20 + #define USB_DIEPCTL0_SNP_SET 0x00100000 + #define USB_DIEPCTL0_SNP_CLR 0xffefffff + #define USB_DIEPCTL0_SNP_MSB 20 + #define USB_DIEPCTL0_SNP_LSB 20 + #define USB_DIEPCTL0_SNP_RESET 0x0 + #define USB_DIEPCTL0_TYPE_BITS 19:18 + #define USB_DIEPCTL0_TYPE_SET 0x000c0000 + #define USB_DIEPCTL0_TYPE_CLR 0xfff3ffff + #define USB_DIEPCTL0_TYPE_MSB 19 + #define USB_DIEPCTL0_TYPE_LSB 18 + #define USB_DIEPCTL0_TYPE_RESET 0x0 + #define USB_DIEPCTL0_NAK_STS_BITS 17:17 + #define USB_DIEPCTL0_NAK_STS_SET 0x00020000 + #define USB_DIEPCTL0_NAK_STS_CLR 0xfffdffff + #define USB_DIEPCTL0_NAK_STS_MSB 17 + #define USB_DIEPCTL0_NAK_STS_LSB 17 + #define USB_DIEPCTL0_NAK_STS_RESET 0x0 + #define USB_DIEPCTL0_DPID_BITS 16:16 + #define USB_DIEPCTL0_DPID_SET 0x00010000 + #define USB_DIEPCTL0_DPID_CLR 0xfffeffff + #define USB_DIEPCTL0_DPID_MSB 16 + #define USB_DIEPCTL0_DPID_LSB 16 + #define USB_DIEPCTL0_DPID_RESET 0x0 + #define USB_DIEPCTL0_EO_FR_NUM_BITS 16:16 + #define USB_DIEPCTL0_EO_FR_NUM_SET 0x00010000 + #define USB_DIEPCTL0_EO_FR_NUM_CLR 0xfffeffff + #define USB_DIEPCTL0_EO_FR_NUM_MSB 16 + #define USB_DIEPCTL0_EO_FR_NUM_LSB 16 + #define USB_DIEPCTL0_EO_FR_NUM_RESET 0x0 + #define USB_DIEPCTL0_USB_ACT_EP_BITS 15:15 + #define USB_DIEPCTL0_USB_ACT_EP_SET 0x00008000 + #define USB_DIEPCTL0_USB_ACT_EP_CLR 0xffff7fff + #define USB_DIEPCTL0_USB_ACT_EP_MSB 15 + #define USB_DIEPCTL0_USB_ACT_EP_LSB 15 + #define USB_DIEPCTL0_USB_ACT_EP_RESET 0x0 + #define USB_DIEPCTL0_NEXT_EP_BITS 14:11 + #define USB_DIEPCTL0_NEXT_EP_SET 0x00007800 + #define USB_DIEPCTL0_NEXT_EP_CLR 0xffff87ff + #define USB_DIEPCTL0_NEXT_EP_MSB 14 + #define USB_DIEPCTL0_NEXT_EP_LSB 11 + #define USB_DIEPCTL0_NEXT_EP_RESET 0x0 + #define USB_DIEPCTL0_MPS_BITS 10:0 + #define USB_DIEPCTL0_MPS_SET 0x000007ff + #define USB_DIEPCTL0_MPS_CLR 0xfffff800 + #define USB_DIEPCTL0_MPS_MSB 10 + #define USB_DIEPCTL0_MPS_LSB 0 + #define USB_DIEPCTL0_MPS_RESET 0x0 +#define USB_DIEPINT0 HW_REGISTER_RW( 0x7e980908 ) + #define USB_DIEPINT0_MASK 0xffffffff + #define USB_DIEPINT0_WIDTH 32 + #define USB_DIEPINT0_BNA_BITS 9:9 + #define USB_DIEPINT0_BNA_SET 0x00000200 + #define USB_DIEPINT0_BNA_CLR 0xfffffdff + #define USB_DIEPINT0_BNA_MSB 9 + #define USB_DIEPINT0_BNA_LSB 9 + #define USB_DIEPINT0_BNA_RESET 0x0 + #define USB_DIEPINT0_TX_FIFO_UNDRN_BITS 8:8 + #define USB_DIEPINT0_TX_FIFO_UNDRN_SET 0x00000100 + #define USB_DIEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff + #define USB_DIEPINT0_TX_FIFO_UNDRN_MSB 8 + #define USB_DIEPINT0_TX_FIFO_UNDRN_LSB 8 + #define USB_DIEPINT0_TX_FIFO_UNDRN_RESET 0x0 + #define USB_DIEPINT0_OUT_PKT_ERR_BITS 8:8 + #define USB_DIEPINT0_OUT_PKT_ERR_SET 0x00000100 + #define USB_DIEPINT0_OUT_PKT_ERR_CLR 0xfffffeff + #define USB_DIEPINT0_OUT_PKT_ERR_MSB 8 + #define USB_DIEPINT0_OUT_PKT_ERR_LSB 8 + #define USB_DIEPINT0_OUT_PKT_ERR_RESET 0x0 + #define USB_DIEPINT0_TXF_EMPTY_BITS 7:7 + #define USB_DIEPINT0_TXF_EMPTY_SET 0x00000080 + #define USB_DIEPINT0_TXF_EMPTY_CLR 0xffffff7f + #define USB_DIEPINT0_TXF_EMPTY_MSB 7 + #define USB_DIEPINT0_TXF_EMPTY_LSB 7 + #define USB_DIEPINT0_TXF_EMPTY_RESET 0x0 + #define USB_DIEPINT0_IN_EP_NAK_EFF_BITS 6:6 + #define USB_DIEPINT0_IN_EP_NAK_EFF_SET 0x00000040 + #define USB_DIEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf + #define USB_DIEPINT0_IN_EP_NAK_EFF_MSB 6 + #define USB_DIEPINT0_IN_EP_NAK_EFF_LSB 6 + #define USB_DIEPINT0_IN_EP_NAK_EFF_RESET 0x0 + #define USB_DIEPINT0_BACK2BACK_SETUP_BITS 6:6 + #define USB_DIEPINT0_BACK2BACK_SETUP_SET 0x00000040 + #define USB_DIEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf + #define USB_DIEPINT0_BACK2BACK_SETUP_MSB 6 + #define USB_DIEPINT0_BACK2BACK_SETUP_LSB 6 + #define USB_DIEPINT0_BACK2BACK_SETUP_RESET 0x0 + #define USB_DIEPINT0_IN_TKN_EP_MIS_BITS 5:5 + #define USB_DIEPINT0_IN_TKN_EP_MIS_SET 0x00000020 + #define USB_DIEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf + #define USB_DIEPINT0_IN_TKN_EP_MIS_MSB 5 + #define USB_DIEPINT0_IN_TKN_EP_MIS_LSB 5 + #define USB_DIEPINT0_IN_TKN_EP_MIS_RESET 0x0 + #define USB_DIEPINT0_STS_PHSE_RCVD_BITS 5:5 + #define USB_DIEPINT0_STS_PHSE_RCVD_SET 0x00000020 + #define USB_DIEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf + #define USB_DIEPINT0_STS_PHSE_RCVD_MSB 5 + #define USB_DIEPINT0_STS_PHSE_RCVD_LSB 5 + #define USB_DIEPINT0_STS_PHSE_RCVD_RESET 0x0 + #define USB_DIEPINT0_IN_TKN_TXFEMP_BITS 4:4 + #define USB_DIEPINT0_IN_TKN_TXFEMP_SET 0x00000010 + #define USB_DIEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef + #define USB_DIEPINT0_IN_TKN_TXFEMP_MSB 4 + #define USB_DIEPINT0_IN_TKN_TXFEMP_LSB 4 + #define USB_DIEPINT0_IN_TKN_TXFEMP_RESET 0x0 + #define USB_DIEPINT0_OUT_TKN_EP_DIS_BITS 4:4 + #define USB_DIEPINT0_OUT_TKN_EP_DIS_SET 0x00000010 + #define USB_DIEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef + #define USB_DIEPINT0_OUT_TKN_EP_DIS_MSB 4 + #define USB_DIEPINT0_OUT_TKN_EP_DIS_LSB 4 + #define USB_DIEPINT0_OUT_TKN_EP_DIS_RESET 0x0 + #define USB_DIEPINT0_TIMEOUT_BITS 3:3 + #define USB_DIEPINT0_TIMEOUT_SET 0x00000008 + #define USB_DIEPINT0_TIMEOUT_CLR 0xfffffff7 + #define USB_DIEPINT0_TIMEOUT_MSB 3 + #define USB_DIEPINT0_TIMEOUT_LSB 3 + #define USB_DIEPINT0_TIMEOUT_RESET 0x0 + #define USB_DIEPINT0_SETUP_BITS 3:3 + #define USB_DIEPINT0_SETUP_SET 0x00000008 + #define USB_DIEPINT0_SETUP_CLR 0xfffffff7 + #define USB_DIEPINT0_SETUP_MSB 3 + #define USB_DIEPINT0_SETUP_LSB 3 + #define USB_DIEPINT0_SETUP_RESET 0x0 + #define USB_DIEPINT0_AHB_ERR_BITS 2:2 + #define USB_DIEPINT0_AHB_ERR_SET 0x00000004 + #define USB_DIEPINT0_AHB_ERR_CLR 0xfffffffb + #define USB_DIEPINT0_AHB_ERR_MSB 2 + #define USB_DIEPINT0_AHB_ERR_LSB 2 + #define USB_DIEPINT0_AHB_ERR_RESET 0x0 + #define USB_DIEPINT0_EP_DISBLD_BITS 1:1 + #define USB_DIEPINT0_EP_DISBLD_SET 0x00000002 + #define USB_DIEPINT0_EP_DISBLD_CLR 0xfffffffd + #define USB_DIEPINT0_EP_DISBLD_MSB 1 + #define USB_DIEPINT0_EP_DISBLD_LSB 1 + #define USB_DIEPINT0_EP_DISBLD_RESET 0x0 + #define USB_DIEPINT0_XFER_COMPL_BITS 0:0 + #define USB_DIEPINT0_XFER_COMPL_SET 0x00000001 + #define USB_DIEPINT0_XFER_COMPL_CLR 0xfffffffe + #define USB_DIEPINT0_XFER_COMPL_MSB 0 + #define USB_DIEPINT0_XFER_COMPL_LSB 0 + #define USB_DIEPINT0_XFER_COMPL_RESET 0x0 +#define USB_DIEPTSIZ0 HW_REGISTER_RW( 0x7e980910 ) + #define USB_DIEPTSIZ0_MASK 0xffffffff + #define USB_DIEPTSIZ0_WIDTH 32 + #define USB_DIEPTSIZ0_SUP_CNT_BITS 30:29 + #define USB_DIEPTSIZ0_SUP_CNT_SET 0x60000000 + #define USB_DIEPTSIZ0_SUP_CNT_CLR 0x9fffffff + #define USB_DIEPTSIZ0_SUP_CNT_MSB 30 + #define USB_DIEPTSIZ0_SUP_CNT_LSB 29 + #define USB_DIEPTSIZ0_SUP_CNT_RESET 0x0 + #define USB_DIEPTSIZ0_RX_DPID_BITS 30:29 + #define USB_DIEPTSIZ0_RX_DPID_SET 0x60000000 + #define USB_DIEPTSIZ0_RX_DPID_CLR 0x9fffffff + #define USB_DIEPTSIZ0_RX_DPID_MSB 30 + #define USB_DIEPTSIZ0_RX_DPID_LSB 29 + #define USB_DIEPTSIZ0_RX_DPID_RESET 0x0 + #define USB_DIEPTSIZ0_MC_BITS 30:29 + #define USB_DIEPTSIZ0_MC_SET 0x60000000 + #define USB_DIEPTSIZ0_MC_CLR 0x9fffffff + #define USB_DIEPTSIZ0_MC_MSB 30 + #define USB_DIEPTSIZ0_MC_LSB 29 + #define USB_DIEPTSIZ0_MC_RESET 0x0 + #define USB_DIEPTSIZ0_PKT_CNT_BITS 28:19 + #define USB_DIEPTSIZ0_PKT_CNT_SET 0x1ff80000 + #define USB_DIEPTSIZ0_PKT_CNT_CLR 0xe007ffff + #define USB_DIEPTSIZ0_PKT_CNT_MSB 28 + #define USB_DIEPTSIZ0_PKT_CNT_LSB 19 + #define USB_DIEPTSIZ0_PKT_CNT_RESET 0x0 + #define USB_DIEPTSIZ0_XFERSIZE_BITS 18:0 + #define USB_DIEPTSIZ0_XFERSIZE_SET 0x0007ffff + #define USB_DIEPTSIZ0_XFERSIZE_CLR 0xfff80000 + #define USB_DIEPTSIZ0_XFERSIZE_MSB 18 + #define USB_DIEPTSIZ0_XFERSIZE_LSB 0 + #define USB_DIEPTSIZ0_XFERSIZE_RESET 0x0 +#define USB_DIEPDMA0 HW_REGISTER_RW( 0x7e980914 ) + #define USB_DIEPDMA0_MASK 0xffffffff + #define USB_DIEPDMA0_WIDTH 32 +#define USB_DTXFSTS0 HW_REGISTER_RW( 0x7e980918 ) + #define USB_DTXFSTS0_MASK 0xffffffff + #define USB_DTXFSTS0_WIDTH 32 + #define USB_DTXFSTS0_SPC_AVAIL_BITS 31:16 + #define USB_DTXFSTS0_SPC_AVAIL_SET 0xffff0000 + #define USB_DTXFSTS0_SPC_AVAIL_CLR 0x0000ffff + #define USB_DTXFSTS0_SPC_AVAIL_MSB 31 + #define USB_DTXFSTS0_SPC_AVAIL_LSB 16 + #define USB_DTXFSTS0_SPC_AVAIL_RESET 0x0 +#define USB_DIEPDMAB0 HW_REGISTER_RW( 0x7e980918 ) + #define USB_DIEPDMAB0_MASK 0xffffffff + #define USB_DIEPDMAB0_WIDTH 32 +#define USB_DIEPCTL1 HW_REGISTER_RW( 0x7e980920 ) + #define USB_DIEPCTL1_MASK 0xffffffff + #define USB_DIEPCTL1_WIDTH 32 +#define USB_DIEPINT1 HW_REGISTER_RW( 0x7e980928 ) + #define USB_DIEPINT1_MASK 0xffffffff + #define USB_DIEPINT1_WIDTH 32 +#define USB_DIEPTSIZ1 HW_REGISTER_RW( 0x7e980930 ) + #define USB_DIEPTSIZ1_MASK 0xffffffff + #define USB_DIEPTSIZ1_WIDTH 32 +#define USB_DIEPDMA1 HW_REGISTER_RW( 0x7e980934 ) + #define USB_DIEPDMA1_MASK 0xffffffff + #define USB_DIEPDMA1_WIDTH 32 +#define USB_DTXFSTS1 HW_REGISTER_RW( 0x7e980938 ) + #define USB_DTXFSTS1_MASK 0xffffffff + #define USB_DTXFSTS1_WIDTH 32 +#define USB_DIEPDMAB1 HW_REGISTER_RW( 0x7e980938 ) + #define USB_DIEPDMAB1_MASK 0xffffffff + #define USB_DIEPDMAB1_WIDTH 32 +#define USB_DIEPCTL2 HW_REGISTER_RW( 0x7e980940 ) + #define USB_DIEPCTL2_MASK 0xffffffff + #define USB_DIEPCTL2_WIDTH 32 +#define USB_DIEPINT2 HW_REGISTER_RW( 0x7e980948 ) + #define USB_DIEPINT2_MASK 0xffffffff + #define USB_DIEPINT2_WIDTH 32 +#define USB_DIEPTSIZ2 HW_REGISTER_RW( 0x7e980950 ) + #define USB_DIEPTSIZ2_MASK 0xffffffff + #define USB_DIEPTSIZ2_WIDTH 32 +#define USB_DIEPDMA2 HW_REGISTER_RW( 0x7e980954 ) + #define USB_DIEPDMA2_MASK 0xffffffff + #define USB_DIEPDMA2_WIDTH 32 +#define USB_DTXFSTS2 HW_REGISTER_RW( 0x7e980958 ) + #define USB_DTXFSTS2_MASK 0xffffffff + #define USB_DTXFSTS2_WIDTH 32 +#define USB_DIEPDMAB2 HW_REGISTER_RW( 0x7e980958 ) + #define USB_DIEPDMAB2_MASK 0xffffffff + #define USB_DIEPDMAB2_WIDTH 32 +#define USB_DIEPCTL3 HW_REGISTER_RW( 0x7e980960 ) + #define USB_DIEPCTL3_MASK 0xffffffff + #define USB_DIEPCTL3_WIDTH 32 +#define USB_DIEPINT3 HW_REGISTER_RW( 0x7e980968 ) + #define USB_DIEPINT3_MASK 0xffffffff + #define USB_DIEPINT3_WIDTH 32 +#define USB_DIEPTSIZ3 HW_REGISTER_RW( 0x7e980970 ) + #define USB_DIEPTSIZ3_MASK 0xffffffff + #define USB_DIEPTSIZ3_WIDTH 32 +#define USB_DIEPDMA3 HW_REGISTER_RW( 0x7e980974 ) + #define USB_DIEPDMA3_MASK 0xffffffff + #define USB_DIEPDMA3_WIDTH 32 +#define USB_DTXFSTS3 HW_REGISTER_RW( 0x7e980978 ) + #define USB_DTXFSTS3_MASK 0xffffffff + #define USB_DTXFSTS3_WIDTH 32 +#define USB_DIEPDMAB3 HW_REGISTER_RW( 0x7e980978 ) + #define USB_DIEPDMAB3_MASK 0xffffffff + #define USB_DIEPDMAB3_WIDTH 32 +#define USB_DIEPCTL4 HW_REGISTER_RW( 0x7e980980 ) + #define USB_DIEPCTL4_MASK 0xffffffff + #define USB_DIEPCTL4_WIDTH 32 +#define USB_DIEPINT4 HW_REGISTER_RW( 0x7e980988 ) + #define USB_DIEPINT4_MASK 0xffffffff + #define USB_DIEPINT4_WIDTH 32 +#define USB_DIEPTSIZ4 HW_REGISTER_RW( 0x7e980990 ) + #define USB_DIEPTSIZ4_MASK 0xffffffff + #define USB_DIEPTSIZ4_WIDTH 32 +#define USB_DIEPDMA4 HW_REGISTER_RW( 0x7e980994 ) + #define USB_DIEPDMA4_MASK 0xffffffff + #define USB_DIEPDMA4_WIDTH 32 +#define USB_DTXFSTS4 HW_REGISTER_RW( 0x7e980998 ) + #define USB_DTXFSTS4_MASK 0xffffffff + #define USB_DTXFSTS4_WIDTH 32 +#define USB_DIEPDMAB4 HW_REGISTER_RW( 0x7e980998 ) + #define USB_DIEPDMAB4_MASK 0xffffffff + #define USB_DIEPDMAB4_WIDTH 32 +#define USB_DIEPCTL5 HW_REGISTER_RW( 0x7e9809a0 ) + #define USB_DIEPCTL5_MASK 0xffffffff + #define USB_DIEPCTL5_WIDTH 32 +#define USB_DIEPINT5 HW_REGISTER_RW( 0x7e9809a8 ) + #define USB_DIEPINT5_MASK 0xffffffff + #define USB_DIEPINT5_WIDTH 32 +#define USB_DIEPTSIZ5 HW_REGISTER_RW( 0x7e9809b0 ) + #define USB_DIEPTSIZ5_MASK 0xffffffff + #define USB_DIEPTSIZ5_WIDTH 32 +#define USB_DIEPDMA5 HW_REGISTER_RW( 0x7e9809b4 ) + #define USB_DIEPDMA5_MASK 0xffffffff + #define USB_DIEPDMA5_WIDTH 32 +#define USB_DTXFSTS5 HW_REGISTER_RW( 0x7e9809b8 ) + #define USB_DTXFSTS5_MASK 0xffffffff + #define USB_DTXFSTS5_WIDTH 32 +#define USB_DIEPDMAB5 HW_REGISTER_RW( 0x7e9809b8 ) + #define USB_DIEPDMAB5_MASK 0xffffffff + #define USB_DIEPDMAB5_WIDTH 32 +#define USB_DIEPCTL6 HW_REGISTER_RW( 0x7e9809c0 ) + #define USB_DIEPCTL6_MASK 0xffffffff + #define USB_DIEPCTL6_WIDTH 32 +#define USB_DIEPINT6 HW_REGISTER_RW( 0x7e9809c8 ) + #define USB_DIEPINT6_MASK 0xffffffff + #define USB_DIEPINT6_WIDTH 32 +#define USB_DIEPTSIZ6 HW_REGISTER_RW( 0x7e9809d0 ) + #define USB_DIEPTSIZ6_MASK 0xffffffff + #define USB_DIEPTSIZ6_WIDTH 32 +#define USB_DIEPDMA6 HW_REGISTER_RW( 0x7e9809d4 ) + #define USB_DIEPDMA6_MASK 0xffffffff + #define USB_DIEPDMA6_WIDTH 32 +#define USB_DTXFSTS6 HW_REGISTER_RW( 0x7e9809d8 ) + #define USB_DTXFSTS6_MASK 0xffffffff + #define USB_DTXFSTS6_WIDTH 32 +#define USB_DIEPDMAB6 HW_REGISTER_RW( 0x7e9809d8 ) + #define USB_DIEPDMAB6_MASK 0xffffffff + #define USB_DIEPDMAB6_WIDTH 32 +#define USB_DIEPCTL7 HW_REGISTER_RW( 0x7e9809e0 ) + #define USB_DIEPCTL7_MASK 0xffffffff + #define USB_DIEPCTL7_WIDTH 32 +#define USB_DIEPINT7 HW_REGISTER_RW( 0x7e9809e8 ) + #define USB_DIEPINT7_MASK 0xffffffff + #define USB_DIEPINT7_WIDTH 32 +#define USB_DIEPTSIZ7 HW_REGISTER_RW( 0x7e9809f0 ) + #define USB_DIEPTSIZ7_MASK 0xffffffff + #define USB_DIEPTSIZ7_WIDTH 32 +#define USB_DIEPDMA7 HW_REGISTER_RW( 0x7e9809f4 ) + #define USB_DIEPDMA7_MASK 0xffffffff + #define USB_DIEPDMA7_WIDTH 32 +#define USB_DTXFSTS7 HW_REGISTER_RW( 0x7e9809f8 ) + #define USB_DTXFSTS7_MASK 0xffffffff + #define USB_DTXFSTS7_WIDTH 32 +#define USB_DIEPDMAB7 HW_REGISTER_RW( 0x7e9809f8 ) + #define USB_DIEPDMAB7_MASK 0xffffffff + #define USB_DIEPDMAB7_WIDTH 32 +#define USB_DIEPCTL8 HW_REGISTER_RW( 0x7e980a00 ) + #define USB_DIEPCTL8_MASK 0xffffffff + #define USB_DIEPCTL8_WIDTH 32 +#define USB_DIEPINT8 HW_REGISTER_RW( 0x7e980a08 ) + #define USB_DIEPINT8_MASK 0xffffffff + #define USB_DIEPINT8_WIDTH 32 +#define USB_DIEPTSIZ8 HW_REGISTER_RW( 0x7e980a10 ) + #define USB_DIEPTSIZ8_MASK 0xffffffff + #define USB_DIEPTSIZ8_WIDTH 32 +#define USB_DIEPDMA8 HW_REGISTER_RW( 0x7e980a14 ) + #define USB_DIEPDMA8_MASK 0xffffffff + #define USB_DIEPDMA8_WIDTH 32 +#define USB_DTXFSTS8 HW_REGISTER_RW( 0x7e980a18 ) + #define USB_DTXFSTS8_MASK 0xffffffff + #define USB_DTXFSTS8_WIDTH 32 +#define USB_DIEPDMAB8 HW_REGISTER_RW( 0x7e980a18 ) + #define USB_DIEPDMAB8_MASK 0xffffffff + #define USB_DIEPDMAB8_WIDTH 32 +#define USB_DIEPCTL9 HW_REGISTER_RW( 0x7e980a20 ) + #define USB_DIEPCTL9_MASK 0xffffffff + #define USB_DIEPCTL9_WIDTH 32 +#define USB_DIEPINT9 HW_REGISTER_RW( 0x7e980a28 ) + #define USB_DIEPINT9_MASK 0xffffffff + #define USB_DIEPINT9_WIDTH 32 +#define USB_DIEPTSIZ9 HW_REGISTER_RW( 0x7e980a30 ) + #define USB_DIEPTSIZ9_MASK 0xffffffff + #define USB_DIEPTSIZ9_WIDTH 32 +#define USB_DIEPDMA9 HW_REGISTER_RW( 0x7e980a34 ) + #define USB_DIEPDMA9_MASK 0xffffffff + #define USB_DIEPDMA9_WIDTH 32 +#define USB_DTXFSTS9 HW_REGISTER_RW( 0x7e980a38 ) + #define USB_DTXFSTS9_MASK 0xffffffff + #define USB_DTXFSTS9_WIDTH 32 +#define USB_DIEPDMAB9 HW_REGISTER_RW( 0x7e980a38 ) + #define USB_DIEPDMAB9_MASK 0xffffffff + #define USB_DIEPDMAB9_WIDTH 32 +#define USB_DIEPCTL10 HW_REGISTER_RW( 0x7e980a40 ) + #define USB_DIEPCTL10_MASK 0xffffffff + #define USB_DIEPCTL10_WIDTH 32 +#define USB_DIEPINT10 HW_REGISTER_RW( 0x7e980a48 ) + #define USB_DIEPINT10_MASK 0xffffffff + #define USB_DIEPINT10_WIDTH 32 +#define USB_DIEPTSIZ10 HW_REGISTER_RW( 0x7e980a50 ) + #define USB_DIEPTSIZ10_MASK 0xffffffff + #define USB_DIEPTSIZ10_WIDTH 32 +#define USB_DIEPDMA10 HW_REGISTER_RW( 0x7e980a54 ) + #define USB_DIEPDMA10_MASK 0xffffffff + #define USB_DIEPDMA10_WIDTH 32 +#define USB_DTXFSTS10 HW_REGISTER_RW( 0x7e980a58 ) + #define USB_DTXFSTS10_MASK 0xffffffff + #define USB_DTXFSTS10_WIDTH 32 +#define USB_DIEPDMAB10 HW_REGISTER_RW( 0x7e980a58 ) + #define USB_DIEPDMAB10_MASK 0xffffffff + #define USB_DIEPDMAB10_WIDTH 32 +#define USB_DIEPCTL11 HW_REGISTER_RW( 0x7e980a60 ) + #define USB_DIEPCTL11_MASK 0xffffffff + #define USB_DIEPCTL11_WIDTH 32 +#define USB_DIEPINT11 HW_REGISTER_RW( 0x7e980a68 ) + #define USB_DIEPINT11_MASK 0xffffffff + #define USB_DIEPINT11_WIDTH 32 +#define USB_DIEPTSIZ11 HW_REGISTER_RW( 0x7e980a70 ) + #define USB_DIEPTSIZ11_MASK 0xffffffff + #define USB_DIEPTSIZ11_WIDTH 32 +#define USB_DIEPDMA11 HW_REGISTER_RW( 0x7e980a74 ) + #define USB_DIEPDMA11_MASK 0xffffffff + #define USB_DIEPDMA11_WIDTH 32 +#define USB_DTXFSTS11 HW_REGISTER_RW( 0x7e980a78 ) + #define USB_DTXFSTS11_MASK 0xffffffff + #define USB_DTXFSTS11_WIDTH 32 +#define USB_DIEPDMAB11 HW_REGISTER_RW( 0x7e980a78 ) + #define USB_DIEPDMAB11_MASK 0xffffffff + #define USB_DIEPDMAB11_WIDTH 32 +#define USB_DIEPCTL12 HW_REGISTER_RW( 0x7e980a80 ) + #define USB_DIEPCTL12_MASK 0xffffffff + #define USB_DIEPCTL12_WIDTH 32 +#define USB_DIEPINT12 HW_REGISTER_RW( 0x7e980a88 ) + #define USB_DIEPINT12_MASK 0xffffffff + #define USB_DIEPINT12_WIDTH 32 +#define USB_DIEPTSIZ12 HW_REGISTER_RW( 0x7e980a90 ) + #define USB_DIEPTSIZ12_MASK 0xffffffff + #define USB_DIEPTSIZ12_WIDTH 32 +#define USB_DIEPDMA12 HW_REGISTER_RW( 0x7e980a94 ) + #define USB_DIEPDMA12_MASK 0xffffffff + #define USB_DIEPDMA12_WIDTH 32 +#define USB_DTXFSTS12 HW_REGISTER_RW( 0x7e980a98 ) + #define USB_DTXFSTS12_MASK 0xffffffff + #define USB_DTXFSTS12_WIDTH 32 +#define USB_DIEPDMAB12 HW_REGISTER_RW( 0x7e980a98 ) + #define USB_DIEPDMAB12_MASK 0xffffffff + #define USB_DIEPDMAB12_WIDTH 32 +#define USB_DIEPCTL13 HW_REGISTER_RW( 0x7e980aa0 ) + #define USB_DIEPCTL13_MASK 0xffffffff + #define USB_DIEPCTL13_WIDTH 32 +#define USB_DIEPINT13 HW_REGISTER_RW( 0x7e980aa8 ) + #define USB_DIEPINT13_MASK 0xffffffff + #define USB_DIEPINT13_WIDTH 32 +#define USB_DIEPTSIZ13 HW_REGISTER_RW( 0x7e980ab0 ) + #define USB_DIEPTSIZ13_MASK 0xffffffff + #define USB_DIEPTSIZ13_WIDTH 32 +#define USB_DIEPDMA13 HW_REGISTER_RW( 0x7e980ab4 ) + #define USB_DIEPDMA13_MASK 0xffffffff + #define USB_DIEPDMA13_WIDTH 32 +#define USB_DTXFSTS13 HW_REGISTER_RW( 0x7e980ab8 ) + #define USB_DTXFSTS13_MASK 0xffffffff + #define USB_DTXFSTS13_WIDTH 32 +#define USB_DIEPDMAB13 HW_REGISTER_RW( 0x7e980ab8 ) + #define USB_DIEPDMAB13_MASK 0xffffffff + #define USB_DIEPDMAB13_WIDTH 32 +#define USB_DIEPCTL14 HW_REGISTER_RW( 0x7e980ac0 ) + #define USB_DIEPCTL14_MASK 0xffffffff + #define USB_DIEPCTL14_WIDTH 32 +#define USB_DIEPINT14 HW_REGISTER_RW( 0x7e980ac8 ) + #define USB_DIEPINT14_MASK 0xffffffff + #define USB_DIEPINT14_WIDTH 32 +#define USB_DIEPTSIZ14 HW_REGISTER_RW( 0x7e980ad0 ) + #define USB_DIEPTSIZ14_MASK 0xffffffff + #define USB_DIEPTSIZ14_WIDTH 32 +#define USB_DIEPDMA14 HW_REGISTER_RW( 0x7e980ad4 ) + #define USB_DIEPDMA14_MASK 0xffffffff + #define USB_DIEPDMA14_WIDTH 32 +#define USB_DTXFSTS14 HW_REGISTER_RW( 0x7e980ad8 ) + #define USB_DTXFSTS14_MASK 0xffffffff + #define USB_DTXFSTS14_WIDTH 32 +#define USB_DIEPDMAB14 HW_REGISTER_RW( 0x7e980ad8 ) + #define USB_DIEPDMAB14_MASK 0xffffffff + #define USB_DIEPDMAB14_WIDTH 32 +#define USB_DIEPCTL15 HW_REGISTER_RW( 0x7e980ae0 ) + #define USB_DIEPCTL15_MASK 0xffffffff + #define USB_DIEPCTL15_WIDTH 32 +#define USB_DIEPINT15 HW_REGISTER_RW( 0x7e980ae8 ) + #define USB_DIEPINT15_MASK 0xffffffff + #define USB_DIEPINT15_WIDTH 32 +#define USB_DIEPTSIZ15 HW_REGISTER_RW( 0x7e980af0 ) + #define USB_DIEPTSIZ15_MASK 0xffffffff + #define USB_DIEPTSIZ15_WIDTH 32 +#define USB_DIEPDMA15 HW_REGISTER_RW( 0x7e980af4 ) + #define USB_DIEPDMA15_MASK 0xffffffff + #define USB_DIEPDMA15_WIDTH 32 +#define USB_DTXFSTS15 HW_REGISTER_RW( 0x7e980af8 ) + #define USB_DTXFSTS15_MASK 0xffffffff + #define USB_DTXFSTS15_WIDTH 32 +#define USB_DIEPDMAB15 HW_REGISTER_RW( 0x7e980af8 ) + #define USB_DIEPDMAB15_MASK 0xffffffff + #define USB_DIEPDMAB15_WIDTH 32 +#define USB_DOEPCTL0 HW_REGISTER_RW( 0x7e980b00 ) + #define USB_DOEPCTL0_MASK 0xffffffff + #define USB_DOEPCTL0_WIDTH 32 + #define USB_DOEPCTL0_ENA_BITS 31:31 + #define USB_DOEPCTL0_ENA_SET 0x80000000 + #define USB_DOEPCTL0_ENA_CLR 0x7fffffff + #define USB_DOEPCTL0_ENA_MSB 31 + #define USB_DOEPCTL0_ENA_LSB 31 + #define USB_DOEPCTL0_ENA_RESET 0x0 + #define USB_DOEPCTL0_DIS_BITS 30:30 + #define USB_DOEPCTL0_DIS_SET 0x40000000 + #define USB_DOEPCTL0_DIS_CLR 0xbfffffff + #define USB_DOEPCTL0_DIS_MSB 30 + #define USB_DOEPCTL0_DIS_LSB 30 + #define USB_DOEPCTL0_DIS_RESET 0x0 + #define USB_DOEPCTL0_SET_D1_PID_BITS 29:29 + #define USB_DOEPCTL0_SET_D1_PID_SET 0x20000000 + #define USB_DOEPCTL0_SET_D1_PID_CLR 0xdfffffff + #define USB_DOEPCTL0_SET_D1_PID_MSB 29 + #define USB_DOEPCTL0_SET_D1_PID_LSB 29 + #define USB_DOEPCTL0_SET_D1_PID_RESET 0x0 + #define USB_DOEPCTL0_SET_ODD_FR_BITS 29:29 + #define USB_DOEPCTL0_SET_ODD_FR_SET 0x20000000 + #define USB_DOEPCTL0_SET_ODD_FR_CLR 0xdfffffff + #define USB_DOEPCTL0_SET_ODD_FR_MSB 29 + #define USB_DOEPCTL0_SET_ODD_FR_LSB 29 + #define USB_DOEPCTL0_SET_ODD_FR_RESET 0x0 + #define USB_DOEPCTL0_SET_D0_PID_BITS 28:28 + #define USB_DOEPCTL0_SET_D0_PID_SET 0x10000000 + #define USB_DOEPCTL0_SET_D0_PID_CLR 0xefffffff + #define USB_DOEPCTL0_SET_D0_PID_MSB 28 + #define USB_DOEPCTL0_SET_D0_PID_LSB 28 + #define USB_DOEPCTL0_SET_D0_PID_RESET 0x0 + #define USB_DOEPCTL0_SET_EVEN_FR_BITS 28:28 + #define USB_DOEPCTL0_SET_EVEN_FR_SET 0x10000000 + #define USB_DOEPCTL0_SET_EVEN_FR_CLR 0xefffffff + #define USB_DOEPCTL0_SET_EVEN_FR_MSB 28 + #define USB_DOEPCTL0_SET_EVEN_FR_LSB 28 + #define USB_DOEPCTL0_SET_EVEN_FR_RESET 0x0 + #define USB_DOEPCTL0_SNAK_BITS 27:27 + #define USB_DOEPCTL0_SNAK_SET 0x08000000 + #define USB_DOEPCTL0_SNAK_CLR 0xf7ffffff + #define USB_DOEPCTL0_SNAK_MSB 27 + #define USB_DOEPCTL0_SNAK_LSB 27 + #define USB_DOEPCTL0_SNAK_RESET 0x0 + #define USB_DOEPCTL0_CNAK_BITS 26:26 + #define USB_DOEPCTL0_CNAK_SET 0x04000000 + #define USB_DOEPCTL0_CNAK_CLR 0xfbffffff + #define USB_DOEPCTL0_CNAK_MSB 26 + #define USB_DOEPCTL0_CNAK_LSB 26 + #define USB_DOEPCTL0_CNAK_RESET 0x0 + #define USB_DOEPCTL0_TXF_NUM_BITS 25:22 + #define USB_DOEPCTL0_TXF_NUM_SET 0x03c00000 + #define USB_DOEPCTL0_TXF_NUM_CLR 0xfc3fffff + #define USB_DOEPCTL0_TXF_NUM_MSB 25 + #define USB_DOEPCTL0_TXF_NUM_LSB 22 + #define USB_DOEPCTL0_TXF_NUM_RESET 0x0 + #define USB_DOEPCTL0_STALL_BITS 21:21 + #define USB_DOEPCTL0_STALL_SET 0x00200000 + #define USB_DOEPCTL0_STALL_CLR 0xffdfffff + #define USB_DOEPCTL0_STALL_MSB 21 + #define USB_DOEPCTL0_STALL_LSB 21 + #define USB_DOEPCTL0_STALL_RESET 0x0 + #define USB_DOEPCTL0_SNP_BITS 20:20 + #define USB_DOEPCTL0_SNP_SET 0x00100000 + #define USB_DOEPCTL0_SNP_CLR 0xffefffff + #define USB_DOEPCTL0_SNP_MSB 20 + #define USB_DOEPCTL0_SNP_LSB 20 + #define USB_DOEPCTL0_SNP_RESET 0x0 + #define USB_DOEPCTL0_TYPE_BITS 19:18 + #define USB_DOEPCTL0_TYPE_SET 0x000c0000 + #define USB_DOEPCTL0_TYPE_CLR 0xfff3ffff + #define USB_DOEPCTL0_TYPE_MSB 19 + #define USB_DOEPCTL0_TYPE_LSB 18 + #define USB_DOEPCTL0_TYPE_RESET 0x0 + #define USB_DOEPCTL0_NAK_STS_BITS 17:17 + #define USB_DOEPCTL0_NAK_STS_SET 0x00020000 + #define USB_DOEPCTL0_NAK_STS_CLR 0xfffdffff + #define USB_DOEPCTL0_NAK_STS_MSB 17 + #define USB_DOEPCTL0_NAK_STS_LSB 17 + #define USB_DOEPCTL0_NAK_STS_RESET 0x0 + #define USB_DOEPCTL0_DPID_BITS 16:16 + #define USB_DOEPCTL0_DPID_SET 0x00010000 + #define USB_DOEPCTL0_DPID_CLR 0xfffeffff + #define USB_DOEPCTL0_DPID_MSB 16 + #define USB_DOEPCTL0_DPID_LSB 16 + #define USB_DOEPCTL0_DPID_RESET 0x0 + #define USB_DOEPCTL0_EO_FR_NUM_BITS 16:16 + #define USB_DOEPCTL0_EO_FR_NUM_SET 0x00010000 + #define USB_DOEPCTL0_EO_FR_NUM_CLR 0xfffeffff + #define USB_DOEPCTL0_EO_FR_NUM_MSB 16 + #define USB_DOEPCTL0_EO_FR_NUM_LSB 16 + #define USB_DOEPCTL0_EO_FR_NUM_RESET 0x0 + #define USB_DOEPCTL0_USB_ACT_EP_BITS 15:15 + #define USB_DOEPCTL0_USB_ACT_EP_SET 0x00008000 + #define USB_DOEPCTL0_USB_ACT_EP_CLR 0xffff7fff + #define USB_DOEPCTL0_USB_ACT_EP_MSB 15 + #define USB_DOEPCTL0_USB_ACT_EP_LSB 15 + #define USB_DOEPCTL0_USB_ACT_EP_RESET 0x0 + #define USB_DOEPCTL0_NEXT_EP_BITS 14:11 + #define USB_DOEPCTL0_NEXT_EP_SET 0x00007800 + #define USB_DOEPCTL0_NEXT_EP_CLR 0xffff87ff + #define USB_DOEPCTL0_NEXT_EP_MSB 14 + #define USB_DOEPCTL0_NEXT_EP_LSB 11 + #define USB_DOEPCTL0_NEXT_EP_RESET 0x0 + #define USB_DOEPCTL0_MPS_BITS 10:0 + #define USB_DOEPCTL0_MPS_SET 0x000007ff + #define USB_DOEPCTL0_MPS_CLR 0xfffff800 + #define USB_DOEPCTL0_MPS_MSB 10 + #define USB_DOEPCTL0_MPS_LSB 0 + #define USB_DOEPCTL0_MPS_RESET 0x0 +#define USB_DOEPINT0 HW_REGISTER_RW( 0x7e980b08 ) + #define USB_DOEPINT0_MASK 0xffffffff + #define USB_DOEPINT0_WIDTH 32 + #define USB_DOEPINT0_BNA_BITS 9:9 + #define USB_DOEPINT0_BNA_SET 0x00000200 + #define USB_DOEPINT0_BNA_CLR 0xfffffdff + #define USB_DOEPINT0_BNA_MSB 9 + #define USB_DOEPINT0_BNA_LSB 9 + #define USB_DOEPINT0_BNA_RESET 0x0 + #define USB_DOEPINT0_TX_FIFO_UNDRN_BITS 8:8 + #define USB_DOEPINT0_TX_FIFO_UNDRN_SET 0x00000100 + #define USB_DOEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff + #define USB_DOEPINT0_TX_FIFO_UNDRN_MSB 8 + #define USB_DOEPINT0_TX_FIFO_UNDRN_LSB 8 + #define USB_DOEPINT0_TX_FIFO_UNDRN_RESET 0x0 + #define USB_DOEPINT0_OUT_PKT_ERR_BITS 8:8 + #define USB_DOEPINT0_OUT_PKT_ERR_SET 0x00000100 + #define USB_DOEPINT0_OUT_PKT_ERR_CLR 0xfffffeff + #define USB_DOEPINT0_OUT_PKT_ERR_MSB 8 + #define USB_DOEPINT0_OUT_PKT_ERR_LSB 8 + #define USB_DOEPINT0_OUT_PKT_ERR_RESET 0x0 + #define USB_DOEPINT0_TXF_EMPTY_BITS 7:7 + #define USB_DOEPINT0_TXF_EMPTY_SET 0x00000080 + #define USB_DOEPINT0_TXF_EMPTY_CLR 0xffffff7f + #define USB_DOEPINT0_TXF_EMPTY_MSB 7 + #define USB_DOEPINT0_TXF_EMPTY_LSB 7 + #define USB_DOEPINT0_TXF_EMPTY_RESET 0x0 + #define USB_DOEPINT0_IN_EP_NAK_EFF_BITS 6:6 + #define USB_DOEPINT0_IN_EP_NAK_EFF_SET 0x00000040 + #define USB_DOEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf + #define USB_DOEPINT0_IN_EP_NAK_EFF_MSB 6 + #define USB_DOEPINT0_IN_EP_NAK_EFF_LSB 6 + #define USB_DOEPINT0_IN_EP_NAK_EFF_RESET 0x0 + #define USB_DOEPINT0_BACK2BACK_SETUP_BITS 6:6 + #define USB_DOEPINT0_BACK2BACK_SETUP_SET 0x00000040 + #define USB_DOEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf + #define USB_DOEPINT0_BACK2BACK_SETUP_MSB 6 + #define USB_DOEPINT0_BACK2BACK_SETUP_LSB 6 + #define USB_DOEPINT0_BACK2BACK_SETUP_RESET 0x0 + #define USB_DOEPINT0_IN_TKN_EP_MIS_BITS 5:5 + #define USB_DOEPINT0_IN_TKN_EP_MIS_SET 0x00000020 + #define USB_DOEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf + #define USB_DOEPINT0_IN_TKN_EP_MIS_MSB 5 + #define USB_DOEPINT0_IN_TKN_EP_MIS_LSB 5 + #define USB_DOEPINT0_IN_TKN_EP_MIS_RESET 0x0 + #define USB_DOEPINT0_STS_PHSE_RCVD_BITS 5:5 + #define USB_DOEPINT0_STS_PHSE_RCVD_SET 0x00000020 + #define USB_DOEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf + #define USB_DOEPINT0_STS_PHSE_RCVD_MSB 5 + #define USB_DOEPINT0_STS_PHSE_RCVD_LSB 5 + #define USB_DOEPINT0_STS_PHSE_RCVD_RESET 0x0 + #define USB_DOEPINT0_IN_TKN_TXFEMP_BITS 4:4 + #define USB_DOEPINT0_IN_TKN_TXFEMP_SET 0x00000010 + #define USB_DOEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef + #define USB_DOEPINT0_IN_TKN_TXFEMP_MSB 4 + #define USB_DOEPINT0_IN_TKN_TXFEMP_LSB 4 + #define USB_DOEPINT0_IN_TKN_TXFEMP_RESET 0x0 + #define USB_DOEPINT0_OUT_TKN_EP_DIS_BITS 4:4 + #define USB_DOEPINT0_OUT_TKN_EP_DIS_SET 0x00000010 + #define USB_DOEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef + #define USB_DOEPINT0_OUT_TKN_EP_DIS_MSB 4 + #define USB_DOEPINT0_OUT_TKN_EP_DIS_LSB 4 + #define USB_DOEPINT0_OUT_TKN_EP_DIS_RESET 0x0 + #define USB_DOEPINT0_TIMEOUT_BITS 3:3 + #define USB_DOEPINT0_TIMEOUT_SET 0x00000008 + #define USB_DOEPINT0_TIMEOUT_CLR 0xfffffff7 + #define USB_DOEPINT0_TIMEOUT_MSB 3 + #define USB_DOEPINT0_TIMEOUT_LSB 3 + #define USB_DOEPINT0_TIMEOUT_RESET 0x0 + #define USB_DOEPINT0_SETUP_BITS 3:3 + #define USB_DOEPINT0_SETUP_SET 0x00000008 + #define USB_DOEPINT0_SETUP_CLR 0xfffffff7 + #define USB_DOEPINT0_SETUP_MSB 3 + #define USB_DOEPINT0_SETUP_LSB 3 + #define USB_DOEPINT0_SETUP_RESET 0x0 + #define USB_DOEPINT0_AHB_ERR_BITS 2:2 + #define USB_DOEPINT0_AHB_ERR_SET 0x00000004 + #define USB_DOEPINT0_AHB_ERR_CLR 0xfffffffb + #define USB_DOEPINT0_AHB_ERR_MSB 2 + #define USB_DOEPINT0_AHB_ERR_LSB 2 + #define USB_DOEPINT0_AHB_ERR_RESET 0x0 + #define USB_DOEPINT0_EP_DISBLD_BITS 1:1 + #define USB_DOEPINT0_EP_DISBLD_SET 0x00000002 + #define USB_DOEPINT0_EP_DISBLD_CLR 0xfffffffd + #define USB_DOEPINT0_EP_DISBLD_MSB 1 + #define USB_DOEPINT0_EP_DISBLD_LSB 1 + #define USB_DOEPINT0_EP_DISBLD_RESET 0x0 + #define USB_DOEPINT0_XFER_COMPL_BITS 0:0 + #define USB_DOEPINT0_XFER_COMPL_SET 0x00000001 + #define USB_DOEPINT0_XFER_COMPL_CLR 0xfffffffe + #define USB_DOEPINT0_XFER_COMPL_MSB 0 + #define USB_DOEPINT0_XFER_COMPL_LSB 0 + #define USB_DOEPINT0_XFER_COMPL_RESET 0x0 +#define USB_DOEPTSIZ0 HW_REGISTER_RW( 0x7e980b10 ) + #define USB_DOEPTSIZ0_MASK 0xffffffff + #define USB_DOEPTSIZ0_WIDTH 32 + #define USB_DOEPTSIZ0_SUP_CNT_BITS 30:29 + #define USB_DOEPTSIZ0_SUP_CNT_SET 0x60000000 + #define USB_DOEPTSIZ0_SUP_CNT_CLR 0x9fffffff + #define USB_DOEPTSIZ0_SUP_CNT_MSB 30 + #define USB_DOEPTSIZ0_SUP_CNT_LSB 29 + #define USB_DOEPTSIZ0_SUP_CNT_RESET 0x0 + #define USB_DOEPTSIZ0_RX_DPID_BITS 30:29 + #define USB_DOEPTSIZ0_RX_DPID_SET 0x60000000 + #define USB_DOEPTSIZ0_RX_DPID_CLR 0x9fffffff + #define USB_DOEPTSIZ0_RX_DPID_MSB 30 + #define USB_DOEPTSIZ0_RX_DPID_LSB 29 + #define USB_DOEPTSIZ0_RX_DPID_RESET 0x0 + #define USB_DOEPTSIZ0_MC_BITS 30:29 + #define USB_DOEPTSIZ0_MC_SET 0x60000000 + #define USB_DOEPTSIZ0_MC_CLR 0x9fffffff + #define USB_DOEPTSIZ0_MC_MSB 30 + #define USB_DOEPTSIZ0_MC_LSB 29 + #define USB_DOEPTSIZ0_MC_RESET 0x0 + #define USB_DOEPTSIZ0_PKT_CNT_BITS 28:19 + #define USB_DOEPTSIZ0_PKT_CNT_SET 0x1ff80000 + #define USB_DOEPTSIZ0_PKT_CNT_CLR 0xe007ffff + #define USB_DOEPTSIZ0_PKT_CNT_MSB 28 + #define USB_DOEPTSIZ0_PKT_CNT_LSB 19 + #define USB_DOEPTSIZ0_PKT_CNT_RESET 0x0 + #define USB_DOEPTSIZ0_XFERSIZE_BITS 18:0 + #define USB_DOEPTSIZ0_XFERSIZE_SET 0x0007ffff + #define USB_DOEPTSIZ0_XFERSIZE_CLR 0xfff80000 + #define USB_DOEPTSIZ0_XFERSIZE_MSB 18 + #define USB_DOEPTSIZ0_XFERSIZE_LSB 0 + #define USB_DOEPTSIZ0_XFERSIZE_RESET 0x0 +#define USB_DOEPDMA0 HW_REGISTER_RW( 0x7e980b14 ) + #define USB_DOEPDMA0_MASK 0xffffffff + #define USB_DOEPDMA0_WIDTH 32 +#define USB_DOEPDMAB0 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB0_MASK 0xffffffff + #define USB_DOEPDMAB0_WIDTH 32 +#define USB_DOEPCTL1 HW_REGISTER_RW( 0x7e980b20 ) + #define USB_DOEPCTL1_MASK 0xffffffff + #define USB_DOEPCTL1_WIDTH 32 +#define USB_DOEPINT1 HW_REGISTER_RW( 0x7e980b28 ) + #define USB_DOEPINT1_MASK 0xffffffff + #define USB_DOEPINT1_WIDTH 32 +#define USB_DOEPTSIZ1 HW_REGISTER_RW( 0x7e980b30 ) + #define USB_DOEPTSIZ1_MASK 0xffffffff + #define USB_DOEPTSIZ1_WIDTH 32 +#define USB_DOEPDMA1 HW_REGISTER_RW( 0x7e980b34 ) + #define USB_DOEPDMA1_MASK 0xffffffff + #define USB_DOEPDMA1_WIDTH 32 +#define USB_DOEPDMAB1 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB1_MASK 0xffffffff + #define USB_DOEPDMAB1_WIDTH 32 +#define USB_DOEPCTL2 HW_REGISTER_RW( 0x7e980b40 ) + #define USB_DOEPCTL2_MASK 0xffffffff + #define USB_DOEPCTL2_WIDTH 32 +#define USB_DOEPINT2 HW_REGISTER_RW( 0x7e980b48 ) + #define USB_DOEPINT2_MASK 0xffffffff + #define USB_DOEPINT2_WIDTH 32 +#define USB_DOEPTSIZ2 HW_REGISTER_RW( 0x7e980b50 ) + #define USB_DOEPTSIZ2_MASK 0xffffffff + #define USB_DOEPTSIZ2_WIDTH 32 +#define USB_DOEPDMA2 HW_REGISTER_RW( 0x7e980b54 ) + #define USB_DOEPDMA2_MASK 0xffffffff + #define USB_DOEPDMA2_WIDTH 32 +#define USB_DOEPDMAB2 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB2_MASK 0xffffffff + #define USB_DOEPDMAB2_WIDTH 32 +#define USB_DOEPCTL3 HW_REGISTER_RW( 0x7e980b60 ) + #define USB_DOEPCTL3_MASK 0xffffffff + #define USB_DOEPCTL3_WIDTH 32 +#define USB_DOEPINT3 HW_REGISTER_RW( 0x7e980b68 ) + #define USB_DOEPINT3_MASK 0xffffffff + #define USB_DOEPINT3_WIDTH 32 +#define USB_DOEPTSIZ3 HW_REGISTER_RW( 0x7e980b70 ) + #define USB_DOEPTSIZ3_MASK 0xffffffff + #define USB_DOEPTSIZ3_WIDTH 32 +#define USB_DOEPDMA3 HW_REGISTER_RW( 0x7e980b74 ) + #define USB_DOEPDMA3_MASK 0xffffffff + #define USB_DOEPDMA3_WIDTH 32 +#define USB_DOEPDMAB3 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB3_MASK 0xffffffff + #define USB_DOEPDMAB3_WIDTH 32 +#define USB_DOEPCTL4 HW_REGISTER_RW( 0x7e980b80 ) + #define USB_DOEPCTL4_MASK 0xffffffff + #define USB_DOEPCTL4_WIDTH 32 +#define USB_DOEPINT4 HW_REGISTER_RW( 0x7e980b88 ) + #define USB_DOEPINT4_MASK 0xffffffff + #define USB_DOEPINT4_WIDTH 32 +#define USB_DOEPTSIZ4 HW_REGISTER_RW( 0x7e980b90 ) + #define USB_DOEPTSIZ4_MASK 0xffffffff + #define USB_DOEPTSIZ4_WIDTH 32 +#define USB_DOEPDMA4 HW_REGISTER_RW( 0x7e980b94 ) + #define USB_DOEPDMA4_MASK 0xffffffff + #define USB_DOEPDMA4_WIDTH 32 +#define USB_DOEPDMAB4 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB4_MASK 0xffffffff + #define USB_DOEPDMAB4_WIDTH 32 +#define USB_DOEPCTL5 HW_REGISTER_RW( 0x7e980ba0 ) + #define USB_DOEPCTL5_MASK 0xffffffff + #define USB_DOEPCTL5_WIDTH 32 +#define USB_DOEPINT5 HW_REGISTER_RW( 0x7e980ba8 ) + #define USB_DOEPINT5_MASK 0xffffffff + #define USB_DOEPINT5_WIDTH 32 +#define USB_DOEPTSIZ5 HW_REGISTER_RW( 0x7e980bb0 ) + #define USB_DOEPTSIZ5_MASK 0xffffffff + #define USB_DOEPTSIZ5_WIDTH 32 +#define USB_DOEPDMA5 HW_REGISTER_RW( 0x7e980bb4 ) + #define USB_DOEPDMA5_MASK 0xffffffff + #define USB_DOEPDMA5_WIDTH 32 +#define USB_DOEPDMAB5 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB5_MASK 0xffffffff + #define USB_DOEPDMAB5_WIDTH 32 +#define USB_DOEPCTL6 HW_REGISTER_RW( 0x7e980bc0 ) + #define USB_DOEPCTL6_MASK 0xffffffff + #define USB_DOEPCTL6_WIDTH 32 +#define USB_DOEPINT6 HW_REGISTER_RW( 0x7e980bc8 ) + #define USB_DOEPINT6_MASK 0xffffffff + #define USB_DOEPINT6_WIDTH 32 +#define USB_DOEPTSIZ6 HW_REGISTER_RW( 0x7e980bd0 ) + #define USB_DOEPTSIZ6_MASK 0xffffffff + #define USB_DOEPTSIZ6_WIDTH 32 +#define USB_DOEPDMA6 HW_REGISTER_RW( 0x7e980bd4 ) + #define USB_DOEPDMA6_MASK 0xffffffff + #define USB_DOEPDMA6_WIDTH 32 +#define USB_DOEPDMAB6 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB6_MASK 0xffffffff + #define USB_DOEPDMAB6_WIDTH 32 +#define USB_DOEPCTL7 HW_REGISTER_RW( 0x7e980be0 ) + #define USB_DOEPCTL7_MASK 0xffffffff + #define USB_DOEPCTL7_WIDTH 32 +#define USB_DOEPINT7 HW_REGISTER_RW( 0x7e980be8 ) + #define USB_DOEPINT7_MASK 0xffffffff + #define USB_DOEPINT7_WIDTH 32 +#define USB_DOEPTSIZ7 HW_REGISTER_RW( 0x7e980bf0 ) + #define USB_DOEPTSIZ7_MASK 0xffffffff + #define USB_DOEPTSIZ7_WIDTH 32 +#define USB_DOEPDMA7 HW_REGISTER_RW( 0x7e980bf4 ) + #define USB_DOEPDMA7_MASK 0xffffffff + #define USB_DOEPDMA7_WIDTH 32 +#define USB_DOEPDMAB7 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB7_MASK 0xffffffff + #define USB_DOEPDMAB7_WIDTH 32 +#define USB_DOEPCTL8 HW_REGISTER_RW( 0x7e980c00 ) + #define USB_DOEPCTL8_MASK 0xffffffff + #define USB_DOEPCTL8_WIDTH 32 +#define USB_DOEPINT8 HW_REGISTER_RW( 0x7e980c08 ) + #define USB_DOEPINT8_MASK 0xffffffff + #define USB_DOEPINT8_WIDTH 32 +#define USB_DOEPTSIZ8 HW_REGISTER_RW( 0x7e980c10 ) + #define USB_DOEPTSIZ8_MASK 0xffffffff + #define USB_DOEPTSIZ8_WIDTH 32 +#define USB_DOEPDMA8 HW_REGISTER_RW( 0x7e980c14 ) + #define USB_DOEPDMA8_MASK 0xffffffff + #define USB_DOEPDMA8_WIDTH 32 +#define USB_DOEPDMAB8 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB8_MASK 0xffffffff + #define USB_DOEPDMAB8_WIDTH 32 +#define USB_DOEPCTL9 HW_REGISTER_RW( 0x7e980c20 ) + #define USB_DOEPCTL9_MASK 0xffffffff + #define USB_DOEPCTL9_WIDTH 32 +#define USB_DOEPINT9 HW_REGISTER_RW( 0x7e980c28 ) + #define USB_DOEPINT9_MASK 0xffffffff + #define USB_DOEPINT9_WIDTH 32 +#define USB_DOEPTSIZ9 HW_REGISTER_RW( 0x7e980c30 ) + #define USB_DOEPTSIZ9_MASK 0xffffffff + #define USB_DOEPTSIZ9_WIDTH 32 +#define USB_DOEPDMA9 HW_REGISTER_RW( 0x7e980c34 ) + #define USB_DOEPDMA9_MASK 0xffffffff + #define USB_DOEPDMA9_WIDTH 32 +#define USB_DOEPDMAB9 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB9_MASK 0xffffffff + #define USB_DOEPDMAB9_WIDTH 32 +#define USB_DOEPCTL10 HW_REGISTER_RW( 0x7e980c40 ) + #define USB_DOEPCTL10_MASK 0xffffffff + #define USB_DOEPCTL10_WIDTH 32 +#define USB_DOEPINT10 HW_REGISTER_RW( 0x7e980c48 ) + #define USB_DOEPINT10_MASK 0xffffffff + #define USB_DOEPINT10_WIDTH 32 +#define USB_DOEPTSIZ10 HW_REGISTER_RW( 0x7e980c50 ) + #define USB_DOEPTSIZ10_MASK 0xffffffff + #define USB_DOEPTSIZ10_WIDTH 32 +#define USB_DOEPDMA10 HW_REGISTER_RW( 0x7e980c54 ) + #define USB_DOEPDMA10_MASK 0xffffffff + #define USB_DOEPDMA10_WIDTH 32 +#define USB_DOEPDMAB10 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB10_MASK 0xffffffff + #define USB_DOEPDMAB10_WIDTH 32 +#define USB_DOEPCTL11 HW_REGISTER_RW( 0x7e980c60 ) + #define USB_DOEPCTL11_MASK 0xffffffff + #define USB_DOEPCTL11_WIDTH 32 +#define USB_DOEPINT11 HW_REGISTER_RW( 0x7e980c68 ) + #define USB_DOEPINT11_MASK 0xffffffff + #define USB_DOEPINT11_WIDTH 32 +#define USB_DOEPTSIZ11 HW_REGISTER_RW( 0x7e980c70 ) + #define USB_DOEPTSIZ11_MASK 0xffffffff + #define USB_DOEPTSIZ11_WIDTH 32 +#define USB_DOEPDMA11 HW_REGISTER_RW( 0x7e980c74 ) + #define USB_DOEPDMA11_MASK 0xffffffff + #define USB_DOEPDMA11_WIDTH 32 +#define USB_DOEPDMAB11 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB11_MASK 0xffffffff + #define USB_DOEPDMAB11_WIDTH 32 +#define USB_DOEPCTL12 HW_REGISTER_RW( 0x7e980c80 ) + #define USB_DOEPCTL12_MASK 0xffffffff + #define USB_DOEPCTL12_WIDTH 32 +#define USB_DOEPINT12 HW_REGISTER_RW( 0x7e980c88 ) + #define USB_DOEPINT12_MASK 0xffffffff + #define USB_DOEPINT12_WIDTH 32 +#define USB_DOEPTSIZ12 HW_REGISTER_RW( 0x7e980c90 ) + #define USB_DOEPTSIZ12_MASK 0xffffffff + #define USB_DOEPTSIZ12_WIDTH 32 +#define USB_DOEPDMA12 HW_REGISTER_RW( 0x7e980c94 ) + #define USB_DOEPDMA12_MASK 0xffffffff + #define USB_DOEPDMA12_WIDTH 32 +#define USB_DOEPDMAB12 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB12_MASK 0xffffffff + #define USB_DOEPDMAB12_WIDTH 32 +#define USB_DOEPCTL13 HW_REGISTER_RW( 0x7e980ca0 ) + #define USB_DOEPCTL13_MASK 0xffffffff + #define USB_DOEPCTL13_WIDTH 32 +#define USB_DOEPINT13 HW_REGISTER_RW( 0x7e980ca8 ) + #define USB_DOEPINT13_MASK 0xffffffff + #define USB_DOEPINT13_WIDTH 32 +#define USB_DOEPTSIZ13 HW_REGISTER_RW( 0x7e980cb0 ) + #define USB_DOEPTSIZ13_MASK 0xffffffff + #define USB_DOEPTSIZ13_WIDTH 32 +#define USB_DOEPDMA13 HW_REGISTER_RW( 0x7e980cb4 ) + #define USB_DOEPDMA13_MASK 0xffffffff + #define USB_DOEPDMA13_WIDTH 32 +#define USB_DOEPDMAB13 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB13_MASK 0xffffffff + #define USB_DOEPDMAB13_WIDTH 32 +#define USB_DOEPCTL14 HW_REGISTER_RW( 0x7e980cc0 ) + #define USB_DOEPCTL14_MASK 0xffffffff + #define USB_DOEPCTL14_WIDTH 32 +#define USB_DOEPINT14 HW_REGISTER_RW( 0x7e980cc8 ) + #define USB_DOEPINT14_MASK 0xffffffff + #define USB_DOEPINT14_WIDTH 32 +#define USB_DOEPTSIZ14 HW_REGISTER_RW( 0x7e980cd0 ) + #define USB_DOEPTSIZ14_MASK 0xffffffff + #define USB_DOEPTSIZ14_WIDTH 32 +#define USB_DOEPDMA14 HW_REGISTER_RW( 0x7e980cd4 ) + #define USB_DOEPDMA14_MASK 0xffffffff + #define USB_DOEPDMA14_WIDTH 32 +#define USB_DOEPDMAB14 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB14_MASK 0xffffffff + #define USB_DOEPDMAB14_WIDTH 32 +#define USB_DOEPCTL15 HW_REGISTER_RW( 0x7e980ce0 ) + #define USB_DOEPCTL15_MASK 0xffffffff + #define USB_DOEPCTL15_WIDTH 32 +#define USB_DOEPINT15 HW_REGISTER_RW( 0x7e980ce8 ) + #define USB_DOEPINT15_MASK 0xffffffff + #define USB_DOEPINT15_WIDTH 32 +#define USB_DOEPTSIZ15 HW_REGISTER_RW( 0x7e980cf0 ) + #define USB_DOEPTSIZ15_MASK 0xffffffff + #define USB_DOEPTSIZ15_WIDTH 32 +#define USB_DOEPDMA15 HW_REGISTER_RW( 0x7e980cf4 ) + #define USB_DOEPDMA15_MASK 0xffffffff + #define USB_DOEPDMA15_WIDTH 32 +#define USB_DOEPDMAB15 HW_REGISTER_RW( 0x7e980b1c ) + #define USB_DOEPDMAB15_MASK 0xffffffff + #define USB_DOEPDMAB15_WIDTH 32 +#define USB_PCGCR HW_REGISTER_RW( 0x7e980e00 ) + #define USB_PCGCR_MASK 0x0000000f + #define USB_PCGCR_WIDTH 4 + #define USB_PCGCR_RST_PDWN_MODULE_BITS 3:3 + #define USB_PCGCR_RST_PDWN_MODULE_SET 0x00000008 + #define USB_PCGCR_RST_PDWN_MODULE_CLR 0xfffffff7 + #define USB_PCGCR_RST_PDWN_MODULE_MSB 3 + #define USB_PCGCR_RST_PDWN_MODULE_LSB 3 + #define USB_PCGCR_RST_PDWN_MODULE_RESET 0x0 + #define USB_PCGCR_PWR_CLMP_BITS 2:2 + #define USB_PCGCR_PWR_CLMP_SET 0x00000004 + #define USB_PCGCR_PWR_CLMP_CLR 0xfffffffb + #define USB_PCGCR_PWR_CLMP_MSB 2 + #define USB_PCGCR_PWR_CLMP_LSB 2 + #define USB_PCGCR_PWR_CLMP_RESET 0x0 + #define USB_PCGCR_GATE_HCLK_BITS 1:1 + #define USB_PCGCR_GATE_HCLK_SET 0x00000002 + #define USB_PCGCR_GATE_HCLK_CLR 0xfffffffd + #define USB_PCGCR_GATE_HCLK_MSB 1 + #define USB_PCGCR_GATE_HCLK_LSB 1 + #define USB_PCGCR_GATE_HCLK_RESET 0x0 + #define USB_PCGCR_STOP_PCLK_BITS 0:0 + #define USB_PCGCR_STOP_PCLK_SET 0x00000001 + #define USB_PCGCR_STOP_PCLK_CLR 0xfffffffe + #define USB_PCGCR_STOP_PCLK_MSB 0 + #define USB_PCGCR_STOP_PCLK_LSB 0 + #define USB_PCGCR_STOP_PCLK_RESET 0x0 +#define USB_DFIFO0 HW_REGISTER_RW( 0x7e981000 ) + #define USB_DFIFO0_MASK 0xffffffff + #define USB_DFIFO0_WIDTH 32 +#define USB_DFIFO1 HW_REGISTER_RW( 0x7e982000 ) + #define USB_DFIFO1_MASK 0xffffffff + #define USB_DFIFO1_WIDTH 32 +#define USB_DFIFO2 HW_REGISTER_RW( 0x7e983000 ) + #define USB_DFIFO2_MASK 0xffffffff + #define USB_DFIFO2_WIDTH 32 +#define USB_DFIFO3 HW_REGISTER_RW( 0x7e984000 ) + #define USB_DFIFO3_MASK 0xffffffff + #define USB_DFIFO3_WIDTH 32 +#define USB_DFIFO4 HW_REGISTER_RW( 0x7e985000 ) + #define USB_DFIFO4_MASK 0xffffffff + #define USB_DFIFO4_WIDTH 32 +#define USB_DFIFO5 HW_REGISTER_RW( 0x7e986000 ) + #define USB_DFIFO5_MASK 0xffffffff + #define USB_DFIFO5_WIDTH 32 +#define USB_DFIFO6 HW_REGISTER_RW( 0x7e987000 ) + #define USB_DFIFO6_MASK 0xffffffff + #define USB_DFIFO6_WIDTH 32 +#define USB_DFIFO7 HW_REGISTER_RW( 0x7e988000 ) + #define USB_DFIFO7_MASK 0xffffffff + #define USB_DFIFO7_WIDTH 32 +#define USB_DFIFO8 HW_REGISTER_RW( 0x7e989000 ) + #define USB_DFIFO8_MASK 0xffffffff + #define USB_DFIFO8_WIDTH 32 +#define USB_DFIFO9 HW_REGISTER_RW( 0x7e98a000 ) + #define USB_DFIFO9_MASK 0xffffffff + #define USB_DFIFO9_WIDTH 32 +#define USB_DFIFO10 HW_REGISTER_RW( 0x7e98b000 ) + #define USB_DFIFO10_MASK 0xffffffff + #define USB_DFIFO10_WIDTH 32 +#define USB_DFIFO11 HW_REGISTER_RW( 0x7e98c000 ) + #define USB_DFIFO11_MASK 0xffffffff + #define USB_DFIFO11_WIDTH 32 +#define USB_DFIFO12 HW_REGISTER_RW( 0x7e98d000 ) + #define USB_DFIFO12_MASK 0xffffffff + #define USB_DFIFO12_WIDTH 32 +#define USB_DFIFO13 HW_REGISTER_RW( 0x7e98e000 ) + #define USB_DFIFO13_MASK 0xffffffff + #define USB_DFIFO13_WIDTH 32 +#define USB_DFIFO14 HW_REGISTER_RW( 0x7e98f000 ) + #define USB_DFIFO14_MASK 0xffffffff + #define USB_DFIFO14_WIDTH 32 +#define USB_DFIFO15 HW_REGISTER_RW( 0x7e990000 ) + #define USB_DFIFO15_MASK 0xffffffff + #define USB_DFIFO15_WIDTH 32 diff --git a/bcm2708_chip/v3d.h b/bcm2708_chip/v3d.h new file mode 100755 index 0000000..2ee79a9 --- /dev/null +++ b/bcm2708_chip/v3d.h @@ -0,0 +1,306 @@ +// This file was generated by the create_regs script +#ifdef ANDROID +extern void *regbase; +#define V3D_BASE ((unsigned long)regbase) +#else // ANDROID +#if defined(__CC_ARM) && defined(V3D_INCLUDED) +#if defined(_HERA_) || defined(_RHEA_) || defined(_SAMOA_) +#define V3D_BASE 0x3c00b000 /* for Hera V3D */ +#elif defined(_ATHENA_) +#define V3D_BASE 0x08950000 +#else + #error "WRONG BASEBAND CHIP!!!" +#endif +#else +#define V3D_BASE 0x7ec00000 /* for VC4 V3D */ +#endif +#endif // ANDROID + +#define V3D_IDENT0 HW_REGISTER_RW( V3D_BASE+0x0000 ) + #define V3D_IDENT0_MASK 0xffffffff + #define V3D_IDENT0_WIDTH 32 +#define V3D_IDENT1 HW_REGISTER_RW( V3D_BASE+0x0004 ) + #define V3D_IDENT1_MASK 0xffffffff + #define V3D_IDENT1_WIDTH 32 +#define V3D_IDENT2 HW_REGISTER_RW( V3D_BASE+0x0008 ) + #define V3D_IDENT2_MASK 0xffffffff + #define V3D_IDENT2_WIDTH 32 +#define V3D_IDENT3 HW_REGISTER_RW( V3D_BASE+0x000c ) + #define V3D_IDENT3_MASK 0xffffffff + #define V3D_IDENT3_WIDTH 32 +#define V3D_SCRATCH HW_REGISTER_RW( V3D_BASE+0x0010 ) + #define V3D_SCRATCH_MASK 0xffffffff + #define V3D_SCRATCH_WIDTH 32 +#define V3D_L2CACTL HW_REGISTER_RW( V3D_BASE+0x0020 ) + #define V3D_L2CACTL_MASK 0xffffffff + #define V3D_L2CACTL_WIDTH 32 +#define V3D_SLCACTL HW_REGISTER_RW( V3D_BASE+0x0024 ) + #define V3D_SLCACTL_MASK 0xffffffff + #define V3D_SLCACTL_WIDTH 32 +#define V3D_INTCTL HW_REGISTER_RW( V3D_BASE+0x0030 ) + #define V3D_INTCTL_MASK 0xffffffff + #define V3D_INTCTL_WIDTH 32 +#define V3D_INTENA HW_REGISTER_RW( V3D_BASE+0x0034 ) + #define V3D_INTENA_MASK 0xffffffff + #define V3D_INTENA_WIDTH 32 +#define V3D_INTDIS HW_REGISTER_RW( V3D_BASE+0x0038 ) + #define V3D_INTDIS_MASK 0xffffffff + #define V3D_INTDIS_WIDTH 32 +#define V3D_CT0CS HW_REGISTER_RW( V3D_BASE+0x0100 ) + #define V3D_CT0CS_MASK 0xffffffff + #define V3D_CT0CS_WIDTH 32 +#define V3D_CT1CS HW_REGISTER_RW( V3D_BASE+0x0104 ) + #define V3D_CT1CS_MASK 0xffffffff + #define V3D_CT1CS_WIDTH 32 +#define V3D_CT0EA HW_REGISTER_RW( V3D_BASE+0x0108 ) + #define V3D_CT0EA_MASK 0xffffffff + #define V3D_CT0EA_WIDTH 32 +#define V3D_CT1EA HW_REGISTER_RW( V3D_BASE+0x010c ) + #define V3D_CT1EA_MASK 0xffffffff + #define V3D_CT1EA_WIDTH 32 +#define V3D_CT0CA HW_REGISTER_RW( V3D_BASE+0x0110 ) + #define V3D_CT0CA_MASK 0xffffffff + #define V3D_CT0CA_WIDTH 32 +#define V3D_CT1CA HW_REGISTER_RW( V3D_BASE+0x0114 ) + #define V3D_CT1CA_MASK 0xffffffff + #define V3D_CT1CA_WIDTH 32 +#define V3D_CT00RA0 HW_REGISTER_RW( V3D_BASE+0x0118 ) + #define V3D_CT00RA0_MASK 0xffffffff + #define V3D_CT00RA0_WIDTH 32 +#define V3D_CT01RA0 HW_REGISTER_RW( V3D_BASE+0x011c ) + #define V3D_CT01RA0_MASK 0xffffffff + #define V3D_CT01RA0_WIDTH 32 +#define V3D_CT0LC HW_REGISTER_RW( V3D_BASE+0x0120 ) + #define V3D_CT0LC_MASK 0xffffffff + #define V3D_CT0LC_WIDTH 32 +#define V3D_CT1LC HW_REGISTER_RW( V3D_BASE+0x0124 ) + #define V3D_CT1LC_MASK 0xffffffff + #define V3D_CT1LC_WIDTH 32 +#define V3D_CT0PC HW_REGISTER_RW( V3D_BASE+0x0128 ) + #define V3D_CT0PC_MASK 0xffffffff + #define V3D_CT0PC_WIDTH 32 +#define V3D_CT1PC HW_REGISTER_RW( V3D_BASE+0x012c ) + #define V3D_CT1PC_MASK 0xffffffff + #define V3D_CT1PC_WIDTH 32 +#define V3D_PCS HW_REGISTER_RW( V3D_BASE+0x0130 ) + #define V3D_PCS_MASK 0x0000013f + #define V3D_PCS_WIDTH 9 +#define V3D_BFC HW_REGISTER_RW( V3D_BASE+0x0134 ) + #define V3D_BFC_MASK 0x000000ff + #define V3D_BFC_WIDTH 8 +#define V3D_RFC HW_REGISTER_RW( V3D_BASE+0x0138 ) + #define V3D_RFC_MASK 0x000000ff + #define V3D_RFC_WIDTH 8 +#define V3D_BPCA HW_REGISTER_RW( V3D_BASE+0x0300 ) + #define V3D_BPCA_MASK 0xffffffff + #define V3D_BPCA_WIDTH 32 +#define V3D_BPCS HW_REGISTER_RW( V3D_BASE+0x0304 ) + #define V3D_BPCS_MASK 0xffffffff + #define V3D_BPCS_WIDTH 32 +#define V3D_BPOA HW_REGISTER_RW( V3D_BASE+0x0308 ) + #define V3D_BPOA_MASK 0xffffffff + #define V3D_BPOA_WIDTH 32 +#define V3D_BPOS HW_REGISTER_RW( V3D_BASE+0x030c ) + #define V3D_BPOS_MASK 0xffffffff + #define V3D_BPOS_WIDTH 32 +#define V3D_BXCF HW_REGISTER_RW( V3D_BASE+0x0310 ) + #define V3D_BXCF_MASK 0x00000003 + #define V3D_BXCF_WIDTH 2 +#define V3D_SQRSV0 HW_REGISTER_RW( V3D_BASE+0x0410 ) + #define V3D_SQRSV0_MASK 0xffffffff + #define V3D_SQRSV0_WIDTH 32 +#define V3D_SQRSV1 HW_REGISTER_RW( V3D_BASE+0x0414 ) + #define V3D_SQRSV1_MASK 0xffffffff + #define V3D_SQRSV1_WIDTH 32 +#define V3D_SQCNTL HW_REGISTER_RW( V3D_BASE+0x0418 ) + #define V3D_SQCNTL_MASK 0x0000000f + #define V3D_SQCNTL_WIDTH 4 +#define V3D_SQCSTAT HW_REGISTER_RW( V3D_BASE+0x041c ) + #define V3D_SQCSTAT_MASK 0xffffffff + #define V3D_SQCSTAT_WIDTH 32 +#define V3D_SRQPC HW_REGISTER_RW( V3D_BASE+0x0430 ) + #define V3D_SRQPC_MASK 0xffffffff + #define V3D_SRQPC_WIDTH 32 +#define V3D_SRQUA HW_REGISTER_RW( V3D_BASE+0x0434 ) + #define V3D_SRQUA_MASK 0xffffffff + #define V3D_SRQUA_WIDTH 32 +#define V3D_SRQUL HW_REGISTER_RW( V3D_BASE+0x0438 ) + #define V3D_SRQUL_MASK 0x00000fff + #define V3D_SRQUL_WIDTH 12 +#define V3D_SRQCS HW_REGISTER_RW( V3D_BASE+0x043c ) + #define V3D_SRQCS_MASK 0x00ffffbf + #define V3D_SRQCS_WIDTH 24 +#define V3D_VPACNTL HW_REGISTER_RW( V3D_BASE+0x0500 ) + #define V3D_VPACNTL_MASK 0xffffffff + #define V3D_VPACNTL_WIDTH 32 +#define V3D_VPMBASE HW_REGISTER_RW( V3D_BASE+0x0504 ) + #define V3D_VPMBASE_MASK 0xffffffff + #define V3D_VPMBASE_WIDTH 32 +#define V3D_PCTRC HW_REGISTER_RW( 0x7ec00670 ) + #define V3D_PCTRC_MASK 0x0000ffff + #define V3D_PCTRC_WIDTH 16 +#define V3D_PCTRE HW_REGISTER_RW( 0x7ec00674 ) + #define V3D_PCTRE_MASK 0x8000ffff + #define V3D_PCTRE_WIDTH 32 +#define V3D_PCTR0 HW_REGISTER_RW( 0x7ec00680 ) + #define V3D_PCTR0_MASK 0xffffffff + #define V3D_PCTR0_WIDTH 32 +#define V3D_PCTRS0 HW_REGISTER_RW( 0x7ec00684 ) + #define V3D_PCTRS0_MASK 0x0000001f + #define V3D_PCTRS0_WIDTH 5 +#define V3D_PCTR1 HW_REGISTER_RW( 0x7ec00688 ) + #define V3D_PCTR1_MASK 0xffffffff + #define V3D_PCTR1_WIDTH 32 +#define V3D_PCTRS1 HW_REGISTER_RW( 0x7ec0068c ) + #define V3D_PCTRS1_MASK 0x0000001f + #define V3D_PCTRS1_WIDTH 5 +#define V3D_PCTR2 HW_REGISTER_RW( 0x7ec00690 ) + #define V3D_PCTR2_MASK 0xffffffff + #define V3D_PCTR2_WIDTH 32 +#define V3D_PCTRS2 HW_REGISTER_RW( 0x7ec00694 ) + #define V3D_PCTRS2_MASK 0x0000001f + #define V3D_PCTRS2_WIDTH 5 +#define V3D_PCTR3 HW_REGISTER_RW( 0x7ec00698 ) + #define V3D_PCTR3_MASK 0xffffffff + #define V3D_PCTR3_WIDTH 32 +#define V3D_PCTRS3 HW_REGISTER_RW( 0x7ec0069c ) + #define V3D_PCTRS3_MASK 0x0000001f + #define V3D_PCTRS3_WIDTH 5 +#define V3D_PCTR4 HW_REGISTER_RW( 0x7ec006a0 ) + #define V3D_PCTR4_MASK 0xffffffff + #define V3D_PCTR4_WIDTH 32 +#define V3D_PCTRS4 HW_REGISTER_RW( 0x7ec006a4 ) + #define V3D_PCTRS4_MASK 0x0000001f + #define V3D_PCTRS4_WIDTH 5 +#define V3D_PCTR5 HW_REGISTER_RW( 0x7ec006a8 ) + #define V3D_PCTR5_MASK 0xffffffff + #define V3D_PCTR5_WIDTH 32 +#define V3D_PCTRS5 HW_REGISTER_RW( 0x7ec006ac ) + #define V3D_PCTRS5_MASK 0x0000001f + #define V3D_PCTRS5_WIDTH 5 +#define V3D_PCTR6 HW_REGISTER_RW( 0x7ec006b0 ) + #define V3D_PCTR6_MASK 0xffffffff + #define V3D_PCTR6_WIDTH 32 +#define V3D_PCTRS6 HW_REGISTER_RW( 0x7ec006b4 ) + #define V3D_PCTRS6_MASK 0x0000001f + #define V3D_PCTRS6_WIDTH 5 +#define V3D_PCTR7 HW_REGISTER_RW( 0x7ec006b8 ) + #define V3D_PCTR7_MASK 0xffffffff + #define V3D_PCTR7_WIDTH 32 +#define V3D_PCTRS7 HW_REGISTER_RW( 0x7ec006bc ) + #define V3D_PCTRS7_MASK 0x0000001f + #define V3D_PCTRS7_WIDTH 5 +#define V3D_PCTR8 HW_REGISTER_RW( 0x7ec006c0 ) + #define V3D_PCTR8_MASK 0xffffffff + #define V3D_PCTR8_WIDTH 32 +#define V3D_PCTRS8 HW_REGISTER_RW( 0x7ec006c4 ) + #define V3D_PCTRS8_MASK 0x0000001f + #define V3D_PCTRS8_WIDTH 5 +#define V3D_PCTR9 HW_REGISTER_RW( 0x7ec006c8 ) + #define V3D_PCTR9_MASK 0xffffffff + #define V3D_PCTR9_WIDTH 32 +#define V3D_PCTRS9 HW_REGISTER_RW( 0x7ec006cc ) + #define V3D_PCTRS9_MASK 0x0000001f + #define V3D_PCTRS9_WIDTH 5 +#define V3D_PCTR10 HW_REGISTER_RW( 0x7ec006d0 ) + #define V3D_PCTR10_MASK 0xffffffff + #define V3D_PCTR10_WIDTH 32 +#define V3D_PCTRS10 HW_REGISTER_RW( 0x7ec006d4 ) + #define V3D_PCTRS10_MASK 0x0000001f + #define V3D_PCTRS10_WIDTH 5 +#define V3D_PCTR11 HW_REGISTER_RW( 0x7ec006d8 ) + #define V3D_PCTR11_MASK 0xffffffff + #define V3D_PCTR11_WIDTH 32 +#define V3D_PCTRS11 HW_REGISTER_RW( 0x7ec006dc ) + #define V3D_PCTRS11_MASK 0x0000001f + #define V3D_PCTRS11_WIDTH 5 +#define V3D_PCTR12 HW_REGISTER_RW( 0x7ec006e0 ) + #define V3D_PCTR12_MASK 0xffffffff + #define V3D_PCTR12_WIDTH 32 +#define V3D_PCTRS12 HW_REGISTER_RW( 0x7ec006e4 ) + #define V3D_PCTRS12_MASK 0x0000001f + #define V3D_PCTRS12_WIDTH 5 +#define V3D_PCTR13 HW_REGISTER_RW( 0x7ec006e8 ) + #define V3D_PCTR13_MASK 0xffffffff + #define V3D_PCTR13_WIDTH 32 +#define V3D_PCTRS13 HW_REGISTER_RW( 0x7ec006ec ) + #define V3D_PCTRS13_MASK 0x0000001f + #define V3D_PCTRS13_WIDTH 5 +#define V3D_PCTR14 HW_REGISTER_RW( 0x7ec006f0 ) + #define V3D_PCTR14_MASK 0xffffffff + #define V3D_PCTR14_WIDTH 32 +#define V3D_PCTRS14 HW_REGISTER_RW( 0x7ec006f4 ) + #define V3D_PCTRS14_MASK 0x0000001f + #define V3D_PCTRS14_WIDTH 5 +#define V3D_PCTR15 HW_REGISTER_RW( 0x7ec006f8 ) + #define V3D_PCTR15_MASK 0xffffffff + #define V3D_PCTR15_WIDTH 32 +#define V3D_PCTRS15 HW_REGISTER_RW( 0x7ec006fc ) + #define V3D_PCTRS15_MASK 0x0000001f + #define V3D_PCTRS15_WIDTH 5 +#define V3D_DBCFG HW_REGISTER_RW( V3D_BASE+0x0e00 ) + #define V3D_DBCFG_MASK 0xffffffff + #define V3D_DBCFG_WIDTH 32 +#define V3D_DBSCS HW_REGISTER_RW( V3D_BASE+0x0e04 ) + #define V3D_DBSCS_MASK 0xffffffff + #define V3D_DBSCS_WIDTH 32 +#define V3D_DBSCFG HW_REGISTER_RW( V3D_BASE+0x0e08 ) + #define V3D_DBSCFG_MASK 0xffffffff + #define V3D_DBSCFG_WIDTH 32 +#define V3D_DBSSR HW_REGISTER_RW( V3D_BASE+0x0e0c ) + #define V3D_DBSSR_MASK 0xffffffff + #define V3D_DBSSR_WIDTH 32 +#define V3D_DBSDR0 HW_REGISTER_RW( V3D_BASE+0x0e10 ) + #define V3D_DBSDR0_MASK 0xffffffff + #define V3D_DBSDR0_WIDTH 32 +#define V3D_DBSDR1 HW_REGISTER_RW( V3D_BASE+0x0e14 ) + #define V3D_DBSDR1_MASK 0xffffffff + #define V3D_DBSDR1_WIDTH 32 +#define V3D_DBSDR2 HW_REGISTER_RW( V3D_BASE+0x0e18 ) + #define V3D_DBSDR2_MASK 0xffffffff + #define V3D_DBSDR2_WIDTH 32 +#define V3D_DBSDR3 HW_REGISTER_RW( V3D_BASE+0x0e1c ) + #define V3D_DBSDR3_MASK 0xffffffff + #define V3D_DBSDR3_WIDTH 32 +#define V3D_DBQRUN HW_REGISTER_RW( V3D_BASE+0x0e20 ) + #define V3D_DBQRUN_MASK 0xffffffff + #define V3D_DBQRUN_WIDTH 32 +#define V3D_DBQHLT HW_REGISTER_RW( V3D_BASE+0x0e24 ) + #define V3D_DBQHLT_MASK 0xffffffff + #define V3D_DBQHLT_WIDTH 32 +#define V3D_DBQSTP HW_REGISTER_RW( V3D_BASE+0x0e28 ) + #define V3D_DBQSTP_MASK 0xffffffff + #define V3D_DBQSTP_WIDTH 32 +#define V3D_DBQITE HW_REGISTER_RW( V3D_BASE+0x0e2c ) + #define V3D_DBQITE_MASK 0xffffffff + #define V3D_DBQITE_WIDTH 32 +#define V3D_DBQITC HW_REGISTER_RW( V3D_BASE+0x0e30 ) + #define V3D_DBQITC_MASK 0xffffffff + #define V3D_DBQITC_WIDTH 32 +#define V3D_DBQGHC HW_REGISTER_RW( V3D_BASE+0x0e34 ) + #define V3D_DBQGHC_MASK 0xffffffff + #define V3D_DBQGHC_WIDTH 32 +#define V3D_DBQGHG HW_REGISTER_RW( V3D_BASE+0x0e38 ) + #define V3D_DBQGHG_MASK 0xffffffff + #define V3D_DBQGHG_WIDTH 32 +#define V3D_DBQGHH HW_REGISTER_RW( V3D_BASE+0x0e3c ) + #define V3D_DBQGHH_MASK 0xffffffff + #define V3D_DBQGHH_WIDTH 32 +#define V3D_DBGE HW_REGISTER_RW( V3D_BASE+0x0f00 ) + #define V3D_DBGE_MASK 0xffffffff + #define V3D_DBGE_WIDTH 32 +#define V3D_FDBG0 HW_REGISTER_RW( V3D_BASE+0x0f04 ) + #define V3D_FDBG0_MASK 0xffffffff + #define V3D_FDBG0_WIDTH 32 +#define V3D_FDBGB HW_REGISTER_RW( V3D_BASE+0x0f08 ) + #define V3D_FDBGB_MASK 0xffffffff + #define V3D_FDBGB_WIDTH 32 +#define V3D_FDBGR HW_REGISTER_RW( V3D_BASE+0x0f0c ) + #define V3D_FDBGR_MASK 0xffffffff + #define V3D_FDBGR_WIDTH 32 +#define V3D_FDBGS HW_REGISTER_RW( V3D_BASE+0x0f10 ) + #define V3D_FDBGS_MASK 0xffffffff + #define V3D_FDBGS_WIDTH 32 +#define V3D_ERRSTAT HW_REGISTER_RW( V3D_BASE+0x0f20 ) + #define V3D_ERRSTAT_MASK 0xffffffff + #define V3D_ERRSTAT_WIDTH 32 diff --git a/bcm2708_chip/vcodec.h b/bcm2708_chip/vcodec.h new file mode 100755 index 0000000..ba9dc50 --- /dev/null +++ b/bcm2708_chip/vcodec.h @@ -0,0 +1,793 @@ +/*============================================================================= +Copyright (c) 2006 Broadcom Europe Limited. +All rights reserved. + +Project : VideoCore III +Module : Video codec specific header (vcodec) +File : $RCSfile: vcodec.h,v $ +Revision : $Revision: 1.14 $ + +FILE DESCRIPTION +Chip I/O for the video codec. +=============================================================================*/ + +#ifndef __VCODEC_H__ +#define __VCODEC_H__ + +#define VCODEC_IO_BASE 0x7f000000 + + +typedef enum +{ + WIDTH_MASK0 = 0, + WIDTH_MASK1 = 0x00000001, + WIDTH_MASK2 = 0x00000003, + WIDTH_MASK3 = 0x00000007, + WIDTH_MASK4 = 0x0000000f, + WIDTH_MASK5 = 0x0000001f, + WIDTH_MASK6 = 0x0000003f, + WIDTH_MASK7 = 0x0000007f, + WIDTH_MASK8 = 0x000000ff, + WIDTH_MASK9 = 0x000001ff, + WIDTH_MASK10 = 0x000003ff, + WIDTH_MASK11 = 0x000007ff, + WIDTH_MASK12 = 0x00000fff, + WIDTH_MASK13 = 0x00001fff, + WIDTH_MASK14 = 0x00003fff, + WIDTH_MASK15 = 0x00007fff, + WIDTH_MASK16 = 0x0000ffff, + WIDTH_MASK17 = 0x0001ffff, + WIDTH_MASK18 = 0x0003ffff, + WIDTH_MASK19 = 0x0007ffff, + WIDTH_MASK20 = 0x000fffff, + WIDTH_MASK21 = 0x001fffff, + WIDTH_MASK22 = 0x003fffff, + WIDTH_MASK23 = 0x007fffff, + WIDTH_MASK24 = 0x00ffffff, + WIDTH_MASK25 = 0x01ffffff, + WIDTH_MASK26 = 0x03ffffff, + WIDTH_MASK27 = 0x07ffffff, + WIDTH_MASK28 = 0x0fffffff, + WIDTH_MASK29 = 0x1fffffff, + WIDTH_MASK30 = 0x3fffffff, + WIDTH_MASK31 = 0x7fffffff, + WIDTH_MASK32 = 0xffffffff +} WIDTH_MASKS; + + +/* Pull the register addresses from 'RegFld.h' and create an enum; + * this gives us a set of constants that we can use to access the + * registers in IO statements. + */ + #define CHIP "sv_chip_regmap.h" + #define CHIP2 "sv_enc_chip_regmap.h" + +enum +{ +#define RegAreaFunc(a,b,c) a = b, a##End = c, a##Max = c-b, +#define RegFunc(mod, modbase, regname, offset, name, addr) name = addr, +#define FldFunc(a,b,c,d) + +#include CHIP +//#include CHIP2 + +#undef FldFunc +#undef RegFunc +#undef RegAreaFunc +}; + +// Enum of FIELD_Reg +typedef enum { +#define FldFunc(reg, field, lsb, width) FIELD_ ##reg ##_ ##field = (WIDTH_MASK ##width << lsb), +#include CHIP +//#include CHIP2 +}RegAddrField; +#undef FldFunc + +// Enum of POS_Reg +typedef enum { +#define FldFunc(reg, field, lsb, width) POS_ ##reg ##_ ##field = lsb, +#include CHIP +//#include CHIP2 +}RegAddrPos; +#undef FldFunc + + + +/* Don't use _VCODEC_IO directly - prefer Reg{Rd|Wt} below */ +#define _VCODEC_IO(x) (* (volatile unsigned long *) (VCODEC_IO_BASE | (x))) + +/* Use these rather than _IO() directly so that it's easy to replace the macros with simulation functions */ +#define RegWt( addr, value ) _VCODEC_IO( addr ) = ( value ) +#define RegRd( addr ) _VCODEC_IO( addr ) + + + +#define RegValFieldGet(RegVal, Reg, Field) ((RegVal & FIELD_ ##Reg ##_ ##Field) >> POS_ ##Reg ##_ ##Field) +#define RegValFieldSetTo(RegVal, Reg, Field, To) ( (RegVal) += -((RegVal)&FIELD_ ##Reg ##_ ##Field) + (To<>30)&0x3)==0) + #define IS_ALIAS_L1_NONALLOCATING(x) ((((unsigned)(x)>>30)&0x3)==1) +#if defined(__BCM2708__) + // HW-2827 workaround + #define IS_ALIAS_L1L2_NONALLOCATING(x) IS_ALIAS_L1_NONALLOCATING(x) +#else + #define IS_ALIAS_L1L2_NONALLOCATING(x) ((((unsigned)(x)>>29)&0x7)==4) // make sure we are not considering peripherals +#endif + #define IS_ALIAS_DIRECT(x) ((((unsigned)(x)>>30)&0x3)==3) + #define IS_ALIAS_NONALLOCATING(x) (((unsigned)(x)>>29)>=3) + #define IS_ALIAS_PERIPHERAL(x) (((unsigned)(x)>>29)==0x3) + #define IS_ALIAS_COHERENT(x) IS_ALIAS_L1L2_NONALLOCATING(x) + #define IS_ALIAS_NOT_L1(p) (IS_ALIAS_L1_NONALLOCATING(p) || IS_ALIAS_NONALLOCATING(p)) + + //number of cores + #define VIDEOCORE_NUM_CORES 2 + + //The size of the stacked SDRAM + #define SDRAM_SIZE (1024 * 1024 * 128) //32MBytes + #define SDRAM_START_ADDRESS 0 //starts at 0 in our memory space + + //The size of the L2 cache + #define L2CACHE_SIZE (1024 * 128) //starts at 0 in our memory space + + //default interrupt vector table base address + #define INTERRUPT_VECTOR_BASE 0 + + //common interrupts + #define INTERRUPT_EXCEPTION_OFFSET 0 + #define INTERRUPT_EXCEPTION_NUM 32 + + #define INTERRUPT_SOFTINT_OFFSET 32 + #define INTERRUPT_SOFTINT_NUM 32 + + #define INTERRUPT_HARDINT_OFFSET 64 + #define INTERRUPT_HARDINT_NUM 64 + + #define MAX_TIMER_NUM 4 + #define MAX_EXCEPTION_NUM 8 + + // In A0 address order (ie RESET_CONTROLLER for B0 is later in the list) + + #define BOOTROM_BASE_ADDRESS 0x60000000 + + #define L2CACHE_BASE L2_BASE + #define I0CACHE_BASE L1_BASE + #define D0CACHE_BASE (L1_BASE+0x100) + + #define SDRAM_BASE_ADDRESS SD_BASE + #define DEBUG_MASTER_BASE NU_BASE + #define ARBITER_CTRL_BASE SYSAC_BASE + #define VPU0_THREAD_CTRL_BASE_ADDRESS 0x18011000 + + + // vc_run APB Bridge - 0x1A00_0000 - 0x1A0F_FFFF + #define RUN_ARBITER_CTRL_BASE_ADDRESS 0x1A003000 + #define V3D_BASE_ADDRESS 0x1A005000 + #define VPU1_THREAD_CTRL_BASE_ADDRESS 0x1A008000 + #define VPU1_UNIFORM_MEM_BASE_ADDRESS 0x1A00A000 + #define V3D_MEM1_BASE_ADDRESS 0x1A00B000 + #define V3D_MEM2_BASE_ADDRESS 0x1A00C000 + #define VIDEOCODEC_BASE_ADDRESS 0x7f000000 + + // peri_audio APB Bridge - 0x7e20_0000 - 0x7E21_FFFF + #define UART_BASE_ADDRESS UART_BASE + #define I2C_BASE_0 I2C0_BASE + #define PIXELVALVE_0_BASE_ADDRESS PIXELVALVE0_BASE + #define PIXELVALVE_1_BASE_ADDRESS PIXELVALVE1_BASE + #define DSI_BASE DSI0_BASE + #define PWM_BASE_ADDRESS PWM_BASE + #define PERFMON_BASE_ADDRESS PRM_BASE +// #define SPI_BASE_ADDRESS SPI_BASE +// #define DSI1_BASE_ADDRESS DSI1_BASE + #define OTP_BASE_ADDRESS OTP_BASE +// #define CPG_BASE_ADDRESS CPG_BASE +// #define TEMP_SENS_BASE_ADDRESS TS_BASE + + + // cprman Audio APB bridge + #define POWERMAN_BASE_ADDRESS PM_BASE + #define RESET_CONTROLLER_BASE RS_BASE + + #define JPEG_BASE JP_BASE + #define TRANSPOSER_BASE_ADDRESS TXP_BASE + //#define CCP2TX_BASE CCP2TX_BASE // definition in ccp2tx.h + + // what to do with these ?? + #define DISPC_BASE_ADDRESS 0x1C009000 + #define CDP_BASE 0x1C00E000 + #define ACIS_BASE_ADDRESS 0x1C004800 + #define ADC_BASE_ADDRESS 0x1C00E000 + + // The AXI bus to the SMI - 0x1C20_0000 - 0x1C2F_FFFF + #define SMI_BASE 0x7E600000 + #define SMI_BASE_DIRECT 0x7E601000 + + // perp run APB bridge + + // peri_image APB Bridge - 0x7e80_0000 - 0x7E81_FFFF + // Camera - now have two Unicam modules at + // CAM 0 : 0x7e800000 (CAM0_BASE) + // CAM 1 : 0x7e801000 (CAM1_BASE) + + #define I2C_BASE_1 I2C1_BASE + #define I2C_BASE_2 I2C2_BASE + #define PIXELVALVE_2_BASE_ADDRESS PIXELVALVE2_BASE + #define VEC_BASE_ADDRESS VEC_BASE + + //interrupt definitions + #define INTERRUPT_HW_NUM (64) + #define INTERRUPT_HW_OFFSET (64) + #define INTERRUPT_SW_OFFSET (32) + #define INTERRUPT_SW_NUM (32) + + #define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 ) + #define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 ) + #define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 ) + #define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 ) + #define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 ) + #define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 ) + #define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 ) + #define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 ) + #define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 ) + #define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 ) + #define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 ) + #define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 ) + #define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 ) + #define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 ) + #define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 ) + #define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 ) + #define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 ) + #define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 ) + #define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 ) + #define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 ) + #define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 ) + #define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 ) + #define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 ) + #define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 ) + #define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 ) +#if defined(__BCM2708A0__) + // A0 only has 9 dma interrupts + //#define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 ) + //#define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 ) + //#define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 ) + //#define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 ) + //#define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 ) + //#define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 ) + //#define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 ) +#else + #define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 ) + #define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 ) + #define INTERRUPT_DMA11_12_13_14 (INTERRUPT_HW_OFFSET + 27 ) + #define INTERRUPT_DMA_ALL (INTERRUPT_HW_OFFSET + 28 ) + #define INTERRUPT_UART_SPI0_SPI1 (INTERRUPT_HW_OFFSET + 29 ) + #define INTERRUPT_AUXIO INTERRUPT_UART_SPI0_SPI1 + #define INTERRUPT_ARM (INTERRUPT_HW_OFFSET + 30 ) + #define INTERRUPT_DMA_VPU (INTERRUPT_HW_OFFSET + 31 ) +#endif + #define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 ) + #define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 ) + #define INTERRUPT_CCP2TX (INTERRUPT_HW_OFFSET + 34 ) + #define INTERRUPT_SDC (INTERRUPT_HW_OFFSET + 35 ) + #define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 ) + #define INTERRUPT_AVE (INTERRUPT_HW_OFFSET + 37 ) + #define INTERRUPT_CAM0 (INTERRUPT_HW_OFFSET + 38 ) + # define INTERRUPT_CCP2 INTERRUPT_CAM0 // backward compatibility + #define INTERRUPT_CAM1 (INTERRUPT_HW_OFFSET + 39 ) + # define INTERRUPT_CSI2 INTERRUPT_CAM1 // backward compatibility + #define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 ) + #define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 ) + #define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 ) + #define INTERRUPT_I2C_SLV (INTERRUPT_HW_OFFSET + 43 ) + #define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 44 ) + #define INTERRUPT_PWA0 (INTERRUPT_HW_OFFSET + 45 ) + #define INTERRUPT_PWA1 (INTERRUPT_HW_OFFSET + 46 ) + #define INTERRUPT_CPR (INTERRUPT_HW_OFFSET + 47 ) + #define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 48 ) + #define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 49 ) + #define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 50 ) + #define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 51 ) + #define INTERRUPT_GPIO3 (INTERRUPT_HW_OFFSET + 52 ) + #define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 ) + #define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 ) + #define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 ) + #define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 ) + #define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 ) + #define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 58 ) + #define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 ) + #define INTERRUPT_CPG (INTERRUPT_HW_OFFSET + 60 ) + #define INTERRUPT_RNG (INTERRUPT_HW_OFFSET + 61 ) +#if defined(__BCM2708A0__) + // FIXME: see middleware/rpc/rpc.c + #define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 ) + #define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 ) +#else + #define INTERRUPT_ASDIO (INTERRUPT_HW_OFFSET + 62 ) + #define INTERRUPT_AVSPMON (INTERRUPT_HW_OFFSET + 63 ) +#endif + #define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 ) + + // aliases + #define INTERRUPT_HOSTINTERFACE INTERRUPT_HOSTPORT + #define INTERRUPT_SDCARDHOST INTERRUPT_SDIO + + + // temporary dummy register definitions to avoid compile errors + #define DUMMYREG HW_REGISTER_RW( 0x7C ) //software exception vector 15 + + /*---------------------------------------------------------------------------*/ + /* TODO FIXME ETC... VCII Clock Manager defs */ + #define CMPREC DUMMYREG + #define CMPRE1 DUMMYREG + #define CMPRE2 DUMMYREG + #define CMPRE3 DUMMYREG + #define CMPLLC DUMMYREG + #define CMPLL1 DUMMYREG + #define CMPLL2 DUMMYREG + #define CMPLL3 DUMMYREG + #define CMCORE DUMMYREG + #define CMCAM DUMMYREG + #define CMLCD DUMMYREG + #define CMACIS DUMMYREG + #define CMPCM DUMMYREG + #define CMUSB DUMMYREG + #define CMGEN DUMMYREG + #define CMMSP DUMMYREG + #define CMUART DUMMYREG + #define CMTIMER DUMMYREG + #define CMUARTF DUMMYREG + #define CMTIMERF DUMMYREG + #define CMNVT DUMMYREG + + /*---------------------------------------------------------------------------*/ + /* Nexus Controller */ + + #define NOWNT HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x4) + #define NIOREQ HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x0) + + /*---------------------------------------------------------------------------*/ + /* Reset Controller */ + +// #define RSTCS HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x0) +// #define RSTWD HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x4) +// #define RSTID HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x8) +// #define RSTFD HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0xc) +// +// #define RSC0ADDR HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x10) + + /*---------------------------------------------------------------------------*/ + /* Scaler hardware registers */ + + #define SCALER_BASE_ADDRESS SCALER_BASE + #define SCALER_INPUT_CONTROL HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x00 ) + #define SCALER_IRQ_STATUS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x04 ) + #define SCALER_ID HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x08 ) + #define SCALER_ALT_CONTROL HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x0C ) + #define SCALER_PROFILE HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x10 ) + #define SCALER_DITHER HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x14 ) + //#define SCALER_DISPEOLN HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x18 ) + + #define SCALER_DISP_LIST_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x20 ) + #define SCALER_DISP_LIST_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x24 ) + #define SCALER_DISP_LIST_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x28 ) + #define SCALER_DISP_LIST_STATUS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x2C ) + + #define SCALER_DISPCTL_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x40 ) + #define SCALER_DISPBKGND_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x44 ) + #define SCALER_DISPSTAT_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x48 ) + + #define SCALER_DISPCTL_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x50 ) + #define SCALER_DISPBKGND_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x54 ) + #define SCALER_DISPSTAT_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x58 ) + #define SCALER_DISPBASE_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x5C ) + + #define SCALER_DISPCTL_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x60 ) + #define SCALER_DISPBKGND_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x64 ) + #define SCALER_DISPSTAT_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x68 ) + #define SCALER_DISPBASE_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x6C ) + + #define SCALER_GAM_ADDRESS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x78 ) + #define SCALER_GAM_DATA HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xE0 ) + + //#define SCALER_DISPSLAVE0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xC0 ) + //#define SCALER_DISPSLAVE1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xC8 ) + //#define SCALER_DISPSLAVE2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xD0 ) + + //the start location of the scalers context memory + #define SCALER_CONTEXT_MEMORY_START (SCALER_BASE_ADDRESS + 0x2000) + + #define SCALER_CONTEXT_MEM_SIZE ( 1024 * 16 ) //16k + + //the size of the line buffer memory + #define SCALER_LINE_BUFFER_MEM_SIZE (94 * 1024) + + //The size of the COB buffer (the output fifo) in pixels + #define SCALER_COB_FIFO_SIZE (0x4000) //16Kpix == 48kBytes + + /*---------------------------------------------------------------------------*/ + /* PWM */ + #define PWMCTL HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x00 ) + #define PWMSTA HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x04 ) + #define PWMDMAC HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x08 ) + #define PWMRNG1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10 ) + #define PWMDAT1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x14 ) + #define PWMFIF1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x18 ) + #define PWMRNG2 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x20 ) + #define PWMDAT2 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x24 ) + #define PWMRNG3 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x30 ) + #define PWMDAT3 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x34 ) + #define PWMRNG4 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x40 ) + #define PWMDAT4 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x44 ) + + #define PWMRNG(n) HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10*n ) // n=1,2,3,4 + #define PWMDAT(n) HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10*n + 4 ) + + #define PWMCTL_PWEN1 0 + #define PWMCTL_MODE1 1 + #define PWMCTL_RPTL1 2 + #define PWMCTL_SBIT1 3 + #define PWMCTL_POLA1 4 + #define PWMCTL_USEF1 5 + #define PWMCTL_CLRF1 6 + #define PWMCTL_MSEN1 7 + #define PWMCTL_PWEN2 8 + #define PWMCTL_MODE2 9 + #define PWMCTL_RPTL2 10 + #define PWMCTL_SBIT2 11 + #define PWMCTL_POLA2 12 + #define PWMCTL_USEF2 13 + #define PWMCTL_MSEN2 15 + #define PWMCTL_PWEN3 16 + #define PWMCTL_MODE3 17 + #define PWMCTL_RPTL3 18 + #define PWMCTL_SBIT3 19 + #define PWMCTL_POLA3 20 + #define PWMCTL_USEF3 21 + #define PWMCTL_MSEN3 23 + #define PWMCTL_PWEN4 24 + #define PWMCTL_MODE4 25 + #define PWMCTL_RPTL4 26 + #define PWMCTL_SBIT4 27 + #define PWMCTL_POLA4 28 + #define PWMCTL_USEF4 29 + #define PWMCTL_MSEN4 31 + #define PWMCTL_PWEN(n) (((n-1)<<3)+0) // n=1,2,3,4 + #define PWMCTL_MODE(n) (((n-1)<<3)+1) + #define PWMCTL_RPTL(n) (((n-1)<<3)+2) + #define PWMCTL_SBIT(n) (((n-1)<<3)+3) + #define PWMCTL_POLA(n) (((n-1)<<3)+4) + #define PWMCTL_USEF(n) (((n-1)<<3)+5) + #define PWMCTL_MSEN(n) (((n-1)<<3)+7) + + #define PWMSTA_FULL1 0 + #define PWMSTA_EMPT1 1 + #define PWMSTA_WERR1 2 + #define PWMSTA_RERR1 3 + #define PWMSTA_GAPO1 4 + #define PWMSTA_GAPO2 5 + #define PWMSTA_GAPO3 6 + #define PWMSTA_GAPO4 7 + #define PWMSTA_BERR 8 + #define PWMSTA_STA1 9 + #define PWMSTA_STA2 10 + #define PWMSTA_STA3 11 + #define PWMSTA_STA4 12 + + #define PWMDMAC_DREQ_LEN 8 + #define PWMDMAC_DREQ 0 + #define PWMDMAC_PANIC_LEN 8 + #define PWMDMAC_PANIC 8 + #define PWMDMAC_ENAB 31 + + /*---------------------------------------------------------------------------*/ + /* Transposer */ + + #define TRANSPOSER_DST_PTR HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x00 ) + #define TRANSPOSER_DST_PITCH HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x04 ) + #define TRANSPOSER_DIMENSIONS HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x08 ) + #define TRANSPOSER_CONTROL HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x0C ) + #define TRANSPOSER_PROGRESS HW_REGISTER_RO( TRANSPOSER_BASE_ADDRESS + 0x10 ) + + /*---------------------------------------------------------------------------*/ + /* Video Codec */ + + #define VCSIGNAL0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408b4) + #define VCINTMASK0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408b8) + #define VCSIGNAL1 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408bc) + #define VCINTMASK1 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408c0) +#ifndef VCODEC_VERSION + // Set default to old A0 version + #define VCODEC_VERSION 821 +#endif + +#if (VCODEC_VERSION>=800) + + #define VCE_BASE 0x7f100000 + #define VCE_DATA_MEM_OFFSET 0 + #define VCE_DATA_MEM_SIZE 0x2000 + #define VCE_PROGRAM_MEM_OFFSET 0x10000 + #define VCE_PROGRAM_MEM_SIZE 0x4000 + #define VCE_REGISTERS_OFFSET 0x20000 + #define VCE_REGISTERS_COUNT 63 + #define VCE_STATUS_OFFSET 0x40000 + #define VCE_STATUS_BUSYBITS_MASK 0xffff + #define VCE_STATUS_REASON_POS 16 + #define VCE_STATUS_REASON_MASK 0x1f + #define VCE_BUSY_BKPT 0x00 + #define VCE_BUSY_USER 0x01 // up to 0x07 inclusive + #define VCE_BUSY_DMAIN 0x08 + #define VCE_BUSY_DMAOUT 0x09 + #define VCE_BUSY_MEMSYNC 0x0a + #define VCE_BUSY_SLEEP 0x0b + #define VCE_REASON_STOPPED 0x10 + #define VCE_REASON_RUNNING 0x11 + #define VCE_REASON_RESET 0x12 + #define VCE_REASON_SINGLE 0x13 + #define VCE_STATUS_RUNNING_POS 24 + #define VCE_STATUS_NANOFLAG_POS 25 + #define VCE_STATUS_INTERRUPT_POS 31 + #define VCE_VERSION_OFFSET 0x40004 + #define VCE_PC_PF0_OFFSET 0x40008 + #define VCE_PC_IF0_OFFSET 0x4000c + #define VCE_PC_RD0_OFFSET 0x40010 + #define VCE_PC_EX0_OFFSET 0x40014 + #define VCE_CONTROL_OFFSET 0x40020 + #define VCE_CONTROL_CLEAR_RUN 0 + #define VCE_CONTROL_SET_RUN 1 + #define VCE_CONTROL_SINGLE_STEP 3 + #define VCE_BAD_ADDR_OFFSET 0x40030 + #define VCE_SEMA_CLEAR_OFFSET 0x40024 + #define VCE_SEMA_SET_OFFSET 0x40028 + #define VCE_SEMA_COUNT 8 + #define VCE_SIM_DEBUG_OPTIONS_OFFSET 0x40100 + + #define VCE_DATA_MEM_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x100000) + #define VCE_PROGRAM_MEM_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110000) + #define VCE_REGISTERS_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x120000) + #define VCE_STATUS HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140000) + #define VCE_VERSION HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140004) + #define VCE_PC_PF0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140008) + #define VCE_PC_IF0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x14000C) + #define VCE_PC_RD0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140010) + #define VCE_PC_EX0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140014) + #define VCE_CONTROL HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140020) + #define VCE_SEMA_CLEAR HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140024) + #define VCE_SEMA_SET HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140028) + #define VCE_BAD_ADDR HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140030) + #define VCE_SIM_DEBUG_OPTIONS HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140100) + +#else + #define PP_PC HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110000) + #define PP_CNTL HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110004) + #define PP_ACC HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110008) +#endif + + /*---------------------------------------------------------------------------*/ + /* DSI */ + + // Define some macros for compatability with old VCIII code which does not + // know about more than one dsi peripheral. Just direct it to DSI0... + #define DSI_CTRL HW_REGISTER_RW( DSI_BASE + 0x00 ) + #define DSI_CMD_PKTC HW_REGISTER_RW( DSI_BASE + 0x04 ) + #define DSI_CMD_PKTH HW_REGISTER_RW( DSI_BASE + 0x08 ) + #define DSI_RX1_PKTH HW_REGISTER_RW( DSI_BASE + 0x0C ) + #define DSI_RX2_PKTH HW_REGISTER_RW( DSI_BASE + 0x10 ) + #define DSI_CMD_DATA_FIFO HW_REGISTER_RW( DSI_BASE + 0x14 ) + #define DSI_DISP0_CTRL HW_REGISTER_RW( DSI_BASE + 0x18 ) + #define DSI_DISP1_CTRL HW_REGISTER_RW( DSI_BASE + 0x1C ) + #define DSI_PIX_FIFO HW_REGISTER_RW( DSI_BASE + 0x20 ) + #define DSI_INT_STATUS HW_REGISTER_RW( DSI_BASE + 0x24 ) + #define DSI_INT_ENABLE HW_REGISTER_RW( DSI_BASE + 0x28 ) + #define DSI_STAT HW_REGISTER_RW( DSI_BASE + 0x2C ) + #define DSI_HSTX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x30 ) + #define DSI_LPRX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x34 ) + #define DSI_TA_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x38 ) + #define DSI_PR_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x3C ) + #define DSI_PHY_CONTROL HW_REGISTER_RW( DSI_BASE + 0x40 ) + // HSCLKZERO, HSCLKPRE, HSCLKPREP + #define DSI_HS_CLT0 HW_REGISTER_RW( DSI_BASE + 0x44 ) + // HSCLKTRAIL, HSCLKPOST + #define DSI_HS_CLT1 HW_REGISTER_RW( DSI_BASE + 0x48 ) + // HSWAKEUP + #define DSI_HS_CLT2 HW_REGISTER_RW( DSI_BASE + 0x4C ) + // HS EXIT, ZERO, PRE + #define DSI_HS_DLT3 HW_REGISTER_RW( DSI_BASE + 0x50 ) + // HS TRAIL LPX + #define DSI_HS_DLT4 HW_REGISTER_RW( DSI_BASE + 0x54 ) + // HS INIT + #define DSI_HS_DLT5 HW_REGISTER_RW( DSI_BASE + 0x58 ) + // lp GET SURE GO LPX + #define DSI_LP_DLT6 HW_REGISTER_RW( DSI_BASE + 0x5C ) + // LP WAKEUP + #define DSI_LP_DLT7 HW_REGISTER_RW( DSI_BASE + 0x60 ) + #define DSI_AFEC0 HW_REGISTER_RW( DSI_BASE + 0x64 ) + #define DSI_AFEC1 HW_REGISTER_RW( DSI_BASE + 0x68 ) + #define DSI_TST_SEL HW_REGISTER_RW( DSI_BASE + 0x6C ) + #define DSI_TST_MON HW_REGISTER_RW( DSI_BASE + 0x70 ) + + /*---------------------------------------------------------------------------*/ + /* CDP */ + + #define CDPC HW_REGISTER_RW( CDP_BASE + 0x00 ) + #define CDP_PHYC HW_REGISTER_RW( CDP_BASE + 0x04 ) + #define CDP_PHYTSTDAT HW_REGISTER_RW( CDP_BASE + 0x08 ) + #define CDP_DEBUG0 HW_REGISTER_RW( CDP_BASE + 0x0C ) + #define CDP_DEBUG1 HW_REGISTER_RW( CDP_BASE + 0x10 ) + + /*---------------------------------------------------------------------------*/ + /* BootROM Peripheral */ + + #define BOOTROM_ROM_START ( BOOTROM_BASE_ADDRESS + 0x0 ) //Start of the ROM + #define BOOTROM_ROM_LENGTH ( 1024 * 32 ) // Length of the Boot ROM + + #define BOOTROM_RAM_START ( BOOTROM_BASE_ADDRESS + 0x8000 ) //Start of the RAM + #define BOOTROM_RAM_LENGTH ( 1024 * 2 ) // Length of the Boot RAM + + #define BOOTROM_BRCTL HW_REGISTER_RW( BOOTROM_BASE_ADDRESS + 0xC000 ) + + /*---------------------------------------------------------------------------*/ + /* Unicam Peripheral */ + #define UNICAM_REG( x, d ) HW_REGISTER_RW( (((x) == 0) ? CAM0_BASE : CAM1_BASE) + d ) + +#if defined(__BCM2708A0__) + #define UNICAM_CTRL( x ) UNICAM_REG( x, 0x000 ) + #define UNICAM_STA( x ) UNICAM_REG( x, 0x004 ) + #define UNICAM_ANA( x ) UNICAM_REG( x, 0x008 ) + #define UNICAM_PRI( x ) UNICAM_REG( x, 0x00c ) + #define UNICAM_CLK( x ) UNICAM_REG( x, 0x010 ) + #define UNICAM_DAT0( x ) UNICAM_REG( x, 0x014 ) + #define UNICAM_DAT1( x ) UNICAM_REG( x, 0x018 ) + #define UNICAM_DAT2( x ) UNICAM_REG( x, 0x01c ) + #define UNICAM_DAT3( x ) UNICAM_REG( x, 0x020 ) + #define UNICAM_CMP0( x ) UNICAM_REG( x, 0x024 ) + #define UNICAM_CMP1( x ) UNICAM_REG( x, 0x028 ) + #define UNICAM_CAP0( x ) UNICAM_REG( x, 0x02c ) + #define UNICAM_CAP1( x ) UNICAM_REG( x, 0x030 ) + #define UNICAM_DBG0( x ) UNICAM_REG( x, 0x0f0 ) + #define UNICAM_DBG1( x ) UNICAM_REG( x, 0x0f4 ) + #define UNICAM_DBG2( x ) UNICAM_REG( x, 0x0f8 ) + #define UNICAM_ICTL( x ) UNICAM_REG( x, 0x100 ) + #define UNICAM_ISTA( x ) UNICAM_REG( x, 0x104 ) + #define UNICAM_IDI( x ) UNICAM_REG( x, 0x108 ) + #define UNICAM_IPIPE( x ) UNICAM_REG( x, 0x10c ) + #define UNICAM_IBSA( x ) UNICAM_REG( x, 0x110 ) + #define UNICAM_IBEA( x ) UNICAM_REG( x, 0x114 ) + #define UNICAM_IBLS( x ) UNICAM_REG( x, 0x118 ) + #define UNICAM_IBWP( x ) UNICAM_REG( x, 0x11c ) + #define UNICAM_IHWIN( x ) UNICAM_REG( x, 0x120 ) + #define UNICAM_IHSTA( x ) UNICAM_REG( x, 0x124 ) + #define UNICAM_IVWIN( x ) UNICAM_REG( x, 0x128 ) + #define UNICAM_IVSTA( x ) UNICAM_REG( x, 0x12c ) + #define UNICAM_DCS( x ) UNICAM_REG( x, 0x200 ) + #define UNICAM_DBSA( x ) UNICAM_REG( x, 0x204 ) + #define UNICAM_DBEA( x ) UNICAM_REG( x, 0x208 ) + #define UNICAM_DBWP( x ) UNICAM_REG( x, 0x20c ) +#else + #define UNICAM_CTRL( x ) UNICAM_REG( x, 0x000 ) + #define UNICAM_STA( x ) UNICAM_REG( x, 0x004 ) + #define UNICAM_ANA( x ) UNICAM_REG( x, 0x008 ) + #define UNICAM_PRI( x ) UNICAM_REG( x, 0x00c ) + #define UNICAM_CLK( x ) UNICAM_REG( x, 0x010 ) + #define UNICAM_CLT( x ) UNICAM_REG( x, 0x014 ) + #define UNICAM_DAT0( x ) UNICAM_REG( x, 0x018 ) + #define UNICAM_DAT1( x ) UNICAM_REG( x, 0x01c ) + #define UNICAM_DAT2( x ) UNICAM_REG( x, 0x020 ) + #define UNICAM_DAT3( x ) UNICAM_REG( x, 0x024 ) + #define UNICAM_DLT( x ) UNICAM_REG( x, 0x028 ) + #define UNICAM_CMP0( x ) UNICAM_REG( x, 0x02c ) + #define UNICAM_CMP1( x ) UNICAM_REG( x, 0x030 ) + #define UNICAM_CAP0( x ) UNICAM_REG( x, 0x034 ) + #define UNICAM_CAP1( x ) UNICAM_REG( x, 0x038 ) + #define UNICAM_ICTL( x ) UNICAM_REG( x, 0x100 ) + #define UNICAM_ISTA( x ) UNICAM_REG( x, 0x104 ) + #define UNICAM_IDI0( x ) UNICAM_REG( x, 0x108 ) + #define UNICAM_IPIPE( x ) UNICAM_REG( x, 0x10c ) + #define UNICAM_IBSA0( x ) UNICAM_REG( x, 0x110 ) + #define UNICAM_IBEA0( x ) UNICAM_REG( x, 0x114 ) + #define UNICAM_IBLS( x ) UNICAM_REG( x, 0x118 ) + #define UNICAM_IBWP( x ) UNICAM_REG( x, 0x11c ) + #define UNICAM_IHWIN( x ) UNICAM_REG( x, 0x120 ) + #define UNICAM_IHSTA( x ) UNICAM_REG( x, 0x124 ) + #define UNICAM_IVWIN( x ) UNICAM_REG( x, 0x128 ) + #define UNICAM_IVSTA( x ) UNICAM_REG( x, 0x12c ) + #define UNICAM_ICC( x ) UNICAM_REG( x, 0x130 ) + #define UNICAM_ICS( x ) UNICAM_REG( x, 0x134 ) + #define UNICAM_IDC( x ) UNICAM_REG( x, 0x138 ) + #define UNICAM_IDPO( x ) UNICAM_REG( x, 0x13c ) + #define UNICAM_IDCA( x ) UNICAM_REG( x, 0x140 ) + #define UNICAM_IDCD( x ) UNICAM_REG( x, 0x144 ) + #define UNICAM_IDS( x ) UNICAM_REG( x, 0x148 ) + #define UNICAM_DCS( x ) UNICAM_REG( x, 0x200 ) + #define UNICAM_DBSA0( x ) UNICAM_REG( x, 0x204 ) + #define UNICAM_DBEA0( x ) UNICAM_REG( x, 0x208 ) + #define UNICAM_DBWP( x ) UNICAM_REG( x, 0x20c ) + #define UNICAM_DBCTL( x ) UNICAM_REG( x, 0x300 ) + #define UNICAM_IBSA1( x ) UNICAM_REG( x, 0x304 ) + #define UNICAM_IBEA1( x ) UNICAM_REG( x, 0x308 ) + #define UNICAM_IDI1( x ) UNICAM_REG( x, 0x30c ) + #define UNICAM_DBSA1( x ) UNICAM_REG( x, 0x310 ) + #define UNICAM_DBEA1( x ) UNICAM_REG( x, 0x314 ) + #define UNICAM_MISC( x ) UNICAM_REG( x, 0x400 ) +#endif + + /*---------------------------------------------------------------------------*/ + /* CCP2TX Peripheral - now from ccp2tx[_a0].h */ + #define CCP2TC CCP2TX_TC + #define CCP2TS CCP2TX_TS +#ifndef __BCM2708A0__ + #define CCP2TAC CCP2TX_TAC +#endif + #define CCP2TPC CCP2TX_TPC + #define CCP2TSC CCP2TX_TSC + #define CCP2TIC CCP2TX_TIC + #define CCP2TTC CCP2TX_TTC + #define CCP2TBA CCP2TX_TBA + #define CCP2TDL CCP2TX_TDL + #define CCP2TD CCP2TX_TD +#ifndef __BCM2708A0__ + #define CCP2TSPARE CCP2TX_TSPARE +#endif + + /*---------------------------------------------------------------------------*/ + /* VEC Peripheral */ + + #define WSE_RESET VEC_WSE_RESET + #define WSE_CONTROL VEC_WSE_CONTROL + #define WSE_WSS_DATA VEC_WSE_WSS_DATA + #define WSE_VPS_DATA_1 VEC_WSE_VPS_DATA_1 + #define WSE_VPS_CONTROL VEC_WSE_VPS_CONTROL + + #define CGMSAE_RESET VEC_CGMSAE_RESET + #define CGMSAE_TOP_CONTROL VEC_CGMSAE_TOP_CONTROL + #define CGMSAE_BOT_CONTROL VEC_CGMSAE_BOT_CONTROL + #define CGMSAE_TOP_FORMAT VEC_CGMSAE_TOP_FORMAT + #define CGMSAE_BOT_FORMAT VEC_CGMSAE_BOT_FORMAT + #define CGMSAE_TOP_DATA VEC_CGMSAE_TOP_DATA + #define CGMSAE_BOT_DATA VEC_CGMSAE_BOT_DATA + #define CGMSAE_REVID VEC_CGMSAE_REVID + + /*---------------------------------------------------------------------------*/ + /* System Timer */ + + // The old register names are used all over the place, so we probably need to + // keep these for now. + // These also appear in systimer.h; ideally, any modules which access these + // registers directly should #include that header file. +#if 1 // TODO: remove these one day. + #define STCS_0 ST_CS + #define STC_0 ST_CLO + #define STCLO_0 ST_CLO + #define STCHI_0 ST_CHI + #define STC0_0 ST_C0 + #define STC1_0 ST_C1 + #define STC2_0 ST_C2 + #define STC3_0 ST_C3 + + #define STCS ST_CS + #define STC ST_CLO + #define STCLO ST_CLO + #define STCHI ST_CHI + #define STC0 ST_C0 + #define STC1 ST_C1 + #define STC2 ST_C2 + #define STC3 ST_C3 +#endif + /*---------------------------------------------------------------------------*/ + /* Crypto/ID module */ + #define IDCLVWMCU HW_REGISTER_RW(0x10002000) + #define IDCMDIDU HW_REGISTER_RW(0x10002004) + #define IDCKEYHU HW_REGISTER_RW(0x10002008) + #define IDCKEYLU HW_REGISTER_RW(0x1000200C) + #define IDCCMD HW_REGISTER_RW(0x10002010) + #define IDCCFG HW_REGISTER_RW(0x10002014) + #define IDCKSEL HW_REGISTER_RW(0x10002018) + #define IDCLVWMC HW_REGISTER_RW(0x10002020) + #define IDCMDID HW_REGISTER_RW(0x10002024) + + /*---------------------------------------------------------------------------*/ + /* Single 16550 UART */ + #define URBR HW_REGISTER_RO(UART_BASE + 0x00) + #define UTHR HW_REGISTER_RW(UART_BASE + 0x00) + #define UIER HW_REGISTER_RW(UART_BASE + 0x04) + #define UIIR HW_REGISTER_RO(UART_BASE + 0x08) + #define UFCR HW_REGISTER_RW(UART_BASE + 0x08) + #define ULCR HW_REGISTER_RW(UART_BASE + 0x0C) + #define UMCR HW_REGISTER_RW(UART_BASE + 0x10) + #define ULSR HW_REGISTER_RW(UART_BASE + 0x14) + #define UMSR HW_REGISTER_RW(UART_BASE + 0x18) + #define USCR HW_REGISTER_RW(UART_BASE + 0x1C) + #define UDLL HW_REGISTER_RW(UART_BASE + 0x00) + #define UDLM HW_REGISTER_RW(UART_BASE + 0x04) + #define UEN HW_REGISTER_RW(UART_BASE + 0x20) + + #define VIDEOCORE_NUM_UART_PORTS 1 + + /*---------------------------------------------------------------------------*/ + /* ADC */ + #define ADCCS HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x00) + #define ADCR0 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x04) + #define ADCR1 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x08) + + /*---------------------------------------------------------------------------*/ + /* General Purpose I/O */ + + //Max num of pins in the chip + #define GPIO_MAX_PINS 54 + + /*---------------------------------------------------------------------------*/ + /* JPEG block */ + #define JCTRL HW_REGISTER_RW(JPEG_BASE + 0) + #define JICST HW_REGISTER_RW(JPEG_BASE + 0x4) + #define JMCTRL HW_REGISTER_RW(JPEG_BASE + 0x8) + #define JDCCTRL HW_REGISTER_RW(JPEG_BASE + 0x0C) + #define JCBA HW_REGISTER_RW(JPEG_BASE + 0x10) + #define JNCB HW_REGISTER_RW(JPEG_BASE + 0x14) + #define JSDA HW_REGISTER_RW(JPEG_BASE + 0x18) + #define JNSB HW_REGISTER_RW(JPEG_BASE + 0x1C) + #define JSBO HW_REGISTER_RW(JPEG_BASE + 0x20) + #define JMOP HW_REGISTER_RW(JPEG_BASE + 0x24) + #define JHADDR HW_REGISTER_RW(JPEG_BASE + 0x28) + #define JHWDATA HW_REGISTER_RW(JPEG_BASE + 0x2C) + #define JMADDR HW_REGISTER_RW(JPEG_BASE + 0x30) + #define JMWDATA HW_REGISTER_RW(JPEG_BASE + 0x34) + #define JOADDR HW_REGISTER_RW(JPEG_BASE + 0x38) + #define JOWDATA HW_REGISTER_RW(JPEG_BASE + 0x3C) + #define JQADDR HW_REGISTER_RW(JPEG_BASE + 0x40) + #define JQWDATA HW_REGISTER_RW(JPEG_BASE + 0x44) + #define JQCTRL HW_REGISTER_RW(JPEG_BASE + 0x48) + #define JC0BA HW_REGISTER_RW(JPEG_BASE + 0x4C) + #define JC1BA HW_REGISTER_RW(JPEG_BASE + 0x50) + #define JC2BA HW_REGISTER_RW(JPEG_BASE + 0x54) + #define JC0S HW_REGISTER_RW(JPEG_BASE + 0x58) + #define JC1S HW_REGISTER_RW(JPEG_BASE + 0x5C) + #define JC2S HW_REGISTER_RW(JPEG_BASE + 0x60) + #define JC0W HW_REGISTER_RW(JPEG_BASE + 0x64) + #define JC1W HW_REGISTER_RW(JPEG_BASE + 0x68) + #define JC2W HW_REGISTER_RW(JPEG_BASE + 0x6C) + + #define JCTRL_START (1 << 7) + #define JCTRL_DCTEN (1 << 4) + #define JCTRL_RESET (1 << 3) + #define JCTRL_FLUSH (1 << 2) + #define JCTRL_STUFF (1 << 1) + #define JCTRL_MODE (1 << 0) + + #define JHADDR_TABLEF (1 << 31) + + #define JICST_ERR (1 << 19) + #define JICST_MARKER (1 << 18) + #define JICST_SDONE (1 << 17) + #define JICST_CDONE (1 << 16) + #define JICST_INTE (1 << 3) + #define JICST_INTM (1 << 2) + #define JICST_INTSD (1 << 1) + #define JICST_INTCD (1 << 0) + + #define JDCCTRL_DISDC (1 << 20) + #define JDCCTRL_SETDC(n) (1 << ((n) + 16)) + #define JDCCTRL_DCCOMP_MASK 0xFFFF + + #define JMCTRL_DC_TAB(n) (1 << (2*(n))) + #define JMCTRL_AC_TAB(n) (1 << (2*(n)+1)) + #define JMCTRL_NUMCMP (1 << 8) + #define JMCTRL_CMP(n) (1 << (4*(n) + 16)) + #define JMCTRL_420_MODE (0 << 14) + #define JMCTRL_422_MODE (1 << 14) + #define JMCTRL_444_MODE (2 << 14) + + #define JMCTRL_UNUSED_BITS ((1 << 13) | (1 << 12) | (1 << 11)) + + #define AC_HUFFTABLE_OFFSET(t) ((t) * 0x100) + #define DC_HUFFTABLE_OFFSET(t) ((t) * 0x10 + 0x200) + + #define AC_OSETTABLE_OFFSET(t) ((t) * 0x10) + #define DC_OSETTABLE_OFFSET(t) ((t) * 0x10 + 0x20) + + #define AC_MAXCTABLE_OFFSET(t) ((t) * 0x10) + #define DC_MAXCTABLE_OFFSET(t) ((t) * 0x10 + 0x20) + + /*---------------------------------------------------------------------------*/ + /* External Memory Interface */ + #define SDCS HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x00) + #define SDSA HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x04) + #define SDSB HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x08) + #define SDSC HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x0C) + #define SDEM HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x10) + #define SDPT HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x14) + #define SDIDL HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x18) + #define SDRTC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x1C) + #define SDWTC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x20) + #define SDRDC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x24) + #define SDWDC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x28) + #define SDRAC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x2C) + #define SDCYC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x30) + #define SDACC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x34) + #define SDDAT HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x38) + #define SDSECSRT0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x3C) + #define SDSECEND0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x40) + #define SDSECSRT1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x44) + #define SDSECEND1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x48) + #define SDSECSRT2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x4C) + #define SDSECEND2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x50) + #define SDSECSRT3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x54) + #define SDSECEND3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x58) + #define SDDELC0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x5C) + #define SDDELS0 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x60) + #define SDDELC1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x64) + #define SDDELS1 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x68) + #define SDDELC2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x6C) + #define SDDELS2 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x70) + #define SDDELC3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x74) + #define SDDELS3 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x78) + #define SDTMC HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x7C) + + + /*---------------------------------------------------------------------------*/ + /* Secondary Memory Interface */ + + #define SMICS HW_REGISTER_RW(SMI_BASE + 0x00) + #define SMIL HW_REGISTER_RW(SMI_BASE + 0x04) + #define SMIA HW_REGISTER_RW(SMI_BASE + 0x08) + #define SMID HW_REGISTER_RW(SMI_BASE + 0x0C) + #define SMIDSR0 HW_REGISTER_RW(SMI_BASE + 0x10) + #define SMIDSW0 HW_REGISTER_RW(SMI_BASE + 0x14) + #define SMIDSR1 HW_REGISTER_RW(SMI_BASE + 0x18) + #define SMIDSW1 HW_REGISTER_RW(SMI_BASE + 0x1C) + #define SMIDSR2 HW_REGISTER_RW(SMI_BASE + 0x20) + #define SMIDSW2 HW_REGISTER_RW(SMI_BASE + 0x24) + #define SMIDSR3 HW_REGISTER_RW(SMI_BASE + 0x28) + #define SMIDSW3 HW_REGISTER_RW(SMI_BASE + 0x2C) + #define SMIDC HW_REGISTER_RW(SMI_BASE + 0x30) + #define SMIDCS HW_REGISTER_RW(SMI_BASE + 0x34) + #define SMIDA HW_REGISTER_RW(SMI_BASE + 0x38) + #define SMIDD HW_REGISTER_RW(SMI_BASE + 0x3C) + #define SMIFD HW_REGISTER_RW(SMI_BASE + 0x40) + + #define SMI_FIFO_ADDRESS(device,addr) (((((device))&0x3)<<8)|((addr)&0xff)) + + // SMI control register bits + #define SMICS_ENABLE 0 + #define SMICS_DONE 1 + #define SMICS_ACTIVE 2 + #define SMICS_START 3 + #define SMICS_CLEARFIFO 4 + #define SMICS_WRITE 5 + #define SMICS_PAD 6 + #define SMICS_TEEN 8 + #define SMICS_INTD 9 + #define SMICS_INTT 10 + #define SMICS_INTR 11 + #define SMICS_PVMODE 12 + #define SMICS_SETERR 13 + #define SMICS_PXLDAT 14 + #define SMICS_EDREQ 15 + #define SMICS_AFERR 25 + #define SMICS_TXW 26 + #define SMICS_RXR 27 + #define SMICS_TXD 28 + #define SMICS_RXD 29 + #define SMICS_TXE 30 + #define SMICS_RXF 31 + + // SMI address and direct address register bits. + #define SMIA_DEVICE 8 + #define SMIDA_DEVICE 8 + + // SMI DSR* and DSW* common fields + #define SMIDS_STROBE 0 + #define SMIDS_DREQ 7 + #define SMIDS_PACE 8 + #define SMIDS_PACEALL 15 + #define SMIDS_HOLD 16 + #define SMIDS_SETUP 24 + #define SMIDS_WIDTH 30 + // SMI DSR* register specific + #define SMIDS_FSETUP 22 + #define SMIDS_MODE68 23 + // SMI DSW* register specific + #define SMIDS_SWAP 22 + #define SMIDS_FORMAT 23 + + // SMI direct control/status register bits. + #define SMIDCS_ENABLE 0 + #define SMIDCS_START 1 + #define SMIDCS_DONE 2 + #define SMIDCS_WRITE 3 + + // SMI dma control threshold register bits. + #define SMIDC_REQW 0 + #define SMIDC_REQR 6 + #define SMIDC_PANICW 12 + #define SMIDC_PANICR 18 + #define SMIDC_DMAP 24 + #define SMIDC_DMAEN 28 + + // SMI FIFO debug + #define SMIFD_FCNT 0 + #define SMIFD_FLVL 8 + + /*---------------------------------------------------------------------------*/ + /* AC'97/I2S Controller */ + #define ACISCS HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x00 ) + #define ACISFIFO HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x04 ) + #define ACISCA HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x08 ) + #define ACISCD HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x0C ) + #define ACISMODE HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x10 ) + #define ACISASR HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x14 ) + + #define ACPLAYRATE 0x2c + #define ACRECORDRATE 0x32 + + /*---------------------------------------------------------------------------*/ + /* SLIMbus interface */ + #define SLIM_NUM_DCC 10 /* there are 10 data channel controllers */ + #define SLIM_DCC_BASE(n) (SLIM_BASE + 0x200 + (n) * 0x20) + #define SLIM_DCC_PA0(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x00) + #define SLIM_DCC_PA1(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x04) + #define SLIM_DCC_CON(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x08) + #define SLIM_DCC_STAT(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x0c) + +#if defined(__BCM2708A0__) + // backward compatibility for drivers that use B0 register definitions + #define SLIM_MC_IN_CON SLIM_SMC_IN_CON + #define SLIM_MC_OUT_CON SLIM_SMC_OUT_CON + #define SLIM_MC_IN_STAT SLIM_SMC_IN_STAT + #define SLIM_MC_OUT_STAT SLIM_SMC_OUT_STAT + #define SLIM_DMA_MC_TX SLIM_DMA_SMC_TX + #define SLIM_DMA_MC_RX SLIM_DMA_SMC_RX +#endif + + /*---------------------------------------------------------------------------*/ + /* USB Peripheral */ + #define USB_DIEPINT_off(n) HW_REGISTER_RW(&USB_DIEPINT+(n*0x20)) + #define USB_HCINT_off(n) HW_REGISTER_RW(&USB_HCINT+(n*0x20)) + + #define USB_DFIFOn(n) HW_REGISTER_RW(USB_BASE+0x1000+(n*0x1000)) + #define USB_DIEPCTLn(n) HW_REGISTER_RW(USB_BASE+0x0900+(n*0x20)) + #define USB_DIEPTSIZn(n) HW_REGISTER_RW(USB_BASE+0x0910+(n*0x20)) + #define USB_DIEPDMAn(n) HW_REGISTER_RW(USB_BASE+0x0914+(n*0x20)) + #define USB_DTXFSTSn(n) HW_REGISTER_RW(USB_BASE+0x0918+(n*0x20)) + + #define USB_MDIO_CSR HW_REGISTER_RW( USB_BASE + 0x80 ) + #define USB_MDIO_GEN HW_REGISTER_RW( USB_BASE + 0x84 ) + #define USB_VBUS_DRV HW_REGISTER_RW( USB_BASE + 0x88 ) + #define USB_VBUS_DRV_SESSEND (1<<0) + #define USB_VBUS_DRV_VBUSVALID (1<<1) + #define USB_VBUS_DRV_BVALID (1<<2) + #define USB_VBUS_DRV_AVALID (1<<3) + #define USB_VBUS_DRV_DRVVBUS (1<<4) + #define USB_VBUS_DRV_CHRGVBUS (1<<5) + #define USB_VBUS_DRV_DISCHRGVBUS (1<<6) + + /*---------------------------------------------------------------------------*/ + /* PCM Controller */ + #define PCMCS PCM_CS_A + //#define PCMFIFO PCM_FIFO_A erroneously defined as _RO in bcm2708_chip/pcm.h + #define PCMFIFO HW_REGISTER_RW( PCM_BASE + 0x04 ) + #define PCMMODE PCM_MODE_A + #define PCMRXC PCM_RXC_A + #define PCMTXC PCM_TXC_A + #define PCMDREQ HW_REGISTER_RW( PCM_BASE + 0x14 ) + #define PCMINTEN HW_REGISTER_RW( PCM_BASE + 0x18 ) + #define PCMINTSTC HW_REGISTER_RW( PCM_BASE + 0x1c ) + + + // bit fields for PCMCS + #define PCMCS_EN (1 << 0) + #define PCMCS_RXON (1 << 1) + #define PCMCS_TXON (1 << 2) + #define PCMCS_TXCLR (1 << 3) + #define PCMCS_RXCLR (1 << 4) + #define PCMCS_TXTHR_LSB 5 + #define PCMCS_TXTHR_EMPTY (0 << PCMCS_TXTHR_LSB) + #define PCMCS_TXTHR_1_QUARTER (1 << PCMCS_TXTHR_LSB) + #define PCMCS_TXTHR_3_QUARTER (2 << PCMCS_TXTHR_LSB) + #define PCMCS_TXTHR_FULL (3 << PCMCS_TXTHR_LSB) + #define PCMCS_RXTHR_LSB 7 + #define PCMCS_RXTHR_EMPTY (0 << PCMCS_RXTHR_LSB) + #define PCMCS_RXTHR_1_QUARTER (1 << PCMCS_RXTHR_LSB) + #define PCMCS_RXTHR_3_QUARTER (2 << PCMCS_RXTHR_LSB) + #define PCMCS_RXTHR_FULL (3 << PCMCS_RXTHR_LSB) + + #define PCMCS_DMAEN (1 << 9) + #define PCMCS_INTT (1 << 10) + #define PCMCS_INTR (1 << 11) + #define PCMCS_INTE (1 << 12) + #define PCMCS_TXSYNC (1 << 13) + #define PCMCS_RXSYNC (1 << 14) + #define PCMCS_TXERR (1 << 15) + #define PCMCS_RXERR (1 << 16) + #define PCMCS_TXW (1 << 17) + #define PCMCS_RXR (1 << 18) + #define PCMCS_TXD (1 << 19) + #define PCMCS_RXD (1 << 20) + #define PCMCS_TXE (1 << 21) + #define PCMCS_RXF (1 << 22) + #define PCMCS_RXSEX (1 << 23) + #define PCMCS_SYNC (1 << 24) + + // bit fields for PCMMODE + #define PCMMODE_FSI (1 << 20) + #define PCMMODE_FSM (1 << 21) + #define PCMMODE_CLKI (1 << 22) + #define PCMMODE_CLKM (1 << 23) + #define PCMMODE_FLEN 10 + #define PCMMODE_FSLEN 0 + #define PCMMODE_FTXP (1 << 24) + #define PCMMODE_FRXP (1 << 25) + #define PCMMODE_PDMRX (1 << 26) + #define PCMMODE_PDMRXN (1 << 27) + + // macros for PCMTXC and PCMRXC + #define PCM_CH1POS_LSB 20 + #define PCM_CH1WID_LSB 16 + #define PCM_CH2POS_LSB 4 + #define PCM_CH2WID_LSB 0 + // parameters --> bitmasks + #define PCM_CH1WEX (1 << 31) + #define PCM_CH2WEX (1 << 15) + #define PCM_WIDTH2(x) ( (((x - 8) & 0x0f) << PCM_CH2WID_LSB) + PCM_CH2WEX * (((x-8)&0x10)>>4) ) + #define PCM_POS2(x) (((x) & 0x3ff) << PCM_CH2POS_LSB) + #define PCM_WIDTH1(x) ( (((x - 8) & 0x0f) << PCM_CH1WID_LSB) + PCM_CH1WEX * (((x-8)&0x10)>>4) ) + #define PCM_POS1(x) (((x) & 0x3ff) << PCM_CH1POS_LSB) + #define PCM_CH2EN (1 << 14) + #define PCM_CH1EN (1 << 30) + // bitmasks --> parameters + #define PCM_WID1(x) ( (((x >> PCM_CH1WID_LSB) & 0x0f) + 8) + ((x & PCM_CH1WEX) ? 16 : 0) ) + #define PCM_WID2(x) ( (((x >> PCM_CH2WID_LSB) & 0x0f) + 8) + ((x & PCM_CH2WEX) ? 16 : 0) ) + + // bit fields in the PCMDREQ register + #define PCMDREQ_TXPANICTHR_LSB 24 + #define PCMDREQ_RXPANICTHR_LSB 16 + #define PCMDREQ_TXDREQTHR_LSB 8 + #define PCMDREQ_RXDREQTHR_LSB 0 + + #define PCM_FIFO_DEPTH 64 // words + + + /*---------------------------------------------------------------------------*/ + /* I2C Master */ + #define I2CC_0 HW_REGISTER_RW(I2C_BASE_0 + 0x00) + #define I2CS_0 HW_REGISTER_RW(I2C_BASE_0 + 0x04) + #define I2CDLEN_0 HW_REGISTER_RW(I2C_BASE_0 + 0x08) + #define I2CA_0 HW_REGISTER_RW(I2C_BASE_0 + 0x0C) + #define I2CFIFO_0 HW_REGISTER_RW(I2C_BASE_0 + 0x10) + #define I2CDIV_0 HW_REGISTER_RW(I2C_BASE_0 + 0x14) + #define I2CDEL_0 HW_REGISTER_RW(I2C_BASE_0 + 0x18) + #define I2CCLKT_0 HW_REGISTER_RW(I2C_BASE_0 + 0x1C) + + #define I2CC_1 HW_REGISTER_RW(I2C_BASE_1 + 0x00) + #define I2CS_1 HW_REGISTER_RW(I2C_BASE_1 + 0x04) + #define I2CDLEN_1 HW_REGISTER_RW(I2C_BASE_1 + 0x08) + #define I2CA_1 HW_REGISTER_RW(I2C_BASE_1 + 0x0C) + #define I2CFIFO_1 HW_REGISTER_RW(I2C_BASE_1 + 0x10) + #define I2CDIV_1 HW_REGISTER_RW(I2C_BASE_1 + 0x14) + #define I2CDEL_1 HW_REGISTER_RW(I2C_BASE_1 + 0x18) + #define I2CCLKT_1 HW_REGISTER_RW(I2C_BASE_1 + 0x1C) + + #define I2CC_2 HW_REGISTER_RW(I2C_BASE_2 + 0x00) + #define I2CS_2 HW_REGISTER_RW(I2C_BASE_2 + 0x04) + #define I2CDLEN_2 HW_REGISTER_RW(I2C_BASE_2 + 0x08) + #define I2CA_2 HW_REGISTER_RW(I2C_BASE_2 + 0x0C) + #define I2CFIFO_2 HW_REGISTER_RW(I2C_BASE_2 + 0x10) + #define I2CDIV_2 HW_REGISTER_RW(I2C_BASE_2 + 0x14) + #define I2CDEL_2 HW_REGISTER_RW(I2C_BASE_2 + 0x18) + #define I2CCLKT_2 HW_REGISTER_RW(I2C_BASE_2 + 0x1C) + + #define I2CC_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x00 ) + #define I2CS_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x04 ) + #define I2CDLEN_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x08 ) + #define I2CA_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x0C ) + #define I2CFIFO_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x10 ) + #define I2CDIV_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x14 ) + #define I2CDEL_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x18 ) + #define I2CCLKT_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x1C ) + + // define some bitfields within these I2C registers... + #define I2CC_EN (1 << 15) + #define I2CC_INTR (1 << 10) + #define I2CC_INTT (1 << 9) + #define I2CC_INTD (1 << 8) + #define I2CC_START (1 << 7) + #define I2CC_CLEAR (3 << 4) + #define I2CC_READ (1 << 0) + + #define I2CS_CLKT (1 << 9) + #define I2CS_ERR (1 << 8) + #define I2CS_RXF (1 << 7) + #define I2CS_TXE (1 << 6) + #define I2CS_RXD (1 << 5) + #define I2CS_TXD (1 << 4) + #define I2CS_RXR (1 << 3) + #define I2CS_TXW (1 << 2) + #define I2CS_DONE (1 << 1) + #define I2CS_TA (1 << 0) + + #define I2CDEL_FEDL (16) + #define I2CDEL_REDL (0) + + //Note! Remove this eventually. + //Just define the old VCII I2C peripheral + #define I2CC I2CC_0 + #define I2CS I2CS_0 + #define I2CDLEN I2CDLEN_0 + #define I2CA I2CA_0 + #define I2CFIFO I2CFIFO_0 + #define I2CDIV I2CDIV_0 + #define I2CDEL I2CDEL_0 + #define I2CCLKT I2CCLKT_0 + + /*---------------------------------------------------------------------------*/ + /* Performance Monitor */ + #define PRMCS HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x00) + #define PRMCV HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x04) + #define PRMSCC HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x08) + + /*---------------------------------------------------------------------------*/ + /* OTP */ + + //#define OTP_CONFIG_REG OTP_WRAP_CONFIG_REG + //OTP bit definitions + // NB the addressing has changed between VCIII and VCIV - we now address by row (each row contains 32 bits) + #define OTP_JTAG_DEBUG_KEY_ROW 8 + #define OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS 4 + #define OTP_VPU_CACHE_KEY_ROW (OTP_JTAG_DEBUG_KEY_ROW+OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS) + #define OTP_VPU_CACHE_KEY_SIZE_IN_ROWS 4 + + #define OTP_CONTROL_ROW (OTP_VPU_CACHE_KEY_ROW+OTP_VPU_CACHE_KEY_SIZE_IN_ROWS) + #define OTP_CONTROL_SIZE_IN_ROWS 1 + + #define OTP_BOOT_ROM_ROW (OTP_CONTROL_ROW+OTP_CONTROL_SIZE_IN_ROWS) + #define OTP_BOOT_ROM_SIZE_IN_ROWS 1 + + #define OTP_BOOT_ROM_ROW_REDUNDANT (OTP_BOOT_ROM_ROW+OTP_BOOT_ROM_SIZE_IN_ROWS) + +#ifdef __BCM2708A0__ + #define OTP_BOOT_SIGNING_KEY_ROW (OTP_BOOT_ROM_ROW_REDUNDANT+OTP_BOOT_ROM_SIZE_IN_ROWS) + #define OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4 + + #define OTP_BOOT_SIGNING_PARITY_ROW (OTP_BOOT_SIGNING_KEY_ROW+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) + #define OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1 + + #define OTP_CODE_SIGNING_KEY_ROW (OTP_BOOT_SIGNING_PARITY_ROW+OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS) + #define OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4 + + #define OTP_CODE_SIGNING_PARITY_ROW (OTP_CODE_SIGNING_KEY_ROW+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) + #define OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1 + + #define OTP_HDCP_AES_KEY_ROW (OTP_CODE_SIGNING_PARITY_ROW+OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS) + #define OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4 + + #define OTP_HDCP_AES_PARITY_ROW (OTP_HDCP_AES_KEY_ROW+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) + #define OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1 + + #define OTP_PUBLIC_KEY_ROW (OTP_HDCP_AES_PARITY_ROW+OTP_HDCP_AES_PARITY_SIZE_IN_ROWS) + #define OTP_PUBLIC_KEY_SIZE_IN_ROWS 4 + + #define OTP_PUBLIC_PARITY_ROW (OTP_PUBLIC_KEY_ROW+OTP_PUBLIC_KEY_SIZE_IN_ROWS) + #define OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1 + + #define OTP_PRIVATE_KEY_ROW (OTP_PUBLIC_PARITY_ROW+OTP_PUBLIC_PARITY_SIZE_IN_ROWS) + #define OTP_PRIVATE_KEY_SIZE_IN_ROWS 4 + + #define OTP_PRIVATE_PARITY_ROW (OTP_PRIVATE_KEY_ROW+OTP_PRIVATE_KEY_SIZE_IN_ROWS) + #define OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1 + + #define OTP_CODE_SIGNING_FLAG_ROW (OTP_PRIVATE_PARITY_ROW+OTP_PRIVATE_PARITY_SIZE_IN_ROWS) + #define OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1 + + // Suspend/resume secure RAM key: ensure that these values match the ones + // used in vcsuspend_asm_vc4.s + #define OTP_SUSPEND_SECURE_RAM_KEY (OTP_CODE_SIGNING_FLAG_ROW+OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS) // 64 + #define OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2 + + // to allow A0 to continue to build without too many #ifdefs define the redundant rows to be the same as the original + #define OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT OTP_BOOT_SIGNING_KEY_ROW + #define OTP_CODE_SIGNING_KEY_ROW_REDUNDANT OTP_CODE_SIGNING_KEY_ROW + #define OTP_HDCP_AES_KEY_ROW_REDUNDANT OTP_HDCP_AES_KEY_ROW + #define OTP_PUBLIC_KEY_ROW_REDUNDANT OTP_PUBLIC_KEY_ROW + #define OTP_PRIVATE_KEY_ROW_REDUNDANT OTP_PRIVATE_KEY_ROW +#else + // BCM2708B0 has less reliable OTP so we need a redundant row for the boot signing key (and the corresponding parity) + #define OTP_BOOT_SIGNING_KEY_ROW (OTP_BOOT_ROM_ROW_REDUNDANT+OTP_BOOT_ROM_SIZE_IN_ROWS) // 19 + #define OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4 + + #define OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT (OTP_BOOT_SIGNING_KEY_ROW+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) // 23 + + #define OTP_BOOT_SIGNING_PARITY_ROW (OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) // 27 + #define OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1 + + #define OTP_CODE_SIGNING_KEY_ROW (OTP_BOOT_SIGNING_PARITY_ROW+OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS) // 28 + #define OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4 + + #define OTP_CODE_SIGNING_KEY_ROW_REDUNDANT (OTP_CODE_SIGNING_KEY_ROW+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) // 32 + + #define OTP_CODE_SIGNING_PARITY_ROW (OTP_CODE_SIGNING_KEY_ROW_REDUNDANT+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) // 36 + #define OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1 + + #define OTP_HDCP_AES_KEY_ROW (OTP_CODE_SIGNING_PARITY_ROW+OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS) // 37 + #define OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4 + + #define OTP_HDCP_AES_KEY_ROW_REDUNDANT (OTP_HDCP_AES_KEY_ROW+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) // 41 + + #define OTP_HDCP_AES_PARITY_ROW (OTP_HDCP_AES_KEY_ROW_REDUNDANT+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) // 45 + #define OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1 + + #define OTP_PUBLIC_KEY_ROW (OTP_HDCP_AES_PARITY_ROW+OTP_HDCP_AES_PARITY_SIZE_IN_ROWS) // 46 + #define OTP_PUBLIC_KEY_SIZE_IN_ROWS 4 + + #define OTP_PUBLIC_KEY_ROW_REDUNDANT (OTP_PUBLIC_KEY_ROW+OTP_PUBLIC_KEY_SIZE_IN_ROWS) // 50 + + #define OTP_PUBLIC_PARITY_ROW (OTP_PUBLIC_KEY_ROW_REDUNDANT+OTP_PUBLIC_KEY_SIZE_IN_ROWS) // 54 + #define OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1 + + #define OTP_PRIVATE_KEY_ROW (OTP_PUBLIC_PARITY_ROW+OTP_PUBLIC_PARITY_SIZE_IN_ROWS) // 55 + #define OTP_PRIVATE_KEY_SIZE_IN_ROWS 4 + + #define OTP_PRIVATE_KEY_ROW_REDUNDANT (OTP_PRIVATE_KEY_ROW+OTP_PRIVATE_KEY_SIZE_IN_ROWS) // 59 + + #define OTP_PRIVATE_PARITY_ROW (OTP_PRIVATE_KEY_ROW_REDUNDANT+OTP_PRIVATE_KEY_SIZE_IN_ROWS) // 63 + #define OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1 + + #define OTP_CODE_SIGNING_FLAG_ROW (OTP_PRIVATE_PARITY_ROW+OTP_PRIVATE_PARITY_SIZE_IN_ROWS) // 64 + #define OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1 + + // Suspend/resume secure RAM key: ensure that these values match the ones + // used in vcsuspend_asm_vc4.s + #define OTP_SUSPEND_SECURE_RAM_KEY (OTP_CODE_SIGNING_FLAG_ROW+OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS) // 65 + #define OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2 + + // strictly this is C0 only + #define OTP_BOOT_EXTRAS_ROW (OTP_SUSPEND_SECURE_RAM_KEY+OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS) // 67 + #define OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS 1 +// locations fixed by hardware + #define OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT 68 + #define OTP_VPU_CACHE_KEY_ROW_REDUNDANT 72 + #define OTP_JTAG_VPU_PARITY_REDUNDANT 76 + + #if( OTP_BOOT_EXTRAS_ROW+OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS > OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT ) + #error "User OTP space has overwritten CPU bits" OTP_SUSPEND_SECURE_RAM_KEY OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT + #endif + +#endif + + + #define OTP_MIN_ROW OTP_JTAG_DEBUG_KEY_ROW + #define OTP_MAX_ROW OTP_SUSPEND_SECURE_RAM_KEY + + // bit locations in the CONTROL OTP register + #define OTP_JTAG_DEBUG_KEY_PARITY_START_BIT 0 + #define OTP_VPU_CACHE_KEY_PARITY_START_BIT 8 + #define OTP_JTAG_DISABLE_BIT 16 + #define OTP_JTAG_DISABLE_REDUNDANT_BIT 17 + #define OTP_MACROVISION_START_BIT 18 + #define OTP_MACROVISION_REDUNDANT_START_BIT 20 + #define OTP_DECRYPTION_ENABLE_FOR_DEBUG 22 + #define OTP_ARM_DISABLE_BIT 24 + #define OTP_ARM_DISABLE_REDUNDANT_BIT 25 + + #define OTP_JTAG_PARITY_MASK 0xFF + #define OTP_VPU_CACHE_PARITY_MASK 0xFF + + #define OTP_BYTES_PER_ROW 4 + +// make sure locations used by the hardware are correct +#if( OTP_CONTROL_ROW != 16) + #error "The OTP control row has moved - it must be 16!" +#endif +#if( OTP_BOOT_ROM_ROW != 17 ) + #error "The OTP bootrom row has moved - it must be 17!" +#endif +#if( OTP_BOOT_ROM_ROW_REDUNDANT != 18 ) + #error "The OTP bootrom copy row has moved - it must be 18!" +#endif + + /*---------------------------------------------------------------------------*/ + /* Threading unit */ + + /* Registers for the threading unit */ + #define TH0_BASE 0x18011000 + #define TH0_ADDR_MASK 0x0000003F + #define TH1_BASE 0x1A008000 + #define TH1_ADDR_MASK 0x0000003F + + #define TH0CS HW_REGISTER_RW(TH0_BASE + 0x00) + #define TH0CFG HW_REGISTER_RW(TH0_BASE + 0x04) + #define TH0STPC HW_REGISTER_RW(TH0_BASE + 0x08) + #define TH0ITPC HW_REGISTER_RW(TH0_BASE + 0x0C) + #define TH0T0PC HW_REGISTER_RW(TH0_BASE + 0x10) + #define TH0T0UD HW_REGISTER_RW(TH0_BASE + 0x14) + #define TH0T1PC HW_REGISTER_RW(TH0_BASE + 0x18) + #define TH0T1UD HW_REGISTER_RW(TH0_BASE + 0x1C) + #define TH0T2PC HW_REGISTER_RW(TH0_BASE + 0x20) + #define TH0T2UD HW_REGISTER_RW(TH0_BASE + 0x24) + #define TH0T3PC HW_REGISTER_RW(TH0_BASE + 0x28) + #define TH0T3UD HW_REGISTER_RW(TH0_BASE + 0x2C) + + #define TH1CS HW_REGISTER_RW(TH1_BASE + 0x00) + #define TH1CFG HW_REGISTER_RW(TH1_BASE + 0x04) + #define TH1STPC HW_REGISTER_RW(TH1_BASE + 0x08) + #define TH1ITPC HW_REGISTER_RW(TH1_BASE + 0x0C) + #define TH1T0PC HW_REGISTER_RW(TH1_BASE + 0x10) + #define TH1T0UD HW_REGISTER_RW(TH1_BASE + 0x14) + #define TH1T1PC HW_REGISTER_RW(TH1_BASE + 0x18) + #define TH1T1UD HW_REGISTER_RW(TH1_BASE + 0x1C) + #define TH1T2PC HW_REGISTER_RW(TH1_BASE + 0x20) + #define TH1T2UD HW_REGISTER_RW(TH1_BASE + 0x24) + #define TH1T3PC HW_REGISTER_RW(TH1_BASE + 0x28) + #define TH1T3UD HW_REGISTER_RW(TH1_BASE + 0x2C) + + /* Windows Open GL plugin - emulator only */ + #define WOGLPTR HW_REGISTER_RW(0x1C00FFFC) + + /* Hardware 3D unit */ + + #define GR_VCACHE_BASE 0x1a00a000 + #define GR_VCACHE_ADDR_MASK 0x00001fff + #define GR_VCACHE_SIZE 0x00002000 // in bytes + + #define GR_UNIFORM_BASE 0x1a00c000 + #define GR_UNIFORM_ADDR_MASK 0x00000fff + #define GR_UNIFORM_SIZE 0x00001000 // in bytes + + /* Registers for Vertex Cache Manager */ + #define GR_VCM_BASE 0x1A005C00 + #define GR_VCM_ADDR_MASK 0x0000003f + #define GR_VCM_CI_BASE 0x1A005C80 + #define GR_VCM_CI_ADDR_MASK 0x0000007f + + #define GRMCS HW_REGISTER_RW(GR_VCM_BASE + 0x00) + #define GRMCFG HW_REGISTER_RW(GR_VCM_BASE + 0x04) + #define GRMSVI HW_REGISTER_RW(GR_VCM_BASE + 0x08) + #define GRMSADR HW_REGISTER_RW(GR_VCM_BASE + 0x0C) + #define GRMSCT HW_REGISTER_RW(GR_VCM_BASE + 0x10) + #define GRMOADR HW_REGISTER_RW(GR_VCM_BASE + 0x14) + #define GRMOCT HW_REGISTER_RW(GR_VCM_BASE + 0x18) + #define GRMMCT HW_REGISTER_RW(GR_VCM_BASE + 0x1C) + #define GRMSSI0 HW_REGISTER_RW(GR_VCM_BASE + 0x20) + #define GRMSSI1 HW_REGISTER_RW(GR_VCM_BASE + 0x24) + #define GRMCCT HW_REGISTER_RW(GR_VCM_BASE + 0x28) + + #define GRMCIL0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x00) + #define GRMCIL1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x20) + #define GRMCIH0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x40) + #define GRMCIH1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x60) + + #define GR_VCD_BASE 0x1A005A00 + #define GR_VCD_ADDR_MASK 0x0000007f + + #define GRDCS HW_REGISTER_RW(GR_VCD_BASE + 0x00) + #define GRDCFG HW_REGISTER_RW(GR_VCD_BASE + 0x04) + #define GRDACFG0 HW_REGISTER_RW(GR_VCD_BASE + 0x20) + #define GRDACFG1 HW_REGISTER_RW(GR_VCD_BASE + 0x24) + #define GRDACFG2 HW_REGISTER_RW(GR_VCD_BASE + 0x28) + #define GRDACFG3 HW_REGISTER_RW(GR_VCD_BASE + 0x2C) + #define GRDACFG4 HW_REGISTER_RW(GR_VCD_BASE + 0x30) + #define GRDACFG5 HW_REGISTER_RW(GR_VCD_BASE + 0x34) + #define GRDACFG6 HW_REGISTER_RW(GR_VCD_BASE + 0x38) + #define GRDACFG7 HW_REGISTER_RW(GR_VCD_BASE + 0x3C) + #define GRDAADR0 HW_REGISTER_RW(GR_VCD_BASE + 0x40) + #define GRDAADR1 HW_REGISTER_RW(GR_VCD_BASE + 0x44) + #define GRDAADR2 HW_REGISTER_RW(GR_VCD_BASE + 0x48) + #define GRDAADR3 HW_REGISTER_RW(GR_VCD_BASE + 0x4C) + #define GRDAADR4 HW_REGISTER_RW(GR_VCD_BASE + 0x50) + #define GRDAADR5 HW_REGISTER_RW(GR_VCD_BASE + 0x54) + #define GRDAADR6 HW_REGISTER_RW(GR_VCD_BASE + 0x58) + #define GRDAADR7 HW_REGISTER_RW(GR_VCD_BASE + 0x5C) + + /* Registers for Primitive Setup Engine */ + #define GR_PSE_BASE 0x1A005800 + #define GR_PSE_ADDR_MASK 0x0000007f + + #define GRSCS HW_REGISTER_RW(GR_PSE_BASE + 0x00) + #define GRSCFG HW_REGISTER_RW(GR_PSE_BASE + 0x04) + #define GRSVADR HW_REGISTER_RW(GR_PSE_BASE + 0x08) + #define GRSVFMT HW_REGISTER_RW(GR_PSE_BASE + 0x0C) + #define GRSSP HW_REGISTER_RW(GR_PSE_BASE + 0x10) + #define GRSPADR HW_REGISTER_RW(GR_PSE_BASE + 0x14) + #define GRSPCT HW_REGISTER_RW(GR_PSE_BASE + 0x18) + #define GRSAADR HW_REGISTER_RW(GR_PSE_BASE + 0x1C) + #define GRSACT HW_REGISTER_RW(GR_PSE_BASE + 0x20) + #define GRSDOF HW_REGISTER_RW(GR_PSE_BASE + 0x24) + #define GRSDOU HW_REGISTER_RW(GR_PSE_BASE + 0x28) + #define GRSDMIN HW_REGISTER_RW(GR_PSE_BASE + 0x2C) + #define GRSDMAX HW_REGISTER_RW(GR_PSE_BASE + 0x30) + #define GRSPSZ HW_REGISTER_RW(GR_PSE_BASE + 0x34) + #define GRSLW HW_REGISTER_RW(GR_PSE_BASE + 0x38) + #define GRSFSF HW_REGISTER_RW(GR_PSE_BASE + 0x3C) + #define GRSDZS HW_REGISTER_RW(GR_PSE_BASE + 0x40) + #define GRSHPX HW_REGISTER_RW(GR_PSE_BASE + 0x44) + + /* Debug Registers for Primitive Setup Engine */ + #define GR_PSE_DEBUG_BASE 0x1A005900 + #define GR_PSE_DEBUG_ADDR_MASK 0x00000003 + + #define GRS_DBGE HW_REGISTER_RW(GR_PSE_DEBUG_BASE + 0x00) + + /* Registers for Pixel Pipeline */ + #define GR_PPL_BASE 0x1A005600 + #define GR_PPL_ADDR_MASK 0x0000007F + + #define GRPCS HW_REGISTER_RW(GR_PPL_BASE + 0x00) + #define GRPCFG HW_REGISTER_RW(GR_PPL_BASE + 0x04) + #define GRPCLXY HW_REGISTER_RW(GR_PPL_BASE + 0x08) + #define GRPCLSZ HW_REGISTER_RW(GR_PPL_BASE + 0x0C) + #define GRPVORG HW_REGISTER_RW(GR_PPL_BASE + 0x10) + // gap of 8 bytes + // gap of 16 bytes + // gap of 16 bytes + #define GRPZBCG HW_REGISTER_RW(GR_PPL_BASE + 0x40) + #define GRPSFCG HW_REGISTER_RW(GR_PPL_BASE + 0x44) + #define GRPSBCG HW_REGISTER_RW(GR_PPL_BASE + 0x48) + #define GRPSCC HW_REGISTER_RW(GR_PPL_BASE + 0x4C) + #define GRPBCFG HW_REGISTER_RW(GR_PPL_BASE + 0x50) + #define GRPBCC HW_REGISTER_RW(GR_PPL_BASE + 0x54) + #define GRPCDSM HW_REGISTER_RW(GR_PPL_BASE + 0x58) // xxx dc4 + #define GRPCZSM HW_REGISTER_RW(GR_PPL_BASE + 0x58) + + #define GRPCBS HW_REGISTER_RW(GR_PPL_BASE + 0x5C) + #define GRPABS HW_REGISTER_RW(GR_PPL_BASE + 0x60) + #define GRPFCOL HW_REGISTER_RW(GR_PPL_BASE + 0x64) + + /* Debug Registers for Pixel Pipeline */ + #define GR_PPL_DEBUG_BASE 0x1A005740 + #define GR_PPL_DEBUG_ADDR_MASK 0x0000001F + + #define GRP_FDBGO HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x00) + #define GRP_FDBGB HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x04) + #define GRP_FDBGR HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x08) + #define GRP_FDBGS HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x0C) + #define GRP_SDBG0 HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x10) + + + /* Registers for the Frame Buffer Cache */ + #define GR_FBC_BASE 0x1A005400 + #define GR_FBC_ADDR_MASK 0x0000007F + + #define GRFCS HW_REGISTER_RW(GR_FBC_BASE + 0x00) + #define GRFCFG HW_REGISTER_RW(GR_FBC_BASE + 0x04) + #define GRFTLOC HW_REGISTER_RW(GR_FBC_BASE + 0x08) + #define GRFDIMS HW_REGISTER_RW(GR_FBC_BASE + 0x0C) + #define GRFCCFG HW_REGISTER_RW(GR_FBC_BASE + 0x10) + #define GRFCBA HW_REGISTER_RW(GR_FBC_BASE + 0x14) + #define GRFZCFG HW_REGISTER_RW(GR_FBC_BASE + 0x1C) + #define GRFZBA HW_REGISTER_RW(GR_FBC_BASE + 0x20) + #define GRFZCV HW_REGISTER_RW(GR_FBC_BASE + 0x24) + #define GRFSCV HW_REGISTER_RW(GR_FBC_BASE + 0x28) + #define GRFCMSK HW_REGISTER_RW(GR_FBC_BASE + 0x2C) + #define GRFECFG HW_REGISTER_RW(GR_FBC_BASE + 0x30) + #define GRFEBA HW_REGISTER_RW(GR_FBC_BASE + 0x34) + #define GRFCCV0 HW_REGISTER_RW(GR_FBC_BASE + 0x40) + #define GRFCCV1 HW_REGISTER_RW(GR_FBC_BASE + 0x44) + #define GRFCCV2 HW_REGISTER_RW(GR_FBC_BASE + 0x48) + #define GRFCCV3 HW_REGISTER_RW(GR_FBC_BASE + 0x4C) + #define GRFCCV4 HW_REGISTER_RW(GR_FBC_BASE + 0x50) + #define GRFCCV5 HW_REGISTER_RW(GR_FBC_BASE + 0x54) + #define GRFCCV6 HW_REGISTER_RW(GR_FBC_BASE + 0x58) + #define GRFCCV7 HW_REGISTER_RW(GR_FBC_BASE + 0x5C) + + #define GR_FBC_DEBUG_BASE 0x1A005500 + #define GR_FBC_DEBUG_ADDR_MASK 0x7F + + #define GRFCSTAT HW_REGISTER_RW(GR_FBC_DEBUG_BASE + 0x00) + + /* VPM access via VRF configuration */ + #define GR_VPM_VRFCFG_BASE 0x1A005D00 + #define GR_VPM_VRFCFG_ADDR_MASK 0x00000003 + #define GRVVSTRD HW_REGISTER_RW(GR_VPM_VRFCFG_BASE + 0x00) + + /* Registers for the Texture Unit */ + + /* Mipmap pointer memoies (TU0 & TU1) */ + #define GRTMPM0_BASE 0x1A005E00 + #define GRTMPM1_BASE 0x1A005F00 + + #define GRTMPM0 HW_REGISTER_RW(GRTMPM0_BASE + 0x00) + #define GRTMPM1 HW_REGISTER_RW(GRTMPM1_BASE + 0x00) + + #define GRTMPM_MASK 0xFFFFFF00 + + #define GR_TU_BASE0 0x1A005200 + #define GR_TU_BASE1 0x1A005220 + #define GR_TU_BASE2 0x1A005240 + #define GR_TU_BASE3 0x1A005260 + + #define GR_TU_BASE4 0x1A005280 + #define GR_TU_BASE5 0x1A0052A0 + #define GR_TU_BASE6 0x1A0052C0 + #define GR_TU_BASE7 0x1A0052E0 + + #define GR_TU_DBG_BASE 0x1A005300 + + #define GR_TU_ADDR_MASK 0x000000FF + #define GR_TU_UNIT_MASK 0xFFFFFF1F + + /* Control/Status registers for TU0 & TU1 */ + #define GRTCS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x00) + #define GRTCS1 HW_REGISTER_RW(GR_TU_BASE4 + 0x00) + + /* Common palette for all contexts per texutre unit */ + #define GRTPTBA0 HW_REGISTER_RW(GR_TU_BASE1 + 0x00) + #define GRTPTBA1 HW_REGISTER_RW(GR_TU_BASE5 + 0x00) + + /* 4 sets of context registers for physical texture unit 0 */ + #define GRTCFG0 HW_REGISTER_RW(GR_TU_BASE0 + 0x04) + #define GRTDIM0 HW_REGISTER_RW(GR_TU_BASE0 + 0x08) + #define GRTBCOL0 HW_REGISTER_RW(GR_TU_BASE0 + 0x0C) + #define GRTLBIAS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x1C) + + #define GRTCFG1 HW_REGISTER_RW(GR_TU_BASE1 + 0x04) + #define GRTDIM1 HW_REGISTER_RW(GR_TU_BASE1 + 0x08) + #define GRTBCOL1 HW_REGISTER_RW(GR_TU_BASE1 + 0x0C) + #define GRTLBIAS1 HW_REGISTER_RW(GR_TU_BASE1 + 0x1C) + + #define GRTCFG2 HW_REGISTER_RW(GR_TU_BASE2 + 0x04) + #define GRTDIM2 HW_REGISTER_RW(GR_TU_BASE2 + 0x08) + #define GRTBCOL2 HW_REGISTER_RW(GR_TU_BASE2 + 0x0C) + #define GRTLBIAS2 HW_REGISTER_RW(GR_TU_BASE2 + 0x1C) + + #define GRTCFG3 HW_REGISTER_RW(GR_TU_BASE3 + 0x04) + #define GRTDIM3 HW_REGISTER_RW(GR_TU_BASE3 + 0x08) + #define GRTBCOL3 HW_REGISTER_RW(GR_TU_BASE3 + 0x0C) + #define GRTLBIAS3 HW_REGISTER_RW(GR_TU_BASE3 + 0x1C) + + /* 4 sets of context registers for physical texture unit 1 */ + #define GRTCFG4 HW_REGISTER_RW(GR_TU_BASE4 + 0x04) + #define GRTDIM4 HW_REGISTER_RW(GR_TU_BASE4 + 0x08) + #define GRTBCOL4 HW_REGISTER_RW(GR_TU_BASE4 + 0x0C) + #define GRTLBIAS4 HW_REGISTER_RW(GR_TU_BASE4 + 0x1C) + + #define GRTCFG5 HW_REGISTER_RW(GR_TU_BASE5 + 0x04) + #define GRTDIM5 HW_REGISTER_RW(GR_TU_BASE5 + 0x08) + #define GRTBCOL5 HW_REGISTER_RW(GR_TU_BASE5 + 0x0C) + #define GRTLBIAS5 HW_REGISTER_RW(GR_TU_BASE5 + 0x1C) + + #define GRTCFG6 HW_REGISTER_RW(GR_TU_BASE6 + 0x04) + #define GRTDIM6 HW_REGISTER_RW(GR_TU_BASE6 + 0x08) + #define GRTBCOL6 HW_REGISTER_RW(GR_TU_BASE6 + 0x0C) + #define GRTLBIAS6 HW_REGISTER_RW(GR_TU_BASE6 + 0x1C) + + #define GRTCFG7 HW_REGISTER_RW(GR_TU_BASE7 + 0x04) + #define GRTDIM7 HW_REGISTER_RW(GR_TU_BASE7 + 0x08) + #define GRTBCOL7 HW_REGISTER_RW(GR_TU_BASE7 + 0x0C) + #define GRTLBIAS7 HW_REGISTER_RW(GR_TU_BASE7 + 0x1C) + + /* TU debug registers */ + #define GRTDBG0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x00) + + /* Extra registers per TU for child image support */ + #define GRTCOFF0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x04) + #define GRTCDIM0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x08) + #define GRTCOFF1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x84) + #define GRTCDIM1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x88) + + + /* System Registers */ + #define GR_SYSTEM_BASE 0x1A005000 + + #define GROCS HW_REGISTER_RW(GR_SYSTEM_BASE) + #define GROCFG HW_REGISTER_RW(GR_SYSTEM_BASE + 4) + #define GROIDC HW_REGISTER_RW(GR_SYSTEM_BASE + 8) + + /* System debug register */ + #define GR_SYSTEM_DEBUG_BASE 0x1A005100 + + #define GRODBGA HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x000) + + /* Performance Counters Regs */ + #define GROPCTRC HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x070) + #define GROPCTRE HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x074) + + #define GROPCTR0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x080) + #define GROPCTRS0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x084) + #define GROPCTR1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x088) + #define GROPCTRS1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x08C) + #define GROPCTR2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x090) + #define GROPCTRS2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x094) + #define GROPCTR3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x098) + #define GROPCTRS3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x09C) + #define GROPCTR4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A0) + #define GROPCTRS4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A4) + #define GROPCTR5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A8) + #define GROPCTRS5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0AC) + #define GROPCTR6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B0) + #define GROPCTRS6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B4) + #define GROPCTR7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B8) + #define GROPCTRS7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0BC) + #define GROPCTR8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C0) + #define GROPCTRS8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C4) + #define GROPCTR9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C8) + #define GROPCTRS9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0CC) + #define GROPCTR10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D0) + #define GROPCTRS10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D4) + #define GROPCTR11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D8) + #define GROPCTRS11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0DC) + + /* Performance Counters Defs */ + + #define GROPCTR_FOVCULLEDPRIMS 0x01 + #define GROPCTR_FOVCLIPPEDPRIMS 0x02 + #define GROPCTR_REVCULLEDPRIMS 0x03 + #define GROPCTR_NOFEPIXELPRIMS 0x04 + #define GROPCTR_FEVALIDPRIMS 0x05 + #define GROPCTR_FEZCULLEDQUADS 0x06 + #define GROPCTR_FEVALIDQUADS 0x07 + #define GROPCTR_FEINVALIDPIXELS 0x08 + #define GROPCTR_FEPEZRDY 0x09 + #define GROPCTR_FEPEZIDLE 0x0A + #define GROPCTR_FESTALLPREFETCH 0x0B + #define GROPCTR_FESPMRDY 0x0C + #define GROPCTR_FESPMSTALL 0x0D + #define GROPCTR_TU0_SAME_SET_STALL 0x0E + #define GROPCTR_TU0_SAME_BANK_STALL 0x0F + #define GROPCTR_TU0_AXI_REQ_FIFO_FULL 0x10 + #define GROPCTR_TU0_CACHE_ACCESSES 0x11 + #define GROPCTR_TU0_CACHE_STALLS 0x12 + #define GROPCTR_TU0_CACHE_REQ_STALLS 0x13 + #define GROPCTR_TU0_CACHE_MISSES 0x14 + #define GROPCTR_TU0_CACHE_RCV_WAITS 0x15 + #define GROPCTR_TU1_SAME_SET_STALL 0x16 + #define GROPCTR_TU1_SAME_BANK_STALL 0x17 + #define GROPCTR_TU1_AXI_REQ_FIFO_FULL 0x18 + #define GROPCTR_TU1_CACHE_ACCESSES 0x19 + #define GROPCTR_TU1_CACHE_STALLS 0x1A + #define GROPCTR_TU1_CACHE_REQ_STALLS 0x1B + #define GROPCTR_TU1_CACHE_MISSES 0x1C + #define GROPCTR_TU1_CACHE_RCV_WAITS 0x1D + #define GROPCTR_PBE_FE_STALLS 0x1E + #define GROPCTR_PBE_DEPTH_TEST_FAIL 0x1F + #define GROPCTR_PBE_STCL_TEST_FAIL 0x20 + #define GROPCTR_PBE_DPTH_STCL_PASS 0x21 + #define GROPCTR_FBC_CZ_CLRFLG_FETCHES 0x22 + #define GROPCTR_FBC_CZ_LINE_FLUSHES 0x23 + #define GROPCTR_FBC_CZ_PBE_REQS 0x24 + #define GROPCTR_FBC_CZ_PBE_STALLS 0x25 + #define GROPCTR_FBC_CZ_PBE_MISSES 0x26 + #define GROPCTR_FBC_CZ_PBE_HITS 0x27 + #define GROPCTR_FBC_CZ_FETCH_STALLS 0x28 + #define GROPCTR_FBC_CZ_FE_QUAD_REQS 0x29 + #define GROPCTR_FBC_CZ_FE_LINE_REQS 0x2A + #define GROPCTR_FBC_CZ_FE_UNUSED 0x2B + #define GROPCTR_FBC_CZ_FE_MISSES 0x2C + #define GROPCTR_FBC_CZ_FE_HITS 0x2D + #define GROPCTR_FBC_CZ_FE_DISCARDED 0x2E + #define GROPCTR_FBC_CZ_UM_STALLS 0x2F + #define GROPCTR_FBC_CZ_FETCHES 0x30 + #define GROPCTR_FBC_CZ_EVICTIONS 0x31 + #define GROPCTR_FBC_EZ_CLRFLG_FETCHES 0x32 + #define GROPCTR_FBC_EZ_LINE_FLUSHES 0x33 + #define GROPCTR_FBC_EZ_PBE_REQS 0x34 + #define GROPCTR_FBC_EZ_PBE_STALLS 0x35 + #define GROPCTR_FBC_EZ_PBE_MISSES 0x36 + #define GROPCTR_FBC_EZ_PBE_HITS 0x37 + #define GROPCTR_FBC_EZ_FETCH_STALLS 0x38 + #define GROPCTR_FBC_EZ_FE_REQS 0x39 + #define GROPCTR_FBC_EZ_FE_MISSES 0x3A + #define GROPCTR_FBC_EZ_FE_HITS 0x3B + #define GROPCTR_FBC_EZ_FE_FETCHES 0x3C + #define GROPCTR_FBC_EZ_UM_STALLS 0x3D + #define GROPCTR_FBC_EZ_FETCHES 0x3E + #define GROPCTR_FBC_EZ_EVICTIONS 0x3F + + //VRF defines + #define VRF_SIZE (4096+64+64) + +#endif /* _HARDWARE_VC4_H */ diff --git a/lib/common.h b/lib/common.h new file mode 100755 index 0000000..4ee290a --- /dev/null +++ b/lib/common.h @@ -0,0 +1,55 @@ +#pragma once + +#include "xprintf.h" +#include "stdarg.h" + +typedef unsigned long long u64; +typedef unsigned long long uint64_t; +typedef long long int64_t; + +typedef unsigned int u32; +typedef unsigned int uint32_t; +typedef int int32_t; + +typedef unsigned short u16; +typedef unsigned short uint16_t; +typedef short int16_t; + +typedef unsigned char u8; +typedef unsigned char uint8_t; + +typedef int bool; + +#define true 1 +#define false 0 + +# define ALWAYS_INLINE __attribute__((always_inline)) inline + +extern void panic(const char* fmt, ...) + __attribute__((noreturn)) + __attribute__ ((format (printf, 1, 2))); + +#define panic_plain(ex, ...) \ + (panic)(ex, ## __VA_ARGS__) +#define __STRINGIFY(x) #x +#define LINE_NUMBER(x) __STRINGIFY(x) +#define PANIC_LOCATION __FILE__ ":" LINE_NUMBER(__LINE__) +#define panic(ex, ...) \ + (panic)(# ex "@" PANIC_LOCATION, ## __VA_ARGS__) + +#define printf xprintf + +#define _OPEN_SOURCE + +extern void udelay(uint32_t time); +extern uint32_t __div64_32(uint64_t *n, uint32_t base); + +#define do_div __div64_32 + +/* + * this is done like that because clang likes using __builtin_memcpy + * which makes LLC choke in a fabulous way. + */ +extern void *__memcpy(void *_dst, const void *_src, unsigned len); +#define bcopy(s,d,l) __memcpy(d,s,l) +#define memcpy(d,s,l) __memcpy(d,s,l) \ No newline at end of file diff --git a/lib/memcpy.c b/lib/memcpy.c new file mode 100755 index 0000000..576be62 --- /dev/null +++ b/lib/memcpy.c @@ -0,0 +1,11 @@ + + +void *__memcpy(void *_dst, const void *_src, unsigned len) +{ + unsigned char *dst = _dst; + const unsigned char *src = _src; + while(len-- > 0) { + *dst++ = *src++; + } + return _dst; +} \ No newline at end of file diff --git a/lib/panic.c b/lib/panic.c new file mode 100755 index 0000000..cb9465c --- /dev/null +++ b/lib/panic.c @@ -0,0 +1,36 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +Panic routine. + +=============================================================================*/ + + +#include "xprintf.h" + +void panic(const char* fmt, ...) { + xputs("panic(): "); + + va_list arp; + va_start(arp, fmt); + xvprintf(fmt, arp); + va_end(arp); + + xputc('\n'); + + for (;;) { + __asm__ __volatile__ ("nop" :::); + } +} \ No newline at end of file diff --git a/lib/stdarg.h b/lib/stdarg.h new file mode 100755 index 0000000..efe5571 --- /dev/null +++ b/lib/stdarg.h @@ -0,0 +1,9 @@ + + +#pragma once + +typedef __builtin_va_list va_list; + +#define va_start(v,l) __builtin_va_start(v,l) +#define va_arg(v,l) __builtin_va_arg(v,l) +#define va_end(v) __builtin_va_end(v) \ No newline at end of file diff --git a/lib/udelay.c b/lib/udelay.c new file mode 100755 index 0000000..58135cf --- /dev/null +++ b/lib/udelay.c @@ -0,0 +1,37 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +Simple timer based delay routine. + +=============================================================================*/ + +#ifdef __arm__ +#else +#include "common.h" +#endif + +#include "../hardware.h" + + +void udelay(uint32_t t) { + uint32_t tv = ST_CLO; + + for (;;) { + /* nop still takes a cycle i think? */ + __asm__ __volatile__ ("nop" :::); + if ((ST_CLO - tv) > t) + return; + } +} \ No newline at end of file diff --git a/lib/xprintf.c b/lib/xprintf.c new file mode 100755 index 0000000..06d8179 --- /dev/null +++ b/lib/xprintf.c @@ -0,0 +1,191 @@ +/*------------------------------------------------------------------------/ +/ Universal string handler for user console interface +/-------------------------------------------------------------------------/ +/ +/ Copyright (C) 2011, ChaN, all right reserved. +/ +/ * This software is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-------------------------------------------------------------------------*/ + +#include "xprintf.h" + +extern void uart_putc(unsigned int ch); + +/*----------------------------------------------*/ +/* Put a character */ +/*----------------------------------------------*/ + +void xputc (char c) +{ + if (_CR_CRLF && c == '\n') xputc('\r'); /* CR -> CRLF */ + + uart_putc(c); +} + +/*----------------------------------------------*/ +/* Put a null-terminated string */ +/*----------------------------------------------*/ + +void xputs ( /* Put a string to the default device */ + const char* str /* Pointer to the string */ +) +{ + while (*str) + xputc(*str++); +} + +/*----------------------------------------------*/ +/* Formatted string output */ +/*----------------------------------------------*/ +/* xprintf("%d", 1234); "1234" + xprintf("%6d,%3d%%", -200, 5); " -200, 5%" + xprintf("%-6u", 100); "100 " + xprintf("%ld", 12345678L); "12345678" + xprintf("%04x", 0xA3); "00a3" + xprintf("%08LX", 0x123ABC); "00123ABC" + xprintf("%016b", 0x550F); "0101010100001111" + xprintf("%s", "String"); "String" + xprintf("%-4s", "abc"); "abc " + xprintf("%4s", "abc"); " abc" + xprintf("%c", 'a'); "a" + xprintf("%f", 10.0); +*/ + +void xvprintf ( + const char* fmt, /* Pointer to the format string */ + va_list arp /* Pointer to arguments */ +) +{ + unsigned int r, i, j, w, f; + unsigned long v; + char s[16], c, d, *p; + + + for (;;) { + c = *fmt++; /* Get a char */ + if (!c) break; /* End of format? */ + if (c != '%') { /* Pass through it if not a % sequense */ + xputc(c); continue; + } + f = 0; + c = *fmt++; /* Get first char of the sequense */ + if (c == '0') { /* Flag: '0' padded */ + f = 1; c = *fmt++; + } else { + if (c == '-') { /* Flag: left justified */ + f = 2; c = *fmt++; + } + } + for (w = 0; c >= '0' && c <= '9'; c = *fmt++) /* Minimum width */ + w = w * 10 + c - '0'; + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 4; c = *fmt++; + } + if (!c) break; /* End of format? */ + d = c; + if (d >= 'a') d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + p = va_arg(arp, char*); + for (j = 0; p[j]; j++) ; + while (!(f & 2) && j++ < w) xputc(' '); + xputs(p); + while (j++ < w) xputc(' '); + continue; + case 'C' : /* Character */ + xputc((char)va_arg(arp, int)); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown type (passthrough) */ + xputc(c); continue; + } + + /* Get an argument and put it in numeral */ + v = (f & 4) ? va_arg(arp, long) : ((d == 'D') ? (long)va_arg(arp, int) : (long)va_arg(arp, unsigned int)); + if (d == 'D' && (v & 0x80000000)) { + v = 0 - v; + f |= 8; + } + i = 0; + do { + d = (char)(v % r); v /= r; + if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + s[i++] = d + '0'; + } while (v && i < sizeof(s)); + if (f & 8) s[i++] = '-'; + j = i; d = (f & 1) ? '0' : ' '; + while (!(f & 2) && j++ < w) xputc(d); + do xputc(s[--i]); while(i); + while (j++ < w) xputc(' '); + } +} + + +void xprintf ( /* Put a formatted string to the default device */ + const char* fmt, /* Pointer to the format string */ + ... /* Optional arguments */ +) +{ + va_list arp; + + va_start(arp, fmt); + xvprintf(fmt, arp); + va_end(arp); +} + + +/*----------------------------------------------*/ +/* Dump a line of binary dump */ +/*----------------------------------------------*/ + +void put_dump ( + const void* buff, /* Pointer to the array to be dumped */ + unsigned long addr, /* Heading address value */ + int len, /* Number of items to be dumped */ + int width /* Size of the items (DF_CHAR, DF_SHORT, DF_LONG) */ +) +{ + int i; + const unsigned char *bp; + const unsigned short *sp; + const unsigned long *lp; + + + xprintf("%08lX ", addr); /* address */ + + switch (width) { + case DW_CHAR: + bp = buff; + for (i = 0; i < len; i++) /* Hexdecimal dump */ + xprintf(" %02X", bp[i]); + xputc(' '); + for (i = 0; i < len; i++) /* ASCII dump */ + xputc((bp[i] >= ' ' && bp[i] <= '~') ? bp[i] : '.'); + break; + case DW_SHORT: + sp = buff; + do /* Hexdecimal dump */ + xprintf(" %04X", *sp++); + while (--len); + break; + case DW_LONG: + lp = buff; + do /* Hexdecimal dump */ + xprintf(" %08LX", *lp++); + while (--len); + break; + } + + xputc('\n'); +} \ No newline at end of file diff --git a/lib/xprintf.h b/lib/xprintf.h new file mode 100755 index 0000000..3ac32e0 --- /dev/null +++ b/lib/xprintf.h @@ -0,0 +1,36 @@ +/*------------------------------------------------------------------------*/ +/* Universal string handler for user console interface (C)ChaN, 2011 */ +/*------------------------------------------------------------------------*/ + +#ifdef __arm__ + #include +#else + #include "stdarg.h" +#endif + + +#ifndef _STRFUNC +#define _STRFUNC + +#define _USE_XFUNC_OUT 1 /* 1: Use output functions */ +#define _CR_CRLF 1 /* 1: Convert \n ==> \r\n in the output char */ + +void xputc (char c); +void xputs (const char* str); +void xfputs (void (*func)(unsigned char), const char* str); +void xprintf (const char* fmt, ...) __attribute__ ((format (printf, 1, 2))); +void xsprintf (char* buff, const char* fmt, ...); +void xfprintf (void (*func)(unsigned char), const char* fmt, ...); +void put_dump (const void* buff, unsigned long addr, int len, int width); + + +void xvprintf ( + const char* fmt, /* Pointer to the format string */ + va_list arp /* Pointer to arguments */ +); + +#define DW_CHAR sizeof(char) +#define DW_SHORT sizeof(short) +#define DW_LONG sizeof(long) + +#endif diff --git a/romstage.c b/romstage.c new file mode 100755 index 0000000..1bd0b08 --- /dev/null +++ b/romstage.c @@ -0,0 +1,183 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +VideoCoreIV first stage bootloader. + +=============================================================================*/ + +#include "lib/common.h" +#include "hardware.h" + +uint32_t g_CPUID; + +void uart_putc(unsigned int ch) +{ + while(1) { + if (mmio_read32(AUX_MU_LSR_REG) & 0x20) + break; + } + mmio_write32(AUX_MU_IO_REG, ch); +} + +void uart_init(void) { + unsigned int ra = GP_FSEL1; + ra &= ~(7 << 12); + ra |= 2 << 12; + GP_FSEL1 = ra; + + GP_PUD = 0; + + udelay(150); + GP_PUDCLK0 = (1 << 14) | (1 << 15); + udelay(150); + GP_PUDCLK0 = 0; + + mmio_write32(AUX_ENABLES, 1); + mmio_write32(AUX_MU_IER_REG, 0); + mmio_write32(AUX_MU_CNTL_REG, 0); + mmio_write32(AUX_MU_LCR_REG, 3); + mmio_write32(AUX_MU_MCR_REG, 0); + mmio_write32(AUX_MU_IER_REG, 0); + mmio_write32(AUX_MU_IIR_REG, 0xC6); + + mmio_write32(AUX_MU_BAUD_REG, 270); + + mmio_write32(AUX_MU_LCR_REG, 3); + mmio_write32(AUX_MU_CNTL_REG, 3); +} + +void led_init(void) { + unsigned int ra; + + ra = GP_FSEL1; + ra &= ~(7 << 18); + ra |= 1 << 18; + + GP_FSEL1 = ra; +} + +/* + #define CM_PLLC_DIGRST_BITS 9:9 + #define CM_PLLC_DIGRST_SET 0x00000200 + #define CM_PLLC_ANARST_BITS 8:8 + #define CM_PLLC_ANARST_SET 0x00000100 + #define CM_PLLC_HOLDPER_BITS 7:7 + #define CM_PLLC_HOLDPER_SET 0x00000080 + #define CM_PLLC_LOADPER_BITS 6:6 + #define CM_PLLC_LOADPER_SET 0x00000040 + #define CM_PLLC_HOLDCORE2_BITS 5:5 + #define CM_PLLC_HOLDCORE2_SET 0x00000020 + #define CM_PLLC_LOADCORE2_BITS 4:4 + #define CM_PLLC_LOADCORE2_SET 0x00000010 + #define CM_PLLC_HOLDCORE1_BITS 3:3 + #define CM_PLLC_HOLDCORE1_SET 0x00000008 + #define CM_PLLC_LOADCORE1_BITS 2:2 + #define CM_PLLC_LOADCORE1_SET 0x00000004 + #define CM_PLLC_HOLDCORE0_BITS 1:1 + #define CM_PLLC_HOLDCORE0_SET 0x00000002 + #define CM_PLLC_LOADCORE0_BITS 0:0 + #define CM_PLLC_LOADCORE0_SET 0x00000001 +*/ + +void switch_vpu_to_pllc() { + A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLCEN_SET; + + A2W_PLLC_FRAC = A2W_PASSWORD | 87380; + A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000; + + A2W_PLLC_ANA3 = A2W_PASSWORD | 0x100; + A2W_PLLC_ANA2 = A2W_PASSWORD | 0x0; + A2W_PLLC_ANA1 = A2W_PASSWORD | 0x144000; + A2W_PLLC_ANA0 = A2W_PASSWORD | 0x0; + + CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET; + + /* hold all */ + CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET; + + A2W_PLLC_DIG3 = A2W_PASSWORD | 0x0; + A2W_PLLC_DIG2 = A2W_PASSWORD | 0x400000; + A2W_PLLC_DIG1 = A2W_PASSWORD | 0x5; + A2W_PLLC_DIG0 = A2W_PASSWORD | 52 | 0x555000; + + A2W_PLLC_CTRL = A2W_PASSWORD | 52 | 0x1000 | A2W_PLLC_CTRL_PRSTN_SET; + + A2W_PLLC_DIG3 = A2W_PASSWORD | 0x42; + A2W_PLLC_DIG2 = A2W_PASSWORD | 0x500401; + A2W_PLLC_DIG1 = A2W_PASSWORD | 0x4005; + A2W_PLLC_DIG0 = A2W_PASSWORD | 52 | 0x555000; + + A2W_PLLC_CORE0 = A2W_PASSWORD | 2; + + CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET; + + CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET; + + CM_PLLC = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET; + + CM_VPUCTL = CM_PASSWORD | CM_VPUCTL_FRAC_SET | CM_SRC_OSC | CM_VPUCTL_GATE_SET; + CM_VPUDIV = CM_PASSWORD | (4 << 12); + CM_VPUCTL = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET; + CM_VPUCTL = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET | 0x10; /* ENAB */ + + CM_TIMERDIV = CM_PASSWORD | (19 << 12) | 819; + CM_TIMERCTL = CM_PASSWORD | CM_SRC_OSC | 0x10; +} + +extern void sdram_init(); +extern void arm_init(); + +int _main(unsigned int cpuid, unsigned int load_address) { + switch_vpu_to_pllc(); + + led_init(); + uart_init(); + + printf( + "=========================================================\n" + "::\n" + ":: kFW for bcm2708, Copyright 2016, Kristina Brooks. \n" + "::\n" + ":: BUILDATE : %s %s \n" + ":: BUILDSTYLE: %s \n" + "::\n" + "=========================================================\n", + __DATE__, __TIME__, + "OPENSOURCE" + ); + + printf("CPUID = 0x%X\n", cpuid); + printf("LoadAddr = 0x%X\n", load_address); + + g_CPUID = cpuid; + + /* bring up SDRAM */ + sdram_init(); + printf("SDRAM initialization completed successfully!\n"); + + /* bring up ARM */ + arm_init(); + + panic("main exiting!"); +} + diff --git a/sdram.c b/sdram.c new file mode 100755 index 0000000..42f4d12 --- /dev/null +++ b/sdram.c @@ -0,0 +1,360 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +VideoCoreIV SDRAM initialization code. + +=============================================================================*/ + +#include "lib/common.h" +#include "hardware.h" + + +extern uint32_t g_CPUID; + +#define MR_REQUEST_SUCCESS(x) ((SD_MR_TIMEOUT_SET & x) != SD_MR_TIMEOUT_SET) +#define MR_GET_RDATA(x) ((x & SD_MR_RDATA_SET) >> SD_MR_RDATA_LSB) + +#define RAM_TEST_ADDR 0xC0000000 +#define RAM_TEST_PATTERN 0xAAAAAAAA + +#define SIP_DEBUG(x) x +#define SCLKU_DEBUG(x) //SIP_DEBUG(x) + +ALWAYS_INLINE inline void sdram_clkman_update_begin() { + CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_UPDATE_SET; + SCLKU_DEBUG(printf("%s: waiting for ACCPT (%X) ...\n", __FUNCTION__, CM_SDCCTL)); + for (;;) if (CM_SDCCTL & CM_SDCCTL_ACCPT_SET) break; + SCLKU_DEBUG(printf("%s: ACCPT received! (%X)\n", __FUNCTION__, CM_SDCCTL)); +} + +ALWAYS_INLINE inline void sdram_clkman_update_end() { + CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_UPDATE_CLR); + SCLKU_DEBUG(printf("%s: waiting for ACCPT clear (%X) ...\n", __FUNCTION__, CM_SDCCTL)); + for (;;) if ((CM_SDCCTL & CM_SDCCTL_ACCPT_SET) == 0) break; + SCLKU_DEBUG(printf("%s: ACCPT cleared! (%X)\n", __FUNCTION__, CM_SDCCTL)); +} + +ALWAYS_INLINE void sdram_reset_phy_lines() { + SIP_DEBUG(printf("%s: resetting APHY/DPHY lines ...\n", __FUNCTION__)); + + /* politely tell sdc that we'll be messing with address lines */ + APHY_CSR_PHY_BIST_CNTRL_SPR = 0x30; + + DPHY_CSR_GLBL_DQ_DLL_RESET = 0x1; + APHY_CSR_GLBL_ADDR_DLL_RESET = 0x1; + + /* stall ... */ + SD_CS; + SD_CS; + SD_CS; + SD_CS; + + DPHY_CSR_GLBL_DQ_DLL_RESET = 0x0; + APHY_CSR_GLBL_ADDR_DLL_RESET = 0x0; + + SIP_DEBUG(printf("%s: waiting for DPHY master PLL to lock ...\n", __FUNCTION__)); + for (;;) if ((DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT & 0xFFFF) == 0xFFFF) break; + SIP_DEBUG(printf("%s: DPHY master PLL locked!\n", __FUNCTION__)); +} + +void sdram_init_late() { + uint32_t ctrl = 0x4; + + SD_CS = (SD_CS & ~(SD_CS_DEL_KEEP_SET|SD_CS_DPD_SET|SD_CS_RESTRT_SET)) | SD_CS_STBY_SET; + + /* wait for SDRAM controller to go down */ + SIP_DEBUG(printf("%s: waiting for SDRAM controller to go down (%X) ...\n", __FUNCTION__, SD_CS)); + for (;;) if ((SD_CS & SD_CS_SDUP_SET) == 0) break; + SIP_DEBUG(printf("%s: SDRAM controller down!\n", __FUNCTION__)); + + /* disable SDRAM clock */ + sdram_clkman_update_begin(); + CM_SDCCTL = (CM_SDCCTL & ~(CM_SDCCTL_ENAB_SET|CM_SDCCTL_CTRL_SET)) | CM_PASSWORD; + sdram_clkman_update_end(); + + SIP_DEBUG(printf("%s: SDRAM clock disabled!\n", __FUNCTION__)); + + /* left */ + + APHY_CSR_DDR_PLL_PWRDWN = 0; + APHY_CSR_DDR_PLL_GLOBAL_RESET = 0; + APHY_CSR_DDR_PLL_POST_DIV_RESET = 0; + + APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 = (1 << 16) | 0x53 /* magic */; + APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 = 0; + APHY_CSR_DDR_PLL_MDIV_VALUE = 0; + APHY_CSR_DDR_PLL_GLOBAL_RESET = 1; + + SIP_DEBUG(printf("%s: waiting for APHY DDR PLL to lock ...\n", __FUNCTION__)); + for (;;) if (APHY_CSR_DDR_PLL_LOCK_STATUS & (1 << 16)) break; + SIP_DEBUG(printf("%s: APHY DDR PLL locked!\n", __FUNCTION__)); + + APHY_CSR_DDR_PLL_POST_DIV_RESET = 1; + + sdram_clkman_update_begin(); + + CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR); + sdram_clkman_update_end(); + + SIP_DEBUG(printf("%s: CM_SDCCTL = 0x%X\n", __FUNCTION__, CM_SDCCTL)); + + /* second stage magic values */ + SD_SA = 0x0C293395; + SD_SB = 0x0F9; + SD_SC = 0x32200743; + SD_SD = 0x71810F66; + SD_SE = 0x10412136; + SD_PT1 = 0x137B828; + SD_PT2 = 0x0F96; + SD_MRT = 0x3; + + sdram_reset_phy_lines(); + + /* wait for address line pll to come back */ + SIP_DEBUG(printf("%s: waiting for APHY global PLL to lock ...\n", __FUNCTION__)); + for (;;) if (APHY_CSR_GLBL_ADR_DLL_LOCK_STAT == 3) break; + SIP_DEBUG(printf("%s: APHY global PLL locked!\n", __FUNCTION__)); + + /* tell sdc we're done messing with address lines */ + APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0; + + /* woo, turn on sdram! */ + SD_CS = (0x200042 & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET; +} + +unsigned int sdram_read_mr(unsigned int addr) { + while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + SD_MR = addr & 0xFF; + unsigned int mrr; + while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + return mrr; +} + +unsigned int sdram_write_mr(unsigned int addr, unsigned int data, bool wait) { + while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + + SD_MR = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET; + + if (wait) { + unsigned int mrr; + while (((mrr = SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + + if (mrr & SD_MR_TIMEOUT_SET) + panic("MR write timed out (addr=%d data=0x%X)", addr, data); + + return mrr; + } + else { + return 0; + } +} + +void sdram_reset_phy() { + printf("%s: resetting SDRAM PHY ...\n", __FUNCTION__); + + /* reset PHYC */ + SD_PHYC = SD_PHYC_PHYRST_SET; + udelay(64); + SD_PHYC = 0; + + printf("%s: resetting DPHY CTRL ...\n", __FUNCTION__); + + DPHY_CSR_DQ_PHY_MISC_CTRL = 0x7; + DPHY_CSR_DQ_PAD_MISC_CTRL = 0x0; + DPHY_CSR_BOOT_READ_DQS_GATE_CTRL = 0x11; + + sdram_reset_phy_lines(); + + APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0; +} + +static void sdram_set_clock_source(unsigned int source, unsigned int div_) { + CM_SDCDIV = CM_PASSWORD | (div_ << CM_SDCDIV_DIV_LSB); + CM_SDCCTL = CM_PASSWORD | (CM_SDCCTL & CM_SDCCTL_SRC_CLR) | source; + CM_SDCCTL |= CM_PASSWORD | CM_SDCCTL_ENAB_SET; + + printf("%s: source set to %d, div to %d, waiting for BUSY set (%X) ... \n", __FUNCTION__, source, div_, CM_SDCCTL); + + for (;;) if (CM_SDCCTL & CM_SDCCTL_BUSY_SET) break; + + printf("%s: BUSY set! (%X)\n", __FUNCTION__, CM_SDCCTL); +} + +static void sdram_init_clkman() +{ + uint32_t ctrl = 0; + + sdram_clkman_update_begin(); + CM_SDCCTL = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (CM_SDCCTL & CM_SDCCTL_CTRL_CLR); + sdram_clkman_update_end(); +} + +static const char* lpddr2_manufacturer_name(uint32_t mr) { + switch (mr) { + case 1: return "Samsung"; + case 2: return "Qimonda"; + case 3: return "Elpida"; + case 4: return "Etron"; + case 5: return "Nanya"; + case 6: return "Hynix"; + default: return "Unknown"; + } +} + +static const char* lpddr2_density(uint32_t mr) { + /* + * i'm so stupid, why did i not notice that LPDDR2 + * spec listed those as bits, not bytes *sigh* + */ + switch ((mr & 0x33) >> 3) { + case 1: return "128MB"; + case 2: return "256MB"; + case 3: return "512MB"; + case 4: return "1GB"; + case 5: return "2GB"; + case 6: return "4GB"; + default: return "Unknown"; + } +} + +static void sdram_calibrate() { + /* some hw revisions require different slews */ + bool st = ((g_CPUID >> 4) & 0xFFF) == 0x14; + uint32_t dq_slew = (st ? 2 : 3); + + /* i don't get it, the spec says do not use this register */ + sdram_write_mr(0xFF, 0, true); + /* RL = 6 / WL = 3 */ + sdram_write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, true); + + APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL = 0x333; + DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = (dq_slew << 8) | (dq_slew << 4) | 3; + + printf("%s: DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", __FUNCTION__, DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL); + + /* tell sdc we want to calibrate */ + APHY_CSR_PHY_BIST_CNTRL_SPR = 0x20; + + APHY_CSR_ADDR_PVT_COMP_CTRL = 0x1; + printf("%s: waiting for address PVT calibration ...\n", __FUNCTION__); + for (;;) if (APHY_CSR_ADDR_PVT_COMP_STATUS & 2) break; + + DPHY_CSR_DQ_PVT_COMP_CTRL = 0x1; + printf("%s: waiting for data PVT calibration ...\n", __FUNCTION__); + for (;;) if (DPHY_CSR_DQ_PVT_COMP_STATUS & 2) break; + + /* tell sdc we're done calibrating */ + APHY_CSR_PHY_BIST_CNTRL_SPR = 0x0; + + /* send calibration command */ + uint32_t old_mrt = SD_MRT; + SD_MRT = 20; + printf("%s: waiting for SDRAM calibration command ...\n", __FUNCTION__); + SD_MR = LPDDR2_MR_CALIBRATION | (0xFF << 8) | SD_MR_RW_SET | SD_MR_HI_Z_SET; + while ((SD_MR & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + SD_MRT = old_mrt; + + sdram_write_mr(LPDDR2_MR_IO_CONFIG, is_thing ? 3 : 2, false); +} + +static void sdram_selftest() +{ + volatile uint32_t* p = (volatile uint32_t*)RAM_TEST_ADDR; + + printf("Testing SDRAM ...\n"); + + for (int i = 0; i < 0x100000; i++) { + p[i] = RAM_TEST_PATTERN; + if (p[i] != RAM_TEST_PATTERN) + panic("sdram initialization failed (idx=%d exptected=0x%x got=0x%x)", i, RAM_TEST_PATTERN, p[i]); + } + + printf("SDRAM test successful!\n"); +} + +void sdram_init() { + uint32_t vendor_id, bc; + + printf("%s: (0) SD_CS = 0x%X\n", __FUNCTION__, SD_CS); + + PM_SMPS = PM_PASSWORD | 0x1; + A2W_SMPS_LDO1 = A2W_PASSWORD | 0x40000; + A2W_SMPS_LDO0 = A2W_PASSWORD | 0x0; + + A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_DDREN_SET; + + /* + * STEP 1: + * configure the low-frequency PLL and enable SDC and perform + * the calibration sequence. + */ + + sdram_set_clock_source(CM_SRC_OSC, 1); + + sdram_init_clkman(); + + sdram_reset_phy(); + + /* magic values */ + SD_SA = 0x6E3395; + SD_SB = 0x0F9; + SD_SC = 0x6000431; + SD_SD = 0x10000011; + SD_SE = 0x10106000; + SD_PT1 = 0x0AF002; + SD_PT2 = 0x8C; + SD_MRT = 0x3; + SD_CS = 0x200042; + + /* wait for SDRAM controller */ + printf("%s: waiting for SDUP (%X) ...\n", __FUNCTION__, SD_CS); + for (;;) if (SD_CS & SD_CS_SDUP_SET) break; + printf("%s: SDRAM controller has arrived! (%X)\n", __FUNCTION__, SD_CS); + + /* RL = 6 / WL = 3 */ + sdram_write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false); + sdram_calibrate(); + + /* identify installed memory */ + vendor_id = sdram_read_mr(LPDDR2_MR_MANUFACTURER_ID); + if (!MR_REQUEST_SUCCESS(vendor_id)) { + panic("vendor id memory register read timed out"); + } + vendor_id = MR_GET_RDATA(vendor_id); + + bc = sdram_read_mr(LPDDR2_MR_METRICS); + if (!MR_REQUEST_SUCCESS(bc)) { + panic("basic configuration memory register read timed out"); + } + bc = MR_GET_RDATA(bc); + + printf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n", + lpddr2_manufacturer_name(vendor_id), + lpddr2_density(bc), + bc); + + /* + * STEP 2: + * after calibration, enable high-freq SDRAM PLL. because we're + * running from cache, we can freely mess with SDRAM clock without + * any issues, removing the need to copy the SDRAM late init stuff + * to bootrom ram. if later code that's running from SDRAM wants to + * mess with SDRAM clock it would need to do that. + */ + + sdram_init_late(); + sdram_selftest(); +} + diff --git a/start.s b/start.s new file mode 100755 index 0000000..8beda47 --- /dev/null +++ b/start.s @@ -0,0 +1,165 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +Entry. + +A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to +0x80000200. This region corresponds to L1/L2 cached IO and cache is never +evicted as long as we don't touch memory above that. This gives us 128KB +of memory at startup. + +Exception names are from the public release from: + brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c + +=============================================================================*/ + + +.text + +empty_space: + .space 0x200 + +.include "ghetto.s" + +/* main entry point */ + +.globl _start +.align 2 +_start: + mov r0, cpuid + mov r5, r0 + + # get addr of the exception vector table + lea r1, __INTERRUPT_VECTORS + mov r3, r1 + + /* + * populate the exception vector table using PC relative labels + * so the code isnt position dependent + */ +.macro RegExceptionHandler label, exception_number + lea r2, Exc_\label + st r2, (r1) + add r1, #4 +.endm + + RegExceptionHandler zero, #0 + RegExceptionHandler misaligned, #1 + RegExceptionHandler dividebyzero, #2 + RegExceptionHandler undefinedinstruction, #3 + RegExceptionHandler forbiddeninstruction, #4 + RegExceptionHandler illegalmemory, #5 + RegExceptionHandler buserror, #6 + RegExceptionHandler floatingpoint, #7 + RegExceptionHandler isp, #8 + RegExceptionHandler dummy, #9 + RegExceptionHandler icache, #10 + RegExceptionHandler veccore, #11 + RegExceptionHandler badl2alias, #12 + RegExceptionHandler breakpoint, #13 + RegExceptionHandler unknown, #14 + + /* + * load the interrupt and normal stack pointers. these + * are chosen to be near the top of the available cache memory + */ + + mov r28, #0x1D000 + mov sp, #0x1C000 + + /* set interrupt vector bases */ + mov r0, #IC0_VADDR + st r3, (r0) + mov r0, #IC1_VADDR + st r3, (r0) + + /* jump to C code */ + mov r0, r5 + lea r1, _start + + ei + + bl _main + +/************************************************************ + * Debug + ************************************************************/ + +blinker: + mov r1, #GPFSEL1 + ld r0, (r1) + and r0, #(~(7<<18)) + or r0, #(1<<18) + st r0, (r1) + mov r1, #GPSET0 + mov r2, #GPCLR0 + mov r3, #(1<<16) +loop: + st r3, (r1) + mov r0, #0 +delayloop1: + add r0, #1 + cmp r0, #0x100000 + bne delayloop1 + st r3, (r2) + mov r0, #0 +delayloop2: + add r0, #1 + cmp r0, #0x100000 + bne delayloop2 + b loop + +/************************************************************ + * Exception Handling + ************************************************************/ + +_sleh_generic_gate: + # get faulting PC + ld r1, 4(sp) + # call the C exception handler + b sleh_fatal + + +.macro ExceptionHandler label, exception_number +Exc_\label: + mov r0, \exception_number + b _sleh_generic_gate +.endm + + ExceptionHandler zero, #0 + ExceptionHandler misaligned, #1 + ExceptionHandler dividebyzero, #2 + ExceptionHandler undefinedinstruction, #3 + ExceptionHandler forbiddeninstruction, #4 + ExceptionHandler illegalmemory, #5 + ExceptionHandler buserror, #6 + ExceptionHandler floatingpoint, #7 + ExceptionHandler isp, #8 + ExceptionHandler dummy, #9 + ExceptionHandler icache, #10 + ExceptionHandler veccore, #11 + ExceptionHandler badl2alias, #12 + ExceptionHandler breakpoint, #13 + ExceptionHandler unknown, #14 + +/************************************************************ + * ISRs + ************************************************************/ + +.align 4 +__INTERRUPT_VECTORS: + # 31 slots, 4 byte each for processor exceptions. patched to have the correct + # exception handler routines at runtime to allow the code to be loaded anywhere + .space 124, 0 diff --git a/trap.c b/trap.c new file mode 100755 index 0000000..6e5a973 --- /dev/null +++ b/trap.c @@ -0,0 +1,53 @@ +/*============================================================================= +Copyright (C) 2016 Kristina Brooks +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +VideoCoreIV second level exception handlers. + +=============================================================================*/ + +#include "lib/common.h" +#include "hardware.h" + +/* + * this file in the public release documents all exception names. + * brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c + */ + +static const char* g_ExceptionNames[] = { + "zero", + "misaligned", + "divide by zero", + "undefined instruction", + "forbidden instruction", + "illegal memory", + "bus error", + "floating point", + "isp", + "dummy", + "icache", + "vec core", + "bad l2 alias", + "breakpoint" +}; + +static const char* exception_name(uint32_t n) { + if (n >= (sizeof(g_ExceptionNames)/4)) + return "unknown"; + return g_ExceptionNames[n]; +} + +void sleh_fatal(uint32_t n, uint32_t pc) { + panic("fatal processor exception: %s (%d) at 0x%0x", exception_name(n), n, pc); +} \ No newline at end of file