// This file was generated by the create_regs script
#define CCP_BASE                                                 0x7e801000
#define CCP_APB_ID                                               0x63637032
#define CCP_RC                                                   HW_REGISTER_RW( 0x7e801000 ) 
   #define CCP_RC_MASK                                           0xffffffff
   #define CCP_RC_WIDTH                                          32
      #define CCP_RC__MSB                                        31
      #define CCP_RC__LSB                                        0
#define CCP_RS                                                   HW_REGISTER_RW( 0x7e801004 ) 
   #define CCP_RS_MASK                                           0xffffffff
   #define CCP_RS_WIDTH                                          32
      #define CCP_RS__MSB                                        31
      #define CCP_RS__LSB                                        0
#define CCP_RDR1                                                 HW_REGISTER_RW( 0x7e801080 ) 
   #define CCP_RDR1_MASK                                         0xffffffff
   #define CCP_RDR1_WIDTH                                        32
      #define CCP_RDR1__MSB                                      31
      #define CCP_RDR1__LSB                                      0
#define CCP_RDR2                                                 HW_REGISTER_RW( 0x7e801084 ) 
   #define CCP_RDR2_MASK                                         0xffffffff
   #define CCP_RDR2_WIDTH                                        32
      #define CCP_RDR2__MSB                                      31
      #define CCP_RDR2__LSB                                      0
#define CCP_RDR3                                                 HW_REGISTER_RW( 0x7e801088 ) 
   #define CCP_RDR3_MASK                                         0xffffffff
   #define CCP_RDR3_WIDTH                                        32
      #define CCP_RDR3__MSB                                      31
      #define CCP_RDR3__LSB                                      0
#define CCP_RC0                                                  HW_REGISTER_RW( 0x7e801100 ) 
   #define CCP_RC0_MASK                                          0xffffffff
   #define CCP_RC0_WIDTH                                         32
      #define CCP_RC0__MSB                                       31
      #define CCP_RC0__LSB                                       0
#define CCP_RPC0                                                 HW_REGISTER_RW( 0x7e801104 ) 
   #define CCP_RPC0_MASK                                         0xffffffff
   #define CCP_RPC0_WIDTH                                        32
      #define CCP_RPC0__MSB                                      31
      #define CCP_RPC0__LSB                                      0
#define CCP_RS0                                                  HW_REGISTER_RW( 0x7e801108 ) 
   #define CCP_RS0_MASK                                          0xffffffff
   #define CCP_RS0_WIDTH                                         32
      #define CCP_RS0__MSB                                       31
      #define CCP_RS0__LSB                                       0
#define CCP_RSA0                                                 HW_REGISTER_RW( 0x7e80110c ) 
   #define CCP_RSA0_MASK                                         0xffffffff
   #define CCP_RSA0_WIDTH                                        32
      #define CCP_RSA0__MSB                                      31
      #define CCP_RSA0__LSB                                      0
#define CCP_REA0                                                 HW_REGISTER_RW( 0x7e801110 ) 
   #define CCP_REA0_MASK                                         0xffffffff
   #define CCP_REA0_WIDTH                                        32
      #define CCP_REA0__MSB                                      31
      #define CCP_REA0__LSB                                      0
#define CCP_RWP0                                                 HW_REGISTER_RW( 0x7e801114 ) 
   #define CCP_RWP0_MASK                                         0xffffffff
   #define CCP_RWP0_WIDTH                                        32
      #define CCP_RWP0__MSB                                      31
      #define CCP_RWP0__LSB                                      0
#define CCP_RBC0                                                 HW_REGISTER_RW( 0x7e801118 ) 
   #define CCP_RBC0_MASK                                         0xffffffff
   #define CCP_RBC0_WIDTH                                        32
      #define CCP_RBC0__MSB                                      31
      #define CCP_RBC0__LSB                                      0
#define CCP_RLS0                                                 HW_REGISTER_RW( 0x7e80111c ) 
   #define CCP_RLS0_MASK                                         0xffffffff
   #define CCP_RLS0_WIDTH                                        32
      #define CCP_RLS0__MSB                                      31
      #define CCP_RLS0__LSB                                      0
#define CCP_RDSA0                                                HW_REGISTER_RW( 0x7e801120 ) 
   #define CCP_RDSA0_MASK                                        0xffffffff
   #define CCP_RDSA0_WIDTH                                       32
      #define CCP_RDSA0__MSB                                     31
      #define CCP_RDSA0__LSB                                     0
#define CCP_RDEA0                                                HW_REGISTER_RW( 0x7e801124 ) 
   #define CCP_RDEA0_MASK                                        0xffffffff
   #define CCP_RDEA0_WIDTH                                       32
      #define CCP_RDEA0__MSB                                     31
      #define CCP_RDEA0__LSB                                     0
#define CCP_RDS0                                                 HW_REGISTER_RW( 0x7e801128 ) 
   #define CCP_RDS0_MASK                                         0xffffffff
   #define CCP_RDS0_WIDTH                                        32
      #define CCP_RDS0__MSB                                      31
      #define CCP_RDS0__LSB                                      0
#define CCP_RC1                                                  HW_REGISTER_RW( 0x7e801200 ) 
   #define CCP_RC1_MASK                                          0xffffffff
   #define CCP_RC1_WIDTH                                         32
      #define CCP_RC1__MSB                                       31
      #define CCP_RC1__LSB                                       0
#define CCP_RPC1                                                 HW_REGISTER_RW( 0x7e801204 ) 
   #define CCP_RPC1_MASK                                         0xffffffff
   #define CCP_RPC1_WIDTH                                        32
      #define CCP_RPC1__MSB                                      31
      #define CCP_RPC1__LSB                                      0
#define CCP_RS1                                                  HW_REGISTER_RW( 0x7e801208 ) 
   #define CCP_RS1_MASK                                          0xffffffff
   #define CCP_RS1_WIDTH                                         32
      #define CCP_RS1__MSB                                       31
      #define CCP_RS1__LSB                                       0
#define CCP_RSA1                                                 HW_REGISTER_RW( 0x7e80120c ) 
   #define CCP_RSA1_MASK                                         0xffffffff
   #define CCP_RSA1_WIDTH                                        32
      #define CCP_RSA1__MSB                                      31
      #define CCP_RSA1__LSB                                      0
#define CCP_REA1                                                 HW_REGISTER_RW( 0x7e801210 ) 
   #define CCP_REA1_MASK                                         0xffffffff
   #define CCP_REA1_WIDTH                                        32
      #define CCP_REA1__MSB                                      31
      #define CCP_REA1__LSB                                      0
#define CCP_RWP1                                                 HW_REGISTER_RW( 0x7e801214 ) 
   #define CCP_RWP1_MASK                                         0xffffffff
   #define CCP_RWP1_WIDTH                                        32
      #define CCP_RWP1__MSB                                      31
      #define CCP_RWP1__LSB                                      0
#define CCP_RBC1                                                 HW_REGISTER_RW( 0x7e801218 ) 
   #define CCP_RBC1_MASK                                         0xffffffff
   #define CCP_RBC1_WIDTH                                        32
      #define CCP_RBC1__MSB                                      31
      #define CCP_RBC1__LSB                                      0
#define CCP_RLS1                                                 HW_REGISTER_RW( 0x7e80121c ) 
   #define CCP_RLS1_MASK                                         0xffffffff
   #define CCP_RLS1_WIDTH                                        32
      #define CCP_RLS1__MSB                                      31
      #define CCP_RLS1__LSB                                      0
#define CCP_RDSA1                                                HW_REGISTER_RW( 0x7e801220 ) 
   #define CCP_RDSA1_MASK                                        0xffffffff
   #define CCP_RDSA1_WIDTH                                       32
      #define CCP_RDSA1__MSB                                     31
      #define CCP_RDSA1__LSB                                     0
#define CCP_RDEA1                                                HW_REGISTER_RW( 0x7e801224 ) 
   #define CCP_RDEA1_MASK                                        0xffffffff
   #define CCP_RDEA1_WIDTH                                       32
      #define CCP_RDEA1__MSB                                     31
      #define CCP_RDEA1__LSB                                     0
#define CCP_RDS1                                                 HW_REGISTER_RW( 0x7e801228 ) 
   #define CCP_RDS1_MASK                                         0xffffffff
   #define CCP_RDS1_WIDTH                                        32
      #define CCP_RDS1__MSB                                      31
      #define CCP_RDS1__LSB                                      0