// This file was generated by the create_regs script #define DSI0_BASE 0x7e209000 #define DSI0_APB_ID 0x00647369 #define DSI0_CTRL HW_REGISTER_RW( 0x7e209000 ) #define DSI0_CTRL_MASK 0x00000007 #define DSI0_CTRL_WIDTH 3 #define DSI0_CTRL_RESET 0000000000 #define DSI0_CTRL_CTRL2_BITS 2:2 #define DSI0_CTRL_CTRL2_SET 0x00000004 #define DSI0_CTRL_CTRL2_CLR 0xfffffffb #define DSI0_CTRL_CTRL2_MSB 2 #define DSI0_CTRL_CTRL2_LSB 2 #define DSI0_CTRL_CTRL1_BITS 1:1 #define DSI0_CTRL_CTRL1_SET 0x00000002 #define DSI0_CTRL_CTRL1_CLR 0xfffffffd #define DSI0_CTRL_CTRL1_MSB 1 #define DSI0_CTRL_CTRL1_LSB 1 #define DSI0_CTRL_CTRL0_BITS 0:0 #define DSI0_CTRL_CTRL0_SET 0x00000001 #define DSI0_CTRL_CTRL0_CLR 0xfffffffe #define DSI0_CTRL_CTRL0_MSB 0 #define DSI0_CTRL_CTRL0_LSB 0 #define DSI0_CMD_PKTC HW_REGISTER_RW( 0x7e209004 ) #define DSI0_CMD_PKTC_MASK 0xffffffff #define DSI0_CMD_PKTC_WIDTH 32 #define DSI0_CMD_PKTC_RESET 0000000000 #define DSI0_CMD_PKTH HW_REGISTER_RW( 0x7e209008 ) #define DSI0_CMD_PKTH_MASK 0xffffffff #define DSI0_CMD_PKTH_WIDTH 32 #define DSI0_CMD_PKTH_RESET 0000000000 #define DSI0_RX1_PKTH HW_REGISTER_RO( 0x7e20900c ) #define DSI0_RX1_PKTH_MASK 0xffffffff #define DSI0_RX1_PKTH_WIDTH 32 #define DSI0_RX2_PKTH HW_REGISTER_RO( 0x7e209010 ) #define DSI0_RX2_PKTH_MASK 0xffffffff #define DSI0_RX2_PKTH_WIDTH 32 #define DSI0_CMD_DATAF HW_REGISTER_RW( 0x7e209014 ) #define DSI0_CMD_DATAF_MASK 0x000000ff #define DSI0_CMD_DATAF_WIDTH 8 #define DSI0_DISP0_CTR HW_REGISTER_RW( 0x7e209018 ) #define DSI0_DISP0_CTR_MASK 0xffffffff #define DSI0_DISP0_CTR_WIDTH 32 #define DSI0_DISP0_CTR_RESET 0000000000 #define DSI0_DISP1_CTR HW_REGISTER_RW( 0x7e20901c ) #define DSI0_DISP1_CTR_MASK 0xffffffff #define DSI0_DISP1_CTR_WIDTH 32 #define DSI0_DISP1_CTR_RESET 0000000000 #define DSI0_PIX_FIFO HW_REGISTER_RW( 0x7e209020 ) #define DSI0_PIX_FIFO_MASK 0xffffffff #define DSI0_PIX_FIFO_WIDTH 32 #define DSI0_INT_STAT HW_REGISTER_RW( 0x7e209024 ) #define DSI0_INT_STAT_MASK 0xffffffff #define DSI0_INT_STAT_WIDTH 32 #define DSI0_INT_EN HW_REGISTER_RW( 0x7e209028 ) #define DSI0_INT_EN_MASK 0x0fffffff #define DSI0_INT_EN_WIDTH 28 #define DSI0_INT_EN_RESET 0000000000 #define DSI0_STAT HW_REGISTER_RW( 0x7e20902c ) #define DSI0_STAT_MASK 0xffffffff #define DSI0_STAT_WIDTH 32 #define DSI0_HSTX_TO_C HW_REGISTER_RW( 0x7e209030 ) #define DSI0_HSTX_TO_C_MASK 0x00ffffff #define DSI0_HSTX_TO_C_WIDTH 24 #define DSI0_HSTX_TO_C_RESET 0000000000 #define DSI0_LPRX_TO_C HW_REGISTER_RW( 0x7e209034 ) #define DSI0_LPRX_TO_C_MASK 0xffffffff #define DSI0_LPRX_TO_C_WIDTH 32 #define DSI0_LPRX_TO_C_RESET 0000000000 #define DSI0_TA_TO_CNT HW_REGISTER_RW( 0x7e209038 ) #define DSI0_TA_TO_CNT_MASK 0xffffffff #define DSI0_TA_TO_CNT_WIDTH 32 #define DSI0_TA_TO_CNT_RESET 0000000000 #define DSI0_PR_TO_CNT HW_REGISTER_RW( 0x7e20903c ) #define DSI0_PR_TO_CNT_MASK 0xffffffff #define DSI0_PR_TO_CNT_WIDTH 32 #define DSI0_PR_TO_CNT_RESET 0000000000 #define DSI0_PHYC HW_REGISTER_RW( 0x7e209040 ) #define DSI0_PHYC_MASK 0x0003f777 #define DSI0_PHYC_WIDTH 18 #define DSI0_PHYC_RESET 0000000000 #define DSI0_PHYC_dsi_esc_lpdt_BITS 17:12 #define DSI0_PHYC_dsi_esc_lpdt_SET 0x0003f000 #define DSI0_PHYC_dsi_esc_lpdt_CLR 0xfffc0fff #define DSI0_PHYC_dsi_esc_lpdt_MSB 17 #define DSI0_PHYC_dsi_esc_lpdt_LSB 12 #define DSI0_PHYC_txhsclk_cont_sync_BITS 10:10 #define DSI0_PHYC_txhsclk_cont_sync_SET 0x00000400 #define DSI0_PHYC_txhsclk_cont_sync_CLR 0xfffffbff #define DSI0_PHYC_txhsclk_cont_sync_MSB 10 #define DSI0_PHYC_txhsclk_cont_sync_LSB 10 #define DSI0_PHYC_txulps_clk_sync_BITS 9:9 #define DSI0_PHYC_txulps_clk_sync_SET 0x00000200 #define DSI0_PHYC_txulps_clk_sync_CLR 0xfffffdff #define DSI0_PHYC_txulps_clk_sync_MSB 9 #define DSI0_PHYC_txulps_clk_sync_LSB 9 #define DSI0_PHYC_clane_hsen_sync_BITS 8:8 #define DSI0_PHYC_clane_hsen_sync_SET 0x00000100 #define DSI0_PHYC_clane_hsen_sync_CLR 0xfffffeff #define DSI0_PHYC_clane_hsen_sync_MSB 8 #define DSI0_PHYC_clane_hsen_sync_LSB 8 #define DSI0_PHYC_txulpshs_1_sync_BITS 6:6 #define DSI0_PHYC_txulpshs_1_sync_SET 0x00000040 #define DSI0_PHYC_txulpshs_1_sync_CLR 0xffffffbf #define DSI0_PHYC_txulpshs_1_sync_MSB 6 #define DSI0_PHYC_txulpshs_1_sync_LSB 6 #define DSI0_PHYC_dlane_hsen_1_sync_BITS 5:5 #define DSI0_PHYC_dlane_hsen_1_sync_SET 0x00000020 #define DSI0_PHYC_dlane_hsen_1_sync_CLR 0xffffffdf #define DSI0_PHYC_dlane_hsen_1_sync_MSB 5 #define DSI0_PHYC_dlane_hsen_1_sync_LSB 5 #define DSI0_PHYC_unused_BITS 4:4 #define DSI0_PHYC_unused_SET 0x00000010 #define DSI0_PHYC_unused_CLR 0xffffffef #define DSI0_PHYC_unused_MSB 4 #define DSI0_PHYC_unused_LSB 4 #define DSI0_PHYC_forcehsstop_sync_BITS 2:2 #define DSI0_PHYC_forcehsstop_sync_SET 0x00000004 #define DSI0_PHYC_forcehsstop_sync_CLR 0xfffffffb #define DSI0_PHYC_forcehsstop_sync_MSB 2 #define DSI0_PHYC_forcehsstop_sync_LSB 2 #define DSI0_PHYC_txulpshs_0_sync_BITS 1:1 #define DSI0_PHYC_txulpshs_0_sync_SET 0x00000002 #define DSI0_PHYC_txulpshs_0_sync_CLR 0xfffffffd #define DSI0_PHYC_txulpshs_0_sync_MSB 1 #define DSI0_PHYC_txulpshs_0_sync_LSB 1 #define DSI0_PHYC_dlane_hsen_0_sync_BITS 0:0 #define DSI0_PHYC_dlane_hsen_0_sync_SET 0x00000001 #define DSI0_PHYC_dlane_hsen_0_sync_CLR 0xfffffffe #define DSI0_PHYC_dlane_hsen_0_sync_MSB 0 #define DSI0_PHYC_dlane_hsen_0_sync_LSB 0 #define DSI0_HS_CLT0 HW_REGISTER_RW( 0x7e209044 ) #define DSI0_HS_CLT0_MASK 0xfffffffc #define DSI0_HS_CLT0_WIDTH 32 #define DSI0_HS_CLT0_RESET 0000000000 #define DSI0_HS_CLT1 HW_REGISTER_RW( 0x7e209048 ) #define DSI0_HS_CLT1_MASK 0x000003fc #define DSI0_HS_CLT1_WIDTH 10 #define DSI0_HS_CLT1_RESET 0000000000 #define DSI0_HS_CLT2 HW_REGISTER_RW( 0x7e20904c ) #define DSI0_HS_CLT2_MASK 0x000003fc #define DSI0_HS_CLT2_WIDTH 10 #define DSI0_HS_CLT2_RESET 0000000000 #define DSI0_HS_DLT3 HW_REGISTER_RW( 0x7e209050 ) #define DSI0_HS_DLT3_MASK 0x000003fc #define DSI0_HS_DLT3_WIDTH 10 #define DSI0_HS_DLT3_RESET 0000000000 #define DSI0_HS_DLT4 HW_REGISTER_RW( 0x7e209054 ) #define DSI0_HS_DLT4_MASK 0x000003fc #define DSI0_HS_DLT4_WIDTH 10 #define DSI0_HS_DLT4_RESET 0000000000 #define DSI0_HS_DLT5 HW_REGISTER_RW( 0x7e209058 ) #define DSI0_HS_DLT5_MASK 0x000003fc #define DSI0_HS_DLT5_WIDTH 10 #define DSI0_HS_DLT5_RESET 0000000000 #define DSI0_LP_DLT6 HW_REGISTER_RW( 0x7e20905c ) #define DSI0_LP_DLT6_MASK 0x000003fc #define DSI0_LP_DLT6_WIDTH 10 #define DSI0_LP_DLT6_RESET 0000000000 #define DSI0_LP_DLT7 HW_REGISTER_RW( 0x7e209060 ) #define DSI0_LP_DLT7_MASK 0x000003fc #define DSI0_LP_DLT7_WIDTH 10 #define DSI0_LP_DLT7_RESET 0000000000 #define DSI0_PHY_AFEC0 HW_REGISTER_RW( 0x7e209064 ) #define DSI0_PHY_AFEC0_MASK 0x000000ff #define DSI0_PHY_AFEC0_WIDTH 8 #define DSI0_PHY_AFEC0_RESET 0000000000 #define DSI0_PHY_AFEC1 HW_REGISTER_RW( 0x7e209068 ) #define DSI0_PHY_AFEC1_MASK 0xffffffff #define DSI0_PHY_AFEC1_WIDTH 32 #define DSI0_PHY_AFEC1_RESET 0000000000 #define DSI0_TST_SEL HW_REGISTER_RW( 0x7e20906c ) #define DSI0_TST_SEL_MASK 0x000000ff #define DSI0_TST_SEL_WIDTH 8 #define DSI0_TST_SEL_RESET 0000000000 #define DSI0_TST_MON HW_REGISTER_RW( 0x7e209070 ) #define DSI0_TST_MON_MASK 0x000000ff #define DSI0_TST_MON_WIDTH 8 #define DSI0_TST_MON_RESET 0000000000