// This file was generated by the create_regs script #define EMMC_BASE 0x7e300000 #define EMMC_ARG2 HW_REGISTER_RW( 0x7e300000 ) #define EMMC_ARG2_MASK 0xffffffff #define EMMC_ARG2_WIDTH 32 #define EMMC_ARG2_RESET 0000000000 #define EMMC_BLKSIZECNT HW_REGISTER_RW( 0x7e300004 ) #define EMMC_BLKSIZECNT_MASK 0xffffffff #define EMMC_BLKSIZECNT_WIDTH 32 #define EMMC_BLKSIZECNT_RESET 0000000000 #define EMMC_BLKSIZECNT_BLKCNT_BITS 31:16 #define EMMC_BLKSIZECNT_BLKCNT_SET 0xffff0000 #define EMMC_BLKSIZECNT_BLKCNT_CLR 0x0000ffff #define EMMC_BLKSIZECNT_BLKCNT_MSB 31 #define EMMC_BLKSIZECNT_BLKCNT_LSB 16 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_BITS 15:15 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_SET 0x00008000 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_CLR 0xffff7fff #define EMMC_BLKSIZECNT_BLKSIZE_MS1_MSB 15 #define EMMC_BLKSIZECNT_BLKSIZE_MS1_LSB 15 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_BITS 14:12 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_SET 0x00007000 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_CLR 0xffff8fff #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_MSB 14 #define EMMC_BLKSIZECNT_SDMA_BLKSIZE_LSB 12 #define EMMC_BLKSIZECNT_BLKSIZE_BITS 11:0 #define EMMC_BLKSIZECNT_BLKSIZE_SET 0x00000fff #define EMMC_BLKSIZECNT_BLKSIZE_CLR 0xfffff000 #define EMMC_BLKSIZECNT_BLKSIZE_MSB 11 #define EMMC_BLKSIZECNT_BLKSIZE_LSB 0 #define EMMC_ARG1 HW_REGISTER_RW( 0x7e300008 ) #define EMMC_ARG1_MASK 0xffffffff #define EMMC_ARG1_WIDTH 32 #define EMMC_ARG1_RESET 0000000000 #define EMMC_CMDTM HW_REGISTER_RW( 0x7e30000c ) #define EMMC_CMDTM_MASK 0x3ffb003f #define EMMC_CMDTM_WIDTH 30 #define EMMC_CMDTM_RESET 0000000000 #define EMMC_CMDTM_CMD_INDEX_BITS 29:24 #define EMMC_CMDTM_CMD_INDEX_SET 0x3f000000 #define EMMC_CMDTM_CMD_INDEX_CLR 0xc0ffffff #define EMMC_CMDTM_CMD_INDEX_MSB 29 #define EMMC_CMDTM_CMD_INDEX_LSB 24 #define EMMC_CMDTM_CMD_TYPE_BITS 23:22 #define EMMC_CMDTM_CMD_TYPE_SET 0x00c00000 #define EMMC_CMDTM_CMD_TYPE_CLR 0xff3fffff #define EMMC_CMDTM_CMD_TYPE_MSB 23 #define EMMC_CMDTM_CMD_TYPE_LSB 22 #define EMMC_CMDTM_CMD_ISDATA_BITS 21:21 #define EMMC_CMDTM_CMD_ISDATA_SET 0x00200000 #define EMMC_CMDTM_CMD_ISDATA_CLR 0xffdfffff #define EMMC_CMDTM_CMD_ISDATA_MSB 21 #define EMMC_CMDTM_CMD_ISDATA_LSB 21 #define EMMC_CMDTM_CMD_IXCHK_EN_BITS 20:20 #define EMMC_CMDTM_CMD_IXCHK_EN_SET 0x00100000 #define EMMC_CMDTM_CMD_IXCHK_EN_CLR 0xffefffff #define EMMC_CMDTM_CMD_IXCHK_EN_MSB 20 #define EMMC_CMDTM_CMD_IXCHK_EN_LSB 20 #define EMMC_CMDTM_CMD_CRCCHK_EN_BITS 19:19 #define EMMC_CMDTM_CMD_CRCCHK_EN_SET 0x00080000 #define EMMC_CMDTM_CMD_CRCCHK_EN_CLR 0xfff7ffff #define EMMC_CMDTM_CMD_CRCCHK_EN_MSB 19 #define EMMC_CMDTM_CMD_CRCCHK_EN_LSB 19 #define EMMC_CMDTM_CMD_RSPNS_TYPE_BITS 17:16 #define EMMC_CMDTM_CMD_RSPNS_TYPE_SET 0x00030000 #define EMMC_CMDTM_CMD_RSPNS_TYPE_CLR 0xfffcffff #define EMMC_CMDTM_CMD_RSPNS_TYPE_MSB 17 #define EMMC_CMDTM_CMD_RSPNS_TYPE_LSB 16 #define EMMC_CMDTM_TM_MULTI_BLOCK_BITS 5:5 #define EMMC_CMDTM_TM_MULTI_BLOCK_SET 0x00000020 #define EMMC_CMDTM_TM_MULTI_BLOCK_CLR 0xffffffdf #define EMMC_CMDTM_TM_MULTI_BLOCK_MSB 5 #define EMMC_CMDTM_TM_MULTI_BLOCK_LSB 5 #define EMMC_CMDTM_TM_DAT_DIR_BITS 4:4 #define EMMC_CMDTM_TM_DAT_DIR_SET 0x00000010 #define EMMC_CMDTM_TM_DAT_DIR_CLR 0xffffffef #define EMMC_CMDTM_TM_DAT_DIR_MSB 4 #define EMMC_CMDTM_TM_DAT_DIR_LSB 4 #define EMMC_CMDTM_TM_AUTO_CMD_EN_BITS 3:2 #define EMMC_CMDTM_TM_AUTO_CMD_EN_SET 0x0000000c #define EMMC_CMDTM_TM_AUTO_CMD_EN_CLR 0xfffffff3 #define EMMC_CMDTM_TM_AUTO_CMD_EN_MSB 3 #define EMMC_CMDTM_TM_AUTO_CMD_EN_LSB 2 #define EMMC_CMDTM_TM_BLKCNT_EN_BITS 1:1 #define EMMC_CMDTM_TM_BLKCNT_EN_SET 0x00000002 #define EMMC_CMDTM_TM_BLKCNT_EN_CLR 0xfffffffd #define EMMC_CMDTM_TM_BLKCNT_EN_MSB 1 #define EMMC_CMDTM_TM_BLKCNT_EN_LSB 1 #define EMMC_CMDTM_TM_DMA_EN_BITS 0:0 #define EMMC_CMDTM_TM_DMA_EN_SET 0x00000001 #define EMMC_CMDTM_TM_DMA_EN_CLR 0xfffffffe #define EMMC_CMDTM_TM_DMA_EN_MSB 0 #define EMMC_CMDTM_TM_DMA_EN_LSB 0 #define EMMC_RESP0 HW_REGISTER_RW( 0x7e300010 ) #define EMMC_RESP0_MASK 0xffffffff #define EMMC_RESP0_WIDTH 32 #define EMMC_RESP0_RESET 0000000000 #define EMMC_RESP1 HW_REGISTER_RW( 0x7e300014 ) #define EMMC_RESP1_MASK 0xffffffff #define EMMC_RESP1_WIDTH 32 #define EMMC_RESP1_RESET 0000000000 #define EMMC_RESP2 HW_REGISTER_RW( 0x7e300018 ) #define EMMC_RESP2_MASK 0xffffffff #define EMMC_RESP2_WIDTH 32 #define EMMC_RESP2_RESET 0000000000 #define EMMC_RESP3 HW_REGISTER_RW( 0x7e30001c ) #define EMMC_RESP3_MASK 0xffffffff #define EMMC_RESP3_WIDTH 32 #define EMMC_RESP3_RESET 0000000000 #define EMMC_DATA HW_REGISTER_RW( 0x7e300020 ) #define EMMC_DATA_MASK 0xffffffff #define EMMC_DATA_WIDTH 32 #define EMMC_DATA_RESET 0000000000 #define EMMC_STATUS HW_REGISTER_RW( 0x7e300024 ) #define EMMC_STATUS_MASK 0x1fff0f0f #define EMMC_STATUS_WIDTH 29 #define EMMC_STATUS_RESET 0x1ff00000 #define EMMC_STATUS_DAT_LEVEL1_BITS 28:25 #define EMMC_STATUS_DAT_LEVEL1_SET 0x1e000000 #define EMMC_STATUS_DAT_LEVEL1_CLR 0xe1ffffff #define EMMC_STATUS_DAT_LEVEL1_MSB 28 #define EMMC_STATUS_DAT_LEVEL1_LSB 25 #define EMMC_STATUS_CMD_LEVEL_BITS 24:24 #define EMMC_STATUS_CMD_LEVEL_SET 0x01000000 #define EMMC_STATUS_CMD_LEVEL_CLR 0xfeffffff #define EMMC_STATUS_CMD_LEVEL_MSB 24 #define EMMC_STATUS_CMD_LEVEL_LSB 24 #define EMMC_STATUS_DAT_LEVEL0_BITS 23:20 #define EMMC_STATUS_DAT_LEVEL0_SET 0x00f00000 #define EMMC_STATUS_DAT_LEVEL0_CLR 0xff0fffff #define EMMC_STATUS_DAT_LEVEL0_MSB 23 #define EMMC_STATUS_DAT_LEVEL0_LSB 20 #define EMMC_STATUS_WRT_PROTECT_BITS 19:19 #define EMMC_STATUS_WRT_PROTECT_SET 0x00080000 #define EMMC_STATUS_WRT_PROTECT_CLR 0xfff7ffff #define EMMC_STATUS_WRT_PROTECT_MSB 19 #define EMMC_STATUS_WRT_PROTECT_LSB 19 #define EMMC_STATUS_CARD_DETECT_BITS 18:18 #define EMMC_STATUS_CARD_DETECT_SET 0x00040000 #define EMMC_STATUS_CARD_DETECT_CLR 0xfffbffff #define EMMC_STATUS_CARD_DETECT_MSB 18 #define EMMC_STATUS_CARD_DETECT_LSB 18 #define EMMC_STATUS_CARD_STABLE_BITS 17:17 #define EMMC_STATUS_CARD_STABLE_SET 0x00020000 #define EMMC_STATUS_CARD_STABLE_CLR 0xfffdffff #define EMMC_STATUS_CARD_STABLE_MSB 17 #define EMMC_STATUS_CARD_STABLE_LSB 17 #define EMMC_STATUS_CARD_INSERT_BITS 16:16 #define EMMC_STATUS_CARD_INSERT_SET 0x00010000 #define EMMC_STATUS_CARD_INSERT_CLR 0xfffeffff #define EMMC_STATUS_CARD_INSERT_MSB 16 #define EMMC_STATUS_CARD_INSERT_LSB 16 #define EMMC_STATUS_NEW_READ_DATA_BITS 11:11 #define EMMC_STATUS_NEW_READ_DATA_SET 0x00000800 #define EMMC_STATUS_NEW_READ_DATA_CLR 0xfffff7ff #define EMMC_STATUS_NEW_READ_DATA_MSB 11 #define EMMC_STATUS_NEW_READ_DATA_LSB 11 #define EMMC_STATUS_NEW_WRITE_DATA_BITS 10:10 #define EMMC_STATUS_NEW_WRITE_DATA_SET 0x00000400 #define EMMC_STATUS_NEW_WRITE_DATA_CLR 0xfffffbff #define EMMC_STATUS_NEW_WRITE_DATA_MSB 10 #define EMMC_STATUS_NEW_WRITE_DATA_LSB 10 #define EMMC_STATUS_READ_TRANSFER_BITS 9:9 #define EMMC_STATUS_READ_TRANSFER_SET 0x00000200 #define EMMC_STATUS_READ_TRANSFER_CLR 0xfffffdff #define EMMC_STATUS_READ_TRANSFER_MSB 9 #define EMMC_STATUS_READ_TRANSFER_LSB 9 #define EMMC_STATUS_WRITE_TRANSFER_BITS 8:8 #define EMMC_STATUS_WRITE_TRANSFER_SET 0x00000100 #define EMMC_STATUS_WRITE_TRANSFER_CLR 0xfffffeff #define EMMC_STATUS_WRITE_TRANSFER_MSB 8 #define EMMC_STATUS_WRITE_TRANSFER_LSB 8 #define EMMC_STATUS_RETUNING_REQ_BITS 3:3 #define EMMC_STATUS_RETUNING_REQ_SET 0x00000008 #define EMMC_STATUS_RETUNING_REQ_CLR 0xfffffff7 #define EMMC_STATUS_RETUNING_REQ_MSB 3 #define EMMC_STATUS_RETUNING_REQ_LSB 3 #define EMMC_STATUS_DAT_ACTIVE_BITS 2:2 #define EMMC_STATUS_DAT_ACTIVE_SET 0x00000004 #define EMMC_STATUS_DAT_ACTIVE_CLR 0xfffffffb #define EMMC_STATUS_DAT_ACTIVE_MSB 2 #define EMMC_STATUS_DAT_ACTIVE_LSB 2 #define EMMC_STATUS_DAT_INHIBIT_BITS 1:1 #define EMMC_STATUS_DAT_INHIBIT_SET 0x00000002 #define EMMC_STATUS_DAT_INHIBIT_CLR 0xfffffffd #define EMMC_STATUS_DAT_INHIBIT_MSB 1 #define EMMC_STATUS_DAT_INHIBIT_LSB 1 #define EMMC_STATUS_CMD_INHIBIT_BITS 0:0 #define EMMC_STATUS_CMD_INHIBIT_SET 0x00000001 #define EMMC_STATUS_CMD_INHIBIT_CLR 0xfffffffe #define EMMC_STATUS_CMD_INHIBIT_MSB 0 #define EMMC_STATUS_CMD_INHIBIT_LSB 0 #define EMMC_CONTROL0 HW_REGISTER_RW( 0x7e300028 ) #define EMMC_CONTROL0_MASK 0x07ff1fff #define EMMC_CONTROL0_WIDTH 27 #define EMMC_CONTROL0_RESET 0000000000 #define EMMC_CONTROL0_WAKE_ONREM_EN_BITS 26:26 #define EMMC_CONTROL0_WAKE_ONREM_EN_SET 0x04000000 #define EMMC_CONTROL0_WAKE_ONREM_EN_CLR 0xfbffffff #define EMMC_CONTROL0_WAKE_ONREM_EN_MSB 26 #define EMMC_CONTROL0_WAKE_ONREM_EN_LSB 26 #define EMMC_CONTROL0_WAKE_ONINS_EN_BITS 25:25 #define EMMC_CONTROL0_WAKE_ONINS_EN_SET 0x02000000 #define EMMC_CONTROL0_WAKE_ONINS_EN_CLR 0xfdffffff #define EMMC_CONTROL0_WAKE_ONINS_EN_MSB 25 #define EMMC_CONTROL0_WAKE_ONINS_EN_LSB 25 #define EMMC_CONTROL0_WAKE_ONINT_EN_BITS 24:24 #define EMMC_CONTROL0_WAKE_ONINT_EN_SET 0x01000000 #define EMMC_CONTROL0_WAKE_ONINT_EN_CLR 0xfeffffff #define EMMC_CONTROL0_WAKE_ONINT_EN_MSB 24 #define EMMC_CONTROL0_WAKE_ONINT_EN_LSB 24 #define EMMC_CONTROL0_ALT_BOOT_EN_BITS 22:22 #define EMMC_CONTROL0_ALT_BOOT_EN_SET 0x00400000 #define EMMC_CONTROL0_ALT_BOOT_EN_CLR 0xffbfffff #define EMMC_CONTROL0_ALT_BOOT_EN_MSB 22 #define EMMC_CONTROL0_ALT_BOOT_EN_LSB 22 #define EMMC_CONTROL0_BOOT_EN_BITS 21:21 #define EMMC_CONTROL0_BOOT_EN_SET 0x00200000 #define EMMC_CONTROL0_BOOT_EN_CLR 0xffdfffff #define EMMC_CONTROL0_BOOT_EN_MSB 21 #define EMMC_CONTROL0_BOOT_EN_LSB 21 #define EMMC_CONTROL0_SPI_MODE_BITS 20:20 #define EMMC_CONTROL0_SPI_MODE_SET 0x00100000 #define EMMC_CONTROL0_SPI_MODE_CLR 0xffefffff #define EMMC_CONTROL0_SPI_MODE_MSB 20 #define EMMC_CONTROL0_SPI_MODE_LSB 20 #define EMMC_CONTROL0_GAP_IEN_BITS 19:19 #define EMMC_CONTROL0_GAP_IEN_SET 0x00080000 #define EMMC_CONTROL0_GAP_IEN_CLR 0xfff7ffff #define EMMC_CONTROL0_GAP_IEN_MSB 19 #define EMMC_CONTROL0_GAP_IEN_LSB 19 #define EMMC_CONTROL0_READWAIT_EN_BITS 18:18 #define EMMC_CONTROL0_READWAIT_EN_SET 0x00040000 #define EMMC_CONTROL0_READWAIT_EN_CLR 0xfffbffff #define EMMC_CONTROL0_READWAIT_EN_MSB 18 #define EMMC_CONTROL0_READWAIT_EN_LSB 18 #define EMMC_CONTROL0_GAP_RESTART_BITS 17:17 #define EMMC_CONTROL0_GAP_RESTART_SET 0x00020000 #define EMMC_CONTROL0_GAP_RESTART_CLR 0xfffdffff #define EMMC_CONTROL0_GAP_RESTART_MSB 17 #define EMMC_CONTROL0_GAP_RESTART_LSB 17 #define EMMC_CONTROL0_GAP_STOP_BITS 16:16 #define EMMC_CONTROL0_GAP_STOP_SET 0x00010000 #define EMMC_CONTROL0_GAP_STOP_CLR 0xfffeffff #define EMMC_CONTROL0_GAP_STOP_MSB 16 #define EMMC_CONTROL0_GAP_STOP_LSB 16 #define EMMC_CONTROL0_PWCTL_HWRST_BITS 12:12 #define EMMC_CONTROL0_PWCTL_HWRST_SET 0x00001000 #define EMMC_CONTROL0_PWCTL_HWRST_CLR 0xffffefff #define EMMC_CONTROL0_PWCTL_HWRST_MSB 12 #define EMMC_CONTROL0_PWCTL_HWRST_LSB 12 #define EMMC_CONTROL0_PWCTL_SDVOLTS_BITS 11:9 #define EMMC_CONTROL0_PWCTL_SDVOLTS_SET 0x00000e00 #define EMMC_CONTROL0_PWCTL_SDVOLTS_CLR 0xfffff1ff #define EMMC_CONTROL0_PWCTL_SDVOLTS_MSB 11 #define EMMC_CONTROL0_PWCTL_SDVOLTS_LSB 9 #define EMMC_CONTROL0_PWCTL_ON_BITS 8:8 #define EMMC_CONTROL0_PWCTL_ON_SET 0x00000100 #define EMMC_CONTROL0_PWCTL_ON_CLR 0xfffffeff #define EMMC_CONTROL0_PWCTL_ON_MSB 8 #define EMMC_CONTROL0_PWCTL_ON_LSB 8 #define EMMC_CONTROL0_HCTL_CRDDET_S_BITS 7:7 #define EMMC_CONTROL0_HCTL_CRDDET_S_SET 0x00000080 #define EMMC_CONTROL0_HCTL_CRDDET_S_CLR 0xffffff7f #define EMMC_CONTROL0_HCTL_CRDDET_S_MSB 7 #define EMMC_CONTROL0_HCTL_CRDDET_S_LSB 7 #define EMMC_CONTROL0_HCTL_CRDDET_BITS 6:6 #define EMMC_CONTROL0_HCTL_CRDDET_SET 0x00000040 #define EMMC_CONTROL0_HCTL_CRDDET_CLR 0xffffffbf #define EMMC_CONTROL0_HCTL_CRDDET_MSB 6 #define EMMC_CONTROL0_HCTL_CRDDET_LSB 6 #define EMMC_CONTROL0_HCTL_8BIT_BITS 5:5 #define EMMC_CONTROL0_HCTL_8BIT_SET 0x00000020 #define EMMC_CONTROL0_HCTL_8BIT_CLR 0xffffffdf #define EMMC_CONTROL0_HCTL_8BIT_MSB 5 #define EMMC_CONTROL0_HCTL_8BIT_LSB 5 #define EMMC_CONTROL0_HCTL_DMA_BITS 4:3 #define EMMC_CONTROL0_HCTL_DMA_SET 0x00000018 #define EMMC_CONTROL0_HCTL_DMA_CLR 0xffffffe7 #define EMMC_CONTROL0_HCTL_DMA_MSB 4 #define EMMC_CONTROL0_HCTL_DMA_LSB 3 #define EMMC_CONTROL0_HCTL_HS_EN_BITS 2:2 #define EMMC_CONTROL0_HCTL_HS_EN_SET 0x00000004 #define EMMC_CONTROL0_HCTL_HS_EN_CLR 0xfffffffb #define EMMC_CONTROL0_HCTL_HS_EN_MSB 2 #define EMMC_CONTROL0_HCTL_HS_EN_LSB 2 #define EMMC_CONTROL0_HCTL_DWIDTH_BITS 1:1 #define EMMC_CONTROL0_HCTL_DWIDTH_SET 0x00000002 #define EMMC_CONTROL0_HCTL_DWIDTH_CLR 0xfffffffd #define EMMC_CONTROL0_HCTL_DWIDTH_MSB 1 #define EMMC_CONTROL0_HCTL_DWIDTH_LSB 1 #define EMMC_CONTROL0_HCTL_LED_BITS 0:0 #define EMMC_CONTROL0_HCTL_LED_SET 0x00000001 #define EMMC_CONTROL0_HCTL_LED_CLR 0xfffffffe #define EMMC_CONTROL0_HCTL_LED_MSB 0 #define EMMC_CONTROL0_HCTL_LED_LSB 0 #define EMMC_CONTROL1 HW_REGISTER_RW( 0x7e30002c ) #define EMMC_CONTROL1_MASK 0x070fffe7 #define EMMC_CONTROL1_WIDTH 27 #define EMMC_CONTROL1_RESET 0000000000 #define EMMC_CONTROL1_SRST_DATA_BITS 26:26 #define EMMC_CONTROL1_SRST_DATA_SET 0x04000000 #define EMMC_CONTROL1_SRST_DATA_CLR 0xfbffffff #define EMMC_CONTROL1_SRST_DATA_MSB 26 #define EMMC_CONTROL1_SRST_DATA_LSB 26 #define EMMC_CONTROL1_SRST_CMD_BITS 25:25 #define EMMC_CONTROL1_SRST_CMD_SET 0x02000000 #define EMMC_CONTROL1_SRST_CMD_CLR 0xfdffffff #define EMMC_CONTROL1_SRST_CMD_MSB 25 #define EMMC_CONTROL1_SRST_CMD_LSB 25 #define EMMC_CONTROL1_SRST_HC_BITS 24:24 #define EMMC_CONTROL1_SRST_HC_SET 0x01000000 #define EMMC_CONTROL1_SRST_HC_CLR 0xfeffffff #define EMMC_CONTROL1_SRST_HC_MSB 24 #define EMMC_CONTROL1_SRST_HC_LSB 24 #define EMMC_CONTROL1_DATA_TOUNIT_BITS 19:16 #define EMMC_CONTROL1_DATA_TOUNIT_SET 0x000f0000 #define EMMC_CONTROL1_DATA_TOUNIT_CLR 0xfff0ffff #define EMMC_CONTROL1_DATA_TOUNIT_MSB 19 #define EMMC_CONTROL1_DATA_TOUNIT_LSB 16 #define EMMC_CONTROL1_CLK_FREQ8_BITS 15:8 #define EMMC_CONTROL1_CLK_FREQ8_SET 0x0000ff00 #define EMMC_CONTROL1_CLK_FREQ8_CLR 0xffff00ff #define EMMC_CONTROL1_CLK_FREQ8_MSB 15 #define EMMC_CONTROL1_CLK_FREQ8_LSB 8 #define EMMC_CONTROL1_CLK_FREQ_MS2_BITS 7:6 #define EMMC_CONTROL1_CLK_FREQ_MS2_SET 0x000000c0 #define EMMC_CONTROL1_CLK_FREQ_MS2_CLR 0xffffff3f #define EMMC_CONTROL1_CLK_FREQ_MS2_MSB 7 #define EMMC_CONTROL1_CLK_FREQ_MS2_LSB 6 #define EMMC_CONTROL1_CLK_GENSEL_BITS 5:5 #define EMMC_CONTROL1_CLK_GENSEL_SET 0x00000020 #define EMMC_CONTROL1_CLK_GENSEL_CLR 0xffffffdf #define EMMC_CONTROL1_CLK_GENSEL_MSB 5 #define EMMC_CONTROL1_CLK_GENSEL_LSB 5 #define EMMC_CONTROL1_CLK_EN_BITS 2:2 #define EMMC_CONTROL1_CLK_EN_SET 0x00000004 #define EMMC_CONTROL1_CLK_EN_CLR 0xfffffffb #define EMMC_CONTROL1_CLK_EN_MSB 2 #define EMMC_CONTROL1_CLK_EN_LSB 2 #define EMMC_CONTROL1_CLK_STABLE_BITS 1:1 #define EMMC_CONTROL1_CLK_STABLE_SET 0x00000002 #define EMMC_CONTROL1_CLK_STABLE_CLR 0xfffffffd #define EMMC_CONTROL1_CLK_STABLE_MSB 1 #define EMMC_CONTROL1_CLK_STABLE_LSB 1 #define EMMC_CONTROL1_CLK_INTLEN_BITS 0:0 #define EMMC_CONTROL1_CLK_INTLEN_SET 0x00000001 #define EMMC_CONTROL1_CLK_INTLEN_CLR 0xfffffffe #define EMMC_CONTROL1_CLK_INTLEN_MSB 0 #define EMMC_CONTROL1_CLK_INTLEN_LSB 0 #define EMMC_INTERRUPT HW_REGISTER_RW( 0x7e300030 ) #define EMMC_INTERRUPT_MASK 0xffffffff #define EMMC_INTERRUPT_WIDTH 32 #define EMMC_INTERRUPT_RESET 0000000000 #define EMMC_INTERRUPT_OEM_ERR_BITS 31:30 #define EMMC_INTERRUPT_OEM_ERR_SET 0xc0000000 #define EMMC_INTERRUPT_OEM_ERR_CLR 0x3fffffff #define EMMC_INTERRUPT_OEM_ERR_MSB 31 #define EMMC_INTERRUPT_OEM_ERR_LSB 30 #define EMMC_INTERRUPT_ATA_ERR_BITS 29:29 #define EMMC_INTERRUPT_ATA_ERR_SET 0x20000000 #define EMMC_INTERRUPT_ATA_ERR_CLR 0xdfffffff #define EMMC_INTERRUPT_ATA_ERR_MSB 29 #define EMMC_INTERRUPT_ATA_ERR_LSB 29 #define EMMC_INTERRUPT_DMA_ERR_BITS 28:28 #define EMMC_INTERRUPT_DMA_ERR_SET 0x10000000 #define EMMC_INTERRUPT_DMA_ERR_CLR 0xefffffff #define EMMC_INTERRUPT_DMA_ERR_MSB 28 #define EMMC_INTERRUPT_DMA_ERR_LSB 28 #define EMMC_INTERRUPT_TUNE_ERR_BITS 26:26 #define EMMC_INTERRUPT_TUNE_ERR_SET 0x04000000 #define EMMC_INTERRUPT_TUNE_ERR_CLR 0xfbffffff #define EMMC_INTERRUPT_TUNE_ERR_MSB 26 #define EMMC_INTERRUPT_TUNE_ERR_LSB 26 #define EMMC_INTERRUPT_ADMA_ERR_BITS 25:25 #define EMMC_INTERRUPT_ADMA_ERR_SET 0x02000000 #define EMMC_INTERRUPT_ADMA_ERR_CLR 0xfdffffff #define EMMC_INTERRUPT_ADMA_ERR_MSB 25 #define EMMC_INTERRUPT_ADMA_ERR_LSB 25 #define EMMC_INTERRUPT_ACMD_ERR_BITS 24:24 #define EMMC_INTERRUPT_ACMD_ERR_SET 0x01000000 #define EMMC_INTERRUPT_ACMD_ERR_CLR 0xfeffffff #define EMMC_INTERRUPT_ACMD_ERR_MSB 24 #define EMMC_INTERRUPT_ACMD_ERR_LSB 24 #define EMMC_INTERRUPT_SDOFF_ERR_BITS 23:23 #define EMMC_INTERRUPT_SDOFF_ERR_SET 0x00800000 #define EMMC_INTERRUPT_SDOFF_ERR_CLR 0xff7fffff #define EMMC_INTERRUPT_SDOFF_ERR_MSB 23 #define EMMC_INTERRUPT_SDOFF_ERR_LSB 23 #define EMMC_INTERRUPT_DEND_ERR_BITS 22:22 #define EMMC_INTERRUPT_DEND_ERR_SET 0x00400000 #define EMMC_INTERRUPT_DEND_ERR_CLR 0xffbfffff #define EMMC_INTERRUPT_DEND_ERR_MSB 22 #define EMMC_INTERRUPT_DEND_ERR_LSB 22 #define EMMC_INTERRUPT_DCRC_ERR_BITS 21:21 #define EMMC_INTERRUPT_DCRC_ERR_SET 0x00200000 #define EMMC_INTERRUPT_DCRC_ERR_CLR 0xffdfffff #define EMMC_INTERRUPT_DCRC_ERR_MSB 21 #define EMMC_INTERRUPT_DCRC_ERR_LSB 21 #define EMMC_INTERRUPT_DTO_ERR_BITS 20:20 #define EMMC_INTERRUPT_DTO_ERR_SET 0x00100000 #define EMMC_INTERRUPT_DTO_ERR_CLR 0xffefffff #define EMMC_INTERRUPT_DTO_ERR_MSB 20 #define EMMC_INTERRUPT_DTO_ERR_LSB 20 #define EMMC_INTERRUPT_CBAD_ERR_BITS 19:19 #define EMMC_INTERRUPT_CBAD_ERR_SET 0x00080000 #define EMMC_INTERRUPT_CBAD_ERR_CLR 0xfff7ffff #define EMMC_INTERRUPT_CBAD_ERR_MSB 19 #define EMMC_INTERRUPT_CBAD_ERR_LSB 19 #define EMMC_INTERRUPT_CEND_ERR_BITS 18:18 #define EMMC_INTERRUPT_CEND_ERR_SET 0x00040000 #define EMMC_INTERRUPT_CEND_ERR_CLR 0xfffbffff #define EMMC_INTERRUPT_CEND_ERR_MSB 18 #define EMMC_INTERRUPT_CEND_ERR_LSB 18 #define EMMC_INTERRUPT_CCRC_ERR_BITS 17:17 #define EMMC_INTERRUPT_CCRC_ERR_SET 0x00020000 #define EMMC_INTERRUPT_CCRC_ERR_CLR 0xfffdffff #define EMMC_INTERRUPT_CCRC_ERR_MSB 17 #define EMMC_INTERRUPT_CCRC_ERR_LSB 17 #define EMMC_INTERRUPT_CTO_ERR_BITS 16:16 #define EMMC_INTERRUPT_CTO_ERR_SET 0x00010000 #define EMMC_INTERRUPT_CTO_ERR_CLR 0xfffeffff #define EMMC_INTERRUPT_CTO_ERR_MSB 16 #define EMMC_INTERRUPT_CTO_ERR_LSB 16 #define EMMC_INTERRUPT_ERR_BITS 15:15 #define EMMC_INTERRUPT_ERR_SET 0x00008000 #define EMMC_INTERRUPT_ERR_CLR 0xffff7fff #define EMMC_INTERRUPT_ERR_MSB 15 #define EMMC_INTERRUPT_ERR_LSB 15 #define EMMC_INTERRUPT_ENDBOOT_BITS 14:14 #define EMMC_INTERRUPT_ENDBOOT_SET 0x00004000 #define EMMC_INTERRUPT_ENDBOOT_CLR 0xffffbfff #define EMMC_INTERRUPT_ENDBOOT_MSB 14 #define EMMC_INTERRUPT_ENDBOOT_LSB 14 #define EMMC_INTERRUPT_BOOTACK_BITS 13:13 #define EMMC_INTERRUPT_BOOTACK_SET 0x00002000 #define EMMC_INTERRUPT_BOOTACK_CLR 0xffffdfff #define EMMC_INTERRUPT_BOOTACK_MSB 13 #define EMMC_INTERRUPT_BOOTACK_LSB 13 #define EMMC_INTERRUPT_RETUNE_BITS 12:12 #define EMMC_INTERRUPT_RETUNE_SET 0x00001000 #define EMMC_INTERRUPT_RETUNE_CLR 0xffffefff #define EMMC_INTERRUPT_RETUNE_MSB 12 #define EMMC_INTERRUPT_RETUNE_LSB 12 #define EMMC_INTERRUPT_INT_C_BITS 11:11 #define EMMC_INTERRUPT_INT_C_SET 0x00000800 #define EMMC_INTERRUPT_INT_C_CLR 0xfffff7ff #define EMMC_INTERRUPT_INT_C_MSB 11 #define EMMC_INTERRUPT_INT_C_LSB 11 #define EMMC_INTERRUPT_INT_B_BITS 10:10 #define EMMC_INTERRUPT_INT_B_SET 0x00000400 #define EMMC_INTERRUPT_INT_B_CLR 0xfffffbff #define EMMC_INTERRUPT_INT_B_MSB 10 #define EMMC_INTERRUPT_INT_B_LSB 10 #define EMMC_INTERRUPT_INT_A_BITS 9:9 #define EMMC_INTERRUPT_INT_A_SET 0x00000200 #define EMMC_INTERRUPT_INT_A_CLR 0xfffffdff #define EMMC_INTERRUPT_INT_A_MSB 9 #define EMMC_INTERRUPT_INT_A_LSB 9 #define EMMC_INTERRUPT_CARD_BITS 8:8 #define EMMC_INTERRUPT_CARD_SET 0x00000100 #define EMMC_INTERRUPT_CARD_CLR 0xfffffeff #define EMMC_INTERRUPT_CARD_MSB 8 #define EMMC_INTERRUPT_CARD_LSB 8 #define EMMC_INTERRUPT_CARD_OUT_BITS 7:7 #define EMMC_INTERRUPT_CARD_OUT_SET 0x00000080 #define EMMC_INTERRUPT_CARD_OUT_CLR 0xffffff7f #define EMMC_INTERRUPT_CARD_OUT_MSB 7 #define EMMC_INTERRUPT_CARD_OUT_LSB 7 #define EMMC_INTERRUPT_CARD_IN_BITS 6:6 #define EMMC_INTERRUPT_CARD_IN_SET 0x00000040 #define EMMC_INTERRUPT_CARD_IN_CLR 0xffffffbf #define EMMC_INTERRUPT_CARD_IN_MSB 6 #define EMMC_INTERRUPT_CARD_IN_LSB 6 #define EMMC_INTERRUPT_READ_RDY_BITS 5:5 #define EMMC_INTERRUPT_READ_RDY_SET 0x00000020 #define EMMC_INTERRUPT_READ_RDY_CLR 0xffffffdf #define EMMC_INTERRUPT_READ_RDY_MSB 5 #define EMMC_INTERRUPT_READ_RDY_LSB 5 #define EMMC_INTERRUPT_WRITE_RDY_BITS 4:4 #define EMMC_INTERRUPT_WRITE_RDY_SET 0x00000010 #define EMMC_INTERRUPT_WRITE_RDY_CLR 0xffffffef #define EMMC_INTERRUPT_WRITE_RDY_MSB 4 #define EMMC_INTERRUPT_WRITE_RDY_LSB 4 #define EMMC_INTERRUPT_DMA_BITS 3:3 #define EMMC_INTERRUPT_DMA_SET 0x00000008 #define EMMC_INTERRUPT_DMA_CLR 0xfffffff7 #define EMMC_INTERRUPT_DMA_MSB 3 #define EMMC_INTERRUPT_DMA_LSB 3 #define EMMC_INTERRUPT_BLOCK_GAP_BITS 2:2 #define EMMC_INTERRUPT_BLOCK_GAP_SET 0x00000004 #define EMMC_INTERRUPT_BLOCK_GAP_CLR 0xfffffffb #define EMMC_INTERRUPT_BLOCK_GAP_MSB 2 #define EMMC_INTERRUPT_BLOCK_GAP_LSB 2 #define EMMC_INTERRUPT_DATA_DONE_BITS 1:1 #define EMMC_INTERRUPT_DATA_DONE_SET 0x00000002 #define EMMC_INTERRUPT_DATA_DONE_CLR 0xfffffffd #define EMMC_INTERRUPT_DATA_DONE_MSB 1 #define EMMC_INTERRUPT_DATA_DONE_LSB 1 #define EMMC_INTERRUPT_CMD_DONE_BITS 0:0 #define EMMC_INTERRUPT_CMD_DONE_SET 0x00000001 #define EMMC_INTERRUPT_CMD_DONE_CLR 0xfffffffe #define EMMC_INTERRUPT_CMD_DONE_MSB 0 #define EMMC_INTERRUPT_CMD_DONE_LSB 0 #define EMMC_IRPT_MASK HW_REGISTER_RW( 0x7e300034 ) #define EMMC_IRPT_MASK_MASK 0xffffffff #define EMMC_IRPT_MASK_WIDTH 32 #define EMMC_IRPT_MASK_RESET 0000000000 #define EMMC_IRPT_MASK_OEM_ERR_BITS 31:30 #define EMMC_IRPT_MASK_OEM_ERR_SET 0xc0000000 #define EMMC_IRPT_MASK_OEM_ERR_CLR 0x3fffffff #define EMMC_IRPT_MASK_OEM_ERR_MSB 31 #define EMMC_IRPT_MASK_OEM_ERR_LSB 30 #define EMMC_IRPT_MASK_ATA_ERR_BITS 29:29 #define EMMC_IRPT_MASK_ATA_ERR_SET 0x20000000 #define EMMC_IRPT_MASK_ATA_ERR_CLR 0xdfffffff #define EMMC_IRPT_MASK_ATA_ERR_MSB 29 #define EMMC_IRPT_MASK_ATA_ERR_LSB 29 #define EMMC_IRPT_MASK_DMA_ERR_BITS 28:28 #define EMMC_IRPT_MASK_DMA_ERR_SET 0x10000000 #define EMMC_IRPT_MASK_DMA_ERR_CLR 0xefffffff #define EMMC_IRPT_MASK_DMA_ERR_MSB 28 #define EMMC_IRPT_MASK_DMA_ERR_LSB 28 #define EMMC_IRPT_MASK_ADMA_ERR_BITS 25:25 #define EMMC_IRPT_MASK_ADMA_ERR_SET 0x02000000 #define EMMC_IRPT_MASK_ADMA_ERR_CLR 0xfdffffff #define EMMC_IRPT_MASK_ADMA_ERR_MSB 25 #define EMMC_IRPT_MASK_ADMA_ERR_LSB 25 #define EMMC_IRPT_MASK_ACMD_ERR_BITS 24:24 #define EMMC_IRPT_MASK_ACMD_ERR_SET 0x01000000 #define EMMC_IRPT_MASK_ACMD_ERR_CLR 0xfeffffff #define EMMC_IRPT_MASK_ACMD_ERR_MSB 24 #define EMMC_IRPT_MASK_ACMD_ERR_LSB 24 #define EMMC_IRPT_MASK_SDOFF_ERR_BITS 23:23 #define EMMC_IRPT_MASK_SDOFF_ERR_SET 0x00800000 #define EMMC_IRPT_MASK_SDOFF_ERR_CLR 0xff7fffff #define EMMC_IRPT_MASK_SDOFF_ERR_MSB 23 #define EMMC_IRPT_MASK_SDOFF_ERR_LSB 23 #define EMMC_IRPT_MASK_DEND_ERR_BITS 22:22 #define EMMC_IRPT_MASK_DEND_ERR_SET 0x00400000 #define EMMC_IRPT_MASK_DEND_ERR_CLR 0xffbfffff #define EMMC_IRPT_MASK_DEND_ERR_MSB 22 #define EMMC_IRPT_MASK_DEND_ERR_LSB 22 #define EMMC_IRPT_MASK_DCRC_ERR_BITS 21:21 #define EMMC_IRPT_MASK_DCRC_ERR_SET 0x00200000 #define EMMC_IRPT_MASK_DCRC_ERR_CLR 0xffdfffff #define EMMC_IRPT_MASK_DCRC_ERR_MSB 21 #define EMMC_IRPT_MASK_DCRC_ERR_LSB 21 #define EMMC_IRPT_MASK_DTO_ERR_BITS 20:20 #define EMMC_IRPT_MASK_DTO_ERR_SET 0x00100000 #define EMMC_IRPT_MASK_DTO_ERR_CLR 0xffefffff #define EMMC_IRPT_MASK_DTO_ERR_MSB 20 #define EMMC_IRPT_MASK_DTO_ERR_LSB 20 #define EMMC_IRPT_MASK_CBAD_ERR_BITS 19:19 #define EMMC_IRPT_MASK_CBAD_ERR_SET 0x00080000 #define EMMC_IRPT_MASK_CBAD_ERR_CLR 0xfff7ffff #define EMMC_IRPT_MASK_CBAD_ERR_MSB 19 #define EMMC_IRPT_MASK_CBAD_ERR_LSB 19 #define EMMC_IRPT_MASK_CEND_ERR_BITS 18:18 #define EMMC_IRPT_MASK_CEND_ERR_SET 0x00040000 #define EMMC_IRPT_MASK_CEND_ERR_CLR 0xfffbffff #define EMMC_IRPT_MASK_CEND_ERR_MSB 18 #define EMMC_IRPT_MASK_CEND_ERR_LSB 18 #define EMMC_IRPT_MASK_CCRC_ERR_BITS 17:17 #define EMMC_IRPT_MASK_CCRC_ERR_SET 0x00020000 #define EMMC_IRPT_MASK_CCRC_ERR_CLR 0xfffdffff #define EMMC_IRPT_MASK_CCRC_ERR_MSB 17 #define EMMC_IRPT_MASK_CCRC_ERR_LSB 17 #define EMMC_IRPT_MASK_CTO_ERR_BITS 16:16 #define EMMC_IRPT_MASK_CTO_ERR_SET 0x00010000 #define EMMC_IRPT_MASK_CTO_ERR_CLR 0xfffeffff #define EMMC_IRPT_MASK_CTO_ERR_MSB 16 #define EMMC_IRPT_MASK_CTO_ERR_LSB 16 #define EMMC_IRPT_MASK_ENDBOOT_BITS 14:14 #define EMMC_IRPT_MASK_ENDBOOT_SET 0x00004000 #define EMMC_IRPT_MASK_ENDBOOT_CLR 0xffffbfff #define EMMC_IRPT_MASK_ENDBOOT_MSB 14 #define EMMC_IRPT_MASK_ENDBOOT_LSB 14 #define EMMC_IRPT_MASK_BOOTACK_BITS 13:13 #define EMMC_IRPT_MASK_BOOTACK_SET 0x00002000 #define EMMC_IRPT_MASK_BOOTACK_CLR 0xffffdfff #define EMMC_IRPT_MASK_BOOTACK_MSB 13 #define EMMC_IRPT_MASK_BOOTACK_LSB 13 #define EMMC_IRPT_MASK_RETUNE_BITS 12:12 #define EMMC_IRPT_MASK_RETUNE_SET 0x00001000 #define EMMC_IRPT_MASK_RETUNE_CLR 0xffffefff #define EMMC_IRPT_MASK_RETUNE_MSB 12 #define EMMC_IRPT_MASK_RETUNE_LSB 12 #define EMMC_IRPT_MASK_INT_C_BITS 11:11 #define EMMC_IRPT_MASK_INT_C_SET 0x00000800 #define EMMC_IRPT_MASK_INT_C_CLR 0xfffff7ff #define EMMC_IRPT_MASK_INT_C_MSB 11 #define EMMC_IRPT_MASK_INT_C_LSB 11 #define EMMC_IRPT_MASK_INT_B_BITS 10:10 #define EMMC_IRPT_MASK_INT_B_SET 0x00000400 #define EMMC_IRPT_MASK_INT_B_CLR 0xfffffbff #define EMMC_IRPT_MASK_INT_B_MSB 10 #define EMMC_IRPT_MASK_INT_B_LSB 10 #define EMMC_IRPT_MASK_INT_A_BITS 9:9 #define EMMC_IRPT_MASK_INT_A_SET 0x00000200 #define EMMC_IRPT_MASK_INT_A_CLR 0xfffffdff #define EMMC_IRPT_MASK_INT_A_MSB 9 #define EMMC_IRPT_MASK_INT_A_LSB 9 #define EMMC_IRPT_MASK_CARD_BITS 8:8 #define EMMC_IRPT_MASK_CARD_SET 0x00000100 #define EMMC_IRPT_MASK_CARD_CLR 0xfffffeff #define EMMC_IRPT_MASK_CARD_MSB 8 #define EMMC_IRPT_MASK_CARD_LSB 8 #define EMMC_IRPT_MASK_CARD_OUT_BITS 7:7 #define EMMC_IRPT_MASK_CARD_OUT_SET 0x00000080 #define EMMC_IRPT_MASK_CARD_OUT_CLR 0xffffff7f #define EMMC_IRPT_MASK_CARD_OUT_MSB 7 #define EMMC_IRPT_MASK_CARD_OUT_LSB 7 #define EMMC_IRPT_MASK_CARD_IN_BITS 6:6 #define EMMC_IRPT_MASK_CARD_IN_SET 0x00000040 #define EMMC_IRPT_MASK_CARD_IN_CLR 0xffffffbf #define EMMC_IRPT_MASK_CARD_IN_MSB 6 #define EMMC_IRPT_MASK_CARD_IN_LSB 6 #define EMMC_IRPT_MASK_READ_RDY_BITS 5:5 #define EMMC_IRPT_MASK_READ_RDY_SET 0x00000020 #define EMMC_IRPT_MASK_READ_RDY_CLR 0xffffffdf #define EMMC_IRPT_MASK_READ_RDY_MSB 5 #define EMMC_IRPT_MASK_READ_RDY_LSB 5 #define EMMC_IRPT_MASK_WRITE_RDY_BITS 4:4 #define EMMC_IRPT_MASK_WRITE_RDY_SET 0x00000010 #define EMMC_IRPT_MASK_WRITE_RDY_CLR 0xffffffef #define EMMC_IRPT_MASK_WRITE_RDY_MSB 4 #define EMMC_IRPT_MASK_WRITE_RDY_LSB 4 #define EMMC_IRPT_MASK_DMA_BITS 3:3 #define EMMC_IRPT_MASK_DMA_SET 0x00000008 #define EMMC_IRPT_MASK_DMA_CLR 0xfffffff7 #define EMMC_IRPT_MASK_DMA_MSB 3 #define EMMC_IRPT_MASK_DMA_LSB 3 #define EMMC_IRPT_MASK_BLOCK_GAP_BITS 2:2 #define EMMC_IRPT_MASK_BLOCK_GAP_SET 0x00000004 #define EMMC_IRPT_MASK_BLOCK_GAP_CLR 0xfffffffb #define EMMC_IRPT_MASK_BLOCK_GAP_MSB 2 #define EMMC_IRPT_MASK_BLOCK_GAP_LSB 2 #define EMMC_IRPT_MASK_DATA_DONE_BITS 1:1 #define EMMC_IRPT_MASK_DATA_DONE_SET 0x00000002 #define EMMC_IRPT_MASK_DATA_DONE_CLR 0xfffffffd #define EMMC_IRPT_MASK_DATA_DONE_MSB 1 #define EMMC_IRPT_MASK_DATA_DONE_LSB 1 #define EMMC_IRPT_MASK_CMD_DONE_BITS 0:0 #define EMMC_IRPT_MASK_CMD_DONE_SET 0x00000001 #define EMMC_IRPT_MASK_CMD_DONE_CLR 0xfffffffe #define EMMC_IRPT_MASK_CMD_DONE_MSB 0 #define EMMC_IRPT_MASK_CMD_DONE_LSB 0 #define EMMC_IRPT_EN HW_REGISTER_RW( 0x7e300038 ) #define EMMC_IRPT_EN_MASK 0xffffffff #define EMMC_IRPT_EN_WIDTH 32 #define EMMC_IRPT_EN_RESET 0000000000 #define EMMC_IRPT_EN_OEM_ERR_BITS 31:30 #define EMMC_IRPT_EN_OEM_ERR_SET 0xc0000000 #define EMMC_IRPT_EN_OEM_ERR_CLR 0x3fffffff #define EMMC_IRPT_EN_OEM_ERR_MSB 31 #define EMMC_IRPT_EN_OEM_ERR_LSB 30 #define EMMC_IRPT_EN_ATA_ERR_BITS 29:29 #define EMMC_IRPT_EN_ATA_ERR_SET 0x20000000 #define EMMC_IRPT_EN_ATA_ERR_CLR 0xdfffffff #define EMMC_IRPT_EN_ATA_ERR_MSB 29 #define EMMC_IRPT_EN_ATA_ERR_LSB 29 #define EMMC_IRPT_EN_DMA_ERR_BITS 28:28 #define EMMC_IRPT_EN_DMA_ERR_SET 0x10000000 #define EMMC_IRPT_EN_DMA_ERR_CLR 0xefffffff #define EMMC_IRPT_EN_DMA_ERR_MSB 28 #define EMMC_IRPT_EN_DMA_ERR_LSB 28 #define EMMC_IRPT_EN_TUNE_ERR_BITS 26:26 #define EMMC_IRPT_EN_TUNE_ERR_SET 0x04000000 #define EMMC_IRPT_EN_TUNE_ERR_CLR 0xfbffffff #define EMMC_IRPT_EN_TUNE_ERR_MSB 26 #define EMMC_IRPT_EN_TUNE_ERR_LSB 26 #define EMMC_IRPT_EN_ADMA_ERR_BITS 25:25 #define EMMC_IRPT_EN_ADMA_ERR_SET 0x02000000 #define EMMC_IRPT_EN_ADMA_ERR_CLR 0xfdffffff #define EMMC_IRPT_EN_ADMA_ERR_MSB 25 #define EMMC_IRPT_EN_ADMA_ERR_LSB 25 #define EMMC_IRPT_EN_ACMD_ERR_BITS 24:24 #define EMMC_IRPT_EN_ACMD_ERR_SET 0x01000000 #define EMMC_IRPT_EN_ACMD_ERR_CLR 0xfeffffff #define EMMC_IRPT_EN_ACMD_ERR_MSB 24 #define EMMC_IRPT_EN_ACMD_ERR_LSB 24 #define EMMC_IRPT_EN_SDOFF_ERR_BITS 23:23 #define EMMC_IRPT_EN_SDOFF_ERR_SET 0x00800000 #define EMMC_IRPT_EN_SDOFF_ERR_CLR 0xff7fffff #define EMMC_IRPT_EN_SDOFF_ERR_MSB 23 #define EMMC_IRPT_EN_SDOFF_ERR_LSB 23 #define EMMC_IRPT_EN_DEND_ERR_BITS 22:22 #define EMMC_IRPT_EN_DEND_ERR_SET 0x00400000 #define EMMC_IRPT_EN_DEND_ERR_CLR 0xffbfffff #define EMMC_IRPT_EN_DEND_ERR_MSB 22 #define EMMC_IRPT_EN_DEND_ERR_LSB 22 #define EMMC_IRPT_EN_DCRC_ERR_BITS 21:21 #define EMMC_IRPT_EN_DCRC_ERR_SET 0x00200000 #define EMMC_IRPT_EN_DCRC_ERR_CLR 0xffdfffff #define EMMC_IRPT_EN_DCRC_ERR_MSB 21 #define EMMC_IRPT_EN_DCRC_ERR_LSB 21 #define EMMC_IRPT_EN_DTO_ERR_BITS 20:20 #define EMMC_IRPT_EN_DTO_ERR_SET 0x00100000 #define EMMC_IRPT_EN_DTO_ERR_CLR 0xffefffff #define EMMC_IRPT_EN_DTO_ERR_MSB 20 #define EMMC_IRPT_EN_DTO_ERR_LSB 20 #define EMMC_IRPT_EN_CBAD_ERR_BITS 19:19 #define EMMC_IRPT_EN_CBAD_ERR_SET 0x00080000 #define EMMC_IRPT_EN_CBAD_ERR_CLR 0xfff7ffff #define EMMC_IRPT_EN_CBAD_ERR_MSB 19 #define EMMC_IRPT_EN_CBAD_ERR_LSB 19 #define EMMC_IRPT_EN_CEND_ERR_BITS 18:18 #define EMMC_IRPT_EN_CEND_ERR_SET 0x00040000 #define EMMC_IRPT_EN_CEND_ERR_CLR 0xfffbffff #define EMMC_IRPT_EN_CEND_ERR_MSB 18 #define EMMC_IRPT_EN_CEND_ERR_LSB 18 #define EMMC_IRPT_EN_CCRC_ERR_BITS 17:17 #define EMMC_IRPT_EN_CCRC_ERR_SET 0x00020000 #define EMMC_IRPT_EN_CCRC_ERR_CLR 0xfffdffff #define EMMC_IRPT_EN_CCRC_ERR_MSB 17 #define EMMC_IRPT_EN_CCRC_ERR_LSB 17 #define EMMC_IRPT_EN_CTO_ERR_BITS 16:16 #define EMMC_IRPT_EN_CTO_ERR_SET 0x00010000 #define EMMC_IRPT_EN_CTO_ERR_CLR 0xfffeffff #define EMMC_IRPT_EN_CTO_ERR_MSB 16 #define EMMC_IRPT_EN_CTO_ERR_LSB 16 #define EMMC_IRPT_EN_ENDBOOT_BITS 14:14 #define EMMC_IRPT_EN_ENDBOOT_SET 0x00004000 #define EMMC_IRPT_EN_ENDBOOT_CLR 0xffffbfff #define EMMC_IRPT_EN_ENDBOOT_MSB 14 #define EMMC_IRPT_EN_ENDBOOT_LSB 14 #define EMMC_IRPT_EN_BOOTACK_BITS 13:13 #define EMMC_IRPT_EN_BOOTACK_SET 0x00002000 #define EMMC_IRPT_EN_BOOTACK_CLR 0xffffdfff #define EMMC_IRPT_EN_BOOTACK_MSB 13 #define EMMC_IRPT_EN_BOOTACK_LSB 13 #define EMMC_IRPT_EN_RETUNE_BITS 12:12 #define EMMC_IRPT_EN_RETUNE_SET 0x00001000 #define EMMC_IRPT_EN_RETUNE_CLR 0xffffefff #define EMMC_IRPT_EN_RETUNE_MSB 12 #define EMMC_IRPT_EN_RETUNE_LSB 12 #define EMMC_IRPT_EN_INT_C_BITS 11:11 #define EMMC_IRPT_EN_INT_C_SET 0x00000800 #define EMMC_IRPT_EN_INT_C_CLR 0xfffff7ff #define EMMC_IRPT_EN_INT_C_MSB 11 #define EMMC_IRPT_EN_INT_C_LSB 11 #define EMMC_IRPT_EN_INT_B_BITS 10:10 #define EMMC_IRPT_EN_INT_B_SET 0x00000400 #define EMMC_IRPT_EN_INT_B_CLR 0xfffffbff #define EMMC_IRPT_EN_INT_B_MSB 10 #define EMMC_IRPT_EN_INT_B_LSB 10 #define EMMC_IRPT_EN_INT_A_BITS 9:9 #define EMMC_IRPT_EN_INT_A_SET 0x00000200 #define EMMC_IRPT_EN_INT_A_CLR 0xfffffdff #define EMMC_IRPT_EN_INT_A_MSB 9 #define EMMC_IRPT_EN_INT_A_LSB 9 #define EMMC_IRPT_EN_CARD_BITS 8:8 #define EMMC_IRPT_EN_CARD_SET 0x00000100 #define EMMC_IRPT_EN_CARD_CLR 0xfffffeff #define EMMC_IRPT_EN_CARD_MSB 8 #define EMMC_IRPT_EN_CARD_LSB 8 #define EMMC_IRPT_EN_CARD_OUT_BITS 7:7 #define EMMC_IRPT_EN_CARD_OUT_SET 0x00000080 #define EMMC_IRPT_EN_CARD_OUT_CLR 0xffffff7f #define EMMC_IRPT_EN_CARD_OUT_MSB 7 #define EMMC_IRPT_EN_CARD_OUT_LSB 7 #define EMMC_IRPT_EN_CARD_IN_BITS 6:6 #define EMMC_IRPT_EN_CARD_IN_SET 0x00000040 #define EMMC_IRPT_EN_CARD_IN_CLR 0xffffffbf #define EMMC_IRPT_EN_CARD_IN_MSB 6 #define EMMC_IRPT_EN_CARD_IN_LSB 6 #define EMMC_IRPT_EN_READ_RDY_BITS 5:5 #define EMMC_IRPT_EN_READ_RDY_SET 0x00000020 #define EMMC_IRPT_EN_READ_RDY_CLR 0xffffffdf #define EMMC_IRPT_EN_READ_RDY_MSB 5 #define EMMC_IRPT_EN_READ_RDY_LSB 5 #define EMMC_IRPT_EN_WRITE_RDY_BITS 4:4 #define EMMC_IRPT_EN_WRITE_RDY_SET 0x00000010 #define EMMC_IRPT_EN_WRITE_RDY_CLR 0xffffffef #define EMMC_IRPT_EN_WRITE_RDY_MSB 4 #define EMMC_IRPT_EN_WRITE_RDY_LSB 4 #define EMMC_IRPT_EN_DMA_BITS 3:3 #define EMMC_IRPT_EN_DMA_SET 0x00000008 #define EMMC_IRPT_EN_DMA_CLR 0xfffffff7 #define EMMC_IRPT_EN_DMA_MSB 3 #define EMMC_IRPT_EN_DMA_LSB 3 #define EMMC_IRPT_EN_BLOCK_GAP_BITS 2:2 #define EMMC_IRPT_EN_BLOCK_GAP_SET 0x00000004 #define EMMC_IRPT_EN_BLOCK_GAP_CLR 0xfffffffb #define EMMC_IRPT_EN_BLOCK_GAP_MSB 2 #define EMMC_IRPT_EN_BLOCK_GAP_LSB 2 #define EMMC_IRPT_EN_DATA_DONE_BITS 1:1 #define EMMC_IRPT_EN_DATA_DONE_SET 0x00000002 #define EMMC_IRPT_EN_DATA_DONE_CLR 0xfffffffd #define EMMC_IRPT_EN_DATA_DONE_MSB 1 #define EMMC_IRPT_EN_DATA_DONE_LSB 1 #define EMMC_IRPT_EN_CMD_DONE_BITS 0:0 #define EMMC_IRPT_EN_CMD_DONE_SET 0x00000001 #define EMMC_IRPT_EN_CMD_DONE_CLR 0xfffffffe #define EMMC_IRPT_EN_CMD_DONE_MSB 0 #define EMMC_IRPT_EN_CMD_DONE_LSB 0 #define EMMC_CONTROL2 HW_REGISTER_RW( 0x7e30003c ) #define EMMC_CONTROL2_MASK 0xc0ff009f #define EMMC_CONTROL2_WIDTH 32 #define EMMC_CONTROL2_RESET 0x00080000 #define EMMC_CONTROL2_EN_PSV_BITS 31:31 #define EMMC_CONTROL2_EN_PSV_SET 0x80000000 #define EMMC_CONTROL2_EN_PSV_CLR 0x7fffffff #define EMMC_CONTROL2_EN_PSV_MSB 31 #define EMMC_CONTROL2_EN_PSV_LSB 31 #define EMMC_CONTROL2_EN_AINT_BITS 30:30 #define EMMC_CONTROL2_EN_AINT_SET 0x40000000 #define EMMC_CONTROL2_EN_AINT_CLR 0xbfffffff #define EMMC_CONTROL2_EN_AINT_MSB 30 #define EMMC_CONTROL2_EN_AINT_LSB 30 #define EMMC_CONTROL2_TUNED_BITS 23:23 #define EMMC_CONTROL2_TUNED_SET 0x00800000 #define EMMC_CONTROL2_TUNED_CLR 0xff7fffff #define EMMC_CONTROL2_TUNED_MSB 23 #define EMMC_CONTROL2_TUNED_LSB 23 #define EMMC_CONTROL2_TUNEON_BITS 22:22 #define EMMC_CONTROL2_TUNEON_SET 0x00400000 #define EMMC_CONTROL2_TUNEON_CLR 0xffbfffff #define EMMC_CONTROL2_TUNEON_MSB 22 #define EMMC_CONTROL2_TUNEON_LSB 22 #define EMMC_CONTROL2_DRVTYPE_BITS 21:20 #define EMMC_CONTROL2_DRVTYPE_SET 0x00300000 #define EMMC_CONTROL2_DRVTYPE_CLR 0xffcfffff #define EMMC_CONTROL2_DRVTYPE_MSB 21 #define EMMC_CONTROL2_DRVTYPE_LSB 20 #define EMMC_CONTROL2_SIGTYPE_BITS 19:19 #define EMMC_CONTROL2_SIGTYPE_SET 0x00080000 #define EMMC_CONTROL2_SIGTYPE_CLR 0xfff7ffff #define EMMC_CONTROL2_SIGTYPE_MSB 19 #define EMMC_CONTROL2_SIGTYPE_LSB 19 #define EMMC_CONTROL2_UHSMODE_BITS 18:16 #define EMMC_CONTROL2_UHSMODE_SET 0x00070000 #define EMMC_CONTROL2_UHSMODE_CLR 0xfff8ffff #define EMMC_CONTROL2_UHSMODE_MSB 18 #define EMMC_CONTROL2_UHSMODE_LSB 16 #define EMMC_CONTROL2_NOTC12_ERR_BITS 7:7 #define EMMC_CONTROL2_NOTC12_ERR_SET 0x00000080 #define EMMC_CONTROL2_NOTC12_ERR_CLR 0xffffff7f #define EMMC_CONTROL2_NOTC12_ERR_MSB 7 #define EMMC_CONTROL2_NOTC12_ERR_LSB 7 #define EMMC_CONTROL2_ACBAD_ERR_BITS 4:4 #define EMMC_CONTROL2_ACBAD_ERR_SET 0x00000010 #define EMMC_CONTROL2_ACBAD_ERR_CLR 0xffffffef #define EMMC_CONTROL2_ACBAD_ERR_MSB 4 #define EMMC_CONTROL2_ACBAD_ERR_LSB 4 #define EMMC_CONTROL2_ACEND_ERR_BITS 3:3 #define EMMC_CONTROL2_ACEND_ERR_SET 0x00000008 #define EMMC_CONTROL2_ACEND_ERR_CLR 0xfffffff7 #define EMMC_CONTROL2_ACEND_ERR_MSB 3 #define EMMC_CONTROL2_ACEND_ERR_LSB 3 #define EMMC_CONTROL2_ACCRC_ERR_BITS 2:2 #define EMMC_CONTROL2_ACCRC_ERR_SET 0x00000004 #define EMMC_CONTROL2_ACCRC_ERR_CLR 0xfffffffb #define EMMC_CONTROL2_ACCRC_ERR_MSB 2 #define EMMC_CONTROL2_ACCRC_ERR_LSB 2 #define EMMC_CONTROL2_ACTO_ERR_BITS 1:1 #define EMMC_CONTROL2_ACTO_ERR_SET 0x00000002 #define EMMC_CONTROL2_ACTO_ERR_CLR 0xfffffffd #define EMMC_CONTROL2_ACTO_ERR_MSB 1 #define EMMC_CONTROL2_ACTO_ERR_LSB 1 #define EMMC_CONTROL2_ACNOX_ERR_BITS 0:0 #define EMMC_CONTROL2_ACNOX_ERR_SET 0x00000001 #define EMMC_CONTROL2_ACNOX_ERR_CLR 0xfffffffe #define EMMC_CONTROL2_ACNOX_ERR_MSB 0 #define EMMC_CONTROL2_ACNOX_ERR_LSB 0 #define EMMC_HWCAP0 HW_REGISTER_RW( 0x7e300040 ) #define EMMC_HWCAP0_MASK 0xffffffff #define EMMC_HWCAP0_WIDTH 32 #define EMMC_HWCAP0_RESET 0000000000 #define EMMC_HWCAP0_SLOT_TYPE_BITS 31:30 #define EMMC_HWCAP0_SLOT_TYPE_SET 0xc0000000 #define EMMC_HWCAP0_SLOT_TYPE_CLR 0x3fffffff #define EMMC_HWCAP0_SLOT_TYPE_MSB 31 #define EMMC_HWCAP0_SLOT_TYPE_LSB 30 #define EMMC_HWCAP0_AINT_BITS 29:29 #define EMMC_HWCAP0_AINT_SET 0x20000000 #define EMMC_HWCAP0_AINT_CLR 0xdfffffff #define EMMC_HWCAP0_AINT_MSB 29 #define EMMC_HWCAP0_AINT_LSB 29 #define EMMC_HWCAP0_BUS64_BITS 28:28 #define EMMC_HWCAP0_BUS64_SET 0x10000000 #define EMMC_HWCAP0_BUS64_CLR 0xefffffff #define EMMC_HWCAP0_BUS64_MSB 28 #define EMMC_HWCAP0_BUS64_LSB 28 #define EMMC_HWCAP0_V1_8_BITS 26:26 #define EMMC_HWCAP0_V1_8_SET 0x04000000 #define EMMC_HWCAP0_V1_8_CLR 0xfbffffff #define EMMC_HWCAP0_V1_8_MSB 26 #define EMMC_HWCAP0_V1_8_LSB 26 #define EMMC_HWCAP0_V3_0_BITS 25:25 #define EMMC_HWCAP0_V3_0_SET 0x02000000 #define EMMC_HWCAP0_V3_0_CLR 0xfdffffff #define EMMC_HWCAP0_V3_0_MSB 25 #define EMMC_HWCAP0_V3_0_LSB 25 #define EMMC_HWCAP0_V3_3_BITS 24:24 #define EMMC_HWCAP0_V3_3_SET 0x01000000 #define EMMC_HWCAP0_V3_3_CLR 0xfeffffff #define EMMC_HWCAP0_V3_3_MSB 24 #define EMMC_HWCAP0_V3_3_LSB 24 #define EMMC_HWCAP0_RESUME_BITS 23:23 #define EMMC_HWCAP0_RESUME_SET 0x00800000 #define EMMC_HWCAP0_RESUME_CLR 0xff7fffff #define EMMC_HWCAP0_RESUME_MSB 23 #define EMMC_HWCAP0_RESUME_LSB 23 #define EMMC_HWCAP0_SDMA_BITS 22:22 #define EMMC_HWCAP0_SDMA_SET 0x00400000 #define EMMC_HWCAP0_SDMA_CLR 0xffbfffff #define EMMC_HWCAP0_SDMA_MSB 22 #define EMMC_HWCAP0_SDMA_LSB 22 #define EMMC_HWCAP0_HS_BITS 21:21 #define EMMC_HWCAP0_HS_SET 0x00200000 #define EMMC_HWCAP0_HS_CLR 0xffdfffff #define EMMC_HWCAP0_HS_MSB 21 #define EMMC_HWCAP0_HS_LSB 21 #define EMMC_HWCAP0_ADMA2_BITS 19:19 #define EMMC_HWCAP0_ADMA2_SET 0x00080000 #define EMMC_HWCAP0_ADMA2_CLR 0xfff7ffff #define EMMC_HWCAP0_ADMA2_MSB 19 #define EMMC_HWCAP0_ADMA2_LSB 19 #define EMMC_HWCAP0_XMEDBUS_BITS 18:18 #define EMMC_HWCAP0_XMEDBUS_SET 0x00040000 #define EMMC_HWCAP0_XMEDBUS_CLR 0xfffbffff #define EMMC_HWCAP0_XMEDBUS_MSB 18 #define EMMC_HWCAP0_XMEDBUS_LSB 18 #define EMMC_HWCAP0_MAXLEN_BITS 17:16 #define EMMC_HWCAP0_MAXLEN_SET 0x00030000 #define EMMC_HWCAP0_MAXLEN_CLR 0xfffcffff #define EMMC_HWCAP0_MAXLEN_MSB 17 #define EMMC_HWCAP0_MAXLEN_LSB 16 #define EMMC_HWCAP0_BASEMHZ_BITS 15:8 #define EMMC_HWCAP0_BASEMHZ_SET 0x0000ff00 #define EMMC_HWCAP0_BASEMHZ_CLR 0xffff00ff #define EMMC_HWCAP0_BASEMHZ_MSB 15 #define EMMC_HWCAP0_BASEMHZ_LSB 8 #define EMMC_HWCAP0_TCLKUNIT_BITS 7:7 #define EMMC_HWCAP0_TCLKUNIT_SET 0x00000080 #define EMMC_HWCAP0_TCLKUNIT_CLR 0xffffff7f #define EMMC_HWCAP0_TCLKUNIT_MSB 7 #define EMMC_HWCAP0_TCLKUNIT_LSB 7 #define EMMC_HWCAP0_TCLKFREQ_BITS 5:0 #define EMMC_HWCAP0_TCLKFREQ_SET 0x0000003f #define EMMC_HWCAP0_TCLKFREQ_CLR 0xffffffc0 #define EMMC_HWCAP0_TCLKFREQ_MSB 5 #define EMMC_HWCAP0_TCLKFREQ_LSB 0 #define EMMC_HWCAP1 HW_REGISTER_RW( 0x7e300044 ) #define EMMC_HWCAP1_MASK 0x03ffef77 #define EMMC_HWCAP1_WIDTH 26 #define EMMC_HWCAP1_RESET 0x03000777 #define EMMC_HWCAP1_SPI_BLOCKMODE_BITS 25:25 #define EMMC_HWCAP1_SPI_BLOCKMODE_SET 0x02000000 #define EMMC_HWCAP1_SPI_BLOCKMODE_CLR 0xfdffffff #define EMMC_HWCAP1_SPI_BLOCKMODE_MSB 25 #define EMMC_HWCAP1_SPI_BLOCKMODE_LSB 25 #define EMMC_HWCAP1_SPI_MODE_BITS 24:24 #define EMMC_HWCAP1_SPI_MODE_SET 0x01000000 #define EMMC_HWCAP1_SPI_MODE_CLR 0xfeffffff #define EMMC_HWCAP1_SPI_MODE_MSB 24 #define EMMC_HWCAP1_SPI_MODE_LSB 24 #define EMMC_HWCAP1_MULTIPLIER_BITS 23:16 #define EMMC_HWCAP1_MULTIPLIER_SET 0x00ff0000 #define EMMC_HWCAP1_MULTIPLIER_CLR 0xff00ffff #define EMMC_HWCAP1_MULTIPLIER_MSB 23 #define EMMC_HWCAP1_MULTIPLIER_LSB 16 #define EMMC_HWCAP1_DATA_RETUNE_BITS 15:14 #define EMMC_HWCAP1_DATA_RETUNE_SET 0x0000c000 #define EMMC_HWCAP1_DATA_RETUNE_CLR 0xffff3fff #define EMMC_HWCAP1_DATA_RETUNE_MSB 15 #define EMMC_HWCAP1_DATA_RETUNE_LSB 14 #define EMMC_HWCAP1_SDR50_TUNE_BITS 13:13 #define EMMC_HWCAP1_SDR50_TUNE_SET 0x00002000 #define EMMC_HWCAP1_SDR50_TUNE_CLR 0xffffdfff #define EMMC_HWCAP1_SDR50_TUNE_MSB 13 #define EMMC_HWCAP1_SDR50_TUNE_LSB 13 #define EMMC_HWCAP1_RETUNE_TMR_BITS 11:8 #define EMMC_HWCAP1_RETUNE_TMR_SET 0x00000f00 #define EMMC_HWCAP1_RETUNE_TMR_CLR 0xfffff0ff #define EMMC_HWCAP1_RETUNE_TMR_MSB 11 #define EMMC_HWCAP1_RETUNE_TMR_LSB 8 #define EMMC_HWCAP1_DRV18_TYPED_BITS 6:6 #define EMMC_HWCAP1_DRV18_TYPED_SET 0x00000040 #define EMMC_HWCAP1_DRV18_TYPED_CLR 0xffffffbf #define EMMC_HWCAP1_DRV18_TYPED_MSB 6 #define EMMC_HWCAP1_DRV18_TYPED_LSB 6 #define EMMC_HWCAP1_DRV18_TYPEC_BITS 5:5 #define EMMC_HWCAP1_DRV18_TYPEC_SET 0x00000020 #define EMMC_HWCAP1_DRV18_TYPEC_CLR 0xffffffdf #define EMMC_HWCAP1_DRV18_TYPEC_MSB 5 #define EMMC_HWCAP1_DRV18_TYPEC_LSB 5 #define EMMC_HWCAP1_DRV18_TYPEA_BITS 4:4 #define EMMC_HWCAP1_DRV18_TYPEA_SET 0x00000010 #define EMMC_HWCAP1_DRV18_TYPEA_CLR 0xffffffef #define EMMC_HWCAP1_DRV18_TYPEA_MSB 4 #define EMMC_HWCAP1_DRV18_TYPEA_LSB 4 #define EMMC_HWCAP1_DDR50_BITS 2:2 #define EMMC_HWCAP1_DDR50_SET 0x00000004 #define EMMC_HWCAP1_DDR50_CLR 0xfffffffb #define EMMC_HWCAP1_DDR50_MSB 2 #define EMMC_HWCAP1_DDR50_LSB 2 #define EMMC_HWCAP1_SDR104_BITS 1:1 #define EMMC_HWCAP1_SDR104_SET 0x00000002 #define EMMC_HWCAP1_SDR104_CLR 0xfffffffd #define EMMC_HWCAP1_SDR104_MSB 1 #define EMMC_HWCAP1_SDR104_LSB 1 #define EMMC_HWCAP1_SDR50_BITS 0:0 #define EMMC_HWCAP1_SDR50_SET 0x00000001 #define EMMC_HWCAP1_SDR50_CLR 0xfffffffe #define EMMC_HWCAP1_SDR50_MSB 0 #define EMMC_HWCAP1_SDR50_LSB 0 #define EMMC_HWMAXAMP0 HW_REGISTER_RW( 0x7e300048 ) #define EMMC_HWMAXAMP0_MASK 0x00ffffff #define EMMC_HWMAXAMP0_WIDTH 24 #define EMMC_HWMAXAMP0_RESET 0000000000 #define EMMC_HWMAXAMP0_AMP_18V_BITS 23:16 #define EMMC_HWMAXAMP0_AMP_18V_SET 0x00ff0000 #define EMMC_HWMAXAMP0_AMP_18V_CLR 0xff00ffff #define EMMC_HWMAXAMP0_AMP_18V_MSB 23 #define EMMC_HWMAXAMP0_AMP_18V_LSB 16 #define EMMC_HWMAXAMP0_AMP_30V_BITS 15:8 #define EMMC_HWMAXAMP0_AMP_30V_SET 0x0000ff00 #define EMMC_HWMAXAMP0_AMP_30V_CLR 0xffff00ff #define EMMC_HWMAXAMP0_AMP_30V_MSB 15 #define EMMC_HWMAXAMP0_AMP_30V_LSB 8 #define EMMC_HWMAXAMP0_AMP_33V_BITS 7:0 #define EMMC_HWMAXAMP0_AMP_33V_SET 0x000000ff #define EMMC_HWMAXAMP0_AMP_33V_CLR 0xffffff00 #define EMMC_HWMAXAMP0_AMP_33V_MSB 7 #define EMMC_HWMAXAMP0_AMP_33V_LSB 0 #define EMMC_FORCE_IRPT HW_REGISTER_RW( 0x7e300050 ) #define EMMC_FORCE_IRPT_MASK 0xffff00ff #define EMMC_FORCE_IRPT_WIDTH 32 #define EMMC_FORCE_IRPT_RESET 0x00000001 #define EMMC_FORCE_IRPT_OEM_ERR_BITS 31:30 #define EMMC_FORCE_IRPT_OEM_ERR_SET 0xc0000000 #define EMMC_FORCE_IRPT_OEM_ERR_CLR 0x3fffffff #define EMMC_FORCE_IRPT_OEM_ERR_MSB 31 #define EMMC_FORCE_IRPT_OEM_ERR_LSB 30 #define EMMC_FORCE_IRPT_ATA_ERR_BITS 29:29 #define EMMC_FORCE_IRPT_ATA_ERR_SET 0x20000000 #define EMMC_FORCE_IRPT_ATA_ERR_CLR 0xdfffffff #define EMMC_FORCE_IRPT_ATA_ERR_MSB 29 #define EMMC_FORCE_IRPT_ATA_ERR_LSB 29 #define EMMC_FORCE_IRPT_DMA_ERR_BITS 28:28 #define EMMC_FORCE_IRPT_DMA_ERR_SET 0x10000000 #define EMMC_FORCE_IRPT_DMA_ERR_CLR 0xefffffff #define EMMC_FORCE_IRPT_DMA_ERR_MSB 28 #define EMMC_FORCE_IRPT_DMA_ERR_LSB 28 #define EMMC_FORCE_IRPT_TUNE_ERR_BITS 26:26 #define EMMC_FORCE_IRPT_TUNE_ERR_SET 0x04000000 #define EMMC_FORCE_IRPT_TUNE_ERR_CLR 0xfbffffff #define EMMC_FORCE_IRPT_TUNE_ERR_MSB 26 #define EMMC_FORCE_IRPT_TUNE_ERR_LSB 26 #define EMMC_FORCE_IRPT_ADMA_ERR_BITS 25:25 #define EMMC_FORCE_IRPT_ADMA_ERR_SET 0x02000000 #define EMMC_FORCE_IRPT_ADMA_ERR_CLR 0xfdffffff #define EMMC_FORCE_IRPT_ADMA_ERR_MSB 25 #define EMMC_FORCE_IRPT_ADMA_ERR_LSB 25 #define EMMC_FORCE_IRPT_ACMD_ERR_BITS 24:24 #define EMMC_FORCE_IRPT_ACMD_ERR_SET 0x01000000 #define EMMC_FORCE_IRPT_ACMD_ERR_CLR 0xfeffffff #define EMMC_FORCE_IRPT_ACMD_ERR_MSB 24 #define EMMC_FORCE_IRPT_ACMD_ERR_LSB 24 #define EMMC_FORCE_IRPT_SDOFF_ERR_BITS 23:23 #define EMMC_FORCE_IRPT_SDOFF_ERR_SET 0x00800000 #define EMMC_FORCE_IRPT_SDOFF_ERR_CLR 0xff7fffff #define EMMC_FORCE_IRPT_SDOFF_ERR_MSB 23 #define EMMC_FORCE_IRPT_SDOFF_ERR_LSB 23 #define EMMC_FORCE_IRPT_DEND_ERR_BITS 22:22 #define EMMC_FORCE_IRPT_DEND_ERR_SET 0x00400000 #define EMMC_FORCE_IRPT_DEND_ERR_CLR 0xffbfffff #define EMMC_FORCE_IRPT_DEND_ERR_MSB 22 #define EMMC_FORCE_IRPT_DEND_ERR_LSB 22 #define EMMC_FORCE_IRPT_DCRC_ERR_BITS 21:21 #define EMMC_FORCE_IRPT_DCRC_ERR_SET 0x00200000 #define EMMC_FORCE_IRPT_DCRC_ERR_CLR 0xffdfffff #define EMMC_FORCE_IRPT_DCRC_ERR_MSB 21 #define EMMC_FORCE_IRPT_DCRC_ERR_LSB 21 #define EMMC_FORCE_IRPT_DTO_ERR_BITS 20:20 #define EMMC_FORCE_IRPT_DTO_ERR_SET 0x00100000 #define EMMC_FORCE_IRPT_DTO_ERR_CLR 0xffefffff #define EMMC_FORCE_IRPT_DTO_ERR_MSB 20 #define EMMC_FORCE_IRPT_DTO_ERR_LSB 20 #define EMMC_FORCE_IRPT_CBAD_ERR_BITS 19:19 #define EMMC_FORCE_IRPT_CBAD_ERR_SET 0x00080000 #define EMMC_FORCE_IRPT_CBAD_ERR_CLR 0xfff7ffff #define EMMC_FORCE_IRPT_CBAD_ERR_MSB 19 #define EMMC_FORCE_IRPT_CBAD_ERR_LSB 19 #define EMMC_FORCE_IRPT_CEND_ERR_BITS 18:18 #define EMMC_FORCE_IRPT_CEND_ERR_SET 0x00040000 #define EMMC_FORCE_IRPT_CEND_ERR_CLR 0xfffbffff #define EMMC_FORCE_IRPT_CEND_ERR_MSB 18 #define EMMC_FORCE_IRPT_CEND_ERR_LSB 18 #define EMMC_FORCE_IRPT_CCRC_ERR_BITS 17:17 #define EMMC_FORCE_IRPT_CCRC_ERR_SET 0x00020000 #define EMMC_FORCE_IRPT_CCRC_ERR_CLR 0xfffdffff #define EMMC_FORCE_IRPT_CCRC_ERR_MSB 17 #define EMMC_FORCE_IRPT_CCRC_ERR_LSB 17 #define EMMC_FORCE_IRPT_CTO_ERR_BITS 16:16 #define EMMC_FORCE_IRPT_CTO_ERR_SET 0x00010000 #define EMMC_FORCE_IRPT_CTO_ERR_CLR 0xfffeffff #define EMMC_FORCE_IRPT_CTO_ERR_MSB 16 #define EMMC_FORCE_IRPT_CTO_ERR_LSB 16 #define EMMC_FORCE_IRPT_CARD_OUT_BITS 7:7 #define EMMC_FORCE_IRPT_CARD_OUT_SET 0x00000080 #define EMMC_FORCE_IRPT_CARD_OUT_CLR 0xffffff7f #define EMMC_FORCE_IRPT_CARD_OUT_MSB 7 #define EMMC_FORCE_IRPT_CARD_OUT_LSB 7 #define EMMC_FORCE_IRPT_CARD_IN_BITS 6:6 #define EMMC_FORCE_IRPT_CARD_IN_SET 0x00000040 #define EMMC_FORCE_IRPT_CARD_IN_CLR 0xffffffbf #define EMMC_FORCE_IRPT_CARD_IN_MSB 6 #define EMMC_FORCE_IRPT_CARD_IN_LSB 6 #define EMMC_FORCE_IRPT_READ_RDY_BITS 5:5 #define EMMC_FORCE_IRPT_READ_RDY_SET 0x00000020 #define EMMC_FORCE_IRPT_READ_RDY_CLR 0xffffffdf #define EMMC_FORCE_IRPT_READ_RDY_MSB 5 #define EMMC_FORCE_IRPT_READ_RDY_LSB 5 #define EMMC_FORCE_IRPT_WRITE_RDY_BITS 4:4 #define EMMC_FORCE_IRPT_WRITE_RDY_SET 0x00000010 #define EMMC_FORCE_IRPT_WRITE_RDY_CLR 0xffffffef #define EMMC_FORCE_IRPT_WRITE_RDY_MSB 4 #define EMMC_FORCE_IRPT_WRITE_RDY_LSB 4 #define EMMC_FORCE_IRPT_DMA_BITS 3:3 #define EMMC_FORCE_IRPT_DMA_SET 0x00000008 #define EMMC_FORCE_IRPT_DMA_CLR 0xfffffff7 #define EMMC_FORCE_IRPT_DMA_MSB 3 #define EMMC_FORCE_IRPT_DMA_LSB 3 #define EMMC_FORCE_IRPT_BLOCK_GAP_BITS 2:2 #define EMMC_FORCE_IRPT_BLOCK_GAP_SET 0x00000004 #define EMMC_FORCE_IRPT_BLOCK_GAP_CLR 0xfffffffb #define EMMC_FORCE_IRPT_BLOCK_GAP_MSB 2 #define EMMC_FORCE_IRPT_BLOCK_GAP_LSB 2 #define EMMC_FORCE_IRPT_DATA_DONE_BITS 1:1 #define EMMC_FORCE_IRPT_DATA_DONE_SET 0x00000002 #define EMMC_FORCE_IRPT_DATA_DONE_CLR 0xfffffffd #define EMMC_FORCE_IRPT_DATA_DONE_MSB 1 #define EMMC_FORCE_IRPT_DATA_DONE_LSB 1 #define EMMC_FORCE_IRPT_CMD_DONE_BITS 0:0 #define EMMC_FORCE_IRPT_CMD_DONE_SET 0x00000001 #define EMMC_FORCE_IRPT_CMD_DONE_CLR 0xfffffffe #define EMMC_FORCE_IRPT_CMD_DONE_MSB 0 #define EMMC_FORCE_IRPT_CMD_DONE_LSB 0 #define EMMC_DMA_STATUS HW_REGISTER_RW( 0x7e300054 ) #define EMMC_DMA_STATUS_MASK 0xffff00ff #define EMMC_DMA_STATUS_WIDTH 32 #define EMMC_DMA_STATUS_RESET 0000000000 #define EMMC_DMA_STATUS_LEN_NOMATCH_BITS 2:2 #define EMMC_DMA_STATUS_LEN_NOMATCH_SET 0x00000004 #define EMMC_DMA_STATUS_LEN_NOMATCH_CLR 0xfffffffb #define EMMC_DMA_STATUS_LEN_NOMATCH_MSB 2 #define EMMC_DMA_STATUS_LEN_NOMATCH_LSB 2 #define EMMC_DMA_STATUS_ERR_AT_BITS 1:0 #define EMMC_DMA_STATUS_ERR_AT_SET 0x00000003 #define EMMC_DMA_STATUS_ERR_AT_CLR 0xfffffffc #define EMMC_DMA_STATUS_ERR_AT_MSB 1 #define EMMC_DMA_STATUS_ERR_AT_LSB 0 #define EMMC_BOOT_TIMEOUT HW_REGISTER_RW( 0x7e300070 ) #define EMMC_BOOT_TIMEOUT_MASK 0xffffffff #define EMMC_BOOT_TIMEOUT_WIDTH 32 #define EMMC_BOOT_TIMEOUT_RESET 0000000000 #define EMMC_BOOT_TIMEOUT_TIMEOUT_BITS 31:0 #define EMMC_BOOT_TIMEOUT_TIMEOUT_SET 0xffffffff #define EMMC_BOOT_TIMEOUT_TIMEOUT_CLR 0x00000000 #define EMMC_BOOT_TIMEOUT_TIMEOUT_MSB 31 #define EMMC_BOOT_TIMEOUT_TIMEOUT_LSB 0 #define EMMC_DBG_SEL HW_REGISTER_RW( 0x7e300074 ) #define EMMC_DBG_SEL_MASK 0x00000001 #define EMMC_DBG_SEL_WIDTH 1 #define EMMC_DBG_SEL_RESET 0000000000 #define EMMC_DBG_SEL_SELECT_BITS 0:0 #define EMMC_DBG_SEL_SELECT_SET 0x00000001 #define EMMC_DBG_SEL_SELECT_CLR 0xfffffffe #define EMMC_DBG_SEL_SELECT_MSB 0 #define EMMC_DBG_SEL_SELECT_LSB 0 #define EMMC_EXRDFIFO_CFG HW_REGISTER_RW( 0x7e300080 ) #define EMMC_EXRDFIFO_CFG_MASK 0x00000007 #define EMMC_EXRDFIFO_CFG_WIDTH 3 #define EMMC_EXRDFIFO_CFG_RESET 0000000000 #define EMMC_EXRDFIFO_CFG_RD_THRSH_BITS 2:0 #define EMMC_EXRDFIFO_CFG_RD_THRSH_SET 0x00000007 #define EMMC_EXRDFIFO_CFG_RD_THRSH_CLR 0xfffffff8 #define EMMC_EXRDFIFO_CFG_RD_THRSH_MSB 2 #define EMMC_EXRDFIFO_CFG_RD_THRSH_LSB 0 #define EMMC_EXRDFIFO_EN HW_REGISTER_RW( 0x7e300084 ) #define EMMC_EXRDFIFO_EN_MASK 0x00000001 #define EMMC_EXRDFIFO_EN_WIDTH 1 #define EMMC_EXRDFIFO_EN_RESET 0000000000 #define EMMC_EXRDFIFO_EN_ENABLE_BITS 0:0 #define EMMC_EXRDFIFO_EN_ENABLE_SET 0x00000001 #define EMMC_EXRDFIFO_EN_ENABLE_CLR 0xfffffffe #define EMMC_EXRDFIFO_EN_ENABLE_MSB 0 #define EMMC_EXRDFIFO_EN_ENABLE_LSB 0 #define EMMC_TUNE_STEP HW_REGISTER_RW( 0x7e300088 ) #define EMMC_TUNE_STEP_MASK 0x00000007 #define EMMC_TUNE_STEP_WIDTH 3 #define EMMC_TUNE_STEP_RESET 0000000000 #define EMMC_TUNE_STEP_DELAY_BITS 2:0 #define EMMC_TUNE_STEP_DELAY_SET 0x00000007 #define EMMC_TUNE_STEP_DELAY_CLR 0xfffffff8 #define EMMC_TUNE_STEP_DELAY_MSB 2 #define EMMC_TUNE_STEP_DELAY_LSB 0 #define EMMC_TUNE_STEPS_STD HW_REGISTER_RW( 0x7e30008c ) #define EMMC_TUNE_STEPS_STD_MASK 0x0000003f #define EMMC_TUNE_STEPS_STD_WIDTH 6 #define EMMC_TUNE_STEPS_STD_RESET 0000000000 #define EMMC_TUNE_STEPS_STD_STEPS_BITS 5:0 #define EMMC_TUNE_STEPS_STD_STEPS_SET 0x0000003f #define EMMC_TUNE_STEPS_STD_STEPS_CLR 0xffffffc0 #define EMMC_TUNE_STEPS_STD_STEPS_MSB 5 #define EMMC_TUNE_STEPS_STD_STEPS_LSB 0 #define EMMC_TUNE_STEPS_DDR HW_REGISTER_RW( 0x7e300090 ) #define EMMC_TUNE_STEPS_DDR_MASK 0x0000003f #define EMMC_TUNE_STEPS_DDR_WIDTH 6 #define EMMC_TUNE_STEPS_DDR_RESET 0000000000 #define EMMC_TUNE_STEPS_DDR_STEPS_BITS 5:0 #define EMMC_TUNE_STEPS_DDR_STEPS_SET 0x0000003f #define EMMC_TUNE_STEPS_DDR_STEPS_CLR 0xffffffc0 #define EMMC_TUNE_STEPS_DDR_STEPS_MSB 5 #define EMMC_TUNE_STEPS_DDR_STEPS_LSB 0 #define EMMC_BUS_CTRL HW_REGISTER_RW( 0x7e3000e0 ) #define EMMC_BUS_CTRL_MASK 0xffffffff #define EMMC_BUS_CTRL_WIDTH 32 #define EMMC_BUS_CTRL_RESET 0000000000 #define EMMC_BUS_CTRL_BE_PWR_BITS 30:24 #define EMMC_BUS_CTRL_BE_PWR_SET 0x7f000000 #define EMMC_BUS_CTRL_BE_PWR_CLR 0x80ffffff #define EMMC_BUS_CTRL_BE_PWR_MSB 30 #define EMMC_BUS_CTRL_BE_PWR_LSB 24 #define EMMC_BUS_CTRL_IRQSEL_BITS 22:20 #define EMMC_BUS_CTRL_IRQSEL_SET 0x00700000 #define EMMC_BUS_CTRL_IRQSEL_CLR 0xff8fffff #define EMMC_BUS_CTRL_IRQSEL_MSB 22 #define EMMC_BUS_CTRL_IRQSEL_LSB 20 #define EMMC_BUS_CTRL_BUS_WIDTH_BITS 14:8 #define EMMC_BUS_CTRL_BUS_WIDTH_SET 0x00007f00 #define EMMC_BUS_CTRL_BUS_WIDTH_CLR 0xffff80ff #define EMMC_BUS_CTRL_BUS_WIDTH_MSB 14 #define EMMC_BUS_CTRL_BUS_WIDTH_LSB 8 #define EMMC_BUS_CTRL_IRQ_PINS_BITS 5:3 #define EMMC_BUS_CTRL_IRQ_PINS_SET 0x00000038 #define EMMC_BUS_CTRL_IRQ_PINS_CLR 0xffffffc7 #define EMMC_BUS_CTRL_IRQ_PINS_MSB 5 #define EMMC_BUS_CTRL_IRQ_PINS_LSB 3 #define EMMC_BUS_CTRL_CLK_PINS_BITS 2:0 #define EMMC_BUS_CTRL_CLK_PINS_SET 0x00000007 #define EMMC_BUS_CTRL_CLK_PINS_CLR 0xfffffff8 #define EMMC_BUS_CTRL_CLK_PINS_MSB 2 #define EMMC_BUS_CTRL_CLK_PINS_LSB 0 #define EMMC_SPI_INT_SPT HW_REGISTER_RW( 0x7e3000f0 ) #define EMMC_SPI_INT_SPT_MASK 0x000000ff #define EMMC_SPI_INT_SPT_WIDTH 8 #define EMMC_SPI_INT_SPT_RESET 0000000000 #define EMMC_SPI_INT_SPT_SELECT_BITS 7:0 #define EMMC_SPI_INT_SPT_SELECT_SET 0x000000ff #define EMMC_SPI_INT_SPT_SELECT_CLR 0xffffff00 #define EMMC_SPI_INT_SPT_SELECT_MSB 7 #define EMMC_SPI_INT_SPT_SELECT_LSB 0 #define EMMC_SLOTISR_VER HW_REGISTER_RW( 0x7e3000fc ) #define EMMC_SLOTISR_VER_MASK 0xffff00ff #define EMMC_SLOTISR_VER_WIDTH 32 #define EMMC_SLOTISR_VER_RESET 0x99020000 #define EMMC_SLOTISR_VER_VENDOR_BITS 31:24 #define EMMC_SLOTISR_VER_VENDOR_SET 0xff000000 #define EMMC_SLOTISR_VER_VENDOR_CLR 0x00ffffff #define EMMC_SLOTISR_VER_VENDOR_MSB 31 #define EMMC_SLOTISR_VER_VENDOR_LSB 24 #define EMMC_SLOTISR_VER_SDVERSION_BITS 23:16 #define EMMC_SLOTISR_VER_SDVERSION_SET 0x00ff0000 #define EMMC_SLOTISR_VER_SDVERSION_CLR 0xff00ffff #define EMMC_SLOTISR_VER_SDVERSION_MSB 23 #define EMMC_SLOTISR_VER_SDVERSION_LSB 16 #define EMMC_SLOTISR_VER_SLOT_STATUS_BITS 7:0 #define EMMC_SLOTISR_VER_SLOT_STATUS_SET 0x000000ff #define EMMC_SLOTISR_VER_SLOT_STATUS_CLR 0xffffff00 #define EMMC_SLOTISR_VER_SLOT_STATUS_MSB 7 #define EMMC_SLOTISR_VER_SLOT_STATUS_LSB 0