// This file was generated by the create_regs script #define GP_BASE 0x7e200000 #define GP_APB_ID 0x6770696f #define GP_FSEL0 HW_REGISTER_RW( 0x7e200000 ) #define GP_FSEL0_MASK 0x3fffffff #define GP_FSEL0_WIDTH 30 #define GP_FSEL0_RESET 0000000000 #define GP_FSEL0_FSEL09_BITS 29:27 #define GP_FSEL0_FSEL09_SET 0x38000000 #define GP_FSEL0_FSEL09_CLR 0xc7ffffff #define GP_FSEL0_FSEL09_MSB 29 #define GP_FSEL0_FSEL09_LSB 27 #define GP_FSEL0_FSEL08_BITS 26:24 #define GP_FSEL0_FSEL08_SET 0x07000000 #define GP_FSEL0_FSEL08_CLR 0xf8ffffff #define GP_FSEL0_FSEL08_MSB 26 #define GP_FSEL0_FSEL08_LSB 24 #define GP_FSEL0_FSEL07_BITS 23:21 #define GP_FSEL0_FSEL07_SET 0x00e00000 #define GP_FSEL0_FSEL07_CLR 0xff1fffff #define GP_FSEL0_FSEL07_MSB 23 #define GP_FSEL0_FSEL07_LSB 21 #define GP_FSEL0_FSEL06_BITS 20:18 #define GP_FSEL0_FSEL06_SET 0x001c0000 #define GP_FSEL0_FSEL06_CLR 0xffe3ffff #define GP_FSEL0_FSEL06_MSB 20 #define GP_FSEL0_FSEL06_LSB 18 #define GP_FSEL0_FSEL05_BITS 17:15 #define GP_FSEL0_FSEL05_SET 0x00038000 #define GP_FSEL0_FSEL05_CLR 0xfffc7fff #define GP_FSEL0_FSEL05_MSB 17 #define GP_FSEL0_FSEL05_LSB 15 #define GP_FSEL0_FSEL04_BITS 14:12 #define GP_FSEL0_FSEL04_SET 0x00007000 #define GP_FSEL0_FSEL04_CLR 0xffff8fff #define GP_FSEL0_FSEL04_MSB 14 #define GP_FSEL0_FSEL04_LSB 12 #define GP_FSEL0_FSEL03_BITS 11:9 #define GP_FSEL0_FSEL03_SET 0x00000e00 #define GP_FSEL0_FSEL03_CLR 0xfffff1ff #define GP_FSEL0_FSEL03_MSB 11 #define GP_FSEL0_FSEL03_LSB 9 #define GP_FSEL0_FSEL02_BITS 8:6 #define GP_FSEL0_FSEL02_SET 0x000001c0 #define GP_FSEL0_FSEL02_CLR 0xfffffe3f #define GP_FSEL0_FSEL02_MSB 8 #define GP_FSEL0_FSEL02_LSB 6 #define GP_FSEL0_FSEL01_BITS 5:3 #define GP_FSEL0_FSEL01_SET 0x00000038 #define GP_FSEL0_FSEL01_CLR 0xffffffc7 #define GP_FSEL0_FSEL01_MSB 5 #define GP_FSEL0_FSEL01_LSB 3 #define GP_FSEL0_FSEL00_BITS 2:0 #define GP_FSEL0_FSEL00_SET 0x00000007 #define GP_FSEL0_FSEL00_CLR 0xfffffff8 #define GP_FSEL0_FSEL00_MSB 2 #define GP_FSEL0_FSEL00_LSB 0 #define GP_FSEL1 HW_REGISTER_RW( 0x7e200004 ) #define GP_FSEL1_MASK 0x3fffffff #define GP_FSEL1_WIDTH 30 #define GP_FSEL1_RESET 0000000000 #define GP_FSEL1_FSEL19_BITS 29:27 #define GP_FSEL1_FSEL19_SET 0x38000000 #define GP_FSEL1_FSEL19_CLR 0xc7ffffff #define GP_FSEL1_FSEL19_MSB 29 #define GP_FSEL1_FSEL19_LSB 27 #define GP_FSEL1_FSEL18_BITS 26:24 #define GP_FSEL1_FSEL18_SET 0x07000000 #define GP_FSEL1_FSEL18_CLR 0xf8ffffff #define GP_FSEL1_FSEL18_MSB 26 #define GP_FSEL1_FSEL18_LSB 24 #define GP_FSEL1_FSEL17_BITS 23:21 #define GP_FSEL1_FSEL17_SET 0x00e00000 #define GP_FSEL1_FSEL17_CLR 0xff1fffff #define GP_FSEL1_FSEL17_MSB 23 #define GP_FSEL1_FSEL17_LSB 21 #define GP_FSEL1_FSEL16_BITS 20:18 #define GP_FSEL1_FSEL16_SET 0x001c0000 #define GP_FSEL1_FSEL16_CLR 0xffe3ffff #define GP_FSEL1_FSEL16_MSB 20 #define GP_FSEL1_FSEL16_LSB 18 #define GP_FSEL1_FSEL15_BITS 17:15 #define GP_FSEL1_FSEL15_SET 0x00038000 #define GP_FSEL1_FSEL15_CLR 0xfffc7fff #define GP_FSEL1_FSEL15_MSB 17 #define GP_FSEL1_FSEL15_LSB 15 #define GP_FSEL1_FSEL14_BITS 14:12 #define GP_FSEL1_FSEL14_SET 0x00007000 #define GP_FSEL1_FSEL14_CLR 0xffff8fff #define GP_FSEL1_FSEL14_MSB 14 #define GP_FSEL1_FSEL14_LSB 12 #define GP_FSEL1_FSEL13_BITS 11:9 #define GP_FSEL1_FSEL13_SET 0x00000e00 #define GP_FSEL1_FSEL13_CLR 0xfffff1ff #define GP_FSEL1_FSEL13_MSB 11 #define GP_FSEL1_FSEL13_LSB 9 #define GP_FSEL1_FSEL12_BITS 8:6 #define GP_FSEL1_FSEL12_SET 0x000001c0 #define GP_FSEL1_FSEL12_CLR 0xfffffe3f #define GP_FSEL1_FSEL12_MSB 8 #define GP_FSEL1_FSEL12_LSB 6 #define GP_FSEL1_FSEL11_BITS 5:3 #define GP_FSEL1_FSEL11_SET 0x00000038 #define GP_FSEL1_FSEL11_CLR 0xffffffc7 #define GP_FSEL1_FSEL11_MSB 5 #define GP_FSEL1_FSEL11_LSB 3 #define GP_FSEL1_FSEL10_BITS 2:0 #define GP_FSEL1_FSEL10_SET 0x00000007 #define GP_FSEL1_FSEL10_CLR 0xfffffff8 #define GP_FSEL1_FSEL10_MSB 2 #define GP_FSEL1_FSEL10_LSB 0 #define GP_FSEL2 HW_REGISTER_RW( 0x7e200008 ) #define GP_FSEL2_MASK 0x3fffffff #define GP_FSEL2_WIDTH 30 #define GP_FSEL2_RESET 0000000000 #define GP_FSEL2_FSEL29_BITS 29:27 #define GP_FSEL2_FSEL29_SET 0x38000000 #define GP_FSEL2_FSEL29_CLR 0xc7ffffff #define GP_FSEL2_FSEL29_MSB 29 #define GP_FSEL2_FSEL29_LSB 27 #define GP_FSEL2_FSEL28_BITS 26:24 #define GP_FSEL2_FSEL28_SET 0x07000000 #define GP_FSEL2_FSEL28_CLR 0xf8ffffff #define GP_FSEL2_FSEL28_MSB 26 #define GP_FSEL2_FSEL28_LSB 24 #define GP_FSEL2_FSEL27_BITS 23:21 #define GP_FSEL2_FSEL27_SET 0x00e00000 #define GP_FSEL2_FSEL27_CLR 0xff1fffff #define GP_FSEL2_FSEL27_MSB 23 #define GP_FSEL2_FSEL27_LSB 21 #define GP_FSEL2_FSEL26_BITS 20:18 #define GP_FSEL2_FSEL26_SET 0x001c0000 #define GP_FSEL2_FSEL26_CLR 0xffe3ffff #define GP_FSEL2_FSEL26_MSB 20 #define GP_FSEL2_FSEL26_LSB 18 #define GP_FSEL2_FSEL25_BITS 17:15 #define GP_FSEL2_FSEL25_SET 0x00038000 #define GP_FSEL2_FSEL25_CLR 0xfffc7fff #define GP_FSEL2_FSEL25_MSB 17 #define GP_FSEL2_FSEL25_LSB 15 #define GP_FSEL2_FSEL24_BITS 14:12 #define GP_FSEL2_FSEL24_SET 0x00007000 #define GP_FSEL2_FSEL24_CLR 0xffff8fff #define GP_FSEL2_FSEL24_MSB 14 #define GP_FSEL2_FSEL24_LSB 12 #define GP_FSEL2_FSEL23_BITS 11:9 #define GP_FSEL2_FSEL23_SET 0x00000e00 #define GP_FSEL2_FSEL23_CLR 0xfffff1ff #define GP_FSEL2_FSEL23_MSB 11 #define GP_FSEL2_FSEL23_LSB 9 #define GP_FSEL2_FSEL22_BITS 8:6 #define GP_FSEL2_FSEL22_SET 0x000001c0 #define GP_FSEL2_FSEL22_CLR 0xfffffe3f #define GP_FSEL2_FSEL22_MSB 8 #define GP_FSEL2_FSEL22_LSB 6 #define GP_FSEL2_FSEL21_BITS 5:3 #define GP_FSEL2_FSEL21_SET 0x00000038 #define GP_FSEL2_FSEL21_CLR 0xffffffc7 #define GP_FSEL2_FSEL21_MSB 5 #define GP_FSEL2_FSEL21_LSB 3 #define GP_FSEL2_FSEL20_BITS 2:0 #define GP_FSEL2_FSEL20_SET 0x00000007 #define GP_FSEL2_FSEL20_CLR 0xfffffff8 #define GP_FSEL2_FSEL20_MSB 2 #define GP_FSEL2_FSEL20_LSB 0 #define GP_FSEL3 HW_REGISTER_RW( 0x7e20000c ) #define GP_FSEL3_MASK 0x3fffffff #define GP_FSEL3_WIDTH 30 #define GP_FSEL3_RESET 0000000000 #define GP_FSEL3_FSEL39_BITS 29:27 #define GP_FSEL3_FSEL39_SET 0x38000000 #define GP_FSEL3_FSEL39_CLR 0xc7ffffff #define GP_FSEL3_FSEL39_MSB 29 #define GP_FSEL3_FSEL39_LSB 27 #define GP_FSEL3_FSEL38_BITS 26:24 #define GP_FSEL3_FSEL38_SET 0x07000000 #define GP_FSEL3_FSEL38_CLR 0xf8ffffff #define GP_FSEL3_FSEL38_MSB 26 #define GP_FSEL3_FSEL38_LSB 24 #define GP_FSEL3_FSEL37_BITS 23:21 #define GP_FSEL3_FSEL37_SET 0x00e00000 #define GP_FSEL3_FSEL37_CLR 0xff1fffff #define GP_FSEL3_FSEL37_MSB 23 #define GP_FSEL3_FSEL37_LSB 21 #define GP_FSEL3_FSEL36_BITS 20:18 #define GP_FSEL3_FSEL36_SET 0x001c0000 #define GP_FSEL3_FSEL36_CLR 0xffe3ffff #define GP_FSEL3_FSEL36_MSB 20 #define GP_FSEL3_FSEL36_LSB 18 #define GP_FSEL3_FSEL35_BITS 17:15 #define GP_FSEL3_FSEL35_SET 0x00038000 #define GP_FSEL3_FSEL35_CLR 0xfffc7fff #define GP_FSEL3_FSEL35_MSB 17 #define GP_FSEL3_FSEL35_LSB 15 #define GP_FSEL3_FSEL34_BITS 14:12 #define GP_FSEL3_FSEL34_SET 0x00007000 #define GP_FSEL3_FSEL34_CLR 0xffff8fff #define GP_FSEL3_FSEL34_MSB 14 #define GP_FSEL3_FSEL34_LSB 12 #define GP_FSEL3_FSEL33_BITS 11:9 #define GP_FSEL3_FSEL33_SET 0x00000e00 #define GP_FSEL3_FSEL33_CLR 0xfffff1ff #define GP_FSEL3_FSEL33_MSB 11 #define GP_FSEL3_FSEL33_LSB 9 #define GP_FSEL3_FSEL32_BITS 8:6 #define GP_FSEL3_FSEL32_SET 0x000001c0 #define GP_FSEL3_FSEL32_CLR 0xfffffe3f #define GP_FSEL3_FSEL32_MSB 8 #define GP_FSEL3_FSEL32_LSB 6 #define GP_FSEL3_FSEL31_BITS 5:3 #define GP_FSEL3_FSEL31_SET 0x00000038 #define GP_FSEL3_FSEL31_CLR 0xffffffc7 #define GP_FSEL3_FSEL31_MSB 5 #define GP_FSEL3_FSEL31_LSB 3 #define GP_FSEL3_FSEL30_BITS 2:0 #define GP_FSEL3_FSEL30_SET 0x00000007 #define GP_FSEL3_FSEL30_CLR 0xfffffff8 #define GP_FSEL3_FSEL30_MSB 2 #define GP_FSEL3_FSEL30_LSB 0 #define GP_FSEL4 HW_REGISTER_RW( 0x7e200010 ) #define GP_FSEL4_MASK 0x3fffffff #define GP_FSEL4_WIDTH 30 #define GP_FSEL4_RESET 0000000000 #define GP_FSEL4_FSEL49_BITS 29:27 #define GP_FSEL4_FSEL49_SET 0x38000000 #define GP_FSEL4_FSEL49_CLR 0xc7ffffff #define GP_FSEL4_FSEL49_MSB 29 #define GP_FSEL4_FSEL49_LSB 27 #define GP_FSEL4_FSEL48_BITS 26:24 #define GP_FSEL4_FSEL48_SET 0x07000000 #define GP_FSEL4_FSEL48_CLR 0xf8ffffff #define GP_FSEL4_FSEL48_MSB 26 #define GP_FSEL4_FSEL48_LSB 24 #define GP_FSEL4_FSEL47_BITS 23:21 #define GP_FSEL4_FSEL47_SET 0x00e00000 #define GP_FSEL4_FSEL47_CLR 0xff1fffff #define GP_FSEL4_FSEL47_MSB 23 #define GP_FSEL4_FSEL47_LSB 21 #define GP_FSEL4_FSEL46_BITS 20:18 #define GP_FSEL4_FSEL46_SET 0x001c0000 #define GP_FSEL4_FSEL46_CLR 0xffe3ffff #define GP_FSEL4_FSEL46_MSB 20 #define GP_FSEL4_FSEL46_LSB 18 #define GP_FSEL4_FSEL45_BITS 17:15 #define GP_FSEL4_FSEL45_SET 0x00038000 #define GP_FSEL4_FSEL45_CLR 0xfffc7fff #define GP_FSEL4_FSEL45_MSB 17 #define GP_FSEL4_FSEL45_LSB 15 #define GP_FSEL4_FSEL44_BITS 14:12 #define GP_FSEL4_FSEL44_SET 0x00007000 #define GP_FSEL4_FSEL44_CLR 0xffff8fff #define GP_FSEL4_FSEL44_MSB 14 #define GP_FSEL4_FSEL44_LSB 12 #define GP_FSEL4_FSEL43_BITS 11:9 #define GP_FSEL4_FSEL43_SET 0x00000e00 #define GP_FSEL4_FSEL43_CLR 0xfffff1ff #define GP_FSEL4_FSEL43_MSB 11 #define GP_FSEL4_FSEL43_LSB 9 #define GP_FSEL4_FSEL42_BITS 8:6 #define GP_FSEL4_FSEL42_SET 0x000001c0 #define GP_FSEL4_FSEL42_CLR 0xfffffe3f #define GP_FSEL4_FSEL42_MSB 8 #define GP_FSEL4_FSEL42_LSB 6 #define GP_FSEL4_FSEL41_BITS 5:3 #define GP_FSEL4_FSEL41_SET 0x00000038 #define GP_FSEL4_FSEL41_CLR 0xffffffc7 #define GP_FSEL4_FSEL41_MSB 5 #define GP_FSEL4_FSEL41_LSB 3 #define GP_FSEL4_FSEL40_BITS 2:0 #define GP_FSEL4_FSEL40_SET 0x00000007 #define GP_FSEL4_FSEL40_CLR 0xfffffff8 #define GP_FSEL4_FSEL40_MSB 2 #define GP_FSEL4_FSEL40_LSB 0 #define GP_FSEL5 HW_REGISTER_RW( 0x7e200014 ) #define GP_FSEL5_MASK 0x3fffffff #define GP_FSEL5_WIDTH 30 #define GP_FSEL5_RESET 0000000000 #define GP_FSEL5_FSEL59_BITS 29:27 #define GP_FSEL5_FSEL59_SET 0x38000000 #define GP_FSEL5_FSEL59_CLR 0xc7ffffff #define GP_FSEL5_FSEL59_MSB 29 #define GP_FSEL5_FSEL59_LSB 27 #define GP_FSEL5_FSEL58_BITS 26:24 #define GP_FSEL5_FSEL58_SET 0x07000000 #define GP_FSEL5_FSEL58_CLR 0xf8ffffff #define GP_FSEL5_FSEL58_MSB 26 #define GP_FSEL5_FSEL58_LSB 24 #define GP_FSEL5_FSEL57_BITS 23:21 #define GP_FSEL5_FSEL57_SET 0x00e00000 #define GP_FSEL5_FSEL57_CLR 0xff1fffff #define GP_FSEL5_FSEL57_MSB 23 #define GP_FSEL5_FSEL57_LSB 21 #define GP_FSEL5_FSEL56_BITS 20:18 #define GP_FSEL5_FSEL56_SET 0x001c0000 #define GP_FSEL5_FSEL56_CLR 0xffe3ffff #define GP_FSEL5_FSEL56_MSB 20 #define GP_FSEL5_FSEL56_LSB 18 #define GP_FSEL5_FSEL55_BITS 17:15 #define GP_FSEL5_FSEL55_SET 0x00038000 #define GP_FSEL5_FSEL55_CLR 0xfffc7fff #define GP_FSEL5_FSEL55_MSB 17 #define GP_FSEL5_FSEL55_LSB 15 #define GP_FSEL5_FSEL54_BITS 14:12 #define GP_FSEL5_FSEL54_SET 0x00007000 #define GP_FSEL5_FSEL54_CLR 0xffff8fff #define GP_FSEL5_FSEL54_MSB 14 #define GP_FSEL5_FSEL54_LSB 12 #define GP_FSEL5_FSEL53_BITS 11:9 #define GP_FSEL5_FSEL53_SET 0x00000e00 #define GP_FSEL5_FSEL53_CLR 0xfffff1ff #define GP_FSEL5_FSEL53_MSB 11 #define GP_FSEL5_FSEL53_LSB 9 #define GP_FSEL5_FSEL52_BITS 8:6 #define GP_FSEL5_FSEL52_SET 0x000001c0 #define GP_FSEL5_FSEL52_CLR 0xfffffe3f #define GP_FSEL5_FSEL52_MSB 8 #define GP_FSEL5_FSEL52_LSB 6 #define GP_FSEL5_FSEL51_BITS 5:3 #define GP_FSEL5_FSEL51_SET 0x00000038 #define GP_FSEL5_FSEL51_CLR 0xffffffc7 #define GP_FSEL5_FSEL51_MSB 5 #define GP_FSEL5_FSEL51_LSB 3 #define GP_FSEL5_FSEL50_BITS 2:0 #define GP_FSEL5_FSEL50_SET 0x00000007 #define GP_FSEL5_FSEL50_CLR 0xfffffff8 #define GP_FSEL5_FSEL50_MSB 2 #define GP_FSEL5_FSEL50_LSB 0 #define GP_FSEL6 HW_REGISTER_RW( 0x7e200018 ) #define GP_FSEL6_MASK 0x3fffffff #define GP_FSEL6_WIDTH 30 #define GP_FSEL6_RESET 0000000000 #define GP_FSEL6_FSEL69_BITS 29:27 #define GP_FSEL6_FSEL69_SET 0x38000000 #define GP_FSEL6_FSEL69_CLR 0xc7ffffff #define GP_FSEL6_FSEL69_MSB 29 #define GP_FSEL6_FSEL69_LSB 27 #define GP_FSEL6_FSEL68_BITS 26:24 #define GP_FSEL6_FSEL68_SET 0x07000000 #define GP_FSEL6_FSEL68_CLR 0xf8ffffff #define GP_FSEL6_FSEL68_MSB 26 #define GP_FSEL6_FSEL68_LSB 24 #define GP_FSEL6_FSEL67_BITS 23:21 #define GP_FSEL6_FSEL67_SET 0x00e00000 #define GP_FSEL6_FSEL67_CLR 0xff1fffff #define GP_FSEL6_FSEL67_MSB 23 #define GP_FSEL6_FSEL67_LSB 21 #define GP_FSEL6_FSEL66_BITS 20:18 #define GP_FSEL6_FSEL66_SET 0x001c0000 #define GP_FSEL6_FSEL66_CLR 0xffe3ffff #define GP_FSEL6_FSEL66_MSB 20 #define GP_FSEL6_FSEL66_LSB 18 #define GP_FSEL6_FSEL65_BITS 17:15 #define GP_FSEL6_FSEL65_SET 0x00038000 #define GP_FSEL6_FSEL65_CLR 0xfffc7fff #define GP_FSEL6_FSEL65_MSB 17 #define GP_FSEL6_FSEL65_LSB 15 #define GP_FSEL6_FSEL64_BITS 14:12 #define GP_FSEL6_FSEL64_SET 0x00007000 #define GP_FSEL6_FSEL64_CLR 0xffff8fff #define GP_FSEL6_FSEL64_MSB 14 #define GP_FSEL6_FSEL64_LSB 12 #define GP_FSEL6_FSEL63_BITS 11:9 #define GP_FSEL6_FSEL63_SET 0x00000e00 #define GP_FSEL6_FSEL63_CLR 0xfffff1ff #define GP_FSEL6_FSEL63_MSB 11 #define GP_FSEL6_FSEL63_LSB 9 #define GP_FSEL6_FSEL62_BITS 8:6 #define GP_FSEL6_FSEL62_SET 0x000001c0 #define GP_FSEL6_FSEL62_CLR 0xfffffe3f #define GP_FSEL6_FSEL62_MSB 8 #define GP_FSEL6_FSEL62_LSB 6 #define GP_FSEL6_FSEL61_BITS 5:3 #define GP_FSEL6_FSEL61_SET 0x00000038 #define GP_FSEL6_FSEL61_CLR 0xffffffc7 #define GP_FSEL6_FSEL61_MSB 5 #define GP_FSEL6_FSEL61_LSB 3 #define GP_FSEL6_FSEL60_BITS 2:0 #define GP_FSEL6_FSEL60_SET 0x00000007 #define GP_FSEL6_FSEL60_CLR 0xfffffff8 #define GP_FSEL6_FSEL60_MSB 2 #define GP_FSEL6_FSEL60_LSB 0 #define GP_SET0 HW_REGISTER_RW( 0x7e20001c ) #define GP_SET0_MASK 0xffffffff #define GP_SET0_WIDTH 32 #define GP_SET0_RESET 0000000000 #define GP_SET0_SETn0_BITS 31:0 #define GP_SET0_SETn0_SET 0xffffffff #define GP_SET0_SETn0_CLR 0x00000000 #define GP_SET0_SETn0_MSB 31 #define GP_SET0_SETn0_LSB 0 #define GP_SET1 HW_REGISTER_RW( 0x7e200020 ) #define GP_SET1_MASK 0xffffffff #define GP_SET1_WIDTH 32 #define GP_SET1_RESET 0000000000 #define GP_SET1_SETn32_BITS 31:0 #define GP_SET1_SETn32_SET 0xffffffff #define GP_SET1_SETn32_CLR 0x00000000 #define GP_SET1_SETn32_MSB 31 #define GP_SET1_SETn32_LSB 0 #define GP_SET2 HW_REGISTER_RW( 0x7e200024 ) #define GP_SET2_MASK 0x0000003f #define GP_SET2_WIDTH 6 #define GP_SET2_RESET 0000000000 #define GP_SET2_SETn64_BITS 5:0 #define GP_SET2_SETn64_SET 0x0000003f #define GP_SET2_SETn64_CLR 0xffffffc0 #define GP_SET2_SETn64_MSB 5 #define GP_SET2_SETn64_LSB 0 #define GP_CLR0 HW_REGISTER_RW( 0x7e200028 ) #define GP_CLR0_MASK 0xffffffff #define GP_CLR0_WIDTH 32 #define GP_CLR0_RESET 0000000000 #define GP_CLR0_CLRn0_BITS 31:0 #define GP_CLR0_CLRn0_SET 0xffffffff #define GP_CLR0_CLRn0_CLR 0x00000000 #define GP_CLR0_CLRn0_MSB 31 #define GP_CLR0_CLRn0_LSB 0 #define GP_CLR1 HW_REGISTER_RW( 0x7e20002c ) #define GP_CLR1_MASK 0xffffffff #define GP_CLR1_WIDTH 32 #define GP_CLR1_RESET 0000000000 #define GP_CLR1_CLRn32_BITS 31:0 #define GP_CLR1_CLRn32_SET 0xffffffff #define GP_CLR1_CLRn32_CLR 0x00000000 #define GP_CLR1_CLRn32_MSB 31 #define GP_CLR1_CLRn32_LSB 0 #define GP_CLR2 HW_REGISTER_RW( 0x7e200030 ) #define GP_CLR2_MASK 0x0000003f #define GP_CLR2_WIDTH 6 #define GP_CLR2_RESET 0000000000 #define GP_CLR2_CLRn64_BITS 5:0 #define GP_CLR2_CLRn64_SET 0x0000003f #define GP_CLR2_CLRn64_CLR 0xffffffc0 #define GP_CLR2_CLRn64_MSB 5 #define GP_CLR2_CLRn64_LSB 0 #define GP_LEV0 HW_REGISTER_RO( 0x7e200034 ) #define GP_LEV0_MASK 0xffffffff #define GP_LEV0_WIDTH 32 #define GP_LEV0_RESET 0000000000 #define GP_LEV0_LEVn0_BITS 31:0 #define GP_LEV0_LEVn0_SET 0xffffffff #define GP_LEV0_LEVn0_CLR 0x00000000 #define GP_LEV0_LEVn0_MSB 31 #define GP_LEV0_LEVn0_LSB 0 #define GP_LEV1 HW_REGISTER_RO( 0x7e200038 ) #define GP_LEV1_MASK 0xffffffff #define GP_LEV1_WIDTH 32 #define GP_LEV1_RESET 0000000000 #define GP_LEV1_LEVn32_BITS 31:0 #define GP_LEV1_LEVn32_SET 0xffffffff #define GP_LEV1_LEVn32_CLR 0x00000000 #define GP_LEV1_LEVn32_MSB 31 #define GP_LEV1_LEVn32_LSB 0 #define GP_LEV2 HW_REGISTER_RO( 0x7e20003c ) #define GP_LEV2_MASK 0x0000003f #define GP_LEV2_WIDTH 6 #define GP_LEV2_RESET 0000000000 #define GP_LEV2_LEVn64_BITS 5:0 #define GP_LEV2_LEVn64_SET 0x0000003f #define GP_LEV2_LEVn64_CLR 0xffffffc0 #define GP_LEV2_LEVn64_MSB 5 #define GP_LEV2_LEVn64_LSB 0 #define GP_EDS0 HW_REGISTER_RW( 0x7e200040 ) #define GP_EDS0_MASK 0xffffffff #define GP_EDS0_WIDTH 32 #define GP_EDS0_RESET 0000000000 #define GP_EDS0_EDSn0_BITS 31:0 #define GP_EDS0_EDSn0_SET 0xffffffff #define GP_EDS0_EDSn0_CLR 0x00000000 #define GP_EDS0_EDSn0_MSB 31 #define GP_EDS0_EDSn0_LSB 0 #define GP_EDS1 HW_REGISTER_RW( 0x7e200044 ) #define GP_EDS1_MASK 0xffffffff #define GP_EDS1_WIDTH 32 #define GP_EDS1_RESET 0000000000 #define GP_EDS1_EDSn32_BITS 31:0 #define GP_EDS1_EDSn32_SET 0xffffffff #define GP_EDS1_EDSn32_CLR 0x00000000 #define GP_EDS1_EDSn32_MSB 31 #define GP_EDS1_EDSn32_LSB 0 #define GP_EDS2 HW_REGISTER_RW( 0x7e200048 ) #define GP_EDS2_MASK 0x0000003f #define GP_EDS2_WIDTH 6 #define GP_EDS2_RESET 0000000000 #define GP_EDS2_EDSn64_BITS 5:0 #define GP_EDS2_EDSn64_SET 0x0000003f #define GP_EDS2_EDSn64_CLR 0xffffffc0 #define GP_EDS2_EDSn64_MSB 5 #define GP_EDS2_EDSn64_LSB 0 #define GP_REN0 HW_REGISTER_RW( 0x7e20004c ) #define GP_REN0_MASK 0xffffffff #define GP_REN0_WIDTH 32 #define GP_REN0_RESET 0000000000 #define GP_REN0_RENn0_BITS 31:0 #define GP_REN0_RENn0_SET 0xffffffff #define GP_REN0_RENn0_CLR 0x00000000 #define GP_REN0_RENn0_MSB 31 #define GP_REN0_RENn0_LSB 0 #define GP_REN1 HW_REGISTER_RW( 0x7e200050 ) #define GP_REN1_MASK 0xffffffff #define GP_REN1_WIDTH 32 #define GP_REN1_RESET 0000000000 #define GP_REN1_RENn32_BITS 31:0 #define GP_REN1_RENn32_SET 0xffffffff #define GP_REN1_RENn32_CLR 0x00000000 #define GP_REN1_RENn32_MSB 31 #define GP_REN1_RENn32_LSB 0 #define GP_REN2 HW_REGISTER_RW( 0x7e200054 ) #define GP_REN2_MASK 0x0000003f #define GP_REN2_WIDTH 6 #define GP_REN2_RESET 0000000000 #define GP_REN2_RENn64_BITS 5:0 #define GP_REN2_RENn64_SET 0x0000003f #define GP_REN2_RENn64_CLR 0xffffffc0 #define GP_REN2_RENn64_MSB 5 #define GP_REN2_RENn64_LSB 0 #define GP_FEN0 HW_REGISTER_RW( 0x7e200058 ) #define GP_FEN0_MASK 0xffffffff #define GP_FEN0_WIDTH 32 #define GP_FEN0_RESET 0000000000 #define GP_FEN0_FENn0_BITS 31:0 #define GP_FEN0_FENn0_SET 0xffffffff #define GP_FEN0_FENn0_CLR 0x00000000 #define GP_FEN0_FENn0_MSB 31 #define GP_FEN0_FENn0_LSB 0 #define GP_FEN1 HW_REGISTER_RW( 0x7e20005c ) #define GP_FEN1_MASK 0xffffffff #define GP_FEN1_WIDTH 32 #define GP_FEN1_RESET 0000000000 #define GP_FEN1_FENn32_BITS 31:0 #define GP_FEN1_FENn32_SET 0xffffffff #define GP_FEN1_FENn32_CLR 0x00000000 #define GP_FEN1_FENn32_MSB 31 #define GP_FEN1_FENn32_LSB 0 #define GP_FEN2 HW_REGISTER_RW( 0x7e200060 ) #define GP_FEN2_MASK 0x0000003f #define GP_FEN2_WIDTH 6 #define GP_FEN2_RESET 0000000000 #define GP_FEN2_FENn64_BITS 5:0 #define GP_FEN2_FENn64_SET 0x0000003f #define GP_FEN2_FENn64_CLR 0xffffffc0 #define GP_FEN2_FENn64_MSB 5 #define GP_FEN2_FENn64_LSB 0 #define GP_HEN0 HW_REGISTER_RW( 0x7e200064 ) #define GP_HEN0_MASK 0xffffffff #define GP_HEN0_WIDTH 32 #define GP_HEN0_RESET 0000000000 #define GP_HEN0_HENn0_BITS 31:0 #define GP_HEN0_HENn0_SET 0xffffffff #define GP_HEN0_HENn0_CLR 0x00000000 #define GP_HEN0_HENn0_MSB 31 #define GP_HEN0_HENn0_LSB 0 #define GP_HEN1 HW_REGISTER_RW( 0x7e200068 ) #define GP_HEN1_MASK 0xffffffff #define GP_HEN1_WIDTH 32 #define GP_HEN1_RESET 0000000000 #define GP_HEN1_HENn32_BITS 31:0 #define GP_HEN1_HENn32_SET 0xffffffff #define GP_HEN1_HENn32_CLR 0x00000000 #define GP_HEN1_HENn32_MSB 31 #define GP_HEN1_HENn32_LSB 0 #define GP_HEN2 HW_REGISTER_RW( 0x7e20006c ) #define GP_HEN2_MASK 0x0000003f #define GP_HEN2_WIDTH 6 #define GP_HEN2_RESET 0000000000 #define GP_HEN2_HENn64_BITS 5:0 #define GP_HEN2_HENn64_SET 0x0000003f #define GP_HEN2_HENn64_CLR 0xffffffc0 #define GP_HEN2_HENn64_MSB 5 #define GP_HEN2_HENn64_LSB 0 #define GP_LEN0 HW_REGISTER_RW( 0x7e200070 ) #define GP_LEN0_MASK 0xffffffff #define GP_LEN0_WIDTH 32 #define GP_LEN0_RESET 0000000000 #define GP_LEN0_LENn0_BITS 31:0 #define GP_LEN0_LENn0_SET 0xffffffff #define GP_LEN0_LENn0_CLR 0x00000000 #define GP_LEN0_LENn0_MSB 31 #define GP_LEN0_LENn0_LSB 0 #define GP_LEN1 HW_REGISTER_RW( 0x7e200074 ) #define GP_LEN1_MASK 0xffffffff #define GP_LEN1_WIDTH 32 #define GP_LEN1_RESET 0000000000 #define GP_LEN1_LENn32_BITS 31:0 #define GP_LEN1_LENn32_SET 0xffffffff #define GP_LEN1_LENn32_CLR 0x00000000 #define GP_LEN1_LENn32_MSB 31 #define GP_LEN1_LENn32_LSB 0 #define GP_LEN2 HW_REGISTER_RW( 0x7e200078 ) #define GP_LEN2_MASK 0x0000003f #define GP_LEN2_WIDTH 6 #define GP_LEN2_RESET 0000000000 #define GP_LEN2_LENn64_BITS 5:0 #define GP_LEN2_LENn64_SET 0x0000003f #define GP_LEN2_LENn64_CLR 0xffffffc0 #define GP_LEN2_LENn64_MSB 5 #define GP_LEN2_LENn64_LSB 0 #define GP_AREN0 HW_REGISTER_RW( 0x7e20007c ) #define GP_AREN0_MASK 0xffffffff #define GP_AREN0_WIDTH 32 #define GP_AREN0_RESET 0000000000 #define GP_AREN0_ARENn0_BITS 31:0 #define GP_AREN0_ARENn0_SET 0xffffffff #define GP_AREN0_ARENn0_CLR 0x00000000 #define GP_AREN0_ARENn0_MSB 31 #define GP_AREN0_ARENn0_LSB 0 #define GP_AREN1 HW_REGISTER_RW( 0x7e200080 ) #define GP_AREN1_MASK 0xffffffff #define GP_AREN1_WIDTH 32 #define GP_AREN1_RESET 0000000000 #define GP_AREN1_ARENn32_BITS 31:0 #define GP_AREN1_ARENn32_SET 0xffffffff #define GP_AREN1_ARENn32_CLR 0x00000000 #define GP_AREN1_ARENn32_MSB 31 #define GP_AREN1_ARENn32_LSB 0 #define GP_AREN2 HW_REGISTER_RW( 0x7e200084 ) #define GP_AREN2_MASK 0x0000003f #define GP_AREN2_WIDTH 6 #define GP_AREN2_RESET 0000000000 #define GP_AREN2_ARENn64_BITS 5:0 #define GP_AREN2_ARENn64_SET 0x0000003f #define GP_AREN2_ARENn64_CLR 0xffffffc0 #define GP_AREN2_ARENn64_MSB 5 #define GP_AREN2_ARENn64_LSB 0 #define GP_AFEN0 HW_REGISTER_RW( 0x7e200088 ) #define GP_AFEN0_MASK 0xffffffff #define GP_AFEN0_WIDTH 32 #define GP_AFEN0_RESET 0000000000 #define GP_AFEN0_AFENn0_BITS 31:0 #define GP_AFEN0_AFENn0_SET 0xffffffff #define GP_AFEN0_AFENn0_CLR 0x00000000 #define GP_AFEN0_AFENn0_MSB 31 #define GP_AFEN0_AFENn0_LSB 0 #define GP_AFEN1 HW_REGISTER_RW( 0x7e20008c ) #define GP_AFEN1_MASK 0xffffffff #define GP_AFEN1_WIDTH 32 #define GP_AFEN1_RESET 0000000000 #define GP_AFEN1_AFENn32_BITS 31:0 #define GP_AFEN1_AFENn32_SET 0xffffffff #define GP_AFEN1_AFENn32_CLR 0x00000000 #define GP_AFEN1_AFENn32_MSB 31 #define GP_AFEN1_AFENn32_LSB 0 #define GP_AFEN2 HW_REGISTER_RW( 0x7e200090 ) #define GP_AFEN2_MASK 0x0000003f #define GP_AFEN2_WIDTH 6 #define GP_AFEN2_RESET 0000000000 #define GP_AFEN2_AFENn64_BITS 5:0 #define GP_AFEN2_AFENn64_SET 0x0000003f #define GP_AFEN2_AFENn64_CLR 0xffffffc0 #define GP_AFEN2_AFENn64_MSB 5 #define GP_AFEN2_AFENn64_LSB 0 #define GP_PUD HW_REGISTER_RW( 0x7e200094 ) #define GP_PUD_MASK 0x00000003 #define GP_PUD_WIDTH 2 #define GP_PUD_RESET 0000000000 #define GP_PUD_PUD_BITS 1:0 #define GP_PUD_PUD_SET 0x00000003 #define GP_PUD_PUD_CLR 0xfffffffc #define GP_PUD_PUD_MSB 1 #define GP_PUD_PUD_LSB 0 #define GP_PUDCLK0 HW_REGISTER_RW( 0x7e200098 ) #define GP_PUDCLK0_MASK 0xffffffff #define GP_PUDCLK0_WIDTH 32 #define GP_PUDCLK0_RESET 0000000000 #define GP_PUDCLK0_PUDCLKn0_BITS 31:0 #define GP_PUDCLK0_PUDCLKn0_SET 0xffffffff #define GP_PUDCLK0_PUDCLKn0_CLR 0x00000000 #define GP_PUDCLK0_PUDCLKn0_MSB 31 #define GP_PUDCLK0_PUDCLKn0_LSB 0 #define GP_PUDCLK1 HW_REGISTER_RW( 0x7e20009c ) #define GP_PUDCLK1_MASK 0xffffffff #define GP_PUDCLK1_WIDTH 32 #define GP_PUDCLK1_RESET 0000000000 #define GP_PUDCLK1_PUDCLKn32_BITS 31:0 #define GP_PUDCLK1_PUDCLKn32_SET 0xffffffff #define GP_PUDCLK1_PUDCLKn32_CLR 0x00000000 #define GP_PUDCLK1_PUDCLKn32_MSB 31 #define GP_PUDCLK1_PUDCLKn32_LSB 0 #define GP_PUDCLK2 HW_REGISTER_RW( 0x7e2000a0 ) #define GP_PUDCLK2_MASK 0x0000003f #define GP_PUDCLK2_WIDTH 6 #define GP_PUDCLK2_RESET 0000000000 #define GP_PUDCLK2_PUDCLKn64_BITS 5:0 #define GP_PUDCLK2_PUDCLKn64_SET 0x0000003f #define GP_PUDCLK2_PUDCLKn64_CLR 0xffffffc0 #define GP_PUDCLK2_PUDCLKn64_MSB 5 #define GP_PUDCLK2_PUDCLKn64_LSB 0 #define GP_SEN0 HW_REGISTER_RW( 0x7e2000a4 ) #define GP_SEN0_MASK 0xffffffff #define GP_SEN0_WIDTH 32 #define GP_SEN0_RESET 0xffffffff #define GP_SEN0_SEN_BITS 31:0 #define GP_SEN0_SEN_SET 0xffffffff #define GP_SEN0_SEN_CLR 0x00000000 #define GP_SEN0_SEN_MSB 31 #define GP_SEN0_SEN_LSB 0 #define GP_SEN1 HW_REGISTER_RW( 0x7e2000a8 ) #define GP_SEN1_MASK 0x003fffff #define GP_SEN1_WIDTH 22 #define GP_SEN1_RESET 0x003fffff #define GP_SEN1_SEN_BITS 21:0 #define GP_SEN1_SEN_SET 0x003fffff #define GP_SEN1_SEN_CLR 0xffc00000 #define GP_SEN1_SEN_MSB 21 #define GP_SEN1_SEN_LSB 0 #define GP_GPTEST HW_REGISTER_RW( 0x7e2000b0 ) #define GP_GPTEST_MASK 0x0000000f #define GP_GPTEST_WIDTH 4 #define GP_GPTEST_RESET 0000000000 #define GP_GPTEST_SMPS_BITS 0:0 #define GP_GPTEST_SMPS_SET 0x00000001 #define GP_GPTEST_SMPS_CLR 0xfffffffe #define GP_GPTEST_SMPS_MSB 0 #define GP_GPTEST_SMPS_LSB 0 #define GP_GPTEST_SPARE_BITS 3:1 #define GP_GPTEST_SPARE_SET 0x0000000e #define GP_GPTEST_SPARE_CLR 0xfffffff1 #define GP_GPTEST_SPARE_MSB 3 #define GP_GPTEST_SPARE_LSB 1 #define GP_AJBCONF HW_REGISTER_RW( 0x7e2000c0 ) #define GP_AJBCONF_MASK 0x80ffffff #define GP_AJBCONF_WIDTH 32 #define GP_AJBCONF_RESET 0000000000 #define GP_AJBTMS HW_REGISTER_RW( 0x7e2000c4 ) #define GP_AJBTMS_MASK 0xffffffff #define GP_AJBTMS_WIDTH 32 #define GP_AJBTMS_RESET 0000000000 #define GP_AJBTDI HW_REGISTER_RW( 0x7e2000c8 ) #define GP_AJBTDI_MASK 0xffffffff #define GP_AJBTDI_WIDTH 32 #define GP_AJBTDI_RESET 0000000000 #define GP_AJBTDO HW_REGISTER_RW( 0x7e2000cc ) #define GP_AJBTDO_MASK 0xffffffff #define GP_AJBTDO_WIDTH 32 #define GP_AJBTDO_RESET 0000000000