// This file was generated by the create_regs script #define IC0_BASE 0x7e002000 #define IC0_APB_ID 0x494e5445 #define IC0_C HW_REGISTER_RW( 0x7e002000 ) #define IC0_C_MASK 0x0000000f #define IC0_C_WIDTH 4 #define IC0_C_RESET 0000000000 #define IC0_S HW_REGISTER_RO( 0x7e002004 ) #define IC0_S_MASK 0x073f073f #define IC0_S_WIDTH 27 #define IC0_SRC0 HW_REGISTER_RO( 0x7e002008 ) #define IC0_SRC0_MASK 0xffffffff #define IC0_SRC0_WIDTH 32 #define IC0_SRC1 HW_REGISTER_RO( 0x7e00200c ) #define IC0_SRC1_MASK 0xffffffff #define IC0_SRC1_WIDTH 32 #define IC0_MASK0 HW_REGISTER_RW( 0x7e002010 ) #define IC0_MASK0_MASK 0x77777777 #define IC0_MASK0_WIDTH 31 #define IC0_MASK0_RESET 0000000000 #define IC0_MASK1 HW_REGISTER_RW( 0x7e002014 ) #define IC0_MASK1_MASK 0x77777777 #define IC0_MASK1_WIDTH 31 #define IC0_MASK1_RESET 0000000000 #define IC0_MASK2 HW_REGISTER_RW( 0x7e002018 ) #define IC0_MASK2_MASK 0x77777777 #define IC0_MASK2_WIDTH 31 #define IC0_MASK2_RESET 0000000000 #define IC0_MASK3 HW_REGISTER_RW( 0x7e00201c ) #define IC0_MASK3_MASK 0x77777777 #define IC0_MASK3_WIDTH 31 #define IC0_MASK3_RESET 0000000000 #define IC0_MASK4 HW_REGISTER_RW( 0x7e002020 ) #define IC0_MASK4_MASK 0x77777777 #define IC0_MASK4_WIDTH 31 #define IC0_MASK4_RESET 0000000000 #define IC0_MASK5 HW_REGISTER_RW( 0x7e002024 ) #define IC0_MASK5_MASK 0x77777777 #define IC0_MASK5_WIDTH 31 #define IC0_MASK5_RESET 0000000000 #define IC0_MASK6 HW_REGISTER_RW( 0x7e002028 ) #define IC0_MASK6_MASK 0x77777777 #define IC0_MASK6_WIDTH 31 #define IC0_MASK6_RESET 0000000000 #define IC0_MASK7 HW_REGISTER_RW( 0x7e00202c ) #define IC0_MASK7_MASK 0x77777777 #define IC0_MASK7_WIDTH 31 #define IC0_MASK7_RESET 0000000000 #define IC0_VADDR HW_REGISTER_RW( 0x7e002030 ) #define IC0_VADDR_MASK 0xfffffe00 #define IC0_VADDR_WIDTH 32 #define IC0_VADDR_RESET 0000000000 #define IC0_WAKEUP HW_REGISTER_RW( 0x7e002034 ) #define IC0_WAKEUP_MASK 0xfffffffe #define IC0_WAKEUP_WIDTH 32 #define IC0_WAKEUP_RESET 0x10000000 #define IC0_PROFILE HW_REGISTER_RW( 0x7e002038 ) #define IC0_PROFILE_MASK 0x0000ffff #define IC0_PROFILE_WIDTH 16 #define IC0_FORCE0 HW_REGISTER_RW( 0x7e002040 ) #define IC0_FORCE0_MASK 0xffffffff #define IC0_FORCE0_WIDTH 32 #define IC0_FORCE0_RESET 0000000000 #define IC0_FORCE1 HW_REGISTER_RW( 0x7e002044 ) #define IC0_FORCE1_MASK 0xffffffff #define IC0_FORCE1_WIDTH 32 #define IC0_FORCE1_RESET 0000000000 #define IC0_FORCE0_SET HW_REGISTER_RW( 0x7e002048 ) #define IC0_FORCE0_SET_MASK 0xffffffff #define IC0_FORCE0_SET_WIDTH 32 #define IC0_FORCE0_SET_RESET 0000000000 #define IC0_FORCE1_SET HW_REGISTER_RW( 0x7e00204c ) #define IC0_FORCE1_SET_MASK 0xffffffff #define IC0_FORCE1_SET_WIDTH 32 #define IC0_FORCE1_SET_RESET 0000000000 #define IC0_FORCE0_CLR HW_REGISTER_RW( 0x7e002050 ) #define IC0_FORCE0_CLR_MASK 0xffffffff #define IC0_FORCE0_CLR_WIDTH 32 #define IC0_FORCE0_CLR_RESET 0000000000 #define IC0_FORCE1_CLR HW_REGISTER_RW( 0x7e002054 ) #define IC0_FORCE1_CLR_MASK 0xffffffff #define IC0_FORCE1_CLR_WIDTH 32 #define IC0_FORCE1_CLR_RESET 0000000000