// This file was generated by the create_regs script
#define MS_BASE 0x7e000000
#define MS_APB_ID 0x4d554c54
#define MS_SEMA_0 HW_REGISTER_RW( 0x7e000000 )
#define MS_SEMA_0_MASK 0x00000001
#define MS_SEMA_0_WIDTH 1
#define MS_SEMA_0_RESET 0000000000
#define MS_SEMA_0_MASK_BITS 0:0
#define MS_SEMA_0_MASK_SET 0x00000001
#define MS_SEMA_0_MASK_CLR 0xfffffffe
#define MS_SEMA_0_MASK_MSB 0
#define MS_SEMA_0_MASK_LSB 0
#define MS_SEMA_1 HW_REGISTER_RW( 0x7e000004 )
#define MS_SEMA_1_MASK 0x00000001
#define MS_SEMA_1_WIDTH 1
#define MS_SEMA_1_RESET 0000000000
#define MS_SEMA_1_MASK_BITS 0:0
#define MS_SEMA_1_MASK_SET 0x00000001
#define MS_SEMA_1_MASK_CLR 0xfffffffe
#define MS_SEMA_1_MASK_MSB 0
#define MS_SEMA_1_MASK_LSB 0
#define MS_SEMA_2 HW_REGISTER_RW( 0x7e000008 )
#define MS_SEMA_2_MASK 0x00000001
#define MS_SEMA_2_WIDTH 1
#define MS_SEMA_2_RESET 0000000000
#define MS_SEMA_2_MASK_BITS 0:0
#define MS_SEMA_2_MASK_SET 0x00000001
#define MS_SEMA_2_MASK_CLR 0xfffffffe
#define MS_SEMA_2_MASK_MSB 0
#define MS_SEMA_2_MASK_LSB 0
#define MS_SEMA_3 HW_REGISTER_RW( 0x7e00000c )
#define MS_SEMA_3_MASK 0x00000001
#define MS_SEMA_3_WIDTH 1
#define MS_SEMA_3_RESET 0000000000
#define MS_SEMA_3_MASK_BITS 0:0
#define MS_SEMA_3_MASK_SET 0x00000001
#define MS_SEMA_3_MASK_CLR 0xfffffffe
#define MS_SEMA_3_MASK_MSB 0
#define MS_SEMA_3_MASK_LSB 0
#define MS_SEMA_4 HW_REGISTER_RW( 0x7e000010 )
#define MS_SEMA_4_MASK 0x00000001
#define MS_SEMA_4_WIDTH 1
#define MS_SEMA_4_RESET 0000000000
#define MS_SEMA_4_MASK_BITS 0:0
#define MS_SEMA_4_MASK_SET 0x00000001
#define MS_SEMA_4_MASK_CLR 0xfffffffe
#define MS_SEMA_4_MASK_MSB 0
#define MS_SEMA_4_MASK_LSB 0
#define MS_SEMA_5 HW_REGISTER_RW( 0x7e000014 )
#define MS_SEMA_5_MASK 0x00000001
#define MS_SEMA_5_WIDTH 1
#define MS_SEMA_5_RESET 0000000000
#define MS_SEMA_5_MASK_BITS 0:0
#define MS_SEMA_5_MASK_SET 0x00000001
#define MS_SEMA_5_MASK_CLR 0xfffffffe
#define MS_SEMA_5_MASK_MSB 0
#define MS_SEMA_5_MASK_LSB 0
#define MS_SEMA_6 HW_REGISTER_RW( 0x7e000018 )
#define MS_SEMA_6_MASK 0x00000001
#define MS_SEMA_6_WIDTH 1
#define MS_SEMA_6_RESET 0000000000
#define MS_SEMA_6_MASK_BITS 0:0
#define MS_SEMA_6_MASK_SET 0x00000001
#define MS_SEMA_6_MASK_CLR 0xfffffffe
#define MS_SEMA_6_MASK_MSB 0
#define MS_SEMA_6_MASK_LSB 0
#define MS_SEMA_7 HW_REGISTER_RW( 0x7e00001c )
#define MS_SEMA_7_MASK 0x00000001
#define MS_SEMA_7_WIDTH 1
#define MS_SEMA_7_RESET 0000000000
#define MS_SEMA_7_MASK_BITS 0:0
#define MS_SEMA_7_MASK_SET 0x00000001
#define MS_SEMA_7_MASK_CLR 0xfffffffe
#define MS_SEMA_7_MASK_MSB 0
#define MS_SEMA_7_MASK_LSB 0
#define MS_SEMA_8 HW_REGISTER_RW( 0x7e000020 )
#define MS_SEMA_8_MASK 0x00000001
#define MS_SEMA_8_WIDTH 1
#define MS_SEMA_8_RESET 0000000000
#define MS_SEMA_8_MASK_BITS 0:0
#define MS_SEMA_8_MASK_SET 0x00000001
#define MS_SEMA_8_MASK_CLR 0xfffffffe
#define MS_SEMA_8_MASK_MSB 0
#define MS_SEMA_8_MASK_LSB 0
#define MS_SEMA_9 HW_REGISTER_RW( 0x7e000024 )
#define MS_SEMA_9_MASK 0x00000001
#define MS_SEMA_9_WIDTH 1
#define MS_SEMA_9_RESET 0000000000
#define MS_SEMA_9_MASK_BITS 0:0
#define MS_SEMA_9_MASK_SET 0x00000001
#define MS_SEMA_9_MASK_CLR 0xfffffffe
#define MS_SEMA_9_MASK_MSB 0
#define MS_SEMA_9_MASK_LSB 0
#define MS_SEMA_10 HW_REGISTER_RW( 0x7e000028 )
#define MS_SEMA_10_MASK 0x00000001
#define MS_SEMA_10_WIDTH 1
#define MS_SEMA_10_RESET 0000000000
#define MS_SEMA_10_MASK_BITS 0:0
#define MS_SEMA_10_MASK_SET 0x00000001
#define MS_SEMA_10_MASK_CLR 0xfffffffe
#define MS_SEMA_10_MASK_MSB 0
#define MS_SEMA_10_MASK_LSB 0
#define MS_SEMA_11 HW_REGISTER_RW( 0x7e00002c )
#define MS_SEMA_11_MASK 0x00000001
#define MS_SEMA_11_WIDTH 1
#define MS_SEMA_11_RESET 0000000000
#define MS_SEMA_11_MASK_BITS 0:0
#define MS_SEMA_11_MASK_SET 0x00000001
#define MS_SEMA_11_MASK_CLR 0xfffffffe
#define MS_SEMA_11_MASK_MSB 0
#define MS_SEMA_11_MASK_LSB 0
#define MS_SEMA_12 HW_REGISTER_RW( 0x7e000030 )
#define MS_SEMA_12_MASK 0x00000001
#define MS_SEMA_12_WIDTH 1
#define MS_SEMA_12_RESET 0000000000
#define MS_SEMA_12_MASK_BITS 0:0
#define MS_SEMA_12_MASK_SET 0x00000001
#define MS_SEMA_12_MASK_CLR 0xfffffffe
#define MS_SEMA_12_MASK_MSB 0
#define MS_SEMA_12_MASK_LSB 0
#define MS_SEMA_13 HW_REGISTER_RW( 0x7e000034 )
#define MS_SEMA_13_MASK 0x00000001
#define MS_SEMA_13_WIDTH 1
#define MS_SEMA_13_RESET 0000000000
#define MS_SEMA_13_MASK_BITS 0:0
#define MS_SEMA_13_MASK_SET 0x00000001
#define MS_SEMA_13_MASK_CLR 0xfffffffe
#define MS_SEMA_13_MASK_MSB 0
#define MS_SEMA_13_MASK_LSB 0
#define MS_SEMA_14 HW_REGISTER_RW( 0x7e000038 )
#define MS_SEMA_14_MASK 0x00000001
#define MS_SEMA_14_WIDTH 1
#define MS_SEMA_14_RESET 0000000000
#define MS_SEMA_14_MASK_BITS 0:0
#define MS_SEMA_14_MASK_SET 0x00000001
#define MS_SEMA_14_MASK_CLR 0xfffffffe
#define MS_SEMA_14_MASK_MSB 0
#define MS_SEMA_14_MASK_LSB 0
#define MS_SEMA_15 HW_REGISTER_RW( 0x7e00003c )
#define MS_SEMA_15_MASK 0x00000001
#define MS_SEMA_15_WIDTH 1
#define MS_SEMA_15_RESET 0000000000
#define MS_SEMA_15_MASK_BITS 0:0
#define MS_SEMA_15_MASK_SET 0x00000001
#define MS_SEMA_15_MASK_CLR 0xfffffffe
#define MS_SEMA_15_MASK_MSB 0
#define MS_SEMA_15_MASK_LSB 0
#define MS_SEMA_16 HW_REGISTER_RW( 0x7e000040 )
#define MS_SEMA_16_MASK 0x00000001
#define MS_SEMA_16_WIDTH 1
#define MS_SEMA_16_RESET 0000000000
#define MS_SEMA_16_MASK_BITS 0:0
#define MS_SEMA_16_MASK_SET 0x00000001
#define MS_SEMA_16_MASK_CLR 0xfffffffe
#define MS_SEMA_16_MASK_MSB 0
#define MS_SEMA_16_MASK_LSB 0
#define MS_SEMA_17 HW_REGISTER_RW( 0x7e000044 )
#define MS_SEMA_17_MASK 0x00000001
#define MS_SEMA_17_WIDTH 1
#define MS_SEMA_17_RESET 0000000000
#define MS_SEMA_17_MASK_BITS 0:0
#define MS_SEMA_17_MASK_SET 0x00000001
#define MS_SEMA_17_MASK_CLR 0xfffffffe
#define MS_SEMA_17_MASK_MSB 0
#define MS_SEMA_17_MASK_LSB 0
#define MS_SEMA_18 HW_REGISTER_RW( 0x7e000048 )
#define MS_SEMA_18_MASK 0x00000001
#define MS_SEMA_18_WIDTH 1
#define MS_SEMA_18_RESET 0000000000
#define MS_SEMA_18_MASK_BITS 0:0
#define MS_SEMA_18_MASK_SET 0x00000001
#define MS_SEMA_18_MASK_CLR 0xfffffffe
#define MS_SEMA_18_MASK_MSB 0
#define MS_SEMA_18_MASK_LSB 0
#define MS_SEMA_19 HW_REGISTER_RW( 0x7e00004c )
#define MS_SEMA_19_MASK 0x00000001
#define MS_SEMA_19_WIDTH 1
#define MS_SEMA_19_RESET 0000000000
#define MS_SEMA_19_MASK_BITS 0:0
#define MS_SEMA_19_MASK_SET 0x00000001
#define MS_SEMA_19_MASK_CLR 0xfffffffe
#define MS_SEMA_19_MASK_MSB 0
#define MS_SEMA_19_MASK_LSB 0
#define MS_SEMA_20 HW_REGISTER_RW( 0x7e000050 )
#define MS_SEMA_20_MASK 0x00000001
#define MS_SEMA_20_WIDTH 1
#define MS_SEMA_20_RESET 0000000000
#define MS_SEMA_20_MASK_BITS 0:0
#define MS_SEMA_20_MASK_SET 0x00000001
#define MS_SEMA_20_MASK_CLR 0xfffffffe
#define MS_SEMA_20_MASK_MSB 0
#define MS_SEMA_20_MASK_LSB 0
#define MS_SEMA_21 HW_REGISTER_RW( 0x7e000054 )
#define MS_SEMA_21_MASK 0x00000001
#define MS_SEMA_21_WIDTH 1
#define MS_SEMA_21_RESET 0000000000
#define MS_SEMA_21_MASK_BITS 0:0
#define MS_SEMA_21_MASK_SET 0x00000001
#define MS_SEMA_21_MASK_CLR 0xfffffffe
#define MS_SEMA_21_MASK_MSB 0
#define MS_SEMA_21_MASK_LSB 0
#define MS_SEMA_22 HW_REGISTER_RW( 0x7e000058 )
#define MS_SEMA_22_MASK 0x00000001
#define MS_SEMA_22_WIDTH 1
#define MS_SEMA_22_RESET 0000000000
#define MS_SEMA_22_MASK_BITS 0:0
#define MS_SEMA_22_MASK_SET 0x00000001
#define MS_SEMA_22_MASK_CLR 0xfffffffe
#define MS_SEMA_22_MASK_MSB 0
#define MS_SEMA_22_MASK_LSB 0
#define MS_SEMA_23 HW_REGISTER_RW( 0x7e00005c )
#define MS_SEMA_23_MASK 0x00000001
#define MS_SEMA_23_WIDTH 1
#define MS_SEMA_23_RESET 0000000000
#define MS_SEMA_23_MASK_BITS 0:0
#define MS_SEMA_23_MASK_SET 0x00000001
#define MS_SEMA_23_MASK_CLR 0xfffffffe
#define MS_SEMA_23_MASK_MSB 0
#define MS_SEMA_23_MASK_LSB 0
#define MS_SEMA_24 HW_REGISTER_RW( 0x7e000060 )
#define MS_SEMA_24_MASK 0x00000001
#define MS_SEMA_24_WIDTH 1
#define MS_SEMA_24_RESET 0000000000
#define MS_SEMA_24_MASK_BITS 0:0
#define MS_SEMA_24_MASK_SET 0x00000001
#define MS_SEMA_24_MASK_CLR 0xfffffffe
#define MS_SEMA_24_MASK_MSB 0
#define MS_SEMA_24_MASK_LSB 0
#define MS_SEMA_25 HW_REGISTER_RW( 0x7e000064 )
#define MS_SEMA_25_MASK 0x00000001
#define MS_SEMA_25_WIDTH 1
#define MS_SEMA_25_RESET 0000000000
#define MS_SEMA_25_MASK_BITS 0:0
#define MS_SEMA_25_MASK_SET 0x00000001
#define MS_SEMA_25_MASK_CLR 0xfffffffe
#define MS_SEMA_25_MASK_MSB 0
#define MS_SEMA_25_MASK_LSB 0
#define MS_SEMA_26 HW_REGISTER_RW( 0x7e000068 )
#define MS_SEMA_26_MASK 0x00000001
#define MS_SEMA_26_WIDTH 1
#define MS_SEMA_26_RESET 0000000000
#define MS_SEMA_26_MASK_BITS 0:0
#define MS_SEMA_26_MASK_SET 0x00000001
#define MS_SEMA_26_MASK_CLR 0xfffffffe
#define MS_SEMA_26_MASK_MSB 0
#define MS_SEMA_26_MASK_LSB 0
#define MS_SEMA_27 HW_REGISTER_RW( 0x7e00006c )
#define MS_SEMA_27_MASK 0x00000001
#define MS_SEMA_27_WIDTH 1
#define MS_SEMA_27_RESET 0000000000
#define MS_SEMA_27_MASK_BITS 0:0
#define MS_SEMA_27_MASK_SET 0x00000001
#define MS_SEMA_27_MASK_CLR 0xfffffffe
#define MS_SEMA_27_MASK_MSB 0
#define MS_SEMA_27_MASK_LSB 0
#define MS_SEMA_28 HW_REGISTER_RW( 0x7e000070 )
#define MS_SEMA_28_MASK 0x00000001
#define MS_SEMA_28_WIDTH 1
#define MS_SEMA_28_RESET 0000000000
#define MS_SEMA_28_MASK_BITS 0:0
#define MS_SEMA_28_MASK_SET 0x00000001
#define MS_SEMA_28_MASK_CLR 0xfffffffe
#define MS_SEMA_28_MASK_MSB 0
#define MS_SEMA_28_MASK_LSB 0
#define MS_SEMA_29 HW_REGISTER_RW( 0x7e000074 )
#define MS_SEMA_29_MASK 0x00000001
#define MS_SEMA_29_WIDTH 1
#define MS_SEMA_29_RESET 0000000000
#define MS_SEMA_29_MASK_BITS 0:0
#define MS_SEMA_29_MASK_SET 0x00000001
#define MS_SEMA_29_MASK_CLR 0xfffffffe
#define MS_SEMA_29_MASK_MSB 0
#define MS_SEMA_29_MASK_LSB 0
#define MS_SEMA_30 HW_REGISTER_RW( 0x7e000078 )
#define MS_SEMA_30_MASK 0x00000001
#define MS_SEMA_30_WIDTH 1
#define MS_SEMA_30_RESET 0000000000
#define MS_SEMA_30_MASK_BITS 0:0
#define MS_SEMA_30_MASK_SET 0x00000001
#define MS_SEMA_30_MASK_CLR 0xfffffffe
#define MS_SEMA_30_MASK_MSB 0
#define MS_SEMA_30_MASK_LSB 0
#define MS_SEMA_31 HW_REGISTER_RW( 0x7e00007c )
#define MS_SEMA_31_MASK 0x00000001
#define MS_SEMA_31_WIDTH 1
#define MS_SEMA_31_RESET 0000000000
#define MS_SEMA_31_MASK_BITS 0:0
#define MS_SEMA_31_MASK_SET 0x00000001
#define MS_SEMA_31_MASK_CLR 0xfffffffe
#define MS_SEMA_31_MASK_MSB 0
#define MS_SEMA_31_MASK_LSB 0
#define MS_STATUS HW_REGISTER_RO( 0x7e000080 )
#define MS_STATUS_MASK 0xffffffff
#define MS_STATUS_WIDTH 32
#define MS_STATUS_RESET 0000000000
#define MS_STATUS_STATUS_BITS 31:0
#define MS_STATUS_STATUS_SET 0xffffffff
#define MS_STATUS_STATUS_CLR 0x00000000
#define MS_STATUS_STATUS_MSB 31
#define MS_STATUS_STATUS_LSB 0
#define MS_IREQ_0 HW_REGISTER_RW( 0x7e000084 )
#define MS_IREQ_0_MASK 0xffffffff
#define MS_IREQ_0_WIDTH 32
#define MS_IREQ_0_RESET 0000000000
#define MS_IREQ_0_IREQ_0_BITS 31:0
#define MS_IREQ_0_IREQ_0_SET 0xffffffff
#define MS_IREQ_0_IREQ_0_CLR 0x00000000
#define MS_IREQ_0_IREQ_0_MSB 31
#define MS_IREQ_0_IREQ_0_LSB 0
#define MS_IREQ_1 HW_REGISTER_RW( 0x7e000088 )
#define MS_IREQ_1_MASK 0xffffffff
#define MS_IREQ_1_WIDTH 32
#define MS_IREQ_1_RESET 0000000000
#define MS_IREQ_1_IREQ_1_BITS 31:0
#define MS_IREQ_1_IREQ_1_SET 0xffffffff
#define MS_IREQ_1_IREQ_1_CLR 0x00000000
#define MS_IREQ_1_IREQ_1_MSB 31
#define MS_IREQ_1_IREQ_1_LSB 0
#define MS_ICSET_0 HW_REGISTER_RW( 0x7e000090 )
#define MS_ICSET_0_MASK 0x00000001
#define MS_ICSET_0_WIDTH 1
#define MS_ICSET_0_RESET 0000000000
#define MS_ICSET_0_ICSET_0_BITS 0:0
#define MS_ICSET_0_ICSET_0_SET 0x00000001
#define MS_ICSET_0_ICSET_0_CLR 0xfffffffe
#define MS_ICSET_0_ICSET_0_MSB 0
#define MS_ICSET_0_ICSET_0_LSB 0
#define MS_ICSET_1 HW_REGISTER_RW( 0x7e000094 )
#define MS_ICSET_1_MASK 0x00000001
#define MS_ICSET_1_WIDTH 1
#define MS_ICSET_1_RESET 0000000000
#define MS_ICSET_1_ICSET_1_BITS 0:0
#define MS_ICSET_1_ICSET_1_SET 0x00000001
#define MS_ICSET_1_ICSET_1_CLR 0xfffffffe
#define MS_ICSET_1_ICSET_1_MSB 0
#define MS_ICSET_1_ICSET_1_LSB 0
#define MS_ICCLR_0 HW_REGISTER_RW( 0x7e000098 )
#define MS_ICCLR_0_MASK 0x00000001
#define MS_ICCLR_0_WIDTH 1
#define MS_ICCLR_0_RESET 0000000000
#define MS_ICCLR_0_ICCLR_0_BITS 0:0
#define MS_ICCLR_0_ICCLR_0_SET 0x00000001
#define MS_ICCLR_0_ICCLR_0_CLR 0xfffffffe
#define MS_ICCLR_0_ICCLR_0_MSB 0
#define MS_ICCLR_0_ICCLR_0_LSB 0
#define MS_ICCLR_1 HW_REGISTER_RW( 0x7e00009c )
#define MS_ICCLR_1_MASK 0x00000001
#define MS_ICCLR_1_WIDTH 1
#define MS_ICCLR_1_RESET 0000000000
#define MS_ICCLR_1_ICCLR_1_BITS 0:0
#define MS_ICCLR_1_ICCLR_1_SET 0x00000001
#define MS_ICCLR_1_ICCLR_1_CLR 0xfffffffe
#define MS_ICCLR_1_ICCLR_1_MSB 0
#define MS_ICCLR_1_ICCLR_1_LSB 0
#define MS_MBOX_0 HW_REGISTER_RW( 0x7e0000a0 )
#define MS_MBOX_0_MASK 0xffffffff
#define MS_MBOX_0_WIDTH 32
#define MS_MBOX_0_RESET 0000000000
#define MS_MBOX_0_MBOX_BITS 31:0
#define MS_MBOX_0_MBOX_SET 0xffffffff
#define MS_MBOX_0_MBOX_CLR 0x00000000
#define MS_MBOX_0_MBOX_MSB 31
#define MS_MBOX_0_MBOX_LSB 0
#define MS_MBOX_1 HW_REGISTER_RW( 0x7e0000a4 )
#define MS_MBOX_1_MASK 0xffffffff
#define MS_MBOX_1_WIDTH 32
#define MS_MBOX_1_RESET 0000000000
#define MS_MBOX_1_MBOX_BITS 31:0
#define MS_MBOX_1_MBOX_SET 0xffffffff
#define MS_MBOX_1_MBOX_CLR 0x00000000
#define MS_MBOX_1_MBOX_MSB 31
#define MS_MBOX_1_MBOX_LSB 0
#define MS_MBOX_2 HW_REGISTER_RW( 0x7e0000a8 )
#define MS_MBOX_2_MASK 0xffffffff
#define MS_MBOX_2_WIDTH 32
#define MS_MBOX_2_RESET 0000000000
#define MS_MBOX_2_MBOX_BITS 31:0
#define MS_MBOX_2_MBOX_SET 0xffffffff
#define MS_MBOX_2_MBOX_CLR 0x00000000
#define MS_MBOX_2_MBOX_MSB 31
#define MS_MBOX_2_MBOX_LSB 0
#define MS_MBOX_3 HW_REGISTER_RW( 0x7e0000ac )
#define MS_MBOX_3_MASK 0xffffffff
#define MS_MBOX_3_WIDTH 32
#define MS_MBOX_3_RESET 0000000000
#define MS_MBOX_3_MBOX_BITS 31:0
#define MS_MBOX_3_MBOX_SET 0xffffffff
#define MS_MBOX_3_MBOX_CLR 0x00000000
#define MS_MBOX_3_MBOX_MSB 31
#define MS_MBOX_3_MBOX_LSB 0
#define MS_MBOX_4 HW_REGISTER_RW( 0x7e0000b0 )
#define MS_MBOX_4_MASK 0xffffffff
#define MS_MBOX_4_WIDTH 32
#define MS_MBOX_4_RESET 0000000000
#define MS_MBOX_4_MBOX_BITS 31:0
#define MS_MBOX_4_MBOX_SET 0xffffffff
#define MS_MBOX_4_MBOX_CLR 0x00000000
#define MS_MBOX_4_MBOX_MSB 31
#define MS_MBOX_4_MBOX_LSB 0
#define MS_MBOX_5 HW_REGISTER_RW( 0x7e0000b4 )
#define MS_MBOX_5_MASK 0xffffffff
#define MS_MBOX_5_WIDTH 32
#define MS_MBOX_5_RESET 0000000000
#define MS_MBOX_5_MBOX_BITS 31:0
#define MS_MBOX_5_MBOX_SET 0xffffffff
#define MS_MBOX_5_MBOX_CLR 0x00000000
#define MS_MBOX_5_MBOX_MSB 31
#define MS_MBOX_5_MBOX_LSB 0
#define MS_MBOX_6 HW_REGISTER_RW( 0x7e0000b8 )
#define MS_MBOX_6_MASK 0xffffffff
#define MS_MBOX_6_WIDTH 32
#define MS_MBOX_6_RESET 0000000000
#define MS_MBOX_6_MBOX_BITS 31:0
#define MS_MBOX_6_MBOX_SET 0xffffffff
#define MS_MBOX_6_MBOX_CLR 0x00000000
#define MS_MBOX_6_MBOX_MSB 31
#define MS_MBOX_6_MBOX_LSB 0
#define MS_MBOX_7 HW_REGISTER_RW( 0x7e0000bc )
#define MS_MBOX_7_MASK 0xffffffff
#define MS_MBOX_7_WIDTH 32
#define MS_MBOX_7_RESET 0000000000
#define MS_MBOX_7_MBOX_BITS 31:0
#define MS_MBOX_7_MBOX_SET 0xffffffff
#define MS_MBOX_7_MBOX_CLR 0x00000000
#define MS_MBOX_7_MBOX_MSB 31
#define MS_MBOX_7_MBOX_LSB 0
#define MS_VPUSEMA_0 HW_REGISTER_RW( 0x7e0000c0 )
#define MS_VPUSEMA_0_VPUSEMA_0_BITS 0:0
#define MS_VPUSEMA_0_VPUSEMA_0_SET 0x00000001
#define MS_VPUSEMA_0_VPUSEMA_0_CLR 0xfffffffe
#define MS_VPUSEMA_0_VPUSEMA_0_MSB 0
#define MS_VPUSEMA_0_VPUSEMA_0_LSB 0
#define MS_VPUSEMA_1 HW_REGISTER_RW( 0x7e0000c4 )
#define MS_VPUSEMA_1_VPUSEMA_1_BITS 0:0
#define MS_VPUSEMA_1_VPUSEMA_1_SET 0x00000001
#define MS_VPUSEMA_1_VPUSEMA_1_CLR 0xfffffffe
#define MS_VPUSEMA_1_VPUSEMA_1_MSB 0
#define MS_VPUSEMA_1_VPUSEMA_1_LSB 0
#define MS_VPU_STAT HW_REGISTER_RO( 0x7e0000c8 )
#define MS_VPU_STAT_MASK 0x00ff00ff
#define MS_VPU_STAT_WIDTH 24
#define MS_VPU_STAT_VPU_STAT_BITS 0:0
#define MS_VPU_STAT_VPU_STAT_SET 0x00000001
#define MS_VPU_STAT_VPU_STAT_CLR 0xfffffffe
#define MS_VPU_STAT_VPU_STAT_MSB 0
#define MS_VPU_STAT_VPU_STAT_LSB 0