// This file was generated by the create_regs script #define PIXELVALVE1_BASE 0x7e207000 #define PIXELVALVE1_APB_ID 0x70697876 #define PIXELVALVE1_C HW_REGISTER_RW( 0x7e207000 ) #define PIXELVALVE1_C_MASK 0x00ffffff #define PIXELVALVE1_C_WIDTH 24 #define PIXELVALVE1_VC HW_REGISTER_RW( 0x7e207004 ) #define PIXELVALVE1_VC_MASK 0x007fffff #define PIXELVALVE1_VC_WIDTH 23 #define PIXELVALVE1_VSYNCD_EVEN HW_REGISTER_RW( 0x7e207008 ) #define PIXELVALVE1_VSYNCD_EVEN_MASK 0x0001ffff #define PIXELVALVE1_VSYNCD_EVEN_WIDTH 17 #define PIXELVALVE1_HORZA HW_REGISTER_RW( 0x7e20700c ) #define PIXELVALVE1_HORZA_MASK 0xffffffff #define PIXELVALVE1_HORZA_WIDTH 32 #define PIXELVALVE1_HORZB HW_REGISTER_RW( 0x7e207010 ) #define PIXELVALVE1_HORZB_MASK 0xffffffff #define PIXELVALVE1_HORZB_WIDTH 32 #define PIXELVALVE1_VERTA HW_REGISTER_RW( 0x7e207014 ) #define PIXELVALVE1_VERTA_MASK 0xffffffff #define PIXELVALVE1_VERTA_WIDTH 32 #define PIXELVALVE1_VERTB HW_REGISTER_RW( 0x7e207018 ) #define PIXELVALVE1_VERTB_MASK 0xffffffff #define PIXELVALVE1_VERTB_WIDTH 32 #define PIXELVALVE1_VERTA_EVEN HW_REGISTER_RW( 0x7e20701c ) #define PIXELVALVE1_VERTA_EVEN_MASK 0xffffffff #define PIXELVALVE1_VERTA_EVEN_WIDTH 32 #define PIXELVALVE1_VERTB_EVEN HW_REGISTER_RW( 0x7e207020 ) #define PIXELVALVE1_VERTB_EVEN_MASK 0xffffffff #define PIXELVALVE1_VERTB_EVEN_WIDTH 32 #define PIXELVALVE1_INTEN HW_REGISTER_RW( 0x7e207024 ) #define PIXELVALVE1_INTEN_MASK 0x000003ff #define PIXELVALVE1_INTEN_WIDTH 10 #define PIXELVALVE1_INTSTAT HW_REGISTER_RW( 0x7e207028 ) #define PIXELVALVE1_INTSTAT_MASK 0x000003ff #define PIXELVALVE1_INTSTAT_WIDTH 10 #define PIXELVALVE1_STAT HW_REGISTER_RW( 0x7e20702c ) #define PIXELVALVE1_STAT_MASK 0x000003ff #define PIXELVALVE1_STAT_WIDTH 10 #define PIXELVALVE1_DSI_HACT_ACT HW_REGISTER_RW( 0x7e207030 ) #define PIXELVALVE1_DSI_HACT_ACT_MASK 0x0000ffff #define PIXELVALVE1_DSI_HACT_ACT_WIDTH 16