// This file was generated by the create_regs script #define SD_BASE 0x7ee00000 #define SD_APB_ID 0x5344434f #define SD_CS HW_REGISTER_RW( 0x7ee00000 ) #define SD_CS_MASK 0x01ffffff #define SD_CS_WIDTH 25 #define SD_CS_STALLING_BITS 24:24 #define SD_CS_STALLING_SET 0x01000000 #define SD_CS_STALLING_CLR 0xfeffffff #define SD_CS_STALLING_MSB 24 #define SD_CS_STALLING_LSB 24 #define SD_CS_STALLING_RESET 0x0 #define SD_CS_EXCEPTION_BITS 23:23 #define SD_CS_EXCEPTION_SET 0x00800000 #define SD_CS_EXCEPTION_CLR 0xff7fffff #define SD_CS_EXCEPTION_MSB 23 #define SD_CS_EXCEPTION_LSB 23 #define SD_CS_EXCEPTION_RESET 0x0 #define SD_CS_ASHDN_T_BITS 22:19 #define SD_CS_ASHDN_T_SET 0x00780000 #define SD_CS_ASHDN_T_CLR 0xff87ffff #define SD_CS_ASHDN_T_MSB 22 #define SD_CS_ASHDN_T_LSB 19 #define SD_CS_ASHDN_T_RESET 0xf #define SD_CS_DEL_KEEP_BITS 18:18 #define SD_CS_DEL_KEEP_SET 0x00040000 #define SD_CS_DEL_KEEP_CLR 0xfffbffff #define SD_CS_DEL_KEEP_MSB 18 #define SD_CS_DEL_KEEP_LSB 18 #define SD_CS_DEL_KEEP_RESET 0x0 #define SD_CS_ASHDNE_BITS 17:17 #define SD_CS_ASHDNE_SET 0x00020000 #define SD_CS_ASHDNE_CLR 0xfffdffff #define SD_CS_ASHDNE_MSB 17 #define SD_CS_ASHDNE_LSB 17 #define SD_CS_ASHDNE_RESET 0x0 #define SD_CS_RDH_IDLE_BITS 16:16 #define SD_CS_RDH_IDLE_SET 0x00010000 #define SD_CS_RDH_IDLE_CLR 0xfffeffff #define SD_CS_RDH_IDLE_MSB 16 #define SD_CS_RDH_IDLE_LSB 16 #define SD_CS_RDH_IDLE_RESET 0x0 #define SD_CS_SDUP_BITS 15:15 #define SD_CS_SDUP_SET 0x00008000 #define SD_CS_SDUP_CLR 0xffff7fff #define SD_CS_SDUP_MSB 15 #define SD_CS_SDUP_LSB 15 #define SD_CS_SDUP_RESET 0x0 #define SD_CS_CLKOFF_BITS 14:14 #define SD_CS_CLKOFF_SET 0x00004000 #define SD_CS_CLKOFF_CLR 0xffffbfff #define SD_CS_CLKOFF_MSB 14 #define SD_CS_CLKOFF_LSB 14 #define SD_CS_CLKOFF_RESET 0x1 #define SD_CS_DLLCAL_BITS 11:10 #define SD_CS_DLLCAL_SET 0x00000c00 #define SD_CS_DLLCAL_CLR 0xfffff3ff #define SD_CS_DLLCAL_MSB 11 #define SD_CS_DLLCAL_LSB 10 #define SD_CS_DLLCAL_RESET 0x0 #define SD_CS_IDLE_BITS 9:9 #define SD_CS_IDLE_SET 0x00000200 #define SD_CS_IDLE_CLR 0xfffffdff #define SD_CS_IDLE_MSB 9 #define SD_CS_IDLE_LSB 9 #define SD_CS_IDLE_RESET 0x0 #define SD_CS_SREF2RUN_BITS 8:8 #define SD_CS_SREF2RUN_SET 0x00000100 #define SD_CS_SREF2RUN_CLR 0xfffffeff #define SD_CS_SREF2RUN_MSB 8 #define SD_CS_SREF2RUN_LSB 8 #define SD_CS_SREF2RUN_RESET 0x0 #define SD_CS_STOP_BITS 7:7 #define SD_CS_STOP_SET 0x00000080 #define SD_CS_STOP_CLR 0xffffff7f #define SD_CS_STOP_MSB 7 #define SD_CS_STOP_LSB 7 #define SD_CS_STOP_RESET 0x0 #define SD_CS_STATEN_BITS 6:6 #define SD_CS_STATEN_SET 0x00000040 #define SD_CS_STATEN_CLR 0xffffffbf #define SD_CS_STATEN_MSB 6 #define SD_CS_STATEN_LSB 6 #define SD_CS_STATEN_RESET 0x0 #define SD_CS_SDTST_BITS 5:5 #define SD_CS_SDTST_SET 0x00000020 #define SD_CS_SDTST_CLR 0xffffffdf #define SD_CS_SDTST_MSB 5 #define SD_CS_SDTST_LSB 5 #define SD_CS_SDTST_RESET 0x0 #define SD_CS_PUSKIP_BITS 4:4 #define SD_CS_PUSKIP_SET 0x00000010 #define SD_CS_PUSKIP_CLR 0xffffffef #define SD_CS_PUSKIP_MSB 4 #define SD_CS_PUSKIP_LSB 4 #define SD_CS_PUSKIP_RESET 0x0 #define SD_CS_STBY_BITS 3:3 #define SD_CS_STBY_SET 0x00000008 #define SD_CS_STBY_CLR 0xfffffff7 #define SD_CS_STBY_MSB 3 #define SD_CS_STBY_LSB 3 #define SD_CS_STBY_RESET 0x0 #define SD_CS_DPD_BITS 2:2 #define SD_CS_DPD_SET 0x00000004 #define SD_CS_DPD_CLR 0xfffffffb #define SD_CS_DPD_MSB 2 #define SD_CS_DPD_LSB 2 #define SD_CS_DPD_RESET 0x0 #define SD_CS_EN_BITS 1:1 #define SD_CS_EN_SET 0x00000002 #define SD_CS_EN_CLR 0xfffffffd #define SD_CS_EN_MSB 1 #define SD_CS_EN_LSB 1 #define SD_CS_EN_RESET 0x0 #define SD_CS_RESTRT_BITS 0:0 #define SD_CS_RESTRT_SET 0x00000001 #define SD_CS_RESTRT_CLR 0xfffffffe #define SD_CS_RESTRT_MSB 0 #define SD_CS_RESTRT_LSB 0 #define SD_CS_RESTRT_RESET 0x0 #define SD_SA HW_REGISTER_RW( 0x7ee00004 ) #define SD_SA_MASK 0xffffffff #define SD_SA_WIDTH 32 #define SD_SA_RFSH_T_BITS 31:16 #define SD_SA_RFSH_T_SET 0xffff0000 #define SD_SA_RFSH_T_CLR 0x0000ffff #define SD_SA_RFSH_T_MSB 31 #define SD_SA_RFSH_T_LSB 16 #define SD_SA_RFSH_T_RESET 0x30c #define SD_SA_PGEHLD_IDL_BITS 15:15 #define SD_SA_PGEHLD_IDL_SET 0x00008000 #define SD_SA_PGEHLD_IDL_CLR 0xffff7fff #define SD_SA_PGEHLD_IDL_MSB 15 #define SD_SA_PGEHLD_IDL_LSB 15 #define SD_SA_PGEHLD_IDL_RESET 0x0 #define SD_SA_PGEHLDE_BITS 8:8 #define SD_SA_PGEHLDE_SET 0x00000100 #define SD_SA_PGEHLDE_CLR 0xfffffeff #define SD_SA_PGEHLDE_MSB 8 #define SD_SA_PGEHLDE_LSB 8 #define SD_SA_PGEHLDE_RESET 0x0 #define SD_SA_CLKSTOP_BITS 7:7 #define SD_SA_CLKSTOP_SET 0x00000080 #define SD_SA_CLKSTOP_CLR 0xffffff7f #define SD_SA_CLKSTOP_MSB 7 #define SD_SA_CLKSTOP_LSB 7 #define SD_SA_CLKSTOP_RESET 0x1 #define SD_SA_POWSAVE_BITS 0:0 #define SD_SA_POWSAVE_SET 0x00000001 #define SD_SA_POWSAVE_CLR 0xfffffffe #define SD_SA_POWSAVE_MSB 0 #define SD_SA_POWSAVE_LSB 0 #define SD_SA_POWSAVE_RESET 0x0 #define SD_SB HW_REGISTER_RW( 0x7ee00008 ) #define SD_SB_MASK 0xfff001ff #define SD_SB_WIDTH 32 #define SD_SB_STBY_T_BITS 31:20 #define SD_SB_STBY_T_SET 0xfff00000 #define SD_SB_STBY_T_CLR 0x000fffff #define SD_SB_STBY_T_MSB 31 #define SD_SB_STBY_T_LSB 20 #define SD_SB_STBY_T_RESET 0x0 #define SD_SB_INHIBIT_LA_BITS 8:8 #define SD_SB_INHIBIT_LA_SET 0x00000100 #define SD_SB_INHIBIT_LA_CLR 0xfffffeff #define SD_SB_INHIBIT_LA_MSB 8 #define SD_SB_INHIBIT_LA_LSB 8 #define SD_SB_INHIBIT_LA_RESET 0x0 #define SD_SB_REORDER_BITS 7:7 #define SD_SB_REORDER_SET 0x00000080 #define SD_SB_REORDER_CLR 0xffffff7f #define SD_SB_REORDER_MSB 7 #define SD_SB_REORDER_LSB 7 #define SD_SB_REORDER_RESET 0x0 #define SD_SB_BANKLOW_BITS 6:5 #define SD_SB_BANKLOW_SET 0x00000060 #define SD_SB_BANKLOW_CLR 0xffffff9f #define SD_SB_BANKLOW_MSB 6 #define SD_SB_BANKLOW_LSB 5 #define SD_SB_BANKLOW_RESET 0x0 #define SD_SB_EIGHTBANK_BITS 4:4 #define SD_SB_EIGHTBANK_SET 0x00000010 #define SD_SB_EIGHTBANK_CLR 0xffffffef #define SD_SB_EIGHTBANK_MSB 4 #define SD_SB_EIGHTBANK_LSB 4 #define SD_SB_EIGHTBANK_RESET 0x0 #define SD_SB_ROWBITS_BITS 3:2 #define SD_SB_ROWBITS_SET 0x0000000c #define SD_SB_ROWBITS_CLR 0xfffffff3 #define SD_SB_ROWBITS_MSB 3 #define SD_SB_ROWBITS_LSB 2 #define SD_SB_ROWBITS_RESET 0x1 #define SD_SB_COLBITS_BITS 1:0 #define SD_SB_COLBITS_SET 0x00000003 #define SD_SB_COLBITS_CLR 0xfffffffc #define SD_SB_COLBITS_MSB 1 #define SD_SB_COLBITS_LSB 0 #define SD_SB_COLBITS_RESET 0x1 #define SD_SC HW_REGISTER_RW( 0x7ee0000c ) #define SD_SC_MASK 0x7ff00f77 #define SD_SC_WIDTH 31 #define SD_SC_T_RFC_BITS 30:24 #define SD_SC_T_RFC_SET 0x7f000000 #define SD_SC_T_RFC_CLR 0x80ffffff #define SD_SC_T_RFC_MSB 30 #define SD_SC_T_RFC_LSB 24 #define SD_SC_T_RFC_RESET 0x1e #define SD_SC_T_RRD_BITS 23:20 #define SD_SC_T_RRD_SET 0x00f00000 #define SD_SC_T_RRD_CLR 0xff0fffff #define SD_SC_T_RRD_MSB 23 #define SD_SC_T_RRD_LSB 20 #define SD_SC_T_RRD_RESET 0x4 #define SD_SC_T_WR_BITS 11:8 #define SD_SC_T_WR_SET 0x00000f00 #define SD_SC_T_WR_CLR 0xfffff0ff #define SD_SC_T_WR_MSB 11 #define SD_SC_T_WR_LSB 8 #define SD_SC_T_WR_RESET 0x6 #define SD_SC_T_WTR_BITS 6:4 #define SD_SC_T_WTR_SET 0x00000070 #define SD_SC_T_WTR_CLR 0xffffff8f #define SD_SC_T_WTR_MSB 6 #define SD_SC_T_WTR_LSB 4 #define SD_SC_T_WTR_RESET 0x3 #define SD_SC_WL_BITS 2:0 #define SD_SC_WL_SET 0x00000007 #define SD_SC_WL_CLR 0xfffffff8 #define SD_SC_WL_MSB 2 #define SD_SC_WL_LSB 0 #define SD_SC_WL_RESET 0x2 #define SD_SD HW_REGISTER_RW( 0x7ee00094 ) #define SD_SD_MASK 0xf1f71fff #define SD_SD_WIDTH 32 #define SD_SD_T_RPab_BITS 31:28 #define SD_SD_T_RPab_SET 0xf0000000 #define SD_SD_T_RPab_CLR 0x0fffffff #define SD_SD_T_RPab_MSB 31 #define SD_SD_T_RPab_LSB 28 #define SD_SD_T_RPab_RESET 0xa #define SD_SD_T_RC_BITS 24:20 #define SD_SD_T_RC_SET 0x01f00000 #define SD_SD_T_RC_CLR 0xfe0fffff #define SD_SD_T_RC_MSB 24 #define SD_SD_T_RC_LSB 20 #define SD_SD_T_RC_RESET 0x14 #define SD_SD_T_XP_BITS 18:16 #define SD_SD_T_XP_SET 0x00070000 #define SD_SD_T_XP_CLR 0xfff8ffff #define SD_SD_T_XP_MSB 18 #define SD_SD_T_XP_LSB 16 #define SD_SD_T_XP_RESET 0x2 #define SD_SD_T_RAS_BITS 12:8 #define SD_SD_T_RAS_SET 0x00001f00 #define SD_SD_T_RAS_CLR 0xffffe0ff #define SD_SD_T_RAS_MSB 12 #define SD_SD_T_RAS_LSB 8 #define SD_SD_T_RAS_RESET 0xe #define SD_SD_T_RPpb_BITS 7:4 #define SD_SD_T_RPpb_SET 0x000000f0 #define SD_SD_T_RPpb_CLR 0xffffff0f #define SD_SD_T_RPpb_MSB 7 #define SD_SD_T_RPpb_LSB 4 #define SD_SD_T_RPpb_RESET 0x8 #define SD_SD_T_RCD_BITS 3:0 #define SD_SD_T_RCD_SET 0x0000000f #define SD_SD_T_RCD_CLR 0xfffffff0 #define SD_SD_T_RCD_MSB 3 #define SD_SD_T_RCD_LSB 0 #define SD_SD_T_RCD_RESET 0x8 #define SD_SE HW_REGISTER_RW( 0x7ee00098 ) #define SD_SE_MASK 0x13f3f73f #define SD_SE_WIDTH 29 #define SD_SE_RL_EN_BITS 28:28 #define SD_SE_RL_EN_SET 0x10000000 #define SD_SE_RL_EN_CLR 0xefffffff #define SD_SE_RL_EN_MSB 28 #define SD_SE_RL_EN_LSB 28 #define SD_SE_RL_EN_RESET 0x0 #define SD_SE_RL_BITS 25:20 #define SD_SE_RL_SET 0x03f00000 #define SD_SE_RL_CLR 0xfc0fffff #define SD_SE_RL_MSB 25 #define SD_SE_RL_LSB 20 #define SD_SE_RL_RESET 0x8 #define SD_SE_T_FAW_BITS 17:12 #define SD_SE_T_FAW_SET 0x0003f000 #define SD_SE_T_FAW_CLR 0xfffc0fff #define SD_SE_T_FAW_MSB 17 #define SD_SE_T_FAW_LSB 12 #define SD_SE_T_FAW_RESET 0x19 #define SD_SE_T_RTP_BITS 10:8 #define SD_SE_T_RTP_SET 0x00000700 #define SD_SE_T_RTP_CLR 0xfffff8ff #define SD_SE_T_RTP_MSB 10 #define SD_SE_T_RTP_LSB 8 #define SD_SE_T_RTP_RESET 0x3 #define SD_SE_T_XSR_BITS 5:0 #define SD_SE_T_XSR_SET 0x0000003f #define SD_SE_T_XSR_CLR 0xffffffc0 #define SD_SE_T_XSR_MSB 5 #define SD_SE_T_XSR_LSB 0 #define SD_SE_T_XSR_RESET 0x28 #define SD_SF HW_REGISTER_RW( 0x7ee000b4 ) #define SD_SF_MASK 0x3fffffff #define SD_SF_WIDTH 30 #define SD_SF_PHYHOLD_BITS 29:29 #define SD_SF_PHYHOLD_SET 0x20000000 #define SD_SF_PHYHOLD_CLR 0xdfffffff #define SD_SF_PHYHOLD_MSB 29 #define SD_SF_PHYHOLD_LSB 29 #define SD_SF_PHYHOLD_RESET 0x0 #define SD_SF_PGEHLD_T_BITS 28:19 #define SD_SF_PGEHLD_T_SET 0x1ff80000 #define SD_SF_PGEHLD_T_CLR 0xe007ffff #define SD_SF_PGEHLD_T_MSB 28 #define SD_SF_PGEHLD_T_LSB 19 #define SD_SF_PGEHLD_T_RESET 0x100 #define SD_SF_POWSAV_T_BITS 18:9 #define SD_SF_POWSAV_T_SET 0x0007fe00 #define SD_SF_POWSAV_T_CLR 0xfff801ff #define SD_SF_POWSAV_T_MSB 18 #define SD_SF_POWSAV_T_LSB 9 #define SD_SF_POWSAV_T_RESET 0x040 #define SD_SF_MDLL_CAL_BITS 8:0 #define SD_SF_MDLL_CAL_SET 0x000001ff #define SD_SF_MDLL_CAL_CLR 0xfffffe00 #define SD_SF_MDLL_CAL_MSB 8 #define SD_SF_MDLL_CAL_LSB 0 #define SD_SF_MDLL_CAL_RESET 0x12c #define SD_MR HW_REGISTER_RW( 0x7ee00090 ) #define SD_MR_MASK 0xf0ffffff #define SD_MR_WIDTH 32 #define SD_MR_DONE_BITS 31:31 #define SD_MR_DONE_SET 0x80000000 #define SD_MR_DONE_CLR 0x7fffffff #define SD_MR_DONE_MSB 31 #define SD_MR_DONE_LSB 31 #define SD_MR_DONE_RESET 0x1 #define SD_MR_TIMEOUT_BITS 30:30 #define SD_MR_TIMEOUT_SET 0x40000000 #define SD_MR_TIMEOUT_CLR 0xbfffffff #define SD_MR_TIMEOUT_MSB 30 #define SD_MR_TIMEOUT_LSB 30 #define SD_MR_TIMEOUT_RESET 0x0 #define SD_MR_HI_Z_BITS 29:29 #define SD_MR_HI_Z_SET 0x20000000 #define SD_MR_HI_Z_CLR 0xdfffffff #define SD_MR_HI_Z_MSB 29 #define SD_MR_HI_Z_LSB 29 #define SD_MR_HI_Z_RESET 0x0 #define SD_MR_RW_BITS 28:28 #define SD_MR_RW_SET 0x10000000 #define SD_MR_RW_CLR 0xefffffff #define SD_MR_RW_MSB 28 #define SD_MR_RW_LSB 28 #define SD_MR_RW_RESET 0x0 #define SD_MR_RDATA_BITS 23:16 #define SD_MR_RDATA_SET 0x00ff0000 #define SD_MR_RDATA_CLR 0xff00ffff #define SD_MR_RDATA_MSB 23 #define SD_MR_RDATA_LSB 16 #define SD_MR_RDATA_RESET 0x0 #define SD_MR_WDATA_BITS 15:8 #define SD_MR_WDATA_SET 0x0000ff00 #define SD_MR_WDATA_CLR 0xffff00ff #define SD_MR_WDATA_MSB 15 #define SD_MR_WDATA_LSB 8 #define SD_MR_WDATA_RESET 0x0 #define SD_MR_ADDR_BITS 7:0 #define SD_MR_ADDR_SET 0x000000ff #define SD_MR_ADDR_CLR 0xffffff00 #define SD_MR_ADDR_MSB 7 #define SD_MR_ADDR_LSB 0 #define SD_MR_ADDR_RESET 0x0 #define SD_MRT HW_REGISTER_RW( 0x7ee00064 ) #define SD_MRT_MASK 0x000001ff #define SD_MRT_WIDTH 9 #define SD_MRT_T_MRW_BITS 8:0 #define SD_MRT_T_MRW_SET 0x000001ff #define SD_MRT_T_MRW_CLR 0xfffffe00 #define SD_MRT_T_MRW_MSB 8 #define SD_MRT_T_MRW_LSB 0 #define SD_MRT_T_MRW_RESET 0x4 #define SD_PT1 HW_REGISTER_RW( 0x7ee00014 ) #define SD_PT1_MASK 0x0fffffff #define SD_PT1_WIDTH 28 #define SD_PT1_T_INIT3_BITS 27:8 #define SD_PT1_T_INIT3_SET 0x0fffff00 #define SD_PT1_T_INIT3_CLR 0xf00000ff #define SD_PT1_T_INIT3_MSB 27 #define SD_PT1_T_INIT3_LSB 8 #define SD_PT1_T_INIT3_RESET 0x13880 #define SD_PT1_T_INIT1_BITS 7:0 #define SD_PT1_T_INIT1_SET 0x000000ff #define SD_PT1_T_INIT1_CLR 0xffffff00 #define SD_PT1_T_INIT1_MSB 7 #define SD_PT1_T_INIT1_LSB 0 #define SD_PT1_T_INIT1_RESET 0x28 #define SD_PT2 HW_REGISTER_RW( 0x7ee00010 ) #define SD_PT2_MASK 0xffffffff #define SD_PT2_WIDTH 32 #define SD_PT2_T_INIT5_BITS 15:0 #define SD_PT2_T_INIT5_SET 0x0000ffff #define SD_PT2_T_INIT5_CLR 0xffff0000 #define SD_PT2_T_INIT5_MSB 15 #define SD_PT2_T_INIT5_LSB 0 #define SD_PT2_T_INIT5_RESET 0xfa0 #define SD_IDL HW_REGISTER_RW( 0x7ee00018 ) #define SD_IDL_MASK 0x0fffffff #define SD_IDL_WIDTH 28 #define SD_IDL_RESET 0000000000 #define SD_RTC HW_REGISTER_RW( 0x7ee0001c ) #define SD_RTC_MASK 0xffffffff #define SD_RTC_WIDTH 32 #define SD_RTC_RESET 0000000000 #define SD_WTC HW_REGISTER_RO( 0x7ee00020 ) #define SD_WTC_MASK 0x0fffffff #define SD_WTC_WIDTH 28 #define SD_WTC_RESET 0000000000 #define SD_RDC HW_REGISTER_RO( 0x7ee00024 ) #define SD_RDC_MASK 0x0fffffff #define SD_RDC_WIDTH 28 #define SD_RDC_RESET 0000000000 #define SD_WDC HW_REGISTER_RO( 0x7ee00028 ) #define SD_WDC_MASK 0x0fffffff #define SD_WDC_WIDTH 28 #define SD_WDC_RESET 0000000000 #define SD_RAC HW_REGISTER_RO( 0x7ee0002c ) #define SD_RAC_MASK 0x0fffffff #define SD_RAC_WIDTH 28 #define SD_RAC_RESET 0000000000 #define SD_CYC HW_REGISTER_RO( 0x7ee00030 ) #define SD_CYC_MASK 0x0fffffff #define SD_CYC_WIDTH 28 #define SD_CYC_RESET 0000000000 #define SD_CMD HW_REGISTER_RO( 0x7ee00034 ) #define SD_CMD_MASK 0x0fffffff #define SD_CMD_WIDTH 28 #define SD_CMD_RESET 0000000000 #define SD_DAT HW_REGISTER_RO( 0x7ee00038 ) #define SD_DAT_MASK 0x0fffffff #define SD_DAT_WIDTH 28 #define SD_DAT_RESET 0000000000 #define SD_REORD HW_REGISTER_RO( 0x7ee000a8 ) #define SD_REORD_MASK 0x0fffffff #define SD_REORD_WIDTH 28 #define SD_REORD_RESET 0000000000 #define SD_LAC HW_REGISTER_RO( 0x7ee000ac ) #define SD_LAC_MASK 0x0fffffff #define SD_LAC_WIDTH 28 #define SD_LAC_RESET 0000000000 #define SD_PRE HW_REGISTER_RO( 0x7ee000b0 ) #define SD_PRE_MASK 0x0fffffff #define SD_PRE_WIDTH 28 #define SD_PRE_RESET 0000000000 #define SD_SECSRT0 HW_REGISTER_RW( 0x7ee0003c ) #define SD_SECSRT0_MASK 0xffffffff #define SD_SECSRT0_WIDTH 32 #define SD_SECSRT0_ADDR_MS_BITS 31:13 #define SD_SECSRT0_ADDR_MS_SET 0xffffe000 #define SD_SECSRT0_ADDR_MS_CLR 0x00001fff #define SD_SECSRT0_ADDR_MS_MSB 31 #define SD_SECSRT0_ADDR_MS_LSB 13 #define SD_SECSRT0_ADDR_MS_RESET 0x0 #define SD_SECSRT0_ADDR_LS_BITS 12:1 #define SD_SECSRT0_ADDR_LS_SET 0x00001ffe #define SD_SECSRT0_ADDR_LS_CLR 0xffffe001 #define SD_SECSRT0_ADDR_LS_MSB 12 #define SD_SECSRT0_ADDR_LS_LSB 1 #define SD_SECSRT0_ADDR_LS_RESET 0x0 #define SD_SECSRT0_EN_BITS 0:0 #define SD_SECSRT0_EN_SET 0x00000001 #define SD_SECSRT0_EN_CLR 0xfffffffe #define SD_SECSRT0_EN_MSB 0 #define SD_SECSRT0_EN_LSB 0 #define SD_SECSRT0_EN_RESET 0x0 #define SD_SECEND0 HW_REGISTER_RW( 0x7ee00040 ) #define SD_SECEND0_MASK 0xffffffff #define SD_SECEND0_WIDTH 32 #define SD_SECEND0_ADDR_MS_BITS 31:13 #define SD_SECEND0_ADDR_MS_SET 0xffffe000 #define SD_SECEND0_ADDR_MS_CLR 0x00001fff #define SD_SECEND0_ADDR_MS_MSB 31 #define SD_SECEND0_ADDR_MS_LSB 13 #define SD_SECEND0_ADDR_MS_RESET 0x0 #define SD_SECEND0_ADDR_LS_BITS 12:0 #define SD_SECEND0_ADDR_LS_SET 0x00001fff #define SD_SECEND0_ADDR_LS_CLR 0xffffe000 #define SD_SECEND0_ADDR_LS_MSB 12 #define SD_SECEND0_ADDR_LS_LSB 0 #define SD_SECEND0_ADDR_LS_RESET 0xfff #define SD_SECSRT1 HW_REGISTER_RW( 0x7ee00044 ) #define SD_SECSRT1_MASK 0xffffffff #define SD_SECSRT1_WIDTH 32 #define SD_SECSRT1_ADDR_MS_BITS 31:13 #define SD_SECSRT1_ADDR_MS_SET 0xffffe000 #define SD_SECSRT1_ADDR_MS_CLR 0x00001fff #define SD_SECSRT1_ADDR_MS_MSB 31 #define SD_SECSRT1_ADDR_MS_LSB 13 #define SD_SECSRT1_ADDR_MS_RESET 0x0 #define SD_SECSRT1_ADDR_LS_BITS 12:1 #define SD_SECSRT1_ADDR_LS_SET 0x00001ffe #define SD_SECSRT1_ADDR_LS_CLR 0xffffe001 #define SD_SECSRT1_ADDR_LS_MSB 12 #define SD_SECSRT1_ADDR_LS_LSB 1 #define SD_SECSRT1_ADDR_LS_RESET 0x0 #define SD_SECSRT1_EN_BITS 0:0 #define SD_SECSRT1_EN_SET 0x00000001 #define SD_SECSRT1_EN_CLR 0xfffffffe #define SD_SECSRT1_EN_MSB 0 #define SD_SECSRT1_EN_LSB 0 #define SD_SECSRT1_EN_RESET 0x0 #define SD_SECEND1 HW_REGISTER_RW( 0x7ee00048 ) #define SD_SECEND1_MASK 0xffffffff #define SD_SECEND1_WIDTH 32 #define SD_SECEND1_ADDR_MS_BITS 31:13 #define SD_SECEND1_ADDR_MS_SET 0xffffe000 #define SD_SECEND1_ADDR_MS_CLR 0x00001fff #define SD_SECEND1_ADDR_MS_MSB 31 #define SD_SECEND1_ADDR_MS_LSB 13 #define SD_SECEND1_ADDR_MS_RESET 0x0 #define SD_SECEND1_ADDR_LS_BITS 12:0 #define SD_SECEND1_ADDR_LS_SET 0x00001fff #define SD_SECEND1_ADDR_LS_CLR 0xffffe000 #define SD_SECEND1_ADDR_LS_MSB 12 #define SD_SECEND1_ADDR_LS_LSB 0 #define SD_SECEND1_ADDR_LS_RESET 0xfff #define SD_SECSRT2 HW_REGISTER_RW( 0x7ee0004c ) #define SD_SECSRT2_MASK 0xffffffff #define SD_SECSRT2_WIDTH 32 #define SD_SECSRT2_ADDR_MS_BITS 31:13 #define SD_SECSRT2_ADDR_MS_SET 0xffffe000 #define SD_SECSRT2_ADDR_MS_CLR 0x00001fff #define SD_SECSRT2_ADDR_MS_MSB 31 #define SD_SECSRT2_ADDR_MS_LSB 13 #define SD_SECSRT2_ADDR_MS_RESET 0x0 #define SD_SECSRT2_ADDR_LS_BITS 12:1 #define SD_SECSRT2_ADDR_LS_SET 0x00001ffe #define SD_SECSRT2_ADDR_LS_CLR 0xffffe001 #define SD_SECSRT2_ADDR_LS_MSB 12 #define SD_SECSRT2_ADDR_LS_LSB 1 #define SD_SECSRT2_ADDR_LS_RESET 0x0 #define SD_SECSRT2_EN_BITS 0:0 #define SD_SECSRT2_EN_SET 0x00000001 #define SD_SECSRT2_EN_CLR 0xfffffffe #define SD_SECSRT2_EN_MSB 0 #define SD_SECSRT2_EN_LSB 0 #define SD_SECSRT2_EN_RESET 0x0 #define SD_SECEND2 HW_REGISTER_RW( 0x7ee00050 ) #define SD_SECEND2_MASK 0xffffffff #define SD_SECEND2_WIDTH 32 #define SD_SECEND2_ADDR_MS_BITS 31:13 #define SD_SECEND2_ADDR_MS_SET 0xffffe000 #define SD_SECEND2_ADDR_MS_CLR 0x00001fff #define SD_SECEND2_ADDR_MS_MSB 31 #define SD_SECEND2_ADDR_MS_LSB 13 #define SD_SECEND2_ADDR_MS_RESET 0x0 #define SD_SECEND2_ADDR_LS_BITS 12:0 #define SD_SECEND2_ADDR_LS_SET 0x00001fff #define SD_SECEND2_ADDR_LS_CLR 0xffffe000 #define SD_SECEND2_ADDR_LS_MSB 12 #define SD_SECEND2_ADDR_LS_LSB 0 #define SD_SECEND2_ADDR_LS_RESET 0xfff #define SD_SECSRT3 HW_REGISTER_RW( 0x7ee00054 ) #define SD_SECSRT3_MASK 0xffffffff #define SD_SECSRT3_WIDTH 32 #define SD_SECSRT3_ADDR_MS_BITS 31:13 #define SD_SECSRT3_ADDR_MS_SET 0xffffe000 #define SD_SECSRT3_ADDR_MS_CLR 0x00001fff #define SD_SECSRT3_ADDR_MS_MSB 31 #define SD_SECSRT3_ADDR_MS_LSB 13 #define SD_SECSRT3_ADDR_MS_RESET 0x0 #define SD_SECSRT3_ADDR_LS_BITS 12:1 #define SD_SECSRT3_ADDR_LS_SET 0x00001ffe #define SD_SECSRT3_ADDR_LS_CLR 0xffffe001 #define SD_SECSRT3_ADDR_LS_MSB 12 #define SD_SECSRT3_ADDR_LS_LSB 1 #define SD_SECSRT3_ADDR_LS_RESET 0x0 #define SD_SECSRT3_EN_BITS 0:0 #define SD_SECSRT3_EN_SET 0x00000001 #define SD_SECSRT3_EN_CLR 0xfffffffe #define SD_SECSRT3_EN_MSB 0 #define SD_SECSRT3_EN_LSB 0 #define SD_SECSRT3_EN_RESET 0x0 #define SD_SECEND3 HW_REGISTER_RW( 0x7ee00058 ) #define SD_SECEND3_MASK 0xffffffff #define SD_SECEND3_WIDTH 32 #define SD_SECEND3_ADDR_MS_BITS 31:13 #define SD_SECEND3_ADDR_MS_SET 0xffffe000 #define SD_SECEND3_ADDR_MS_CLR 0x00001fff #define SD_SECEND3_ADDR_MS_MSB 31 #define SD_SECEND3_ADDR_MS_LSB 13 #define SD_SECEND3_ADDR_MS_RESET 0x0 #define SD_SECEND3_ADDR_LS_BITS 12:0 #define SD_SECEND3_ADDR_LS_SET 0x00001fff #define SD_SECEND3_ADDR_LS_CLR 0xffffe000 #define SD_SECEND3_ADDR_LS_MSB 12 #define SD_SECEND3_ADDR_LS_LSB 0 #define SD_SECEND3_ADDR_LS_RESET 0xfff #define SD_PHYC HW_REGISTER_RW( 0x7ee00060 ) #define SD_PHYC_MASK 0x01111111 #define SD_PHYC_WIDTH 25 #define SD_PHYC_CRC_CLR_BITS 24:24 #define SD_PHYC_CRC_CLR_SET 0x01000000 #define SD_PHYC_CRC_CLR_CLR 0xfeffffff #define SD_PHYC_CRC_CLR_MSB 24 #define SD_PHYC_CRC_CLR_LSB 24 #define SD_PHYC_CRC_CLR_RESET 0x0 #define SD_PHYC_CRC_EN_BITS 20:20 #define SD_PHYC_CRC_EN_SET 0x00100000 #define SD_PHYC_CRC_EN_CLR 0xffefffff #define SD_PHYC_CRC_EN_MSB 20 #define SD_PHYC_CRC_EN_LSB 20 #define SD_PHYC_CRC_EN_RESET 0x0 #define SD_PHYC_MDLL_TMODE_BITS 16:16 #define SD_PHYC_MDLL_TMODE_SET 0x00010000 #define SD_PHYC_MDLL_TMODE_CLR 0xfffeffff #define SD_PHYC_MDLL_TMODE_MSB 16 #define SD_PHYC_MDLL_TMODE_LSB 16 #define SD_PHYC_MDLL_TMODE_RESET 0x0 #define SD_PHYC_IOB_TMODE_BITS 12:12 #define SD_PHYC_IOB_TMODE_SET 0x00001000 #define SD_PHYC_IOB_TMODE_CLR 0xffffefff #define SD_PHYC_IOB_TMODE_MSB 12 #define SD_PHYC_IOB_TMODE_LSB 12 #define SD_PHYC_IOB_TMODE_RESET 0x0 #define SD_PHYC_BIST_MODE_BITS 8:8 #define SD_PHYC_BIST_MODE_SET 0x00000100 #define SD_PHYC_BIST_MODE_CLR 0xfffffeff #define SD_PHYC_BIST_MODE_MSB 8 #define SD_PHYC_BIST_MODE_LSB 8 #define SD_PHYC_BIST_MODE_RESET 0x0 #define SD_PHYC_VREF_ENB_BITS 4:4 #define SD_PHYC_VREF_ENB_SET 0x00000010 #define SD_PHYC_VREF_ENB_CLR 0xffffffef #define SD_PHYC_VREF_ENB_MSB 4 #define SD_PHYC_VREF_ENB_LSB 4 #define SD_PHYC_VREF_ENB_RESET 0x0 #define SD_PHYC_PHYRST_BITS 0:0 #define SD_PHYC_PHYRST_SET 0x00000001 #define SD_PHYC_PHYRST_CLR 0xfffffffe #define SD_PHYC_PHYRST_MSB 0 #define SD_PHYC_PHYRST_LSB 0 #define SD_PHYC_PHYRST_RESET 0x0 #define SD_TMC HW_REGISTER_RW( 0x7ee0007c ) #define SD_TMC_MASK 0xffffff73 #define SD_TMC_WIDTH 32 #define SD_TMC_TSTPAT_BITS 31:16 #define SD_TMC_TSTPAT_SET 0xffff0000 #define SD_TMC_TSTPAT_CLR 0x0000ffff #define SD_TMC_TSTPAT_MSB 31 #define SD_TMC_TSTPAT_LSB 16 #define SD_TMC_TSTPAT_RESET 0x0 #define SD_TMC_IPRD_BITS 15:8 #define SD_TMC_IPRD_SET 0x0000ff00 #define SD_TMC_IPRD_CLR 0xffff00ff #define SD_TMC_IPRD_MSB 15 #define SD_TMC_IPRD_LSB 8 #define SD_TMC_IPRD_RESET 0x0 #define SD_TMC_IPSEL_BITS 6:4 #define SD_TMC_IPSEL_SET 0x00000070 #define SD_TMC_IPSEL_CLR 0xffffff8f #define SD_TMC_IPSEL_MSB 6 #define SD_TMC_IPSEL_LSB 4 #define SD_TMC_IPSEL_RESET 0x0 #define SD_TMC_TS_BITS 1:1 #define SD_TMC_TS_SET 0x00000002 #define SD_TMC_TS_CLR 0xfffffffd #define SD_TMC_TS_MSB 1 #define SD_TMC_TS_LSB 1 #define SD_TMC_TS_RESET 0x0 #define SD_TMC_TSTCLK_BITS 0:0 #define SD_TMC_TSTCLK_SET 0x00000001 #define SD_TMC_TSTCLK_CLR 0xfffffffe #define SD_TMC_TSTCLK_MSB 0 #define SD_TMC_TSTCLK_LSB 0 #define SD_TMC_TSTCLK_RESET 0x0 #define SD_RWC HW_REGISTER_RW( 0x7ee00080 ) #define SD_RWC_MASK 0x9fdf9f9f #define SD_RWC_WIDTH 32 #define SD_RWC_RSTMAX_BITS 31:31 #define SD_RWC_RSTMAX_SET 0x80000000 #define SD_RWC_RSTMAX_CLR 0x7fffffff #define SD_RWC_RSTMAX_MSB 31 #define SD_RWC_RSTMAX_LSB 31 #define SD_RWC_RSTMAX_RESET 0x0 #define SD_RWC_MAXCNT_BITS 28:24 #define SD_RWC_MAXCNT_SET 0x1f000000 #define SD_RWC_MAXCNT_CLR 0xe0ffffff #define SD_RWC_MAXCNT_MSB 28 #define SD_RWC_MAXCNT_LSB 24 #define SD_RWC_MAXCNT_RESET 0x0 #define SD_RWC_MARGIN_BITS 23:22 #define SD_RWC_MARGIN_SET 0x00c00000 #define SD_RWC_MARGIN_CLR 0xff3fffff #define SD_RWC_MARGIN_MSB 23 #define SD_RWC_MARGIN_LSB 22 #define SD_RWC_MARGIN_RESET 0x1 #define SD_RWC_LASTCNT_BITS 20:16 #define SD_RWC_LASTCNT_SET 0x001f0000 #define SD_RWC_LASTCNT_CLR 0xffe0ffff #define SD_RWC_LASTCNT_MSB 20 #define SD_RWC_LASTCNT_LSB 16 #define SD_RWC_LASTCNT_RESET 0x0 #define SD_RWC_WRTOVR_BITS 15:15 #define SD_RWC_WRTOVR_SET 0x00008000 #define SD_RWC_WRTOVR_CLR 0xffff7fff #define SD_RWC_WRTOVR_MSB 15 #define SD_RWC_WRTOVR_LSB 15 #define SD_RWC_WRTOVR_RESET 0x0 #define SD_RWC_WRTVAL_BITS 12:8 #define SD_RWC_WRTVAL_SET 0x00001f00 #define SD_RWC_WRTVAL_CLR 0xffffe0ff #define SD_RWC_WRTVAL_MSB 12 #define SD_RWC_WRTVAL_LSB 8 #define SD_RWC_WRTVAL_RESET 0x0 #define SD_RWC_RXOVR_BITS 7:7 #define SD_RWC_RXOVR_SET 0x00000080 #define SD_RWC_RXOVR_CLR 0xffffff7f #define SD_RWC_RXOVR_MSB 7 #define SD_RWC_RXOVR_LSB 7 #define SD_RWC_RXOVR_RESET 0x0 #define SD_RWC_RXVAL_BITS 4:0 #define SD_RWC_RXVAL_SET 0x0000001f #define SD_RWC_RXVAL_CLR 0xffffffe0 #define SD_RWC_RXVAL_MSB 4 #define SD_RWC_RXVAL_LSB 0 #define SD_RWC_RXVAL_RESET 0x0 #define SD_VAD HW_REGISTER_RO( 0x7ee00084 ) #define SD_VAD_MASK 0xffffffff #define SD_VAD_WIDTH 32 #define SD_VAD_RESET 0000000000 #define SD_VIN HW_REGISTER_RW( 0x7ee00088 ) #define SD_VIN_MASK 0x9113ffff #define SD_VIN_WIDTH 32 #define SD_VIN_CLEAR_BITS 31:31 #define SD_VIN_CLEAR_SET 0x80000000 #define SD_VIN_CLEAR_CLR 0x7fffffff #define SD_VIN_CLEAR_MSB 31 #define SD_VIN_CLEAR_LSB 31 #define SD_VIN_CLEAR_RESET 0x0 #define SD_VIN_INT_EN_BITS 28:28 #define SD_VIN_INT_EN_SET 0x10000000 #define SD_VIN_INT_EN_CLR 0xefffffff #define SD_VIN_INT_EN_MSB 28 #define SD_VIN_INT_EN_LSB 28 #define SD_VIN_INT_EN_RESET 0x0 #define SD_VIN_MULT_BITS 24:24 #define SD_VIN_MULT_SET 0x01000000 #define SD_VIN_MULT_CLR 0xfeffffff #define SD_VIN_MULT_MSB 24 #define SD_VIN_MULT_LSB 24 #define SD_VIN_MULT_RESET 0x0 #define SD_VIN_VIO_BITS 20:20 #define SD_VIN_VIO_SET 0x00100000 #define SD_VIN_VIO_CLR 0xffefffff #define SD_VIN_VIO_MSB 20 #define SD_VIN_VIO_LSB 20 #define SD_VIN_VIO_RESET 0x0 #define SD_VIN_SPLIT_BITS 17:17 #define SD_VIN_SPLIT_SET 0x00020000 #define SD_VIN_SPLIT_CLR 0xfffdffff #define SD_VIN_SPLIT_MSB 17 #define SD_VIN_SPLIT_LSB 17 #define SD_VIN_SPLIT_RESET 0x0 #define SD_VIN_WRITE_BITS 16:16 #define SD_VIN_WRITE_SET 0x00010000 #define SD_VIN_WRITE_CLR 0xfffeffff #define SD_VIN_WRITE_MSB 16 #define SD_VIN_WRITE_LSB 16 #define SD_VIN_WRITE_RESET 0x0 #define SD_VIN_ID_BITS 15:0 #define SD_VIN_ID_SET 0x0000ffff #define SD_VIN_ID_CLR 0xffff0000 #define SD_VIN_ID_MSB 15 #define SD_VIN_ID_LSB 0 #define SD_VIN_ID_RESET 0x0 #define SD_VER HW_REGISTER_RO( 0x7ee0009c ) #define SD_VER_MASK 0xffffffff #define SD_VER_WIDTH 32 #define SD_VER_RESET 0x00000009 #define SD_STALL HW_REGISTER_RW( 0x7ee000a0 ) // ENGINEERING & DEBUG USE ONLY #define SD_STALL_MASK 0x000003ff #define SD_STALL_WIDTH 10 #define SD_STALL_CYCLES_BITS 9:0 #define SD_STALL_CYCLES_SET 0x000003ff #define SD_STALL_CYCLES_CLR 0xfffffc00 #define SD_STALL_CYCLES_MSB 9 #define SD_STALL_CYCLES_LSB 0 #define SD_STALL_CYCLES_RESET 0x0 #define SD_CARCRC HW_REGISTER_RO( 0x7ee00100 ) #define SD_CARCRC_MASK 0xffffffff #define SD_CARCRC_WIDTH 32 #define SD_CARCRC_RISE_BITS 31:16 #define SD_CARCRC_RISE_SET 0xffff0000 #define SD_CARCRC_RISE_CLR 0x0000ffff #define SD_CARCRC_RISE_MSB 31 #define SD_CARCRC_RISE_LSB 16 #define SD_CARCRC_RISE_RESET 0x0 #define SD_CARCRC_FALL_BITS 15:0 #define SD_CARCRC_FALL_SET 0x0000ffff #define SD_CARCRC_FALL_CLR 0xffff0000 #define SD_CARCRC_FALL_MSB 15 #define SD_CARCRC_FALL_LSB 0 #define SD_CARCRC_FALL_RESET 0x0 #define SD_DMRCRC0 HW_REGISTER_RO( 0x7ee00104 ) #define SD_DMRCRC0_MASK 0xffffffff #define SD_DMRCRC0_WIDTH 32 #define SD_DMRCRC0_HIGH_BITS 31:16 #define SD_DMRCRC0_HIGH_SET 0xffff0000 #define SD_DMRCRC0_HIGH_CLR 0x0000ffff #define SD_DMRCRC0_HIGH_MSB 31 #define SD_DMRCRC0_HIGH_LSB 16 #define SD_DMRCRC0_HIGH_RESET 0x0 #define SD_DMRCRC0_LOW_BITS 15:0 #define SD_DMRCRC0_LOW_SET 0x0000ffff #define SD_DMRCRC0_LOW_CLR 0xffff0000 #define SD_DMRCRC0_LOW_MSB 15 #define SD_DMRCRC0_LOW_LSB 0 #define SD_DMRCRC0_LOW_RESET 0x0 #define SD_DMRCRC1 HW_REGISTER_RO( 0x7ee00108 ) // (only for 64 bit wide SDRAM) #define SD_DMRCRC1_MASK 0xffffffff #define SD_DMRCRC1_WIDTH 32 #define SD_DMRCRC1_HIGH_BITS 31:16 #define SD_DMRCRC1_HIGH_SET 0xffff0000 #define SD_DMRCRC1_HIGH_CLR 0x0000ffff #define SD_DMRCRC1_HIGH_MSB 31 #define SD_DMRCRC1_HIGH_LSB 16 #define SD_DMRCRC1_HIGH_RESET 0x0 #define SD_DMRCRC1_LOW_BITS 15:0 #define SD_DMRCRC1_LOW_SET 0x0000ffff #define SD_DMRCRC1_LOW_CLR 0xffff0000 #define SD_DMRCRC1_LOW_MSB 15 #define SD_DMRCRC1_LOW_LSB 0 #define SD_DMRCRC1_LOW_RESET 0x0 #define SD_DQRCRC0 HW_REGISTER_RO( 0x7ee0010c ) #define SD_DQRCRC0_MASK 0xffffffff #define SD_DQRCRC0_WIDTH 32 #define SD_DQRCRC0_RISE_BITS 31:16 #define SD_DQRCRC0_RISE_SET 0xffff0000 #define SD_DQRCRC0_RISE_CLR 0x0000ffff #define SD_DQRCRC0_RISE_MSB 31 #define SD_DQRCRC0_RISE_LSB 16 #define SD_DQRCRC0_RISE_RESET 0x0 #define SD_DQRCRC0_FALL_BITS 15:0 #define SD_DQRCRC0_FALL_SET 0x0000ffff #define SD_DQRCRC0_FALL_CLR 0xffff0000 #define SD_DQRCRC0_FALL_MSB 15 #define SD_DQRCRC0_FALL_LSB 0 #define SD_DQRCRC0_FALL_RESET 0x0 #define SD_DQRCRC1 HW_REGISTER_RO( 0x7ee00110 ) #define SD_DQRCRC1_MASK 0xffffffff #define SD_DQRCRC1_WIDTH 32 #define SD_DQRCRC1_RISE_BITS 31:16 #define SD_DQRCRC1_RISE_SET 0xffff0000 #define SD_DQRCRC1_RISE_CLR 0x0000ffff #define SD_DQRCRC1_RISE_MSB 31 #define SD_DQRCRC1_RISE_LSB 16 #define SD_DQRCRC1_RISE_RESET 0x0 #define SD_DQRCRC1_FALL_BITS 15:0 #define SD_DQRCRC1_FALL_SET 0x0000ffff #define SD_DQRCRC1_FALL_CLR 0xffff0000 #define SD_DQRCRC1_FALL_MSB 15 #define SD_DQRCRC1_FALL_LSB 0 #define SD_DQRCRC1_FALL_RESET 0x0 #define SD_DQRCRC2 HW_REGISTER_RO( 0x7ee00114 ) #define SD_DQRCRC2_MASK 0xffffffff #define SD_DQRCRC2_WIDTH 32 #define SD_DQRCRC2_RISE_BITS 31:16 #define SD_DQRCRC2_RISE_SET 0xffff0000 #define SD_DQRCRC2_RISE_CLR 0x0000ffff #define SD_DQRCRC2_RISE_MSB 31 #define SD_DQRCRC2_RISE_LSB 16 #define SD_DQRCRC2_RISE_RESET 0x0 #define SD_DQRCRC2_FALL_BITS 15:0 #define SD_DQRCRC2_FALL_SET 0x0000ffff #define SD_DQRCRC2_FALL_CLR 0xffff0000 #define SD_DQRCRC2_FALL_MSB 15 #define SD_DQRCRC2_FALL_LSB 0 #define SD_DQRCRC2_FALL_RESET 0x0 #define SD_DQRCRC3 HW_REGISTER_RO( 0x7ee00118 ) #define SD_DQRCRC3_MASK 0xffffffff #define SD_DQRCRC3_WIDTH 32 #define SD_DQRCRC3_RISE_BITS 31:16 #define SD_DQRCRC3_RISE_SET 0xffff0000 #define SD_DQRCRC3_RISE_CLR 0x0000ffff #define SD_DQRCRC3_RISE_MSB 31 #define SD_DQRCRC3_RISE_LSB 16 #define SD_DQRCRC3_RISE_RESET 0x0 #define SD_DQRCRC3_FALL_BITS 15:0 #define SD_DQRCRC3_FALL_SET 0x0000ffff #define SD_DQRCRC3_FALL_CLR 0xffff0000 #define SD_DQRCRC3_FALL_MSB 15 #define SD_DQRCRC3_FALL_LSB 0 #define SD_DQRCRC3_FALL_RESET 0x0 #define SD_DQRCRC4 HW_REGISTER_RO( 0x7ee0011c ) #define SD_DQRCRC4_MASK 0xffffffff #define SD_DQRCRC4_WIDTH 32 #define SD_DQRCRC4_RISE_BITS 31:16 #define SD_DQRCRC4_RISE_SET 0xffff0000 #define SD_DQRCRC4_RISE_CLR 0x0000ffff #define SD_DQRCRC4_RISE_MSB 31 #define SD_DQRCRC4_RISE_LSB 16 #define SD_DQRCRC4_RISE_RESET 0x0 #define SD_DQRCRC4_FALL_BITS 15:0 #define SD_DQRCRC4_FALL_SET 0x0000ffff #define SD_DQRCRC4_FALL_CLR 0xffff0000 #define SD_DQRCRC4_FALL_MSB 15 #define SD_DQRCRC4_FALL_LSB 0 #define SD_DQRCRC4_FALL_RESET 0x0 #define SD_DQRCRC5 HW_REGISTER_RO( 0x7ee00120 ) #define SD_DQRCRC5_MASK 0xffffffff #define SD_DQRCRC5_WIDTH 32 #define SD_DQRCRC5_RISE_BITS 31:16 #define SD_DQRCRC5_RISE_SET 0xffff0000 #define SD_DQRCRC5_RISE_CLR 0x0000ffff #define SD_DQRCRC5_RISE_MSB 31 #define SD_DQRCRC5_RISE_LSB 16 #define SD_DQRCRC5_RISE_RESET 0x0 #define SD_DQRCRC5_FALL_BITS 15:0 #define SD_DQRCRC5_FALL_SET 0x0000ffff #define SD_DQRCRC5_FALL_CLR 0xffff0000 #define SD_DQRCRC5_FALL_MSB 15 #define SD_DQRCRC5_FALL_LSB 0 #define SD_DQRCRC5_FALL_RESET 0x0 #define SD_DQRCRC6 HW_REGISTER_RO( 0x7ee00124 ) #define SD_DQRCRC6_MASK 0xffffffff #define SD_DQRCRC6_WIDTH 32 #define SD_DQRCRC6_RISE_BITS 31:16 #define SD_DQRCRC6_RISE_SET 0xffff0000 #define SD_DQRCRC6_RISE_CLR 0x0000ffff #define SD_DQRCRC6_RISE_MSB 31 #define SD_DQRCRC6_RISE_LSB 16 #define SD_DQRCRC6_RISE_RESET 0x0 #define SD_DQRCRC6_FALL_BITS 15:0 #define SD_DQRCRC6_FALL_SET 0x0000ffff #define SD_DQRCRC6_FALL_CLR 0xffff0000 #define SD_DQRCRC6_FALL_MSB 15 #define SD_DQRCRC6_FALL_LSB 0 #define SD_DQRCRC6_FALL_RESET 0x0 #define SD_DQRCRC7 HW_REGISTER_RO( 0x7ee00128 ) #define SD_DQRCRC7_MASK 0xffffffff #define SD_DQRCRC7_WIDTH 32 #define SD_DQRCRC7_RISE_BITS 31:16 #define SD_DQRCRC7_RISE_SET 0xffff0000 #define SD_DQRCRC7_RISE_CLR 0x0000ffff #define SD_DQRCRC7_RISE_MSB 31 #define SD_DQRCRC7_RISE_LSB 16 #define SD_DQRCRC7_RISE_RESET 0x0 #define SD_DQRCRC7_FALL_BITS 15:0 #define SD_DQRCRC7_FALL_SET 0x0000ffff #define SD_DQRCRC7_FALL_CLR 0xffff0000 #define SD_DQRCRC7_FALL_MSB 15 #define SD_DQRCRC7_FALL_LSB 0 #define SD_DQRCRC7_FALL_RESET 0x0 #define SD_DQRCRC8 HW_REGISTER_RO( 0x7ee0012c ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC8_MASK 0xffffffff #define SD_DQRCRC8_WIDTH 32 #define SD_DQRCRC8_RISE_BITS 31:16 #define SD_DQRCRC8_RISE_SET 0xffff0000 #define SD_DQRCRC8_RISE_CLR 0x0000ffff #define SD_DQRCRC8_RISE_MSB 31 #define SD_DQRCRC8_RISE_LSB 16 #define SD_DQRCRC8_RISE_RESET 0x0 #define SD_DQRCRC8_FALL_BITS 15:0 #define SD_DQRCRC8_FALL_SET 0x0000ffff #define SD_DQRCRC8_FALL_CLR 0xffff0000 #define SD_DQRCRC8_FALL_MSB 15 #define SD_DQRCRC8_FALL_LSB 0 #define SD_DQRCRC8_FALL_RESET 0x0 #define SD_DQRCRC9 HW_REGISTER_RO( 0x7ee00130 ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC9_MASK 0xffffffff #define SD_DQRCRC9_WIDTH 32 #define SD_DQRCRC9_RISE_BITS 31:16 #define SD_DQRCRC9_RISE_SET 0xffff0000 #define SD_DQRCRC9_RISE_CLR 0x0000ffff #define SD_DQRCRC9_RISE_MSB 31 #define SD_DQRCRC9_RISE_LSB 16 #define SD_DQRCRC9_RISE_RESET 0x0 #define SD_DQRCRC9_FALL_BITS 15:0 #define SD_DQRCRC9_FALL_SET 0x0000ffff #define SD_DQRCRC9_FALL_CLR 0xffff0000 #define SD_DQRCRC9_FALL_MSB 15 #define SD_DQRCRC9_FALL_LSB 0 #define SD_DQRCRC9_FALL_RESET 0x0 #define SD_DQRCRC10 HW_REGISTER_RO( 0x7ee00134 ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC10_MASK 0xffffffff #define SD_DQRCRC10_WIDTH 32 #define SD_DQRCRC10_RISE_BITS 31:16 #define SD_DQRCRC10_RISE_SET 0xffff0000 #define SD_DQRCRC10_RISE_CLR 0x0000ffff #define SD_DQRCRC10_RISE_MSB 31 #define SD_DQRCRC10_RISE_LSB 16 #define SD_DQRCRC10_RISE_RESET 0x0 #define SD_DQRCRC10_FALL_BITS 15:0 #define SD_DQRCRC10_FALL_SET 0x0000ffff #define SD_DQRCRC10_FALL_CLR 0xffff0000 #define SD_DQRCRC10_FALL_MSB 15 #define SD_DQRCRC10_FALL_LSB 0 #define SD_DQRCRC10_FALL_RESET 0x0 #define SD_DQRCRC11 HW_REGISTER_RO( 0x7ee00138 ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC11_MASK 0xffffffff #define SD_DQRCRC11_WIDTH 32 #define SD_DQRCRC11_RISE_BITS 31:16 #define SD_DQRCRC11_RISE_SET 0xffff0000 #define SD_DQRCRC11_RISE_CLR 0x0000ffff #define SD_DQRCRC11_RISE_MSB 31 #define SD_DQRCRC11_RISE_LSB 16 #define SD_DQRCRC11_RISE_RESET 0x0 #define SD_DQRCRC11_FALL_BITS 15:0 #define SD_DQRCRC11_FALL_SET 0x0000ffff #define SD_DQRCRC11_FALL_CLR 0xffff0000 #define SD_DQRCRC11_FALL_MSB 15 #define SD_DQRCRC11_FALL_LSB 0 #define SD_DQRCRC11_FALL_RESET 0x0 #define SD_DQRCRC12 HW_REGISTER_RO( 0x7ee0013c ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC12_MASK 0xffffffff #define SD_DQRCRC12_WIDTH 32 #define SD_DQRCRC12_RISE_BITS 31:16 #define SD_DQRCRC12_RISE_SET 0xffff0000 #define SD_DQRCRC12_RISE_CLR 0x0000ffff #define SD_DQRCRC12_RISE_MSB 31 #define SD_DQRCRC12_RISE_LSB 16 #define SD_DQRCRC12_RISE_RESET 0x0 #define SD_DQRCRC12_FALL_BITS 15:0 #define SD_DQRCRC12_FALL_SET 0x0000ffff #define SD_DQRCRC12_FALL_CLR 0xffff0000 #define SD_DQRCRC12_FALL_MSB 15 #define SD_DQRCRC12_FALL_LSB 0 #define SD_DQRCRC12_FALL_RESET 0x0 #define SD_DQRCRC13 HW_REGISTER_RO( 0x7ee00140 ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC13_MASK 0xffffffff #define SD_DQRCRC13_WIDTH 32 #define SD_DQRCRC13_RISE_BITS 31:16 #define SD_DQRCRC13_RISE_SET 0xffff0000 #define SD_DQRCRC13_RISE_CLR 0x0000ffff #define SD_DQRCRC13_RISE_MSB 31 #define SD_DQRCRC13_RISE_LSB 16 #define SD_DQRCRC13_RISE_RESET 0x0 #define SD_DQRCRC13_FALL_BITS 15:0 #define SD_DQRCRC13_FALL_SET 0x0000ffff #define SD_DQRCRC13_FALL_CLR 0xffff0000 #define SD_DQRCRC13_FALL_MSB 15 #define SD_DQRCRC13_FALL_LSB 0 #define SD_DQRCRC13_FALL_RESET 0x0 #define SD_DQRCRC14 HW_REGISTER_RO( 0x7ee00144 ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC14_MASK 0xffffffff #define SD_DQRCRC14_WIDTH 32 #define SD_DQRCRC14_RISE_BITS 31:16 #define SD_DQRCRC14_RISE_SET 0xffff0000 #define SD_DQRCRC14_RISE_CLR 0x0000ffff #define SD_DQRCRC14_RISE_MSB 31 #define SD_DQRCRC14_RISE_LSB 16 #define SD_DQRCRC14_RISE_RESET 0x0 #define SD_DQRCRC14_FALL_BITS 15:0 #define SD_DQRCRC14_FALL_SET 0x0000ffff #define SD_DQRCRC14_FALL_CLR 0xffff0000 #define SD_DQRCRC14_FALL_MSB 15 #define SD_DQRCRC14_FALL_LSB 0 #define SD_DQRCRC14_FALL_RESET 0x0 #define SD_DQRCRC15 HW_REGISTER_RO( 0x7ee00148 ) // (only for 64 bit wide SDRAM) #define SD_DQRCRC15_MASK 0xffffffff #define SD_DQRCRC15_WIDTH 32 #define SD_DQRCRC15_RISE_BITS 31:16 #define SD_DQRCRC15_RISE_SET 0xffff0000 #define SD_DQRCRC15_RISE_CLR 0x0000ffff #define SD_DQRCRC15_RISE_MSB 31 #define SD_DQRCRC15_RISE_LSB 16 #define SD_DQRCRC15_RISE_RESET 0x0 #define SD_DQRCRC15_FALL_BITS 15:0 #define SD_DQRCRC15_FALL_SET 0x0000ffff #define SD_DQRCRC15_FALL_CLR 0xffff0000 #define SD_DQRCRC15_FALL_MSB 15 #define SD_DQRCRC15_FALL_LSB 0 #define SD_DQRCRC15_FALL_RESET 0x0 #define SD_DQLCRC0 HW_REGISTER_RO( 0x7ee0014c ) #define SD_DQLCRC0_MASK 0xffffffff #define SD_DQLCRC0_WIDTH 32 #define SD_DQLCRC0_RISE_BITS 31:16 #define SD_DQLCRC0_RISE_SET 0xffff0000 #define SD_DQLCRC0_RISE_CLR 0x0000ffff #define SD_DQLCRC0_RISE_MSB 31 #define SD_DQLCRC0_RISE_LSB 16 #define SD_DQLCRC0_RISE_RESET 0x0 #define SD_DQLCRC0_FALL_BITS 15:0 #define SD_DQLCRC0_FALL_SET 0x0000ffff #define SD_DQLCRC0_FALL_CLR 0xffff0000 #define SD_DQLCRC0_FALL_MSB 15 #define SD_DQLCRC0_FALL_LSB 0 #define SD_DQLCRC0_FALL_RESET 0x0 #define SD_DQLCRC1 HW_REGISTER_RO( 0x7ee00150 ) #define SD_DQLCRC1_MASK 0xffffffff #define SD_DQLCRC1_WIDTH 32 #define SD_DQLCRC1_RISE_BITS 31:16 #define SD_DQLCRC1_RISE_SET 0xffff0000 #define SD_DQLCRC1_RISE_CLR 0x0000ffff #define SD_DQLCRC1_RISE_MSB 31 #define SD_DQLCRC1_RISE_LSB 16 #define SD_DQLCRC1_RISE_RESET 0x0 #define SD_DQLCRC1_FALL_BITS 15:0 #define SD_DQLCRC1_FALL_SET 0x0000ffff #define SD_DQLCRC1_FALL_CLR 0xffff0000 #define SD_DQLCRC1_FALL_MSB 15 #define SD_DQLCRC1_FALL_LSB 0 #define SD_DQLCRC1_FALL_RESET 0x0 #define SD_DQLCRC2 HW_REGISTER_RO( 0x7ee00154 ) #define SD_DQLCRC2_MASK 0xffffffff #define SD_DQLCRC2_WIDTH 32 #define SD_DQLCRC2_RISE_BITS 31:16 #define SD_DQLCRC2_RISE_SET 0xffff0000 #define SD_DQLCRC2_RISE_CLR 0x0000ffff #define SD_DQLCRC2_RISE_MSB 31 #define SD_DQLCRC2_RISE_LSB 16 #define SD_DQLCRC2_RISE_RESET 0x0 #define SD_DQLCRC2_FALL_BITS 15:0 #define SD_DQLCRC2_FALL_SET 0x0000ffff #define SD_DQLCRC2_FALL_CLR 0xffff0000 #define SD_DQLCRC2_FALL_MSB 15 #define SD_DQLCRC2_FALL_LSB 0 #define SD_DQLCRC2_FALL_RESET 0x0 #define SD_DQLCRC3 HW_REGISTER_RO( 0x7ee00158 ) #define SD_DQLCRC3_MASK 0xffffffff #define SD_DQLCRC3_WIDTH 32 #define SD_DQLCRC3_RISE_BITS 31:16 #define SD_DQLCRC3_RISE_SET 0xffff0000 #define SD_DQLCRC3_RISE_CLR 0x0000ffff #define SD_DQLCRC3_RISE_MSB 31 #define SD_DQLCRC3_RISE_LSB 16 #define SD_DQLCRC3_RISE_RESET 0x0 #define SD_DQLCRC3_FALL_BITS 15:0 #define SD_DQLCRC3_FALL_SET 0x0000ffff #define SD_DQLCRC3_FALL_CLR 0xffff0000 #define SD_DQLCRC3_FALL_MSB 15 #define SD_DQLCRC3_FALL_LSB 0 #define SD_DQLCRC3_FALL_RESET 0x0 #define SD_DQLCRC4 HW_REGISTER_RO( 0x7ee0015c ) #define SD_DQLCRC4_MASK 0xffffffff #define SD_DQLCRC4_WIDTH 32 #define SD_DQLCRC4_RISE_BITS 31:16 #define SD_DQLCRC4_RISE_SET 0xffff0000 #define SD_DQLCRC4_RISE_CLR 0x0000ffff #define SD_DQLCRC4_RISE_MSB 31 #define SD_DQLCRC4_RISE_LSB 16 #define SD_DQLCRC4_RISE_RESET 0x0 #define SD_DQLCRC4_FALL_BITS 15:0 #define SD_DQLCRC4_FALL_SET 0x0000ffff #define SD_DQLCRC4_FALL_CLR 0xffff0000 #define SD_DQLCRC4_FALL_MSB 15 #define SD_DQLCRC4_FALL_LSB 0 #define SD_DQLCRC4_FALL_RESET 0x0 #define SD_DQLCRC5 HW_REGISTER_RO( 0x7ee00160 ) #define SD_DQLCRC5_MASK 0xffffffff #define SD_DQLCRC5_WIDTH 32 #define SD_DQLCRC5_RISE_BITS 31:16 #define SD_DQLCRC5_RISE_SET 0xffff0000 #define SD_DQLCRC5_RISE_CLR 0x0000ffff #define SD_DQLCRC5_RISE_MSB 31 #define SD_DQLCRC5_RISE_LSB 16 #define SD_DQLCRC5_RISE_RESET 0x0 #define SD_DQLCRC5_FALL_BITS 15:0 #define SD_DQLCRC5_FALL_SET 0x0000ffff #define SD_DQLCRC5_FALL_CLR 0xffff0000 #define SD_DQLCRC5_FALL_MSB 15 #define SD_DQLCRC5_FALL_LSB 0 #define SD_DQLCRC5_FALL_RESET 0x0 #define SD_DQLCRC6 HW_REGISTER_RO( 0x7ee00164 ) #define SD_DQLCRC6_MASK 0xffffffff #define SD_DQLCRC6_WIDTH 32 #define SD_DQLCRC6_RISE_BITS 31:16 #define SD_DQLCRC6_RISE_SET 0xffff0000 #define SD_DQLCRC6_RISE_CLR 0x0000ffff #define SD_DQLCRC6_RISE_MSB 31 #define SD_DQLCRC6_RISE_LSB 16 #define SD_DQLCRC6_RISE_RESET 0x0 #define SD_DQLCRC6_FALL_BITS 15:0 #define SD_DQLCRC6_FALL_SET 0x0000ffff #define SD_DQLCRC6_FALL_CLR 0xffff0000 #define SD_DQLCRC6_FALL_MSB 15 #define SD_DQLCRC6_FALL_LSB 0 #define SD_DQLCRC6_FALL_RESET 0x0 #define SD_DQLCRC7 HW_REGISTER_RO( 0x7ee00168 ) #define SD_DQLCRC7_MASK 0xffffffff #define SD_DQLCRC7_WIDTH 32 #define SD_DQLCRC7_RISE_BITS 31:16 #define SD_DQLCRC7_RISE_SET 0xffff0000 #define SD_DQLCRC7_RISE_CLR 0x0000ffff #define SD_DQLCRC7_RISE_MSB 31 #define SD_DQLCRC7_RISE_LSB 16 #define SD_DQLCRC7_RISE_RESET 0x0 #define SD_DQLCRC7_FALL_BITS 15:0 #define SD_DQLCRC7_FALL_SET 0x0000ffff #define SD_DQLCRC7_FALL_CLR 0xffff0000 #define SD_DQLCRC7_FALL_MSB 15 #define SD_DQLCRC7_FALL_LSB 0 #define SD_DQLCRC7_FALL_RESET 0x0 #define SD_DQLCRC8 HW_REGISTER_RO( 0x7ee0016c ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC8_MASK 0xffffffff #define SD_DQLCRC8_WIDTH 32 #define SD_DQLCRC8_RISE_BITS 31:16 #define SD_DQLCRC8_RISE_SET 0xffff0000 #define SD_DQLCRC8_RISE_CLR 0x0000ffff #define SD_DQLCRC8_RISE_MSB 31 #define SD_DQLCRC8_RISE_LSB 16 #define SD_DQLCRC8_RISE_RESET 0x0 #define SD_DQLCRC8_FALL_BITS 15:0 #define SD_DQLCRC8_FALL_SET 0x0000ffff #define SD_DQLCRC8_FALL_CLR 0xffff0000 #define SD_DQLCRC8_FALL_MSB 15 #define SD_DQLCRC8_FALL_LSB 0 #define SD_DQLCRC8_FALL_RESET 0x0 #define SD_DQLCRC9 HW_REGISTER_RO( 0x7ee00170 ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC9_MASK 0xffffffff #define SD_DQLCRC9_WIDTH 32 #define SD_DQLCRC9_RISE_BITS 31:16 #define SD_DQLCRC9_RISE_SET 0xffff0000 #define SD_DQLCRC9_RISE_CLR 0x0000ffff #define SD_DQLCRC9_RISE_MSB 31 #define SD_DQLCRC9_RISE_LSB 16 #define SD_DQLCRC9_RISE_RESET 0x0 #define SD_DQLCRC9_FALL_BITS 15:0 #define SD_DQLCRC9_FALL_SET 0x0000ffff #define SD_DQLCRC9_FALL_CLR 0xffff0000 #define SD_DQLCRC9_FALL_MSB 15 #define SD_DQLCRC9_FALL_LSB 0 #define SD_DQLCRC9_FALL_RESET 0x0 #define SD_DQLCRC10 HW_REGISTER_RO( 0x7ee00174 ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC10_MASK 0xffffffff #define SD_DQLCRC10_WIDTH 32 #define SD_DQLCRC10_RISE_BITS 31:16 #define SD_DQLCRC10_RISE_SET 0xffff0000 #define SD_DQLCRC10_RISE_CLR 0x0000ffff #define SD_DQLCRC10_RISE_MSB 31 #define SD_DQLCRC10_RISE_LSB 16 #define SD_DQLCRC10_RISE_RESET 0x0 #define SD_DQLCRC10_FALL_BITS 15:0 #define SD_DQLCRC10_FALL_SET 0x0000ffff #define SD_DQLCRC10_FALL_CLR 0xffff0000 #define SD_DQLCRC10_FALL_MSB 15 #define SD_DQLCRC10_FALL_LSB 0 #define SD_DQLCRC10_FALL_RESET 0x0 #define SD_DQLCRC11 HW_REGISTER_RO( 0x7ee00178 ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC11_MASK 0xffffffff #define SD_DQLCRC11_WIDTH 32 #define SD_DQLCRC11_RISE_BITS 31:16 #define SD_DQLCRC11_RISE_SET 0xffff0000 #define SD_DQLCRC11_RISE_CLR 0x0000ffff #define SD_DQLCRC11_RISE_MSB 31 #define SD_DQLCRC11_RISE_LSB 16 #define SD_DQLCRC11_RISE_RESET 0x0 #define SD_DQLCRC11_FALL_BITS 15:0 #define SD_DQLCRC11_FALL_SET 0x0000ffff #define SD_DQLCRC11_FALL_CLR 0xffff0000 #define SD_DQLCRC11_FALL_MSB 15 #define SD_DQLCRC11_FALL_LSB 0 #define SD_DQLCRC11_FALL_RESET 0x0 #define SD_DQLCRC12 HW_REGISTER_RO( 0x7ee0017c ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC12_MASK 0xffffffff #define SD_DQLCRC12_WIDTH 32 #define SD_DQLCRC12_RISE_BITS 31:16 #define SD_DQLCRC12_RISE_SET 0xffff0000 #define SD_DQLCRC12_RISE_CLR 0x0000ffff #define SD_DQLCRC12_RISE_MSB 31 #define SD_DQLCRC12_RISE_LSB 16 #define SD_DQLCRC12_RISE_RESET 0x0 #define SD_DQLCRC12_FALL_BITS 15:0 #define SD_DQLCRC12_FALL_SET 0x0000ffff #define SD_DQLCRC12_FALL_CLR 0xffff0000 #define SD_DQLCRC12_FALL_MSB 15 #define SD_DQLCRC12_FALL_LSB 0 #define SD_DQLCRC12_FALL_RESET 0x0 #define SD_DQLCRC13 HW_REGISTER_RO( 0x7ee00180 ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC13_MASK 0xffffffff #define SD_DQLCRC13_WIDTH 32 #define SD_DQLCRC13_RISE_BITS 31:16 #define SD_DQLCRC13_RISE_SET 0xffff0000 #define SD_DQLCRC13_RISE_CLR 0x0000ffff #define SD_DQLCRC13_RISE_MSB 31 #define SD_DQLCRC13_RISE_LSB 16 #define SD_DQLCRC13_RISE_RESET 0x0 #define SD_DQLCRC13_FALL_BITS 15:0 #define SD_DQLCRC13_FALL_SET 0x0000ffff #define SD_DQLCRC13_FALL_CLR 0xffff0000 #define SD_DQLCRC13_FALL_MSB 15 #define SD_DQLCRC13_FALL_LSB 0 #define SD_DQLCRC13_FALL_RESET 0x0 #define SD_DQLCRC14 HW_REGISTER_RO( 0x7ee00184 ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC14_MASK 0xffffffff #define SD_DQLCRC14_WIDTH 32 #define SD_DQLCRC14_RISE_BITS 31:16 #define SD_DQLCRC14_RISE_SET 0xffff0000 #define SD_DQLCRC14_RISE_CLR 0x0000ffff #define SD_DQLCRC14_RISE_MSB 31 #define SD_DQLCRC14_RISE_LSB 16 #define SD_DQLCRC14_RISE_RESET 0x0 #define SD_DQLCRC14_FALL_BITS 15:0 #define SD_DQLCRC14_FALL_SET 0x0000ffff #define SD_DQLCRC14_FALL_CLR 0xffff0000 #define SD_DQLCRC14_FALL_MSB 15 #define SD_DQLCRC14_FALL_LSB 0 #define SD_DQLCRC14_FALL_RESET 0x0 #define SD_DQLCRC15 HW_REGISTER_RO( 0x7ee00188 ) // (only for 64 bit wide SDRAM) #define SD_DQLCRC15_MASK 0xffffffff #define SD_DQLCRC15_WIDTH 32 #define SD_DQLCRC15_RISE_BITS 31:16 #define SD_DQLCRC15_RISE_SET 0xffff0000 #define SD_DQLCRC15_RISE_CLR 0x0000ffff #define SD_DQLCRC15_RISE_MSB 31 #define SD_DQLCRC15_RISE_LSB 16 #define SD_DQLCRC15_RISE_RESET 0x0 #define SD_DQLCRC15_FALL_BITS 15:0 #define SD_DQLCRC15_FALL_SET 0x0000ffff #define SD_DQLCRC15_FALL_CLR 0xffff0000 #define SD_DQLCRC15_FALL_MSB 15 #define SD_DQLCRC15_FALL_LSB 0 #define SD_DQLCRC15_FALL_RESET 0x0