// This file was generated by the create_regs script
#define TS_BASE                                                  0x7e212000
#define TS_APB_ID                                                0x7473656e
#define TS_TSENSCTL                                              HW_REGISTER_RW( 0x7e212000 ) 
   #define TS_TSENSCTL_MASK                                      0x07ffffff
   #define TS_TSENSCTL_WIDTH                                     27
   #define TS_TSENSCTL_RESET                                     0000000000
      #define TS_TSENSCTL_PRWDW_BITS                             0:0
      #define TS_TSENSCTL_PRWDW_SET                              0x00000001
      #define TS_TSENSCTL_PRWDW_CLR                              0xfffffffe
      #define TS_TSENSCTL_PRWDW_MSB                              0
      #define TS_TSENSCTL_PRWDW_LSB                              0
      #define TS_TSENSCTL_RSTB_BITS                              1:1
      #define TS_TSENSCTL_RSTB_SET                               0x00000002
      #define TS_TSENSCTL_RSTB_CLR                               0xfffffffd
      #define TS_TSENSCTL_RSTB_MSB                               1
      #define TS_TSENSCTL_RSTB_LSB                               1
      #define TS_TSENSCTL_CTRL_BITS                              4:2
      #define TS_TSENSCTL_CTRL_SET                               0x0000001c
      #define TS_TSENSCTL_CTRL_CLR                               0xffffffe3
      #define TS_TSENSCTL_CTRL_MSB                               4
      #define TS_TSENSCTL_CTRL_LSB                               2
      #define TS_TSENSCTL_EN_INT_BITS                            5:5
      #define TS_TSENSCTL_EN_INT_SET                             0x00000020
      #define TS_TSENSCTL_EN_INT_CLR                             0xffffffdf
      #define TS_TSENSCTL_EN_INT_MSB                             5
      #define TS_TSENSCTL_EN_INT_LSB                             5
      #define TS_TSENSCTL_DIRECT_BITS                            6:6
      #define TS_TSENSCTL_DIRECT_SET                             0x00000040
      #define TS_TSENSCTL_DIRECT_CLR                             0xffffffbf
      #define TS_TSENSCTL_DIRECT_MSB                             6
      #define TS_TSENSCTL_DIRECT_LSB                             6
      #define TS_TSENSCTL_CLR_INT_BITS                           7:7
      #define TS_TSENSCTL_CLR_INT_SET                            0x00000080
      #define TS_TSENSCTL_CLR_INT_CLR                            0xffffff7f
      #define TS_TSENSCTL_CLR_INT_MSB                            7
      #define TS_TSENSCTL_CLR_INT_LSB                            7
      #define TS_TSENSCTL_THOLD_BITS                             17:8
      #define TS_TSENSCTL_THOLD_SET                              0x0003ff00
      #define TS_TSENSCTL_THOLD_CLR                              0xfffc00ff
      #define TS_TSENSCTL_THOLD_MSB                              17
      #define TS_TSENSCTL_THOLD_LSB                              8
      #define TS_TSENSCTL_RSTDELAY_BITS                          25:18
      #define TS_TSENSCTL_RSTDELAY_SET                           0x03fc0000
      #define TS_TSENSCTL_RSTDELAY_CLR                           0xfc03ffff
      #define TS_TSENSCTL_RSTDELAY_MSB                           25
      #define TS_TSENSCTL_RSTDELAY_LSB                           18
      #define TS_TSENSCTL_REGULEN_BITS                           26:26
      #define TS_TSENSCTL_REGULEN_SET                            0x04000000
      #define TS_TSENSCTL_REGULEN_CLR                            0xfbffffff
      #define TS_TSENSCTL_REGULEN_MSB                            26
      #define TS_TSENSCTL_REGULEN_LSB                            26
#define TS_TSENSSTAT                                             HW_REGISTER_RW( 0x7e212004 ) 
   #define TS_TSENSSTAT_MASK                                     0x00000fff
   #define TS_TSENSSTAT_WIDTH                                    12
   #define TS_TSENSSTAT_RESET                                    0000000000
      #define TS_TSENSSTAT_DATA_BITS                             9:0
      #define TS_TSENSSTAT_DATA_SET                              0x000003ff
      #define TS_TSENSSTAT_DATA_CLR                              0xfffffc00
      #define TS_TSENSSTAT_DATA_MSB                              9
      #define TS_TSENSSTAT_DATA_LSB                              0
      #define TS_TSENSSTAT_VALID_BITS                            10:10
      #define TS_TSENSSTAT_VALID_SET                             0x00000400
      #define TS_TSENSSTAT_VALID_CLR                             0xfffffbff
      #define TS_TSENSSTAT_VALID_MSB                             10
      #define TS_TSENSSTAT_VALID_LSB                             10
      #define TS_TSENSSTAT_INTERUPT_BITS                         11:11
      #define TS_TSENSSTAT_INTERUPT_SET                          0x00000800
      #define TS_TSENSSTAT_INTERUPT_CLR                          0xfffff7ff
      #define TS_TSENSSTAT_INTERUPT_MSB                          11
      #define TS_TSENSSTAT_INTERUPT_LSB                          11