// This file was generated by the create_regs script #define TH_BASE 0x18e00000 #define TH_APB_ID 0x74687265 #define TH_XCS HW_REGISTER_RW( 0x18e00000 ) #define TH_XCS__MASK 0xfffffffc #define TH_XCS__WIDTH 32 #define TH_XCS__RESET 0x0155cb00 #define TH_XCS_THR_READIES_MSB 31 #define TH_XCS_THR_READIES_LSB 28 #define TH_XCS_PREV_FIRST_S_MSB 27 #define TH_XCS_PREV_FIRST_S_LSB 27 #define TH_XCS_MODE_2STAGE_MSB 26 #define TH_XCS_MODE_2STAGE_LSB 26 #define TH_XCS_FLUSH_2STAGE_MSB 25 #define TH_XCS_FLUSH_2STAGE_LSB 25 #define TH_XCS_STARTUP_MSB 24 #define TH_XCS_STARTUP_LSB 24 #define TH_XCS_THR_STATE3_MSB 23 #define TH_XCS_THR_STATE3_LSB 22 #define TH_XCS_THR_STATE2_MSB 21 #define TH_XCS_THR_STATE2_LSB 20 #define TH_XCS_THR_STATE1_MSB 19 #define TH_XCS_THR_STATE1_LSB 18 #define TH_XCS_THR_STATE0_MSB 17 #define TH_XCS_THR_STATE0_LSB 16 #define TH_XCS_SYS_STATE_MSB 15 #define TH_XCS_SYS_STATE_LSB 14 #define TH_XCS_NEXT_READY_MSB 13 #define TH_XCS_NEXT_READY_LSB 12 #define TH_XCS_PREV_SYS_MSB 11 #define TH_XCS_PREV_SYS_LSB 11 #define TH_XCS_PREV_IDLE_MSB 10 #define TH_XCS_PREV_IDLE_LSB 10 #define TH_XCS_PREV_THREAD_MSB 9 #define TH_XCS_PREV_THREAD_LSB 8 #define TH_XCS_THREAD_HWEN_MSB 7 #define TH_XCS_THREAD_HWEN_LSB 4 #define TH_XCS_THREAD_SYSFL_MSB 3 #define TH_XCS_THREAD_SYSFL_LSB 3 #define TH_XCS_THREAD_SYSIN_MSB 2 #define TH_XCS_THREAD_SYSIN_LSB 2 #define TH_XCFG HW_REGISTER_RW( 0x18e00004 ) #define TH_XCFG__MASK 0xffffffff #define TH_XCFG__WIDTH 32 #define TH_XCFG__RESET 0000000000 #define TH_XCFG_SW_ENS_MSB 11 #define TH_XCFG_SW_ENS_LSB 8 #define TH_XCFG_SW_SYSFLUSH_MSB 7 #define TH_XCFG_SW_SYSFLUSH_LSB 7 #define TH_XCFG_SW_SYSINTR_MSB 6 #define TH_XCFG_SW_SYSINTR_LSB 6 #define TH_XCFG_SW_EN_SEL_MSB 4 #define TH_XCFG_SW_EN_SEL_LSB 4 #define TH_XCFG_SW_FLUSH_SEL_MSB 3 #define TH_XCFG_SW_FLUSH_SEL_LSB 3 #define TH_XCFG_SW_INTR_SEL_MSB 2 #define TH_XCFG_SW_INTR_SEL_LSB 2 #define TH_XCFG_THR_EN_MSB 0 #define TH_XCFG_THR_EN_LSB 0 #define TH_XSTPC HW_REGISTER_RW( 0x18e00008 ) #define TH_XSTPC__MASK 0xfffffffe #define TH_XSTPC__WIDTH 32 #define TH_XSTPC__RESET 0000000000 #define TH_XSTPC__MSB 31 #define TH_XSTPC__LSB 1 #define TH_XITPC HW_REGISTER_RW( 0x18e0000c ) #define TH_XITPC__MASK 0xfffffffe #define TH_XITPC__WIDTH 32 #define TH_XITPC__RESET 0000000000 #define TH_XITPC__MSB 31 #define TH_XITPC__LSB 1 #define TH_XT0PC HW_REGISTER_RW( 0x18e00010 ) #define TH_XT0PC__MASK 0xfffffffe #define TH_XT0PC__WIDTH 32 #define TH_XT0PC__RESET 0000000000 #define TH_XT0PC__MSB 31 #define TH_XT0PC__LSB 1 #define TH_XT0UD HW_REGISTER_RW( 0x18e00014 ) #define TH_XT0UD__MASK 0xffffffff #define TH_XT0UD__WIDTH 32 #define TH_XT0UD__RESET 0000000000 #define TH_XT0UD__MSB 31 #define TH_XT0UD__LSB 0 #define TH_XT1PC HW_REGISTER_RW( 0x18e00018 ) #define TH_XT1PC__MASK 0xfffffffe #define TH_XT1PC__WIDTH 32 #define TH_XT1PC__RESET 0000000000 #define TH_XT1PC__MSB 31 #define TH_XT1PC__LSB 1 #define TH_XT1UD HW_REGISTER_RW( 0x18e0001c ) #define TH_XT1UD__MASK 0xffffffff #define TH_XT1UD__WIDTH 32 #define TH_XT1UD__RESET 0000000000 #define TH_XT1UD__MSB 31 #define TH_XT1UD__LSB 0 #define TH_XT2PC HW_REGISTER_RW( 0x18e00020 ) #define TH_XT2PC__MASK 0xfffffffe #define TH_XT2PC__WIDTH 32 #define TH_XT2PC__RESET 0000000000 #define TH_XT2PC__MSB 31 #define TH_XT2PC__LSB 1 #define TH_XT2UD HW_REGISTER_RW( 0x18e00024 ) #define TH_XT2UD__MASK 0xffffffff #define TH_XT2UD__WIDTH 32 #define TH_XT2UD__RESET 0000000000 #define TH_XT2UD__MSB 31 #define TH_XT2UD__LSB 0 #define TH_XT3PC HW_REGISTER_RW( 0x18e00028 ) #define TH_XT3PC__MASK 0xfffffffe #define TH_XT3PC__WIDTH 32 #define TH_XT3PC__RESET 0000000000 #define TH_XT3PC__MSB 31 #define TH_XT3PC__LSB 1 #define TH_XT3UD HW_REGISTER_RW( 0x18e0002c ) #define TH_XT3UD__MASK 0xffffffff #define TH_XT3UD__WIDTH 32 #define TH_XT3UD__RESET 0000000000 #define TH_XT3UD__MSB 31 #define TH_XT3UD__LSB 0