// This file was generated by the create_regs script #define HD_BASE 0x7e808000 #define HD_APB_ID 0x48444d49 #define HD_HDM_CTL HW_REGISTER_RW( 0x7e80800c ) #define HD_HDM_CTL_MASK 0x000003f7 #define HD_HDM_CTL_WIDTH 10 #define HD_HDM_CTL_RESET 0x000000f0 #define HD_HDM_CTL_ENABLE_BITS 0:0 #define HD_HDM_CTL_ENABLE_SET 0x00000001 #define HD_HDM_CTL_ENABLE_CLR 0xfffffffe #define HD_HDM_CTL_ENABLE_MSB 0 #define HD_HDM_CTL_ENABLE_LSB 0 #define HD_HDM_CTL_ENABLE_RESET 0x0 #define HD_HDM_CTL_ENDIAN_BITS 1:1 #define HD_HDM_CTL_ENDIAN_SET 0x00000002 #define HD_HDM_CTL_ENDIAN_CLR 0xfffffffd #define HD_HDM_CTL_ENDIAN_MSB 1 #define HD_HDM_CTL_ENDIAN_LSB 1 #define HD_HDM_CTL_ENDIAN_RESET 0x0 #define HD_HDM_CTL_SW_RST_BITS 2:2 #define HD_HDM_CTL_SW_RST_SET 0x00000004 #define HD_HDM_CTL_SW_RST_CLR 0xfffffffb #define HD_HDM_CTL_SW_RST_MSB 2 #define HD_HDM_CTL_SW_RST_LSB 2 #define HD_HDM_CTL_SW_RST_RESET 0x0 #define HD_HDM_CTL_PDSTBY_BITS 5:4 #define HD_HDM_CTL_PDSTBY_SET 0x00000030 #define HD_HDM_CTL_PDSTBY_CLR 0xffffffcf #define HD_HDM_CTL_PDSTBY_MSB 5 #define HD_HDM_CTL_PDSTBY_LSB 4 #define HD_HDM_CTL_PDSTBY_RESET 0x3 #define HD_HDM_CTL_RFSTBY_BITS 7:6 #define HD_HDM_CTL_RFSTBY_SET 0x000000c0 #define HD_HDM_CTL_RFSTBY_CLR 0xffffff3f #define HD_HDM_CTL_RFSTBY_MSB 7 #define HD_HDM_CTL_RFSTBY_LSB 6 #define HD_HDM_CTL_RFSTBY_RESET 0x3 #define HD_HDM_CTL_CECOVR_BITS 8:8 #define HD_HDM_CTL_CECOVR_SET 0x00000100 #define HD_HDM_CTL_CECOVR_CLR 0xfffffeff #define HD_HDM_CTL_CECOVR_MSB 8 #define HD_HDM_CTL_CECOVR_LSB 8 #define HD_HDM_CTL_CECOVR_RESET 0x0 #define HD_HDM_CTL_CECRXD_BITS 9:9 #define HD_HDM_CTL_CECRXD_SET 0x00000200 #define HD_HDM_CTL_CECRXD_CLR 0xfffffdff #define HD_HDM_CTL_CECRXD_MSB 9 #define HD_HDM_CTL_CECRXD_LSB 9 #define HD_HDM_CTL_CECRXD_RESET 0x0 #define HD_MAI_CTL HW_REGISTER_RW( 0x7e808014 ) #define HD_MAI_CTL_MASK 0x0000ffff #define HD_MAI_CTL_WIDTH 16 #define HD_MAI_CTL_RESET 0x00000020 #define HD_MAI_CTL_RST_MAI_BITS 0:0 #define HD_MAI_CTL_RST_MAI_SET 0x00000001 #define HD_MAI_CTL_RST_MAI_CLR 0xfffffffe #define HD_MAI_CTL_RST_MAI_MSB 0 #define HD_MAI_CTL_RST_MAI_LSB 0 #define HD_MAI_CTL_RST_MAI_RESET 0x0 #define HD_MAI_CTL_ERRORF_BITS 1:1 #define HD_MAI_CTL_ERRORF_SET 0x00000002 #define HD_MAI_CTL_ERRORF_CLR 0xfffffffd #define HD_MAI_CTL_ERRORF_MSB 1 #define HD_MAI_CTL_ERRORF_LSB 1 #define HD_MAI_CTL_ERRORF_RESET 0x0 #define HD_MAI_CTL_ERRORE_BITS 2:2 #define HD_MAI_CTL_ERRORE_SET 0x00000004 #define HD_MAI_CTL_ERRORE_CLR 0xfffffffb #define HD_MAI_CTL_ERRORE_MSB 2 #define HD_MAI_CTL_ERRORE_LSB 2 #define HD_MAI_CTL_ERRORE_RESET 0x0 #define HD_MAI_CTL_ENABLE_BITS 3:3 #define HD_MAI_CTL_ENABLE_SET 0x00000008 #define HD_MAI_CTL_ENABLE_CLR 0xfffffff7 #define HD_MAI_CTL_ENABLE_MSB 3 #define HD_MAI_CTL_ENABLE_LSB 3 #define HD_MAI_CTL_ENABLE_RESET 0x0 #define HD_MAI_CTL_CHNUM_BITS 7:4 #define HD_MAI_CTL_CHNUM_SET 0x000000f0 #define HD_MAI_CTL_CHNUM_CLR 0xffffff0f #define HD_MAI_CTL_CHNUM_MSB 7 #define HD_MAI_CTL_CHNUM_LSB 4 #define HD_MAI_CTL_CHNUM_RESET 0x2 #define HD_MAI_CTL_PAREN_BITS 8:8 #define HD_MAI_CTL_PAREN_SET 0x00000100 #define HD_MAI_CTL_PAREN_CLR 0xfffffeff #define HD_MAI_CTL_PAREN_MSB 8 #define HD_MAI_CTL_PAREN_LSB 8 #define HD_MAI_CTL_PAREN_RESET 0x0 #define HD_MAI_CTL_FLUSH_BITS 9:9 #define HD_MAI_CTL_FLUSH_SET 0x00000200 #define HD_MAI_CTL_FLUSH_CLR 0xfffffdff #define HD_MAI_CTL_FLUSH_MSB 9 #define HD_MAI_CTL_FLUSH_LSB 9 #define HD_MAI_CTL_FLUSH_RESET 0x0 #define HD_MAI_CTL_EMPTY_BITS 10:10 #define HD_MAI_CTL_EMPTY_SET 0x00000400 #define HD_MAI_CTL_EMPTY_CLR 0xfffffbff #define HD_MAI_CTL_EMPTY_MSB 10 #define HD_MAI_CTL_EMPTY_LSB 10 #define HD_MAI_CTL_EMPTY_RESET 0x0 #define HD_MAI_CTL_FULL_BITS 11:11 #define HD_MAI_CTL_FULL_SET 0x00000800 #define HD_MAI_CTL_FULL_CLR 0xfffff7ff #define HD_MAI_CTL_FULL_MSB 11 #define HD_MAI_CTL_FULL_LSB 11 #define HD_MAI_CTL_FULL_RESET 0x0 #define HD_MAI_CTL_WHOLSMP_BITS 12:12 #define HD_MAI_CTL_WHOLSMP_SET 0x00001000 #define HD_MAI_CTL_WHOLSMP_CLR 0xffffefff #define HD_MAI_CTL_WHOLSMP_MSB 12 #define HD_MAI_CTL_WHOLSMP_LSB 12 #define HD_MAI_CTL_WHOLSMP_RESET 0x0 #define HD_MAI_CTL_CHALIGN_BITS 13:13 #define HD_MAI_CTL_CHALIGN_SET 0x00002000 #define HD_MAI_CTL_CHALIGN_CLR 0xffffdfff #define HD_MAI_CTL_CHALIGN_MSB 13 #define HD_MAI_CTL_CHALIGN_LSB 13 #define HD_MAI_CTL_CHALIGN_RESET 0x0 #define HD_MAI_CTL_BUSY_BITS 14:14 #define HD_MAI_CTL_BUSY_SET 0x00004000 #define HD_MAI_CTL_BUSY_CLR 0xffffbfff #define HD_MAI_CTL_BUSY_MSB 14 #define HD_MAI_CTL_BUSY_LSB 14 #define HD_MAI_CTL_BUSY_RESET 0x0 #define HD_MAI_CTL_DLATE_BITS 15:15 #define HD_MAI_CTL_DLATE_SET 0x00008000 #define HD_MAI_CTL_DLATE_CLR 0xffff7fff #define HD_MAI_CTL_DLATE_MSB 15 #define HD_MAI_CTL_DLATE_LSB 15 #define HD_MAI_CTL_DLATE_RESET 0x0 #define HD_MAI_THR HW_REGISTER_RW( 0x7e808018 ) #define HD_MAI_THR_MASK 0xffffffff #define HD_MAI_THR_WIDTH 32 #define HD_MAI_THR_RESET 0x01010101 #define HD_MAI_THR_DREQLOW_BITS 5:0 #define HD_MAI_THR_DREQLOW_SET 0x0000003f #define HD_MAI_THR_DREQLOW_CLR 0xffffffc0 #define HD_MAI_THR_DREQLOW_MSB 5 #define HD_MAI_THR_DREQLOW_LSB 0 #define HD_MAI_THR_DREQLOW_RESET 0x1 #define HD_MAI_THR_DREQHIGH_BITS 13:8 #define HD_MAI_THR_DREQHIGH_SET 0x00003f00 #define HD_MAI_THR_DREQHIGH_CLR 0xffffc0ff #define HD_MAI_THR_DREQHIGH_MSB 13 #define HD_MAI_THR_DREQHIGH_LSB 8 #define HD_MAI_THR_DREQHIGH_RESET 0x1 #define HD_MAI_THR_PANICLOW_BITS 21:16 #define HD_MAI_THR_PANICLOW_SET 0x003f0000 #define HD_MAI_THR_PANICLOW_CLR 0xffc0ffff #define HD_MAI_THR_PANICLOW_MSB 21 #define HD_MAI_THR_PANICLOW_LSB 16 #define HD_MAI_THR_PANICLOW_RESET 0x1 #define HD_MAI_THR_PANICHIGH_BITS 29:24 #define HD_MAI_THR_PANICHIGH_SET 0x3f000000 #define HD_MAI_THR_PANICHIGH_CLR 0xc0ffffff #define HD_MAI_THR_PANICHIGH_MSB 29 #define HD_MAI_THR_PANICHIGH_LSB 24 #define HD_MAI_THR_PANICHIGH_RESET 0x1 #define HD_MAI_FMT HW_REGISTER_RW( 0x7e80801c ) #define HD_MAI_FMT_MASK 0xffffffff #define HD_MAI_FMT_WIDTH 32 #define HD_MAI_FMT_RESET 0000000000 #define HD_MAI_DAT HW_REGISTER_RW( 0x7e808020 ) #define HD_MAI_DAT_MASK 0xffffffff #define HD_MAI_DAT_WIDTH 32 #define HD_MAI_DAT_RESET 0000000000 #define HD_SPARE HW_REGISTER_RW( 0x7e808024 ) #define HD_SPARE_MASK 0xffffffff #define HD_SPARE_WIDTH 32 #define HD_SPARE_RESET 0000000000 #define HD_MAI_SMP HW_REGISTER_RW( 0x7e80802c ) #define HD_MAI_SMP_MASK 0xffffffff #define HD_MAI_SMP_WIDTH 32 #define HD_MAI_SMP_RESET 0000000000 #define HD_VID_CTL HW_REGISTER_RW( 0x7e808038 ) #define HD_VID_CTL_MASK 0xfffc0000 #define HD_VID_CTL_WIDTH 32 #define HD_VID_CTL_RESET 0x00040000 #define HD_VID_CTL_BLANKPIX_BITS 18:18 #define HD_VID_CTL_BLANKPIX_SET 0x00040000 #define HD_VID_CTL_BLANKPIX_CLR 0xfffbffff #define HD_VID_CTL_BLANKPIX_MSB 18 #define HD_VID_CTL_BLANKPIX_LSB 18 #define HD_VID_CTL_BLANKPIX_RESET 0x1 #define HD_VID_CTL_EMPRGB_BITS 19:19 #define HD_VID_CTL_EMPRGB_SET 0x00080000 #define HD_VID_CTL_EMPRGB_CLR 0xfff7ffff #define HD_VID_CTL_EMPRGB_MSB 19 #define HD_VID_CTL_EMPRGB_LSB 19 #define HD_VID_CTL_EMPRGB_RESET 0x0 #define HD_VID_CTL_EMPSYNC_BITS 20:20 #define HD_VID_CTL_EMPSYNC_SET 0x00100000 #define HD_VID_CTL_EMPSYNC_CLR 0xffefffff #define HD_VID_CTL_EMPSYNC_MSB 20 #define HD_VID_CTL_EMPSYNC_LSB 20 #define HD_VID_CTL_EMPSYNC_RESET 0x0 #define HD_VID_CTL_FULRGB_BITS 21:21 #define HD_VID_CTL_FULRGB_SET 0x00200000 #define HD_VID_CTL_FULRGB_CLR 0xffdfffff #define HD_VID_CTL_FULRGB_MSB 21 #define HD_VID_CTL_FULRGB_LSB 21 #define HD_VID_CTL_FULRGB_RESET 0x0 #define HD_VID_CTL_FULSYNC_BITS 22:22 #define HD_VID_CTL_FULSYNC_SET 0x00400000 #define HD_VID_CTL_FULSYNC_CLR 0xffbfffff #define HD_VID_CTL_FULSYNC_MSB 22 #define HD_VID_CTL_FULSYNC_LSB 22 #define HD_VID_CTL_FULSYNC_RESET 0x0 #define HD_VID_CTL_CLRRGB_BITS 23:23 #define HD_VID_CTL_CLRRGB_SET 0x00800000 #define HD_VID_CTL_CLRRGB_CLR 0xff7fffff #define HD_VID_CTL_CLRRGB_MSB 23 #define HD_VID_CTL_CLRRGB_LSB 23 #define HD_VID_CTL_CLRRGB_RESET 0x0 #define HD_VID_CTL_CLRSYNC_BITS 24:24 #define HD_VID_CTL_CLRSYNC_SET 0x01000000 #define HD_VID_CTL_CLRSYNC_CLR 0xfeffffff #define HD_VID_CTL_CLRSYNC_MSB 24 #define HD_VID_CTL_CLRSYNC_LSB 24 #define HD_VID_CTL_CLRSYNC_RESET 0x0 #define HD_VID_CTL_ERROR_BITS 26:25 #define HD_VID_CTL_ERROR_SET 0x06000000 #define HD_VID_CTL_ERROR_CLR 0xf9ffffff #define HD_VID_CTL_ERROR_MSB 26 #define HD_VID_CTL_ERROR_LSB 25 #define HD_VID_CTL_ERROR_RESET 0x0 #define HD_VID_CTL_HPOL_BITS 27:27 #define HD_VID_CTL_HPOL_SET 0x08000000 #define HD_VID_CTL_HPOL_CLR 0xf7ffffff #define HD_VID_CTL_HPOL_MSB 27 #define HD_VID_CTL_HPOL_LSB 27 #define HD_VID_CTL_HPOL_RESET 0x0 #define HD_VID_CTL_VPOL_BITS 28:28 #define HD_VID_CTL_VPOL_SET 0x10000000 #define HD_VID_CTL_VPOL_CLR 0xefffffff #define HD_VID_CTL_VPOL_MSB 28 #define HD_VID_CTL_VPOL_LSB 28 #define HD_VID_CTL_VPOL_RESET 0x0 #define HD_VID_CTL_RST_FRAMEC_BITS 29:29 #define HD_VID_CTL_RST_FRAMEC_SET 0x20000000 #define HD_VID_CTL_RST_FRAMEC_CLR 0xdfffffff #define HD_VID_CTL_RST_FRAMEC_MSB 29 #define HD_VID_CTL_RST_FRAMEC_LSB 29 #define HD_VID_CTL_RST_FRAMEC_RESET 0x0 #define HD_VID_CTL_UFEN_BITS 30:30 #define HD_VID_CTL_UFEN_SET 0x40000000 #define HD_VID_CTL_UFEN_CLR 0xbfffffff #define HD_VID_CTL_UFEN_MSB 30 #define HD_VID_CTL_UFEN_LSB 30 #define HD_VID_CTL_UFEN_RESET 0x0 #define HD_VID_CTL_ENABLE_BITS 31:31 #define HD_VID_CTL_ENABLE_SET 0x80000000 #define HD_VID_CTL_ENABLE_CLR 0x7fffffff #define HD_VID_CTL_ENABLE_MSB 31 #define HD_VID_CTL_ENABLE_LSB 31 #define HD_VID_CTL_ENABLE_RESET 0x0 #define HD_CSC_CTL HW_REGISTER_RW( 0x7e808040 ) #define HD_CSC_CTL_MASK 0x000000ff #define HD_CSC_CTL_WIDTH 8 #define HD_CSC_CTL_RESET 0000000000 #define HD_CSC_CTL_ENABLE_BITS 0:0 #define HD_CSC_CTL_ENABLE_SET 0x00000001 #define HD_CSC_CTL_ENABLE_CLR 0xfffffffe #define HD_CSC_CTL_ENABLE_MSB 0 #define HD_CSC_CTL_ENABLE_LSB 0 #define HD_CSC_CTL_ENABLE_RESET 0x0 #define HD_CSC_CTL_USERGB2YCC_BITS 1:1 #define HD_CSC_CTL_USERGB2YCC_SET 0x00000002 #define HD_CSC_CTL_USERGB2YCC_CLR 0xfffffffd #define HD_CSC_CTL_USERGB2YCC_MSB 1 #define HD_CSC_CTL_USERGB2YCC_LSB 1 #define HD_CSC_CTL_USERGB2YCC_RESET 0x0 #define HD_CSC_CTL_MODE_BITS 3:2 #define HD_CSC_CTL_MODE_SET 0x0000000c #define HD_CSC_CTL_MODE_CLR 0xfffffff3 #define HD_CSC_CTL_MODE_MSB 3 #define HD_CSC_CTL_MODE_LSB 2 #define HD_CSC_CTL_MODE_RESET 0x0 #define HD_CSC_CTL_PADMSB_BITS 4:4 #define HD_CSC_CTL_PADMSB_SET 0x00000010 #define HD_CSC_CTL_PADMSB_CLR 0xffffffef #define HD_CSC_CTL_PADMSB_MSB 4 #define HD_CSC_CTL_PADMSB_LSB 4 #define HD_CSC_CTL_PADMSB_RESET 0x0 #define HD_CSC_CTL_COLORD_BITS 7:5 #define HD_CSC_CTL_COLORD_SET 0x000000e0 #define HD_CSC_CTL_COLORD_CLR 0xffffff1f #define HD_CSC_CTL_COLORD_MSB 7 #define HD_CSC_CTL_COLORD_LSB 5 #define HD_CSC_CTL_COLORD_RESET 0x0 #define HD_CSC_12_11 HW_REGISTER_RW( 0x7e808044 ) #define HD_CSC_12_11_MASK 0xffffffff #define HD_CSC_12_11_WIDTH 32 #define HD_CSC_12_11_RESET 0000000000 #define HD_CSC_14_13 HW_REGISTER_RW( 0x7e808048 ) #define HD_CSC_14_13_MASK 0xffffffff #define HD_CSC_14_13_WIDTH 32 #define HD_CSC_14_13_RESET 0000000000 #define HD_CSC_22_21 HW_REGISTER_RW( 0x7e80804c ) #define HD_CSC_22_21_MASK 0xffffffff #define HD_CSC_22_21_WIDTH 32 #define HD_CSC_22_21_RESET 0000000000 #define HD_CSC_24_23 HW_REGISTER_RW( 0x7e808050 ) #define HD_CSC_24_23_MASK 0xffffffff #define HD_CSC_24_23_WIDTH 32 #define HD_CSC_24_23_RESET 0000000000 #define HD_CSC_32_31 HW_REGISTER_RW( 0x7e808054 ) #define HD_CSC_32_31_MASK 0xffffffff #define HD_CSC_32_31_WIDTH 32 #define HD_CSC_32_31_RESET 0000000000 #define HD_CSC_34_33 HW_REGISTER_RW( 0x7e808058 ) #define HD_CSC_34_33_MASK 0xffffffff #define HD_CSC_34_33_WIDTH 32 #define HD_CSC_34_33_RESET 0000000000 #define HD_FRAME_CNT HW_REGISTER_RW( 0x7e808068 ) #define HD_FRAME_CNT_MASK 0xffffffff #define HD_FRAME_CNT_WIDTH 32 #define HD_FRAME_CNT_RESET 0000000000