// This file was generated by the create_regs script #define AVE_IN_BASE 0x7e910000 #define AVE_IN_APB_ID 0x61766530 #define AVE_IN_CTRL HW_REGISTER_RW( 0x7e910000 ) #define AVE_IN_CTRL_MASK 0x87ffffff #define AVE_IN_CTRL_WIDTH 32 #define AVE_IN_CTRL_RESET 0x08000080 #define AVE_IN_CTRL_ENABLE_BITS 31:31 #define AVE_IN_CTRL_ENABLE_SET 0x80000000 #define AVE_IN_CTRL_ENABLE_CLR 0x7fffffff #define AVE_IN_CTRL_ENABLE_MSB 31 #define AVE_IN_CTRL_ENABLE_LSB 31 #define AVE_IN_CTRL_PRIORITY_LIMIT_BITS 26:24 #define AVE_IN_CTRL_PRIORITY_LIMIT_SET 0x07000000 #define AVE_IN_CTRL_PRIORITY_LIMIT_CLR 0xf8ffffff #define AVE_IN_CTRL_PRIORITY_LIMIT_MSB 26 #define AVE_IN_CTRL_PRIORITY_LIMIT_LSB 24 #define AVE_IN_CTRL_HIGH_PRIORITY_BITS 23:20 #define AVE_IN_CTRL_HIGH_PRIORITY_SET 0x00f00000 #define AVE_IN_CTRL_HIGH_PRIORITY_CLR 0xff0fffff #define AVE_IN_CTRL_HIGH_PRIORITY_MSB 23 #define AVE_IN_CTRL_HIGH_PRIORITY_LSB 20 #define AVE_IN_CTRL_LOW_PRIORITY_BITS 19:16 #define AVE_IN_CTRL_LOW_PRIORITY_SET 0x000f0000 #define AVE_IN_CTRL_LOW_PRIORITY_CLR 0xfff0ffff #define AVE_IN_CTRL_LOW_PRIORITY_MSB 19 #define AVE_IN_CTRL_LOW_PRIORITY_LSB 16 #define AVE_IN_CTRL_EN_OVERRUN_ABORT_BITS 15:15 #define AVE_IN_CTRL_EN_OVERRUN_ABORT_SET 0x00008000 #define AVE_IN_CTRL_EN_OVERRUN_ABORT_CLR 0xffff7fff #define AVE_IN_CTRL_EN_OVERRUN_ABORT_MSB 15 #define AVE_IN_CTRL_EN_OVERRUN_ABORT_LSB 15 #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_BITS 14:14 #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_SET 0x00004000 #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_CLR 0xffffbfff #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_MSB 14 #define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_LSB 14 #define AVE_IN_CTRL_BYTE_ORDER_BITS 13:11 #define AVE_IN_CTRL_BYTE_ORDER_SET 0x00003800 #define AVE_IN_CTRL_BYTE_ORDER_CLR 0xffffc7ff #define AVE_IN_CTRL_BYTE_ORDER_MSB 13 #define AVE_IN_CTRL_BYTE_ORDER_LSB 11 #define AVE_IN_CTRL_FRAME_MODE_BITS 10:9 #define AVE_IN_CTRL_FRAME_MODE_SET 0x00000600 #define AVE_IN_CTRL_FRAME_MODE_CLR 0xfffff9ff #define AVE_IN_CTRL_FRAME_MODE_MSB 10 #define AVE_IN_CTRL_FRAME_MODE_LSB 9 #define AVE_IN_CTRL_LENGTH_IN_PXLS_BITS 8:8 #define AVE_IN_CTRL_LENGTH_IN_PXLS_SET 0x00000100 #define AVE_IN_CTRL_LENGTH_IN_PXLS_CLR 0xfffffeff #define AVE_IN_CTRL_LENGTH_IN_PXLS_MSB 8 #define AVE_IN_CTRL_LENGTH_IN_PXLS_LSB 8 #define AVE_IN_CTRL_PRIV_MODE_BITS 7:7 #define AVE_IN_CTRL_PRIV_MODE_SET 0x00000080 #define AVE_IN_CTRL_PRIV_MODE_CLR 0xffffff7f #define AVE_IN_CTRL_PRIV_MODE_MSB 7 #define AVE_IN_CTRL_PRIV_MODE_LSB 7 #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_BITS 6:6 #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_SET 0x00000040 #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_CLR 0xffffffbf #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_MSB 6 #define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_LSB 6 #define AVE_IN_CTRL_HSYNC_IRQ_EN_BITS 5:5 #define AVE_IN_CTRL_HSYNC_IRQ_EN_SET 0x00000020 #define AVE_IN_CTRL_HSYNC_IRQ_EN_CLR 0xffffffdf #define AVE_IN_CTRL_HSYNC_IRQ_EN_MSB 5 #define AVE_IN_CTRL_HSYNC_IRQ_EN_LSB 5 #define AVE_IN_CTRL_LINE_IRQ_EN_BITS 4:4 #define AVE_IN_CTRL_LINE_IRQ_EN_SET 0x00000010 #define AVE_IN_CTRL_LINE_IRQ_EN_CLR 0xffffffef #define AVE_IN_CTRL_LINE_IRQ_EN_MSB 4 #define AVE_IN_CTRL_LINE_IRQ_EN_LSB 4 #define AVE_IN_CTRL_BUF_SER_IRQ_EN_BITS 3:3 #define AVE_IN_CTRL_BUF_SER_IRQ_EN_SET 0x00000008 #define AVE_IN_CTRL_BUF_SER_IRQ_EN_CLR 0xfffffff7 #define AVE_IN_CTRL_BUF_SER_IRQ_EN_MSB 3 #define AVE_IN_CTRL_BUF_SER_IRQ_EN_LSB 3 #define AVE_IN_CTRL_BUF1_IRQ_EN_BITS 2:2 #define AVE_IN_CTRL_BUF1_IRQ_EN_SET 0x00000004 #define AVE_IN_CTRL_BUF1_IRQ_EN_CLR 0xfffffffb #define AVE_IN_CTRL_BUF1_IRQ_EN_MSB 2 #define AVE_IN_CTRL_BUF1_IRQ_EN_LSB 2 #define AVE_IN_CTRL_BUF0_IRQ_EN_BITS 1:1 #define AVE_IN_CTRL_BUF0_IRQ_EN_SET 0x00000002 #define AVE_IN_CTRL_BUF0_IRQ_EN_CLR 0xfffffffd #define AVE_IN_CTRL_BUF0_IRQ_EN_MSB 1 #define AVE_IN_CTRL_BUF0_IRQ_EN_LSB 1 #define AVE_IN_CTRL_OVERRUN_IRQ_EN_BITS 0:0 #define AVE_IN_CTRL_OVERRUN_IRQ_EN_SET 0x00000001 #define AVE_IN_CTRL_OVERRUN_IRQ_EN_CLR 0xfffffffe #define AVE_IN_CTRL_OVERRUN_IRQ_EN_MSB 0 #define AVE_IN_CTRL_OVERRUN_IRQ_EN_LSB 0 #define AVE_IN_STATUS HW_REGISTER_RW( 0x7e910004 ) #define AVE_IN_STATUS_MASK 0x9f733f7f #define AVE_IN_STATUS_WIDTH 32 #define AVE_IN_STATUS_RESET 0000000000 #define AVE_IN_STATUS_CAPTURING_BITS 31:31 #define AVE_IN_STATUS_CAPTURING_SET 0x80000000 #define AVE_IN_STATUS_CAPTURING_CLR 0x7fffffff #define AVE_IN_STATUS_CAPTURING_MSB 31 #define AVE_IN_STATUS_CAPTURING_LSB 31 #define AVE_IN_STATUS_OVERRUN_CNT_BITS 28:24 #define AVE_IN_STATUS_OVERRUN_CNT_SET 0x1f000000 #define AVE_IN_STATUS_OVERRUN_CNT_CLR 0xe0ffffff #define AVE_IN_STATUS_OVERRUN_CNT_MSB 28 #define AVE_IN_STATUS_OVERRUN_CNT_LSB 24 #define AVE_IN_STATUS_AXI_STATE_BITS 22:20 #define AVE_IN_STATUS_AXI_STATE_SET 0x00700000 #define AVE_IN_STATUS_AXI_STATE_CLR 0xff8fffff #define AVE_IN_STATUS_AXI_STATE_MSB 22 #define AVE_IN_STATUS_AXI_STATE_LSB 20 #define AVE_IN_STATUS_CURRENT_BUF_BITS 17:17 #define AVE_IN_STATUS_CURRENT_BUF_SET 0x00020000 #define AVE_IN_STATUS_CURRENT_BUF_CLR 0xfffdffff #define AVE_IN_STATUS_CURRENT_BUF_MSB 17 #define AVE_IN_STATUS_CURRENT_BUF_LSB 17 #define AVE_IN_STATUS_MAX_HIT_BITS 16:16 #define AVE_IN_STATUS_MAX_HIT_SET 0x00010000 #define AVE_IN_STATUS_MAX_HIT_CLR 0xfffeffff #define AVE_IN_STATUS_MAX_HIT_MSB 16 #define AVE_IN_STATUS_MAX_HIT_LSB 16 #define AVE_IN_STATUS_CSYNC_FIELD_BITS 13:13 #define AVE_IN_STATUS_CSYNC_FIELD_SET 0x00002000 #define AVE_IN_STATUS_CSYNC_FIELD_CLR 0xffffdfff #define AVE_IN_STATUS_CSYNC_FIELD_MSB 13 #define AVE_IN_STATUS_CSYNC_FIELD_LSB 13 #define AVE_IN_STATUS_VFORM_FIELD_BITS 12:12 #define AVE_IN_STATUS_VFORM_FIELD_SET 0x00001000 #define AVE_IN_STATUS_VFORM_FIELD_CLR 0xffffefff #define AVE_IN_STATUS_VFORM_FIELD_MSB 12 #define AVE_IN_STATUS_VFORM_FIELD_LSB 12 #define AVE_IN_STATUS_EVEN_FIELD_BITS 11:11 #define AVE_IN_STATUS_EVEN_FIELD_SET 0x00000800 #define AVE_IN_STATUS_EVEN_FIELD_CLR 0xfffff7ff #define AVE_IN_STATUS_EVEN_FIELD_MSB 11 #define AVE_IN_STATUS_EVEN_FIELD_LSB 11 #define AVE_IN_STATUS_INTERLACED_BITS 10:10 #define AVE_IN_STATUS_INTERLACED_SET 0x00000400 #define AVE_IN_STATUS_INTERLACED_CLR 0xfffffbff #define AVE_IN_STATUS_INTERLACED_MSB 10 #define AVE_IN_STATUS_INTERLACED_LSB 10 #define AVE_IN_STATUS_FRAME_RATE_BITS 9:8 #define AVE_IN_STATUS_FRAME_RATE_SET 0x00000300 #define AVE_IN_STATUS_FRAME_RATE_CLR 0xfffffcff #define AVE_IN_STATUS_FRAME_RATE_MSB 9 #define AVE_IN_STATUS_FRAME_RATE_LSB 8 #define AVE_IN_STATUS_FRAME_RATE_DET_BITS 6:6 #define AVE_IN_STATUS_FRAME_RATE_DET_SET 0x00000040 #define AVE_IN_STATUS_FRAME_RATE_DET_CLR 0xffffffbf #define AVE_IN_STATUS_FRAME_RATE_DET_MSB 6 #define AVE_IN_STATUS_FRAME_RATE_DET_LSB 6 #define AVE_IN_STATUS_HSYNC_DET_BITS 5:5 #define AVE_IN_STATUS_HSYNC_DET_SET 0x00000020 #define AVE_IN_STATUS_HSYNC_DET_CLR 0xffffffdf #define AVE_IN_STATUS_HSYNC_DET_MSB 5 #define AVE_IN_STATUS_HSYNC_DET_LSB 5 #define AVE_IN_STATUS_LINE_NUM_HIT_BITS 4:4 #define AVE_IN_STATUS_LINE_NUM_HIT_SET 0x00000010 #define AVE_IN_STATUS_LINE_NUM_HIT_CLR 0xffffffef #define AVE_IN_STATUS_LINE_NUM_HIT_MSB 4 #define AVE_IN_STATUS_LINE_NUM_HIT_LSB 4 #define AVE_IN_STATUS_BUF_NOT_SERV_BITS 3:3 #define AVE_IN_STATUS_BUF_NOT_SERV_SET 0x00000008 #define AVE_IN_STATUS_BUF_NOT_SERV_CLR 0xfffffff7 #define AVE_IN_STATUS_BUF_NOT_SERV_MSB 3 #define AVE_IN_STATUS_BUF_NOT_SERV_LSB 3 #define AVE_IN_STATUS_BUF1_COMPL_BITS 2:2 #define AVE_IN_STATUS_BUF1_COMPL_SET 0x00000004 #define AVE_IN_STATUS_BUF1_COMPL_CLR 0xfffffffb #define AVE_IN_STATUS_BUF1_COMPL_MSB 2 #define AVE_IN_STATUS_BUF1_COMPL_LSB 2 #define AVE_IN_STATUS_BUF0_COMPL_BITS 1:1 #define AVE_IN_STATUS_BUF0_COMPL_SET 0x00000002 #define AVE_IN_STATUS_BUF0_COMPL_CLR 0xfffffffd #define AVE_IN_STATUS_BUF0_COMPL_MSB 1 #define AVE_IN_STATUS_BUF0_COMPL_LSB 1 #define AVE_IN_STATUS_OVERRUN_DET_BITS 0:0 #define AVE_IN_STATUS_OVERRUN_DET_SET 0x00000001 #define AVE_IN_STATUS_OVERRUN_DET_CLR 0xfffffffe #define AVE_IN_STATUS_OVERRUN_DET_MSB 0 #define AVE_IN_STATUS_OVERRUN_DET_LSB 0 #define AVE_IN_BUF0_ADDRESS HW_REGISTER_RW( 0x7e910008 ) #define AVE_IN_BUF0_ADDRESS_MASK 0xffffffff #define AVE_IN_BUF0_ADDRESS_WIDTH 32 #define AVE_IN_BUF0_ADDRESS_RESET 0000000000 #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_BITS 31:0 #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_SET 0xffffffff #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_CLR 0x00000000 #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_MSB 31 #define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_LSB 0 #define AVE_IN_BUF1_ADDRESS HW_REGISTER_RW( 0x7e91000c ) #define AVE_IN_BUF1_ADDRESS_MASK 0xffffffff #define AVE_IN_BUF1_ADDRESS_WIDTH 32 #define AVE_IN_BUF1_ADDRESS_RESET 0000000000 #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_BITS 31:0 #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_SET 0xffffffff #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_CLR 0x00000000 #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_MSB 31 #define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_LSB 0 #define AVE_IN_MAX_TRANSFER HW_REGISTER_RW( 0x7e910010 ) #define AVE_IN_MAX_TRANSFER_MASK 0xffffffff #define AVE_IN_MAX_TRANSFER_WIDTH 32 #define AVE_IN_MAX_TRANSFER_RESET 0000000000 #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_BITS 31:0 #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_SET 0xffffffff #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_CLR 0x00000000 #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_MSB 31 #define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_LSB 0 #define AVE_IN_LINE_LENGTH HW_REGISTER_RW( 0x7e910014 ) #define AVE_IN_LINE_LENGTH_MASK 0x00000fff #define AVE_IN_LINE_LENGTH_WIDTH 12 #define AVE_IN_LINE_LENGTH_RESET 0000000000 #define AVE_IN_LINE_LENGTH_LINE_LENGTH_BITS 11:0 #define AVE_IN_LINE_LENGTH_LINE_LENGTH_SET 0x00000fff #define AVE_IN_LINE_LENGTH_LINE_LENGTH_CLR 0xfffff000 #define AVE_IN_LINE_LENGTH_LINE_LENGTH_MSB 11 #define AVE_IN_LINE_LENGTH_LINE_LENGTH_LSB 0 #define AVE_IN_CURRENT_ADDRESS HW_REGISTER_RW( 0x7e910018 ) #define AVE_IN_CURRENT_ADDRESS_MASK 0xffffffff #define AVE_IN_CURRENT_ADDRESS_WIDTH 32 #define AVE_IN_CURRENT_ADDRESS_RESET 0000000000 #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_BITS 31:0 #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_SET 0xffffffff #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_CLR 0x00000000 #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_MSB 31 #define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_LSB 0 #define AVE_IN_CURRENT_LINE_BUF0 HW_REGISTER_RW( 0x7e91001c ) #define AVE_IN_CURRENT_LINE_BUF0_MASK 0x80000fff #define AVE_IN_CURRENT_LINE_BUF0_WIDTH 32 #define AVE_IN_CURRENT_LINE_BUF0_RESET 0000000000 #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_BITS 11:0 #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_SET 0x00000fff #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_CLR 0xfffff000 #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_MSB 11 #define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_LSB 0 #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_BITS 31:31 #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_SET 0x80000000 #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_CLR 0x7fffffff #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_MSB 31 #define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_LSB 31 #define AVE_IN_CURRENT_LINE_BUF1 HW_REGISTER_RW( 0x7e910020 ) #define AVE_IN_CURRENT_LINE_BUF1_MASK 0x80000fff #define AVE_IN_CURRENT_LINE_BUF1_WIDTH 32 #define AVE_IN_CURRENT_LINE_BUF1_RESET 0000000000 #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_BITS 11:0 #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_SET 0x00000fff #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_CLR 0xfffff000 #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_MSB 11 #define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_LSB 0 #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_BITS 31:31 #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_SET 0x80000000 #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_CLR 0x7fffffff #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_MSB 31 #define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_LSB 31 #define AVE_IN_CURRENT_LINE_NUM HW_REGISTER_RW( 0x7e910024 ) #define AVE_IN_CURRENT_LINE_NUM_MASK 0xe0000fff #define AVE_IN_CURRENT_LINE_NUM_WIDTH 32 #define AVE_IN_CURRENT_LINE_NUM_RESET 0000000000 #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_BITS 11:0 #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_SET 0x00000fff #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_CLR 0xfffff000 #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_MSB 11 #define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_LSB 0 #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_BITS 29:29 #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_SET 0x20000000 #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_CLR 0xdfffffff #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_MSB 29 #define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_LSB 29 #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_BITS 30:30 #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_SET 0x40000000 #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_CLR 0xbfffffff #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_MSB 30 #define AVE_IN_CURRENT_LINE_NUM_INTERLACED_LSB 30 #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_BITS 31:31 #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_SET 0x80000000 #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_CLR 0x7fffffff #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_MSB 31 #define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_LSB 31 #define AVE_IN_OVERRUN_ADDRESS HW_REGISTER_RW( 0x7e910028 ) #define AVE_IN_OVERRUN_ADDRESS_MASK 0xffffffff #define AVE_IN_OVERRUN_ADDRESS_WIDTH 32 #define AVE_IN_OVERRUN_ADDRESS_RESET 0000000000 #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_BITS 31:0 #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_SET 0xffffffff #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_CLR 0x00000000 #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_MSB 31 #define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_LSB 0 #define AVE_IN_LINE_NUM_INT HW_REGISTER_RW( 0x7e91002c ) #define AVE_IN_LINE_NUM_INT_MASK 0x00000fff #define AVE_IN_LINE_NUM_INT_WIDTH 12 #define AVE_IN_LINE_NUM_INT_RESET 0000000000 #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_BITS 11:0 #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_SET 0x00000fff #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_CLR 0xfffff000 #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_MSB 11 #define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_LSB 0 #define AVE_IN_CALC_LINE_STEP HW_REGISTER_RW( 0x7e910030 ) #define AVE_IN_CALC_LINE_STEP_MASK 0x00000fff #define AVE_IN_CALC_LINE_STEP_WIDTH 12 #define AVE_IN_CALC_LINE_STEP_RESET 0000000000 #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_BITS 11:0 #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_SET 0x00000fff #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_CLR 0xfffff000 #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_MSB 11 #define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_LSB 0 #define AVE_IN_OUTSTANDING_BUFF0 HW_REGISTER_RW( 0x7e910034 ) #define AVE_IN_OUTSTANDING_BUFF0_MASK 0x000000ff #define AVE_IN_OUTSTANDING_BUFF0_WIDTH 8 #define AVE_IN_OUTSTANDING_BUFF0_RESET 0000000000 #define AVE_IN_OUTSTANDING_BUFF1 HW_REGISTER_RW( 0x7e910038 ) #define AVE_IN_OUTSTANDING_BUFF1_MASK 0x000000ff #define AVE_IN_OUTSTANDING_BUFF1_WIDTH 8 #define AVE_IN_OUTSTANDING_BUFF1_RESET 0000000000 #define AVE_IN_CHAR_CTRL HW_REGISTER_RW( 0x7e91003c ) #define AVE_IN_CHAR_CTRL_MASK 0x8000000f #define AVE_IN_CHAR_CTRL_WIDTH 32 #define AVE_IN_CHAR_CTRL_RESET 0000000000 #define AVE_IN_SYNC_CTRL HW_REGISTER_RW( 0x7e910040 ) #define AVE_IN_SYNC_CTRL_MASK 0x0000008f #define AVE_IN_SYNC_CTRL_WIDTH 8 #define AVE_IN_SYNC_CTRL_RESET 0000000000 #define AVE_IN_FRAME_NUM HW_REGISTER_RW( 0x7e910044 ) #define AVE_IN_FRAME_NUM_MASK 0x00000fff #define AVE_IN_FRAME_NUM_WIDTH 12 #define AVE_IN_FRAME_NUM_RESET 0000000000 #define AVE_IN_FRAME_NUM_FRAME_NUM_BITS 11:0 #define AVE_IN_FRAME_NUM_FRAME_NUM_SET 0x00000fff #define AVE_IN_FRAME_NUM_FRAME_NUM_CLR 0xfffff000 #define AVE_IN_FRAME_NUM_FRAME_NUM_MSB 11 #define AVE_IN_FRAME_NUM_FRAME_NUM_LSB 0 #define AVE_IN_BLOCK_ID HW_REGISTER_RW( 0x7e910060 ) #define AVE_IN_BLOCK_ID_MASK 0xffffffff #define AVE_IN_BLOCK_ID_WIDTH 32 #define AVE_IN_BLOCK_ID_RESET 0x61766530