// This file was generated by the create_regs script
#define SPI_BASE                                                 0x7e204000
#define SPI_CS                                                   HW_REGISTER_RW( 0x7e204000 ) 
   #define SPI_CS_MASK                                           0x001f07ff
   #define SPI_CS_WIDTH                                          21
   #define SPI_CS_RESET                                          0000000000
      #define SPI_CS_RXF_BITS                                    20:20
      #define SPI_CS_RXF_SET                                     0x00100000
      #define SPI_CS_RXF_CLR                                     0xffefffff
      #define SPI_CS_RXF_MSB                                     20
      #define SPI_CS_RXF_LSB                                     20
      #define SPI_CS_RXR_BITS                                    19:19
      #define SPI_CS_RXR_SET                                     0x00080000
      #define SPI_CS_RXR_CLR                                     0xfff7ffff
      #define SPI_CS_RXR_MSB                                     19
      #define SPI_CS_RXR_LSB                                     19
      #define SPI_CS_TXD_BITS                                    18:18
      #define SPI_CS_TXD_SET                                     0x00040000
      #define SPI_CS_TXD_CLR                                     0xfffbffff
      #define SPI_CS_TXD_MSB                                     18
      #define SPI_CS_TXD_LSB                                     18
      #define SPI_CS_RXD_BITS                                    17:17
      #define SPI_CS_RXD_SET                                     0x00020000
      #define SPI_CS_RXD_CLR                                     0xfffdffff
      #define SPI_CS_RXD_MSB                                     17
      #define SPI_CS_RXD_LSB                                     17
      #define SPI_CS_DONE_BITS                                   16:16
      #define SPI_CS_DONE_SET                                    0x00010000
      #define SPI_CS_DONE_CLR                                    0xfffeffff
      #define SPI_CS_DONE_MSB                                    16
      #define SPI_CS_DONE_LSB                                    16
      #define SPI_CS_INTR_BITS                                   10:10
      #define SPI_CS_INTR_SET                                    0x00000400
      #define SPI_CS_INTR_CLR                                    0xfffffbff
      #define SPI_CS_INTR_MSB                                    10
      #define SPI_CS_INTR_LSB                                    10
      #define SPI_CS_INTD_BITS                                   9:9
      #define SPI_CS_INTD_SET                                    0x00000200
      #define SPI_CS_INTD_CLR                                    0xfffffdff
      #define SPI_CS_INTD_MSB                                    9
      #define SPI_CS_INTD_LSB                                    9
      #define SPI_CS_DMAEN_BITS                                  8:8
      #define SPI_CS_DMAEN_SET                                   0x00000100
      #define SPI_CS_DMAEN_CLR                                   0xfffffeff
      #define SPI_CS_DMAEN_MSB                                   8
      #define SPI_CS_DMAEN_LSB                                   8
      #define SPI_CS_TA_BITS                                     7:7
      #define SPI_CS_TA_SET                                      0x00000080
      #define SPI_CS_TA_CLR                                      0xffffff7f
      #define SPI_CS_TA_MSB                                      7
      #define SPI_CS_TA_LSB                                      7
      #define SPI_CS_CSPOL_BITS                                  6:6
      #define SPI_CS_CSPOL_SET                                   0x00000040
      #define SPI_CS_CSPOL_CLR                                   0xffffffbf
      #define SPI_CS_CSPOL_MSB                                   6
      #define SPI_CS_CSPOL_LSB                                   6
      #define SPI_CS_CLEAR_BITS                                  5:4
      #define SPI_CS_CLEAR_SET                                   0x00000030
      #define SPI_CS_CLEAR_CLR                                   0xffffffcf
      #define SPI_CS_CLEAR_MSB                                   5
      #define SPI_CS_CLEAR_LSB                                   4
      #define SPI_CS_CPOL_BITS                                   3:3
      #define SPI_CS_CPOL_SET                                    0x00000008
      #define SPI_CS_CPOL_CLR                                    0xfffffff7
      #define SPI_CS_CPOL_MSB                                    3
      #define SPI_CS_CPOL_LSB                                    3
      #define SPI_CS_CPHA_BITS                                   2:2
      #define SPI_CS_CPHA_SET                                    0x00000004
      #define SPI_CS_CPHA_CLR                                    0xfffffffb
      #define SPI_CS_CPHA_MSB                                    2
      #define SPI_CS_CPHA_LSB                                    2
#define SPI_FIFO                                                 HW_REGISTER_RW( 0x7e204004 ) 
   #define SPI_FIFO_MASK                                         0x000000ff
   #define SPI_FIFO_WIDTH                                        8
   #define SPI_FIFO_RESET                                        0000000000
      #define SPI_FIFO_DATA_BITS                                 7:0
      #define SPI_FIFO_DATA_SET                                  0x000000ff
      #define SPI_FIFO_DATA_CLR                                  0xffffff00
      #define SPI_FIFO_DATA_MSB                                  7
      #define SPI_FIFO_DATA_LSB                                  0
#define SPI_CLK                                                  HW_REGISTER_RW( 0x7e204008 ) 
   #define SPI_CLK_MASK                                          0x0000ffff
   #define SPI_CLK_WIDTH                                         16
   #define SPI_CLK_RESET                                         0000000000
      #define SPI_CLK_CDIV_BITS                                  15:0
      #define SPI_CLK_CDIV_SET                                   0x0000ffff
      #define SPI_CLK_CDIV_CLR                                   0xffff0000
      #define SPI_CLK_CDIV_MSB                                   15
      #define SPI_CLK_CDIV_LSB                                   0
#define SPI_DLEN                                                 HW_REGISTER_RW( 0x7e20400c ) 
   #define SPI_DLEN_MASK                                         0x0000ffff
   #define SPI_DLEN_WIDTH                                        16
   #define SPI_DLEN_RESET                                        0000000000
      #define SPI_DLEN_LEN_BITS                                  15:0
      #define SPI_DLEN_LEN_SET                                   0x0000ffff
      #define SPI_DLEN_LEN_CLR                                   0xffff0000
      #define SPI_DLEN_LEN_MSB                                   15
      #define SPI_DLEN_LEN_LSB                                   0
#define SPI_LTOH                                                 HW_REGISTER_RW( 0x7e204010 ) 
   #define SPI_LTOH_MASK                                         0x0000000f
   #define SPI_LTOH_WIDTH                                        4
   #define SPI_LTOH_RESET                                        0x00000001
      #define SPI_LTOH_TOH_BITS                                  3:0
      #define SPI_LTOH_TOH_SET                                   0x0000000f
      #define SPI_LTOH_TOH_CLR                                   0xfffffff0
      #define SPI_LTOH_TOH_MSB                                   3
      #define SPI_LTOH_TOH_LSB                                   0