#define FPGA_A0_BASE 0x7e213000 #define FPGA_B0_BASE 0x7e214000 #define FPGA_CTRL0_OFFSET 0x08 #define FPGA_STATUS0_OFFSET 0x0C // This file was generated by the create_regs script #define FPGA_BASE 0x7e20b600 #define FPGA_APB_ID 0x66706761 #define FPGA_VERSION HW_REGISTER_RO( 0x7e20b600 ) #define FPGA_VERSION_MASK 0xffffffff #define FPGA_VERSION_WIDTH 32 #define FPGA_SCRATCH HW_REGISTER_RW( 0x7e20b604 ) #define FPGA_SCRATCH_MASK 0xffffffff #define FPGA_SCRATCH_WIDTH 32 #define FPGA_CTRL0 HW_REGISTER_RW( 0x7e20b608 ) #define FPGA_CTRL0_MASK 0xfffff3fff #define FPGA_CTRL0_WIDTH 36 #define FPGA_CTRL0_SPARE_OUT_BITS 31:20 #define FPGA_CTRL0_SPARE_OUT_SET 0xfff00000 #define FPGA_CTRL0_SPARE_OUT_CLR 0x000fffff #define FPGA_CTRL0_SPARE_OUT_MSB 31 #define FPGA_CTRL0_SPARE_OUT_LSB 20 #define FPGA_CTRL0_LV_SPARE_OUT_BITS 19:18 #define FPGA_CTRL0_LV_SPARE_OUT_SET 0x000c0000 #define FPGA_CTRL0_LV_SPARE_OUT_CLR 0xfff3ffff #define FPGA_CTRL0_LV_SPARE_OUT_MSB 19 #define FPGA_CTRL0_LV_SPARE_OUT_LSB 18 #define FPGA_CTRL0_TERMEN_CLK_BITS 17:17 #define FPGA_CTRL0_TERMEN_CLK_SET 0x00020000 #define FPGA_CTRL0_TERMEN_CLK_CLR 0xfffdffff #define FPGA_CTRL0_TERMEN_CLK_MSB 17 #define FPGA_CTRL0_TERMEN_CLK_LSB 17 #define FPGA_CTRL0_TERMEN_DO_BITS 16:16 #define FPGA_CTRL0_TERMEN_DO_SET 0x00010000 #define FPGA_CTRL0_TERMEN_DO_CLR 0xfffeffff #define FPGA_CTRL0_TERMEN_DO_MSB 16 #define FPGA_CTRL0_TERMEN_DO_LSB 16 #define FPGA_CTRL0_TV_ACTIVITY_BITS 13:13 #define FPGA_CTRL0_TV_ACTIVITY_SET 0x00002000 #define FPGA_CTRL0_TV_ACTIVITY_CLR 0xffffdfff #define FPGA_CTRL0_TV_ACTIVITY_MSB 13 #define FPGA_CTRL0_TV_ACTIVITY_LSB 13 #define FPGA_CTRL0_SPI0_SEL_B_BITS 12:12 #define FPGA_CTRL0_SPI0_SEL_B_SET 0x00001000 #define FPGA_CTRL0_SPI0_SEL_B_CLR 0xffffefff #define FPGA_CTRL0_SPI0_SEL_B_MSB 12 #define FPGA_CTRL0_SPI0_SEL_B_LSB 12 #define FPGA_CTRL0_DISP_BUFFER_BITS 11:11 #define FPGA_CTRL0_DISP_BUFFER_SET 0x00000800 #define FPGA_CTRL0_DISP_BUFFER_CLR 0xfffff7ff #define FPGA_CTRL0_DISP_BUFFER_MSB 11 #define FPGA_CTRL0_DISP_BUFFER_LSB 11 #define FPGA_CTRL0_SPI1_SEL_BITS 10:10 #define FPGA_CTRL0_SPI1_SEL_SET 0x00000400 #define FPGA_CTRL0_SPI1_SEL_CLR 0xfffffbff #define FPGA_CTRL0_SPI1_SEL_MSB 10 #define FPGA_CTRL0_SPI1_SEL_LSB 10 #define FPGA_CTRL0_SPI0_SEL_A_BITS 9:9 #define FPGA_CTRL0_SPI0_SEL_A_SET 0x00000200 #define FPGA_CTRL0_SPI0_SEL_A_CLR 0xfffffdff #define FPGA_CTRL0_SPI0_SEL_A_MSB 9 #define FPGA_CTRL0_SPI0_SEL_A_LSB 9 #define FPGA_CTRL0_SW_SPI_CS_BITS 8:8 #define FPGA_CTRL0_SW_SPI_CS_SET 0x00000100 #define FPGA_CTRL0_SW_SPI_CS_CLR 0xfffffeff #define FPGA_CTRL0_SW_SPI_CS_MSB 8 #define FPGA_CTRL0_SW_SPI_CS_LSB 8 #define FPGA_CTRL0_SW_SPI_SDA_O_BITS 7:7 #define FPGA_CTRL0_SW_SPI_SDA_O_SET 0x00000080 #define FPGA_CTRL0_SW_SPI_SDA_O_CLR 0xffffff7f #define FPGA_CTRL0_SW_SPI_SDA_O_MSB 7 #define FPGA_CTRL0_SW_SPI_SDA_O_LSB 7 #define FPGA_CTRL0_SW_SPI_SCL_BITS 6:6 #define FPGA_CTRL0_SW_SPI_SCL_SET 0x00000040 #define FPGA_CTRL0_SW_SPI_SCL_CLR 0xffffffbf #define FPGA_CTRL0_SW_SPI_SCL_MSB 6 #define FPGA_CTRL0_SW_SPI_SCL_LSB 6 #define FPGA_CTRL0_DIS_SW_SPI_BITS 5:5 #define FPGA_CTRL0_DIS_SW_SPI_SET 0x00000020 #define FPGA_CTRL0_DIS_SW_SPI_CLR 0xffffffdf #define FPGA_CTRL0_DIS_SW_SPI_MSB 5 #define FPGA_CTRL0_DIS_SW_SPI_LSB 5 #define FPGA_CTRL0_SD_PSU_EN_BITS 4:4 #define FPGA_CTRL0_SD_PSU_EN_SET 0x00000010 #define FPGA_CTRL0_SD_PSU_EN_CLR 0xffffffef #define FPGA_CTRL0_SD_PSU_EN_MSB 4 #define FPGA_CTRL0_SD_PSU_EN_LSB 4 #define FPGA_CTRL0_DIS_RST_BITS 3:3 #define FPGA_CTRL0_DIS_RST_SET 0x00000008 #define FPGA_CTRL0_DIS_RST_CLR 0xfffffff7 #define FPGA_CTRL0_DIS_RST_MSB 3 #define FPGA_CTRL0_DIS_RST_LSB 3 #define FPGA_CTRL0_DIS_CTL2_BITS 2:2 #define FPGA_CTRL0_DIS_CTL2_SET 0x00000004 #define FPGA_CTRL0_DIS_CTL2_CLR 0xfffffffb #define FPGA_CTRL0_DIS_CTL2_MSB 2 #define FPGA_CTRL0_DIS_CTL2_LSB 2 #define FPGA_CTRL0_DIS_BL_BITS 1:1 #define FPGA_CTRL0_DIS_BL_SET 0x00000002 #define FPGA_CTRL0_DIS_BL_CLR 0xfffffffd #define FPGA_CTRL0_DIS_BL_MSB 1 #define FPGA_CTRL0_DIS_BL_LSB 1 #define FPGA_CTRL0_DIS_CTL0_BITS 0:0 #define FPGA_CTRL0_DIS_CTL0_SET 0x00000001 #define FPGA_CTRL0_DIS_CTL0_CLR 0xfffffffe #define FPGA_CTRL0_DIS_CTL0_MSB 0 #define FPGA_CTRL0_DIS_CTL0_LSB 0 #define FPGA_CTRL0_CAM_CTL2_BITS 2:2 #define FPGA_CTRL0_CAM_CTL2_SET 0x00000004 #define FPGA_CTRL0_CAM_CTL2_CLR 0xfffffffb #define FPGA_CTRL0_CAM_CTL2_MSB 2 #define FPGA_CTRL0_CAM_CTL2_LSB 2 #define FPGA_CTRL0_CAM_CTL1_BITS 1:1 #define FPGA_CTRL0_CAM_CTL1_SET 0x00000002 #define FPGA_CTRL0_CAM_CTL1_CLR 0xfffffffd #define FPGA_CTRL0_CAM_CTL1_MSB 1 #define FPGA_CTRL0_CAM_CTL1_LSB 1 #define FPGA_CTRL0_CAM_CTL0_BITS 0:0 #define FPGA_CTRL0_CAM_CTL0_SET 0x00000001 #define FPGA_CTRL0_CAM_CTL0_CLR 0xfffffffe #define FPGA_CTRL0_CAM_CTL0_MSB 0 #define FPGA_CTRL0_CAM_CTL0_LSB 0 #define FPGA_STATUS0 HW_REGISTER_RO( 0x7e20b60c ) #define FPGA_STATUS0_MASK 0xfff800ff #define FPGA_STATUS0_WIDTH 32 #define FPGA_STATUS0_SPARE_IN_BITS 31:19 #define FPGA_STATUS0_SPARE_IN_SET 0xfff80000 #define FPGA_STATUS0_SPARE_IN_CLR 0x0007ffff #define FPGA_STATUS0_SPARE_IN_MSB 31 #define FPGA_STATUS0_SPARE_IN_LSB 19 #define FPGA_STATUS0_SW_SPI_SPI_IN_BITS 7:7 #define FPGA_STATUS0_SW_SPI_SPI_IN_SET 0x00000080 #define FPGA_STATUS0_SW_SPI_SPI_IN_CLR 0xffffff7f #define FPGA_STATUS0_SW_SPI_SPI_IN_MSB 7 #define FPGA_STATUS0_SW_SPI_SPI_IN_LSB 7 #define FPGA_STATUS0_NAND_RNB_BITS 6:6 #define FPGA_STATUS0_NAND_RNB_SET 0x00000040 #define FPGA_STATUS0_NAND_RNB_CLR 0xffffffbf #define FPGA_STATUS0_NAND_RNB_MSB 6 #define FPGA_STATUS0_NAND_RNB_LSB 6 #define FPGA_STATUS0_SD_CD_BITS 5:5 #define FPGA_STATUS0_SD_CD_SET 0x00000020 #define FPGA_STATUS0_SD_CD_CLR 0xffffffdf #define FPGA_STATUS0_SD_CD_MSB 5 #define FPGA_STATUS0_SD_CD_LSB 5 #define FPGA_STATUS0_SD_WP_BITS 4:4 #define FPGA_STATUS0_SD_WP_SET 0x00000010 #define FPGA_STATUS0_SD_WP_CLR 0xffffffef #define FPGA_STATUS0_SD_WP_MSB 4 #define FPGA_STATUS0_SD_WP_LSB 4 #define FPGA_STATUS0_HW_ID_BITS 3:0 #define FPGA_STATUS0_HW_ID_SET 0x0000000f #define FPGA_STATUS0_HW_ID_CLR 0xfffffff0 #define FPGA_STATUS0_HW_ID_MSB 3 #define FPGA_STATUS0_HW_ID_LSB 0 #define FPGA_DCM_WR_DATA HW_REGISTER_RW( 0x7e20b610 ) #define FPGA_DCM_WR_DATA_MASK 0x00ffffff #define FPGA_DCM_WR_DATA_WIDTH 24 #define FPGA_DCM_WR_DATA_ADDRESS_BITS 23:16 #define FPGA_DCM_WR_DATA_ADDRESS_SET 0x00ff0000 #define FPGA_DCM_WR_DATA_ADDRESS_CLR 0xff00ffff #define FPGA_DCM_WR_DATA_ADDRESS_MSB 23 #define FPGA_DCM_WR_DATA_ADDRESS_LSB 16 #define FPGA_DCM_WR_DATA_DATA_BITS 15:0 #define FPGA_DCM_WR_DATA_DATA_SET 0x0000ffff #define FPGA_DCM_WR_DATA_DATA_CLR 0xffff0000 #define FPGA_DCM_WR_DATA_DATA_MSB 15 #define FPGA_DCM_WR_DATA_DATA_LSB 0 #define FPGA_DCM_CTRL HW_REGISTER_RW( 0x7e20b614 ) #define FPGA_DCM_CTRL_MASK 0xff0fffff #define FPGA_DCM_CTRL_WIDTH 32 #define FPGA_DCM_CTRL_PERI_WR_EN_BITS 31:28 #define FPGA_DCM_CTRL_PERI_WR_EN_SET 0xf0000000 #define FPGA_DCM_CTRL_PERI_WR_EN_CLR 0x0fffffff #define FPGA_DCM_CTRL_PERI_WR_EN_MSB 31 #define FPGA_DCM_CTRL_PERI_WR_EN_LSB 28 #define FPGA_DCM_CTRL_PERI_EN_BITS 27:24 #define FPGA_DCM_CTRL_PERI_EN_SET 0x0f000000 #define FPGA_DCM_CTRL_PERI_EN_CLR 0xf0ffffff #define FPGA_DCM_CTRL_PERI_EN_MSB 27 #define FPGA_DCM_CTRL_PERI_EN_LSB 24 #define FPGA_DCM_CTRL_PERI_RST_BITS 19:16 #define FPGA_DCM_CTRL_PERI_RST_SET 0x000f0000 #define FPGA_DCM_CTRL_PERI_RST_CLR 0xfff0ffff #define FPGA_DCM_CTRL_PERI_RST_MSB 19 #define FPGA_DCM_CTRL_PERI_RST_LSB 16 #define FPGA_DCM_CTRL_REMOTE_EN_BITS 12:8 #define FPGA_DCM_CTRL_REMOTE_EN_SET 0x00001f00 #define FPGA_DCM_CTRL_REMOTE_EN_CLR 0xffffe0ff #define FPGA_DCM_CTRL_REMOTE_EN_MSB 12 #define FPGA_DCM_CTRL_REMOTE_EN_LSB 8 #define FPGA_DCM_CTRL_REMOTE_RST_BITS 4:0 #define FPGA_DCM_CTRL_REMOTE_RST_SET 0x0000001f #define FPGA_DCM_CTRL_REMOTE_RST_CLR 0xffffffe0 #define FPGA_DCM_CTRL_REMOTE_RST_MSB 4 #define FPGA_DCM_CTRL_REMOTE_RST_LSB 0 #define FPGA_DCM_RD_DATA HW_REGISTER_RO( 0x7e20b618 ) #define FPGA_DCM_RD_DATA_MASK 0x0000ffff #define FPGA_DCM_RD_DATA_WIDTH 16 #define FPGA_DCM_RD_DATA_DATA_BITS 15:0 #define FPGA_DCM_RD_DATA_DATA_SET 0x0000ffff #define FPGA_DCM_RD_DATA_DATA_CLR 0xffff0000 #define FPGA_DCM_RD_DATA_DATA_MSB 15 #define FPGA_DCM_RD_DATA_DATA_LSB 0