192 lines
4.0 KiB
ArmAsm
Executable File
192 lines
4.0 KiB
ArmAsm
Executable File
/*=============================================================================
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Copyright (C) 2016 Kristina Brooks
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All rights reserved.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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FILE DESCRIPTION
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Entry.
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A small explanation. The ROM loads bootcode.bin at 0x80000000 and jumps to
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0x80000200. This region corresponds to L1/L2 cached IO and cache is never
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evicted as long as we don't touch memory above that. This gives us 128KB
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of memory at startup.
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Exception names are from the public release from:
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brcm_usrlib\dag\vmcsx\vcfw\rtos\none\rtos_none.c
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=============================================================================*/
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.text
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empty_space:
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.space 0x200
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.include "ghetto.s"
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/* main entry point */
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.globl _start
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.align 2
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_start:
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mov r0, cpuid
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mov r5, r0
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/* vectors */
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mov r3, #0x1B000
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mov r1, r3
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/*
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* populate the exception vector table using PC relative labels
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* so the code isnt position dependent
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*/
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.macro RegExceptionHandler label, exception_number
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lea r2, fleh_\label
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st r2, (r1)
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add r1, #4
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.endm
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RegExceptionHandler zero, #0
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RegExceptionHandler misaligned, #1
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RegExceptionHandler dividebyzero, #2
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RegExceptionHandler undefinedinstruction, #3
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RegExceptionHandler forbiddeninstruction, #4
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RegExceptionHandler illegalmemory, #5
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RegExceptionHandler buserror, #6
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RegExceptionHandler floatingpoint, #7
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RegExceptionHandler isp, #8
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RegExceptionHandler dummy, #9
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RegExceptionHandler icache, #10
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RegExceptionHandler veccore, #11
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RegExceptionHandler badl2alias, #12
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RegExceptionHandler breakpoint, #13
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RegExceptionHandler unknown, #14
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add r1, r3, #252
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lea r2, fleh_irq
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mov r4, #492
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L_setup_hw_irq:
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st r2, (r1)++
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ble r1, r4, L_setup_hw_irq
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/*
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* load the interrupt and normal stack pointers. these
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* are chosen to be near the top of the available cache memory
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*/
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mov r28, #0x1D000
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mov sp, #0x1C000
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/* set interrupt vector bases */
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mov r0, #IC0_VADDR
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st r3, (r0)
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mov r0, #IC1_VADDR
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st r3, (r0)
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/* jump to C code */
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mov r0, r5
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lea r1, _start
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ei
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bl _main
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/************************************************************
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* Debug
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************************************************************/
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blinker:
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mov r1, #GPFSEL1
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ld r0, (r1)
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and r0, #(~(7<<18))
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or r0, #(1<<18)
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st r0, (r1)
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mov r1, #GPSET0
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mov r2, #GPCLR0
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mov r3, #(1<<16)
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loop:
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st r3, (r1)
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mov r0, #0
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delayloop1:
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add r0, #1
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cmp r0, #0x100000
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bne delayloop1
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st r3, (r2)
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mov r0, #0
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delayloop2:
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add r0, #1
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cmp r0, #0x100000
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bne delayloop2
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b loop
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/************************************************************
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* Exception Handling
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************************************************************/
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.macro SaveRegsLower
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push r0-r5, lr
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.endm
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.macro SaveRegsUpper
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push r6-r15
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push r16-r23
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.endm
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.macro SaveRegsAll
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SaveRegsLower
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SaveRegsUpper
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.endm
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fatal_exception:
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SaveRegsUpper
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mov r0, sp
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b sleh_fatal
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.macro ExceptionHandler label, exception_number
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fleh_\label:
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SaveRegsLower
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mov r1, \exception_number
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b fatal_exception
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.endm
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ExceptionHandler zero, #0
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ExceptionHandler misaligned, #1
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ExceptionHandler dividebyzero, #2
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ExceptionHandler undefinedinstruction, #3
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ExceptionHandler forbiddeninstruction, #4
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ExceptionHandler illegalmemory, #5
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ExceptionHandler buserror, #6
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ExceptionHandler floatingpoint, #7
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ExceptionHandler isp, #8
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ExceptionHandler dummy, #9
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ExceptionHandler icache, #10
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ExceptionHandler veccore, #11
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ExceptionHandler badl2alias, #12
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ExceptionHandler breakpoint, #13
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ExceptionHandler unknown, #14
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fleh_irq:
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SaveRegsAll
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/* top of savearea */
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mov r0, sp
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bl sleh_irq
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return_from_exception:
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pop r16-r23
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pop r6-r15
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pop r0-r15
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ld lr, (sp)++
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rti
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