suzanne.soy/fpgatools
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

worked on directional wires

Browse Source
This commit is contained in:
Wolfgang Spraul 2012-10-30 15:12:32 +01:00
parent 97f03a312c
commit 25bb28cfd4
4 changed files with 525 additions and 564 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
libs/model.h
View File

@ -218,20 +218,23 @@ enum fpga_tile_type
#define TF_WIRED 0x00008000
#define TF_CENTER_MIDBUF 0x00010000
#define Y_INNER_TOP 0x0001
#define Y_INNER_BOTTOM 0x0002
#define Y_CHIP_HORIZ_REGS 0x0004
#define Y_ROW_HORIZ_AXSYMM 0x0008
#define Y_BOTTOM_OF_ROW 0x0010
#define Y_LEFT_WIRED 0x0020
#define Y_RIGHT_WIRED 0x0040
#define Y_OUTER_TOP 0x0001
#define Y_INNER_TOP 0x0002
#define Y_INNER_BOTTOM 0x0004
#define Y_OUTER_BOTTOM 0x0008
#define Y_CHIP_HORIZ_REGS 0x0010
#define Y_ROW_HORIZ_AXSYMM 0x0020
#define Y_BOTTOM_OF_ROW 0x0040
#define Y_LEFT_WIRED 0x0080
#define Y_RIGHT_WIRED 0x0100
// Y_TOPBOT_IO_RANGE checks if y points to the top or bottom outer or
// inner rows.
#define Y_TOPBOT_IO_RANGE 0x0080
#define Y_TOP_OUTER_IO 0x0100
#define Y_TOP_INNER_IO 0x0200
#define Y_BOT_INNER_IO 0x0400
#define Y_BOT_OUTER_IO 0x0800
// inner rows. todo: same as TOP_OUTER|TOP_INNER|BOT_INNER|BOT_OUTER?
#define Y_TOPBOT_IO_RANGE 0x0200
#define Y_TOP_OUTER_IO 0x0400
#define Y_TOP_INNER_IO 0x0800
#define Y_BOT_INNER_IO 0x1000
#define Y_BOT_OUTER_IO 0x2000
#define Y_REGULAR_ROW 0x4000
// multiple checks are combined with OR logic
int is_aty(int check, struct fpga_model* model, int y);
@ -299,6 +302,7 @@ int is_atx(int check, struct fpga_model* model, int x);
#define YX_DEV_LOGIC 0x0020
#define YX_DEV_IOB 0x0040
#define YX_CENTER_MIDBUF 0x0080
#define YX_OUTER_TERM 0x0100
int is_atyx(int check, struct fpga_model* model, int y, int x);
@ -311,6 +315,8 @@ void is_in_row(const struct fpga_model* model, int y,
// which_row() and pos_in_row() return -1 if y is outside of a row
int which_row(int y, struct fpga_model* model);
int pos_in_row(int y, struct fpga_model* model);
// regular_row_pos() returns the index (0..15) without hclk, or -1 if y is a hclk.
int regular_row_pos(int y, struct fpga_model* model);
const char* logicin_s(int wire, int routing_io);
@ -844,8 +850,7 @@ struct w_net
{
// if !last_inc, no incrementing will happen (NO_INCREMENT)
// if last_inc > 0, incrementing will happen to
// the %i in the name from 0:last_inc, for a total
// of last_inc+1 wires.
// the %i in the name from pt.start_count:last_inc
int last_inc;
int num_pts;
struct w_point pt[40];

1009
libs/model_conns.c
View File

File diff suppressed because it is too large Load Diff

42
libs/model_helper.c
View File

@ -290,34 +290,40 @@ xout:
return rc;
}
int add_conn_uni_pref(struct fpga_model* model, int y1, int x1, const char* name1, int y2, int x2, const char* name2)
int add_conn_uni_pref(struct fpga_model* model,
int y1, int x1, const char* name1,
int y2, int x2, const char* name2)
{
return add_conn_uni(model,
y1, x1, wpref(model, y1, x1, name1),
y2, x2, wpref(model, y2, x2, name2));
}
int add_conn_bi(struct fpga_model* model, int y1, int x1, const char* name1, int y2, int x2, const char* name2)
int add_conn_bi(struct fpga_model* model,
int y1, int x1, const char* name1,
int y2, int x2, const char* name2)
{
int rc = add_conn_uni(model, y1, x1, name1, y2, x2, name2);
if (rc) return rc;
return add_conn_uni(model, y2, x2, name2, y1, x1, name1);
}
int add_conn_bi_pref(struct fpga_model* model, int y1, int x1, const char* name1, int y2, int x2, const char* name2)
int add_conn_bi_pref(struct fpga_model* model,
int y1, int x1, const char* name1,
int y2, int x2, const char* name2)
{
return add_conn_bi(model,
y1, x1, wpref(model, y1, x1, name1),
y2, x2, wpref(model, y2, x2, name2));
}
int add_conn_range(struct fpga_model* model, add_conn_f add_conn_func, int y1, int x1, const char* name1, int start1, int last1, int y2, int x2, const char* name2, int start2)
int add_conn_range(struct fpga_model* model, add_conn_f add_conn_func,
int y1, int x1, const char* name1, int start1, int last1,
int y2, int x2, const char* name2, int start2)
{
char buf1[128], buf2[128];
int rc, i;
if (last1 <= start1)
return (*add_conn_func)(model, y1, x1, name1, y2, x2, name2);
for (i = start1; i <= last1; i++) {
snprintf(buf1, sizeof(buf1), name1, i);
if (start2 & COUNT_DOWN)
@ -337,6 +343,13 @@ int add_conn_net(struct fpga_model* model, add_conn_f add_conn_func, const struc
if (net->num_pts < 2) FAIL(EINVAL);
for (i = 0; i < net->num_pts; i++) {
for (j = i+1; j < net->num_pts; j++) {
// We are buildings nets like a NN2 B-M-E net where
// we add the _S0 wire at the end, at the same x/y
// coordinate as the M point. Here we skip such
// connections back to the start tile.
if (net->pt[j].y == net->pt[i].y
&& net->pt[j].x == net->pt[i].x)
continue;
rc = add_conn_range(model, add_conn_func,
net->pt[i].y, net->pt[i].x,
net->pt[i].name,
@ -542,14 +555,17 @@ char last_major(const char* str, int cur_o)
int is_aty(int check, struct fpga_model* model, int y)
{
if (y < 0) return 0;
if (check & Y_OUTER_TOP && y == TOP_OUTER_ROW) return 1;
if (check & Y_INNER_TOP && y == TOP_INNER_ROW) return 1;
if (check & Y_INNER_BOTTOM && y == model->y_height-BOT_INNER_ROW) return 1;
if (check & Y_OUTER_BOTTOM && y == model->y_height-BOT_OUTER_ROW) return 1;
if (check & Y_CHIP_HORIZ_REGS && y == model->center_y) return 1;
if (check & (Y_ROW_HORIZ_AXSYMM|Y_BOTTOM_OF_ROW)) {
if (check & (Y_ROW_HORIZ_AXSYMM|Y_BOTTOM_OF_ROW|Y_REGULAR_ROW)) {
int row_pos;
is_in_row(model, y, 0 /* row_num */, &row_pos);
if (check & Y_ROW_HORIZ_AXSYMM && row_pos == 8) return 1;
if (check & Y_BOTTOM_OF_ROW && row_pos == 16) return 1;
if (check & Y_REGULAR_ROW && ((row_pos >= 0 && row_pos < 8) || (row_pos > 8 && row_pos <= 16))) return 1;
}
if (check & Y_LEFT_WIRED && model->tiles[y*model->x_width].flags & TF_WIRED) return 1;
if (check & Y_RIGHT_WIRED && model->tiles[y*model->x_width + model->x_width-RIGHT_OUTER_O].flags & TF_WIRED) return 1;
@ -615,6 +631,7 @@ int is_atyx(int check, struct fpga_model* model, int y, int x)
struct fpga_tile* tile;
if (y < 0 || x < 0) return 0;
// todo: YX_ROUTING_TILE could be implemented using X_ROUTING_COL and Y_REGULAR_ROW ?
if (check & YX_ROUTING_TILE
&& (model->tiles[x].flags & TF_FABRIC_ROUTING_COL
|| x == LEFT_IO_ROUTING || x == model->x_width-5
@ -634,6 +651,9 @@ int is_atyx(int check, struct fpga_model* model, int y, int x)
if (check & YX_DEV_LOGIC && has_device(model, y, x, DEV_LOGIC)) return 1;
if (check & YX_DEV_IOB && has_device(model, y, x, DEV_IOB)) return 1;
if (check & YX_CENTER_MIDBUF && tile->flags & TF_CENTER_MIDBUF) return 1;
if (check & YX_OUTER_TERM
&& (is_atx(X_OUTER_LEFT|X_OUTER_RIGHT, model, x)
|| is_aty(Y_OUTER_TOP|Y_OUTER_BOTTOM, model, y))) return 1;
return 0;
}
@ -675,6 +695,14 @@ int pos_in_row(int y, struct fpga_model* model)
return result;
}
int regular_row_pos(int y, struct fpga_model* model)
{
int row_pos = pos_in_row(y, model);
if (row_pos == -1 || row_pos == HCLK_POS) return -1;
if (row_pos > HCLK_POS) row_pos--;
return row_pos;
}
const char* logicin_s(int wire, int routing_io)
{
if (routing_io && ((wire & LWF_WIRE_MASK) == X_A5 || (wire & LWF_WIRE_MASK) == X_B4))

3
libs/model_switches.c
View File

@ -1002,7 +1002,8 @@ const char* wire_base(enum wire_type w)
case W_WW4: return "WW4";
case W_NW4: return "NW4";
}
EXIT(1);
HERE();
return "";
}
enum wire_type base2wire(const char* str)