finished logicout switches
This commit is contained in:
Wolfgang Spraul
parent
8ffb4e2143
commit
4c21d2a9c7
147
model.c
147
model.c
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@ -371,7 +371,7 @@ int add_switches(struct set_of_switches* dest,
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}
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if (beg_wire == W_WL1) {
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add_switch_range(dest, end_wire,
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2, 1, beg_wire, 0);
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2, 3, beg_wire, 0);
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sprintf(dest->s[dest->num_s].from, "%sE_S0",
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end_wire_s);
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sprintf(dest->s[dest->num_s].to, "%sB2",
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@ -572,7 +572,7 @@ xout:
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#define LWF_WIRE_MASK 0x0FF // namespace for the enum
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#define LWF_UNDEF 0xFF
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enum logic_wire {
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enum logicin_wire {
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X_A1 = 0,
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X_A2, X_A3, X_A4, X_A5, X_A6, X_AX,
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X_B1, X_B2, X_B3, X_B4, X_B5, X_B6, X_BX,
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@ -585,6 +585,110 @@ enum logic_wire {
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M_WE
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};
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enum logicout_wire {
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X_A = 0,
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X_AMUX, X_AQ, X_B, X_BMUX, X_BQ,
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X_C, X_CMUX, X_CQ, X_D, X_DMUX, X_DQ,
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M_A, M_AMUX, M_AQ, M_B, M_BMUX, M_BQ,
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M_C, M_CMUX, M_CQ, M_D, M_DMUX, M_DQ
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};
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int add_logicout_switches(struct fpga_model* model, int y, int x)
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{
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// 8 groups of 3. The order inside the group does not matter,
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// but the order of the groups does.
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static int out_wires[] = {
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/* group 0 */ M_A, M_CMUX, X_AQ,
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/* group 1 */ M_AQ, X_A, X_CMUX,
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/* group 2 */ M_BQ, X_B, X_DMUX,
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/* group 3 */ M_B, M_DMUX, X_BQ,
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/* group 4 */ M_AMUX, M_C, X_CQ,
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/* group 5 */ M_CQ, X_AMUX, X_C,
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/* group 6 */ M_BMUX, M_D, X_DQ,
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/* group 7 */ M_DQ, X_BMUX, X_D
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};
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// Those are the logicout wires going back into logicin, for
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// each group of out wires. Again the order inside the groups
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// does not matter, but the group order must match the out wire
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// group order.
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static int logicin_wires[] = {
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/* group 0 */ M_AI, M_B6, M_C1, M_D3, X_A6, X_AX, X_B1, X_C3,
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/* group 1 */ M_A6, M_AX, M_B2, M_C3, M_WE, X_B6, X_C2, X_D3,
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/* group 2 */ M_A2, M_B5, M_BI, M_BX, M_D4, X_A5, X_C4, X_D2,
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/* group 3 */ M_A5, M_C4, M_D1, X_A1, X_B5, X_BX, X_CE, X_D4,
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/* group 4 */ M_A1, M_B4, M_CE, M_D5, X_A4, X_C5, X_CX, X_D1,
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/* group 5 */ M_A4, M_C5, M_CI, M_CX, M_D2, X_A2, X_B4, X_D5,
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/* group 6 */ M_A3, M_B1, M_C6, M_DI, X_B3, X_C1, X_D6, X_DX,
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/* group 7 */ M_B3, M_C2, M_D6, M_DX, X_A3, X_B2, X_C6 /*FAN_B*/
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};
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enum wire_type wire;
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char from_str[16], to_str[16];
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int i, j, rc;
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for (i = 0; i < sizeof(out_wires)/sizeof(out_wires[0]); i++) {
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// out to dirwires
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snprintf(from_str, sizeof(from_str), "LOGICOUT%i",
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out_wires[i]);
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wire = W_NN2;
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do {
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// len 2
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snprintf(to_str, sizeof(to_str), "%sB%i",
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wire_base(wire), i/(2*3));
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rc = add_switch(model, y, x, from_str, to_str,
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0 /* bidir */);
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if (rc) goto xout;
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// len 4
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snprintf(to_str, sizeof(to_str), "%sB%i",
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wire_base(W_TO_LEN4(wire)), i/(2*3));
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rc = add_switch(model, y, x, from_str, to_str,
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0 /* bidir */);
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if (rc) goto xout;
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wire = W_CLOCKWISE(wire);
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} while (wire != W_NN2); // one full turn
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// NR1, SL1
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snprintf(to_str, sizeof(to_str), "NR1B%i", i/(2*3));
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rc = add_switch(model, y, x, from_str, to_str, 0 /* bidir */);
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if (rc) goto xout;
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snprintf(to_str, sizeof(to_str), "SL1B%i", i/(2*3));
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rc = add_switch(model, y, x, from_str, to_str, 0 /* bidir */);
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if (rc) goto xout;
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// ER1, SR1, WR1 (+1)
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// NL1, EL1, WL1 (+3)
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{
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static const char* plus1[] = {"ER1B%i", "SR1B%i", "WR1B%i"};
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static const char* plus3[] = {"NL1B%i", "EL1B%i", "WL1B%i"};
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for (j = 0; j < 3; j++) {
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snprintf(to_str, sizeof(to_str), plus1[j], (i/(2*3)+1)%4);
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rc = add_switch(model, y, x, from_str, to_str, 0 /* bidir */);
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if (rc) goto xout;
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snprintf(to_str, sizeof(to_str), plus3[j], (i/(2*3)+3)%4);
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rc = add_switch(model, y, x, from_str, to_str, 0 /* bidir */);
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if (rc) goto xout;
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}
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}
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// back to logicin
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for (j = 0; j < 8; j++) {
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if ((i/3) == 7 && j == 7) // FAN_B
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strcpy(to_str, "FAN_B");
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else
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snprintf(to_str, sizeof(to_str), "LOGICIN_B%i",
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logicin_wires[(i/3)*8 + j]);
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rc = add_switch(model, y, x, from_str, to_str,
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0 /* bidir */);
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if (rc) goto xout;
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}
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}
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return 0;
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xout:
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return rc;
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}
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int add_logicin_switch(struct fpga_model* model, int y, int x,
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enum wire_type dirwire, int dirwire_num,
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int logicin_num)
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@ -732,15 +836,10 @@ xout:
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static int init_switches(struct fpga_model* model)
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{
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int x, y, i, rc;
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int x, y, i, j, rc;
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struct set_of_switches dir_EB_switches;
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enum wire_type wire;
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//groups:
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// 1. VCC/GND/KEEP1, GFAN, GCLK, FAN_B
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// 2. dirwires
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// 3. logicin
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// 4. logicout
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for (x = 0; x < model->x_width; x++) {
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if (!is_atx(X_ROUTING_COL, model, x))
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continue;
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@ -750,12 +849,40 @@ static int init_switches(struct fpga_model* model)
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continue;
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if (y != 68 || x != 12) continue;
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rc = add_switch(model, y, x, "LOGICOUT0", "NN2B0", 0 /* bidir */);
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if (rc) goto xout;
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for (i = X_A1; i <= M_WE; i++) {
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rc = add_switch(model, y, x, "KEEP1_WIRE",
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pf("LOGICIN_B%i", i), 0 /* bidir */);
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if (rc) goto xout;
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}
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// GCLK0:15 -> CLK0:1, GFAN0:1/SR0:1
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for (i = 0; i <= 15; i++) {
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for (j = 0; j <= 1; j++) {
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rc = add_switch(model, y, x,
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pf("GCLK%i", i),
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pf("CLK%i", j), 0 /* bidir */);
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if (rc) goto xout;
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rc = add_switch(model, y, x,
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pf("GCLK%i", i),
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(i < 8) ? pf("GFAN%i", j)
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: pf("SR%i", j),
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0 /* bidir */);
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if (rc) goto xout;
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}
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}
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// connecting directional wires endpoints to logicin
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rc = add_logicin_switches(model, y, x);
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if (rc) goto xout;
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// connecting logicout back to directional wires
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// beginning points (and some back to logicin)
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rc = add_logicout_switches(model, y, x);
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if (rc) goto xout;
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// connecting the directional wires from one's end
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// to another one's beginning
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wire = W_NN2;
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do {
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rc = build_dirwire_switches(&dir_EB_switches, W_TO_LEN1(wire));
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