finished logicin switches
This commit is contained in:
Wolfgang Spraul
parent
a3f09f4906
commit
8ffb4e2143
106
model.c
106
model.c
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@ -585,10 +585,6 @@ enum logic_wire {
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M_WE
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};
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// This function adds the switches for all dirwires in the
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// quarter belonging to dirwire. So dirwire should only be
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// one of W_NN2, W_EE2, W_SS2 or W_WW2 - the rest is handled
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// inside the function.
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int add_logicin_switch(struct fpga_model* model, int y, int x,
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enum wire_type dirwire, int dirwire_num,
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int logicin_num)
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@ -596,8 +592,6 @@ int add_logicin_switch(struct fpga_model* model, int y, int x,
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char from_str[16], to_str[16];
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int rc;
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if ((logicin_num & LWF_WIRE_MASK) == LWF_UNDEF) return 0;
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if (dirwire_num == 0 && logicin_num & LWF_SOUTH0)
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snprintf(from_str, sizeof(from_str), "%sE_S0",
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wire_base(dirwire));
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@ -616,6 +610,49 @@ xout:
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return rc;
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}
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// This function adds the switches for all dirwires in the
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// quarter belonging to dirwire. So dirwire should only be
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// one of W_NN2, W_EE2, W_SS2 or W_WW2 - the rest is handled
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// inside the function.
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int add_logicin_switch_quart(struct fpga_model* model, int y, int x,
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enum wire_type dirwire, int dirwire_num,
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int logicin_num)
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{
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enum wire_type len1;
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int rc;
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rc = add_logicin_switch(model, y, x, dirwire, dirwire_num,
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logicin_num);
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if (rc) goto xout;
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len1 = W_COUNTER_CLOCKWISE(W_TO_LEN1(dirwire));
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rc = add_logicin_switch(model, y, x, len1,
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dirwire_num, logicin_num);
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if (rc) goto xout;
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if (dirwire == W_WW2) {
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int nw_num = dirwire_num+1;
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if (nw_num > 3)
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nw_num = 0;
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rc = add_logicin_switch(model, y, x, W_NW2, nw_num,
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logicin_num);
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if (rc) goto xout;
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rc = add_logicin_switch(model, y, x, W_NL1, nw_num,
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logicin_num);
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if (rc) goto xout;
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} else {
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rc = add_logicin_switch(model, y, x, W_CLOCKWISE(dirwire),
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dirwire_num, logicin_num);
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if (rc) goto xout;
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len1 = rotate_wire(len1, 3);
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rc = add_logicin_switch(model, y, x, len1,
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dirwire_num, logicin_num);
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if (rc) goto xout;
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}
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return 0;
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xout:
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return rc;
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}
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static int loop_and_rotate_over_wires(struct fpga_model* model, int y, int x,
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int* wires, int num_wires, int early_decrement)
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{
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@ -631,7 +668,9 @@ static int loop_and_rotate_over_wires(struct fpga_model* model, int y, int x,
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//
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for (i = 0; i < num_wires*4; i++) {
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rc = add_logicin_switch(model, y, x, FIRST_LEN2+(i%4)*2,
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if ((wires[i/4] & LWF_WIRE_MASK) == LWF_UNDEF)
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continue;
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rc = add_logicin_switch_quart(model, y, x, FIRST_LEN2+(i%4)*2,
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3-((i+early_decrement)/4)%4, wires[i/4]);
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if (rc) goto xout;
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}
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@ -642,52 +681,50 @@ xout:
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int add_logicin_switches(struct fpga_model* model, int y, int x)
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{
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static int decrement_at_NN[] =
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{ M_DI, M_CI, X_CE, M_WE,
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int rc;
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{ static int decrement_at_NN[] =
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{ M_DI | LWF_SOUTH0, M_CI, X_CE, M_WE,
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M_B1 | LWF_SOUTH0, X_A2, X_A1, M_B2,
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M_C6, M_C5, M_C4, M_C3,
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X_D6, X_D5, X_D4, X_D3 };
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M_C6 | LWF_SOUTH0, M_C5, M_C4, M_C3,
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X_D6 | LWF_SOUTH0, X_D5, X_D4, X_D3 };
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static int decrement_at_EE[] =
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_NN,
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sizeof(decrement_at_NN)/sizeof(decrement_at_NN[0]),
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0 /* early_decrement */);
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if (rc) goto xout; }
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{ static int decrement_at_EE[] =
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{ M_CX, X_BX, M_AX, X_DX | LWF_SOUTH0,
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M_D2, M_D1, X_C2, X_C1 | LWF_SOUTH0,
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M_A4, M_A5, M_A6, M_A3 | LWF_SOUTH0,
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X_B4, X_B5, X_B6, X_B3 | LWF_SOUTH0 };
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static int decrement_at_SS[] =
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_EE,
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sizeof(decrement_at_EE)/sizeof(decrement_at_EE[0]),
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3 /* early_decrement */);
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if (rc) goto xout; }
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{ static int decrement_at_SS[] =
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{ LWF_UNDEF, M_CE, M_BI, M_AI | LWF_NORTH3,
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X_B2, M_A1, M_A2, X_B1 | LWF_NORTH3,
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X_C6, X_C5, X_C4, X_C3 | LWF_NORTH3,
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M_D6, M_D5, M_D4, M_D3 | LWF_NORTH3 };
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static int decrement_at_WW[] =
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_SS,
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sizeof(decrement_at_SS)/sizeof(decrement_at_SS[0]),
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2 /* early_decrement */);
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if (rc) goto xout; }
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{ static int decrement_at_WW[] =
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{ M_DX, X_CX, M_BX, X_AX | LWF_NORTH3,
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M_C2, X_D1, X_D2, M_C1 | LWF_NORTH3,
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X_A3, X_A4, X_A5, X_A6 | LWF_NORTH3,
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M_B3, M_B4, M_B5, M_B6 | LWF_NORTH3 };
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int rc;
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_NN,
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sizeof(decrement_at_NN)/sizeof(decrement_at_NN[0]),
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0 /* early_decrement */);
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if (rc) goto xout;
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_EE,
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sizeof(decrement_at_EE)/sizeof(decrement_at_EE[0]),
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3 /* early_decrement */);
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if (rc) goto xout;
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_SS,
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sizeof(decrement_at_SS)/sizeof(decrement_at_SS[0]),
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2 /* early_decrement */);
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if (rc) goto xout;
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rc = loop_and_rotate_over_wires(model, y, x, decrement_at_WW,
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sizeof(decrement_at_WW)/sizeof(decrement_at_WW[0]),
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1 /* early_decrement */);
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if (rc) goto xout;
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if (rc) goto xout; }
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return 0;
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xout:
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return rc;
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@ -715,10 +752,10 @@ static int init_switches(struct fpga_model* model)
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if (y != 68 || x != 12) continue;
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rc = add_switch(model, y, x, "LOGICOUT0", "NN2B0", 0 /* bidir */);
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if (rc) goto xout;
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rc = add_logicin_switches(model, y, x);
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if (rc) goto xout;
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#if 0
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wire = W_NN2;
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do {
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rc = build_dirwire_switches(&dir_EB_switches, W_TO_LEN1(wire));
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@ -750,7 +787,6 @@ static int init_switches(struct fpga_model* model)
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wire = W_CLOCKWISE(wire);
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} while (wire != W_NN2); // one full turn
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#endif
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}
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}
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return 0;
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