a few more devices
This commit is contained in:
Wolfgang Spraul
parent
328d3934c2
commit
5b9da5a1f1
138
model.c
138
model.c
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@ -136,6 +136,92 @@ static int init_devices(struct fpga_model* model)
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int x, y, i, j;
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struct fpga_tile* tile;
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// DCM, PLL_ADV
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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tile = YX_TILE(model, y-1, model->center_x-CMTPLL_FROM_CENTER_O);
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if (i%2) {
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tile->devices[tile->num_devices++].type = DEV_DCM;
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tile->devices[tile->num_devices++].type = DEV_DCM;
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} else
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tile->devices[tile->num_devices++].type = DEV_PLL_ADV;
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}
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// BSCAN
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tile = YX_TILE(model, TOP_IO_TILES, model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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// BSCAN, OCT_CALIBRATE
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tile = YX_TILE(model, TOP_IO_TILES+1, model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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tile->devices[tile->num_devices++].type = DEV_BSCAN;
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tile->devices[tile->num_devices++].type = DEV_OCT_CALIBRATE;
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// ICAP, SPI_ACCESS, OCT_CALIBRATE
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tile = YX_TILE(model, model->y_height-BOT_IO_TILES-1,
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model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_ICAP;
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tile->devices[tile->num_devices++].type = DEV_SPI_ACCESS;
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tile->devices[tile->num_devices++].type = DEV_OCT_CALIBRATE;
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// STARTUP, POST_CRC_INTERNAL, SLAVE_SPI, SUSPEND_SYNC
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tile = YX_TILE(model, model->y_height-BOT_IO_TILES-2,
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model->x_width-RIGHT_IO_DEVS_O);
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tile->devices[tile->num_devices++].type = DEV_STARTUP;
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tile->devices[tile->num_devices++].type = DEV_POST_CRC_INTERNAL;
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tile->devices[tile->num_devices++].type = DEV_SLAVE_SPI;
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tile->devices[tile->num_devices++].type = DEV_SUSPEND_SYNC;
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// BUFGMUX
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tile = YX_TILE(model, model->center_y, model->center_x);
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for (i = 0; i < 16; i++)
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tile->devices[tile->num_devices++].type = DEV_BUFGMUX;
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// BUFIO, BUFIO_FB, BUFPLL, BUFPLL_MCB
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tile = YX_TILE(model, TOP_OUTER_ROW, model->center_x-CMTPLL_FROM_CENTER_O);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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tile = YX_TILE(model, model->center_y, LEFT_OUTER_COL);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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tile = YX_TILE(model, model->center_y, model->x_width - RIGHT_OUTER_O);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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tile = YX_TILE(model, model->y_height - BOT_OUTER_ROW, model->center_x-CMTPLL_FROM_CENTER_O);
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL;
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tile->devices[tile->num_devices++].type = DEV_BUFPLL_MCB;
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for (j = 0; j < 8; j++) {
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tile->devices[tile->num_devices++].type = DEV_BUFIO;
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tile->devices[tile->num_devices++].type = DEV_BUFIO_FB;
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}
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// BUFH
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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tile = YX_TILE(model, y, model->center_x);
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for (j = 0; j < 32; j++)
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tile->devices[tile->num_devices++].type = DEV_BUFH;
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}
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// BRAM
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
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@ -513,10 +599,10 @@ static int init_wires(struct fpga_model* model)
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{
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int rc;
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rc = run_gclk(model);
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rc = run_logic_inout(model);
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if (rc) goto xout;
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rc = run_logic_inout(model);
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rc = run_gclk(model);
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if (rc) goto xout;
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rc = run_direction_wires(model);
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@ -1162,7 +1248,7 @@ static int run_logic_inout(struct fpga_model* model)
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}
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}
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}
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if (is_atx(X_FABRIC_BRAM_ROUTING_COL, model, x)) {
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if (is_atx(X_FABRIC_BRAM_ROUTING_COL|X_FABRIC_MACC_ROUTING_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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@ -1174,6 +1260,52 @@ static int run_logic_inout(struct fpga_model* model)
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "BRAM_LOGICOUT%i_INT1", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "BRAM_LOGICOUT%i_INT0", 0))) goto xout;
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}
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if (YX_TILE(model, y, x)[2].flags & TF_MACC_DEV) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-3, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT3", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-2, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT2", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT1", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y, x+2, "MACC_LOGICOUT%i_INT0", 0))) goto xout;
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}
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}
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}
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if (is_atx(X_CENTER_ROUTING_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_ROW_HORIZ_AXSYMM, model, y)) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x, "LOGICOUT%i", 0, 23, y-1, x+1, "INT_INTERFACE_LOGICOUT%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y+1, x, "LOGICOUT%i", 0, 23, y+1, x+1, "INT_INTERFACE_LOGICOUT%i", 0))) goto xout;
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if (YX_TILE(model, y-1, x+2)->flags & TF_DCM_DEV) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "DCM_CLB2_LOGICOUT%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y+1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "DCM_CLB1_LOGICOUT%i", 0))) goto xout;
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} else if (YX_TILE(model, y-1, x+2)->flags & TF_PLL_DEV) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "PLL_CLB2_LOGICOUT%i", 0))) goto xout;
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if ((rc = add_conn_range(model, NOPREF_BI_F, y+1, x+1, "INT_INTERFACE_LOGICOUT_%i", 0, 23, y-1, x+2, "PLL_CLB1_LOGICOUT%i", 0))) goto xout;
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}
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}
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if (is_aty(Y_CHIP_HORIZ_REGS, model, y)) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y-1, x, "LOGICOUT%i", 0, 23, y-1, x+1, "INT_INTERFACE_REGC_LOGICOUT%i", 0))) goto xout;
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}
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}
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}
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if (is_atx(X_LEFT_IO_ROUTING_COL|X_RIGHT_IO_ROUTING_COL, model, x)) {
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int wired_side, local_size;
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if (is_atx(X_LEFT_IO_ROUTING_COL, model, x)) {
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local_size = 1;
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wired_side = Y_LEFT_WIRED;
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} else {
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local_size = 2;
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wired_side = Y_RIGHT_WIRED;
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}
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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continue;
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if (y < TOP_IO_TILES+local_size || y > model->y_height-BOT_IO_TILES-local_size-1) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICOUT%i", 0, 23, y, x+1, "INT_INTERFACE_LOCAL_LOGICOUT%i", 0))) goto xout;
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} else if (is_aty(wired_side, model, y)) {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICOUT%i", 0, 23, y, x+1, "IOI_LOGICOUT%i", 0))) goto xout;
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} else {
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if ((rc = add_conn_range(model, NOPREF_BI_F, y, x, "LOGICOUT%i", 0, 23, y, x+1, "INT_INTERFACE_LOGICOUT%i", 0))) goto xout;
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}
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}
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}
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}
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21
model.h
21
model.h
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@ -138,11 +138,12 @@ enum fpga_tile_type
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#define TOP_IO_TILES 2
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#define TOP_OUTER_ROW 0
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#define TOP_INNER_ROW 1
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#define BOT_IO_TILES 2
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#define HALF_ROW 8
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#define LAST_POS_IN_ROW 16 // including hclk at 8
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#define ROW_SIZE (HALF_ROW+1+HALF_ROW)
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// Some offsets that are being deducted from their origin
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#define BOT_IO_TILES 2
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#define BOT_OUTER_ROW 1
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#define BOT_INNER_ROW 2
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#define RIGHT_OUTER_O 1
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@ -244,7 +245,23 @@ enum fpgadev_type
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DEV_OLOGIC,
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DEV_IODELAY,
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DEV_BRAM16,
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DEV_BRAM8
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DEV_BRAM8,
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DEV_BUFH,
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DEV_BUFIO,
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DEV_BUFIO_FB,
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DEV_BUFPLL,
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DEV_BUFPLL_MCB,
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DEV_BUFGMUX,
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DEV_BSCAN,
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DEV_DCM,
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DEV_PLL_ADV,
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DEV_ICAP,
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DEV_POST_CRC_INTERNAL,
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DEV_STARTUP,
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DEV_SLAVE_SPI,
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DEV_SUSPEND_SYNC,
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DEV_OCT_CALIBRATE,
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DEV_SPI_ACCESS
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};
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struct fpgadev_logic_x
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48
new_fp.c
48
new_fp.c
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@ -158,6 +158,54 @@ int printf_devices(struct fpga_model* model)
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case DEV_BRAM8:
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printf("device y%02i x%02i RAMB8BWER\n", y, x);
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break;
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case DEV_BUFH:
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printf("device y%02i x%02i BUFH\n", y, x);
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break;
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case DEV_BUFIO:
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printf("device y%02i x%02i BUFIO2\n", y, x);
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break;
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case DEV_BUFIO_FB:
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printf("device y%02i x%02i BUFIO2FB\n", y, x);
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break;
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case DEV_BUFPLL:
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printf("device y%02i x%02i BUFPLL\n", y, x);
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break;
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case DEV_BUFPLL_MCB:
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printf("device y%02i x%02i BUFPLL_MCB\n", y, x);
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break;
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case DEV_BUFGMUX:
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printf("device y%02i x%02i BUFGMUX\n", y, x);
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break;
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case DEV_BSCAN:
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printf("device y%02i x%02i BSCAN\n", y, x);
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break;
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case DEV_DCM:
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printf("device y%02i x%02i DCM\n", y, x);
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break;
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case DEV_PLL_ADV:
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printf("device y%02i x%02i PLL_ADV\n", y, x);
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break;
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case DEV_ICAP:
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printf("device y%02i x%02i ICAP\n", y, x);
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break;
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case DEV_POST_CRC_INTERNAL:
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printf("device y%02i x%02i POST_CRC_INTERNAL\n", y, x);
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break;
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case DEV_STARTUP:
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printf("device y%02i x%02i STARTUP\n", y, x);
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break;
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case DEV_SLAVE_SPI:
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printf("device y%02i x%02i SLAVE_SPI\n", y, x);
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break;
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case DEV_SUSPEND_SYNC:
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printf("device y%02i x%02i SUSPEND_SYNC\n", y, x);
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break;
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case DEV_OCT_CALIBRATE:
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printf("device y%02i x%02i OCT_CALIBRATE\n", y, x);
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break;
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case DEV_SPI_ACCESS:
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printf("device y%02i x%02i SPI_ACCESS\n", y, x);
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break;
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}
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}
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}
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