autotest cleanup
This commit is contained in:
Wolfgang Spraul
parent
c17d502359
commit
75a047ac3e
551
autotest.c
551
autotest.c
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@ -21,6 +21,9 @@ time_t g_start_time;
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struct test_state
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{
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int cmdline_skip;
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char cmdline_diff_exec[1024];
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struct fpga_model* model;
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// test filenames are: tmp_dir/autotest_<base_name>_<diff_counter>.???
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char tmp_dir[256];
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@ -63,13 +66,19 @@ static int diff_printf(struct test_state* tstate)
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FILE* dest_f = 0;
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int rc;
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snprintf(path, sizeof(path), "%s/autotest_%s_%04i", tstate->tmp_dir,
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if (tstate->cmdline_skip >= tstate->next_diff_counter) {
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printf("O Skipping diff %i.\n", tstate->next_diff_counter);
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tstate->next_diff_counter++;
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return 0;
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}
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snprintf(path, sizeof(path), "%s/autotest_%s_%06i", tstate->tmp_dir,
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tstate->base_name, tstate->next_diff_counter);
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path_base = strlen(path);
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if (tstate->next_diff_counter == 1)
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if (tstate->next_diff_counter == tstate->cmdline_skip + 1)
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strcpy(prior_fp, "/dev/null");
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else {
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snprintf(prior_fp, sizeof(prior_fp), "%s/autotest_%s_%04i.fp",
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snprintf(prior_fp, sizeof(prior_fp), "%s/autotest_%s_%06i.fp",
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tstate->tmp_dir, tstate->base_name,
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tstate->next_diff_counter-1);
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}
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@ -86,10 +95,14 @@ static int diff_printf(struct test_state* tstate)
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fclose(dest_f);
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dest_f = 0;
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path[path_base] = 0;
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snprintf(tmp, sizeof(tmp), "./autotest_diff.sh %s %s.fp >%s.log 2>&1",
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prior_fp, path, path);
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snprintf(tmp, sizeof(tmp), "%s %s %s.fp >%s.log 2>&1",
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tstate->cmdline_diff_exec, prior_fp, path, path);
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rc = system(tmp);
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if (rc) FAIL(rc);
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if (rc) {
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printf("#E %s:%i system call '%s' failed with code %i, "
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"check %s.log\n", __FILE__, __LINE__, tmp, rc, path);
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// todo: report the error up so we can avoid adding a switch to the block list etc.
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}
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strcpy(&path[path_base], ".diff");
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rc = dump_file(path);
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@ -102,104 +115,8 @@ fail:
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return rc;
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}
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static void cut_sw_from_end(struct fpga_net* net, int cut_o)
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{
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if (cut_o <= 2) return;
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memmove(&net->el[2], &net->el[cut_o],
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(net->len-cut_o)*sizeof(net->el[0]));
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net->len = 2 + net->len-cut_o;
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}
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int test_net(struct test_state* tstate, net_idx_t net_i);
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int test_net(struct test_state* tstate, net_idx_t net_i)
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{
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struct fpga_net* net;
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struct fpga_net copy_net;
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swidx_t same_sw[64];
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int same_len;
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int i, j, rc;
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net = fpga_net_get(tstate->model, net_i);
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if (!net) FAIL(EINVAL);
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copy_net = *net;
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for (i = net->len-1; i >= 2; i--) {
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printf("round i %i\n", i);
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*net = copy_net;
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cut_sw_from_end(net, i);
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if (net->len <= 2) {
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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continue;
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}
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// what other switches go to SW_TO(el[2])?
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printf_swchain(tstate->model,
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net->el[2].y, net->el[2].x,
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fpga_switch_str_i(tstate->model,
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net->el[2].y, net->el[2].x,
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net->el[2].idx, SW_TO),
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SW_TO, 1, 0, 0);
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same_len = sizeof(same_sw)/sizeof(*same_sw);
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rc = fpga_switch_same_fromto(tstate->model,
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net->el[2].y, net->el[2].x,
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net->el[2].idx, SW_TO, same_sw, &same_len);
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if (rc) FAIL(rc);
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printf("same_len at this level %i\n", same_len);
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for (j = 0; j < same_len; j++) {
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net->el[2].idx = same_sw[j];
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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}
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}
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return 0;
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fail:
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return rc;
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}
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int test_net2(struct test_state* tstate, net_idx_t net_i);
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int test_net2(struct test_state* tstate, net_idx_t net_i)
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{
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struct fpga_net* net;
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struct fpga_net copy_net;
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swidx_t same_sw[64];
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int same_len;
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int i, j, rc;
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net = fpga_net_get(tstate->model, net_i);
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if (!net) FAIL(EINVAL);
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copy_net = *net;
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for (i = 3; i <= net->len-1; i++) {
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printf("round i %i\n", i);
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net->len = i;
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// what other switches go from SW_FROM(el[i-1])?
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printf_swchain(tstate->model,
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net->el[i-1].y, net->el[i-1].x,
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fpga_switch_str_i(tstate->model,
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net->el[i-1].y, net->el[i-1].x,
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net->el[i-1].idx, SW_FROM),
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SW_FROM, 1, 0, 0);
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same_len = sizeof(same_sw)/sizeof(*same_sw);
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rc = fpga_switch_same_fromto(tstate->model,
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net->el[i-1].y, net->el[i-1].x,
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net->el[i-1].idx, SW_FROM, same_sw, &same_len);
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if (rc) FAIL(rc);
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printf("same_len at this level %i\n", same_len);
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for (j = 0; j < same_len; j++) {
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net->el[i-1].idx = same_sw[j];
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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}
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*net = copy_net;
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}
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return 0;
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fail:
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return rc;
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}
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// goal: configure logic devices in all supported variations
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int test_logic_config(struct test_state* tstate);
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int test_logic_config(struct test_state* tstate)
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static int test_logic_config(struct test_state* tstate)
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{
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int a_to_d[] = { A6_LUT, B6_LUT, C6_LUT, D6_LUT };
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int idx_enum[] = { DEV_LOGM, DEV_LOGX };
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@ -227,82 +144,15 @@ fail:
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return rc;
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}
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static int test_device_fingers(struct test_state* tstate, int y, int x,
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int type, int type_idx, swidx_t* block_list, int* block_list_len)
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{
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struct fpga_device* dev;
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struct switch_to_yx switch_to;
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struct sw_chain chain;
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net_idx_t net_idx;
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int i, from_to, rc;
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rc = fdev_set_required_pins(tstate->model, y, x, type, type_idx);
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if (rc) FAIL(rc);
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// fdev_print_required_pins(tstate->model, y, x, type, type_idx);
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dev = fdev_p(tstate->model, y, x, type, type_idx);
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if (!dev) FAIL(EINVAL);
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for (i = 0; i < dev->pinw_req_total; i++) {
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from_to = (i < dev->pinw_req_in) ? SW_TO : SW_FROM;
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switch_to.yx_req = YX_ROUTING_TILE;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = tstate->model;
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switch_to.y = y;
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switch_to.x = x;
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switch_to.start_switch = dev->pinw[dev->pinw_req_for_cfg[i]];
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switch_to.from_to = from_to;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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// printf_switch_to_result(&switch_to);
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rc = construct_sw_chain(&chain, tstate->model, switch_to.dest_y,
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switch_to.dest_x, switch_to.dest_connpt, from_to,
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/*max_depth*/ 1, block_list, *block_list_len);
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if (rc) FAIL(rc);
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while (fpga_switch_chain(&chain) != NO_SWITCH) {
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rc = fpga_net_new(tstate->model, &net_idx);
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if (rc) FAIL(rc);
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// add port
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rc = fpga_net_add_port(tstate->model, net_idx,
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y, x, fpga_dev_idx(tstate->model, y, x,
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type, type_idx), dev->pinw_req_for_cfg[i]);
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if (rc) FAIL(rc);
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// add (one) switch in logic tile
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rc = fpga_net_add_switches(tstate->model, net_idx,
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y, x, &switch_to.set);
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if (rc) FAIL(rc);
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// add switches in routing tile
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rc = fpga_net_add_switches(tstate->model, net_idx,
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switch_to.dest_y, switch_to.dest_x, &chain.set);
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if (rc) FAIL(rc);
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// fprintf_net(stdout, tstate->model, net_idx);
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// printf("set %s\n", fmt_swset(tstate->model, switch_to.dest_y, switch_to.dest_x, &chain.set, from_to));
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#if 1
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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#endif
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fpga_net_delete(tstate->model, net_idx);
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}
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*block_list_len = chain.block_list_len;
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// printf("block_list_len now %i\n", *block_list_len);
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destruct_sw_chain(&chain);
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}
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return 0;
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fail:
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return rc;
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}
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static int test_logic_net(struct test_state* tstate, int logic_y, int logic_x,
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int type_idx, pinw_idx_t port, const struct sw_set* logic_switch_set,
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int routing_y, int routing_x, swidx_t routing_sw1, swidx_t routing_sw2)
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{
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net_idx_t net_idx;
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struct sw_set routing_switches;
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int rc;
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int dbg, rc;
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dbg = 0;
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rc = fpga_net_new(tstate->model, &net_idx);
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if (rc) FAIL(rc);
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@ -327,36 +177,38 @@ static int test_logic_net(struct test_state* tstate, int logic_y, int logic_x,
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routing_y, routing_x, &routing_switches);
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if (rc) FAIL(rc);
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#if 0
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printf("lnet %s %s\n", fpga_switch_print(tstate->model, routing_y,
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routing_x, routing_sw1), routing_sw2 == NO_SWITCH ? ""
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: fpga_switch_print(tstate->model, routing_y, routing_x, routing_sw2));
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#endif
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#if 1
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if (dbg)
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printf("lnet %s %s\n",
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routing_sw2 == NO_SWITCH ? "" : fpga_switch_print(
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tstate->model, routing_y, routing_x,
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routing_sw2),
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fpga_switch_print(tstate->model,
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routing_y, routing_x, routing_sw1));
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rc = diff_printf(tstate);
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if (rc) FAIL(rc);
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#endif
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fpga_net_delete(tstate->model, net_idx);
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return 0;
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fail:
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return rc;
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}
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static int test_logic_fingers(struct test_state* tstate, int y, int x,
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static int test_logic_net_l2(struct test_state* tstate, int y, int x,
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int type, int type_idx, str16_t* done_pinw_list, int* done_pinw_len,
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swidx_t* l2_done_list, int* l2_done_len)
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{
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struct fpga_device* dev;
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struct switch_to_yx switch_to;
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struct sw_chain chain;
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net_idx_t net_idx;
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int i, j, k, l, from_to, direction, rc;
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int i, j, k, l, m, from_to, rc;
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struct sw_set set_l1, set_l2;
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struct fpga_tile* switch_tile;
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int dbg = 0;
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rc = fdev_set_required_pins(tstate->model, y, x, type, type_idx);
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if (rc) FAIL(rc);
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// fdev_print_required_pins(tstate->model, y, x, type, type_idx);
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if (dbg)
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fdev_print_required_pins(tstate->model, y, x, type, type_idx);
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dev = fdev_p(tstate->model, y, x, type, type_idx);
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if (!dev) FAIL(EINVAL);
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@ -381,97 +233,134 @@ static int test_logic_fingers(struct test_state* tstate, int y, int x,
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switch_to.from_to = from_to;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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// printf_switch_to_result(&switch_to);
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if (dbg)
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printf_switch_to_result(&switch_to);
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switch_tile = YX_TILE(tstate->model, switch_to.dest_y, switch_to.dest_x);
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rc = fpga_swset_fromto(tstate->model, switch_to.dest_y,
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switch_to.dest_x, switch_to.dest_connpt, from_to, &set_l1);
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if (rc) FAIL(rc);
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if (dbg)
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fpga_swset_print(tstate->model, switch_to.dest_y,
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switch_to.dest_x, &set_l1, from_to);
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// if (1||(i < dev->pinw_req_in)) {
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// if (i >= dev->pinw_req_in) {
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if (1) {
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// fpga_swset_print(tstate->model, switch_to.dest_y, switch_to.dest_x, &set_l1, from_to);
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for (j = 0; j < set_l1.len; j++) {
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rc = test_logic_net(tstate, y, x, type_idx, dev->pinw_req_for_cfg[i],
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&switch_to.set, switch_to.dest_y, switch_to.dest_x,
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set_l1.sw[j], NO_SWITCH);
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if (rc) FAIL(rc);
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// level one switches themselves cannot become duplicates
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// because we check for unique pinwires already. but we still
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// need to add them to the done_list to compare against
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// future l2 switches.
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// todo: rename l2_done_list to just done_list
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l2_done_list[(*l2_done_len)++] = set_l1.sw[j];
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for (j = 0; j < set_l1.len; j++) {
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for (k = 0; k < 2; k++) {
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// k == 0 is the SW_FROM round, k == 1 is the SW_TO round.
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// For out-pins, we don't need the SW_TO round because they
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// would create multiple sources driving one pin which is
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// illegal.
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if (k && i >= dev->pinw_req_in)
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break;
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rc = fpga_swset_fromto(tstate->model, switch_to.dest_y,
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switch_to.dest_x, CONNPT_STR16(switch_tile,
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SW_I(switch_tile->switches[set_l1.sw[j]], !from_to)),
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i < dev->pinw_req_in ? from_to : !from_to, &set_l2);
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k ? SW_TO : SW_FROM, &set_l2);
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if (rc) FAIL(rc);
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for (k = 0; k < set_l2.len; k++) {
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// on an out pin, we are reversing direction and looking
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// for other switches pointing *to* the output, but we
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// can skip ourselves...
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if (set_l2.sw[k] == set_l1.sw[j])
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continue;
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for (l = 0; l < set_l2.len; l++) {
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// The level 1 switches cannot duplicate because we
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// already track unique pinwires. But level 2 switches
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// must be checked for duplicates.
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for (l = 0; l < *l2_done_len; l++) {
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if (l2_done_list[l] == set_l2.sw[k])
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// duplicate check
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for (m = 0; m < *l2_done_len; m++) {
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if (l2_done_list[m] == set_l2.sw[l])
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break;
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}
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if (l < *l2_done_len)
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if (m < *l2_done_len)
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continue;
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l2_done_list[(*l2_done_len)++] = set_l2.sw[k];
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l2_done_list[(*l2_done_len)++] = set_l2.sw[l];
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// we did the l1 switches in an earlier round, but have to
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// redo them before every l2 switch to make a clean diff
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// on top of l1. The l2 can be in the same mip as the l1
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// so it has to be repeated for every l2 switch, not just
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// once for the set.
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rc = test_logic_net(tstate, y, x, type_idx, dev->pinw_req_for_cfg[i],
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&switch_to.set, switch_to.dest_y, switch_to.dest_x,
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set_l1.sw[j], NO_SWITCH);
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if (rc) FAIL(rc);
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rc = test_logic_net(tstate, y, x, type_idx, dev->pinw_req_for_cfg[i],
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&switch_to.set, switch_to.dest_y, switch_to.dest_x,
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set_l1.sw[j], set_l2.sw[k]);
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set_l1.sw[j], set_l2.sw[l]);
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if (rc) FAIL(rc);
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}
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}
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}
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}
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return 0;
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fail:
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return rc;
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}
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static int test_logic_net_l1(struct test_state* tstate, int y, int x,
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int type, int type_idx, str16_t* done_pinw_list, int* done_pinw_len,
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swidx_t* done_sw_list, int* done_sw_len)
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{
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struct fpga_device* dev;
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struct switch_to_yx switch_to;
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int i, j, k, from_to, rc;
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struct sw_set set_l1;
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int dbg = 0;
|
||||
|
||||
#if 0
|
||||
rc = fdev_set_required_pins(tstate->model, y, x, type, type_idx);
|
||||
if (rc) FAIL(rc);
|
||||
if (dbg)
|
||||
fdev_print_required_pins(tstate->model, y, x, type, type_idx);
|
||||
|
||||
dev = fdev_p(tstate->model, y, x, type, type_idx);
|
||||
if (!dev) FAIL(EINVAL);
|
||||
for (i = 0; i < dev->pinw_req_total; i++) {
|
||||
|
||||
// loop twice, first continue in the same direction as
|
||||
// the in/out pin, second loop in reverse direction
|
||||
for (direction = 0; direction <= 1; direction++) {
|
||||
//printf("direction %i\n", direction);
|
||||
for (j = 0; j < set_l1.len; j++) {
|
||||
|
||||
//printf("j %i\n", j);
|
||||
rc = fpga_swset_fromto(tstate->model, switch_to.dest_y,
|
||||
switch_to.dest_x, CONNPT_STR16(switch_tile,
|
||||
SW_I(switch_tile->switches[set_l1.sw[j]], !from_to)),
|
||||
direction ? !from_to : from_to, &set_l2);
|
||||
if (rc) FAIL(rc);
|
||||
|
||||
#if 0
|
||||
rc = test_logic_net(tstate, y, x, type_idx, dev->pinw_req_for_cfg[i],
|
||||
&switch_to.set, switch_to.dest_y, switch_to.dest_x,
|
||||
set_l1.sw[j], NO_SWITCH);
|
||||
if (rc) FAIL(rc);
|
||||
#endif
|
||||
|
||||
for (k = 0; k < set_l2.len; k++) {
|
||||
#if 0
|
||||
rc = test_logic_net(tstate, y, x, type_idx, dev->pinw_req_for_cfg[i],
|
||||
&switch_to.set, switch_to.dest_y, switch_to.dest_x,
|
||||
set_l1.sw[j], set_l2.sw[k]);
|
||||
if (rc) FAIL(rc);
|
||||
#endif
|
||||
}
|
||||
// fpga_swset_print(tstate->model, switch_to.dest_y, switch_to.dest_x, &set_l2, direction ? !from_to: from_to);
|
||||
}
|
||||
// do every pinw only once across all configs
|
||||
for (j = 0; j < *done_pinw_len; j++) {
|
||||
if (done_pinw_list[j] == dev->pinw[dev->pinw_req_for_cfg[i]])
|
||||
break;
|
||||
}
|
||||
if (j < *done_pinw_len)
|
||||
continue;
|
||||
done_pinw_list[(*done_pinw_len)++] = dev->pinw[dev->pinw_req_for_cfg[i]];
|
||||
|
||||
from_to = (i < dev->pinw_req_in) ? SW_TO : SW_FROM;
|
||||
switch_to.yx_req = YX_ROUTING_TILE;
|
||||
switch_to.flags = SWTO_YX_DEF;
|
||||
switch_to.model = tstate->model;
|
||||
switch_to.y = y;
|
||||
switch_to.x = x;
|
||||
switch_to.start_switch = dev->pinw[dev->pinw_req_for_cfg[i]];
|
||||
switch_to.from_to = from_to;
|
||||
rc = fpga_switch_to_yx(&switch_to);
|
||||
if (rc) FAIL(rc);
|
||||
if (dbg)
|
||||
printf_switch_to_result(&switch_to);
|
||||
|
||||
rc = fpga_swset_fromto(tstate->model, switch_to.dest_y,
|
||||
switch_to.dest_x, switch_to.dest_connpt, from_to, &set_l1);
|
||||
if (rc) FAIL(rc);
|
||||
if (dbg)
|
||||
fpga_swset_print(tstate->model, switch_to.dest_y,
|
||||
switch_to.dest_x, &set_l1, from_to);
|
||||
|
||||
for (j = 0; j < set_l1.len; j++) {
|
||||
// an out-pin can go directly to an in-pin and
|
||||
// we don't need that pin twice
|
||||
for (k = 0; k < *done_sw_len; k++) {
|
||||
if (done_sw_list[k] == set_l1.sw[j])
|
||||
break;
|
||||
}
|
||||
if (k < *done_sw_len)
|
||||
continue;
|
||||
|
||||
rc = test_logic_net(tstate, y, x, type_idx, dev->pinw_req_for_cfg[i],
|
||||
&switch_to.set, switch_to.dest_y, switch_to.dest_x,
|
||||
set_l1.sw[j], NO_SWITCH);
|
||||
if (rc) FAIL(rc);
|
||||
done_sw_list[(*done_sw_len)++] = set_l1.sw[j];
|
||||
if (dbg)
|
||||
printf("done_list %s at %i\n", fpga_switch_print(tstate->model,
|
||||
switch_to.dest_y, switch_to.dest_x, set_l1.sw[j]),
|
||||
(*done_sw_len)-1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return 0;
|
||||
fail:
|
||||
|
|
@ -479,22 +368,22 @@ fail:
|
|||
}
|
||||
|
||||
// goal: use all switches in a routing switchbox
|
||||
int test_logic_routing_switches(struct test_state* tstate);
|
||||
int test_logic_routing_switches(struct test_state* tstate)
|
||||
static int test_logic_routing_switches(struct test_state* tstate)
|
||||
{
|
||||
int a_to_d[] = { A6_LUT, B6_LUT, C6_LUT, D6_LUT };
|
||||
int idx_enum[] = { DEV_LOGM, DEV_LOGX };
|
||||
int y, x, i, j, k, rc;
|
||||
swidx_t l2_done_list[MAX_SWITCHBOX_SIZE];
|
||||
int l2_done_len;
|
||||
swidx_t done_sw_list[MAX_SWITCHBOX_SIZE];
|
||||
int done_sw_len;
|
||||
str16_t done_pinw_list[2000];
|
||||
int done_pinw_len;
|
||||
|
||||
y = 68;
|
||||
x = 13;
|
||||
|
||||
// first make one round over all configs with single-level nets only.
|
||||
done_pinw_len = 0;
|
||||
l2_done_len = 0;
|
||||
done_sw_len = 0;
|
||||
for (i = 0; i < sizeof(idx_enum)/sizeof(*idx_enum); i++) {
|
||||
for (j = 0; j < sizeof(a_to_d)/sizeof(*a_to_d); j++) {
|
||||
for (k = '1'; k <= '6'; k++) {
|
||||
|
|
@ -502,43 +391,148 @@ int test_logic_routing_switches(struct test_state* tstate)
|
|||
idx_enum[i], a_to_d[j], pf("A%c", k), ZTERM);
|
||||
if (rc) FAIL(rc);
|
||||
|
||||
rc = test_logic_fingers(tstate, y, x, DEV_LOGIC,
|
||||
rc = test_logic_net_l1(tstate, y, x, DEV_LOGIC,
|
||||
idx_enum[i], done_pinw_list, &done_pinw_len,
|
||||
l2_done_list, &l2_done_len);
|
||||
done_sw_list, &done_sw_len);
|
||||
if (rc) FAIL(rc);
|
||||
fdev_delete(tstate->model, y, x, DEV_LOGIC, idx_enum[i]);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// second round with two-level nets
|
||||
done_pinw_len = 0; // reset done pinwires
|
||||
for (i = 0; i < sizeof(idx_enum)/sizeof(*idx_enum); i++) {
|
||||
for (j = 0; j < sizeof(a_to_d)/sizeof(*a_to_d); j++) {
|
||||
for (k = '1'; k <= '6'; k++) {
|
||||
rc = fdev_logic_set_lut(tstate->model, y, x,
|
||||
idx_enum[i], a_to_d[j], pf("A%c", k), ZTERM);
|
||||
if (rc) FAIL(rc);
|
||||
|
||||
rc = test_logic_net_l2(tstate, y, x, DEV_LOGIC,
|
||||
idx_enum[i], done_pinw_list, &done_pinw_len,
|
||||
done_sw_list, &done_sw_len);
|
||||
if (rc) FAIL(rc);
|
||||
fdev_delete(tstate->model, y, x, DEV_LOGIC, idx_enum[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
for (i = 0; i < done_list_len; i++) {
|
||||
printf("done %i %s\n", i, fpga_switch_print(tstate->model, 68, 12, done_list[i]));
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
fail:
|
||||
return rc;
|
||||
}
|
||||
|
||||
#define DEFAULT_DIFF_EXEC "./autotest_diff.sh"
|
||||
|
||||
static void printf_help(const char* argv_0, const char** available_tests)
|
||||
{
|
||||
printf( "\n"
|
||||
"fpgatools automatic test suite\n"
|
||||
"\n"
|
||||
"Usage: %s [--test=<name>] [--diff=<diff executable>] [--skip=<num>]\n"
|
||||
"Default diff executable: " DEFAULT_DIFF_EXEC "\n", argv_0);
|
||||
|
||||
if (available_tests) {
|
||||
int i = 0;
|
||||
printf("\n");
|
||||
while (available_tests[i] && available_tests[i][0]) {
|
||||
printf("%s %s\n", !i ? "Available tests:"
|
||||
: " ", available_tests[i]);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
struct fpga_model model;
|
||||
struct fpga_device* P46_dev, *P48_dev, *logic_dev;
|
||||
int P46_y, P46_x, P46_dev_idx, P46_type_idx;
|
||||
int P48_y, P48_x, P48_dev_idx, P48_type_idx, logic_dev_idx, rc;
|
||||
struct test_state tstate;
|
||||
struct switch_to_yx switch_to;
|
||||
net_idx_t P46_net;
|
||||
char param[1024], cmdline_test[1024];
|
||||
int i, param_skip, rc;
|
||||
const char* available_tests[] =
|
||||
{ "logic_cfg", "routing_sw", 0 };
|
||||
|
||||
// flush after every line is better for the autotest
|
||||
// output, tee, etc.
|
||||
// for example: ./autotest 2>&1 | tee autotest.log
|
||||
setvbuf(stdout, /*buf*/ 0, _IOLBF, /*size*/ 0);
|
||||
|
||||
if (argc < 2) {
|
||||
printf_help(argv[0], available_tests);
|
||||
return 0;
|
||||
}
|
||||
|
||||
//
|
||||
// command line
|
||||
//
|
||||
|
||||
memset(&tstate, 0, sizeof(tstate));
|
||||
tstate.cmdline_skip = -1;
|
||||
tstate.cmdline_diff_exec[0] = 0;
|
||||
cmdline_test[0] = 0;
|
||||
for (i = 1; i < argc; i++) {
|
||||
memset(param, 0, sizeof(param));
|
||||
if (sscanf(argv[i], "--test=%1023c", param) == 1) {
|
||||
if (cmdline_test[0]) {
|
||||
printf_help(argv[0], available_tests);
|
||||
return EINVAL;
|
||||
}
|
||||
strcpy(cmdline_test, param);
|
||||
continue;
|
||||
}
|
||||
memset(param, 0, sizeof(param));
|
||||
if (sscanf(argv[i], "--diff=%1023c", param) == 1) {
|
||||
if (tstate.cmdline_diff_exec[0]) {
|
||||
printf_help(argv[0], available_tests);
|
||||
return EINVAL;
|
||||
}
|
||||
strcpy(tstate.cmdline_diff_exec, param);
|
||||
continue;
|
||||
}
|
||||
if (sscanf(argv[i], "--skip=%i", ¶m_skip) == 1) {
|
||||
if (tstate.cmdline_skip != -1) {
|
||||
printf_help(argv[0], available_tests);
|
||||
return EINVAL;
|
||||
}
|
||||
tstate.cmdline_skip = param_skip;
|
||||
continue;
|
||||
}
|
||||
printf_help(argv[0], available_tests);
|
||||
return EINVAL;
|
||||
}
|
||||
if (!cmdline_test[0]) {
|
||||
printf_help(argv[0], available_tests);
|
||||
return EINVAL;
|
||||
}
|
||||
i = 0;
|
||||
while (available_tests[i] && available_tests[i][0]) {
|
||||
if (!strcmp(available_tests[i], cmdline_test))
|
||||
break;
|
||||
i++;
|
||||
}
|
||||
if (!available_tests[i] || !available_tests[i][0]) {
|
||||
printf_help(argv[0], available_tests);
|
||||
return EINVAL;
|
||||
}
|
||||
if (!tstate.cmdline_diff_exec[0])
|
||||
strcpy(tstate.cmdline_diff_exec, DEFAULT_DIFF_EXEC);
|
||||
if (tstate.cmdline_skip == -1)
|
||||
tstate.cmdline_skip = 0;
|
||||
|
||||
//
|
||||
// test
|
||||
//
|
||||
|
||||
printf("\n");
|
||||
printf("O fpgatools automatic test suite. Be welcome and be "
|
||||
"our guest. namo namaha.\n");
|
||||
printf("\n");
|
||||
printf("O Test: %s\n", cmdline_test);
|
||||
printf("O Diff: %s\n", tstate.cmdline_diff_exec);
|
||||
printf("O Skip: %i\n", tstate.cmdline_skip);
|
||||
printf("\n");
|
||||
printf("O Time measured in seconds from 0.\n");
|
||||
g_start_time = time(0);
|
||||
TIMESTAMP();
|
||||
|
|
@ -555,18 +549,17 @@ int main(int argc, char** argv)
|
|||
tstate.model = &model;
|
||||
strcpy(tstate.tmp_dir, AUTOTEST_TMP_DIR);
|
||||
mkdir(tstate.tmp_dir, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
|
||||
rc = diff_start(&tstate, "and");
|
||||
rc = diff_start(&tstate, cmdline_test);
|
||||
if (rc) FAIL(rc);
|
||||
|
||||
#if 0
|
||||
rc = test_logic_config(&tstate);
|
||||
if (rc) FAIL(rc);
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
rc = test_logic_routing_switches(&tstate);
|
||||
if (rc) FAIL(rc);
|
||||
#endif
|
||||
if (!strcmp(cmdline_test, "logic_cfg")) {
|
||||
rc = test_logic_config(&tstate);
|
||||
if (rc) FAIL(rc);
|
||||
}
|
||||
if (!strcmp(cmdline_test, "routing_sw")) {
|
||||
rc = test_logic_routing_switches(&tstate);
|
||||
if (rc) FAIL(rc);
|
||||
}
|
||||
|
||||
// test_iob_config
|
||||
// test_iologic_routing_switches
|
||||
|
|
@ -591,6 +584,14 @@ int main(int argc, char** argv)
|
|||
#endif
|
||||
|
||||
#if 0
|
||||
struct fpga_model model;
|
||||
struct fpga_device* P46_dev, *P48_dev, *logic_dev;
|
||||
int P46_y, P46_x, P46_dev_idx, P46_type_idx;
|
||||
int P48_y, P48_x, P48_dev_idx, P48_type_idx, logic_dev_idx, rc;
|
||||
struct test_state tstate;
|
||||
struct switch_to_yx switch_to;
|
||||
net_idx_t P46_net;
|
||||
|
||||
// configure P46
|
||||
rc = fpga_find_iob(&model, "P46", &P46_y, &P46_x, &P46_type_idx);
|
||||
if (rc) FAIL(rc);
|
||||
|
|
@ -726,7 +727,7 @@ int main(int argc, char** argv)
|
|||
#endif
|
||||
|
||||
printf("\n");
|
||||
printf("O Test suite completed.\n");
|
||||
printf("O Test completed.\n");
|
||||
TIME_AND_MEM();
|
||||
printf("\n");
|
||||
return EXIT_SUCCESS;
|
||||
|
|
|
|||
|
|
@ -12,5 +12,5 @@ fi
|
|||
|
||||
echo "fp:" > ${2%.*}.diff
|
||||
cat ${2%.*}.fp_diff | sed -e '/^--- /d;/^+++ /d;/^@@ /d' >> ${2%.*}.diff
|
||||
echo "b2f:" >> ${2%.*}.diff
|
||||
echo "bit:" >> ${2%.*}.diff
|
||||
cat ${2%.*}.b2f_diff | sed -e '/^--- /d;/^+++ /d;/^@@ /d' >> ${2%.*}.diff
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user