development postponed until 2014
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Wolfgang Spraul
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README
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README
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@ -1,15 +1,22 @@
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**** NOTE - JUNE 2013 ****
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I would L O V E to do continue with fpgatools but each day is
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short so I have to postpone fpgatools development probably
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until 2014. Maybe I can switch directly to Artix then :-)
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If you want to contact me please email wspraul@q-ag.de
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****
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Introduction
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fpgatools is a toolchain to program field-programmable gate arrays
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(FPGAs). The only supported chip at this time is the xc6slx9, a
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7 USD 45nm-generation fpga with 5720 6-input LUTs, block ram and
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45nm-generation fpga with 5720 6-input LUTs, block ram and
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multiply-accumulate devices.
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*) maximize chip performance
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*) fast development cycles
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*) independent toolchain that only depends on other free software
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*) independent toolchain that only depends on free software
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*) reconfigure on-chip
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*) include get-started tools such as jtag, debugging, parts data
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and designs for prototyping hardware
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and hardware designs
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*) design flow that includes asic manufacturing
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*) lightweight C implementation without GUI
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*) supported platform: Linux
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@ -63,22 +70,21 @@ Design Principles
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TODO (as of February, 2013)
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short-term (1 month):
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* finish dist_mem test
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* support block memory
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-> develop structure of dev_bram16/8
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-> write block_mem autotest
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* example: counter (including clock, jtag)
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mid-term (6 months):
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* example: j1 soc
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* llvm backend
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* hls: llvm backend
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* maybe fp2bit should natively write ieee1532 and separate tools convert
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from ieee1532 to .bit and other formats
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* macc
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* more cases in logic block configuration
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* autotest: fix bugs in lut_encoding, logic_cfg, routing_sw, io_sw tests
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* autotest: protect stderr of diff executable in autotest log
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* 3 Debian packages: libfpga, libfpga-doc, fpgatools
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* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
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xc6 or the xc7a100
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* support chips other than xc6slx9, maybe xc7a20
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* write standard design elements for libfpga-stdlib library
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* several places might benefit from a bison parser:
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- switchbox description into bit parser/generator (bit_frames.c)
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@ -471,7 +471,7 @@ void printf_type2(uint8_t *d, int len, int inpos, int num_entries)
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}
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}
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static int ramb_words_to_bram16(uint16_t (*init_data)[64][16], uint16_t (*init_parity)[8][16], int (*ramb_words)[1024])
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static int ramb_words_to_bram16(int (*init_data)[64][16], int (*init_parity)[8][16], int (*ramb_words)[1024])
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{
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int init_i, i, j, bits_set;
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@ -499,8 +499,8 @@ static int ramb_words_to_bram16(uint16_t (*init_data)[64][16], uint16_t (*init_p
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// prepare data words for string printf
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for (init_i = 0; init_i < 64; init_i++) {
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for (i = 0; i < 8; i++) {
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(*init_data)[init_i][i*2] = (*ramb_words)[init_i*8 + i];
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(*init_data)[init_i][i*2+1] = (*ramb_words)[512 + init_i*8 + i];
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(*init_data)[init_i][i*2] = (*ramb_words)[init_i*8 + i] & 0xFFFF;
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(*init_data)[init_i][i*2+1] = (*ramb_words)[512 + init_i*8 + i] & 0xFFFF;
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if ((*init_data)[init_i][i*2]
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|| (*init_data)[init_i][i*2+1])
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@ -510,7 +510,7 @@ static int ramb_words_to_bram16(uint16_t (*init_data)[64][16], uint16_t (*init_p
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return bits_set;
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}
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static int ramb_words_to_bram8(uint16_t (*init_data)[64][16], uint16_t (*init_parity)[8][16], int (*ramb_words)[1024])
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static int ramb_words_to_bram8(int (*init_data)[64][16], int (*init_parity)[8][16], int (*ramb_words)[1024])
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{
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int init_i, i, j, devs_used;
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@ -534,7 +534,7 @@ static int ramb_words_to_bram8(uint16_t (*init_data)[64][16], uint16_t (*init_pa
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// prepare data words (0:31 are for the first bram8 device, 32:63 for the second one)
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for (init_i = 0; init_i < 64; init_i++) {
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for (i = 0; i < 16; i++) {
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(*init_data)[init_i][i] = (*ramb_words)[init_i*16 + i];
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(*init_data)[init_i][i] = (*ramb_words)[init_i*16 + i] & 0xFFFF;
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if ((*init_data)[init_i][i])
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devs_used |= (init_i < 32) ? 0x01 : 0x02;
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}
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@ -545,7 +545,7 @@ static int ramb_words_to_bram8(uint16_t (*init_data)[64][16], uint16_t (*init_pa
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void printf_ramb_data(const uint8_t *bits, int row, int bram_idx)
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{
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int nonzero_head, nonzero_tail, ramb_words[1024];
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uint16_t init_data[64][16], init_parity[8][16];
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int init_data[64][16], init_parity[8][16];
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int i, j, devs_used;
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// check head and tail
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66
libs/model.h
66
libs/model.h
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@ -663,9 +663,16 @@ enum {
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BO_LAST = BO_DOPB3
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};
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struct fpgadev_bram
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// requirements for valid bram
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// rstram and rst_priority must be set for A and B.
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// todo: haven't decided whether dev_bram should be one structure
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// for 8+16 or two separate structures
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struct fpgadev_bram16
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{
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};
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struct fpgadev_bram8
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{
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// rstram and rst_priority must be set for A and B.
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};
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//
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@ -754,7 +761,8 @@ struct fpga_device
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struct fpgadev_bufgmux bufgmux;
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struct fpgadev_bufio bufio;
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struct fpgadev_bscan bscan;
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struct fpgadev_bram bram;
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struct fpgadev_bram16 bram16;
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struct fpgadev_bram8 bram8;
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} u;
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};
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@ -1191,3 +1199,55 @@ struct w_net
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#define ADD_PREF 1
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int add_conn_net(struct fpga_model* model, int add_pref, const struct w_net *net);
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#if 0
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bram16:
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int *data; // points to 1024 words (each 16+2=18 bits)
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int clka_inv; // DEVCFG_INV_Y, DEVCFG_INV_N
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int clkb_inv;
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int data_width_a; // 0,1,2,4,9,18,36
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int data_width_b; // 0,1,2,4,9,18,36
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int doa_reg; // BRAM_OUTREG_ON, BRAM_OUTREG_OFF
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int dob_reg;
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int ena_inv;
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int enb_inv; // BRAM_ENB_INV_Y, BRAM_ENB_INV_N
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int reg_cea_inv;
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int reg_ceb_inv;
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int rsta_inv;
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int rstb_inv;
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int wea_inv[4];
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int web_inv[4];
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int rst_type; // BRAM_RST_SYNC, BRAM_RST_ASYNC
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int write_mode_a; // BRAM_WRITE_FIRST, BRAM_READ_FIRST, BRAM_NO_CHANGE
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int write_mode_b;
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int ram_mode; // BRAM_TDP, BRAM_SDP, BRAM_SP
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int rst_priority_a; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
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int rst_priority_b; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
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int en_rstram_a; // DEVCFG_FALSE, DEVCFG_TRUE
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int en_rstram_b; // DEVCFG_FALSE, DEVCFG_TRUE
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bram8:
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int *data; // points to 512 words (each 16+2=18 bits)
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int clk_awr_inv; // DEVCFG_INV_Y, DEVCFG_INV_N
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int clk_brd_inv;
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int data_width_a; // 0,1,2,4,9,18,36
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int data_width_b; // 0,1,2,4,9,18,36
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int doa_reg; // BRAM_OUTREG_ON, BRAM_OUTREG_OFF
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int dob_reg;
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int en_awr_inv;
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int en_brd_inv; // BRAM_ENB_INV_Y, BRAM_ENB_INV_N
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int reg_cea_inv;
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int reg_ceb_reg_ce_inv;
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int rsta_inv;
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int rstb_rst_inv;
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int wea_wel_inv[2];
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int web_weu_inv[2];
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int rst_type; // BRAM_RST_SYNC, BRAM_RST_ASYNC
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int write_mode_a; // BRAM_WRITE_FIRST, BRAM_READ_FIRST, BRAM_NO_CHANGE
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int write_mode_b;
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int ram_mode; // BRAM_TDP, BRAM_SDP, BRAM_SP
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int rst_priority_a; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
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int rst_priority_b; // BRAM_RST_PRIORITY_SR, BRAM_RST_PRIORITY_CE
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int en_rstram_a; // DEVCFG_FALSE, DEVCFG_TRUE
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int en_rstram_b; // DEVCFG_FALSE, DEVCFG_TRUE
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#endif
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