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switches

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This commit is contained in:
Wolfgang Spraul 2012-11-23 05:34:59 +01:00
parent 80eec05b7a
commit aa4021f7a4
4 changed files with 565 additions and 101 deletions
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2
README
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@ -65,7 +65,6 @@ short-term (1 month):
mid-term (6 months):
* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
xc6 or the xc7a100
* more cases in switches (98% done) and inter-tile connections (70% done)
* more cases in logic block configuration
* configuration of bram and macc blocks, bram initialization data
* write standard design elements for libfpga-stdlib library
@ -82,6 +81,7 @@ cleanup (whenever convenient):
long-term (>6 months):
* auto-crc calculation in .bit file
* MCB switches and connections
* support lm32 or openrisc core, either via libfpga or iverilog backend
* ipv6 or vnc in hardware?
* iverilog fpga backend

336
libs/model_conns.c
View File

@ -9,6 +9,7 @@
#include "model.h"
#include "parts.h"
static int bufpll(struct fpga_model *model);
static int reg_ioclk(struct fpga_model *model);
static int reg_lock(struct fpga_model *model);
static int reg_pll_dcm(struct fpga_model *model);
@ -39,6 +40,7 @@ int init_conns(struct fpga_model *model)
{
RC_CHECK(model);
bufpll(model);
reg_ioclk(model);
reg_lock(model);
reg_pll_dcm(model);
@ -78,6 +80,27 @@ int init_conns(struct fpga_model *model)
RC_RETURN(model);
}
static int bufpll_x(struct fpga_model *model, int x)
{
RC_CHECK(model);
add_switch(model, model->center_y-CENTER_Y_MINUS_2, x,
"CLK0", "INT_BUFPLL_GCLK2", /*bidir*/ 0);
add_switch(model, model->center_y-CENTER_Y_MINUS_2, x,
"CLK1", "INT_BUFPLL_GCLK3", /*bidir*/ 0);
add_switch(model, model->center_y-CENTER_Y_MINUS_1, x,
"CLK0", "INT_BUFPLL_GCLK0", /*bidir*/ 0);
add_switch(model, model->center_y-CENTER_Y_MINUS_1, x,
"CLK1", "INT_BUFPLL_GCLK1", /*bidir*/ 0);
RC_RETURN(model);
}
static int bufpll(struct fpga_model *model)
{
RC_CHECK(model);
bufpll_x(model, LEFT_IO_ROUTING);
bufpll_x(model, model->x_width-RIGHT_IO_ROUTING_O);
RC_RETURN(model);
}
static int find_pll_dcm_y(struct fpga_model *model,
int *top_pll_y, int *top_dcm_y,
int *bot_pll_y, int *bot_dcm_y)
@ -172,7 +195,7 @@ static int reg_ioclk(struct fpga_model *model)
static int reg_lock(struct fpga_model *model)
{
int top_pll_y, top_dcm_y, bot_pll_y, bot_dcm_y, i, rc;
int top_pll_y, top_dcm_y, bot_pll_y, bot_dcm_y, i;
RC_CHECK(model);
@ -183,7 +206,11 @@ static int reg_lock(struct fpga_model *model)
{ "REGH_LTERM_LOCK%i", 0, model->center_y, LEFT_INNER_COL },
{ "REGH_IOI_INT_LOCK%i", 0, model->center_y, LEFT_IO_ROUTING },
{ "INT_BUFPLL_LOCK_LR%i", 0, model->center_y-CENTER_Y_MINUS_1, LEFT_IO_ROUTING }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
add_switch(model, model->center_y-CENTER_Y_MINUS_1, LEFT_IO_ROUTING,
"INT_BUFPLL_LOCK_LR0", "LOGICOUT0", /*bidir*/ 0);
add_switch(model, model->center_y-CENTER_Y_MINUS_1, LEFT_IO_ROUTING,
"INT_BUFPLL_LOCK_LR1", "LOGICOUT1", /*bidir*/ 0);
// right
{ struct w_net n = {
@ -194,7 +221,11 @@ static int reg_lock(struct fpga_model *model)
{ "REGH_RIOI_LOCK%i", 0, model->center_y, model->x_width-RIGHT_IO_DEVS_O },
{ "REGH_RIOI_INT_LOCK%i", 0, model->center_y, model->x_width-RIGHT_IO_ROUTING_O },
{ "INT_BUFPLL_LOCK_LR%i", 0, model->center_y-CENTER_Y_MINUS_1, model->x_width-RIGHT_IO_ROUTING_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
add_switch(model, model->center_y-CENTER_Y_MINUS_1, model->x_width-RIGHT_IO_ROUTING_O,
"INT_BUFPLL_LOCK_LR0", "LOGICOUT0", /*bidir*/ 0);
add_switch(model, model->center_y-CENTER_Y_MINUS_1, model->x_width-RIGHT_IO_ROUTING_O,
"INT_BUFPLL_LOCK_LR1", "LOGICOUT1", /*bidir*/ 0);
// top
{ struct w_net n = {
@ -204,7 +235,11 @@ static int reg_lock(struct fpga_model *model)
{ "REGV_TTERM_LOCK%i", 0, TOP_INNER_ROW, model->center_x },
{ "PLLBUF_TOP_LOCK%i", 0, TOP_INNER_ROW, model->center_x+CENTER_X_PLUS_1 },
{ "INT_BUFPLL_LOCK%i", 0, TOP_OUTER_IO, model->center_x+CENTER_X_PLUS_1 }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
add_switch(model, TOP_OUTER_IO, model->center_x+CENTER_X_PLUS_1,
"INT_BUFPLL_LOCK0", "LOGICOUT18", /*bidir*/ 0);
add_switch(model, TOP_OUTER_IO, model->center_x+CENTER_X_PLUS_1,
"INT_BUFPLL_LOCK1", "LOGICOUT19", /*bidir*/ 0);
// bottom
{ struct w_net n = {
@ -217,7 +252,11 @@ static int reg_lock(struct fpga_model *model)
{ "BIOI_OUTER_LOCK%i", 0, model->y_height-BOT_OUTER_IO, model->center_x+CENTER_X_PLUS_2 },
{ "BIOI_INNER_LOCK%i", 0, model->y_height-BOT_INNER_IO, model->center_x+CENTER_X_PLUS_2 },
{ "INT_BUFPLL_LOCK_DN%i", 0, model->y_height-BOT_INNER_IO, model->center_x+CENTER_X_PLUS_1 }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
add_switch(model, model->y_height-BOT_INNER_IO, model->center_x+CENTER_X_PLUS_1,
"INT_BUFPLL_LOCK_DN0", "LOGICOUT18", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_INNER_IO, model->center_x+CENTER_X_PLUS_1,
"INT_BUFPLL_LOCK_DN1", "LOGICOUT19", /*bidir*/ 0);
find_pll_dcm_y(model, &top_pll_y, &top_dcm_y, &bot_pll_y, &bot_dcm_y);
RC_ASSERT(model, top_pll_y != -1 && top_dcm_y != -1
@ -231,20 +270,18 @@ static int reg_lock(struct fpga_model *model)
{ pf("REGT_TERM_LOCKIN%i", i), 0, TOP_INNER_ROW, model->center_x-CENTER_CMTPLL_O },
{ pf("CMT_PLL_LOCK_UP%i", i), 0, top_pll_y, model->center_x-CENTER_CMTPLL_O },
{ pf("CMT_DCM_LOCK_UP%i", i), 0, top_dcm_y, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc);
add_conn_net(model, NOPREF_BI_F, &n);
}
// :1 between pll and dcm
rc = add_conn_bi(model,
add_conn_bi(model,
top_pll_y, model->center_x-CENTER_CMTPLL_O, "CMT_PLL_LOCK_DN1",
top_dcm_y, model->center_x-CENTER_CMTPLL_O, "CMT_DCM_LOCK_UP1");
if (rc) RC_FAIL(model, rc);
// 0:2 between dcm and center_y
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
top_dcm_y, model->center_x-CENTER_CMTPLL_O, "CMT_DCM_LOCK_DN%i", 0, 2,
model->center_y, model->center_x-CENTER_CMTPLL_O, "PLL_LOCK_TOP%i", 0);
if (rc) RC_FAIL(model, rc);
for (i = 0; i <= 2; i++) {
// nets for :0 and :2 include the dcm, the :1 net ends at the pll
@ -253,14 +290,13 @@ static int reg_lock(struct fpga_model *model)
{{ pf("PLL_LOCK_BOT%i", i), 0, model->center_y, model->center_x-CENTER_CMTPLL_O },
{ pf("CMT_PLL_LOCK_UP%i", i), 0, bot_pll_y, model->center_x-CENTER_CMTPLL_O },
{ pf("CMT_DCM_LOCK_UP%i", i), 0, bot_dcm_y, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc);
add_conn_net(model, NOPREF_BI_F, &n);
}
// :1 between pll and dcm
rc = add_conn_bi(model,
add_conn_bi(model,
bot_pll_y, model->center_x-CENTER_CMTPLL_O, "CMT_PLL_LOCK_DN1",
bot_dcm_y, model->center_x-CENTER_CMTPLL_O, "CMT_DCM_LOCK_UP1");
if (rc) RC_FAIL(model, rc);
// 0:2 to bottom reg
{ struct w_net n = {
@ -268,49 +304,43 @@ static int reg_lock(struct fpga_model *model)
{{ "CMT_DCM_LOCK_DN%i", 0, bot_dcm_y, model->center_x-CENTER_CMTPLL_O },
{ "REGB_TERM_LOCKIN%i", 0, model->y_height-BOT_INNER_ROW, model->center_x-CENTER_CMTPLL_O },
{ "REGB_LOCKIN%i", 0, model->y_height-BOT_OUTER_ROW, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
RC_RETURN(model);
}
static int pll_dcm_clk(struct fpga_model *model, int pll_y, int dcm_y)
{
int rc;
RC_CHECK(model);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
pll_y, model->center_x-CENTER_CMTPLL_O, "CMT_CLK_TO_DCM%i", 1, 2,
dcm_y, model->center_x-CENTER_CMTPLL_O, "DCM%i_CLK_FROM_PLL", 1);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
pll_y, model->center_x-CENTER_CMTPLL_O, "CMT_CLK_FROM_DCM%i", 1, 2,
dcm_y, model->center_x-CENTER_CMTPLL_O, "DCM%i_CLK_TO_PLL", 1);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
pll_y, model->center_x-CENTER_CMTPLL_O, "CMT_DCM%i_CLKFB", 1, 2,
dcm_y, model->center_x-CENTER_CMTPLL_O, "DCM%i_CLKFB_TOPLL", 1);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
pll_y, model->center_x-CENTER_CMTPLL_O, "CMT_DCM%i_CLKIN", 1, 2,
dcm_y, model->center_x-CENTER_CMTPLL_O, "DCM%i_CLKIN_TOPLL", 1);
if (rc) RC_FAIL(model, rc);
RC_RETURN(model);
}
static int reg_pll_dcm(struct fpga_model *model)
{
int y, top_pll_y, top_dcm_y, bot_pll_y, bot_dcm_y, rc;
int y, i, top_pll_y, top_dcm_y, bot_pll_y, bot_dcm_y;
RC_CHECK(model);
for (y = TOP_FIRST_REGULAR; y < model->y_height - BOT_LAST_REGULAR_O; y++) {
// connections at each hclk row
if (is_aty(Y_ROW_HORIZ_AXSYMM, model, y)) {
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
y, model->center_x, "REGV_PLL_HCLK%i", 0, 15,
y-1, model->center_x-CENTER_CMTPLL_O,
has_device(model, y-1, model->center_x
- CENTER_CMTPLL_O, DEV_PLL)
? "CMT_PLL_HCLK%i" : "DCM_HCLK%i", 0);
if (rc) RC_FAIL(model, rc);
}
}
@ -323,10 +353,9 @@ static int reg_pll_dcm(struct fpga_model *model)
//
// from top_pll_y down to top_dcm_y
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
top_pll_y, model->center_x-CENTER_CMTPLL_O, "CLK_PLLCASC_OUT%i", 0, 15,
top_dcm_y, model->center_x-CENTER_CMTPLL_O, "PLL_CLK_CASC_TOP%i", 0);
if (rc) RC_FAIL(model, rc);
// from center up to top_dcm_y and down to bot_pll_y
{ struct w_net n = {
@ -337,7 +366,7 @@ static int reg_pll_dcm(struct fpga_model *model)
model->center_y, model->center_x-CENTER_CMTPLL_O },
{ "PLL_CLK_CASC_BOT%i", 0,
top_dcm_y, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 15, .num_pts = 3, .pt =
{{ "CLKC_PLL_L%i", 0,
@ -346,13 +375,18 @@ static int reg_pll_dcm(struct fpga_model *model)
model->center_y, model->center_x-CENTER_CMTPLL_O },
{ "PLL_CLK_CASC_IN%i", 0,
bot_pll_y, model->center_x-CENTER_CMTPLL_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
for (i = 0; i <= 15; i++) {
add_switch(model, bot_pll_y, model->center_x-CENTER_CMTPLL_O,
pf("CLK_PLLCASC_OUT%i", i), pf("PLL_CLK_CASC_IN%i", i),
/*bidir*/ 0);
}
// from bot_pll_y down to bot_dcm_y
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
bot_pll_y, model->center_x-CENTER_CMTPLL_O, "CLK_PLLCASC_OUT%i", 0, 15,
bot_dcm_y, model->center_x-CENTER_CMTPLL_O, "PLL_CLK_CASC_TOP%i", 0);
if (rc) RC_FAIL(model, rc);
//
// clk between pll and dcm, top and bottom side
@ -366,56 +400,47 @@ static int reg_pll_dcm(struct fpga_model *model)
static int gtp(struct fpga_model *model)
{
int rc;
RC_CHECK(model);
// left
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
model->center_y, LEFT_OUTER_COL, "REGL_GTPCLK%i", 0, 7,
model->center_y, LEFT_INNER_COL, "REGH_LTERM_GTPCLK%i", 0);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
model->center_y, LEFT_OUTER_COL, "REGL_GTPFB%i", 0, 7,
model->center_y, LEFT_INNER_COL, "REGH_LTERM_GTPFB%i", 0);
if (rc) RC_FAIL(model, rc);
// right
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
model->center_y, model->x_width-RIGHT_OUTER_O, "REGR_GTPCLK%i", 0, 7,
model->center_y, model->x_width-RIGHT_INNER_O, "REGH_RTERM_GTPCLK%i", 0);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
model->center_y, model->x_width-RIGHT_OUTER_O, "REGR_GTPFB%i", 0, 7,
model->center_y, model->x_width-RIGHT_INNER_O, "REGH_RTERM_GTPFB%i", 0);
if (rc) RC_FAIL(model, rc);
// top
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
TOP_OUTER_ROW, model->center_x-CENTER_CMTPLL_O, "REGT_GTPCLK%i", 0, 7,
TOP_INNER_ROW, model->center_x-CENTER_CMTPLL_O, "REGT_TTERM_GTPCLK%i", 0);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
TOP_OUTER_ROW, model->center_x-CENTER_CMTPLL_O, "REGT_GTPFB%i", 0, 7,
TOP_INNER_ROW, model->center_x-CENTER_CMTPLL_O, "REGT_TTERM_GTPFB%i", 0);
if (rc) RC_FAIL(model, rc);
// bottom
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
model->y_height-BOT_OUTER_ROW, model->center_x-CENTER_CMTPLL_O, "REGB_GTPCLK%i", 0, 7,
model->y_height-BOT_INNER_ROW, model->center_x-CENTER_CMTPLL_O, "REGB_BTERM_GTPCLK%i", 0);
if (rc) RC_FAIL(model, rc);
rc = add_conn_range(model, NOPREF_BI_F,
add_conn_range(model, NOPREF_BI_F,
model->y_height-BOT_OUTER_ROW, model->center_x-CENTER_CMTPLL_O, "REGB_GTPFB%i", 0, 7,
model->y_height-BOT_INNER_ROW, model->center_x-CENTER_CMTPLL_O, "REGB_BTERM_GTPFB%i", 0);
if (rc) RC_FAIL(model, rc);
RC_RETURN(model);
}
static int pci(struct fpga_model *model)
{
int rc;
static const int pci_wnum[3] = {24, 7, 5};
int i;
RC_CHECK(model);
@ -428,31 +453,38 @@ static int pci(struct fpga_model *model)
{ "LIOB_PCI_IT_RDY", 0, model->center_y-CENTER_Y_MINUS_1, LEFT_OUTER_COL },
{ "LIOB_PCI_IT_RDY", 0, model->center_y-CENTER_Y_MINUS_2, LEFT_OUTER_COL },
{ "LIOB_PCICE_TRDY_EXT", 0, model->center_y-CENTER_Y_MINUS_3, LEFT_OUTER_COL }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 0, .num_pts = 2, .pt =
{{ "REGL_PCI_TRDY_IOB", 0, model->center_y, LEFT_OUTER_COL },
{ "LIOB_PCI_IT_RDY", 0, model->center_y+CENTER_Y_PLUS_1, LEFT_OUTER_COL }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 0, .num_pts = 3, .pt =
{{ "REGL_PCI_IRDY_PINW", 0, model->center_y, LEFT_OUTER_COL },
{ "REGH_LTERM_IRDY_PINW", 0, model->center_y, LEFT_INNER_COL },
{ "REGH_LEFT_PCI_IRDY_PINW", 0, model->center_y, LEFT_IO_ROUTING }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 0, .num_pts = 3, .pt =
{{ "REGL_PCI_TRDY_PINW", 0, model->center_y, LEFT_OUTER_COL },
{ "REGH_LTERM_TRDY_PINW", 0, model->center_y, LEFT_INNER_COL },
{ "REGH_LEFT_PCI_TRDY_PINW", 0, model->center_y, LEFT_IO_ROUTING }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 2, .num_pts = 2, .pt =
{{ "IOI_INT_I%i", 1, model->center_y-CENTER_Y_MINUS_1, LEFT_IO_ROUTING },
{ "REGH_PCI_I%i_INT", 1, model->center_y, LEFT_IO_ROUTING }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
for (i = 1; i <= 3; i++) {
add_switch(model, model->center_y-CENTER_Y_MINUS_1, LEFT_IO_ROUTING,
pf("LOGICIN_B%i", pci_wnum[i-1]), pf("IOI_INT_I%i", i), /*bidir*/ 0);
add_switch(model, model->center_y, LEFT_IO_ROUTING,
pf("REGH_PCI_I%i_INT", i), pf("REGL_PCI_I%i_PINW", i), /*bidir*/ 0);
}
//
// right side
@ -463,12 +495,12 @@ static int pci(struct fpga_model *model)
{ "RIOB_PCI_IT_RDY", 0, model->center_y-CENTER_Y_MINUS_1, model->x_width-RIGHT_OUTER_O },
{ "RIOB_PCI_IT_RDY", 0, model->center_y-CENTER_Y_MINUS_2, model->x_width-RIGHT_OUTER_O },
{ "RIOB_PCI_IT_RDY", 0, model->center_y-CENTER_Y_MINUS_3, model->x_width-RIGHT_OUTER_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 0, .num_pts = 2, .pt =
{{ "REGR_PCI_TRDY_IOB", 0, model->center_y, model->x_width-RIGHT_OUTER_O },
{ "RIOB_PCI_TRDY_EXT", 0, model->center_y+CENTER_Y_PLUS_1, model->x_width-RIGHT_OUTER_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 0, .num_pts = 4, .pt =
@ -476,22 +508,28 @@ static int pci(struct fpga_model *model)
{ "REGH_RTERM_IRDY_PINW", 0, model->center_y, model->x_width-RIGHT_INNER_O },
{ "MCB_REGH_IRDY_PINW", 0, model->center_y, model->x_width-RIGHT_MCB_O },
{ "REGR_RTERM_IRDY_PINW", 0, model->center_y, model->x_width-RIGHT_IO_DEVS_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 0, .num_pts = 4, .pt =
{{ "REGR_PCI_TRDY_PINW", 0, model->center_y, model->x_width-RIGHT_OUTER_O },
{ "REGH_RTERM_TRDY_PINW", 0, model->center_y, model->x_width-RIGHT_INNER_O },
{ "MCB_REGH_TRDY_PINW", 0, model->center_y, model->x_width-RIGHT_MCB_O },
{ "REGR_RTERM_TRDY_PINW", 0, model->center_y, model->x_width-RIGHT_IO_DEVS_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
{ struct w_net n = {
.last_inc = 2, .num_pts = 3, .pt =
{{ "REGH_RIOI_PCI_I%i", 1, model->center_y, model->x_width-RIGHT_IO_DEVS_O },
{ "REGH_IOI_INT_I%i", 1, model->center_y, model->x_width-RIGHT_IO_ROUTING_O },
{ "IOI_INT_I%i", 1, model->center_y-CENTER_Y_MINUS_1, model->x_width-RIGHT_IO_ROUTING_O }}};
if ((rc = add_conn_net(model, NOPREF_BI_F, &n))) RC_FAIL(model, rc); }
add_conn_net(model, NOPREF_BI_F, &n); }
for (i = 1; i <= 3; i++) {
add_switch(model, model->center_y-CENTER_Y_MINUS_1, model->x_width-RIGHT_IO_ROUTING_O,
pf("LOGICIN_B%i", pci_wnum[i-1]), pf("IOI_INT_I%i", i), /*bidir*/ 0);
add_switch(model, model->center_y, model->x_width-RIGHT_IO_DEVS_O,
pf("REGH_RIOI_PCI_I%i", i), pf("REGR_PCI_I%i_PINW", i), /*bidir*/ 0);
}
RC_RETURN(model);
}
@ -756,6 +794,57 @@ static void net_mirror_x(struct fpga_model *model, struct w_net_i *net)
net->yx[i].x = model->x_width - 1 - net->yx[i].x;
}
static const char *io_site_connpt(struct fpga_model *model, int y, int x, int wire)
{
if (wire >= CFB0 && wire <= CFB7) {
if ((wire-CFB0)%2) return "CFB0_ILOGIC_SITE_S";
return "CFB0_ILOGIC_SITE";
}
if (wire >= CFB8 && wire <= CFB15) {
if ((wire-CFB8)%2) return "CFB1_ILOGIC_SITE_S";
return "CFB1_ILOGIC_SITE";
}
if (wire >= DFB0 && wire <= DFB7) {
if ((wire-DFB0)%2) return "DFB_ILOGIC_SITE_S";
return "DFB_ILOGIC_SITE";
}
if (wire >= DQSN0 && wire <= DQSN3) return "OUTN_IODELAY_SITE";
if (wire >= DQSP0 && wire <= DQSP3) return "OUTP_IODELAY_SITE";
return 0;
}
static int add_cfb_dfb_clkpin_dqsn_dqsp_sw(struct fpga_model *model, const struct w_net_i *net)
{
char wstr[MAX_WIRENAME_LEN];
int y, x, i;
RC_CHECK(model);
y = net->yx[net->num_yx-1].y;
x = net->yx[net->num_yx-1].x;
if (is_atx(X_INNER_LEFT|X_INNER_RIGHT, model, x)) {
for (i = 0; i <= net->wire_inc; i++) {
strcpy(wstr, fpga_connpt_str(model, net->wire+i, y, x, -1, -1));
if (net->wire >= CLKPIN0 && net->wire <= CLKPIN7)
add_switch(model, y, x, pf("%cTERM_IOB_IBUF%i",
x < model->center_x ? 'L' : 'R', i),
wstr, /*bidir*/ 0);
else
add_switch(model, y, x, pf("%s_%c",
wstr, x < model->center_x ? 'E' : 'W'),
wstr, /*bidir*/ 0);
}
} else if (is_atyx(YX_DEV_ILOGIC, model, y, x)) {
for (i = 0; i <= net->wire_inc; i++) {
const char *site_str = io_site_connpt(model, y, x, net->wire+i);
if (!site_str) continue;
add_switch(model, y, x, site_str,
fpga_connpt_str(model, net->wire+i, y, x, -1, -1),
/*bidir*/ 0);
}
}
RC_RETURN(model);
}
static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
enum extra_wires first_wire, int num_wires)
{
@ -784,11 +873,13 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
{{ .y = TOP_INNER_ROW, .x = model->center_x-CENTER_LOGIC_O },
{ .y = TOP_OUTER_IO, .x = model->center_x-CENTER_LOGIC_O }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
// bottom into outer io
net_mirror_y(model, &n);
n.wire = first_wire + num_wires/2;
add_conn_net_i(model, &n); }
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
// top into inner io
{ struct w_net_i n = { .wire = first_wire+num_wires/4, .wire_inc = num_wires/4-1, .num_yx = 3,
@ -796,11 +887,13 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
{ .y = TOP_OUTER_IO, .x = model->center_x-CENTER_LOGIC_O },
{ .y = TOP_INNER_IO, .x = model->center_x-CENTER_LOGIC_O }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
// bottom into inner io
net_mirror_y(model, &n);
n.wire = first_wire+num_wires-num_wires/4;
add_conn_net_i(model, &n); }
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
}
//
@ -827,11 +920,13 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
{{ .y = TOP_INNER_ROW, .x = model->center_x+CENTER_X_PLUS_2 },
{ .y = TOP_OUTER_IO, .x = model->center_x+CENTER_X_PLUS_2 }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
// bottom into outer io
net_mirror_y(model, &n);
n.wire = first_wire;
add_conn_net_i(model, &n); }
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
// top into inner io
{ struct w_net_i n = { .wire = first_wire+num_wires-num_wires/4, .wire_inc = num_wires/4-1, .num_yx = 3,
@ -839,17 +934,45 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
{ .y = TOP_OUTER_IO, .x = model->center_x+CENTER_X_PLUS_2 },
{ .y = TOP_INNER_IO, .x = model->center_x+CENTER_X_PLUS_2 }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
// bottom into inner io
net_mirror_y(model, &n);
n.wire = first_wire+num_wires/4;
add_conn_net_i(model, &n); }
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
}
//
// left and right center
//
// term: top side left center
{ struct w_net_i n = { .wire = first_wire+num_wires-num_wires/4, .wire_inc = num_wires/4-1, .num_yx = 6, .yx =
{{ .y = model->center_y, .x = LEFT_OUTER_COL },
{ .y = model->center_y, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_1, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_2, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_3, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_4, .x = LEFT_INNER_COL }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.num_yx--; // one less - remove CENTER_Y_MINUS_4
n.wire = first_wire+num_wires/2;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
// term: top side right center
n.num_yx++;
net_mirror_x(model, &n);
n.wire = first_wire;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.num_yx--; // one less - remove CENTER_Y_MINUS_4
n.wire = first_wire+num_wires/4;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
// term: bottom side left center
{ struct w_net_i n = { .wire = first_wire, .wire_inc = num_wires/4-1, .num_yx = 4,
{{ .y = model->center_y, .x = LEFT_OUTER_COL },
@ -857,9 +980,11 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
{ .y = model->center_y + CENTER_Y_PLUS_1, .x = LEFT_INNER_COL },
{ .y = model->center_y + CENTER_Y_PLUS_2, .x = LEFT_INNER_COL }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.num_yx--; // one less - remove CENTER_Y_PLUS_2
n.wire = first_wire+num_wires/4;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
// term: bottom side right center
n.num_yx++;
@ -867,31 +992,11 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
n.wire = first_wire+num_wires-num_wires/4;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.num_yx--; // one less - remove CENTER_Y_PLUS_2
n.wire = first_wire+num_wires/2;
add_conn_net_i(model, &n); }
// term: top side left center
{ struct w_net_i n = { .wire = first_wire+num_wires-num_wires/4, .wire_inc = num_wires/4-1, .num_yx = 6,
{{ .y = model->center_y, .x = LEFT_OUTER_COL },
{ .y = model->center_y, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_1, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_2, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_3, .x = LEFT_INNER_COL },
{ .y = model->center_y - CENTER_Y_MINUS_4, .x = LEFT_INNER_COL }}};
add_conn_net_i(model, &n);
n.num_yx--; // one less - remove CENTER_Y_MINUS_4
n.wire = first_wire+num_wires/2;
add_conn_net_i(model, &n);
// term: top side right center
n.num_yx++;
net_mirror_x(model, &n);
n.wire = first_wire;
add_conn_net_i(model, &n);
n.num_yx--; // one less - remove CENTER_Y_MINUS_4
n.wire = first_wire+num_wires/4;
add_conn_net_i(model, &n); }
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
if (first_wire != CLKPIN0) {
// io devs: left
@ -900,36 +1005,44 @@ static int add_cfb_dfb_clkpin_dqsn_dqsp_wires(struct fpga_model *model,
{ .y = model->center_y + CENTER_Y_PLUS_2, .x = LEFT_IO_ROUTING },
{ .y = model->center_y + CENTER_Y_PLUS_2, .x = LEFT_IO_DEVS }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.wire = first_wire+num_wires/4;
n.yx[0].y = n.yx[1].y = n.yx[2].y = model->center_y + CENTER_Y_PLUS_1;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.wire = first_wire+(num_wires/4)*2;
n.yx[0].y = n.yx[1].y = n.yx[2].y = model->center_y - CENTER_Y_MINUS_3;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.wire = first_wire+(num_wires/4)*3;
n.yx[0].y = n.yx[1].y = n.yx[2].y = model->center_y - CENTER_Y_MINUS_4;
add_conn_net_i(model, &n); }
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
// io devs: right
// io dev: right
{ struct w_net_i n = { .wire = first_wire, .wire_inc = num_wires/4-1, .num_yx = 2,
{{ .y = model->center_y - CENTER_Y_MINUS_4, .x = model->x_width - RIGHT_INNER_O },
{ .y = model->center_y - CENTER_Y_MINUS_4, .x = model->x_width - RIGHT_IO_DEVS_O }}};
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.wire = first_wire+num_wires/4;
n.yx[0].y = n.yx[1].y = model->center_y - CENTER_Y_MINUS_3;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.wire = first_wire+(num_wires/4)*2;
n.yx[0].y = n.yx[1].y = model->center_y + CENTER_Y_PLUS_1;
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n);
n.wire = first_wire+(num_wires/4)*3;
n.yx[0].y = n.yx[1].y = model->center_y + CENTER_Y_PLUS_2;
add_conn_net_i(model, &n); }
add_conn_net_i(model, &n);
add_cfb_dfb_clkpin_dqsn_dqsp_sw(model, &n); }
}
RC_RETURN(model);
}
@ -1206,23 +1319,46 @@ static int pcice_fill_net_io(struct fpga_model *model, struct w_net *net,
static int pcice_left_right_devs(struct fpga_model *model, int x)
{
int rc;
struct w_net net;
RC_CHECK(model);
// Connect the left and right center upwards and downwards
// one half-row including the subsequent hclk.
rc = pcice_fill_net_devs(model, &net, model->center_y - HCLK_POS - 1, model->center_y + HCLK_POS + 1, x);
if (rc) RC_FAIL(model, rc);
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) RC_FAIL(model, rc);
pcice_fill_net_devs(model, &net, model->center_y - HCLK_POS - 1, model->center_y + HCLK_POS + 1, x);
add_conn_net(model, NOPREF_BI_F, &net);
add_switch(model, TOP_INNER_ROW, x,
"IOI_PCICE_TB", "IOI_PCICE_EW", /*bidir*/ 0);
RC_ASSERT(model, model->center_y-HCLK_POS-1-ROW_SIZE == TOP_FIRST_REGULAR+HCLK_POS);
add_switch(model, TOP_FIRST_REGULAR+HCLK_POS, x,
"HCLK_PCI_CE_SPLIT", "HCLK_PCI_CE_INOUT", /*bidir*/ 0);
add_switch(model, model->center_y-HCLK_POS-1, x,
"HCLK_PCI_CE_OUT", "HCLK_PCI_CE_IN", /*bidir*/ 0);
add_switch(model, model->center_y-HCLK_POS-1, x,
"HCLK_PCI_CE_TRUNK_IN", "HCLK_PCI_CE_TRUNK_OUT", /*bidir*/ 0);
add_switch(model, model->center_y, x,
"REGH_IOI_PCI_CE", "REGH_IOI_PCICE_TB", /*bidir*/ 0);
// top-side net
rc = pcice_fill_net_devs(model, &net, TOP_INNER_ROW, model->center_y - HCLK_POS - 1, x);
if (rc) RC_FAIL(model, rc);
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) RC_FAIL(model, rc);
pcice_fill_net_devs(model, &net, TOP_INNER_ROW, model->center_y - HCLK_POS - 1, x);
add_conn_net(model, NOPREF_BI_F, &net);
// bottom-side net
rc = pcice_fill_net_devs(model, &net, model->center_y + HCLK_POS + 1, model->y_height - BOT_INNER_ROW, x);
if (rc) RC_FAIL(model, rc);
if ((rc = add_conn_net(model, NOPREF_BI_F, &net))) RC_FAIL(model, rc);
pcice_fill_net_devs(model, &net, model->center_y + HCLK_POS + 1, model->y_height - BOT_INNER_ROW, x);
add_conn_net(model, NOPREF_BI_F, &net);
RC_ASSERT(model, model->y_height-BOT_LAST_REGULAR_O-HCLK_POS-ROW_SIZE == model->center_y+1+HCLK_POS);
add_switch(model, model->center_y+1+HCLK_POS, x,
"HCLK_PCI_CE_IN", "HCLK_PCI_CE_OUT", /*bidir*/ 0);
add_switch(model, model->center_y+1+HCLK_POS, x,
"HCLK_PCI_CE_TRUNK_OUT", "HCLK_PCI_CE_TRUNK_IN", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_LAST_REGULAR_O-HCLK_POS, x,
"HCLK_PCI_CE_SPLIT", "HCLK_PCI_CE_INOUT", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_INNER_ROW, x,
"IOI_PCICE_TB", "IOI_PCICE_EW", /*bidir*/ 0);
RC_RETURN(model);
}

2
libs/model_helper.c
View File

@ -850,6 +850,8 @@ const char *fpga_connpt_str(struct fpga_model *model, enum extra_wires wire,
const char *wstr;
int i, wnum, wchar;
if (dest_y == -1) dest_y = y;
if (dest_x == -1) dest_x = x;
last_buf = (last_buf+1)%NUM_BUFS;
buf[last_buf][0] = 0;

326
libs/model_switches.c
View File

@ -9,6 +9,20 @@
#include "model.h"
#include "parts.h"
static int centx_gtp(struct fpga_model *model);
static int centy_pci_rdy(struct fpga_model *model);
static int dev_oct_calibrate(struct fpga_model *model, int y, int x, int index);
static int dev_dna(struct fpga_model *model);
static int dev_pmv(struct fpga_model *model);
static int dev_icap(struct fpga_model *model);
static int dev_spi_access(struct fpga_model *model);
static int dev_post_crc(struct fpga_model *model);
static int dev_startup(struct fpga_model *model);
static int dev_slave_spi(struct fpga_model *model);
static int dev_suspend_sync(struct fpga_model *model);
static int centy_bram_ckpin(struct fpga_model *model);
static int pcice_sw(struct fpga_model *model);
static int term_to_io_sw(struct fpga_model *model, enum extra_wires wire);
static int init_ce_clk(struct fpga_model *model);
static int init_io(struct fpga_model *model);
static int init_routing(struct fpga_model *model);
@ -35,8 +49,34 @@ int init_switches(struct fpga_model *model, int routing_sw)
{
RC_CHECK(model);
centx_gtp(model);
centy_pci_rdy(model);
dev_oct_calibrate(model, TOP_FIRST_REGULAR, LEFT_IO_DEVS, /*idx*/ 0);
dev_oct_calibrate(model, TOP_FIRST_REGULAR, LEFT_IO_DEVS, /*idx*/ 1);
dev_oct_calibrate(model, model->y_height - BOT_LAST_REGULAR_O, LEFT_IO_DEVS, /*idx*/ 0);
dev_oct_calibrate(model, model->y_height - BOT_LAST_REGULAR_O, LEFT_IO_DEVS, /*idx*/ 1);
dev_oct_calibrate(model, TOP_FIRST_REGULAR+1, model->x_width-RIGHT_IO_DEVS_O, /*idx*/ 0);
dev_oct_calibrate(model, model->y_height - BOT_LAST_REGULAR_O, model->x_width-RIGHT_IO_DEVS_O, /*idx*/ 0);
dev_dna(model);
dev_pmv(model);
dev_icap(model);
dev_spi_access(model);
dev_post_crc(model);
dev_startup(model);
dev_slave_spi(model);
dev_suspend_sync(model);
centy_bram_ckpin(model);
pcice_sw(model);
term_to_io_sw(model, IOCE);
term_to_io_sw(model, IOCLK);
term_to_io_sw(model, PLLCE);
term_to_io_sw(model, PLLCLK);
if (routing_sw)
init_routing(model);
init_logic(model);
init_iologic(model);
init_north_south_dirwire_term(model);
@ -61,6 +101,292 @@ int init_switches(struct fpga_model *model, int routing_sw)
RC_RETURN(model);
}
static int centx_gtp(struct fpga_model *model)
{
RC_CHECK(model);
add_switch(model, TOP_INNER_ROW, model->center_x-CENTER_CMTPLL_O,
"REGT_TTERM_GTP_CLKOUTEW0",
"REGT_TTERM_ALTGTP_CLKINEAST0", /*bidir*/ 0);
add_switch(model, TOP_INNER_ROW, model->center_x-CENTER_CMTPLL_O,
"REGT_TTERM_ALTGTP_CLKOUTEW0",
"REGT_TTERM_GTP_CLKINWEST0", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_INNER_ROW, model->center_x-CENTER_CMTPLL_O,
"REGB_BTERM_GTP_CLKOUTEW0",
"REGB_BTERM_ALTGTP_CLKINEAST0", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_INNER_ROW, model->center_x-CENTER_CMTPLL_O,
"REGB_BTERM_ALTGTP_CLKOUTEW0",
"REGB_BTERM_GTP_CLKINWEST0", /*bidir*/ 0);
RC_RETURN(model);
}
static int centy_pci_rdy(struct fpga_model *model)
{
RC_CHECK(model);
add_switch(model, model->center_y-CENTER_Y_MINUS_3, LEFT_OUTER_COL,
"LIOB_TOP_PCI_RDY0", "LIOB_PCICE_TRDY_EXT", /*bidir*/ 0);
add_switch(model, model->center_y+CENTER_Y_PLUS_1, LEFT_OUTER_COL,
"LIOB_BOT_PCI_RDY0", "LIOB_PCI_IT_RDY", /*bidir*/ 0);
add_switch(model, model->center_y-CENTER_Y_MINUS_3, model->x_width-RIGHT_OUTER_O,
"RIOB_BOT_PCI_RDY0", "RIOB_PCI_IT_RDY", /*bidir*/ 0);
add_switch(model, model->center_y+CENTER_Y_PLUS_1, model->x_width-RIGHT_OUTER_O,
"RIOB_TOP_PCI_RDY1", "RIOB_PCI_TRDY_EXT", /*bidir*/ 0);
RC_RETURN(model);
}
static int dev_oct_calibrate(struct fpga_model *model, int y, int x, int index)
{
static const int logicin_wnums[4] = {/*i0*/ 29, 32, /*i1*/ 15, 7};
RC_CHECK(model);
add_switch(model, y, x,
pf("INT_INTERFACE_LOCAL_LOGICBIN%i", logicin_wnums[index*2]),
pf("OCT_CALIBRATE%s_SO_PINWIRE", index ? "1" : ""),
/*bidir*/ 0);
add_switch(model, y, x,
pf("INT_INTERFACE_LOCAL_LOGICBIN%i", logicin_wnums[index*2+1]),
pf("OCT_CALIBRATE%s_S1_PINWIRE", index ? "1" : ""),
/*bidir*/ 0);
RC_RETURN(model);
}
static int dev_dna(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_CLK0", "DNA_PORT_CLK_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN14", "DNA_PORT_TEST_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN31", "DNA_PORT_READ_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN39", "DNA_PORT_DIN_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN8", "DNA_PORT_SHIFT_PINWIRE",
"DNA_PORT_DOUT_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_23",
"" };
RC_CHECK(model);
add_switch_set(model, TOP_OUTER_IO, LEFT_IO_DEVS,
/*prefix*/ 0, pairs, /*inc*/ 0);
RC_RETURN(model);
}
static int dev_pmv(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_LOGICBIN20", "PMV_ENABLEB_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN54", "PMV_SELECTB0_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN48", "PMV_SELECTB1_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN23", "PMV_SELECTB2_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN57", "PMV_SELECTB3_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN44", "PMV_SELECTB4_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN4", "PMV_SELECTB5_PINWIRE",
"PMV_OUT_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_0",
"PMV_OUT_DIV2_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_1",
"PMV_OUT_DIV4_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_2",
"" };
RC_CHECK(model);
add_switch_set(model, TOP_OUTER_IO, LEFT_IO_DEVS,
/*prefix*/ 0, pairs, /*inc*/ 0);
RC_RETURN(model);
}
static int dev_icap(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_CLK1", "ICAP_CLK_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN7", "ICAP_CE_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN42", "ICAP_WRITE_PINWIRE",
"ICAP_BUSY_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_3",
"" };
static const int icap_in_wnums[] =
{16, 5, 12, 47, 20, 45, 36, 17, 25, 34, 54, 48, 23, 57, 44, 4};
int i;
RC_CHECK(model);
add_switch_set(model, model->y_height-BOT_OUTER_IO, model->x_width-RIGHT_IO_DEVS_O,
/*prefix*/ 0, pairs, /*inc*/ 0);
for (i = 0; i <= 15; i++) {
add_switch(model, model->y_height-BOT_OUTER_IO,
model->x_width-RIGHT_IO_DEVS_O,
pf("INT_INTERFACE_LOCAL_LOGICBIN%i", icap_in_wnums[i]),
pf("ICAP_I%i_PINWIRE", i), /*bidir*/ 0);
add_switch(model, model->y_height-BOT_OUTER_IO,
model->x_width-RIGHT_IO_DEVS_O,
pf("ICAP_O%i_PINWIRE", i),
pf("INT_INTERFACE_LOCAL_LOGICOUT_%i", 4+i),
/*bidir*/ 0);
}
RC_RETURN(model);
}
static int dev_spi_access(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_CLK0", "SPI_ACCESS_CLK_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN24", "SPI_ACCESS_CSB_PINWIRE",
"INT_INTERFACE_LOCAL_SR0", "SPI_ACCESS_MOSI_PINWIRE",
"SPI_ACCESS_MISO_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_1",
"" };
RC_CHECK(model);
add_switch_set(model, model->y_height-BOT_OUTER_IO,
model->x_width-RIGHT_IO_DEVS_O, /*prefix*/ 0, pairs, /*inc*/ 0);
RC_RETURN(model);
}
static int dev_post_crc(struct fpga_model *model)
{
RC_CHECK(model);
add_switch(model, model->y_height-BOT_INNER_IO,
model->x_width-RIGHT_IO_DEVS_O,
"POST_CRC_CRCERROR_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICOUT_8",
/*bidir*/ 0);
RC_RETURN(model);
}
static int dev_startup(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_CLK1", "STARTUP_CLK_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN1", "STARTUP_KEYCLEARB_PINWIRE",
"INT_INTERFACE_LOCAL_LOGICBIN24", "STARTUP_GTS_PINWIRE",
"INT_INTERFACE_LOCAL_SR1", "STARTUP_GSR_PINWIRE",
"STARTUP_CFGCLK_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_2",
"STARTUP_CFGMCLK_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_1",
"STARTUP_EOS_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_3",
"" };
RC_CHECK(model);
add_switch_set(model, model->y_height-BOT_INNER_IO,
model->x_width-RIGHT_IO_DEVS_O, /*prefix*/ 0, pairs, /*inc*/ 0);
RC_RETURN(model);
}
static int dev_slave_spi(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_LOGICBIN15", "SLAVE_SPI_CMPMISO_PINWIRE",
"SLAVE_SPI_CMPACTIVEB_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_7",
"SLAVE_SPI_CMPCLK_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_4",
"SLAVE_SPI_CMPCSB_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_5",
"SLAVE_SPI_CMPMOSI_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_6",
"" };
RC_CHECK(model);
add_switch_set(model, model->y_height-BOT_INNER_IO,
model->x_width-RIGHT_IO_DEVS_O, /*prefix*/ 0, pairs, /*inc*/ 0);
RC_RETURN(model);
}
static int dev_suspend_sync(struct fpga_model *model)
{
static const char *pairs[] = {
"INT_INTERFACE_LOCAL_CLK0", "SUSPEND_SYNC_CLK_PINWIRE",
"INT_INTERFACE_LOCAL_SR0", "SUSPEND_SYNC_SACK_PINWIRE",
"SUSPEND_SYNC_SREQ_PINWIRE", "INT_INTERFACE_LOCAL_LOGICOUT_0",
"" };
RC_CHECK(model);
add_switch_set(model, model->y_height-BOT_INNER_IO,
model->x_width-RIGHT_IO_DEVS_O, /*prefix*/ 0, pairs, /*inc*/ 0);
RC_RETURN(model);
}
static int centy_bram_ckpin(struct fpga_model *model)
{
int x, i;
RC_CHECK(model);
for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) {
if (!is_atx(X_FABRIC_BRAM_COL, model, x))
continue;
for (i = 0; i <= 7; i++) {
add_switch(model, model->center_y, x,
pf("REGH_DSP_IN_CKPIN%i", i),
pf("REGH_DSP_OUT_CKPIN%i", i), /*bidir*/ 0);
}
}
RC_RETURN(model);
}
static int pcice_sw(struct fpga_model *model)
{
int x;
RC_CHECK(model);
for (x = LEFT_SIDE_WIDTH; x < model->x_width-RIGHT_SIDE_WIDTH; x++) {
if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
add_switch(model, TOP_INNER_ROW, x,
"BRAM_TTERM_PCICE_IN",
"BRAM_TTERM_PCICE_OUT", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_INNER_ROW, x,
"BRAM_TTERM_PCICE_IN",
"BRAM_TTERM_PCICE_OUT", /*bidir*/ 0);
} else if (is_atx(X_FABRIC_MACC_COL, model, x)) {
add_switch(model, TOP_INNER_ROW, x,
"MACCSITE2_TTERM_PCICE_IN",
"MACCSITE2_TTERM_PCICE_OUT", /*bidir*/ 0);
add_switch(model, model->y_height-BOT_INNER_ROW, x,
"MACCSITE2_TTERM_PCICE_IN",
"MACCSITE2_TTERM_PCICE_OUT", /*bidir*/ 0);
}
}
RC_RETURN(model);
}
static int term_to_io_x(struct fpga_model *model, enum extra_wires wire, int x)
{
const char *s1;
int last_inc, y, i;
RC_CHECK(model);
if (wire == IOCE) {
s1 = "IOCE";
last_inc = 3;
} else if (wire == IOCLK) {
s1 = "IOCLK";
last_inc = 3;
} else if (wire == PLLCE) {
s1 = "PLLCE";
last_inc = 1;
} else if (wire == PLLCLK) {
s1 = "PLLCLK";
last_inc = 1;
} else RC_FAIL(model, EINVAL);
for (y = TOP_FIRST_REGULAR; y <= model->y_height - BOT_LAST_REGULAR_O; y++) {
if (!is_aty(Y_ROW_HORIZ_AXSYMM, model, y))
continue;
// up
for (i = 1; i <= HALF_ROW; i++) {
if (is_aty((x < model->center_x) ? Y_LEFT_WIRED : Y_RIGHT_WIRED, model, y-i)) {
for (i = 0; i <= last_inc; i++) {
add_switch(model, y, x, pf("HCLK_IOIL_%s%i", s1, i),
pf("HCLK_IOIL_%s%i_UP", s1, i), /*bidir*/ 0);
}
break;
}
}
// down
for (i = 1; i <= HALF_ROW; i++) {
if (is_aty((x < model->center_x) ? Y_LEFT_WIRED : Y_RIGHT_WIRED, model, y+i)) {
for (i = 0; i <= last_inc; i++) {
add_switch(model, y, x, pf("HCLK_IOIL_%s%i", s1, i),
pf("HCLK_IOIL_%s%i_DOWN", s1, i), /*bidir*/ 0);
}
break;
}
}
}
RC_RETURN(model);
}
static int term_to_io_sw(struct fpga_model *model, enum extra_wires wire)
{
RC_CHECK(model);
term_to_io_x(model, wire, LEFT_IO_DEVS);
term_to_io_x(model, wire, model->x_width - RIGHT_IO_DEVS_O);
RC_RETURN(model);
}
static int init_logic_tile(struct fpga_model *model, int y, int x)
{
int rc, i, j, ml;