README update with some TODO plans

README

@@ -31,3 +31,28 @@ fpgatools Development Utilities
 - merge_seq          merges a pre-sorted text file into wire sequences
 - pair2net           reads the first two words per line and builds nets
 - hstrrep            high-speed hashed array based search and replace util
+
+TODO (as of 2012-08, expected time to delivery: months to years)
+
+* support chips other than xc6slx9, like slx45, slx150
+* support xc7a100
+* many more test cases for autotester
+* smarter autotester that can remember and verify groups of tests,
+  automatically oversee test execution, etc.
+* Debian packages libfpga, libfpga-doc, fpgatools
+* many more cases in logic block configuration
+* configuration of bram and macc blocks, bram initialization data
+* routing switches
+* many more cases in model of switches and inter-tile connections
+* write standard design elements for libfpga-design library
+* support lm32 or openrisc core, either via libfpga or iverilog backend
+* iverilog fpga backend
+
+ChangeLog
+
+2012-08-20
+* Beginning of full fidelity circle with model, floorplan, conversion from
+  and to bitstream format.
+
+2012-06-03
+* Project started.

bit_frames.c

@@ -154,10 +154,14 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
 				if (!(u64 & (1ULL<<1) && u64 & (1ULL<<2)
 				      && u64 & (1ULL<<7) && u64 & (1ULL<<21)
 				      && u64 & (1ULL<<22) && u64 & (1ULL<<36)
-				      && u64 & (1ULL<<37) && u64 & (1ULL<<39)))
+				      && u64 & (1ULL<<37) && u64 & (1ULL<<39))) {
+					HERE();
 					continue;
-				if (u64 & ~(0x000000B000600086ULL))
+				}
+				if (u64 & ~(0x000000B000600086ULL)) {
+					HERE();
 					continue;
+				}
 
 				// any logic block will enable r0ma17mi22b980
 				if (!get_bit(bits, /*row*/ 0, /*major*/ 17,