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minor testing and lut fixes, merge_log.sh helper script

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This commit is contained in:
Wolfgang Spraul 2012-08-29 03:15:31 +02:00
parent 3e5b83ed07
commit c852442ad3
11 changed files with 151 additions and 84 deletions
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82
autotest.c
View File

@ -181,13 +181,11 @@ static int test_net2(struct test_state* tstate, net_idx_t net_i)
net->el[i-1].idx, SW_FROM, same_sw, &same_len);
if (rc) FAIL(rc);
printf("same_len at this level %i\n", same_len);
#if 1
for (j = 0; j < same_len; j++) {
net->el[i-1].idx = same_sw[j];
rc = diff_printf(tstate);
if (rc) FAIL(rc);
}
#endif
*net = copy_net;
}
return 0;
@ -195,30 +193,27 @@ fail:
return rc;
}
static int test_all_logic_configs(struct test_state* tstate)
static int test_device_fingers(struct test_state* tstate, int y, int x,
int type, int type_idx, int test_inpins, int test_outpins)
{
struct fpga_device* dev;
struct switch_to_yx switch_to;
struct sw_chain chain;
net_idx_t net_idx;
int y, x, i, from_to, rc;
int i, from_to, rc;
// todo: goal: configure valid logic with as many possible in and out
// pins, for M and X device
y = 68;
x = 13;
rc = fdev_logic_set_lut(tstate->model, y, x,
DEV_LOGX, D6_LUT, "A3", ZTERM);
rc = fdev_set_required_pins(tstate->model, y, x, type, type_idx);
if (rc) FAIL(rc);
// fdev_print_required_pins(tstate->model, y, x, type, type_idx);
rc = fdev_set_required_pins(tstate->model, y, x, DEV_LOGIC, DEV_LOGX);
if (rc) FAIL(rc);
// fdev_print_required_pins(tstate->model, y, x, DEV_LOGIC, DEV_LOGX);
dev = fdev_p(tstate->model, y, x, DEV_LOGIC, DEV_LOGX);
dev = fdev_p(tstate->model, y, x, type, type_idx);
if (!dev) FAIL(EINVAL);
for (i = 0; i < dev->pinw_req_total; i++) {
if ((i < dev->pinw_req_in && !test_inpins)
|| (i >= dev->pinw_req_in && !test_outpins))
continue;
from_to = (i < dev->pinw_req_in) ? SW_TO : SW_FROM;
switch_to.yx_req = YX_ROUTING_TILE;
switch_to.flags = SWTO_YX_DEF;
@ -244,7 +239,7 @@ static int test_all_logic_configs(struct test_state* tstate)
// add port
rc = fpga_net_add_port(tstate->model, net_idx,
y, x, fpga_dev_idx(tstate->model, y, x,
DEV_LOGIC, DEV_LOGX), dev->pinw_req_for_cfg[i]);
type, type_idx), dev->pinw_req_for_cfg[i]);
if (rc) FAIL(rc);
// add (one) switch in logic tile
rc = fpga_net_add_switches(tstate->model, net_idx,
@ -267,6 +262,36 @@ fail:
return rc;
}
static int test_all_logic_configs(struct test_state* tstate)
{
int a_to_d[] = { A6_LUT, B6_LUT, C6_LUT, D6_LUT };
int idx_enum[] = { DEV_LOGM, DEV_LOGX };
int y, x, i, j, k, rc;
// todo: goal: configure valid logic with as many possible in and out
// pins, for M and X device
y = 68;
x = 13;
for (i = 0; i < sizeof(idx_enum)/sizeof(*idx_enum); i++) {
for (j = 0; j < sizeof(a_to_d)/sizeof(*a_to_d); j++) {
for (k = '1'; k <= '6'; k++) {
rc = fdev_logic_set_lut(tstate->model, y, x,
idx_enum[i], a_to_d[j], pf("A%c", k), ZTERM);
if (rc) FAIL(rc);
rc = test_device_fingers(tstate, y, x, DEV_LOGIC,
idx_enum[i], /*in*/ 1, /*out*/ k=='1');
if (rc) FAIL(rc);
fdev_delete(tstate->model, y, x, DEV_LOGIC, idx_enum[i]);
}
}
}
return 0;
fail:
return rc;
}
int main(int argc, char** argv)
{
struct fpga_model model;
@ -304,6 +329,19 @@ int main(int argc, char** argv)
mkdir(tstate.tmp_dir, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
rc = diff_start(&tstate, "and");
if (rc) FAIL(rc);
// test_logic_config
// test_logic_routing_switches
// test_iob_config
// test_iologic_routing_switches
#if 0
rc = test_all_logic_configs(&tstate);
if (rc) FAIL(rc);
#endif
printf_swchain(&model, 69, 13, strarray_find(&model.str, "BIOI_INNER_IBUF0"), SW_FROM, MAX_SW_DEPTH);
// printf_swchain(&model, 68, 12, strarray_find(&model.str, "NR1E0"), SW_FROM, MAX_SW_DEPTH);
#if 0
// configure P46
@ -329,12 +367,8 @@ int main(int argc, char** argv)
P48_dev->iob.O_used = 1;
P48_dev->iob.slew = SLEW_SLOW;
P48_dev->iob.suspend = SUSP_3STATE;
#endif
// configure logic
// todo: goal: configure valid logic with as many possible in and out
// pins, for M and X device
#if 0
logic_dev_idx = fpga_dev_idx(&model, /*y*/ 68, /*x*/ 13,
DEV_LOGIC, DEV_LOGX);
if (logic_dev_idx == NO_DEV) FAIL(EINVAL);
@ -343,16 +377,10 @@ int main(int argc, char** argv)
logic_dev->logic.D_used = 1;
rc = fpga_set_lut(&model, logic_dev, D6_LUT, "A3", ZTERM);
if (rc) FAIL(rc);
#endif
rc = test_all_logic_configs(&tstate);
if (rc) FAIL(rc);
#if 0
rc = diff_printf(&tstate);
if (rc) FAIL(rc);
#endif
#if 0
// configure net from P46.I to logic.D3
rc = fpga_net_new(&model, &P46_net);
if (rc) FAIL(rc);

97
bit_frames.c
View File

@ -147,6 +147,69 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
byte_off = row_pos * 8;
if (row_pos >= 8) byte_off += HCLK_BYTES;
// M device
dev_idx = fpga_dev_idx(model, y, x, DEV_LOGIC, DEV_LOGM);
if (dev_idx == NO_DEV) FAIL(EINVAL);
dev = FPGA_DEV(model, y, x, dev_idx);
// A6_LUT
if (frame_get_u32(u8_p + 24*FRAME_SIZE + byte_off + 4)
|| frame_get_u32(u8_p + 25*FRAME_SIZE + byte_off + 4)) {
u64 = read_lut64(u8_p + 24*FRAME_SIZE, (byte_off+4)*8);
{ int logic_base[6] = {0,1,0,0,1,0};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
if (*lut_str) {
rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
A6_LUT, lut_str, ZTERM);
if (rc) FAIL(rc);
*(uint32_t*)(u8_p+24*FRAME_SIZE+byte_off+4) = 0;
*(uint32_t*)(u8_p+25*FRAME_SIZE+byte_off+4) = 0;
}
}
// B6_LUT
if (frame_get_u32(u8_p + 21*FRAME_SIZE + byte_off + 4)
|| frame_get_u32(u8_p + 22*FRAME_SIZE + byte_off + 4)) {
u64 = read_lut64(u8_p + 21*FRAME_SIZE, (byte_off+4)*8);
{ int logic_base[6] = {1,1,0,1,0,1};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
if (*lut_str) {
rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
B6_LUT, lut_str, ZTERM);
if (rc) FAIL(rc);
*(uint32_t*)(u8_p+21*FRAME_SIZE+byte_off+4) = 0;
*(uint32_t*)(u8_p+22*FRAME_SIZE+byte_off+4) = 0;
}
}
// C6_LUT
if (frame_get_u32(u8_p + 24*FRAME_SIZE + byte_off)
|| frame_get_u32(u8_p + 25*FRAME_SIZE + byte_off)) {
u64 = read_lut64(u8_p + 24*FRAME_SIZE, byte_off*8);
{ int logic_base[6] = {0,1,0,0,1,0};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
if (*lut_str) {
rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
C6_LUT, lut_str, ZTERM);
if (rc) FAIL(rc);
*(uint32_t*)(u8_p+24*FRAME_SIZE+byte_off) = 0;
*(uint32_t*)(u8_p+25*FRAME_SIZE+byte_off) = 0;
}
}
// D6_LUT
if (frame_get_u32(u8_p + 21*FRAME_SIZE + byte_off)
|| frame_get_u32(u8_p + 22*FRAME_SIZE + byte_off)) {
u64 = read_lut64(u8_p + 21*FRAME_SIZE, byte_off*8);
{ int logic_base[6] = {1,1,0,1,0,1};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 1); }
if (*lut_str) {
rc = fdev_logic_set_lut(model, y, x, DEV_LOGM,
D6_LUT, lut_str, ZTERM);
if (rc) FAIL(rc);
*(uint32_t*)(u8_p+21*FRAME_SIZE+byte_off) = 0;
*(uint32_t*)(u8_p+22*FRAME_SIZE+byte_off) = 0;
}
}
// X device
u64 = frame_get_u64(u8_p + 26*FRAME_SIZE + byte_off);
if ( u64 ) {
// 21, 22, 36 and 37 are actually not default
@ -170,6 +233,7 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
dev = FPGA_DEV(model, y, x, dev_idx);
*(uint64_t*)(u8_p+26*FRAME_SIZE+byte_off) = 0;
// A6_LUT
u64 = read_lut64(u8_p + 27*FRAME_SIZE, (byte_off+4)*8);
{ int logic_base[6] = {1,1,0,1,1,0};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
@ -180,6 +244,7 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
*(uint32_t*)(u8_p+27*FRAME_SIZE+byte_off+4) = 0;
*(uint32_t*)(u8_p+28*FRAME_SIZE+byte_off+4) = 0;
}
// B6_LUT
u64 = read_lut64(u8_p + 29*FRAME_SIZE, (byte_off+4)*8);
{ int logic_base[6] = {1,1,0,1,1,0};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
@ -189,6 +254,7 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
*(uint32_t*)(u8_p+29*FRAME_SIZE+byte_off+4) = 0;
*(uint32_t*)(u8_p+30*FRAME_SIZE+byte_off+4) = 0;
}
// C6_LUT
u64 = read_lut64(u8_p + 27*FRAME_SIZE, byte_off*8);
{ int logic_base[6] = {0,1,0,0,0,1};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
@ -198,6 +264,7 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
*(uint32_t*)(u8_p+27*FRAME_SIZE+byte_off) = 0;
*(uint32_t*)(u8_p+28*FRAME_SIZE+byte_off) = 0;
}
// D6_LUT
u64 = read_lut64(u8_p + 29*FRAME_SIZE, byte_off*8);
{ int logic_base[6] = {0,1,0,0,0,1};
lut_str = lut2bool(u64, 64, &logic_base, /*flip_b0*/ 0); }
@ -207,36 +274,6 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
*(uint32_t*)(u8_p+29*FRAME_SIZE+byte_off) = 0;
*(uint32_t*)(u8_p+30*FRAME_SIZE+byte_off) = 0;
}
#if 0
// M-LUTs
lut64 = read_lut64(&maj_bits[24*130], frame_off+32);
{ int logic_base[6] = {0,1,0,0,1,0};
lut_str = lut2bool(lut64, 64, &logic_base, 1 /* flip_b0 */); }
if (*lut_str)
printf("r%i ma%i clb i%i s0_A6LUT \"%s\"\n",
row, major, i-start, lut_str);
lut64 = read_lut64(&maj_bits[21*130], frame_off+32);
{ int logic_base[6] = {1,1,0,1,0,1};
lut_str = lut2bool(lut64, 64, &logic_base, 1 /* flip_b0 */); }
if (*lut_str)
printf("r%i ma%i clb i%i s0_B6LUT \"%s\"\n",
row, major, i-start, lut_str);
lut64 = read_lut64(&maj_bits[24*130], frame_off);
{ int logic_base[6] = {0,1,0,0,1,0};
lut_str = lut2bool(lut64, 64, &logic_base, 1 /* flip_b0 */); }
if (*lut_str)
printf("r%i ma%i clb i%i s0_C6LUT \"%s\"\n",
row, major, i-start, lut_str);
lut64 = read_lut64(&maj_bits[21*130], frame_off);
{ int logic_base[6] = {1,1,0,1,0,1};
lut_str = lut2bool(lut64, 64, &logic_base, 1 /* flip_b0 */); }
if (*lut_str)
printf("r%i ma%i clb i%i s0_D6LUT \"%s\"\n",
row, major, i-start, lut_str);
#endif
}
}
}

5
bit_regs.c
View File

@ -718,14 +718,15 @@ static void printf_routing_2minors(uint8_t* bits, int row, int major,
{
int y, i, hclk;
uint64_t u64_0, u64_1;
char bit_str[128];
char bit_str[129];
bit_str[128] = 0;
for (y = 0; y < 16; y++) {
hclk = (y < 8) ? 0 : 2;
u64_0 = frame_get_u64(bits + y*8 + hclk);
u64_1 = frame_get_u64(bits + y*8 + hclk + FRAME_SIZE);
if (u64_0 || u64_1) {
for (i = 0; i < sizeof(bit_str); i++)
for (i = 0; i < 128; i++)
bit_str[i] = '0';
for (i = 0; i < 64; i++) {
if (u64_0 & (1ULL << i))

4
control.c
View File

@ -819,13 +819,15 @@ int fpga_switch_chain(struct sw_chain* chain)
// one level down for each member. This sorts the
// returned switches in a nice way.
chain->first_round = 1;
chain->prior_parents = 0;
chain->num_prior_parents = 0;
return 0;
}
if (!chain->set.len) {
HERE(); goto internal_error;
}
if (chain->first_round) {
// first go through all members are present level
// first go through all members at present level
idx = fpga_switch_next(chain->model, chain->y, chain->x,
chain->set.sw[chain->set.len-1], chain->from_to);
if (idx != NO_SWITCH) {

6
control.h
View File

@ -106,6 +106,10 @@ void fpga_switch_disable(struct fpga_model* model, int y, int x,
const char* fmt_swset(struct fpga_model* model, int y, int x,
struct sw_set* set, int from_to);
// MAX_PRIOR_PARENTS should be larger than the largest known
// numer of switches in a tile, currently 3459 in a slx9 routing tile.
#define MAX_PRIOR_PARENTS 4000
struct sw_chain
{
// start and recurring values:
@ -122,6 +126,8 @@ struct sw_chain
// internal:
int first_round;
swidx_t* prior_parents;
int num_prior_parents;
};
// Returns 0 if another switchset is returned in chain, or

8
floorplan.c
View File

@ -629,8 +629,8 @@ static void read_net_line(struct fpga_model* model, const char* line, int start)
}
memcpy(buf, &line[from_beg], from_end-from_beg);
buf[from_end-from_beg] = 0;
if (strarray_find(&model->str, buf, &from_str_i)
|| from_str_i == STRIDX_NO_ENTRY) {
from_str_i = strarray_find(&model->str, buf);
if (from_str_i == STRIDX_NO_ENTRY) {
HERE();
return;
}
@ -646,8 +646,8 @@ static void read_net_line(struct fpga_model* model, const char* line, int start)
}
memcpy(buf, &line[to_beg], to_end-to_beg);
buf[to_end-to_beg] = 0;
if (strarray_find(&model->str, buf, &to_str_i)
|| to_str_i == STRIDX_NO_ENTRY) {
to_str_i = strarray_find(&model->str, buf);
if (to_str_i == STRIDX_NO_ENTRY) {
HERE();
return;
}

13
helper.c
View File

@ -819,7 +819,7 @@ const char* strarray_lookup(struct hashed_strarray* array, int idx)
return &array->bin_strings[bin][offset];
}
int strarray_find(struct hashed_strarray* array, const char* str, int* idx)
int strarray_find(struct hashed_strarray* array, const char* str)
{
int bin, search_off, i;
uint32_t hash;
@ -834,16 +834,14 @@ int strarray_find(struct hashed_strarray* array, const char* str, int* idx)
i = *(uint32_t*)&array->bin_strings[bin][search_off-6];
if (!i) {
fprintf(stderr, "Internal error - index 0.\n");
return -1;
return STRIDX_NO_ENTRY;
}
*idx = i+1;
return 0;
return i+1;
}
search_off += *(uint16_t*)&array->bin_strings[bin][search_off-2];
}
}
*idx = STRIDX_NO_ENTRY;
return 0;
return STRIDX_NO_ENTRY;
}
int s_stash_at_bin(struct hashed_strarray* array, const char* str, int idx, int bin);
@ -853,8 +851,7 @@ int strarray_add(struct hashed_strarray* array, const char* str, int* idx)
int bin, i, free_index, rc, start_index;
unsigned long hash;
rc = strarray_find(array, str, idx);
if (rc) return rc;
*idx = strarray_find(array, str);
if (*idx != STRIDX_NO_ENTRY) return 0;
hash = hash_djb2((const unsigned char*) str);

2
helper.h
View File

@ -130,7 +130,7 @@ const char* strarray_lookup(struct hashed_strarray* array, int idx);
// The found or created index will never be 0, so the caller
// can use 0 as a special value to indicate 'no string'.
#define STRIDX_NO_ENTRY 0
int strarray_find(struct hashed_strarray* array, const char* str, int* idx);
int strarray_find(struct hashed_strarray* array, const char* str);
int strarray_add(struct hashed_strarray* array, const char* str, int* idx);
// If you stash a string to a fixed index, you cannot use strarray_find()
// anymore, only strarray_lookup().

6
hstrrep.c
View File

@ -85,11 +85,7 @@ int main(int argc, char** argv)
next_wrd = strtok_r(line, " \n", &lasts);
if (next_wrd) {
do {
rc = strarray_find(&search_arr, next_wrd, &search_idx);
if (rc) {
fprintf(stderr, "Internal error in %s:%i\n", __FILE__, __LINE__);
goto xout;
}
search_idx = strarray_find(&search_arr, next_wrd);
if (search_idx == STRIDX_NO_ENTRY)
fputs(next_wrd, stdout);
else {

3
merge_log.sh Executable file
View File

@ -0,0 +1,3 @@
#!/bin/bash
grep '^+net\|^+r0.*v64_'|awk '/^+r0.*v64_/{printf "%s %s\n",$0,x};{x=$0};'|sort

9
model_helper.c
View File

@ -57,8 +57,7 @@ int has_connpt(struct fpga_model* model, int y, int x,
uint16_t name_i;
int i;
if (strarray_find(&model->str, name, &i))
EXIT(1);
i = strarray_find(&model->str, name);
if (i == STRIDX_NO_ENTRY)
return 0;
name_i = i;
@ -337,10 +336,8 @@ int add_switch(struct fpga_model* model, int y, int x, const char* from,
rc = strarray_add(&model->str, to, &to_idx);
if (rc) goto xout;
#else
rc = strarray_find(&model->str, from, &from_idx);
if (rc) goto xout;
rc = strarray_find(&model->str, to, &to_idx);
if (rc) goto xout;
from_idx = strarray_find(&model->str, from);
to_idx = strarray_find(&model->str, to);
#endif
if (from_idx == STRIDX_NO_ENTRY || to_idx == STRIDX_NO_ENTRY) {
fprintf(stderr, "No string for switch from %s (%i) or %s (%i).\n",