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renamed fpga_net to fnet, added hello_world

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This commit is contained in:
Wolfgang Spraul 2012-09-17 14:05:27 +02:00
parent 81e9f80f55
commit cf49add9e7
8 changed files with 252 additions and 73 deletions
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1
.gitignore vendored
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@ -27,6 +27,7 @@ pair2net
autotest
fp2bit
bit2fp
hello_world
#
# folders

6
Makefile
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@ -66,8 +66,8 @@ DYNAMIC_HEADS = bit.h control.h floorplan.h helper.h model.h parts.h
#- libfpga-test autotest suite
#- libfpga-design larger design elements on top of libfpga-control
all: new_fp fp2bit bit2fp draw_svg_tiles \
autotest hstrrep sort_seq merge_seq pair2net
all: new_fp fp2bit bit2fp draw_svg_tiles autotest hstrrep \
sort_seq merge_seq pair2net hello_world
test: test_logic_cfg test_routing_sw
@ -85,6 +85,8 @@ autotest_%.log: autotest fp2bit bit2fp
autotest: autotest.o $(DYNAMIC_LIBS)
hello_world: hello_world.o $(DYNAMIC_LIBS)
fp2bit: fp2bit.o $(DYNAMIC_LIBS)
bit2fp: bit2fp.o $(DYNAMIC_LIBS)

70
autotest.c
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@ -196,16 +196,16 @@ static int test_logic_net(struct test_state* tstate, int logic_y, int logic_x,
int dbg, rc;
dbg = 0;
rc = fpga_net_new(tstate->model, &net_idx);
rc = fnet_new(tstate->model, &net_idx);
if (rc) FAIL(rc);
// add port
rc = fpga_net_add_port(tstate->model, net_idx, logic_y, logic_x,
rc = fnet_add_port(tstate->model, net_idx, logic_y, logic_x,
DEV_LOGIC, type_idx, port);
if (rc) FAIL(rc);
// add (one) switch in logic tile
rc = fpga_net_add_sw(tstate->model, net_idx,
rc = fnet_add_sw(tstate->model, net_idx,
logic_y, logic_x, logic_switch_set->sw, logic_switch_set->len);
if (rc) FAIL(rc);
@ -215,7 +215,7 @@ static int test_logic_net(struct test_state* tstate, int logic_y, int logic_x,
routing_switches.sw[routing_switches.len++] = routing_sw1;
if (routing_sw2 != NO_SWITCH)
routing_switches.sw[routing_switches.len++] = routing_sw2;
rc = fpga_net_add_sw(tstate->model, net_idx,
rc = fnet_add_sw(tstate->model, net_idx,
routing_y, routing_x, routing_switches.sw, routing_switches.len);
if (rc) FAIL(rc);
@ -230,7 +230,7 @@ static int test_logic_net(struct test_state* tstate, int logic_y, int logic_x,
rc = diff_printf(tstate);
if (rc) FAIL(rc);
fpga_net_delete(tstate->model, net_idx);
fnet_delete(tstate->model, net_idx);
return 0;
fail:
return rc;
@ -439,7 +439,7 @@ static int test_switches(struct test_state* tstate, int y, int x,
if (rc) FAIL(rc);
// add len-4 wire
rc = fpga_net_add_sw(tstate->model, net, y, x,
rc = fnet_add_sw(tstate->model, net, y, x,
&sw_set.sw[i], 1);
if (rc) FAIL(rc);
@ -477,7 +477,7 @@ static int test_switches(struct test_state* tstate, int y, int x,
if (rc) FAIL(rc);
// add len-4 target
rc = fpga_net_add_sw(tstate->model, net, y, x,
rc = fnet_add_sw(tstate->model, net, y, x,
&w4_set.sw[j], 1);
if (rc) FAIL(rc);
@ -486,11 +486,11 @@ static int test_switches(struct test_state* tstate, int y, int x,
rc = diff_printf(tstate);
if (rc) FAIL(rc);
rc = fpga_net_remove_sw(tstate->model, net, y, x,
rc = fnet_remove_sw(tstate->model, net, y, x,
&w4_set.sw[j], 1);
if (rc) FAIL(rc);
}
rc = fpga_net_remove_sw(tstate->model, net, y, x,
rc = fnet_remove_sw(tstate->model, net, y, x,
&sw_set.sw[i], 1);
if (rc) FAIL(rc);
}
@ -517,9 +517,9 @@ int test_routing_sw_from_iob(struct test_state* tstate,
iob_dev = fdev_p(tstate->model, iob_y, iob_x, DEV_IOB, iob_type_idx);
if (!iob_dev) FAIL(EINVAL);
rc = fpga_net_new(tstate->model, &net);
rc = fnet_new(tstate->model, &net);
if (rc) FAIL(rc);
rc = fpga_net_add_port(tstate->model, net, iob_y, iob_x,
rc = fnet_add_port(tstate->model, net, iob_y, iob_x,
DEV_IOB, iob_type_idx, IOB_IN_O);
if (rc) FAIL(rc);
@ -534,7 +534,7 @@ int test_routing_sw_from_iob(struct test_state* tstate,
if (rc) FAIL(rc);
if (tstate->dry_run)
printf_switch_to_yx_result(&switch_to);
rc = fpga_net_add_sw(tstate->model, net, switch_to.y,
rc = fnet_add_sw(tstate->model, net, switch_to.y,
switch_to.x, switch_to.set.sw, switch_to.set.len);
if (rc) FAIL(rc);
@ -547,7 +547,7 @@ int test_routing_sw_from_iob(struct test_state* tstate,
switch_to.from_to = SW_TO;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fpga_net_add_sw(tstate->model, net, switch_to.y,
rc = fnet_add_sw(tstate->model, net, switch_to.y,
switch_to.x, switch_to.set.sw, switch_to.set.len);
if (rc) FAIL(rc);
if (tstate->dry_run)
@ -564,7 +564,7 @@ int test_routing_sw_from_iob(struct test_state* tstate,
if (rc) FAIL(rc);
if (tstate->dry_run)
printf_switch_to_yx_result(&switch_to);
rc = fpga_net_add_sw(tstate->model, net, switch_to.y,
rc = fnet_add_sw(tstate->model, net, switch_to.y,
switch_to.x, switch_to.set.sw, switch_to.set.len);
if (rc) FAIL(rc);
@ -573,7 +573,7 @@ int test_routing_sw_from_iob(struct test_state* tstate,
if (rc) FAIL(rc);
fdev_delete(tstate->model, iob_y, iob_x, DEV_IOB, iob_type_idx);
fpga_net_delete(tstate->model, net);
fnet_delete(tstate->model, net);
return 0;
fail:
return rc;
@ -611,9 +611,9 @@ static int test_routing_sw_from_logic(struct test_state* tstate,
if (!dev) FAIL(EINVAL);
if (!dev->pinw_req_in) FAIL(EINVAL);
rc = fpga_net_new(tstate->model, &net);
rc = fnet_new(tstate->model, &net);
if (rc) FAIL(rc);
rc = fpga_net_add_port(tstate->model, net, y, x,
rc = fnet_add_port(tstate->model, net, y, x,
DEV_LOGIC, DEV_LOGM, dev->pinw_req_for_cfg[0]);
if (rc) FAIL(rc);
@ -631,7 +631,7 @@ static int test_routing_sw_from_logic(struct test_state* tstate,
if (!swto.set.len) FAIL(EINVAL);
if (tstate->dry_run)
printf_switch_to_rel_result(&swto);
rc = fpga_net_add_sw(tstate->model, net, swto.start_y,
rc = fnet_add_sw(tstate->model, net, swto.start_y,
swto.start_x, swto.set.sw, swto.set.len);
if (rc) FAIL(rc);
@ -648,7 +648,7 @@ static int test_routing_sw_from_logic(struct test_state* tstate,
if (strlen(str) < 5
|| str[2] != '1' || str[3] != 'B')
continue;
rc = fpga_net_add_sw(tstate->model, net, swto.dest_y,
rc = fnet_add_sw(tstate->model, net, swto.dest_y,
swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
if (rc) FAIL(rc);
if (tstate->dry_run)
@ -658,13 +658,13 @@ static int test_routing_sw_from_logic(struct test_state* tstate,
conns.dest_str_i, net, done_list, done_list_len);
if (rc) FAIL(rc);
rc = fpga_net_remove_sw(tstate->model, net, swto.dest_y,
rc = fnet_remove_sw(tstate->model, net, swto.dest_y,
swto.dest_x, conns.chain.set.sw, conns.chain.set.len);
if (rc) FAIL(rc);
}
destruct_sw_conns(&conns);
fdev_delete(tstate->model, y, x, DEV_LOGIC, DEV_LOGM);
fpga_net_delete(tstate->model, net);
fnet_delete(tstate->model, net);
}
}
return 0;
@ -802,22 +802,22 @@ static int test_iologic_switches2(struct test_state* tstate, int iob_y, int iob_
&chain.set, from_to));
// new net
rc = fpga_net_new(tstate->model, &net_idx);
rc = fnet_new(tstate->model, &net_idx);
if (rc) FAIL(rc);
// add iob port
rc = fpga_net_add_port(tstate->model, net_idx, iob_y, iob_x,
rc = fnet_add_port(tstate->model, net_idx, iob_y, iob_x,
DEV_IOB, iob_type_idx, IOB_IN_O);
if (rc) FAIL(rc);
// add switch in iob tile
rc = fpga_net_add_sw(tstate->model, net_idx, switch_to.y,
rc = fnet_add_sw(tstate->model, net_idx, switch_to.y,
switch_to.x, switch_to.set.sw, switch_to.set.len);
if (rc) FAIL(rc);
// add all but last switch in set
if (chain.set.len > 1) {
rc = fpga_net_add_sw(tstate->model, net_idx, switch_to.dest_y,
rc = fnet_add_sw(tstate->model, net_idx, switch_to.dest_y,
switch_to.dest_x, chain.set.sw, chain.set.len-1);
if (rc) FAIL(rc);
}
@ -825,14 +825,14 @@ static int test_iologic_switches2(struct test_state* tstate, int iob_y, int iob_
if (rc) FAIL(rc);
// add last switch
rc = fpga_net_add_sw(tstate->model, net_idx, switch_to.dest_y,
rc = fnet_add_sw(tstate->model, net_idx, switch_to.dest_y,
switch_to.dest_x, &chain.set.sw[chain.set.len-1], 1);
if (rc) FAIL(rc);
rc = diff_printf(tstate);
if (rc) FAIL(rc);
fpga_net_delete(tstate->model, net_idx);
fnet_delete(tstate->model, net_idx);
}
destruct_sw_chain(&chain);
}
@ -1032,12 +1032,12 @@ int main(int argc, char** argv)
net_idx_t P46_net;
// configure net from P46.I to logic.D3
rc = fpga_net_new(&model, &P46_net);
rc = fnet_new(&model, &P46_net);
if (rc) FAIL(rc);
rc = fpga_net_add_port(&model, P46_net, P46_y, P46_x,
rc = fnet_add_port(&model, P46_net, P46_y, P46_x,
P46_dev_idx, IOB_OUT_I);
if (rc) FAIL(rc);
rc = fpga_net_add_port(&model, P46_net, /*y*/ 68, /*x*/ 13,
rc = fnet_add_port(&model, P46_net, /*y*/ 68, /*x*/ 13,
logic_dev_idx, LI_D3);
if (rc) FAIL(rc);
@ -1050,7 +1050,7 @@ int main(int argc, char** argv)
switch_to.from_to = SW_FROM;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
@ -1063,7 +1063,7 @@ int main(int argc, char** argv)
switch_to.from_to = SW_FROM;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
@ -1076,7 +1076,7 @@ int main(int argc, char** argv)
switch_to.from_to = SW_FROM;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
@ -1105,7 +1105,7 @@ int main(int argc, char** argv)
}
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fpga_net_add_switches(&model, P46_net, switch_to.y,
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
@ -1120,7 +1120,7 @@ int main(int argc, char** argv)
.block_list = 0 };
if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
rc = fpga_net_add_switches(&model, P46_net, c.y, c.x, &c.set);
rc = fnet_add_switches(&model, P46_net, c.y, c.x, &c.set);
if (rc) FAIL(rc);
}
#endif

44
bit_frames.c
View File

@ -385,7 +385,6 @@ static int extract_routing_switches(struct extract_state* es, int y, int x)
int i, is_set, rc;
tile = YX_TILE(es->model, y, x);
if (y != 68 || x != 12) return 0;
for (i = 0; i < es->model->num_bitpos; i++) {
rc = bitpos_is_set(es, y, x, &es->model->sw_bitpos[i], &is_set);
@ -420,8 +419,6 @@ static int extract_switches(struct extract_state* es)
{
int x, y, rc;
// go through all tiles, look for one with switches
// go through each switch, lookup device, is_enabled() -> enable
for (x = 0; x < es->model->x_width; x++) {
for (y = 0; y < es->model->y_height; y++) {
if (is_atx(X_ROUTING_COL, es->model, x)
@ -473,9 +470,9 @@ int extract_model(struct fpga_model* model, struct fpga_bits* bits)
if (model->nets)
HERE(); // should be empty here
for (i = 0; i < es.num_yx_pos; i++) {
rc = fpga_net_new(model, &net_idx);
rc = fnet_new(model, &net_idx);
if (rc) FAIL(rc);
rc = fpga_net_add_sw(model, net_idx, es.yx_pos[i].y,
rc = fnet_add_sw(model, net_idx, es.yx_pos[i].y,
es.yx_pos[i].x, &es.yx_pos[i].idx, 1);
if (rc) FAIL(rc);
}
@ -486,12 +483,9 @@ fail:
int printf_swbits(struct fpga_model* model)
{
struct extract_state es;
char bit_str[129];
int i, j, width, rc;
int i, j, width;
rc = construct_extract_state(&es, model);
if (rc) FAIL(rc);
for (i = 0; i < model->num_bitpos; i++) {
width = (model->sw_bitpos[i].minor == 20) ? 64 : 128;
@ -511,14 +505,40 @@ int printf_swbits(struct fpga_model* model)
model->sw_bitpos[i].bidir ? "<->" : "->");
}
return 0;
fail:
return rc;
}
static int write_switches(struct fpga_bits* bits, struct fpga_model* model)
{
int x, y, i;
struct fpga_tile* tile;
for (x = 0; x < model->x_width; x++) {
for (y = 0; y < model->y_height; y++) {
if (!is_atx(X_ROUTING_COL, model, x)
|| y < TOP_IO_TILES
|| y >= model->y_height-BOT_IO_TILES
|| is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
model, y))
continue;
tile = YX_TILE(model, y, x);
// go through enabled switches, lookup in sw_bitpos
// and set bits
for (i = 0; i < tile->num_switches; i++) {
}
}
}
return 0;
}
int write_model(struct fpga_bits* bits, struct fpga_model* model)
{
int i;
int i, rc;
for (i = 0; i < sizeof(s_default_bits)/sizeof(s_default_bits[0]); i++)
set_bitp(bits, &s_default_bits[i]);
rc = write_switches(bits, model);
if (rc) FAIL(rc);
return 0;
fail:
return rc;
}

26
control.c
View File

@ -1517,7 +1517,7 @@ void printf_switch_to_rel_result(struct switch_to_rel* p)
#define NET_ALLOC_INCREMENT 64
static int fpga_net_useidx(struct fpga_model* model, net_idx_t new_idx)
static int fnet_useidx(struct fpga_model* model, net_idx_t new_idx)
{
void* new_ptr;
int new_array_size, rc;
@ -1543,18 +1543,18 @@ fail:
return rc;
}
int fpga_net_new(struct fpga_model* model, net_idx_t* new_idx)
int fnet_new(struct fpga_model* model, net_idx_t* new_idx)
{
int rc;
// highest_used_net is initialized to NO_NET which becomes 1
rc = fpga_net_useidx(model, model->highest_used_net+1);
rc = fnet_useidx(model, model->highest_used_net+1);
if (rc) return rc;
*new_idx = model->highest_used_net;
return 0;
}
void fpga_net_delete(struct fpga_model* model, net_idx_t net_idx)
void fnet_delete(struct fpga_model* model, net_idx_t net_idx)
{
struct fpga_net* net;
int i;
@ -1574,7 +1574,7 @@ void fpga_net_delete(struct fpga_model* model, net_idx_t net_idx)
model->highest_used_net--;
}
int fpga_net_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next)
int fnet_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next)
{
int i;
@ -1589,7 +1589,7 @@ int fpga_net_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next)
return 0;
}
struct fpga_net* fpga_net_get(struct fpga_model* model, net_idx_t net_i)
struct fpga_net* fnet_get(struct fpga_model* model, net_idx_t net_i)
{
if (net_i <= NO_NET
|| net_i > model->highest_used_net) {
@ -1600,14 +1600,14 @@ struct fpga_net* fpga_net_get(struct fpga_model* model, net_idx_t net_i)
return &model->nets[net_i-1];
}
int fpga_net_add_port(struct fpga_model* model, net_idx_t net_i,
int fnet_add_port(struct fpga_model* model, net_idx_t net_i,
int y, int x, enum fpgadev_type type, dev_type_idx_t type_idx,
pinw_idx_t pinw_idx)
{
struct fpga_net* net;
int rc;
rc = fpga_net_useidx(model, net_i);
rc = fnet_useidx(model, net_i);
if (rc) FAIL(rc);
net = &model->nets[net_i-1];
@ -1624,13 +1624,13 @@ fail:
return rc;
}
int fpga_net_add_sw(struct fpga_model* model, net_idx_t net_i,
int fnet_add_sw(struct fpga_model* model, net_idx_t net_i,
int y, int x, const swidx_t* switches, int num_sw)
{
struct fpga_net* net;
int i, rc;
rc = fpga_net_useidx(model, net_i);
rc = fnet_useidx(model, net_i);
if (rc) FAIL(rc);
net = &model->nets[net_i-1];
@ -1651,7 +1651,7 @@ fail:
return rc;
}
int fpga_net_remove_sw(struct fpga_model* model, net_idx_t net_i,
int fnet_remove_sw(struct fpga_model* model, net_idx_t net_i,
int y, int x, const swidx_t* switches, int num_sw)
{
struct fpga_net* net;
@ -1690,7 +1690,7 @@ fail:
return rc;
}
void fpga_net_free_all(struct fpga_model* model)
void fnet_free_all(struct fpga_model* model)
{
free(model->nets);
model->nets = 0;
@ -1736,7 +1736,7 @@ void fprintf_net(FILE* f, struct fpga_model* model, net_idx_t net_i)
struct fpga_net* net;
int i;
net = fpga_net_get(model, net_i);
net = fnet_get(model, net_i);
if (!net) { HERE(); return; }
for (i = 0; i < net->len; i++) {
if (net->el[i].idx & NET_IDX_IS_PINW) {

16
control.h
View File

@ -310,18 +310,18 @@ struct fpga_net
typedef int net_idx_t; // net indices are 1-based
#define NO_NET 0
int fpga_net_new(struct fpga_model* model, net_idx_t* new_idx);
void fpga_net_delete(struct fpga_model* model, net_idx_t net_idx);
int fnet_new(struct fpga_model* model, net_idx_t* new_idx);
void fnet_delete(struct fpga_model* model, net_idx_t net_idx);
// start a new enumeration by calling with last==NO_NET
int fpga_net_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next);
struct fpga_net* fpga_net_get(struct fpga_model* model, net_idx_t net_i);
int fpga_net_add_port(struct fpga_model* model, net_idx_t net_i,
int fnet_enum(struct fpga_model* model, net_idx_t last, net_idx_t* next);
struct fpga_net* fnet_get(struct fpga_model* model, net_idx_t net_i);
int fnet_add_port(struct fpga_model* model, net_idx_t net_i,
int y, int x, enum fpgadev_type type, dev_type_idx_t type_idx, pinw_idx_t pinw_idx);
int fpga_net_add_sw(struct fpga_model* model, net_idx_t net_i,
int fnet_add_sw(struct fpga_model* model, net_idx_t net_i,
int y, int x, const swidx_t* switches, int num_sw);
int fpga_net_remove_sw(struct fpga_model* model, net_idx_t net_i,
int fnet_remove_sw(struct fpga_model* model, net_idx_t net_i,
int y, int x, const swidx_t* switches, int num_sw);
void fpga_net_free_all(struct fpga_model* model);
void fnet_free_all(struct fpga_model* model);
void fprintf_net(FILE* f, struct fpga_model* model, net_idx_t net_i);

6
floorplan.c
View File

@ -728,7 +728,7 @@ int printf_nets(FILE* f, struct fpga_model* model)
int rc;
net_i = NO_NET;
while (!(rc = fpga_net_enum(model, net_i, &net_i)) && net_i != NO_NET)
while (!(rc = fnet_enum(model, net_i, &net_i)) && net_i != NO_NET)
fprintf_net(f, model, net_i);
if (rc) FAIL(rc);
return 0;
@ -846,7 +846,7 @@ static void read_net_line(struct fpga_model* model, const char* line, int start)
if (fpga_switch_is_used(model, y_coord, x_coord, sw.sw[0]))
HERE();
sw.len = 1;
if (fpga_net_add_sw(model, net_idx, y_coord, x_coord, sw.sw, sw.len))
if (fnet_add_sw(model, net_idx, y_coord, x_coord, sw.sw, sw.len))
HERE();
return;
}
@ -874,7 +874,7 @@ static void read_net_line(struct fpga_model* model, const char* line, int start)
pinw_idx = fdev_pinw_str2idx(dev_type, &line[pin_name_beg],
pin_name_end-pin_name_beg);
if (pinw_idx == PINW_NO_IDX) { HERE(); return; }
if (fpga_net_add_port(model, net_idx, y_coord, x_coord, dev_type,
if (fnet_add_port(model, net_idx, y_coord, x_coord, dev_type,
to_i(&line[dev_type_idx_str_beg], dev_type_idx_str_end
-dev_type_idx_str_beg), pinw_idx))
HERE();

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//
// Author: Wolfgang Spraul
//
// This is free and unencumbered software released into the public domain.
// For details see the UNLICENSE file at the root of the source tree.
//
#include "model.h"
#include "floorplan.h"
#include "control.h"
int main(int argc, char** argv)
{
struct fpga_model model;
int iob_inA_y, iob_inA_x, iob_inA_type_idx;
int iob_inB_y, iob_inB_x, iob_inB_type_idx;
int iob_out_y, iob_out_x, iob_out_type_idx;
int rc;
if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc);
if ((rc = fpga_find_iob(&model, "P45", &iob_inA_y, &iob_inA_x,
&iob_inA_type_idx))) FAIL(rc);
if ((rc = fdev_iob_input(&model, iob_inA_y, iob_inA_x,
iob_inA_type_idx))) FAIL(rc);
if ((rc = fpga_find_iob(&model, "P46", &iob_inB_y, &iob_inB_x,
&iob_inB_type_idx))) FAIL(rc);
if ((rc = fdev_iob_input(&model, iob_inB_y, iob_inB_x,
iob_inB_type_idx))) FAIL(rc);
if ((rc = fpga_find_iob(&model, "P48", &iob_out_y, &iob_out_x,
&iob_out_type_idx))) FAIL(rc);
if ((rc = fdev_iob_output(&model, iob_out_y, iob_out_x,
iob_out_type_idx))) FAIL(rc);
if ((rc = fdev_logic_set_lut(&model, 68, 13, DEV_LOGM,
LUT_A, 6, "A1*A2", ZTERM))) FAIL(rc);
// fnet_new
// fnet_add_port
// fnet_add_port
// fnet_autoroute
// fnet_autoroute
// P45.I -> logic.A1
// P46.I -> logic.A2
// logic.A -> P48.O
#if 0
struct fpga_device* P46_dev, *P48_dev, *logic_dev;
int P46_y, P46_x, P46_dev_idx, P46_type_idx;
int P48_y, P48_x, P48_dev_idx, P48_type_idx, logic_dev_idx, rc;
net_idx_t P46_net;
struct switch_to_yx switch_to;
int iob_y, iob_x, iob_type_idx, rc;
struct fpga_device* iob_dev;
net_idx_t net;
// configure net from P46.I to logic.D3
rc = fnet_new(&model, &P46_net);
if (rc) FAIL(rc);
rc = fnet_add_port(&model, P46_net, P46_y, P46_x,
P46_dev_idx, IOB_OUT_I);
if (rc) FAIL(rc);
rc = fnet_add_port(&model, P46_net, /*y*/ 68, /*x*/ 13,
logic_dev_idx, LI_D3);
if (rc) FAIL(rc);
switch_to.yx_req = YX_DEV_ILOGIC;
switch_to.flags = SWTO_YX_DEF;
switch_to.model = &model;
switch_to.y = P46_y;
switch_to.x = P46_x;
switch_to.start_switch = P46_dev->pinw[IOB_OUT_I];
switch_to.from_to = SW_FROM;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
switch_to.yx_req = YX_ROUTING_TILE;
switch_to.flags = SWTO_YX_DEF;
switch_to.model = &model;
switch_to.y = switch_to.dest_y;
switch_to.x = switch_to.dest_x;
switch_to.start_switch = switch_to.dest_connpt;
switch_to.from_to = SW_FROM;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
switch_to.yx_req = YX_ROUTING_TO_FABLOGIC;
switch_to.flags = SWTO_YX_CLOSEST;
switch_to.model = &model;
switch_to.y = switch_to.dest_y;
switch_to.x = switch_to.dest_x;
switch_to.start_switch = switch_to.dest_connpt;
switch_to.from_to = SW_FROM;
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
switch_to.yx_req = YX_DEV_LOGIC;
switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH;
switch_to.model = &model;
switch_to.y = switch_to.dest_y;
switch_to.x = switch_to.dest_x;
switch_to.start_switch = switch_to.dest_connpt;
switch_to.from_to = SW_FROM;
switch_to.max_switch_depth = 1;
{
note: update to constructor
struct sw_chain c = {
.model = &model, .y = switch_to.dest_y,
.x = switch_to.dest_x+1,
.start_switch = logic_dev->pinw[LI_D3],
.from_to = SW_TO,
.max_depth = SW_SET_SIZE,
.block_list = 0 };
if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
switch_to.target_connpt = fpga_switch_str_i(&model,
switch_to.dest_y, switch_to.dest_x+1,
c.set.sw[c.set.len-1], SW_FROM);
}
rc = fpga_switch_to_yx(&switch_to);
if (rc) FAIL(rc);
rc = fnet_add_switches(&model, P46_net, switch_to.y,
switch_to.x, &switch_to.set);
if (rc) FAIL(rc);
{
note: update to constructor
struct sw_chain c = {
.model = &model, .y = switch_to.dest_y,
.x = switch_to.dest_x,
.start_switch = switch_to.dest_connpt,
.from_to = SW_FROM,
.max_depth = SW_SET_SIZE,
.block_list = 0 };
if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
rc = fnet_add_switches(&model, P46_net, c.y, c.x, &c.set);
if (rc) FAIL(rc);
}
#endif
if ((rc = write_floorplan(stdout, &model, FP_DEFAULT))) FAIL(rc);
return EXIT_SUCCESS;
fail:
return rc;
}