157 lines
4.6 KiB
C
157 lines
4.6 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include "model.h"
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#include "floorplan.h"
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#include "control.h"
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int main(int argc, char** argv)
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{
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struct fpga_model model;
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int iob_inA_y, iob_inA_x, iob_inA_type_idx;
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int iob_inB_y, iob_inB_x, iob_inB_type_idx;
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int iob_out_y, iob_out_x, iob_out_type_idx;
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int rc;
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if ((rc = fpga_build_model(&model, XC6SLX9_ROWS, XC6SLX9_COLUMNS,
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XC6SLX9_LEFT_WIRING, XC6SLX9_RIGHT_WIRING))) FAIL(rc);
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if ((rc = fpga_find_iob(&model, "P45", &iob_inA_y, &iob_inA_x,
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&iob_inA_type_idx))) FAIL(rc);
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if ((rc = fdev_iob_input(&model, iob_inA_y, iob_inA_x,
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iob_inA_type_idx))) FAIL(rc);
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if ((rc = fpga_find_iob(&model, "P46", &iob_inB_y, &iob_inB_x,
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&iob_inB_type_idx))) FAIL(rc);
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if ((rc = fdev_iob_input(&model, iob_inB_y, iob_inB_x,
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iob_inB_type_idx))) FAIL(rc);
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if ((rc = fpga_find_iob(&model, "P48", &iob_out_y, &iob_out_x,
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&iob_out_type_idx))) FAIL(rc);
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if ((rc = fdev_iob_output(&model, iob_out_y, iob_out_x,
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iob_out_type_idx))) FAIL(rc);
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if ((rc = fdev_logic_set_lut(&model, 68, 13, DEV_LOGM,
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LUT_A, 6, "A1*A2", ZTERM))) FAIL(rc);
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// fnet_new
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// fnet_add_port
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// fnet_add_port
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// fnet_autoroute
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// fnet_autoroute
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// P45.I -> logic.A1
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// P46.I -> logic.A2
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// logic.A -> P48.O
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#if 0
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struct fpga_device* P46_dev, *P48_dev, *logic_dev;
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int P46_y, P46_x, P46_dev_idx, P46_type_idx;
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int P48_y, P48_x, P48_dev_idx, P48_type_idx, logic_dev_idx, rc;
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net_idx_t P46_net;
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struct switch_to_yx switch_to;
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int iob_y, iob_x, iob_type_idx, rc;
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struct fpga_device* iob_dev;
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net_idx_t net;
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// configure net from P46.I to logic.D3
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rc = fnet_new(&model, &P46_net);
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if (rc) FAIL(rc);
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rc = fnet_add_port(&model, P46_net, P46_y, P46_x,
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P46_dev_idx, IOB_OUT_I);
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if (rc) FAIL(rc);
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rc = fnet_add_port(&model, P46_net, /*y*/ 68, /*x*/ 13,
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logic_dev_idx, LI_D3);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_DEV_ILOGIC;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = &model;
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switch_to.y = P46_y;
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switch_to.x = P46_x;
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switch_to.start_switch = P46_dev->pinw[IOB_OUT_I];
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switch_to.from_to = SW_FROM;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_ROUTING_TILE;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_ROUTING_TO_FABLOGIC;
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switch_to.flags = SWTO_YX_CLOSEST;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_DEV_LOGIC;
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switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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switch_to.max_switch_depth = 1;
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{
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note: update to constructor
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struct sw_chain c = {
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.model = &model, .y = switch_to.dest_y,
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.x = switch_to.dest_x+1,
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.start_switch = logic_dev->pinw[LI_D3],
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.from_to = SW_TO,
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.max_depth = SW_SET_SIZE,
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.block_list = 0 };
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if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
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if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
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switch_to.target_connpt = fpga_switch_str_i(&model,
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switch_to.dest_y, switch_to.dest_x+1,
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c.set.sw[c.set.len-1], SW_FROM);
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}
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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{
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note: update to constructor
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struct sw_chain c = {
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.model = &model, .y = switch_to.dest_y,
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.x = switch_to.dest_x,
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.start_switch = switch_to.dest_connpt,
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.from_to = SW_FROM,
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.max_depth = SW_SET_SIZE,
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.block_list = 0 };
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if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
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if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
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rc = fnet_add_switches(&model, P46_net, c.y, c.x, &c.set);
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if (rc) FAIL(rc);
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}
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#endif
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if ((rc = write_floorplan(stdout, &model, FP_DEFAULT))) FAIL(rc);
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return EXIT_SUCCESS;
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fail:
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return rc;
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}
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