hello world minor improvement
This commit is contained in:
Wolfgang Spraul
parent
700f888ae2
commit
d5bb9ceb28
235
hello_world.c
235
hello_world.c
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@ -9,8 +9,6 @@
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#include "floorplan.h"
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#include "control.h"
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// Searches a connection in search_y/search_x that connects to
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// target_y/target_x/target_pt.
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int fpga_find_conn(struct fpga_model* model, int search_y, int search_x,
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str16_t* pt, int target_y, int target_x, str16_t target_pt)
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{
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@ -44,34 +42,27 @@ static int froute_direct(struct fpga_model* model, int start_y, int start_x,
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struct sw_set end_switches;
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int i, rc;
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printf("start %02i %02i %s end %02i %02i %s\n", start_y, start_x, strarray_lookup(&model->str, start_pt),
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end_y, end_x, strarray_lookup(&model->str, end_pt));
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rc = fpga_swset_fromto(model, end_y, end_x, end_pt, SW_TO, &end_switches);
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if (rc) FAIL(rc);
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fpga_swset_print(model, end_y, end_x, &end_switches, SW_TO);
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if (!end_switches.len) FAIL(EINVAL);
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// TODO: WR1 is not in model, so cannot connect...
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if (construct_sw_conns(&conns, model, start_y, start_x, start_pt, SW_FROM, /*max_depth*/ 1))
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{ HERE(); return; }
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rc = construct_sw_conns(&conns, model, start_y, start_x, start_pt,
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SW_FROM, /*max_depth*/ 1);
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if (rc) FAIL(rc);
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while (fpga_switch_conns(&conns) != NO_CONN) {
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if (conns.dest_y != end_y
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|| conns.dest_x != end_x) continue;
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for (i = 0; i < end_switches.len; i++) {
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if (conns.dest_str_i == fpga_switch_str_i(model, end_y, end_x, end_switches.sw[i], SW_FROM)) {
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if (conns.dest_str_i == fpga_switch_str_i(model, end_y,
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end_x, end_switches.sw[i], SW_FROM)) {
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*start_set = conns.chain.set;
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end_set->len = 1;
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end_set->sw[0] = end_switches.sw[i];
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return 0;
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}
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}
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printf("sw %s conn y%02i x%02i %s\n", fmt_swset(model, start_y, start_x,
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&conns.chain.set, SW_FROM),
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conns.dest_y, conns.dest_x,
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strarray_lookup(&model->str, conns.dest_str_i));
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}
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printf("sw -\n");
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destruct_sw_conns(&conns);
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start_set->len = 0;
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end_set->len = 0;
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@ -85,9 +76,8 @@ static int fnet_autoroute(struct fpga_model* model, net_idx_t net_i)
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struct fpga_net* net_p;
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struct fpga_device* dev_p, *out_dev, *in_dev;
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struct switch_to_yx switch_to;
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struct sw_chain ch;
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struct sw_set logic_set, logic_route_set, iologic_route_set;
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str16_t route_pt;
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struct sw_set logic_route_set, iologic_route_set;
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struct switch_to_rel switch_to_rel;
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int i, out_i, in_i, rc;
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// todo: gnd and vcc nets are special and have no outpin
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@ -153,94 +143,105 @@ static int fnet_autoroute(struct fpga_model* model, net_idx_t net_i)
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switch_to.set.sw, switch_to.set.len);
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if (rc) FAIL(rc);
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// switch inside logic tile
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rc = fpga_swset_fromto(model, net_p->el[in_i].y,
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net_p->el[in_i].x,
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in_dev->pinw[net_p->el[in_i].idx & NET_IDX_MASK],
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SW_TO, &logic_set);
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// switch from logic tile to logic routing tile
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switch_to_rel.model = model;
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switch_to_rel.start_y = net_p->el[in_i].y;
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switch_to_rel.start_x = net_p->el[in_i].x;
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switch_to_rel.start_switch =
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in_dev->pinw[net_p->el[in_i].idx & NET_IDX_MASK];
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switch_to_rel.from_to = SW_TO;
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switch_to_rel.rel_y = 0;
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switch_to_rel.rel_x = -1;
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switch_to_rel.target_connpt = STRIDX_NO_ENTRY;
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rc = fpga_switch_to_rel(&switch_to_rel);
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if (rc) FAIL(rc);
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if (logic_set.len != 1) FAIL(EINVAL);
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// switch in routing tile connecting to logic tile
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rc = fpga_find_conn(model,
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net_p->el[in_i].y, net_p->el[in_i].x-1, &route_pt,
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net_p->el[in_i].y, net_p->el[in_i].x,
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fpga_switch_str_i(model, net_p->el[in_i].y,
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net_p->el[in_i].x, logic_set.sw[0], SW_FROM));
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rc = fnet_add_sw(model, net_i, switch_to_rel.start_y,
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switch_to_rel.start_x, switch_to_rel.set.sw,
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switch_to_rel.set.len);
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if (rc) FAIL(rc);
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printf("%s\n", strarray_lookup(&model->str, route_pt));
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// route from ilogic routing to logic routing
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rc = froute_direct(model, switch_to.dest_y, switch_to.dest_x,
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switch_to.dest_connpt,
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net_p->el[in_i].y, net_p->el[in_i].x-1, route_pt,
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switch_to_rel.dest_y, switch_to_rel.dest_x,
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switch_to_rel.dest_connpt,
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&iologic_route_set, &logic_route_set);
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if (rc) FAIL(rc);
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#if 0
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static int froute_direct(struct fpga_model* model, int start_y, int start_x,
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str16_t start_pt, int end_y, int end_x, str16_t end_pt,
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int from_to, struct sw_set* sw)
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switch_to.yx_req = YX_ROUTING_TO_FABLOGIC;
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switch_to.flags = SWTO_YX_CLOSEST;
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switch_to.model = model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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printf("from1 y%02i x%02i %s\n", switch_to.dest_y, switch_to.dest_x,
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strarray_lookup(&model->str, switch_to.dest_connpt));
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67/12/LOGICOUT7
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-> WR1B1
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-> 68/12 WR1E1
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-> LOGICIN_B30
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params: 67/12/LOGICOUT7
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dest: 68/12/LOGICIN_B30
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func:
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SW_TO LOGICIN_B30
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go through, call switch_to with target_connpt
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rc = fpga_switch_to_yx(&switch_to);
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if (!iologic_route_set.len || !logic_route_set.len) FAIL(EINVAL);
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rc = fnet_add_sw(model, net_i, switch_to.dest_y, switch_to.dest_x,
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iologic_route_set.sw, iologic_route_set.len);
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if (rc) FAIL(rc);
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rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x,
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switch_to.set.sw, switch_to.set.len);
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rc = fnet_add_sw(model, net_i, net_p->el[in_i].y, net_p->el[in_i].x-1,
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logic_route_set.sw, logic_route_set.len);
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if (rc) FAIL(rc);
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switch_to.yx_req = YX_DEV_LOGIC;
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switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH;
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switch_to.model = model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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switch_to.max_switch_depth = 1;
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printf("from y%02i x%02i %s\n", switch_to.dest_y, switch_to.dest_x,
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strarray_lookup(&model->str, switch_to.dest_connpt));
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rc = construct_sw_chain(&ch, model, switch_to.dest_y,
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switch_to.dest_x+1, in_dev->pinw[net_p->el[in_i].idx
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& NET_IDX_MASK], SW_TO, /*max_depth*/ -1,
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/*block*/ 0, 0);
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if (rc) FAIL(rc);
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if (fpga_switch_chain(&ch) == NO_CONN) FAIL(EINVAL);
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if (!ch.set.len) { HERE(); FAIL(EINVAL); }
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switch_to.target_connpt = fpga_switch_str_i(model,
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switch_to.dest_y, switch_to.dest_x+1,
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ch.set.sw[ch.set.len-1], SW_FROM);
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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printf_switch_to_yx_result(&switch_to);
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rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x,
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switch_to.set.sw, switch_to.set.len);
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if (rc) FAIL(rc);
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#endif
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return 0;
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}
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if (out_dev->type == DEV_LOGIC) {
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if (in_dev->type != DEV_IOB)
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FAIL(ENOTSUP);
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// switch from ologic to iob
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switch_to.yx_req = YX_DEV_OLOGIC;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = model;
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switch_to.y = net_p->el[in_i].y;
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switch_to.x = net_p->el[in_i].x;
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switch_to.start_switch = in_dev->pinw[net_p->el[in_i].idx
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& NET_IDX_MASK];
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switch_to.from_to = SW_TO;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x,
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switch_to.set.sw, switch_to.set.len);
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if (rc) FAIL(rc);
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// switches inside ologic to ologic routing
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switch_to.yx_req = YX_ROUTING_TILE;
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switch_to.flags = SWTO_YX_DEF;
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switch_to.model = model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_TO;
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_sw(model, net_i, switch_to.y, switch_to.x,
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switch_to.set.sw, switch_to.set.len);
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if (rc) FAIL(rc);
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// switch inside logic tile
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switch_to_rel.model = model;
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switch_to_rel.start_y = net_p->el[out_i].y;
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switch_to_rel.start_x = net_p->el[out_i].x;
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switch_to_rel.start_switch =
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out_dev->pinw[net_p->el[out_i].idx & NET_IDX_MASK];
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switch_to_rel.from_to = SW_FROM;
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switch_to_rel.rel_y = 0;
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switch_to_rel.rel_x = -1;
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switch_to_rel.target_connpt = STRIDX_NO_ENTRY;
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rc = fpga_switch_to_rel(&switch_to_rel);
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if (rc) FAIL(rc);
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rc = fnet_add_sw(model, net_i, switch_to_rel.start_y,
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switch_to_rel.start_x, switch_to_rel.set.sw,
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switch_to_rel.set.len);
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if (rc) FAIL(rc);
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// route from logic routing to ilogic routing
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rc = froute_direct(model, switch_to_rel.dest_y,
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switch_to_rel.dest_x, switch_to_rel.dest_connpt,
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switch_to.dest_y, switch_to.dest_x, switch_to.dest_connpt,
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&logic_route_set, &iologic_route_set);
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if (rc) FAIL(rc);
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if (!iologic_route_set.len || !logic_route_set.len) FAIL(EINVAL);
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rc = fnet_add_sw(model, net_i, switch_to.dest_y, switch_to.dest_x,
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iologic_route_set.sw, iologic_route_set.len);
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if (rc) FAIL(rc);
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rc = fnet_add_sw(model, net_i, switch_to_rel.dest_y,
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switch_to_rel.dest_x, logic_route_set.sw,
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logic_route_set.len);
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if (rc) FAIL(rc);
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return 0;
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}
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FAIL(ENOTSUP);
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@ -278,75 +279,31 @@ int main(int argc, char** argv)
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logic_y = 68;
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logic_x = 13;
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logic_type_idx = DEV_LOGM;
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logic_type_idx = DEV_LOGX;
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if ((rc = fdev_logic_set_lut(&model, logic_y, logic_x, logic_type_idx,
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LUT_A, 6, "A1*A2", ZTERM))) FAIL(rc);
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LUT_D, 6, "A3*A5", ZTERM))) FAIL(rc);
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if ((rc = fnet_new(&model, &inA_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inA_net, iob_inA_y, iob_inA_x,
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DEV_IOB, iob_inA_type_idx, IOB_OUT_I))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inA_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LI_A1))) FAIL(rc);
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logic_type_idx, LI_D3))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, inA_net))) FAIL(rc);
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if ((rc = fnet_new(&model, &inB_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inB_net, iob_inB_y, iob_inB_x,
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DEV_IOB, iob_inB_type_idx, IOB_OUT_I))) FAIL(rc);
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if ((rc = fnet_add_port(&model, inB_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LI_A2))) FAIL(rc);
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logic_type_idx, LI_D5))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, inB_net))) FAIL(rc);
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if ((rc = fnet_new(&model, &out_net))) FAIL(rc);
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if ((rc = fnet_add_port(&model, out_net, logic_y, logic_x, DEV_LOGIC,
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logic_type_idx, LO_A))) FAIL(rc);
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logic_type_idx, LO_D))) FAIL(rc);
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if ((rc = fnet_add_port(&model, out_net, iob_out_y, iob_out_x,
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DEV_IOB, iob_out_type_idx, IOB_IN_O))) FAIL(rc);
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if ((rc = fnet_autoroute(&model, out_net))) FAIL(rc);
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#if 0
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switch_to.yx_req = YX_DEV_LOGIC;
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switch_to.flags = SWTO_YX_TARGET_CONNPT|SWTO_YX_MAX_SWITCH_DEPTH;
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switch_to.model = &model;
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switch_to.y = switch_to.dest_y;
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switch_to.x = switch_to.dest_x;
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switch_to.start_switch = switch_to.dest_connpt;
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switch_to.from_to = SW_FROM;
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switch_to.max_switch_depth = 1;
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{
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note: update to constructor
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struct sw_chain c = {
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.model = &model, .y = switch_to.dest_y,
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.x = switch_to.dest_x+1,
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.start_switch = logic_dev->pinw[LI_D3],
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.from_to = SW_TO,
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.max_depth = SW_SET_SIZE,
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.block_list = 0 };
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if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
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if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
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switch_to.target_connpt = fpga_switch_str_i(&model,
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switch_to.dest_y, switch_to.dest_x+1,
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c.set.sw[c.set.len-1], SW_FROM);
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}
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rc = fpga_switch_to_yx(&switch_to);
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if (rc) FAIL(rc);
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rc = fnet_add_switches(&model, P46_net, switch_to.y,
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switch_to.x, &switch_to.set);
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if (rc) FAIL(rc);
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{
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note: update to constructor
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struct sw_chain c = {
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.model = &model, .y = switch_to.dest_y,
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.x = switch_to.dest_x,
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.start_switch = switch_to.dest_connpt,
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.from_to = SW_FROM,
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.max_depth = SW_SET_SIZE,
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.block_list = 0 };
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if (fpga_switch_chain(&c) == NO_CONN) FAIL(EINVAL);
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if (c.set.len == 0) { HERE(); FAIL(EINVAL); }
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rc = fnet_add_switches(&model, P46_net, c.y, c.x, &c.set);
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if (rc) FAIL(rc);
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}
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#endif
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if ((rc = write_floorplan(stdout, &model, FP_DEFAULT))) FAIL(rc);
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return EXIT_SUCCESS;
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fail:
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