some more switches
This commit is contained in:
Wolfgang Spraul
parent
63ec0e2253
commit
ea40792a4e
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@ -9,28 +9,29 @@
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#include "model.h"
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#include "parts.h"
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static int init_ce_clk(struct fpga_model* model);
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static int init_io(struct fpga_model* model);
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static int init_routing(struct fpga_model* model);
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static int init_north_south_dirwire_term(struct fpga_model* model);
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static int init_east_west_dirwire_term(struct fpga_model* model);
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static int init_iologic(struct fpga_model* model);
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static int init_logic(struct fpga_model* model);
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static int init_center(struct fpga_model* model);
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static int init_hclk(struct fpga_model* model);
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static int init_logicout_fw(struct fpga_model* model);
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static int init_bram(struct fpga_model* model);
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static int init_macc(struct fpga_model* model);
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static int init_topbot_tterm_gclk(struct fpga_model* model);
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static int init_bufio(struct fpga_model* model);
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static int init_bscan(struct fpga_model* model);
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static int init_dcm(struct fpga_model* model);
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static int init_pll(struct fpga_model* model);
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static int init_center_hclk(struct fpga_model* model);
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static int init_center_midbuf(struct fpga_model* model);
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static int init_center_reg_tblr(struct fpga_model* model);
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static int init_ce_clk(struct fpga_model *model);
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static int init_io(struct fpga_model *model);
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static int init_routing(struct fpga_model *model);
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static int init_north_south_dirwire_term(struct fpga_model *model);
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static int init_east_west_dirwire_term(struct fpga_model *model);
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static int init_iologic(struct fpga_model *model);
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static int init_logic(struct fpga_model *model);
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static int init_center(struct fpga_model *model);
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static int init_hclk(struct fpga_model *model);
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static int init_logicout_fw(struct fpga_model *model);
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static int init_bram(struct fpga_model *model);
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static int init_macc(struct fpga_model *model);
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static int init_topbot_tterm_gclk(struct fpga_model *model);
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static int init_bufio(struct fpga_model *model);
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static int init_bscan(struct fpga_model *model);
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static int init_dcm(struct fpga_model *model);
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static int init_pll(struct fpga_model *model);
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static int init_center_hclk(struct fpga_model *model);
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static int init_center_midbuf(struct fpga_model *model);
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static int init_center_reg_tblr(struct fpga_model *model);
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static int init_center_topbot_cfb_dfb(struct fpga_model *model);
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int init_switches(struct fpga_model* model, int routing_sw)
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int init_switches(struct fpga_model *model, int routing_sw)
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{
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int rc;
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@ -95,12 +96,15 @@ int init_switches(struct fpga_model* model, int routing_sw)
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rc = init_center_reg_tblr(model);
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if (rc) FAIL(rc);
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rc = init_center_topbot_cfb_dfb(model);
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if (rc) FAIL(rc);
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return 0;
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fail:
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return rc;
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}
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static int init_logic_tile(struct fpga_model* model, int y, int x)
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static int init_logic_tile(struct fpga_model *model, int y, int x)
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{
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int rc, i, j, ml;
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const char* xp;
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@ -187,7 +191,7 @@ xout:
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return rc;
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}
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static int init_logic(struct fpga_model* model)
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static int init_logic(struct fpga_model *model)
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{
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int x, y, rc;
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@ -206,7 +210,7 @@ xout:
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return rc;
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}
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static int init_iologic_tile(struct fpga_model* model, int y, int x)
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static int init_iologic_tile(struct fpga_model *model, int y, int x)
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{
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int i, j, rc;
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const char* io_prefix, *prefix, *prefix2;
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@ -581,7 +585,7 @@ xout:
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return rc;
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}
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static int init_iologic(struct fpga_model* model)
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static int init_iologic(struct fpga_model *model)
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{
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int x, y, rc;
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@ -618,7 +622,7 @@ xout:
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return rc;
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}
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static int init_north_south_dirwire_term(struct fpga_model* model)
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static int init_north_south_dirwire_term(struct fpga_model *model)
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{
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static const int logicin_pairs[] = {21,20, 28,36, 52,44, 60,62};
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int x, i, rc;
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@ -696,7 +700,7 @@ xout:
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return rc;
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}
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static int init_east_west_dirwire_term(struct fpga_model* model)
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static int init_east_west_dirwire_term(struct fpga_model *model)
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{
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int y, rc;
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@ -734,7 +738,7 @@ fail:
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return rc;
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}
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static int init_ce_clk(struct fpga_model* model)
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static int init_ce_clk(struct fpga_model *model)
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{
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int x, y, i, rc;
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@ -868,7 +872,7 @@ xout:
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return rc;
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}
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static int init_io_tile(struct fpga_model* model, int y, int x)
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static int init_io_tile(struct fpga_model *model, int y, int x)
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{
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const char* prefix;
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int i, num_devs, rc;
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@ -935,7 +939,7 @@ xout:
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return rc;
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}
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static int init_io(struct fpga_model* model)
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static int init_io(struct fpga_model *model)
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{
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int x, y, rc;
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@ -1097,7 +1101,7 @@ static const char* routing_wirestr(enum extra_wires wire,
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return fpga_wire2str(wire);
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}
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static int init_routing_tile(struct fpga_model* model, int y, int x)
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static int init_routing_tile(struct fpga_model *model, int y, int x)
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{
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int i, routing_io, gclk_brk, from_wire, to_wire, is_bidir, rc;
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struct fpga_tile* tile;
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@ -1177,7 +1181,7 @@ fail:
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return rc;
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}
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static int init_routing(struct fpga_model* model)
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static int init_routing(struct fpga_model *model)
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{
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int x, y, rc;
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@ -1197,7 +1201,7 @@ fail:
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return rc;
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}
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int replicate_routing_switches(struct fpga_model* model)
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int replicate_routing_switches(struct fpga_model *model)
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{
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struct fpga_tile* tile;
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int x, y, first_y, first_x, rc;
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@ -1236,7 +1240,7 @@ fail:
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return rc;
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}
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static int init_center(struct fpga_model* model)
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static int init_center(struct fpga_model *model)
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{
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int i, j, rc;
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@ -1324,7 +1328,7 @@ fail:
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return rc;
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}
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static int init_hclk(struct fpga_model* model)
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static int init_hclk(struct fpga_model *model)
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{
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int x, y, i, rc;
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@ -1440,7 +1444,7 @@ fail:
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return rc;
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}
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static int init_bram(struct fpga_model* model)
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static int init_bram(struct fpga_model *model)
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{
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int i, x, y, tile0_to_3, wire_num, rc;
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@ -1526,7 +1530,7 @@ fail:
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return rc;
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}
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static int init_macc(struct fpga_model* model)
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static int init_macc(struct fpga_model *model)
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{
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int i, x, y, tile0_to_3, wire_num, rc;
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@ -1588,7 +1592,7 @@ fail:
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return rc;
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}
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static int init_topbot_tterm_gclk(struct fpga_model* model)
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static int init_topbot_tterm_gclk(struct fpga_model *model)
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{
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int i, rc;
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@ -1607,7 +1611,7 @@ fail:
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return rc;
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}
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static int init_bufio_tile(struct fpga_model* model, int y, int x, const char *s1, const char *s2)
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static int init_bufio_tile(struct fpga_model *model, int y, int x, const char *s1, const char *s2)
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{
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int i, j, rc;
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@ -1686,7 +1690,7 @@ fail:
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return rc;
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}
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static int init_bufio(struct fpga_model* model)
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static int init_bufio(struct fpga_model *model)
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{
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int y, x, j, rc;
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const char *s1, *s2;
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@ -1740,7 +1744,7 @@ fail:
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return rc;
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}
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static int init_bscan(struct fpga_model* model)
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static int init_bscan(struct fpga_model *model)
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{
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int y, x, num_bscan_devs, i, j, rc;
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const char *s[] = {
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@ -1777,7 +1781,7 @@ fail:
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return rc;
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}
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static int init_dcm(struct fpga_model* model)
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static int init_dcm(struct fpga_model *model)
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{
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int y, x, i, j, k, num_devs, rc;
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@ -1957,7 +1961,7 @@ fail:
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return rc;
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}
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static int init_pll(struct fpga_model* model)
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static int init_pll(struct fpga_model *model)
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{
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int y, x, i, j, num_devs, rc;
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@ -2124,7 +2128,7 @@ fail:
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return rc;
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}
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static int init_center_hclk(struct fpga_model* model)
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static int init_center_hclk(struct fpga_model *model)
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{
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int y, x, i, rc;
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@ -2180,7 +2184,7 @@ fail:
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return rc;
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}
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static int init_center_midbuf(struct fpga_model* model)
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static int init_center_midbuf(struct fpga_model *model)
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{
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int y, x, i, rc;
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@ -2219,7 +2223,7 @@ fail:
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return rc;
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}
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static int init_center_reg_tile(struct fpga_model* model, int y, int x, const char *s1, const char *s2)
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static int init_center_reg_tile(struct fpga_model *model, int y, int x, const char *s1, const char *s2)
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{
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int i, j, rc;
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@ -2241,7 +2245,7 @@ fail:
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return rc;
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}
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static int init_center_reg_tblr(struct fpga_model* model)
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static int init_center_reg_tblr(struct fpga_model *model)
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{
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int y, x, i, j, rc;
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const char *s1, *s2;
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@ -2445,3 +2449,61 @@ static int init_center_reg_tblr(struct fpga_model* model)
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fail:
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return rc;
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}
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static int init_center_topbot_cfb_dfb(struct fpga_model *model)
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{
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const int x_enum[] = { model->center_x-CENTER_LOGIC_O,
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model->center_x+CENTER_X_PLUS_2 };
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int y, i, x_i, rc;
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y = TOP_INNER_ROW;
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for (x_i = 0; x_i < sizeof(x_enum)/sizeof(*x_enum); x_i++) {
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for (i = 0; i <= 1; i++) {
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_CFB1_M%i_S", i+1),
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pf("IOI_REGT_CFB1_M%i", i+1), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_CFB1_S%i_S", i+1),
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pf("IOI_REGT_CFB1_S%i", i+1), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_CFB_M%i_S", i+1),
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pf("IOI_REGT_CFB_M%i", i+1), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_CFB_S%i_S", i+1),
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pf("IOI_REGT_CFB_S%i", i+1), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_DFB_M%i_S", i+1),
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pf("IOI_REGT_DFB_M%i", i+1), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_DFB_S%i_S", i+1),
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pf("IOI_REGT_DFB_S%i", i+1), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_DQSN%i_S", i),
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pf("IOI_REGT_DQSN%i", i), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("IOI_REGT_DQSP%i_S", i),
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pf("IOI_REGT_DQSP%i", i), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("TTERM_IOIBOT_IBUF%i", i),
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pf("IOI_REGT_CLKPIN%i", i+2), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("TTERM_IOIUP_IBUF%i", i),
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pf("IOI_REGT_CLKPIN%i", i), /*bidir*/ 0))) FAIL(rc);
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}
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}
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y = model->y_height-BOT_INNER_ROW;
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for (x_i = 0; x_i < sizeof(x_enum)/sizeof(*x_enum); x_i++) {
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for (i = 0; i <= 3; i++) {
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_CLB_CFB1_%i_N", i+4),
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pf("BTERM_CLB_CFB1_%i", i+4), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_CLB_CFB%i_N", i+4),
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pf("BTERM_CLB_CFB%i", i+4), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_CLB_DFB%i_N", i+4),
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pf("BTERM_CLB_DFB%i", i+4), /*bidir*/ 0))) FAIL(rc);
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}
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for (i = 0; i <= 1; i++) {
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_CLB_DQSN%i_N", i+2),
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pf("BTERM_CLB_DQSN%i", i+2), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_CLB_DQSP%i_N", i+2),
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pf("BTERM_CLB_DQSP%i", i+2), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_IOIBOT_IBUF%i", i),
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pf("BTERM_CLB_CLKPIN%i", i+4), /*bidir*/ 0))) FAIL(rc);
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if ((rc = add_switch(model, y, x_enum[x_i], pf("BTERM_IOIUP_IBUF%i", i),
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pf("BTERM_CLB_CLKPIN%i", i+6), /*bidir*/ 0))) FAIL(rc);
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}
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}
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return 0;
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fail:
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return rc;
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}
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