Design Principles

- small independent command line utilities, no GUI
- plain C, no C++
- simple Makefiles
- text-based file formats
- no documentation - please read the sources
- automatic test suite

Libraries

- libfpga-test       test harness for model, control and design
- libfpga-model      memory-only representation of an FPGA
- libfpga-control    programmatic access to libfpga-model
- libfpga-design     larger design elements on top of libfpga-control
- libfpga-floorplan  reads and writes .fp floorplan files
- libfpga-bit        reads and writes .bit bitstream files

Design Utilities

- new_fp             creates empty .fp floorplan file
- fp2bit             converts .fp floorplan into .bit bitstream
- bit2fp             converts .bit bitstream into .fp floorplan
- draw_svg_tiles     draws a simple .svg showing tile types

fpgatools Development Utilities

- autotest           executes test suite
- sort_seq           sorts line-based text file by sequence numbers in strings
- merge_seq          merges a pre-sorted text file into wire sequences
- pair2net           reads the first two words per line and builds nets
- hstrrep            high-speed hashed array based search and replace util

TODO (as of 2012-08, expected time to delivery: months to years
      completion status overall: 1%)

* support chips other than xc6slx9, like slx45, slx150
* support xc7a100
* many more test cases for autotester
* smarter autotester that can remember and verify groups of tests,
  automatically oversee test execution, etc.
* 3 Debian packages: libfpga, libfpga-doc, fpgatools
* correct auto-crc calculation in .bit file
* many more cases in logic block configuration
* configuration of bram and macc blocks, bram initialization data
* routing switches
* many more cases in model of switches and inter-tile connections
* write standard design elements for libfpga-design library
* support lm32 or openrisc core, either via libfpga or iverilog backend
* iverilog fpga backend

ChangeLog

2012-08-20
* Beginning of full fidelity circle with model, floorplan, conversion from
  and to bitstream and floorplan formats.

2012-06-03
* Project started.