436 lines
13 KiB
C
436 lines
13 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <stdarg.h>
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#include "model.h"
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enum which_side
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{
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TOP_S, BOTTOM_S, RIGHT_S, LEFT_S
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};
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static int init_iologic_ports(struct fpga_model* model, int y, int x,
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enum which_side side, int dup_warn)
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{
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static const char* prefix, *suffix1, *suffix2;
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int rc, i;
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RC_CHECK(model);
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switch (side) {
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case TOP_S: prefix = "TIOI"; break;
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case BOTTOM_S: prefix = "BIOI"; break;
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case LEFT_S: prefix = "LIOI"; break;
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case RIGHT_S: prefix = "RIOI"; break;
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default: EXIT(1);
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}
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if (side == LEFT_S || side == RIGHT_S) {
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suffix1 = "_M";
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suffix2 = "_S";
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} else {
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suffix1 = "_STUB";
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suffix2 = "_S_STUB";
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}
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for (i = X_A /* 0 */; i <= M_DQ /* 23 */; i++) {
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rc = add_connpt_name(model, y, x, pf("IOI_INTER_LOGICOUT%i", i),
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dup_warn, /*name_i*/ 0, /*connpt_o*/ 0);
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if (rc) goto xout;
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}
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rc = add_connpt_name(model, y, x, pf("%s_GND_TIEOFF", prefix),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_VCC_TIEOFF", prefix),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_KEEP1_STUB", prefix),
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (i = 0; i <= 4; i++) {
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rc = add_connpt_2(model, y, x, pf("AUXADDR%i_IODELAY", i),
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suffix1, suffix2, dup_warn);
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if (rc) goto xout;
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}
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rc = add_connpt_2(model, y, x, "AUXSDOIN_IODELAY", suffix1, suffix2,
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, "AUXSDO_IODELAY", suffix1, suffix2,
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, "MEMUPDATE_IODELAY", suffix1, suffix2,
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "OUTN_IODELAY_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "STUB_OUTN_IODELAY_S",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "OUTP_IODELAY_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "STUB_OUTP_IODELAY_S",
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (i = 1; i <= 4; i++) {
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rc = add_connpt_2(model, y, x, pf("Q%i_ILOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, pf("D%i_OLOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, pf("T%i_OLOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, pf("SHIFTIN%i_OLOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, pf("SHIFTOUT%i_OLOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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}
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for (i = 0; i <= 1; i++) {
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rc = add_connpt_2(model, y, x, pf("CFB%i_ILOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, pf("CLK%i_ILOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, pf("CLK%i_OLOGIC_SITE", i), "", "_S",
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dup_warn);
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if (rc) goto xout;
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}
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{
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static const char* mcb_2[] = {
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"BITSLIP_ILOGIC_SITE", "BUSY_IODELAY_SITE",
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"CAL_IODELAY_SITE", "CE0_ILOGIC_SITE",
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"CE_IODELAY_SITE", "CIN_IODELAY_SITE",
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"CLKDIV_ILOGIC_SITE", "CLKDIV_OLOGIC_SITE",
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"CLK_IODELAY_SITE", "DATAOUT_IODELAY_SITE",
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"DDLY2_ILOGIC_SITE", "DDLY_ILOGIC_SITE",
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"DFB_ILOGIC_SITE", "D_ILOGIC_IDATAIN_IODELAY",
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"D_ILOGIC_SITE", "DOUT_IODELAY_SITE",
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"FABRICOUT_ILOGIC_SITE", "IDATAIN_IODELAY_SITE",
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"INCDEC_ILOGIC_SITE", "INC_IODELAY_SITE",
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"IOCE_ILOGIC_SITE", "IOCE_OLOGIC_SITE",
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"IOCLK1_IODELAY_SITE", "IOCLK_IODELAY_SITE",
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"LOAD_IODELAY_SITE", "OCE_OLOGIC_SITE",
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"ODATAIN_IODELAY_SITE", "OFB_ILOGIC_SITE",
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"OQ_OLOGIC_SITE", "RCLK_IODELAY_SITE",
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"READEN_IODELAY_UNUSED_SITE", "REV_ILOGIC_SITE",
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"REV_OLOGIC_SITE", "RST_IODELAY_SITE",
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"SHIFTIN_ILOGIC_SITE", "SHIFTOUT_ILOGIC_SITE",
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"SR_ILOGIC_SITE", "SR_OLOGIC_SITE",
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"TCE_OLOGIC_SITE", "TFB_ILOGIC_SITE",
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"T_IODELAY_SITE", "TOUT_IODELAY_SITE",
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"TQ_OLOGIC_SITE", "TRAIN_OLOGIC_SITE",
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"VALID_ILOGIC_SITE", "" };
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for (i = 0; mcb_2[i][0]; i++) {
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rc = add_connpt_2(model, y, x, mcb_2[i], "", "_S",
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dup_warn);
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}
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}
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rc = add_connpt_name(model, y, x, "DATAOUT2_IODELAY_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "DATAOUT2_IODELAY2_SITE_S",
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (i = 0; i <= 2; i++) {
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rc = add_connpt_2(model, y, x, pf("IOI_CLK%iINTER", i),
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"_M", "_S", dup_warn);
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if (rc) goto xout;
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}
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for (i = 0; i <= 1; i++) {
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rc = add_connpt_2(model, y, x, pf("IOI_CLKDIST_IOCE%i", i),
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"_M", "_S", dup_warn);
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if (rc) goto xout;
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}
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rc = add_connpt_2(model, y, x, "IOI_CLKDIST_CLK0_ILOGIC", "_M", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, "IOI_CLKDIST_CLK0_OLOGIC", "_M", "_S",
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dup_warn);
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if (rc) goto xout;
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rc = add_connpt_2(model, y, x, "IOI_CLKDIST_CLK1", "_M", "_S",
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dup_warn);
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if (rc) goto xout;
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if (side == TOP_S || side == BOTTOM_S) {
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static const char* mcb_2[] = {
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"IOI_MCB_DQIEN", "IOI_MCB_INBYP",
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"IOI_MCB_IN", "IOI_MCB_OUTN",
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"IOI_MCB_OUTP", "" };
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static const char* mcb_1[] = {
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"IOI_MCB_DRPADD", "IOI_MCB_DRPBROADCAST",
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"IOI_MCB_DRPCLK", "IOI_MCB_DRPCS",
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"IOI_MCB_DRPSDI", "IOI_MCB_DRPSDO",
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"IOI_MCB_DRPTRAIN", "" };
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for (i = 0; mcb_2[i][0]; i++) {
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rc = add_connpt_2(model, y, x, mcb_2[i], "_M", "_S",
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dup_warn);
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if (rc) goto xout;
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}
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for (i = 0; mcb_1[i][0]; i++) {
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rc = add_connpt_name(model, y, x, mcb_1[i],
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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}
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return 0;
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xout:
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return rc;
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}
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int init_ports(struct fpga_model* model, int dup_warn)
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{
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int x, y, i, j, k, row_num, row_pos, rc;
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RC_CHECK(model);
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// inner and outer IO tiles (ILOGIC/ILOGIC/IODELAY)
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for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
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if (has_device(model, TOP_OUTER_IO, x, DEV_ILOGIC)) {
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rc = init_iologic_ports(model, TOP_OUTER_IO, x, TOP_S, dup_warn);
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if (rc) goto xout;
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}
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if (has_device(model, TOP_INNER_IO, x, DEV_ILOGIC)) {
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rc = init_iologic_ports(model, TOP_INNER_IO, x, TOP_S, dup_warn);
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if (rc) goto xout;
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}
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if (has_device(model, model->y_height - BOT_INNER_IO, x, DEV_ILOGIC)) {
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rc = init_iologic_ports(model, model->y_height - BOT_INNER_IO, x, BOTTOM_S, dup_warn);
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if (rc) goto xout;
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}
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if (has_device(model, model->y_height - BOT_OUTER_IO, x, DEV_ILOGIC)) {
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rc = init_iologic_ports(model, model->y_height - BOT_OUTER_IO, x, BOTTOM_S, dup_warn);
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if (rc) goto xout;
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}
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}
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (has_device(model, y, LEFT_IO_DEVS, DEV_ILOGIC)) {
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rc = init_iologic_ports(model, y, LEFT_IO_DEVS, LEFT_S, dup_warn);
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if (rc) goto xout;
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}
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if (has_device(model, y, model->x_width - RIGHT_IO_DEVS_O, DEV_ILOGIC)) {
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rc = init_iologic_ports(model, y, model->x_width - RIGHT_IO_DEVS_O, RIGHT_S, dup_warn);
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if (rc) goto xout;
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}
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}
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for (x = 0; x < model->x_width; x++) {
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// VCC, GND and fans
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if (is_atx(X_ROUTING_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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continue;
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rc = add_connpt_name(model, y, x, "VCC_WIRE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "GND_WIRE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "KEEP1_WIRE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "FAN",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "FAN_B",
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dup_warn, 0, 0);
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if (rc) goto xout;
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if (!is_atyx(YX_IO_ROUTING, model, y, x)) {
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for (i = 0; i <= 1; i++) {
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rc = add_connpt_name(model, y, x, pf("GFAN%i", i),
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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} else {
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if (!is_atx(X_CENTER_ROUTING_COL, model, x)
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|| is_aty(Y_TOPBOT_IO_RANGE, model, y)) {
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// In the center those 2 wires are connected
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// to the PLL, but elsewhere? Not clear what they
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// connect to...
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rc = add_connpt_name(model, y, x,
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logicin_s(X_A5, 1 /* routing_io */),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x,
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logicin_s(X_B4, 1 /* routing_io */),
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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}
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}
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}
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// logicin
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if (is_atx(X_FABRIC_LOGIC_XL_ROUTING_COL
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|X_CENTER_ROUTING_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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static const int n[] = { 36, 44, 53, 61, 62 };
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if (is_aty(Y_TOPBOT_IO_RANGE, model, y)
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&& !is_atx(X_ROUTING_NO_IO, model, x))
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continue;
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if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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continue;
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if (is_atx(X_CENTER_ROUTING_COL, model, x)
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&& (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y+1)
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|| is_aty(Y_ROW_HORIZ_AXSYMM, model, y-1)))
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continue;
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for (i = 0; i < sizeof(n)/sizeof(*n); i++) {
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rc = add_connpt_name(model, y, x,
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pf("LOGICIN_B%i", n[i]), dup_warn, 0, 0);
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if (rc) goto xout;
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}
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}
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}
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// bram
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if (is_atx(X_FABRIC_BRAM_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (YX_TILE(model, y, x)->flags & TF_BRAM_DEV) {
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static const char* pass_str[3] = {"RAMB16BWER", "RAMB8BWER_0", "RAMB8BWER_1"};
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// pass 0 is ramb16, pass 1 and 2 are for ramb8
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for (i = 0; i <= 2; i++) {
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for (j = 'A'; j <= 'B'; j++) {
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rc = add_connpt_name(model, y, x, pf("%s_CLK%c", pass_str[i], j),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_EN%c", pass_str[i], j),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_REGCE%c", pass_str[i], j),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_RST%c", pass_str[i], j),
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (k = 0; k <= (!i ? 3 : 1); k++) {
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rc = add_connpt_name(model, y, x, pf("%s_DIP%c%i", pass_str[i], j, k),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_DOP%c%i", pass_str[i], j, k),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_WE%c%i", pass_str[i], j, k),
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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for (k = 0; k <= (!i ? 13 : 12); k++) {
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rc = add_connpt_name(model, y, x, pf("%s_ADDR%c%i", pass_str[i], j, k),
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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for (k = 0; k <= (!i ? 31 : 15); k++) {
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rc = add_connpt_name(model, y, x, pf("%s_DI%c%i", pass_str[i], j, k),
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, pf("%s_DO%c%i", pass_str[i], j, k),
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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}
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}
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}
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}
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}
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// macc
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if (is_atx(X_FABRIC_MACC_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (YX_TILE(model, y, x)->flags & TF_MACC_DEV) {
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static const char* pref[] = {"CE", "RST", ""};
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static const char* seq[] = {"A", "B", "C", "D", "M", "P", "OPMODE", ""};
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is_in_row(model, y, &row_num, &row_pos);
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if (!row_num && row_pos == LAST_POS_IN_ROW) {
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rc = add_connpt_name(model, y, x, "CARRYIN_DSP48A1_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (i = 0; i <= 47; i++) {
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rc = add_connpt_name(model, y, x, pf("PCIN%i_DSP48A1_SITE", i),
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dup_warn, 0, 0);
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if (rc) goto xout;
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}
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}
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rc = add_connpt_name(model, y, x, "CLK_DSP48A1_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "CARRYOUT_DSP48A1_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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rc = add_connpt_name(model, y, x, "CARRYOUTF_DSP48A1_SITE",
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (i = 0; pref[i][0]; i++) {
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rc = add_connpt_name(model, y, x, pf("%sCARRYIN_DSP48A1_SITE", pref[i]),
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dup_warn, 0, 0);
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if (rc) goto xout;
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for (j = 0; seq[j][0]; j++) {
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rc = add_connpt_name(model, y, x, pf("%s%s_DSP48A1_SITE", pref[i], seq[j]),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i <= 17; i++) {
|
|
rc = add_connpt_name(model, y, x, pf("A%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
rc = add_connpt_name(model, y, x, pf("B%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
rc = add_connpt_name(model, y, x, pf("D%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
rc = add_connpt_name(model, y, x, pf("BCOUT%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
}
|
|
for (i = 0; i <= 47; i++) {
|
|
rc = add_connpt_name(model, y, x, pf("C%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
rc = add_connpt_name(model, y, x, pf("P%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
rc = add_connpt_name(model, y, x, pf("PCOUT%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
}
|
|
for (i = 0; i <= 35; i++) {
|
|
rc = add_connpt_name(model, y, x, pf("M%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
}
|
|
for (i = 0; i <= 7; i++) {
|
|
rc = add_connpt_name(model, y, x, pf("OPMODE%i_DSP48A1_SITE", i),
|
|
dup_warn, 0, 0);
|
|
if (rc) goto xout;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
xout:
|
|
return rc;
|
|
}
|