540 lines
17 KiB
C
540 lines
17 KiB
C
//
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// Author: Wolfgang Spraul
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//
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// This is free and unencumbered software released into the public domain.
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// For details see the UNLICENSE file at the root of the source tree.
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//
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#include <stdarg.h>
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#include "model.h"
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#include "control.h"
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static int add_dev(struct fpga_model* model,
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int y, int x, int type, int subtype);
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static int init_iob(struct fpga_model* model, int y, int x, int idx);
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static int init_logic(struct fpga_model* model, int y, int x, int idx);
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int init_devices(struct fpga_model* model)
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{
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int x, y, i, j, rc;
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// DCM, PLL
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW-1 + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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x = model->center_x-CENTER_CMTPLL_O;
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if (i%2) {
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if ((rc = add_dev(model, y, x, DEV_DCM, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_DCM, 0))) goto fail;
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} else
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if ((rc = add_dev(model, y, x, DEV_PLL, 0))) goto fail;
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}
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// BSCAN
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y = TOP_IO_TILES;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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// BSCAN, OCT_CALIBRATE
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y = TOP_IO_TILES+1;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BSCAN, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_OCT_CALIBRATE, 0))) goto fail;
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// ICAP, SPI_ACCESS, OCT_CALIBRATE
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y = model->y_height-BOT_IO_TILES-1;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_ICAP, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_SPI_ACCESS, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_OCT_CALIBRATE, 0))) goto fail;
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// STARTUP, POST_CRC_INTERNAL, SLAVE_SPI, SUSPEND_SYNC
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y = model->y_height-BOT_IO_TILES-2;
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x = model->x_width-RIGHT_IO_DEVS_O;
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if ((rc = add_dev(model, y, x, DEV_STARTUP, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_POST_CRC_INTERNAL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_SLAVE_SPI, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_SUSPEND_SYNC, 0))) goto fail;
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// BUFGMUX
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y = model->center_y;
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x = model->center_x;
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for (i = 0; i < 16; i++)
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if ((rc = add_dev(model, y, x, DEV_BUFGMUX, 0))) goto fail;
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// BUFIO, BUFIO_FB, BUFPLL, BUFPLL_MCB
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y = TOP_OUTER_ROW;
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x = model->center_x-CENTER_CMTPLL_O;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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y = model->center_y;
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x = LEFT_OUTER_COL;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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y = model->center_y;
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x = model->x_width - RIGHT_OUTER_O;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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y = model->y_height - BOT_OUTER_ROW;
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x = model->center_x-CENTER_CMTPLL_O;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFPLL_MCB, 0))) goto fail;
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for (j = 0; j < 8; j++) {
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if ((rc = add_dev(model, y, x, DEV_BUFIO, 0))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_BUFIO_FB, 0))) goto fail;
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}
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// BUFH
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for (i = 0; i < model->cfg_rows; i++) {
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y = TOP_IO_TILES + HALF_ROW + i*ROW_SIZE;
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if (y > model->center_y) y++; // central regs
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x = model->center_x;
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for (j = 0; j < 32; j++)
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if ((rc = add_dev(model, y, x, DEV_BUFH, 0))) goto fail;
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}
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// BRAM
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for (x = 0; x < model->x_width; x++) {
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if (!is_atx(X_FABRIC_BRAM_COL, model, x))
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continue;
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for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
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if (!(YX_TILE(model, y, x)->flags & TF_BRAM_DEV))
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continue;
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if ((rc = add_dev(model, y, x, DEV_BRAM16, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_BRAM8, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_BRAM8, 0)))
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goto fail;
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}
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}
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// MACC
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for (x = 0; x < model->x_width; x++) {
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if (!is_atx(X_FABRIC_MACC_COL, model, x))
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continue;
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for (y = TOP_IO_TILES; y < model->y_height-BOT_IO_TILES; y++) {
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if (!(YX_TILE(model, y, x)->flags & TF_MACC_DEV))
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continue;
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if ((rc = add_dev(model, y, x, DEV_MACC, 0))) goto fail;
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}
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}
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// ILOGIC/OLOGIC/IODELAY
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for (x = LEFT_SIDE_WIDTH; x < model->x_width - RIGHT_SIDE_WIDTH; x++) {
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if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)
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|| is_atx(X_ROUTING_NO_IO, model, x-1))
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continue;
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for (i = 0; i <= 1; i++) {
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y = TOP_IO_TILES+i;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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y = model->y_height-BOT_IO_TILES-i-1;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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}
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}
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_LEFT_WIRED, model, y)) {
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x = LEFT_IO_DEVS;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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}
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if (is_aty(Y_RIGHT_WIRED, model, y)) {
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x = model->x_width-RIGHT_IO_DEVS_O;
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for (j = 0; j <= 1; j++) {
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if ((rc = add_dev(model, y, x, DEV_ILOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_OLOGIC, 0)))
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goto fail;
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if ((rc = add_dev(model, y, x, DEV_IODELAY, 0)))
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goto fail;
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}
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}
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}
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// IOB
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for (x = 0; x < model->x_width; x++) {
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// Note that the order of sub-types IOBM and IOBS must match
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// the order in the control.c sitename arrays.
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if (is_atx(X_OUTER_LEFT, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_LEFT_WIRED, model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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}
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}
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if (is_atx(X_OUTER_RIGHT, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_RIGHT_WIRED, model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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}
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}
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if (is_atx(X_FABRIC_LOGIC_ROUTING_COL|X_CENTER_ROUTING_COL, model, x)
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&& !is_atx(X_ROUTING_NO_IO, model, x)) {
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y = TOP_OUTER_ROW;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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y = model->y_height-BOT_OUTER_ROW;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBS))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_IOB, IOBM))) goto fail;
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}
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}
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// TIEOFF
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y = model->center_y;
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x = LEFT_OUTER_COL;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = model->center_y;
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x = model->x_width-RIGHT_OUTER_O;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = TOP_OUTER_ROW;
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x = model->center_x-1;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = model->y_height-BOT_OUTER_ROW;
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x = model->center_x-CENTER_CMTPLL_O;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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for (x = 0; x < model->x_width; x++) {
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if (is_atx(X_LEFT_IO_DEVS_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_LEFT_WIRED, model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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}
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}
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if (is_atx(X_RIGHT_IO_DEVS_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!is_aty(Y_RIGHT_WIRED, model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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}
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}
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if (is_atx(X_CENTER_CMTPLL_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (!(YX_TILE(model, y, x)->flags & TF_PLL_DEV))
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continue;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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}
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}
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if (is_atx(X_ROUTING_COL, model, x)) {
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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if (is_aty(Y_ROW_HORIZ_AXSYMM|Y_CHIP_HORIZ_REGS,
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model, y))
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continue;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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}
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}
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if (is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x)
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&& !is_atx(X_ROUTING_NO_IO, model, x-1)) {
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for (i = 0; i <= 1; i++) {
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y = TOP_IO_TILES+i;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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y = model->y_height-BOT_IO_TILES-i-1;
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if ((rc = add_dev(model, y, x, DEV_TIEOFF, 0))) goto fail;
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}
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}
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}
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// LOGIC
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for (x = 0; x < model->x_width; x++) {
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if (!is_atx(X_FABRIC_LOGIC_COL|X_CENTER_LOGIC_COL, model, x))
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continue;
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for (y = TOP_IO_TILES; y < model->y_height - BOT_IO_TILES; y++) {
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// M and L are at index 0 (DEV_LOGM and DEV_LOGL), X is at index 1 (DEV_LOGX).
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if (YX_TILE(model, y, x)->flags & TF_LOGIC_XM_DEV) {
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if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_M))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_X))) goto fail;
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}
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if (YX_TILE(model, y, x)->flags & TF_LOGIC_XL_DEV) {
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if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_L))) goto fail;
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if ((rc = add_dev(model, y, x, DEV_LOGIC, LOGIC_X))) goto fail;
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}
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}
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}
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return 0;
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fail:
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return rc;
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}
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void free_devices(struct fpga_model* model)
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{
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struct fpga_tile* tile;
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int x, y, i;
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for (x = 0; x < model->x_width; x++) {
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for (y = 0; y < model->y_height; y++) {
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tile = YX_TILE(model, y, x);
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if (!tile->num_devs)
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continue;
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if (!tile->devs) {
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HERE();
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continue;
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}
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for (i = 0; i < tile->num_devs; i++) {
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fdev_delete(model, y, x, tile->devs[i].type,
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fdev_typeidx(model, y, x, i));
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}
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free(tile->devs);
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tile->devs = 0;
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tile->num_devs = 0;
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}
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}
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}
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#define DEV_INCREMENT 4
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static int add_dev(struct fpga_model* model,
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int y, int x, int type, int subtype)
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{
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struct fpga_tile* tile;
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int new_dev_i;
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int rc;
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tile = YX_TILE(model, y, x);
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if (!(tile->num_devs % DEV_INCREMENT)) {
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void* new_ptr = realloc(tile->devs,
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(tile->num_devs+DEV_INCREMENT)*sizeof(*tile->devs));
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EXIT(!new_ptr);
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memset(new_ptr + tile->num_devs * sizeof(*tile->devs),
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0, DEV_INCREMENT*sizeof(*tile->devs));
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tile->devs = new_ptr;
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}
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new_dev_i = tile->num_devs;
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tile->num_devs++;
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// init new device
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tile->devs[new_dev_i].type = type;
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tile->devs[new_dev_i].subtype = subtype;
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if (type == DEV_IOB) {
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rc = init_iob(model, y, x, new_dev_i);
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if (rc) FAIL(rc);
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} else if (type == DEV_LOGIC) {
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rc = init_logic(model, y, x, new_dev_i);
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if (rc) FAIL(rc);
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}
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return 0;
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fail:
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return rc;
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}
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static int init_iob(struct fpga_model* model, int y, int x, int idx)
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{
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struct fpga_tile* tile;
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const char* prefix;
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int type_idx, rc;
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char tmp_str[128];
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tile = YX_TILE(model, y, x);
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type_idx = fdev_typeidx(model, y, x, idx);
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if (!y)
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prefix = "TIOB";
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else if (y == model->y_height - BOT_OUTER_ROW)
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prefix = "BIOB";
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else if (x == 0)
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prefix = "LIOB";
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else if (x == model->x_width - RIGHT_OUTER_O)
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prefix = "RIOB";
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else
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FAIL(EINVAL);
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tile->devs[idx].pinw = calloc((IOB_LAST_OUTPUT_PINW+1)
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*sizeof(tile->devs[idx].pinw[0]), /*elsize*/ 1);
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if (!tile->devs[idx].pinw) FAIL(ENOMEM);
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tile->devs[idx].num_pinw_total = IOB_LAST_OUTPUT_PINW+1;
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tile->devs[idx].num_pinw_in = IOB_LAST_INPUT_PINW+1;
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snprintf(tmp_str, sizeof(tmp_str), "%s_O%i_PINW", prefix, type_idx);
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rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
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&tile->devs[idx].pinw[IOB_IN_O], 0);
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if (rc) FAIL(rc);
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snprintf(tmp_str, sizeof(tmp_str), "%s_T%i_PINW", prefix, type_idx);
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_IN_T], 0);
|
|
if (rc) FAIL(rc);
|
|
snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFI_IN%i", prefix, type_idx);
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_IN_DIFFI_IN], 0);
|
|
if (rc) FAIL(rc);
|
|
snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_IN%i", prefix, type_idx);
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_IN_DIFFO_IN], 0);
|
|
if (rc) FAIL(rc);
|
|
|
|
snprintf(tmp_str, sizeof(tmp_str), "%s_IBUF%i_PINW", prefix, type_idx);
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_OUT_I], 0);
|
|
if (rc) FAIL(rc);
|
|
snprintf(tmp_str, sizeof(tmp_str), "%s_PADOUT%i", prefix, type_idx);
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_OUT_PADOUT], 0);
|
|
if (rc) FAIL(rc);
|
|
snprintf(tmp_str, sizeof(tmp_str), "%s_DIFFO_OUT%i", prefix, type_idx);
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_OUT_DIFFO_OUT], 0);
|
|
if (rc) FAIL(rc);
|
|
|
|
if (!x && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 1)
|
|
strcpy(tmp_str, "LIOB_TOP_PCI_RDY0");
|
|
else if (!x && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 0)
|
|
strcpy(tmp_str, "LIOB_BOT_PCI_RDY0");
|
|
else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y - CENTER_TOP_IOB_O && type_idx == 0)
|
|
strcpy(tmp_str, "RIOB_BOT_PCI_RDY0");
|
|
else if (x == model->x_width-RIGHT_OUTER_O && y == model->center_y + CENTER_BOT_IOB_O && type_idx == 1)
|
|
strcpy(tmp_str, "RIOB_TOP_PCI_RDY1");
|
|
else {
|
|
snprintf(tmp_str, sizeof(tmp_str),
|
|
"%s_PCI_RDY%i", prefix, type_idx);
|
|
}
|
|
rc = add_connpt_name(model, y, x, tmp_str, /*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[IOB_OUT_PCI_RDY], 0);
|
|
if (rc) FAIL(rc);
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|
|
|
|
static int init_logic(struct fpga_model* model, int y, int x, int idx)
|
|
{
|
|
struct fpga_tile* tile;
|
|
const char* pre;
|
|
int i, j, rc;
|
|
|
|
tile = YX_TILE(model, y, x);
|
|
if (tile->devs[idx].subtype == LOGIC_M)
|
|
pre = "M_";
|
|
else if (tile->devs[idx].subtype == LOGIC_L)
|
|
pre = "L_";
|
|
else if (tile->devs[idx].subtype == LOGIC_X) {
|
|
pre = is_atx(X_FABRIC_LOGIC_XL_COL|X_CENTER_LOGIC_COL, model, x)
|
|
? "XX_" : "X_";
|
|
} else FAIL(EINVAL);
|
|
|
|
tile->devs[idx].pinw = calloc((LO_LAST+1)
|
|
*sizeof(tile->devs[idx].pinw[0]), /*elsize*/ 1);
|
|
if (!tile->devs[idx].pinw) FAIL(ENOMEM);
|
|
tile->devs[idx].num_pinw_total = LO_LAST+1;
|
|
tile->devs[idx].num_pinw_in = LI_LAST+1;
|
|
|
|
for (i = 0; i < 4; i++) { // 'A' to 'D'
|
|
for (j = 0; j < 6; j++) {
|
|
rc = add_connpt_name(model, y, x, pf("%s%c%i", pre, 'A'+i, j+1),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_A1+i*6+j], 0);
|
|
if (rc) FAIL(rc);
|
|
}
|
|
rc = add_connpt_name(model, y, x, pf("%s%cX", pre, 'A'+i),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_AX+i], 0);
|
|
if (rc) FAIL(rc);
|
|
if (tile->devs[idx].subtype == LOGIC_M) {
|
|
rc = add_connpt_name(model, y, x, pf("%s%cI", pre, 'A'+i),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_AI+i], 0);
|
|
if (rc) FAIL(rc);
|
|
} else
|
|
tile->devs[idx].pinw[LI_AI+i] = STRIDX_NO_ENTRY;
|
|
rc = add_connpt_name(model, y, x, pf("%s%c", pre, 'A'+i),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LO_A+i], 0);
|
|
if (rc) FAIL(rc);
|
|
rc = add_connpt_name(model, y, x, pf("%s%cMUX", pre, 'A'+i),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LO_AMUX+i], 0);
|
|
if (rc) FAIL(rc);
|
|
rc = add_connpt_name(model, y, x, pf("%s%cQ", pre, 'A'+i),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LO_AQ+i], 0);
|
|
if (rc) FAIL(rc);
|
|
}
|
|
rc = add_connpt_name(model, y, x, pf("%sCLK", pre),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_CLK], 0);
|
|
if (rc) FAIL(rc);
|
|
rc = add_connpt_name(model, y, x, pf("%sCE", pre),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_CE], 0);
|
|
if (rc) FAIL(rc);
|
|
rc = add_connpt_name(model, y, x, pf("%sSR", pre),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_SR], 0);
|
|
if (rc) FAIL(rc);
|
|
if (tile->devs[idx].subtype == LOGIC_M) {
|
|
rc = add_connpt_name(model, y, x, pf("%sWE", pre),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_WE], 0);
|
|
if (rc) FAIL(rc);
|
|
} else
|
|
tile->devs[idx].pinw[LI_WE] = STRIDX_NO_ENTRY;
|
|
if (tile->devs[idx].subtype != LOGIC_X
|
|
&& ((is_atx(X_ROUTING_NO_IO, model, x-1)
|
|
&& is_aty(Y_INNER_BOTTOM, model, y+1))
|
|
|| (!is_atx(X_ROUTING_NO_IO, model, x-1)
|
|
&& is_aty(Y_BOT_INNER_IO, model, y+1)))) {
|
|
rc = add_connpt_name(model, y, x, pf("%sCIN", pre),
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LI_CIN], 0);
|
|
if (rc) FAIL(rc);
|
|
} else
|
|
tile->devs[idx].pinw[LI_CIN] = STRIDX_NO_ENTRY;
|
|
if (tile->devs[idx].subtype == LOGIC_M) {
|
|
rc = add_connpt_name(model, y, x, "M_COUT",
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LO_COUT], 0);
|
|
if (rc) FAIL(rc);
|
|
} else if (tile->devs[idx].subtype == LOGIC_L) {
|
|
rc = add_connpt_name(model, y, x, "XL_COUT",
|
|
/*dup_warn*/ 1,
|
|
&tile->devs[idx].pinw[LO_COUT], 0);
|
|
if (rc) FAIL(rc);
|
|
} else
|
|
tile->devs[idx].pinw[LO_COUT] = STRIDX_NO_ENTRY;
|
|
|
|
return 0;
|
|
fail:
|
|
return rc;
|
|
}
|