public domain tools for FPGAs
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Wolfgang Spraul d54a0ff81d more switches
2012-09-13 09:08:47 +02:00
autotest.gold better autotest framework, make test 2012-08-31 08:52:27 +02:00
debian debian: fix man page add libs package 2012-09-08 13:09:04 +08:00
.gitignore switch cleanup 2012-09-13 03:35:16 +02:00
autotest_diff.sh autotest cleanup 2012-08-31 07:05:58 +02:00
autotest.c switch cleanup 2012-09-13 03:35:16 +02:00
bit_frames.c more switches 2012-09-13 09:08:47 +02:00
bit_regs.c minor testing additions - next: big autotest cleanup 2012-08-30 14:40:54 +02:00
bit.h switch cleanup 2012-09-13 03:35:16 +02:00
bit2fp.1 add simple man page for bit2fp and fp2bit 2012-09-08 13:07:42 +08:00
bit2fp.c switch cleanup 2012-09-13 03:35:16 +02:00
control.c more switches 2012-09-13 09:08:47 +02:00
control.h more switches 2012-09-13 09:08:47 +02:00
draw_svg_tiles.c cleanup, some more devices 2012-08-02 08:01:46 +02:00
floorplan.c a few more short north and south wires, autotester 2012-09-12 03:41:32 +02:00
floorplan.h minor floorplan fixes 2012-08-25 12:21:36 +02:00
fp2bit.1 add simple man page for bit2fp and fp2bit 2012-09-08 13:07:42 +08:00
fp2bit.c broke bits.c into 2 separate files bit_regs.c and bit_frames.c 2012-08-19 13:31:14 +02:00
fpgastyle.css css 2012-06-23 16:55:17 +02:00
helper.c minor testing and lut fixes, merge_log.sh helper script 2012-08-29 03:15:31 +02:00
helper.h minor testing and lut fixes, merge_log.sh helper script 2012-08-29 03:15:31 +02:00
hstrrep.c minor testing and lut fixes, merge_log.sh helper script 2012-08-29 03:15:31 +02:00
lib.svg tiny svg steps 2012-06-18 04:47:51 +02:00
LINKS ran into a wall with routing drawings, starting a C model of the chip 2012-07-11 16:01:01 +02:00
lut.svg finished lut equiv. schematic 2012-06-23 16:54:53 +02:00
Makefile switch cleanup 2012-09-13 03:35:16 +02:00
merge_log.sh slightly improved switch design, preparing for switch device 2012-09-05 04:52:43 +02:00
merge_seq.c higher-level compiler warnings - thanks to Werner! 2012-08-14 03:04:33 +02:00
model_conns.c a few more short north and south wires, autotester 2012-09-12 03:41:32 +02:00
model_devices.c more switches 2012-09-13 09:08:47 +02:00
model_helper.c minor testing and lut fixes, merge_log.sh helper script 2012-08-29 03:15:31 +02:00
model_main.c started with routing switches 2012-09-07 14:21:36 +02:00
model_ports.c logic block and logicin ports 2012-08-24 03:51:09 +02:00
model_switches.c started with routing switches 2012-09-07 14:21:36 +02:00
model_tiles.c tile and x-coord flag cleanup 2012-08-24 00:44:34 +02:00
model.h more switches 2012-09-13 09:08:47 +02:00
new_fp.c minor floorplan fixes 2012-08-25 12:21:36 +02:00
pair2net.c minor cleanup 2012-08-16 12:17:37 +02:00
parts.c better routing from and to logic block 2012-08-28 09:23:52 +02:00
parts.h better routing from and to logic block 2012-08-28 09:23:52 +02:00
README a few more short north and south wires, autotester 2012-09-12 03:41:32 +02:00
sort_seq.c autotester 2012-08-16 10:57:51 +02:00
UNLICENSE ramb16 cleanup, going public domain, see unlicense.org 2012-06-26 01:45:43 +02:00

Introduction
 fpgatools is a toolchain to program flexible programmable gate arrays
 (FPGAs). The only supported chip at this time is the xc6slx9, a cheap
 (ca. 10 USD) but powerful 45nm-generation chip with about 2400 LUTs,
 block ram and multiply-accumulate devices.
 The principles of fpgatools are:

 *) reach the maximum physical performance of the chip
 *) fast development cycles
 *) independent toolchain that only depends on other free software
 *) lightweight C implementation without GUI
 *) supported platform: Linux
 *) license: public domain

FAQ
 todo

Libraries

- libfpga-test       autotest suite
- libfpga-cores      reusable cores
- libfpga-stdlib     standard design elements on top of libfpga-control
- libfpga-control    programmatic access to libfpga-model
- libfpga-model      memory-only representation of an FPGA
- libfpga-floorplan  reads and writes .fp floorplan files
- libfpga-bit        reads and writes .bit bitstream files

Design Utilities

- new_fp             creates empty .fp floorplan file
- fp2bit             converts .fp floorplan into .bit bitstream
- bit2fp             converts .bit bitstream into .fp floorplan
- draw_svg_tiles     draws a simple .svg showing tile types

fpgatools Development Utilities

- autotest           executes test suite
- sort_seq           sorts line-based text file by sequence numbers in strings
- merge_seq          merges a pre-sorted text file into wire sequences
- pair2net           reads the first two words per line and builds nets
- hstrrep            high-speed hashed array based search and replace util

Design Principles

- small independent command line utilities, no GUI
- plain C, no C++
- simple Makefiles
- text-based file formats
- automatic test suite
- public domain software

TODO (as of 2012-08, expected time to delivery: months to years
      completion status overall: 1%)

* support chips other than xc6slx9, maybe an ftg256 or fgg484-packaged
  xc6 or the xc7a100
* many more test cases for autotester
* smarter autotester that can remember and verify groups of tests,
  automatically oversee test execution, etc.
* 3 Debian packages: libfpga, libfpga-doc, fpgatools
* auto-crc calculation in .bit file
* many more cases in logic block configuration
* configuration of bram and macc blocks, bram initialization data
* routing switches
* many more cases in model of switches and inter-tile connections
* write standard design elements for libfpga-stdlib library
* support lm32 or openrisc core, either via libfpga or iverilog backend
* ipv6 or vnc in hardware?
* iverilog fpga backend

ChangeLog

2012-08-20
* Beginning of full fidelity circle with model, floorplan, conversion from
  and to bitstream and floorplan formats.

2012-06-03
* Project started.