3546 lines
110 KiB
HTML
3546 lines
110 KiB
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<HTML><HEAD><TITLE>Man page of AS</TITLE>
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</HEAD><BODY>
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<H1>AS</H1>
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Section: GNU Development Tools (1)<BR>Updated: 2021-01-21<BR><A HREF="#index">Index</A>
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<A HREF="/cgi-bin/man/man2html">Return to Main Contents</A><HR>
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<A NAME="lbAB"> </A>
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<H2>NAME</H2>
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AS - the portable GNU assembler.
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<A NAME="lbAC"> </A>
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<H2>SYNOPSIS</H2>
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as [<B>-a</B>[<B>cdghlns</B>][=<I>file</I>]] [<B>--alternate</B>] [<B>-D</B>]
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<BR> [<B>--compress-debug-sections</B>] [<B>--nocompress-debug-sections</B>]
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<BR> [<B>--debug-prefix-map</B> <I>old</I>=<I>new</I>]
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<BR> [<B>--defsym</B> <I>sym</I>=<I>val</I>] [<B>-f</B>] [<B>-g</B>] [<B>--gstabs</B>]
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<BR> [<B>--gstabs+</B>] [<B>--gdwarf-2</B>] [<B>--gdwarf-sections</B>]
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<BR> [<B>--gdwarf-cie-version</B>=<I></I><FONT SIZE="-1"><I>VERSION</I></FONT><I></I>]
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<BR> [<B>--help</B>] [<B>-I</B> <I>dir</I>] [<B>-J</B>]
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<BR> [<B>-K</B>] [<B>-L</B>] [<B>--listing-lhs-width</B>=<I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I>]
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<BR> [<B>--listing-lhs-width2</B>=<I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I>] [<B>--listing-rhs-width</B>=<I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I>]
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<BR> [<B>--listing-cont-lines</B>=<I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I>] [<B>--keep-locals</B>]
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<BR> [<B>--no-pad-sections</B>]
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<BR> [<B>-o</B> <I>objfile</I>] [<B>-R</B>]
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<BR> [<B>--hash-size</B>=<I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I>] [<B>--reduce-memory-overheads</B>]
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<BR> [<B>--statistics</B>]
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<BR> [<B>-v</B>] [<B>-version</B>] [<B>--version</B>]
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<BR> [<B>-W</B>] [<B>--warn</B>] [<B>--fatal-warnings</B>] [<B>-w</B>] [<B>-x</B>]
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<BR> [<B>-Z</B>] [<B>@</B><I></I><FONT SIZE="-1"><I>FILE</I></FONT><I></I>]
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<BR> [<B>--sectname-subst</B>] [<B>--size-check=[error|warning]</B>]
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<BR> [<B>--elf-stt-common=[no|yes]</B>]
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<BR> [<B>--generate-missing-build-notes=[no|yes]</B>]
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<BR> [<B>--target-help</B>] [<I>target-options</I>]
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<BR> [<B>--</B>|<I>files</I> ...]
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<A NAME="lbAD"> </A>
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<H2>TARGET</H2>
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<I>Target AArch64 options:</I>
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<BR> [<B>-EB</B>|<B>-EL</B>]
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<BR> [<B>-mabi</B>=<I></I><FONT SIZE="-1"><I>ABI</I></FONT><I></I>]
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<P>
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<I>Target Alpha options:</I>
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<BR> [<B>-m</B><I>cpu</I>]
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<BR> [<B>-mdebug</B> | <B>-no-mdebug</B>]
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<BR> [<B>-replace</B> | <B>-noreplace</B>]
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<BR> [<B>-relax</B>] [<B>-g</B>] [<B>-G</B><I>size</I>]
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<BR> [<B>-F</B>] [<B>-32addr</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>ARC</I></FONT><I> options:</I>
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<BR> [<B>-mcpu=</B><I>cpu</I>]
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<BR> [<B>-mA6</B>|<B>-mARC600</B>|<B>-mARC601</B>|<B>-mA7</B>|<B>-mARC700</B>|<B>-mEM</B>|<B>-mHS</B>]
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<BR> [<B>-mcode-density</B>]
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<BR> [<B>-mrelax</B>]
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<BR> [<B>-EB</B>|<B>-EL</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>ARM</I></FONT><I> options:</I>
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<BR> [<B>-mcpu</B>=<I>processor</I>[+<I>extension</I>...]]
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<BR> [<B>-march</B>=<I>architecture</I>[+<I>extension</I>...]]
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<BR> [<B>-mfpu</B>=<I>floating-point-format</I>]
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<BR> [<B>-mfloat-abi</B>=<I>abi</I>]
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<BR> [<B>-meabi</B>=<I>ver</I>]
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<BR> [<B>-mthumb</B>]
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<BR> [<B>-EB</B>|<B>-EL</B>]
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<BR> [<B>-mapcs-32</B>|<B>-mapcs-26</B>|<B>-mapcs-float</B>|
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<BR> <B>-mapcs-reentrant</B>]
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<BR> [<B>-mthumb-interwork</B>] [<B>-k</B>]
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<P>
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<I>Target Blackfin options:</I>
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<BR> [<B>-mcpu</B>=<I>processor</I>[-<I>sirevision</I>]]
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<BR> [<B>-mfdpic</B>]
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<BR> [<B>-mno-fdpic</B>]
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<BR> [<B>-mnopic</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>BPF</I></FONT><I> options:</I>
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<BR> [<B>-EL</B>] [<B>-EB</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>CRIS</I></FONT><I> options:</I>
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<BR> [<B>--underscore</B> | <B>--no-underscore</B>]
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<BR> [<B>--pic</B>] [<B>-N</B>]
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<BR> [<B>--emulation=criself</B> | <B>--emulation=crisaout</B>]
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<BR> [<B>--march=v0_v10</B> | <B>--march=v10</B> | <B>--march=v32</B> | <B>--march=common_v10_v32</B>]
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<P>
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<I>Target C-SKY options:</I>
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<BR> [<B>-march=</B><I>arch</I>] [<B>-mcpu=</B><I>cpu</I>]
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<BR> [<B>-EL</B>] [<B>-mlittle-endian</B>] [<B>-EB</B>] [<B>-mbig-endian</B>]
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<BR> [<B>-fpic</B>] [<B>-pic</B>]
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<BR> [<B>-mljump</B>] [<B>-mno-ljump</B>]
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<BR> [<B>-force2bsr</B>] [<B>-mforce2bsr</B>] [<B>-no-force2bsr</B>] [<B>-mno-force2bsr</B>]
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<BR> [<B>-jsri2bsr</B>] [<B>-mjsri2bsr</B>] [<B>-no-jsri2bsr</B> ] [<B>-mno-jsri2bsr</B>]
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<BR> [<B>-mnolrw</B> ] [<B>-mno-lrw</B>]
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<BR> [<B>-melrw</B>] [<B>-mno-elrw</B>]
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<BR> [<B>-mlaf</B> ] [<B>-mliterals-after-func</B>]
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<BR> [<B>-mno-laf</B>] [<B>-mno-literals-after-func</B>]
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<BR> [<B>-mlabr</B>] [<B>-mliterals-after-br</B>]
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<BR> [<B>-mno-labr</B>] [<B>-mnoliterals-after-br</B>]
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<BR> [<B>-mistack</B>] [<B>-mno-istack</B>]
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<BR> [<B>-mhard-float</B>] [<B>-mmp</B>] [<B>-mcp</B>] [<B>-mcache</B>]
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<BR> [<B>-msecurity</B>] [<B>-mtrust</B>]
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<BR> [<B>-mdsp</B>] [<B>-medsp</B>] [<B>-mvdsp</B>]
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<P>
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<I>Target D10V options:</I>
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<BR> [<B>-O</B>]
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<P>
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<I>Target D30V options:</I>
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<BR> [<B>-O</B>|<B>-n</B>|<B>-N</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>EPIPHANY</I></FONT><I> options:</I>
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<BR> [<B>-mepiphany</B>|<B>-mepiphany16</B>]
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<P>
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<I>Target H8/300 options:</I>
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<BR> [-h-tick-hex]
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<P>
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<I>Target i386 options:</I>
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<BR> [<B>--32</B>|<B>--x32</B>|<B>--64</B>] [<B>-n</B>]
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<BR> [<B>-march</B>=<I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I>[+<I></I><FONT SIZE="-1"><I>EXTENSION</I></FONT><I></I>...]] [<B>-mtune</B>=<I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>IA-64</I></FONT><I> options:</I>
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<BR> [<B>-mconstant-gp</B>|<B>-mauto-pic</B>]
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<BR> [<B>-milp32</B>|<B>-milp64</B>|<B>-mlp64</B>|<B>-mp64</B>]
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<BR> [<B>-mle</B>|<B>mbe</B>]
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<BR> [<B>-mtune=itanium1</B>|<B>-mtune=itanium2</B>]
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<BR> [<B>-munwind-check=warning</B>|<B>-munwind-check=error</B>]
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<BR> [<B>-mhint.b=ok</B>|<B>-mhint.b=warning</B>|<B>-mhint.b=error</B>]
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<BR> [<B>-x</B>|<B>-xexplicit</B>] [<B>-xauto</B>] [<B>-xdebug</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>IP2K</I></FONT><I> options:</I>
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<BR> [<B>-mip2022</B>|<B>-mip2022ext</B>]
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<P>
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<I>Target M32C options:</I>
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<BR> [<B>-m32c</B>|<B>-m16c</B>] [-relax] [-h-tick-hex]
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<P>
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<I>Target M32R options:</I>
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<BR> [<B>--m32rx</B>|<B>--[no-]warn-explicit-parallel-conflicts</B>|
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<BR> <B>--W[n]p</B>]
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<P>
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<I>Target M680X0 options:</I>
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<BR> [<B>-l</B>] [<B>-m68000</B>|<B>-m68010</B>|<B>-m68020</B>|...]
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<P>
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<I>Target M68HC11 options:</I>
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<BR> [<B>-m68hc11</B>|<B>-m68hc12</B>|<B>-m68hcs12</B>|<B>-mm9s12x</B>|<B>-mm9s12xg</B>]
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<BR> [<B>-mshort</B>|<B>-mlong</B>]
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<BR> [<B>-mshort-double</B>|<B>-mlong-double</B>]
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<BR> [<B>--force-long-branches</B>] [<B>--short-branches</B>]
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<BR> [<B>--strict-direct-mode</B>] [<B>--print-insn-syntax</B>]
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<BR> [<B>--print-opcodes</B>] [<B>--generate-example</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>MCORE</I></FONT><I> options:</I>
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<BR> [<B>-jsri2bsr</B>] [<B>-sifilter</B>] [<B>-relax</B>]
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<BR> [<B>-mcpu=[210|340]</B>]
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<P>
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<I>Target Meta options:</I>
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<BR> [<B>-mcpu=</B><I>cpu</I>] [<B>-mfpu=</B><I>cpu</I>] [<B>-mdsp=</B><I>cpu</I>]
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<I>Target </I><FONT SIZE="-1"><I>MICROBLAZE</I></FONT><I> options:</I>
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<P>
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<I>Target </I><FONT SIZE="-1"><I>MIPS</I></FONT><I> options:</I>
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<BR> [<B>-nocpp</B>] [<B>-EL</B>] [<B>-EB</B>] [<B>-O</B>[<I>optimization level</I>]]
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<BR> [<B>-g</B>[<I>debug level</I>]] [<B>-G</B> <I>num</I>] [<B>-KPIC</B>] [<B>-call_shared</B>]
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<BR> [<B>-non_shared</B>] [<B>-xgot</B> [<B>-mvxworks-pic</B>]
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<BR> [<B>-mabi</B>=<I></I><FONT SIZE="-1"><I>ABI</I></FONT><I></I>] [<B>-32</B>] [<B>-n32</B>] [<B>-64</B>] [<B>-mfp32</B>] [<B>-mgp32</B>]
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<BR> [<B>-mfp64</B>] [<B>-mgp64</B>] [<B>-mfpxx</B>]
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<BR> [<B>-modd-spreg</B>] [<B>-mno-odd-spreg</B>]
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<BR> [<B>-march</B>=<I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I>] [<B>-mtune</B>=<I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I>] [<B>-mips1</B>] [<B>-mips2</B>]
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<BR> [<B>-mips3</B>] [<B>-mips4</B>] [<B>-mips5</B>] [<B>-mips32</B>] [<B>-mips32r2</B>]
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<BR> [<B>-mips32r3</B>] [<B>-mips32r5</B>] [<B>-mips32r6</B>] [<B>-mips64</B>] [<B>-mips64r2</B>]
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<BR> [<B>-mips64r3</B>] [<B>-mips64r5</B>] [<B>-mips64r6</B>]
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<BR> [<B>-construct-floats</B>] [<B>-no-construct-floats</B>]
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<BR> [<B>-mignore-branch-isa</B>] [<B>-mno-ignore-branch-isa</B>]
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<BR> [<B>-mnan=</B><I>encoding</I>]
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<BR> [<B>-trap</B>] [<B>-no-break</B>] [<B>-break</B>] [<B>-no-trap</B>]
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<BR> [<B>-mips16</B>] [<B>-no-mips16</B>]
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<BR> [<B>-mmips16e2</B>] [<B>-mno-mips16e2</B>]
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<BR> [<B>-mmicromips</B>] [<B>-mno-micromips</B>]
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<BR> [<B>-msmartmips</B>] [<B>-mno-smartmips</B>]
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<BR> [<B>-mips3d</B>] [<B>-no-mips3d</B>]
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<BR> [<B>-mdmx</B>] [<B>-no-mdmx</B>]
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<BR> [<B>-mdsp</B>] [<B>-mno-dsp</B>]
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<BR> [<B>-mdspr2</B>] [<B>-mno-dspr2</B>]
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<BR> [<B>-mdspr3</B>] [<B>-mno-dspr3</B>]
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<BR> [<B>-mmsa</B>] [<B>-mno-msa</B>]
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<BR> [<B>-mxpa</B>] [<B>-mno-xpa</B>]
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<BR> [<B>-mmt</B>] [<B>-mno-mt</B>]
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<BR> [<B>-mmcu</B>] [<B>-mno-mcu</B>]
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<BR> [<B>-mcrc</B>] [<B>-mno-crc</B>]
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<BR> [<B>-mginv</B>] [<B>-mno-ginv</B>]
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<BR> [<B>-mloongson-mmi</B>] [<B>-mno-loongson-mmi</B>]
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<BR> [<B>-mloongson-cam</B>] [<B>-mno-loongson-cam</B>]
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<BR> [<B>-mloongson-ext</B>] [<B>-mno-loongson-ext</B>]
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<BR> [<B>-mloongson-ext2</B>] [<B>-mno-loongson-ext2</B>]
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<BR> [<B>-minsn32</B>] [<B>-mno-insn32</B>]
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<BR> [<B>-mfix7000</B>] [<B>-mno-fix7000</B>]
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<BR> [<B>-mfix-rm7000</B>] [<B>-mno-fix-rm7000</B>]
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<BR> [<B>-mfix-vr4120</B>] [<B>-mno-fix-vr4120</B>]
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<BR> [<B>-mfix-vr4130</B>] [<B>-mno-fix-vr4130</B>]
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<BR> [<B>-mfix-r5900</B>] [<B>-mno-fix-r5900</B>]
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<BR> [<B>-mdebug</B>] [<B>-no-mdebug</B>]
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<BR> [<B>-mpdr</B>] [<B>-mno-pdr</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>MMIX</I></FONT><I> options:</I>
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<BR> [<B>--fixed-special-register-names</B>] [<B>--globalize-symbols</B>]
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<BR> [<B>--gnu-syntax</B>] [<B>--relax</B>] [<B>--no-predefined-symbols</B>]
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<BR> [<B>--no-expand</B>] [<B>--no-merge-gregs</B>] [<B>-x</B>]
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<BR> [<B>--linker-allocated-gregs</B>]
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<P>
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<I>Target Nios </I><FONT SIZE="-1"><I>II</I></FONT><I> options:</I>
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<BR> [<B>-relax-all</B>] [<B>-relax-section</B>] [<B>-no-relax</B>]
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<BR> [<B>-EB</B>] [<B>-EL</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>NDS32</I></FONT><I> options:</I>
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<BR> [<B>-EL</B>] [<B>-EB</B>] [<B>-O</B>] [<B>-Os</B>] [<B>-mcpu=</B><I>cpu</I>]
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<BR> [<B>-misa=</B><I>isa</I>] [<B>-mabi=</B><I>abi</I>] [<B>-mall-ext</B>]
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<BR> [<B>-m[no-]16-bit</B>] [<B>-m[no-]perf-ext</B>] [<B>-m[no-]perf2-ext</B>]
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<BR> [<B>-m[no-]string-ext</B>] [<B>-m[no-]dsp-ext</B>] [<B>-m[no-]mac</B>] [<B>-m[no-]div</B>]
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<BR> [<B>-m[no-]audio-isa-ext</B>] [<B>-m[no-]fpu-sp-ext</B>] [<B>-m[no-]fpu-dp-ext</B>]
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<BR> [<B>-m[no-]fpu-fma</B>] [<B>-mfpu-freg=</B><I></I><FONT SIZE="-1"><I>FREG</I></FONT><I></I>] [<B>-mreduced-regs</B>]
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<BR> [<B>-mfull-regs</B>] [<B>-m[no-]dx-regs</B>] [<B>-mpic</B>] [<B>-mno-relax</B>]
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<BR> [<B>-mb2bb</B>]
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<P>
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<I>Target </I><FONT SIZE="-1"><I>PDP11</I></FONT><I> options:</I>
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<BR> [<B>-mpic</B>|<B>-mno-pic</B>] [<B>-mall</B>] [<B>-mno-extensions</B>]
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<BR> [<B>-m</B><I>extension</I>|<B>-mno-</B><I>extension</I>]
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<BR> [<B>-m</B><I>cpu</I>] [<B>-m</B><I>machine</I>]
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<P>
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<I>Target picoJava options:</I>
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<BR> [<B>-mb</B>|<B>-me</B>]
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<P>
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<I>Target PowerPC options:</I>
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<BR> [<B>-a32</B>|<B>-a64</B>]
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<BR> [<B>-mpwrx</B>|<B>-mpwr2</B>|<B>-mpwr</B>|<B>-m601</B>|<B>-mppc</B>|<B>-mppc32</B>|<B>-m603</B>|<B>-m604</B>|<B>-m403</B>|<B>-m405</B>|
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<BR> <B>-m440</B>|<B>-m464</B>|<B>-m476</B>|<B>-m7400</B>|<B>-m7410</B>|<B>-m7450</B>|<B>-m7455</B>|<B>-m750cl</B>|<B>-mgekko</B>|
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<BR> <B>-mbroadway</B>|<B>-mppc64</B>|<B>-m620</B>|<B>-me500</B>|<B>-e500x2</B>|<B>-me500mc</B>|<B>-me500mc64</B>|<B>-me5500</B>|
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<BR> <B>-me6500</B>|<B>-mppc64bridge</B>|<B>-mbooke</B>|<B>-mpower4</B>|<B>-mpwr4</B>|<B>-mpower5</B>|<B>-mpwr5</B>|<B>-mpwr5x</B>|
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<BR> <B>-mpower6</B>|<B>-mpwr6</B>|<B>-mpower7</B>|<B>-mpwr7</B>|<B>-mpower8</B>|<B>-mpwr8</B>|<B>-mpower9</B>|<B>-mpwr9</B><B>-ma2</B>|
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<BR> <B>-mcell</B>|<B>-mspe</B>|<B>-mspe2</B>|<B>-mtitan</B>|<B>-me300</B>|<B>-mcom</B>]
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<BR> [<B>-many</B>] [<B>-maltivec</B>|<B>-mvsx</B>|<B>-mhtm</B>|<B>-mvle</B>]
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<BR> [<B>-mregnames</B>|<B>-mno-regnames</B>]
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<BR> [<B>-mrelocatable</B>|<B>-mrelocatable-lib</B>|<B>-K </B><FONT SIZE="-1"><B>PIC</B></FONT><B></B>] [<B>-memb</B>]
|
|
<BR> [<B>-mlittle</B>|<B>-mlittle-endian</B>|<B>-le</B>|<B>-mbig</B>|<B>-mbig-endian</B>|<B>-be</B>]
|
|
<BR> [<B>-msolaris</B>|<B>-mno-solaris</B>]
|
|
<BR> [<B>-nops=</B><I>count</I>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>PRU</I></FONT><I> options:</I>
|
|
<BR> [<B>-link-relax</B>]
|
|
<BR> [<B>-mnolink-relax</B>]
|
|
<BR> [<B>-mno-warn-regname-label</B>]
|
|
<P>
|
|
|
|
<I>Target RISC-V options:</I>
|
|
<BR> [<B>-fpic</B>|<B>-fPIC</B>|<B>-fno-pic</B>]
|
|
<BR> [<B>-march</B>=<I></I><FONT SIZE="-1"><I>ISA</I></FONT><I></I>]
|
|
<BR> [<B>-mabi</B>=<I></I><FONT SIZE="-1"><I>ABI</I></FONT><I></I>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>RL78</I></FONT><I> options:</I>
|
|
<BR> [<B>-mg10</B>]
|
|
<BR> [<B>-m32bit-doubles</B>|<B>-m64bit-doubles</B>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>RX</I></FONT><I> options:</I>
|
|
<BR> [<B>-mlittle-endian</B>|<B>-mbig-endian</B>]
|
|
<BR> [<B>-m32bit-doubles</B>|<B>-m64bit-doubles</B>]
|
|
<BR> [<B>-muse-conventional-section-names</B>]
|
|
<BR> [<B>-msmall-data-limit</B>]
|
|
<BR> [<B>-mpid</B>]
|
|
<BR> [<B>-mrelax</B>]
|
|
<BR> [<B>-mint-register=</B><I>number</I>]
|
|
<BR> [<B>-mgcc-abi</B>|<B>-mrx-abi</B>]
|
|
<P>
|
|
|
|
<I>Target s390 options:</I>
|
|
<BR> [<B>-m31</B>|<B>-m64</B>] [<B>-mesa</B>|<B>-mzarch</B>] [<B>-march</B>=<I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I>]
|
|
<BR> [<B>-mregnames</B>|<B>-mno-regnames</B>]
|
|
<BR> [<B>-mwarn-areg-zero</B>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>SCORE</I></FONT><I> options:</I>
|
|
<BR> [<B>-EB</B>][<B>-EL</B>][<B>-FIXDD</B>][<B>-NWARN</B>]
|
|
<BR> [<B>-SCORE5</B>][<B>-SCORE5U</B>][<B>-SCORE7</B>][<B>-SCORE3</B>]
|
|
<BR> [<B>-march=score7</B>][<B>-march=score3</B>]
|
|
<BR> [<B>-USE_R1</B>][<B>-KPIC</B>][<B>-O0</B>][<B>-G</B> <I>num</I>][<B>-V</B>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>SPARC</I></FONT><I> options:</I>
|
|
<BR> [<B>-Av6</B>|<B>-Av7</B>|<B>-Av8</B>|<B>-Aleon</B>|<B>-Asparclet</B>|<B>-Asparclite</B>
|
|
<BR> <B>-Av8plus</B>|<B>-Av8plusa</B>|<B>-Av8plusb</B>|<B>-Av8plusc</B>|<B>-Av8plusd</B>
|
|
<BR> <B>-Av8plusv</B>|<B>-Av8plusm</B>|<B>-Av9</B>|<B>-Av9a</B>|<B>-Av9b</B>|<B>-Av9c</B>
|
|
<BR> <B>-Av9d</B>|<B>-Av9e</B>|<B>-Av9v</B>|<B>-Av9m</B>|<B>-Asparc</B>|<B>-Asparcvis</B>
|
|
<BR> <B>-Asparcvis2</B>|<B>-Asparcfmaf</B>|<B>-Asparcima</B>|<B>-Asparcvis3</B>
|
|
<BR> <B>-Asparcvisr</B>|<B>-Asparc5</B>]
|
|
<BR> [<B>-xarch=v8plus</B>|<B>-xarch=v8plusa</B>]|<B>-xarch=v8plusb</B>|<B>-xarch=v8plusc</B>
|
|
<BR> <B>-xarch=v8plusd</B>|<B>-xarch=v8plusv</B>|<B>-xarch=v8plusm</B>|<B>-xarch=v9</B>
|
|
<BR> <B>-xarch=v9a</B>|<B>-xarch=v9b</B>|<B>-xarch=v9c</B>|<B>-xarch=v9d</B>|<B>-xarch=v9e</B>
|
|
<BR> <B>-xarch=v9v</B>|<B>-xarch=v9m</B>|<B>-xarch=sparc</B>|<B>-xarch=sparcvis</B>
|
|
<BR> <B>-xarch=sparcvis2</B>|<B>-xarch=sparcfmaf</B>|<B>-xarch=sparcima</B>
|
|
<BR> <B>-xarch=sparcvis3</B>|<B>-xarch=sparcvisr</B>|<B>-xarch=sparc5</B>
|
|
<BR> <B>-bump</B>]
|
|
<BR> [<B>-32</B>|<B>-64</B>]
|
|
<BR> [<B>--enforce-aligned-data</B>][<B>--dcti-couples-detect</B>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>TIC54X</I></FONT><I> options:</I>
|
|
<BR> [<B>-mcpu=54[123589]</B>|<B>-mcpu=54[56]lp</B>] [<B>-mfar-mode</B>|<B>-mf</B>]
|
|
<BR> [<B>-merrors-to-file</B> <I><filename></I>|<B>-me</B> <I><filename></I>]
|
|
<P>
|
|
|
|
<I>Target </I><FONT SIZE="-1"><I>TIC6X</I></FONT><I> options:</I>
|
|
<BR> [<B>-march=</B><I>arch</I>] [<B>-mbig-endian</B>|<B>-mlittle-endian</B>]
|
|
<BR> [<B>-mdsbt</B>|<B>-mno-dsbt</B>] [<B>-mpid=no</B>|<B>-mpid=near</B>|<B>-mpid=far</B>]
|
|
<BR> [<B>-mpic</B>|<B>-mno-pic</B>]
|
|
<P>
|
|
|
|
<I>Target TILE-Gx options:</I>
|
|
<BR> [<B>-m32</B>|<B>-m64</B>][<B>-EB</B>][<B>-EL</B>]
|
|
<P>
|
|
|
|
<I>Target Visium options:</I>
|
|
<BR> [<B>-mtune=</B><I>arch</I>]
|
|
<P>
|
|
|
|
<I>Target Xtensa options:</I>
|
|
<BR> [<B>--[no-]text-section-literals</B>] [<B>--[no-]auto-litpools</B>]
|
|
<BR> [<B>--[no-]absolute-literals</B>]
|
|
<BR> [<B>--[no-]target-align</B>] [<B>--[no-]longcalls</B>]
|
|
<BR> [<B>--[no-]transform</B>]
|
|
<BR> [<B>--rename-section</B> <I>oldname</I>=<I>newname</I>]
|
|
<BR> [<B>--[no-]trampolines</B>]
|
|
<P>
|
|
|
|
<I>Target Z80 options:</I>
|
|
<BR> [<B>-z80</B>]|[<B>-z180</B>]|[<B>-r800</B>]|[<B>-ez80</B>]|[<B>-ez80-adl</B>]
|
|
<BR> [<B>-local-prefix=</B><I></I><FONT SIZE="-1"><I>PREFIX</I></FONT><I></I>]
|
|
<BR> [<B>-colonless</B>]
|
|
<BR> [<B>-sdcc</B>]
|
|
<BR> [<B>-fp-s=</B><I></I><FONT SIZE="-1"><I>FORMAT</I></FONT><I></I>]
|
|
<BR> [<B>-fp-d=</B><I></I><FONT SIZE="-1"><I>FORMAT</I></FONT><I></I>]
|
|
<BR> [<B>-strict</B>]|[<B>-full</B>]
|
|
<BR> [<B>-with-inst=</B><I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B>] [<B>-Wnins</B> <I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B>]
|
|
<BR> [<B>-without-inst=</B><I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B>] [<B>-Fins</B> <I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B>]
|
|
<BR> [ <B>-ignore-undocumented-instructions</B>] [<B>-Wnud</B>]
|
|
<BR> [ <B>-ignore-unportable-instructions</B>] [<B>-Wnup</B>]
|
|
<BR> [ <B>-warn-undocumented-instructions</B>] [<B>-Wud</B>]
|
|
<BR> [ <B>-warn-unportable-instructions</B>] [<B>-Wup</B>]
|
|
<BR> [ <B>-forbid-undocumented-instructions</B>] [<B>-Fud</B>]
|
|
<BR> [ <B>-forbid-unportable-instructions</B>] [<B>-Fup</B>]
|
|
<A NAME="lbAE"> </A>
|
|
<H2>DESCRIPTION</H2>
|
|
|
|
|
|
|
|
<FONT SIZE="-1">GNU</FONT> <B>as</B> is really a family of assemblers.
|
|
If you use (or have used) the <FONT SIZE="-1">GNU</FONT> assembler on one architecture, you
|
|
should find a fairly similar environment when you use it on another
|
|
architecture. Each version has much in common with the others,
|
|
including object file formats, most assembler directives (often called
|
|
<I>pseudo-ops</I>) and assembler syntax.
|
|
<P>
|
|
|
|
<B>as</B> is primarily intended to assemble the output of the
|
|
<FONT SIZE="-1">GNU C</FONT> compiler <TT>"gcc"</TT> for use by the linker
|
|
<TT>"ld"</TT>. Nevertheless, we've tried to make <B>as</B>
|
|
assemble correctly everything that other assemblers for the same
|
|
machine would assemble.
|
|
Any exceptions are documented explicitly.
|
|
This doesn't mean <B>as</B> always uses the same syntax as another
|
|
assembler for the same architecture; for example, we know of several
|
|
incompatible versions of 680x0 assembly language syntax.
|
|
<P>
|
|
|
|
Each time you run <B>as</B> it assembles exactly one source
|
|
program. The source program is made up of one or more files.
|
|
(The standard input is also a file.)
|
|
<P>
|
|
|
|
You give <B>as</B> a command line that has zero or more input file
|
|
names. The input files are read (from left file name to right). A
|
|
command-line argument (in any position) that has no special meaning
|
|
is taken to be an input file name.
|
|
<P>
|
|
|
|
If you give <B>as</B> no file names it attempts to read one input file
|
|
from the <B>as</B> standard input, which is normally your terminal. You
|
|
may have to type <B>ctl-D</B> to tell <B>as</B> there is no more program
|
|
to assemble.
|
|
<P>
|
|
|
|
Use <B>--</B> if you need to explicitly name the standard input file
|
|
in your command line.
|
|
<P>
|
|
|
|
If the source is empty, <B>as</B> produces a small, empty object
|
|
file.
|
|
<P>
|
|
|
|
<B>as</B> may write warnings and error messages to the standard error
|
|
file (usually your terminal). This should not happen when a compiler
|
|
runs <B>as</B> automatically. Warnings report an assumption made so
|
|
that <B>as</B> could keep assembling a flawed program; errors report a
|
|
grave problem that stops the assembly.
|
|
<P>
|
|
|
|
If you are invoking <B>as</B> via the <FONT SIZE="-1">GNU C</FONT> compiler,
|
|
you can use the <B>-Wa</B> option to pass arguments through to the assembler.
|
|
The assembler arguments must be separated from each other (and the <B>-Wa</B>)
|
|
by commas. For example:
|
|
<P>
|
|
|
|
|
|
|
|
<PRE>
|
|
gcc -c -g -O -Wa,-alh,-L file.c
|
|
|
|
</PRE>
|
|
|
|
|
|
<P>
|
|
|
|
This passes two options to the assembler: <B>-alh</B> (emit a listing to
|
|
standard output with high-level and assembly source) and <B>-L</B> (retain
|
|
local symbols in the symbol table).
|
|
<P>
|
|
|
|
Usually you do not need to use this <B>-Wa</B> mechanism, since many compiler
|
|
command-line options are automatically passed to the assembler by the compiler.
|
|
(You can call the <FONT SIZE="-1">GNU</FONT> compiler driver with the <B>-v</B> option to see
|
|
precisely what options it passes to each compilation pass, including the
|
|
assembler.)
|
|
<A NAME="lbAF"> </A>
|
|
<H2>OPTIONS</H2>
|
|
|
|
|
|
|
|
<DL COMPACT>
|
|
<DT id="1"><B>@</B><I>file</I><DD>
|
|
|
|
|
|
Read command-line options from <I>file</I>. The options read are
|
|
inserted in place of the original @<I>file</I> option. If <I>file</I>
|
|
does not exist, or cannot be read, then the option will be treated
|
|
literally, and not removed.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
Options in <I>file</I> are separated by whitespace. A whitespace
|
|
character may be included in an option by surrounding the entire
|
|
option in either single or double quotes. Any character (including a
|
|
backslash) may be included by prefixing the character to be included
|
|
with a backslash. The <I>file</I> may itself contain additional
|
|
@<I>file</I> options; any such options will be processed recursively.
|
|
<DT id="2"><B>-a[cdghlmns]</B><DD>
|
|
|
|
|
|
Turn on listings, in any of a variety of ways:
|
|
<DL COMPACT><DT id="3"><DD>
|
|
<DL COMPACT>
|
|
<DT id="4"><B>-ac</B><DD>
|
|
|
|
|
|
omit false conditionals
|
|
<DT id="5"><B>-ad</B><DD>
|
|
|
|
|
|
omit debugging directives
|
|
<DT id="6"><B>-ag</B><DD>
|
|
|
|
|
|
include general information, like as version and options passed
|
|
<DT id="7"><B>-ah</B><DD>
|
|
|
|
|
|
include high-level source
|
|
<DT id="8"><B>-al</B><DD>
|
|
|
|
|
|
include assembly
|
|
<DT id="9"><B>-am</B><DD>
|
|
|
|
|
|
include macro expansions
|
|
<DT id="10"><B>-an</B><DD>
|
|
|
|
|
|
omit forms processing
|
|
<DT id="11"><B>-as</B><DD>
|
|
|
|
|
|
include symbols
|
|
<DT id="12"><B>=file</B><DD>
|
|
|
|
|
|
set the name of the listing file
|
|
</DL>
|
|
</DL>
|
|
|
|
<DL COMPACT><DT id="13"><DD>
|
|
|
|
|
|
<P>
|
|
|
|
|
|
You may combine these options; for example, use <B>-aln</B> for assembly
|
|
listing without forms processing. The <B>=file</B> option, if used, must be
|
|
the last one. By itself, <B>-a</B> defaults to <B>-ahls</B>.
|
|
</DL>
|
|
|
|
<DT id="14"><B>--alternate</B><DD>
|
|
|
|
|
|
Begin in alternate macro mode.
|
|
<DT id="15"><B>--compress-debug-sections</B><DD>
|
|
|
|
|
|
Compress <FONT SIZE="-1">DWARF</FONT> debug sections using zlib with <FONT SIZE="-1">SHF_COMPRESSED</FONT> from the
|
|
<FONT SIZE="-1">ELF ABI.</FONT> The resulting object file may not be compatible with older
|
|
linkers and object file utilities. Note if compression would make a
|
|
given section <I>larger</I> then it is not compressed.
|
|
<DT id="16"><B>--compress-debug-sections=none</B><DD>
|
|
|
|
|
|
|
|
<DT id="17"><B>--compress-debug-sections=zlib</B><DD>
|
|
|
|
|
|
<DT id="18"><B>--compress-debug-sections=zlib-gnu</B><DD>
|
|
|
|
|
|
<DT id="19"><B>--compress-debug-sections=zlib-gabi</B><DD>
|
|
|
|
|
|
|
|
These options control how <FONT SIZE="-1">DWARF</FONT> debug sections are compressed.
|
|
<B>--compress-debug-sections=none</B> is equivalent to
|
|
<B>--nocompress-debug-sections</B>.
|
|
<B>--compress-debug-sections=zlib</B> and
|
|
<B>--compress-debug-sections=zlib-gabi</B> are equivalent to
|
|
<B>--compress-debug-sections</B>.
|
|
<B>--compress-debug-sections=zlib-gnu</B> compresses <FONT SIZE="-1">DWARF</FONT> debug
|
|
sections using zlib. The debug sections are renamed to begin with
|
|
<B>.zdebug</B>. Note if compression would make a given section
|
|
<I>larger</I> then it is not compressed nor renamed.
|
|
<DT id="20"><B>--nocompress-debug-sections</B><DD>
|
|
|
|
|
|
Do not compress <FONT SIZE="-1">DWARF</FONT> debug sections. This is usually the default for all
|
|
targets except the x86/x86_64, but a configure time option can be used to
|
|
override this.
|
|
<DT id="21"><B>-D</B><DD>
|
|
|
|
|
|
Ignored. This option is accepted for script compatibility with calls to
|
|
other assemblers.
|
|
<DT id="22"><B>--debug-prefix-map</B> <I>old</I><B>=</B><I>new</I><DD>
|
|
|
|
|
|
When assembling files in directory <I>old</I>, record debugging
|
|
information describing them as in <I>new</I> instead.
|
|
<DT id="23"><B>--defsym</B> <I>sym</I><B>=</B><I>value</I><DD>
|
|
|
|
|
|
Define the symbol <I>sym</I> to be <I>value</I> before assembling the input file.
|
|
<I>value</I> must be an integer constant. As in C, a leading <B>0x</B>
|
|
indicates a hexadecimal value, and a leading <B>0</B> indicates an octal
|
|
value. The value of the symbol can be overridden inside a source file via the
|
|
use of a <TT>".set"</TT> pseudo-op.
|
|
<DT id="24"><B>-f</B><DD>
|
|
|
|
|
|
``fast''---skip whitespace and comment preprocessing (assume source is
|
|
compiler output).
|
|
<DT id="25"><B>-g</B><DD>
|
|
|
|
|
|
|
|
<DT id="26"><B>--gen-debug</B><DD>
|
|
|
|
|
|
|
|
Generate debugging information for each assembler source line using whichever
|
|
debug format is preferred by the target. This currently means either <FONT SIZE="-1">STABS,
|
|
ECOFF</FONT> or <FONT SIZE="-1">DWARF2.</FONT>
|
|
<DT id="27"><B>--gstabs</B><DD>
|
|
|
|
|
|
Generate stabs debugging information for each assembler line. This
|
|
may help debugging assembler code, if the debugger can handle it.
|
|
<DT id="28"><B>--gstabs+</B><DD>
|
|
|
|
|
|
Generate stabs debugging information for each assembler line, with <FONT SIZE="-1">GNU</FONT>
|
|
extensions that probably only gdb can handle, and that could make other
|
|
debuggers crash or refuse to read your program. This
|
|
may help debugging assembler code. Currently the only <FONT SIZE="-1">GNU</FONT> extension is
|
|
the location of the current working directory at assembling time.
|
|
<DT id="29"><B>--gdwarf-2</B><DD>
|
|
|
|
|
|
Generate <FONT SIZE="-1">DWARF2</FONT> debugging information for each assembler line. This
|
|
may help debugging assembler code, if the debugger can handle it. Note---this
|
|
option is only supported by some targets, not all of them.
|
|
<DT id="30"><B>--gdwarf-sections</B><DD>
|
|
|
|
|
|
Instead of creating a .debug_line section, create a series of
|
|
.debug_line.<I>foo</I> sections where <I>foo</I> is the name of the
|
|
corresponding code section. For example a code section called <I>.text.func</I>
|
|
will have its dwarf line number information placed into a section called
|
|
<I>.debug_line.text.func</I>. If the code section is just called <I>.text</I>
|
|
then debug line section will still be called just <I>.debug_line</I> without any
|
|
suffix.
|
|
<DT id="31"><B>--gdwarf-cie-version=</B><I>version</I><DD>
|
|
|
|
|
|
Control which version of <FONT SIZE="-1">DWARF</FONT> Common Information Entries (CIEs) are produced.
|
|
When this flag is not specificed the default is version 1, though some targets
|
|
can modify this default. Other possible values for <I>version</I> are 3 or 4.
|
|
<DT id="32"><B>--size-check=error</B><DD>
|
|
|
|
|
|
|
|
<DT id="33"><B>--size-check=warning</B><DD>
|
|
|
|
|
|
|
|
Issue an error or warning for invalid <FONT SIZE="-1">ELF</FONT> .size directive.
|
|
<DT id="34"><B>--elf-stt-common=no</B><DD>
|
|
|
|
|
|
|
|
<DT id="35"><B>--elf-stt-common=yes</B><DD>
|
|
|
|
|
|
|
|
These options control whether the <FONT SIZE="-1">ELF</FONT> assembler should generate common
|
|
symbols with the <TT>"STT_COMMON"</TT> type. The default can be controlled
|
|
by a configure option <B>--enable-elf-stt-common</B>.
|
|
<DT id="36"><B>--generate-missing-build-notes=yes</B><DD>
|
|
|
|
|
|
|
|
<DT id="37"><B>--generate-missing-build-notes=no</B><DD>
|
|
|
|
|
|
|
|
These options control whether the <FONT SIZE="-1">ELF</FONT> assembler should generate <FONT SIZE="-1">GNU</FONT> Build
|
|
attribute notes if none are present in the input sources.
|
|
The default can be controlled by the <B>--enable-generate-build-notes</B>
|
|
configure option.
|
|
<DT id="38"><B>--help</B><DD>
|
|
|
|
|
|
Print a summary of the command-line options and exit.
|
|
<DT id="39"><B>--target-help</B><DD>
|
|
|
|
|
|
Print a summary of all target specific options and exit.
|
|
<DT id="40"><B>-I</B> <I>dir</I><DD>
|
|
|
|
|
|
Add directory <I>dir</I> to the search list for <TT>".include"</TT> directives.
|
|
<DT id="41"><B>-J</B><DD>
|
|
|
|
|
|
Don't warn about signed overflow.
|
|
<DT id="42"><B>-K</B><DD>
|
|
|
|
|
|
Issue warnings when difference tables altered for long displacements.
|
|
<DT id="43"><B>-L</B><DD>
|
|
|
|
|
|
|
|
<DT id="44"><B>--keep-locals</B><DD>
|
|
|
|
|
|
|
|
Keep (in the symbol table) local symbols. These symbols start with
|
|
system-specific local label prefixes, typically <B>.L</B> for <FONT SIZE="-1">ELF</FONT> systems
|
|
or <B>L</B> for traditional a.out systems.
|
|
<DT id="45"><B>--listing-lhs-width=</B><I>number</I><DD>
|
|
|
|
|
|
Set the maximum width, in words, of the output data column for an assembler
|
|
listing to <I>number</I>.
|
|
<DT id="46"><B>--listing-lhs-width2=</B><I>number</I><DD>
|
|
|
|
|
|
Set the maximum width, in words, of the output data column for continuation
|
|
lines in an assembler listing to <I>number</I>.
|
|
<DT id="47"><B>--listing-rhs-width=</B><I>number</I><DD>
|
|
|
|
|
|
Set the maximum width of an input source line, as displayed in a listing, to
|
|
<I>number</I> bytes.
|
|
<DT id="48"><B>--listing-cont-lines=</B><I>number</I><DD>
|
|
|
|
|
|
Set the maximum number of lines printed in a listing for a single line of input
|
|
to <I>number</I> + 1.
|
|
<DT id="49"><B>--no-pad-sections</B><DD>
|
|
|
|
|
|
Stop the assembler for padding the ends of output sections to the alignment
|
|
of that section. The default is to pad the sections, but this can waste space
|
|
which might be needed on targets which have tight memory constraints.
|
|
<DT id="50"><B>-o</B> <I>objfile</I><DD>
|
|
|
|
|
|
Name the object-file output from <B>as</B> <I>objfile</I>.
|
|
<DT id="51"><B>-R</B><DD>
|
|
|
|
|
|
Fold the data section into the text section.
|
|
<DT id="52"><B>--hash-size=</B><I>number</I><DD>
|
|
|
|
|
|
Set the default size of <FONT SIZE="-1">GAS</FONT>'s hash tables to a prime number close to
|
|
<I>number</I>. Increasing this value can reduce the length of time it takes the
|
|
assembler to perform its tasks, at the expense of increasing the assembler's
|
|
memory requirements. Similarly reducing this value can reduce the memory
|
|
requirements at the expense of speed.
|
|
<DT id="53"><B>--reduce-memory-overheads</B><DD>
|
|
|
|
|
|
This option reduces <FONT SIZE="-1">GAS</FONT>'s memory requirements, at the expense of making the
|
|
assembly processes slower. Currently this switch is a synonym for
|
|
<B>--hash-size=4051</B>, but in the future it may have other effects as well.
|
|
<DT id="54"><B>--sectname-subst</B><DD>
|
|
|
|
|
|
Honor substitution sequences in section names.
|
|
<DT id="55"><B>--statistics</B><DD>
|
|
|
|
|
|
Print the maximum space (in bytes) and total time (in seconds) used by
|
|
assembly.
|
|
<DT id="56"><B>--strip-local-absolute</B><DD>
|
|
|
|
|
|
Remove local absolute symbols from the outgoing symbol table.
|
|
<DT id="57"><B>-v</B><DD>
|
|
|
|
|
|
|
|
<DT id="58"><B>-version</B><DD>
|
|
|
|
|
|
|
|
Print the <B>as</B> version.
|
|
<DT id="59"><B>--version</B><DD>
|
|
|
|
|
|
Print the <B>as</B> version and exit.
|
|
<DT id="60"><B>-W</B><DD>
|
|
|
|
|
|
|
|
<DT id="61"><B>--no-warn</B><DD>
|
|
|
|
|
|
|
|
Suppress warning messages.
|
|
<DT id="62"><B>--fatal-warnings</B><DD>
|
|
|
|
|
|
Treat warnings as errors.
|
|
<DT id="63"><B>--warn</B><DD>
|
|
|
|
|
|
Don't suppress warning messages or treat them as errors.
|
|
<DT id="64"><B>-w</B><DD>
|
|
|
|
|
|
Ignored.
|
|
<DT id="65"><B>-x</B><DD>
|
|
|
|
|
|
Ignored.
|
|
<DT id="66"><B>-Z</B><DD>
|
|
|
|
|
|
Generate an object file even after errors.
|
|
<DT id="67"><B>-- |</B> <I>files</I> <B>...</B><DD>
|
|
|
|
|
|
Standard input, or source files to assemble.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for the
|
|
64-bit mode of the <FONT SIZE="-1">ARM</FONT> Architecture (AArch64).
|
|
<DL COMPACT>
|
|
<DT id="68"><B>-EB</B><DD>
|
|
|
|
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as being encoded for a big-endian processor.
|
|
<DT id="69"><B>-EL</B><DD>
|
|
|
|
|
|
This option specifies that the output generated by the assembler should
|
|
be marked as being encoded for a little-endian processor.
|
|
<DT id="70"><B>-mabi=</B><I>abi</I><DD>
|
|
|
|
|
|
Specify which <FONT SIZE="-1">ABI</FONT> the source code uses. The recognized arguments
|
|
are: <TT>"ilp32"</TT> and <TT>"lp64"</TT>, which decides the generated object
|
|
file in <FONT SIZE="-1">ELF32</FONT> and <FONT SIZE="-1">ELF64</FONT> format respectively. The default is <TT>"lp64"</TT>.
|
|
<DT id="71"><B>-mcpu=</B><I>processor</I><B>[+</B><I>extension</I><B>...]</B><DD>
|
|
|
|
|
|
This option specifies the target processor. The assembler will issue an error
|
|
message if an attempt is made to assemble an instruction which will not execute
|
|
on the target processor. The following processor names are recognized:
|
|
<TT>"cortex-a34"</TT>,
|
|
<TT>"cortex-a35"</TT>,
|
|
<TT>"cortex-a53"</TT>,
|
|
<TT>"cortex-a55"</TT>,
|
|
<TT>"cortex-a57"</TT>,
|
|
<TT>"cortex-a65"</TT>,
|
|
<TT>"cortex-a65ae"</TT>,
|
|
<TT>"cortex-a72"</TT>,
|
|
<TT>"cortex-a73"</TT>,
|
|
<TT>"cortex-a75"</TT>,
|
|
<TT>"cortex-a76"</TT>,
|
|
<TT>"cortex-a76ae"</TT>,
|
|
<TT>"cortex-a77"</TT>,
|
|
<TT>"ares"</TT>,
|
|
<TT>"exynos-m1"</TT>,
|
|
<TT>"falkor"</TT>,
|
|
<TT>"neoverse-n1"</TT>,
|
|
<TT>"neoverse-e1"</TT>,
|
|
<TT>"qdf24xx"</TT>,
|
|
<TT>"saphira"</TT>,
|
|
<TT>"thunderx"</TT>,
|
|
<TT>"vulcan"</TT>,
|
|
<TT>"xgene1"</TT>
|
|
and
|
|
<TT>"xgene2"</TT>.
|
|
The special name <TT>"all"</TT> may be used to allow the assembler to accept
|
|
instructions valid for any supported processor, including all optional
|
|
extensions.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
In addition to the basic instruction set, the assembler can be told to
|
|
accept, or restrict, various extension mnemonics that extend the
|
|
processor.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
If some implementations of a particular processor can have an
|
|
extension, then then those extensions are automatically enabled.
|
|
Consequently, you will not normally have to specify any additional
|
|
extensions.
|
|
<DT id="72"><B>-march=</B><I>architecture</I><B>[+</B><I>extension</I><B>...]</B><DD>
|
|
|
|
|
|
This option specifies the target architecture. The assembler will
|
|
issue an error message if an attempt is made to assemble an
|
|
instruction which will not execute on the target architecture. The
|
|
following architecture names are recognized: <TT>"armv8-a"</TT>,
|
|
<TT>"armv8.1-a"</TT>, <TT>"armv8.2-a"</TT>, <TT>"armv8.3-a"</TT>, <TT>"armv8.4-a"</TT>
|
|
<TT>"armv8.5-a"</TT>, and <TT>"armv8.6-a"</TT>.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
If both <B>-mcpu</B> and <B>-march</B> are specified, the
|
|
assembler will use the setting for <B>-mcpu</B>. If neither are
|
|
specified, the assembler will default to <B>-mcpu=all</B>.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
The architecture option can be extended with the same instruction set
|
|
extension options as the <B>-mcpu</B> option. Unlike
|
|
<B>-mcpu</B>, extensions are not always enabled by default,
|
|
<DT id="73"><B>-mverbose-error</B><DD>
|
|
|
|
|
|
This option enables verbose error messages for AArch64 gas. This option
|
|
is enabled by default.
|
|
<DT id="74"><B>-mno-verbose-error</B><DD>
|
|
|
|
|
|
This option disables verbose error messages in AArch64 gas.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for an Alpha
|
|
processor.
|
|
<DL COMPACT>
|
|
<DT id="75"><B>-m</B><I>cpu</I><DD>
|
|
|
|
|
|
This option specifies the target processor. If an attempt is made to
|
|
assemble an instruction which will not execute on the target processor,
|
|
the assembler may either expand the instruction as a macro or issue an
|
|
error message. This option is equivalent to the <TT>".arch"</TT> directive.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
The following processor names are recognized:
|
|
<TT>21064</TT>,
|
|
<TT>"21064a"</TT>,
|
|
<TT>21066</TT>,
|
|
<TT>21068</TT>,
|
|
<TT>21164</TT>,
|
|
<TT>"21164a"</TT>,
|
|
<TT>"21164pc"</TT>,
|
|
<TT>21264</TT>,
|
|
<TT>"21264a"</TT>,
|
|
<TT>"21264b"</TT>,
|
|
<TT>"ev4"</TT>,
|
|
<TT>"ev5"</TT>,
|
|
<TT>"lca45"</TT>,
|
|
<TT>"ev5"</TT>,
|
|
<TT>"ev56"</TT>,
|
|
<TT>"pca56"</TT>,
|
|
<TT>"ev6"</TT>,
|
|
<TT>"ev67"</TT>,
|
|
<TT>"ev68"</TT>.
|
|
The special name <TT>"all"</TT> may be used to allow the assembler to accept
|
|
instructions valid for any Alpha processor.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
In order to support existing practice in <FONT SIZE="-1">OSF/1</FONT> with respect to <TT>".arch"</TT>,
|
|
and existing practice within <B></B><FONT SIZE="-1"><B>MILO</B></FONT><B></B> (the Linux <FONT SIZE="-1">ARC</FONT> bootloader), the
|
|
numbered processor names (e.g. 21064) enable the processor-specific PALcode
|
|
instructions, while the ``electro-vlasic'' names (e.g. <TT>"ev4"</TT>) do not.
|
|
<DT id="76"><B>-mdebug</B><DD>
|
|
|
|
|
|
|
|
<DT id="77"><B>-no-mdebug</B><DD>
|
|
|
|
|
|
|
|
Enables or disables the generation of <TT>".mdebug"</TT> encapsulation for
|
|
stabs directives and procedure descriptors. The default is to automatically
|
|
enable <TT>".mdebug"</TT> when the first stabs directive is seen.
|
|
<DT id="78"><B>-relax</B><DD>
|
|
|
|
|
|
This option forces all relocations to be put into the object file, instead
|
|
of saving space and resolving some relocations at assembly time. Note that
|
|
this option does not propagate all symbol arithmetic into the object file,
|
|
because not all symbol arithmetic can be represented. However, the option
|
|
can still be useful in specific applications.
|
|
<DT id="79"><B>-replace</B><DD>
|
|
|
|
|
|
|
|
<DT id="80"><B>-noreplace</B><DD>
|
|
|
|
|
|
|
|
Enables or disables the optimization of procedure calls, both at assemblage
|
|
and at link time. These options are only available for <FONT SIZE="-1">VMS</FONT> targets and
|
|
<TT>"-replace"</TT> is the default. See section 1.4.1 of the OpenVMS Linker
|
|
Utility Manual.
|
|
<DT id="81"><B>-g</B><DD>
|
|
|
|
|
|
This option is used when the compiler generates debug information. When
|
|
<B>gcc</B> is using <B>mips-tfile</B> to generate debug
|
|
information for <FONT SIZE="-1">ECOFF,</FONT> local labels must be passed through to the object
|
|
file. Otherwise this option has no effect.
|
|
<DT id="82"><B>-G</B><I>size</I><DD>
|
|
|
|
|
|
A local common symbol larger than <I>size</I> is placed in <TT>".bss"</TT>,
|
|
while smaller symbols are placed in <TT>".sbss"</TT>.
|
|
<DT id="83"><B>-F</B><DD>
|
|
|
|
|
|
|
|
<DT id="84"><B>-32addr</B><DD>
|
|
|
|
|
|
|
|
These options are ignored for backward compatibility.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for an <FONT SIZE="-1">ARC</FONT>
|
|
processor.
|
|
<DL COMPACT>
|
|
<DT id="85"><B>-mcpu=</B><I>cpu</I><DD>
|
|
|
|
|
|
This option selects the core processor variant.
|
|
<DT id="86"><B>-EB | -EL</B><DD>
|
|
|
|
|
|
Select either big-endian (-EB) or little-endian (-EL) output.
|
|
<DT id="87"><B>-mcode-density</B><DD>
|
|
|
|
|
|
Enable Code Density extenssion instructions.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for the <FONT SIZE="-1">ARM</FONT>
|
|
processor family.
|
|
<DL COMPACT>
|
|
<DT id="88"><B>-mcpu=</B><I>processor</I><B>[+</B><I>extension</I><B>...]</B><DD>
|
|
|
|
|
|
Specify which <FONT SIZE="-1">ARM</FONT> processor variant is the target.
|
|
<DT id="89"><B>-march=</B><I>architecture</I><B>[+</B><I>extension</I><B>...]</B><DD>
|
|
|
|
|
|
Specify which <FONT SIZE="-1">ARM</FONT> architecture variant is used by the target.
|
|
<DT id="90"><B>-mfpu=</B><I>floating-point-format</I><DD>
|
|
|
|
|
|
Select which Floating Point architecture is the target.
|
|
<DT id="91"><B>-mfloat-abi=</B><I>abi</I><DD>
|
|
|
|
|
|
Select which floating point <FONT SIZE="-1">ABI</FONT> is in use.
|
|
<DT id="92"><B>-mthumb</B><DD>
|
|
|
|
|
|
Enable Thumb only instruction decoding.
|
|
<DT id="93"><B>-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant</B><DD>
|
|
|
|
|
|
Select which procedure calling convention is in use.
|
|
<DT id="94"><B>-EB | -EL</B><DD>
|
|
|
|
|
|
Select either big-endian (-EB) or little-endian (-EL) output.
|
|
<DT id="95"><B>-mthumb-interwork</B><DD>
|
|
|
|
|
|
Specify that the code has been generated with interworking between Thumb and
|
|
<FONT SIZE="-1">ARM</FONT> code in mind.
|
|
<DT id="96"><B>-mccs</B><DD>
|
|
|
|
|
|
Turns on CodeComposer Studio assembly syntax compatibility mode.
|
|
<DT id="97"><B>-k</B><DD>
|
|
|
|
|
|
Specify that <FONT SIZE="-1">PIC</FONT> code has been generated.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for
|
|
the Blackfin processor family.
|
|
<DL COMPACT>
|
|
<DT id="98"><B>-mcpu=</B><I>processor</I>[<B>-</B><I>sirevision</I>]<DD>
|
|
|
|
|
|
This option specifies the target processor. The optional <I>sirevision</I>
|
|
is not used in assembler. It's here such that <FONT SIZE="-1">GCC</FONT> can easily pass down its
|
|
<TT>"-mcpu="</TT> option. The assembler will issue an
|
|
error message if an attempt is made to assemble an instruction which
|
|
will not execute on the target processor. The following processor names are
|
|
recognized:
|
|
<TT>"bf504"</TT>,
|
|
<TT>"bf506"</TT>,
|
|
<TT>"bf512"</TT>,
|
|
<TT>"bf514"</TT>,
|
|
<TT>"bf516"</TT>,
|
|
<TT>"bf518"</TT>,
|
|
<TT>"bf522"</TT>,
|
|
<TT>"bf523"</TT>,
|
|
<TT>"bf524"</TT>,
|
|
<TT>"bf525"</TT>,
|
|
<TT>"bf526"</TT>,
|
|
<TT>"bf527"</TT>,
|
|
<TT>"bf531"</TT>,
|
|
<TT>"bf532"</TT>,
|
|
<TT>"bf533"</TT>,
|
|
<TT>"bf534"</TT>,
|
|
<TT>"bf535"</TT> (not implemented yet),
|
|
<TT>"bf536"</TT>,
|
|
<TT>"bf537"</TT>,
|
|
<TT>"bf538"</TT>,
|
|
<TT>"bf539"</TT>,
|
|
<TT>"bf542"</TT>,
|
|
<TT>"bf542m"</TT>,
|
|
<TT>"bf544"</TT>,
|
|
<TT>"bf544m"</TT>,
|
|
<TT>"bf547"</TT>,
|
|
<TT>"bf547m"</TT>,
|
|
<TT>"bf548"</TT>,
|
|
<TT>"bf548m"</TT>,
|
|
<TT>"bf549"</TT>,
|
|
<TT>"bf549m"</TT>,
|
|
<TT>"bf561"</TT>,
|
|
and
|
|
<TT>"bf592"</TT>.
|
|
<DT id="99"><B>-mfdpic</B><DD>
|
|
|
|
|
|
Assemble for the <FONT SIZE="-1">FDPIC ABI.</FONT>
|
|
<DT id="100"><B>-mno-fdpic</B><DD>
|
|
|
|
|
|
|
|
<DT id="101"><B>-mnopic</B><DD>
|
|
|
|
|
|
|
|
Disable -mfdpic.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for
|
|
the Linux kernel <FONT SIZE="-1">BPF</FONT> processor family.
|
|
<P>
|
|
|
|
<TT>@chapter</TT> <FONT SIZE="-1">BPF</FONT> Dependent Features
|
|
<A NAME="lbAG"> </A>
|
|
<H3>Options</H3>
|
|
|
|
|
|
|
|
<DL COMPACT>
|
|
<DT id="102"><B>-EB</B><DD>
|
|
|
|
|
|
This option specifies that the assembler should emit big-endian eBPF.
|
|
<DT id="103"><B>-EL</B><DD>
|
|
|
|
|
|
This option specifies that the assembler should emit little-endian
|
|
eBPF.
|
|
</DL>
|
|
<P>
|
|
|
|
Note that if no endianness option is specified in the command line,
|
|
the host endianness is used.
|
|
See the info pages for documentation of the CRIS-specific options.
|
|
<P>
|
|
|
|
The following options are available when as is configured for
|
|
the C-SKY processor family.
|
|
<DL COMPACT>
|
|
<DT id="104"><B>-march=</B><I>archname</I><DD>
|
|
|
|
|
|
Assemble for architecture <I>archname</I>. The <B>--help</B> option
|
|
lists valid values for <I>archname</I>.
|
|
<DT id="105"><B>-mcpu=</B><I>cpuname</I><DD>
|
|
|
|
|
|
Assemble for architecture <I>cpuname</I>. The <B>--help</B> option
|
|
lists valid values for <I>cpuname</I>.
|
|
<DT id="106"><B>-EL</B><DD>
|
|
|
|
|
|
|
|
<DT id="107"><B>-mlittle-endian</B><DD>
|
|
|
|
|
|
|
|
Generate little-endian output.
|
|
<DT id="108"><B>-EB</B><DD>
|
|
|
|
|
|
|
|
<DT id="109"><B>-mbig-endian</B><DD>
|
|
|
|
|
|
|
|
Generate big-endian output.
|
|
<DT id="110"><B>-fpic</B><DD>
|
|
|
|
|
|
|
|
<DT id="111"><B>-pic</B><DD>
|
|
|
|
|
|
|
|
Generate position-independent code.
|
|
<DT id="112"><B>-mljump</B><DD>
|
|
|
|
|
|
|
|
<DT id="113"><B>-mno-ljump</B><DD>
|
|
|
|
|
|
|
|
Enable/disable transformation of the short branch instructions
|
|
<TT>"jbf"</TT>, <TT>"jbt"</TT>, and <TT>"jbr"</TT> to <TT>"jmpi"</TT>.
|
|
This option is for V2 processors only.
|
|
It is ignored on <FONT SIZE="-1">CK801</FONT> and <FONT SIZE="-1">CK802</FONT> targets, which do not support the <TT>"jmpi"</TT>
|
|
instruction, and is enabled by default for other processors.
|
|
<DT id="114"><B>-mbranch-stub</B><DD>
|
|
|
|
|
|
|
|
<DT id="115"><B>-mno-branch-stub</B><DD>
|
|
|
|
|
|
|
|
Pass through <TT>"R_CKCORE_PCREL_IMM26BY2"</TT> relocations for <TT>"bsr"</TT>
|
|
instructions to the linker.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
This option is only available for bare-metal C-SKY V2 <FONT SIZE="-1">ELF</FONT> targets,
|
|
where it is enabled by default. It cannot be used in code that will be
|
|
dynamically linked against shared libraries.
|
|
<DT id="116"><B>-force2bsr</B><DD>
|
|
|
|
|
|
|
|
<DT id="117"><B>-mforce2bsr</B><DD>
|
|
|
|
|
|
<DT id="118"><B>-no-force2bsr</B><DD>
|
|
|
|
|
|
<DT id="119"><B>-mno-force2bsr</B><DD>
|
|
|
|
|
|
|
|
Enable/disable transformation of <TT>"jbsr"</TT> instructions to <TT>"bsr"</TT>.
|
|
This option is always enabled (and <B>-mno-force2bsr</B> is ignored)
|
|
for <FONT SIZE="-1">CK801/CK802</FONT> targets. It is also always enabled when
|
|
<B>-mbranch-stub</B> is in effect.
|
|
<DT id="120"><B>-jsri2bsr</B><DD>
|
|
|
|
|
|
|
|
<DT id="121"><B>-mjsri2bsr</B><DD>
|
|
|
|
|
|
<DT id="122"><B>-no-jsri2bsr</B><DD>
|
|
|
|
|
|
<DT id="123"><B>-mno-jsri2bsr</B><DD>
|
|
|
|
|
|
|
|
Enable/disable transformation of <TT>"jsri"</TT> instructions to <TT>"bsr"</TT>.
|
|
This option is enabled by default.
|
|
<DT id="124"><B>-mnolrw</B><DD>
|
|
|
|
|
|
|
|
<DT id="125"><B>-mno-lrw</B><DD>
|
|
|
|
|
|
|
|
Enable/disable transformation of <TT>"lrw"</TT> instructions into a
|
|
<TT>"movih"</TT>/<TT>"ori"</TT> pair.
|
|
<DT id="126"><B>-melrw</B><DD>
|
|
|
|
|
|
|
|
<DT id="127"><B>-mno-elrw</B><DD>
|
|
|
|
|
|
|
|
Enable/disable extended <TT>"lrw"</TT> instructions.
|
|
This option is enabled by default for CK800-series processors.
|
|
<DT id="128"><B>-mlaf</B><DD>
|
|
|
|
|
|
|
|
<DT id="129"><B>-mliterals-after-func</B><DD>
|
|
|
|
|
|
<DT id="130"><B>-mno-laf</B><DD>
|
|
|
|
|
|
<DT id="131"><B>-mno-literals-after-func</B><DD>
|
|
|
|
|
|
|
|
Enable/disable placement of literal pools after each function.
|
|
<DT id="132"><B>-mlabr</B><DD>
|
|
|
|
|
|
|
|
<DT id="133"><B>-mliterals-after-br</B><DD>
|
|
|
|
|
|
<DT id="134"><B>-mno-labr</B><DD>
|
|
|
|
|
|
<DT id="135"><B>-mnoliterals-after-br</B><DD>
|
|
|
|
|
|
|
|
Enable/disable placement of literal pools after unconditional branches.
|
|
This option is enabled by default.
|
|
<DT id="136"><B>-mistack</B><DD>
|
|
|
|
|
|
|
|
<DT id="137"><B>-mno-istack</B><DD>
|
|
|
|
|
|
|
|
Enable/disable interrupt stack instructions. This option is enabled by
|
|
default on <FONT SIZE="-1">CK801, CK802,</FONT> and <FONT SIZE="-1">CK802</FONT> processors.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options explicitly enable certain optional instructions.
|
|
These features are also enabled implicitly by using <TT>"-mcpu="</TT> to specify
|
|
a processor that supports it.
|
|
<DL COMPACT>
|
|
<DT id="138"><B>-mhard-float</B><DD>
|
|
|
|
|
|
Enable hard float instructions.
|
|
<DT id="139"><B>-mmp</B><DD>
|
|
|
|
|
|
Enable multiprocessor instructions.
|
|
<DT id="140"><B>-mcp</B><DD>
|
|
|
|
|
|
Enable coprocessor instructions.
|
|
<DT id="141"><B>-mcache</B><DD>
|
|
|
|
|
|
Enable cache prefetch instruction.
|
|
<DT id="142"><B>-msecurity</B><DD>
|
|
|
|
|
|
Enable C-SKY security instructions.
|
|
<DT id="143"><B>-mtrust</B><DD>
|
|
|
|
|
|
Enable C-SKY trust instructions.
|
|
<DT id="144"><B>-mdsp</B><DD>
|
|
|
|
|
|
Enable <FONT SIZE="-1">DSP</FONT> instructions.
|
|
<DT id="145"><B>-medsp</B><DD>
|
|
|
|
|
|
Enable enhanced <FONT SIZE="-1">DSP</FONT> instructions.
|
|
<DT id="146"><B>-mvdsp</B><DD>
|
|
|
|
|
|
Enable vector <FONT SIZE="-1">DSP</FONT> instructions.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for
|
|
an Epiphany processor.
|
|
<DL COMPACT>
|
|
<DT id="147"><B>-mepiphany</B><DD>
|
|
|
|
|
|
Specifies that the both 32 and 16 bit instructions are allowed. This is the
|
|
default behavior.
|
|
<DT id="148"><B>-mepiphany16</B><DD>
|
|
|
|
|
|
Restricts the permitted instructions to just the 16 bit set.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for an H8/300
|
|
processor.
|
|
<TT>@chapter</TT> H8/300 Dependent Features
|
|
<A NAME="lbAH"> </A>
|
|
<H3>Options</H3>
|
|
|
|
|
|
|
|
The Renesas H8/300 version of <TT>"as"</TT> has one
|
|
machine-dependent option:
|
|
<DL COMPACT>
|
|
<DT id="149"><B>-h-tick-hex</B><DD>
|
|
|
|
|
|
Support H'00 style hex constants in addition to 0x00 style.
|
|
<DT id="150"><B>-mach=</B><I>name</I><DD>
|
|
|
|
|
|
Sets the H8300 machine variant. The following machine names
|
|
are recognised:
|
|
<TT>"h8300h"</TT>,
|
|
<TT>"h8300hn"</TT>,
|
|
<TT>"h8300s"</TT>,
|
|
<TT>"h8300sn"</TT>,
|
|
<TT>"h8300sx"</TT> and
|
|
<TT>"h8300sxn"</TT>.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for
|
|
an i386 processor.
|
|
<DL COMPACT>
|
|
<DT id="151"><B>--32 | --x32 | --64</B><DD>
|
|
|
|
|
|
Select the word size, either 32 bits or 64 bits. <B>--32</B>
|
|
implies Intel i386 architecture, while <B>--x32</B> and <B>--64</B>
|
|
imply <FONT SIZE="-1">AMD</FONT> x86-64 architecture with 32-bit or 64-bit word-size
|
|
respectively.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
These options are only available with the <FONT SIZE="-1">ELF</FONT> object file format, and
|
|
require that the necessary <FONT SIZE="-1">BFD</FONT> support has been included (on a 32-bit
|
|
platform you have to add --enable-64-bit-bfd to configure enable 64-bit
|
|
usage and use x86-64 as target platform).
|
|
<DT id="152"><B>-n</B><DD>
|
|
|
|
|
|
By default, x86 <FONT SIZE="-1">GAS</FONT> replaces multiple nop instructions used for
|
|
alignment within code sections with multi-byte nop instructions such
|
|
as leal 0(%esi,1),%esi. This switch disables the optimization if a single
|
|
byte nop (0x90) is explicitly specified as the fill byte for alignment.
|
|
<DT id="153"><B>--divide</B><DD>
|
|
|
|
|
|
On SVR4-derived platforms, the character <B>/</B> is treated as a comment
|
|
character, which means that it cannot be used in expressions. The
|
|
<B>--divide</B> option turns <B>/</B> into a normal character. This does
|
|
not disable <B>/</B> at the beginning of a line starting a comment, or
|
|
affect using <B>#</B> for starting a comment.
|
|
<DT id="154"><B>-march=</B><I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I><B>[+</B><I></I><FONT SIZE="-1"><I>EXTENSION</I></FONT><I></I><B>...]</B><DD>
|
|
|
|
|
|
This option specifies the target processor. The assembler will
|
|
issue an error message if an attempt is made to assemble an instruction
|
|
which will not execute on the target processor. The following
|
|
processor names are recognized:
|
|
<TT>"i8086"</TT>,
|
|
<TT>"i186"</TT>,
|
|
<TT>"i286"</TT>,
|
|
<TT>"i386"</TT>,
|
|
<TT>"i486"</TT>,
|
|
<TT>"i586"</TT>,
|
|
<TT>"i686"</TT>,
|
|
<TT>"pentium"</TT>,
|
|
<TT>"pentiumpro"</TT>,
|
|
<TT>"pentiumii"</TT>,
|
|
<TT>"pentiumiii"</TT>,
|
|
<TT>"pentium4"</TT>,
|
|
<TT>"prescott"</TT>,
|
|
<TT>"nocona"</TT>,
|
|
<TT>"core"</TT>,
|
|
<TT>"core2"</TT>,
|
|
<TT>"corei7"</TT>,
|
|
<TT>"l1om"</TT>,
|
|
<TT>"k1om"</TT>,
|
|
<TT>"iamcu"</TT>,
|
|
<TT>"k6"</TT>,
|
|
<TT>"k6_2"</TT>,
|
|
<TT>"athlon"</TT>,
|
|
<TT>"opteron"</TT>,
|
|
<TT>"k8"</TT>,
|
|
<TT>"amdfam10"</TT>,
|
|
<TT>"bdver1"</TT>,
|
|
<TT>"bdver2"</TT>,
|
|
<TT>"bdver3"</TT>,
|
|
<TT>"bdver4"</TT>,
|
|
<TT>"znver1"</TT>,
|
|
<TT>"znver2"</TT>,
|
|
<TT>"btver1"</TT>,
|
|
<TT>"btver2"</TT>,
|
|
<TT>"generic32"</TT> and
|
|
<TT>"generic64"</TT>.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
In addition to the basic instruction set, the assembler can be told to
|
|
accept various extension mnemonics. For example,
|
|
<TT>"-march=i686+sse4+vmx"</TT> extends <I>i686</I> with <I>sse4</I> and
|
|
<I>vmx</I>. The following extensions are currently supported:
|
|
<TT>8087</TT>,
|
|
<TT>287</TT>,
|
|
<TT>387</TT>,
|
|
<TT>687</TT>,
|
|
<TT>"no87"</TT>,
|
|
<TT>"no287"</TT>,
|
|
<TT>"no387"</TT>,
|
|
<TT>"no687"</TT>,
|
|
<TT>"cmov"</TT>,
|
|
<TT>"nocmov"</TT>,
|
|
<TT>"fxsr"</TT>,
|
|
<TT>"nofxsr"</TT>,
|
|
<TT>"mmx"</TT>,
|
|
<TT>"nommx"</TT>,
|
|
<TT>"sse"</TT>,
|
|
<TT>"sse2"</TT>,
|
|
<TT>"sse3"</TT>,
|
|
<TT>"ssse3"</TT>,
|
|
<TT>"sse4.1"</TT>,
|
|
<TT>"sse4.2"</TT>,
|
|
<TT>"sse4"</TT>,
|
|
<TT>"nosse"</TT>,
|
|
<TT>"nosse2"</TT>,
|
|
<TT>"nosse3"</TT>,
|
|
<TT>"nossse3"</TT>,
|
|
<TT>"nosse4.1"</TT>,
|
|
<TT>"nosse4.2"</TT>,
|
|
<TT>"nosse4"</TT>,
|
|
<TT>"avx"</TT>,
|
|
<TT>"avx2"</TT>,
|
|
<TT>"noavx"</TT>,
|
|
<TT>"noavx2"</TT>,
|
|
<TT>"adx"</TT>,
|
|
<TT>"rdseed"</TT>,
|
|
<TT>"prfchw"</TT>,
|
|
<TT>"smap"</TT>,
|
|
<TT>"mpx"</TT>,
|
|
<TT>"sha"</TT>,
|
|
<TT>"rdpid"</TT>,
|
|
<TT>"ptwrite"</TT>,
|
|
<TT>"cet"</TT>,
|
|
<TT>"gfni"</TT>,
|
|
<TT>"vaes"</TT>,
|
|
<TT>"vpclmulqdq"</TT>,
|
|
<TT>"prefetchwt1"</TT>,
|
|
<TT>"clflushopt"</TT>,
|
|
<TT>"se1"</TT>,
|
|
<TT>"clwb"</TT>,
|
|
<TT>"movdiri"</TT>,
|
|
<TT>"movdir64b"</TT>,
|
|
<TT>"enqcmd"</TT>,
|
|
<TT>"avx512f"</TT>,
|
|
<TT>"avx512cd"</TT>,
|
|
<TT>"avx512er"</TT>,
|
|
<TT>"avx512pf"</TT>,
|
|
<TT>"avx512vl"</TT>,
|
|
<TT>"avx512bw"</TT>,
|
|
<TT>"avx512dq"</TT>,
|
|
<TT>"avx512ifma"</TT>,
|
|
<TT>"avx512vbmi"</TT>,
|
|
<TT>"avx512_4fmaps"</TT>,
|
|
<TT>"avx512_4vnniw"</TT>,
|
|
<TT>"avx512_vpopcntdq"</TT>,
|
|
<TT>"avx512_vbmi2"</TT>,
|
|
<TT>"avx512_vnni"</TT>,
|
|
<TT>"avx512_bitalg"</TT>,
|
|
<TT>"avx512_bf16"</TT>,
|
|
<TT>"noavx512f"</TT>,
|
|
<TT>"noavx512cd"</TT>,
|
|
<TT>"noavx512er"</TT>,
|
|
<TT>"noavx512pf"</TT>,
|
|
<TT>"noavx512vl"</TT>,
|
|
<TT>"noavx512bw"</TT>,
|
|
<TT>"noavx512dq"</TT>,
|
|
<TT>"noavx512ifma"</TT>,
|
|
<TT>"noavx512vbmi"</TT>,
|
|
<TT>"noavx512_4fmaps"</TT>,
|
|
<TT>"noavx512_4vnniw"</TT>,
|
|
<TT>"noavx512_vpopcntdq"</TT>,
|
|
<TT>"noavx512_vbmi2"</TT>,
|
|
<TT>"noavx512_vnni"</TT>,
|
|
<TT>"noavx512_bitalg"</TT>,
|
|
<TT>"noavx512_vp2intersect"</TT>,
|
|
<TT>"noavx512_bf16"</TT>,
|
|
<TT>"noenqcmd"</TT>,
|
|
<TT>"vmx"</TT>,
|
|
<TT>"vmfunc"</TT>,
|
|
<TT>"smx"</TT>,
|
|
<TT>"xsave"</TT>,
|
|
<TT>"xsaveopt"</TT>,
|
|
<TT>"xsavec"</TT>,
|
|
<TT>"xsaves"</TT>,
|
|
<TT>"aes"</TT>,
|
|
<TT>"pclmul"</TT>,
|
|
<TT>"fsgsbase"</TT>,
|
|
<TT>"rdrnd"</TT>,
|
|
<TT>"f16c"</TT>,
|
|
<TT>"bmi2"</TT>,
|
|
<TT>"fma"</TT>,
|
|
<TT>"movbe"</TT>,
|
|
<TT>"ept"</TT>,
|
|
<TT>"lzcnt"</TT>,
|
|
<TT>"hle"</TT>,
|
|
<TT>"rtm"</TT>,
|
|
<TT>"invpcid"</TT>,
|
|
<TT>"clflush"</TT>,
|
|
<TT>"mwaitx"</TT>,
|
|
<TT>"clzero"</TT>,
|
|
<TT>"wbnoinvd"</TT>,
|
|
<TT>"pconfig"</TT>,
|
|
<TT>"waitpkg"</TT>,
|
|
<TT>"cldemote"</TT>,
|
|
<TT>"rdpru"</TT>,
|
|
<TT>"mcommit"</TT>,
|
|
<TT>"lwp"</TT>,
|
|
<TT>"fma4"</TT>,
|
|
<TT>"xop"</TT>,
|
|
<TT>"cx16"</TT>,
|
|
<TT>"syscall"</TT>,
|
|
<TT>"rdtscp"</TT>,
|
|
<TT>"3dnow"</TT>,
|
|
<TT>"3dnowa"</TT>,
|
|
<TT>"sse4a"</TT>,
|
|
<TT>"sse5"</TT>,
|
|
<TT>"svme"</TT>,
|
|
<TT>"abm"</TT> and
|
|
<TT>"padlock"</TT>.
|
|
Note that rather than extending a basic instruction set, the extension
|
|
mnemonics starting with <TT>"no"</TT> revoke the respective functionality.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
When the <TT>".arch"</TT> directive is used with <B>-march</B>, the
|
|
<TT>".arch"</TT> directive will take precedent.
|
|
<DT id="155"><B>-mtune=</B><I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I><DD>
|
|
|
|
|
|
This option specifies a processor to optimize for. When used in
|
|
conjunction with the <B>-march</B> option, only instructions
|
|
of the processor specified by the <B>-march</B> option will be
|
|
generated.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
Valid <I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I> values are identical to the processor list of
|
|
<B>-march=</B><I></I><FONT SIZE="-1"><I>CPU</I></FONT><I></I>.
|
|
<DT id="156"><B>-msse2avx</B><DD>
|
|
|
|
|
|
This option specifies that the assembler should encode <FONT SIZE="-1">SSE</FONT> instructions
|
|
with <FONT SIZE="-1">VEX</FONT> prefix.
|
|
<DT id="157"><B>-msse-check=</B><I>none</I><DD>
|
|
|
|
|
|
|
|
<DT id="158"><B>-msse-check=</B><I>warning</I><DD>
|
|
|
|
|
|
<DT id="159"><B>-msse-check=</B><I>error</I><DD>
|
|
|
|
|
|
|
|
These options control if the assembler should check <FONT SIZE="-1">SSE</FONT> instructions.
|
|
<B>-msse-check=</B><I>none</I> will make the assembler not to check <FONT SIZE="-1">SSE</FONT>
|
|
instructions, which is the default. <B>-msse-check=</B><I>warning</I>
|
|
will make the assembler issue a warning for any <FONT SIZE="-1">SSE</FONT> instruction.
|
|
<B>-msse-check=</B><I>error</I> will make the assembler issue an error
|
|
for any <FONT SIZE="-1">SSE</FONT> instruction.
|
|
<DT id="160"><B>-mavxscalar=</B><I>128</I><DD>
|
|
|
|
|
|
|
|
<DT id="161"><B>-mavxscalar=</B><I>256</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode scalar <FONT SIZE="-1">AVX</FONT>
|
|
instructions. <B>-mavxscalar=</B><I>128</I> will encode scalar
|
|
<FONT SIZE="-1">AVX</FONT> instructions with 128bit vector length, which is the default.
|
|
<B>-mavxscalar=</B><I>256</I> will encode scalar <FONT SIZE="-1">AVX</FONT> instructions
|
|
with 256bit vector length.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
<FONT SIZE="-1">WARNING:</FONT> Don't use this for production code - due to <FONT SIZE="-1">CPU</FONT> errata the
|
|
resulting code may not work on certain models.
|
|
<DT id="162"><B>-mvexwig=</B><I>0</I><DD>
|
|
|
|
|
|
|
|
<DT id="163"><B>-mvexwig=</B><I>1</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode <FONT SIZE="-1">VEX</FONT>.W-ignored (<FONT SIZE="-1">WIG</FONT>)
|
|
<FONT SIZE="-1">VEX</FONT> instructions. <B>-mvexwig=</B><I>0</I> will encode <FONT SIZE="-1">WIG VEX</FONT>
|
|
instructions with vex.w = 0, which is the default.
|
|
<B>-mvexwig=</B><I>1</I> will encode <FONT SIZE="-1">WIG EVEX</FONT> instructions with
|
|
vex.w = 1.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
<FONT SIZE="-1">WARNING:</FONT> Don't use this for production code - due to <FONT SIZE="-1">CPU</FONT> errata the
|
|
resulting code may not work on certain models.
|
|
<DT id="164"><B>-mevexlig=</B><I>128</I><DD>
|
|
|
|
|
|
|
|
<DT id="165"><B>-mevexlig=</B><I>256</I><DD>
|
|
|
|
|
|
<DT id="166"><B>-mevexlig=</B><I>512</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode length-ignored
|
|
(<FONT SIZE="-1">LIG</FONT>) <FONT SIZE="-1">EVEX</FONT> instructions. <B>-mevexlig=</B><I>128</I> will encode <FONT SIZE="-1">LIG
|
|
EVEX</FONT> instructions with 128bit vector length, which is the default.
|
|
<B>-mevexlig=</B><I>256</I> and <B>-mevexlig=</B><I>512</I> will
|
|
encode <FONT SIZE="-1">LIG EVEX</FONT> instructions with 256bit and 512bit vector length,
|
|
respectively.
|
|
<DT id="167"><B>-mevexwig=</B><I>0</I><DD>
|
|
|
|
|
|
|
|
<DT id="168"><B>-mevexwig=</B><I>1</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode w-ignored (<FONT SIZE="-1">WIG</FONT>)
|
|
<FONT SIZE="-1">EVEX</FONT> instructions. <B>-mevexwig=</B><I>0</I> will encode <FONT SIZE="-1">WIG
|
|
EVEX</FONT> instructions with evex.w = 0, which is the default.
|
|
<B>-mevexwig=</B><I>1</I> will encode <FONT SIZE="-1">WIG EVEX</FONT> instructions with
|
|
evex.w = 1.
|
|
<DT id="169"><B>-mmnemonic=</B><I>att</I><DD>
|
|
|
|
|
|
|
|
<DT id="170"><B>-mmnemonic=</B><I>intel</I><DD>
|
|
|
|
|
|
|
|
This option specifies instruction mnemonic for matching instructions.
|
|
The <TT>".att_mnemonic"</TT> and <TT>".intel_mnemonic"</TT> directives will
|
|
take precedent.
|
|
<DT id="171"><B>-msyntax=</B><I>att</I><DD>
|
|
|
|
|
|
|
|
<DT id="172"><B>-msyntax=</B><I>intel</I><DD>
|
|
|
|
|
|
|
|
This option specifies instruction syntax when processing instructions.
|
|
The <TT>".att_syntax"</TT> and <TT>".intel_syntax"</TT> directives will
|
|
take precedent.
|
|
<DT id="173"><B>-mnaked-reg</B><DD>
|
|
|
|
|
|
This option specifies that registers don't require a <B>%</B> prefix.
|
|
The <TT>".att_syntax"</TT> and <TT>".intel_syntax"</TT> directives will take precedent.
|
|
<DT id="174"><B>-madd-bnd-prefix</B><DD>
|
|
|
|
|
|
This option forces the assembler to add <FONT SIZE="-1">BND</FONT> prefix to all branches, even
|
|
if such prefix was not explicitly specified in the source code.
|
|
<DT id="175"><B>-mno-shared</B><DD>
|
|
|
|
|
|
On <FONT SIZE="-1">ELF</FONT> target, the assembler normally optimizes out non-PLT relocations
|
|
against defined non-weak global branch targets with default visibility.
|
|
The <B>-mshared</B> option tells the assembler to generate code which
|
|
may go into a shared library where all non-weak global branch targets
|
|
with default visibility can be preempted. The resulting code is
|
|
slightly bigger. This option only affects the handling of branch
|
|
instructions.
|
|
<DT id="176"><B>-mbig-obj</B><DD>
|
|
|
|
|
|
On x86-64 <FONT SIZE="-1">PE/COFF</FONT> target this option forces the use of big object file
|
|
format, which allows more than 32768 sections.
|
|
<DT id="177"><B>-momit-lock-prefix=</B><I>no</I><DD>
|
|
|
|
|
|
|
|
<DT id="178"><B>-momit-lock-prefix=</B><I>yes</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode lock prefix.
|
|
This option is intended as a workaround for processors, that fail on
|
|
lock prefix. This option can only be safely used with single-core,
|
|
single-thread computers
|
|
<B>-momit-lock-prefix=</B><I>yes</I> will omit all lock prefixes.
|
|
<B>-momit-lock-prefix=</B><I>no</I> will encode lock prefix as usual,
|
|
which is the default.
|
|
<DT id="179"><B>-mfence-as-lock-add=</B><I>no</I><DD>
|
|
|
|
|
|
|
|
<DT id="180"><B>-mfence-as-lock-add=</B><I>yes</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode lfence, mfence and
|
|
sfence.
|
|
<B>-mfence-as-lock-add=</B><I>yes</I> will encode lfence, mfence and
|
|
sfence as <B>lock addl </B>$0x0<B>, (%rsp)</B> in 64-bit mode and
|
|
<B>lock addl </B>$0x0<B>, (%esp)</B> in 32-bit mode.
|
|
<B>-mfence-as-lock-add=</B><I>no</I> will encode lfence, mfence and
|
|
sfence as usual, which is the default.
|
|
<DT id="181"><B>-mrelax-relocations=</B><I>no</I><DD>
|
|
|
|
|
|
|
|
<DT id="182"><B>-mrelax-relocations=</B><I>yes</I><DD>
|
|
|
|
|
|
|
|
These options control whether the assembler should generate relax
|
|
relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
|
|
R_X86_64_REX_GOTPCRELX, in 64-bit mode.
|
|
<B>-mrelax-relocations=</B><I>yes</I> will generate relax relocations.
|
|
<B>-mrelax-relocations=</B><I>no</I> will not generate relax
|
|
relocations. The default can be controlled by a configure option
|
|
<B>--enable-x86-relax-relocations</B>.
|
|
<DT id="183"><B>-malign-branch-boundary=</B><I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I><DD>
|
|
|
|
|
|
This option controls how the assembler should align branches with segment
|
|
prefixes or <FONT SIZE="-1">NOP.</FONT> <I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I> must be a power of 2. It should be 0 or
|
|
no less than 16. Branches will be aligned within <I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I> byte
|
|
boundary. <B>-malign-branch-boundary=0</B>, which is the default,
|
|
doesn't align branches.
|
|
<DT id="184"><B>-malign-branch=</B><I></I><FONT SIZE="-1"><I>TYPE</I></FONT><I></I><B>[+</B><I></I><FONT SIZE="-1"><I>TYPE</I></FONT><I></I><B>...]</B><DD>
|
|
|
|
|
|
This option specifies types of branches to align. <I></I><FONT SIZE="-1"><I>TYPE</I></FONT><I></I> is
|
|
combination of <B>jcc</B>, which aligns conditional jumps,
|
|
<B>fused</B>, which aligns fused conditional jumps, <B>jmp</B>,
|
|
which aligns unconditional jumps, <B>call</B> which aligns calls,
|
|
<B>ret</B>, which aligns rets, <B>indirect</B>, which aligns indirect
|
|
jumps and calls. The default is <B>-malign-branch=jcc+fused+jmp</B>.
|
|
<DT id="185"><B>-malign-branch-prefix-size=</B><I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I><DD>
|
|
|
|
|
|
This option specifies the maximum number of prefixes on an instruction
|
|
to align branches. <I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I> should be between 0 and 5. The default
|
|
<I></I><FONT SIZE="-1"><I>NUM</I></FONT><I></I> is 5.
|
|
<DT id="186"><B>-mbranches-within-32B-boundaries</B><DD>
|
|
|
|
|
|
This option aligns conditional jumps, fused conditional jumps and
|
|
unconditional jumps within 32 byte boundary with up to 5 segment prefixes
|
|
on an instruction. It is equivalent to
|
|
<B>-malign-branch-boundary=32</B>
|
|
<B>-malign-branch=jcc+fused+jmp</B>
|
|
<B>-malign-branch-prefix-size=5</B>.
|
|
The default doesn't align branches.
|
|
<DT id="187"><B>-mx86-used-note=</B><I>no</I><DD>
|
|
|
|
|
|
|
|
<DT id="188"><B>-mx86-used-note=</B><I>yes</I><DD>
|
|
|
|
|
|
|
|
These options control whether the assembler should generate
|
|
<FONT SIZE="-1">GNU_PROPERTY_X86_ISA_1_USED</FONT> and <FONT SIZE="-1">GNU_PROPERTY_X86_FEATURE_2_USED
|
|
GNU</FONT> property notes. The default can be controlled by the
|
|
<B>--enable-x86-used-note</B> configure option.
|
|
<DT id="189"><B>-mevexrcig=</B><I>rne</I><DD>
|
|
|
|
|
|
|
|
<DT id="190"><B>-mevexrcig=</B><I>rd</I><DD>
|
|
|
|
|
|
<DT id="191"><B>-mevexrcig=</B><I>ru</I><DD>
|
|
|
|
|
|
<DT id="192"><B>-mevexrcig=</B><I>rz</I><DD>
|
|
|
|
|
|
|
|
These options control how the assembler should encode SAE-only
|
|
<FONT SIZE="-1">EVEX</FONT> instructions. <B>-mevexrcig=</B><I>rne</I> will encode <FONT SIZE="-1">RC</FONT> bits
|
|
of <FONT SIZE="-1">EVEX</FONT> instruction with 00, which is the default.
|
|
<B>-mevexrcig=</B><I>rd</I>, <B>-mevexrcig=</B><I>ru</I>
|
|
and <B>-mevexrcig=</B><I>rz</I> will encode SAE-only <FONT SIZE="-1">EVEX</FONT> instructions
|
|
with 01, 10 and 11 <FONT SIZE="-1">RC</FONT> bits, respectively.
|
|
<DT id="193"><B>-mamd64</B><DD>
|
|
|
|
|
|
|
|
<DT id="194"><B>-mintel64</B><DD>
|
|
|
|
|
|
|
|
This option specifies that the assembler should accept only <FONT SIZE="-1">AMD64</FONT> or
|
|
Intel64 <FONT SIZE="-1">ISA</FONT> in 64-bit mode. The default is to accept common, Intel64
|
|
only and <FONT SIZE="-1">AMD64</FONT> ISAs.
|
|
<DT id="195"><B>-O0 | -O | -O1 | -O2 | -Os</B><DD>
|
|
|
|
|
|
Optimize instruction encoding with smaller instruction size. <B>-O</B>
|
|
and <B>-O1</B> encode 64-bit register load instructions with 64-bit
|
|
immediate as 32-bit register load instructions with 31-bit or 32-bits
|
|
immediates, encode 64-bit register clearing instructions with 32-bit
|
|
register clearing instructions, encode 256-bit/512-bit <FONT SIZE="-1">VEX/EVEX</FONT> vector
|
|
register clearing instructions with 128-bit <FONT SIZE="-1">VEX</FONT> vector register
|
|
clearing instructions, encode 128-bit/256-bit <FONT SIZE="-1">EVEX</FONT> vector
|
|
register load/store instructions with <FONT SIZE="-1">VEX</FONT> vector register load/store
|
|
instructions, and encode 128-bit/256-bit <FONT SIZE="-1">EVEX</FONT> packed integer logical
|
|
instructions with 128-bit/256-bit <FONT SIZE="-1">VEX</FONT> packed integer logical.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
<B>-O2</B> includes <B>-O1</B> optimization plus encodes
|
|
256-bit/512-bit <FONT SIZE="-1">EVEX</FONT> vector register clearing instructions with 128-bit
|
|
<FONT SIZE="-1">EVEX</FONT> vector register clearing instructions. In 64-bit mode <FONT SIZE="-1">VEX</FONT> encoded
|
|
instructions with commutative source operands will also have their
|
|
source operands swapped if this allows using the 2-byte <FONT SIZE="-1">VEX</FONT> prefix form
|
|
instead of the 3-byte one. Certain forms of <FONT SIZE="-1">AND</FONT> as well as <FONT SIZE="-1">OR</FONT> with the
|
|
same (register) operand specified twice will also be changed to <FONT SIZE="-1">TEST.</FONT>
|
|
|
|
|
|
<P>
|
|
|
|
|
|
<B>-Os</B> includes <B>-O2</B> optimization plus encodes 16-bit, 32-bit
|
|
and 64-bit register tests with immediate as 8-bit register test with
|
|
immediate. <B>-O0</B> turns off this optimization.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for the
|
|
Ubicom <FONT SIZE="-1">IP2K</FONT> series.
|
|
<DL COMPACT>
|
|
<DT id="196"><B>-mip2022ext</B><DD>
|
|
|
|
|
|
Specifies that the extended <FONT SIZE="-1">IP2022</FONT> instructions are allowed.
|
|
<DT id="197"><B>-mip2022</B><DD>
|
|
|
|
|
|
Restores the default behaviour, which restricts the permitted instructions to
|
|
just the basic <FONT SIZE="-1">IP2022</FONT> ones.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for the
|
|
Renesas M32C and M16C processors.
|
|
<DL COMPACT>
|
|
<DT id="198"><B>-m32c</B><DD>
|
|
|
|
|
|
Assemble M32C instructions.
|
|
<DT id="199"><B>-m16c</B><DD>
|
|
|
|
|
|
Assemble M16C instructions (the default).
|
|
<DT id="200"><B>-relax</B><DD>
|
|
|
|
|
|
Enable support for link-time relaxations.
|
|
<DT id="201"><B>-h-tick-hex</B><DD>
|
|
|
|
|
|
Support H'00 style hex constants in addition to 0x00 style.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for the
|
|
Renesas M32R (formerly Mitsubishi M32R) series.
|
|
<DL COMPACT>
|
|
<DT id="202"><B>--m32rx</B><DD>
|
|
|
|
|
|
Specify which processor in the M32R family is the target. The default
|
|
is normally the M32R, but this option changes it to the M32RX.
|
|
<DT id="203"><B>--warn-explicit-parallel-conflicts or --Wp</B><DD>
|
|
|
|
|
|
Produce warning messages when questionable parallel constructs are
|
|
encountered.
|
|
<DT id="204"><B>--no-warn-explicit-parallel-conflicts or --Wnp</B><DD>
|
|
|
|
|
|
Do not produce warning messages when questionable parallel constructs are
|
|
encountered.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for the
|
|
Motorola 68000 series.
|
|
<DL COMPACT>
|
|
<DT id="205"><B>-l</B><DD>
|
|
|
|
|
|
Shorten references to undefined symbols, to one word instead of two.
|
|
<DT id="206"><B>-m68000 | -m68008 | -m68010 | -m68020 | -m68030</B><DD>
|
|
|
|
|
|
|
|
<DT id="207"><B>| -m68040 | -m68060 | -m68302 | -m68331 | -m68332</B><DD>
|
|
|
|
|
|
<DT id="208"><B>| -m68333 | -m68340 | -mcpu32 | -m5200</B><DD>
|
|
|
|
|
|
|
|
Specify what processor in the 68000 family is the target. The default
|
|
is normally the 68020, but this can be changed at configuration time.
|
|
<DT id="209"><B>-m68881 | -m68882 | -mno-68881 | -mno-68882</B><DD>
|
|
|
|
|
|
The target machine does (or does not) have a floating-point coprocessor.
|
|
The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
|
|
the basic 68000 is not compatible with the 68881, a combination of the
|
|
two can be specified, since it's possible to do emulation of the
|
|
coprocessor instructions with the main processor.
|
|
<DT id="210"><B>-m68851 | -mno-68851</B><DD>
|
|
|
|
|
|
The target machine does (or does not) have a memory-management
|
|
unit coprocessor. The default is to assume an <FONT SIZE="-1">MMU</FONT> for 68020 and up.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for an
|
|
Altera Nios <FONT SIZE="-1">II</FONT> processor.
|
|
<DL COMPACT>
|
|
<DT id="211"><B>-relax-section</B><DD>
|
|
|
|
|
|
Replace identified out-of-range branches with PC-relative <TT>"jmp"</TT>
|
|
sequences when possible. The generated code sequences are suitable
|
|
for use in position-independent code, but there is a practical limit
|
|
on the extended branch range because of the length of the sequences.
|
|
This option is the default.
|
|
<DT id="212"><B>-relax-all</B><DD>
|
|
|
|
|
|
Replace branch instructions not determinable to be in range
|
|
and all call instructions with <TT>"jmp"</TT> and <TT>"callr"</TT> sequences
|
|
(respectively). This option generates absolute relocations against the
|
|
target symbols and is not appropriate for position-independent code.
|
|
<DT id="213"><B>-no-relax</B><DD>
|
|
|
|
|
|
Do not replace any branches or calls.
|
|
<DT id="214"><B>-EB</B><DD>
|
|
|
|
|
|
Generate big-endian output.
|
|
<DT id="215"><B>-EL</B><DD>
|
|
|
|
|
|
Generate little-endian output. This is the default.
|
|
<DT id="216"><B>-march=</B><I>architecture</I><DD>
|
|
|
|
|
|
This option specifies the target architecture. The assembler issues
|
|
an error message if an attempt is made to assemble an instruction which
|
|
will not execute on the target architecture. The following architecture
|
|
names are recognized:
|
|
<TT>"r1"</TT>,
|
|
<TT>"r2"</TT>.
|
|
The default is <TT>"r1"</TT>.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for a
|
|
<FONT SIZE="-1">PRU</FONT> processor.
|
|
<DL COMPACT>
|
|
<DT id="217"><B>-mlink-relax</B><DD>
|
|
|
|
|
|
Assume that <FONT SIZE="-1">LD</FONT> would optimize <FONT SIZE="-1">LDI32</FONT> instructions by checking the upper
|
|
16 bits of the <I>expression</I>. If they are all zeros, then <FONT SIZE="-1">LD</FONT> would
|
|
shorten the <FONT SIZE="-1">LDI32</FONT> instruction to a single <FONT SIZE="-1">LDI.</FONT> In such case <TT>"as"</TT>
|
|
will output <FONT SIZE="-1">DIFF</FONT> relocations for diff expressions.
|
|
<DT id="218"><B>-mno-link-relax</B><DD>
|
|
|
|
|
|
Assume that <FONT SIZE="-1">LD</FONT> would not optimize <FONT SIZE="-1">LDI32</FONT> instructions. As a consequence,
|
|
<FONT SIZE="-1">DIFF</FONT> relocations will not be emitted.
|
|
<DT id="219"><B>-mno-warn-regname-label</B><DD>
|
|
|
|
|
|
Do not warn if a label name matches a register name. Usually assembler
|
|
programmers will want this warning to be emitted. C compilers may want
|
|
to turn this off.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for
|
|
a <FONT SIZE="-1">MIPS</FONT> processor.
|
|
<DL COMPACT>
|
|
<DT id="220"><B>-G</B> <I>num</I><DD>
|
|
|
|
|
|
This option sets the largest size of an object that can be referenced
|
|
implicitly with the <TT>"gp"</TT> register. It is only accepted for targets that
|
|
use <FONT SIZE="-1">ECOFF</FONT> format, such as a DECstation running Ultrix. The default value is 8.
|
|
<DT id="221"><B>-EB</B><DD>
|
|
|
|
|
|
Generate ``big endian'' format output.
|
|
<DT id="222"><B>-EL</B><DD>
|
|
|
|
|
|
Generate ``little endian'' format output.
|
|
<DT id="223"><B>-mips1</B><DD>
|
|
|
|
|
|
|
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<DT id="224"><B>-mips2</B><DD>
|
|
|
|
|
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<DT id="225"><B>-mips3</B><DD>
|
|
|
|
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<DT id="226"><B>-mips4</B><DD>
|
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|
|
|
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<DT id="227"><B>-mips5</B><DD>
|
|
|
|
|
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<DT id="228"><B>-mips32</B><DD>
|
|
|
|
|
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<DT id="229"><B>-mips32r2</B><DD>
|
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|
|
|
|
<DT id="230"><B>-mips32r3</B><DD>
|
|
|
|
|
|
<DT id="231"><B>-mips32r5</B><DD>
|
|
|
|
|
|
<DT id="232"><B>-mips32r6</B><DD>
|
|
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|
|
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<DT id="233"><B>-mips64</B><DD>
|
|
|
|
|
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<DT id="234"><B>-mips64r2</B><DD>
|
|
|
|
|
|
<DT id="235"><B>-mips64r3</B><DD>
|
|
|
|
|
|
<DT id="236"><B>-mips64r5</B><DD>
|
|
|
|
|
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<DT id="237"><B>-mips64r6</B><DD>
|
|
|
|
|
|
|
|
Generate code for a particular <FONT SIZE="-1">MIPS</FONT> Instruction Set Architecture level.
|
|
<B>-mips1</B> is an alias for <B>-march=r3000</B>, <B>-mips2</B> is an
|
|
alias for <B>-march=r6000</B>, <B>-mips3</B> is an alias for
|
|
<B>-march=r4000</B> and <B>-mips4</B> is an alias for <B>-march=r8000</B>.
|
|
<B>-mips5</B>, <B>-mips32</B>, <B>-mips32r2</B>, <B>-mips32r3</B>,
|
|
<B>-mips32r5</B>, <B>-mips32r6</B>, <B>-mips64</B>, <B>-mips64r2</B>,
|
|
<B>-mips64r3</B>, <B>-mips64r5</B>, and <B>-mips64r6</B> correspond to generic
|
|
<FONT SIZE="-1">MIPS V, MIPS32, MIPS32</FONT> Release 2, <FONT SIZE="-1">MIPS32</FONT> Release 3, <FONT SIZE="-1">MIPS32</FONT> Release 5, <FONT SIZE="-1">MIPS32</FONT>
|
|
Release 6, <FONT SIZE="-1">MIPS64, MIPS64</FONT> Release 2, <FONT SIZE="-1">MIPS64</FONT> Release 3, <FONT SIZE="-1">MIPS64</FONT> Release 5, and
|
|
<FONT SIZE="-1">MIPS64</FONT> Release 6 <FONT SIZE="-1">ISA</FONT> processors, respectively.
|
|
<DT id="238"><B>-march=</B><I>cpu</I><DD>
|
|
|
|
|
|
Generate code for a particular <FONT SIZE="-1">MIPS CPU.</FONT>
|
|
<DT id="239"><B>-mtune=</B><I>cpu</I><DD>
|
|
|
|
|
|
Schedule and tune for a particular <FONT SIZE="-1">MIPS CPU.</FONT>
|
|
<DT id="240"><B>-mfix7000</B><DD>
|
|
|
|
|
|
|
|
<DT id="241"><B>-mno-fix7000</B><DD>
|
|
|
|
|
|
|
|
Cause nops to be inserted if the read of the destination register
|
|
of an mfhi or mflo instruction occurs in the following two instructions.
|
|
<DT id="242"><B>-mfix-rm7000</B><DD>
|
|
|
|
|
|
|
|
<DT id="243"><B>-mno-fix-rm7000</B><DD>
|
|
|
|
|
|
|
|
Cause nops to be inserted if a dmult or dmultu instruction is
|
|
followed by a load instruction.
|
|
<DT id="244"><B>-mfix-r5900</B><DD>
|
|
|
|
|
|
|
|
<DT id="245"><B>-mno-fix-r5900</B><DD>
|
|
|
|
|
|
|
|
Do not attempt to schedule the preceding instruction into the delay slot
|
|
of a branch instruction placed at the end of a short loop of six
|
|
instructions or fewer and always schedule a <TT>"nop"</TT> instruction there
|
|
instead. The short loop bug under certain conditions causes loops to
|
|
execute only once or twice, due to a hardware bug in the R5900 chip.
|
|
<DT id="246"><B>-mdebug</B><DD>
|
|
|
|
|
|
|
|
<DT id="247"><B>-no-mdebug</B><DD>
|
|
|
|
|
|
|
|
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
|
|
section instead of the standard <FONT SIZE="-1">ELF</FONT> .stabs sections.
|
|
<DT id="248"><B>-mpdr</B><DD>
|
|
|
|
|
|
|
|
<DT id="249"><B>-mno-pdr</B><DD>
|
|
|
|
|
|
|
|
Control generation of <TT>".pdr"</TT> sections.
|
|
<DT id="250"><B>-mgp32</B><DD>
|
|
|
|
|
|
|
|
<DT id="251"><B>-mfp32</B><DD>
|
|
|
|
|
|
|
|
The register sizes are normally inferred from the <FONT SIZE="-1">ISA</FONT> and <FONT SIZE="-1">ABI,</FONT> but these
|
|
flags force a certain group of registers to be treated as 32 bits wide at
|
|
all times. <B>-mgp32</B> controls the size of general-purpose registers
|
|
and <B>-mfp32</B> controls the size of floating-point registers.
|
|
<DT id="252"><B>-mgp64</B><DD>
|
|
|
|
|
|
|
|
<DT id="253"><B>-mfp64</B><DD>
|
|
|
|
|
|
|
|
The register sizes are normally inferred from the <FONT SIZE="-1">ISA</FONT> and <FONT SIZE="-1">ABI,</FONT> but these
|
|
flags force a certain group of registers to be treated as 64 bits wide at
|
|
all times. <B>-mgp64</B> controls the size of general-purpose registers
|
|
and <B>-mfp64</B> controls the size of floating-point registers.
|
|
<DT id="254"><B>-mfpxx</B><DD>
|
|
|
|
|
|
The register sizes are normally inferred from the <FONT SIZE="-1">ISA</FONT> and <FONT SIZE="-1">ABI,</FONT> but using
|
|
this flag in combination with <B>-mabi=32</B> enables an <FONT SIZE="-1">ABI</FONT> variant
|
|
which will operate correctly with floating-point registers which are
|
|
32 or 64 bits wide.
|
|
<DT id="255"><B>-modd-spreg</B><DD>
|
|
|
|
|
|
|
|
<DT id="256"><B>-mno-odd-spreg</B><DD>
|
|
|
|
|
|
|
|
Enable use of floating-point operations on odd-numbered single-precision
|
|
registers when supported by the <FONT SIZE="-1">ISA.</FONT> <B>-mfpxx</B> implies
|
|
<B>-mno-odd-spreg</B>, otherwise the default is <B>-modd-spreg</B>.
|
|
<DT id="257"><B>-mips16</B><DD>
|
|
|
|
|
|
|
|
<DT id="258"><B>-no-mips16</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MIPS 16</FONT> processor. This is equivalent to putting
|
|
<TT>".module mips16"</TT> at the start of the assembly file. <B>-no-mips16</B>
|
|
turns off this option.
|
|
<DT id="259"><B>-mmips16e2</B><DD>
|
|
|
|
|
|
|
|
<DT id="260"><B>-mno-mips16e2</B><DD>
|
|
|
|
|
|
|
|
Enable the use of MIPS16e2 instructions in <FONT SIZE="-1">MIPS16</FONT> mode. This is equivalent
|
|
to putting <TT>".module mips16e2"</TT> at the start of the assembly file.
|
|
<B>-mno-mips16e2</B> turns off this option.
|
|
<DT id="261"><B>-mmicromips</B><DD>
|
|
|
|
|
|
|
|
<DT id="262"><B>-mno-micromips</B><DD>
|
|
|
|
|
|
|
|
Generate code for the microMIPS processor. This is equivalent to putting
|
|
<TT>".module micromips"</TT> at the start of the assembly file.
|
|
<B>-mno-micromips</B> turns off this option. This is equivalent to putting
|
|
<TT>".module nomicromips"</TT> at the start of the assembly file.
|
|
<DT id="263"><B>-msmartmips</B><DD>
|
|
|
|
|
|
|
|
<DT id="264"><B>-mno-smartmips</B><DD>
|
|
|
|
|
|
|
|
Enables the SmartMIPS extension to the <FONT SIZE="-1">MIPS32</FONT> instruction set. This is
|
|
equivalent to putting <TT>".module smartmips"</TT> at the start of the assembly
|
|
file. <B>-mno-smartmips</B> turns off this option.
|
|
<DT id="265"><B>-mips3d</B><DD>
|
|
|
|
|
|
|
|
<DT id="266"><B>-no-mips3d</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MIPS-3D</FONT> Application Specific Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">MIPS-3D</FONT> instructions.
|
|
<B>-no-mips3d</B> turns off this option.
|
|
<DT id="267"><B>-mdmx</B><DD>
|
|
|
|
|
|
|
|
<DT id="268"><B>-no-mdmx</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MDMX</FONT> Application Specific Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">MDMX</FONT> instructions.
|
|
<B>-no-mdmx</B> turns off this option.
|
|
<DT id="269"><B>-mdsp</B><DD>
|
|
|
|
|
|
|
|
<DT id="270"><B>-mno-dsp</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">DSP</FONT> Release 1 Application Specific Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">DSP</FONT> Release 1 instructions.
|
|
<B>-mno-dsp</B> turns off this option.
|
|
<DT id="271"><B>-mdspr2</B><DD>
|
|
|
|
|
|
|
|
<DT id="272"><B>-mno-dspr2</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">DSP</FONT> Release 2 Application Specific Extension.
|
|
This option implies <B>-mdsp</B>.
|
|
This tells the assembler to accept <FONT SIZE="-1">DSP</FONT> Release 2 instructions.
|
|
<B>-mno-dspr2</B> turns off this option.
|
|
<DT id="273"><B>-mdspr3</B><DD>
|
|
|
|
|
|
|
|
<DT id="274"><B>-mno-dspr3</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">DSP</FONT> Release 3 Application Specific Extension.
|
|
This option implies <B>-mdsp</B> and <B>-mdspr2</B>.
|
|
This tells the assembler to accept <FONT SIZE="-1">DSP</FONT> Release 3 instructions.
|
|
<B>-mno-dspr3</B> turns off this option.
|
|
<DT id="275"><B>-mmsa</B><DD>
|
|
|
|
|
|
|
|
<DT id="276"><B>-mno-msa</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MIPS SIMD</FONT> Architecture Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">MSA</FONT> instructions.
|
|
<B>-mno-msa</B> turns off this option.
|
|
<DT id="277"><B>-mxpa</B><DD>
|
|
|
|
|
|
|
|
<DT id="278"><B>-mno-xpa</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MIPS</FONT> eXtended Physical Address (<FONT SIZE="-1">XPA</FONT>) Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">XPA</FONT> instructions.
|
|
<B>-mno-xpa</B> turns off this option.
|
|
<DT id="279"><B>-mmt</B><DD>
|
|
|
|
|
|
|
|
<DT id="280"><B>-mno-mt</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MT</FONT> Application Specific Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">MT</FONT> instructions.
|
|
<B>-mno-mt</B> turns off this option.
|
|
<DT id="281"><B>-mmcu</B><DD>
|
|
|
|
|
|
|
|
<DT id="282"><B>-mno-mcu</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MCU</FONT> Application Specific Extension.
|
|
This tells the assembler to accept <FONT SIZE="-1">MCU</FONT> instructions.
|
|
<B>-mno-mcu</B> turns off this option.
|
|
<DT id="283"><B>-mcrc</B><DD>
|
|
|
|
|
|
|
|
<DT id="284"><B>-mno-crc</B><DD>
|
|
|
|
|
|
|
|
Generate code for the <FONT SIZE="-1">MIPS</FONT> cyclic redundancy check (<FONT SIZE="-1">CRC</FONT>) Application
|
|
Specific Extension. This tells the assembler to accept <FONT SIZE="-1">CRC</FONT> instructions.
|
|
<B>-mno-crc</B> turns off this option.
|
|
<DT id="285"><B>-mginv</B><DD>
|
|
|
|
|
|
|
|
<DT id="286"><B>-mno-ginv</B><DD>
|
|
|
|
|
|
|
|
Generate code for the Global INValidate (<FONT SIZE="-1">GINV</FONT>) Application Specific
|
|
Extension. This tells the assembler to accept <FONT SIZE="-1">GINV</FONT> instructions.
|
|
<B>-mno-ginv</B> turns off this option.
|
|
<DT id="287"><B>-mloongson-mmi</B><DD>
|
|
|
|
|
|
|
|
<DT id="288"><B>-mno-loongson-mmi</B><DD>
|
|
|
|
|
|
|
|
Generate code for the Loongson MultiMedia extensions Instructions (<FONT SIZE="-1">MMI</FONT>)
|
|
Application Specific Extension. This tells the assembler to accept <FONT SIZE="-1">MMI</FONT>
|
|
instructions.
|
|
<B>-mno-loongson-mmi</B> turns off this option.
|
|
<DT id="289"><B>-mloongson-cam</B><DD>
|
|
|
|
|
|
|
|
<DT id="290"><B>-mno-loongson-cam</B><DD>
|
|
|
|
|
|
|
|
Generate code for the Loongson Content Address Memory (<FONT SIZE="-1">CAM</FONT>) instructions.
|
|
This tells the assembler to accept Loongson <FONT SIZE="-1">CAM</FONT> instructions.
|
|
<B>-mno-loongson-cam</B> turns off this option.
|
|
<DT id="291"><B>-mloongson-ext</B><DD>
|
|
|
|
|
|
|
|
<DT id="292"><B>-mno-loongson-ext</B><DD>
|
|
|
|
|
|
|
|
Generate code for the Loongson EXTensions (<FONT SIZE="-1">EXT</FONT>) instructions.
|
|
This tells the assembler to accept Loongson <FONT SIZE="-1">EXT</FONT> instructions.
|
|
<B>-mno-loongson-ext</B> turns off this option.
|
|
<DT id="293"><B>-mloongson-ext2</B><DD>
|
|
|
|
|
|
|
|
<DT id="294"><B>-mno-loongson-ext2</B><DD>
|
|
|
|
|
|
|
|
Generate code for the Loongson EXTensions R2 (<FONT SIZE="-1">EXT2</FONT>) instructions.
|
|
This option implies <B>-mloongson-ext</B>.
|
|
This tells the assembler to accept Loongson <FONT SIZE="-1">EXT2</FONT> instructions.
|
|
<B>-mno-loongson-ext2</B> turns off this option.
|
|
<DT id="295"><B>-minsn32</B><DD>
|
|
|
|
|
|
|
|
<DT id="296"><B>-mno-insn32</B><DD>
|
|
|
|
|
|
|
|
Only use 32-bit instruction encodings when generating code for the
|
|
microMIPS processor. This option inhibits the use of any 16-bit
|
|
instructions. This is equivalent to putting <TT>".set insn32"</TT> at
|
|
the start of the assembly file. <B>-mno-insn32</B> turns off this
|
|
option. This is equivalent to putting <TT>".set noinsn32"</TT> at the
|
|
start of the assembly file. By default <B>-mno-insn32</B> is
|
|
selected, allowing all instructions to be used.
|
|
<DT id="297"><B>--construct-floats</B><DD>
|
|
|
|
|
|
|
|
<DT id="298"><B>--no-construct-floats</B><DD>
|
|
|
|
|
|
|
|
The <B>--no-construct-floats</B> option disables the construction of
|
|
double width floating point constants by loading the two halves of the
|
|
value into the two single width floating point registers that make up
|
|
the double width register. By default <B>--construct-floats</B> is
|
|
selected, allowing construction of these floating point constants.
|
|
<DT id="299"><B>--relax-branch</B><DD>
|
|
|
|
|
|
|
|
<DT id="300"><B>--no-relax-branch</B><DD>
|
|
|
|
|
|
|
|
The <B>--relax-branch</B> option enables the relaxation of out-of-range
|
|
branches. By default <B>--no-relax-branch</B> is selected, causing any
|
|
out-of-range branches to produce an error.
|
|
<DT id="301"><B>-mignore-branch-isa</B><DD>
|
|
|
|
|
|
|
|
<DT id="302"><B>-mno-ignore-branch-isa</B><DD>
|
|
|
|
|
|
|
|
Ignore branch checks for invalid transitions between <FONT SIZE="-1">ISA</FONT> modes. The
|
|
semantics of branches does not provide for an <FONT SIZE="-1">ISA</FONT> mode switch, so in
|
|
most cases the <FONT SIZE="-1">ISA</FONT> mode a branch has been encoded for has to be the
|
|
same as the <FONT SIZE="-1">ISA</FONT> mode of the branch's target label. Therefore <FONT SIZE="-1">GAS</FONT> has
|
|
checks implemented that verify in branch assembly that the two <FONT SIZE="-1">ISA</FONT>
|
|
modes match. <B>-mignore-branch-isa</B> disables these checks. By
|
|
default <B>-mno-ignore-branch-isa</B> is selected, causing any invalid
|
|
branch requiring a transition between <FONT SIZE="-1">ISA</FONT> modes to produce an error.
|
|
<DT id="303"><B>-mnan=</B><I>encoding</I><DD>
|
|
|
|
|
|
Select between the <FONT SIZE="-1">IEEE 754-2008</FONT> (<B>-mnan=2008</B>) or the legacy
|
|
(<B>-mnan=legacy</B>) NaN encoding format. The latter is the default.
|
|
<DT id="304"><B>--emulation=</B><I>name</I><DD>
|
|
|
|
|
|
This option was formerly used to switch between <FONT SIZE="-1">ELF</FONT> and <FONT SIZE="-1">ECOFF</FONT> output
|
|
on targets like <FONT SIZE="-1">IRIX 5</FONT> that supported both. <FONT SIZE="-1">MIPS ECOFF</FONT> support was
|
|
removed in <FONT SIZE="-1">GAS 2.24,</FONT> so the option now serves little purpose.
|
|
It is retained for backwards compatibility.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
The available configuration names are: <B>mipself</B>, <B>mipslelf</B> and
|
|
<B>mipsbelf</B>. Choosing <B>mipself</B> now has no effect, since the output
|
|
is always <FONT SIZE="-1">ELF.</FONT> <B>mipslelf</B> and <B>mipsbelf</B> select little- and
|
|
big-endian output respectively, but <B>-EL</B> and <B>-EB</B> are now the
|
|
preferred options instead.
|
|
<DT id="305"><B>-nocpp</B><DD>
|
|
|
|
|
|
<B>as</B> ignores this option. It is accepted for compatibility with
|
|
the native tools.
|
|
<DT id="306"><B>--trap</B><DD>
|
|
|
|
|
|
|
|
<DT id="307"><B>--no-trap</B><DD>
|
|
|
|
|
|
<DT id="308"><B>--break</B><DD>
|
|
|
|
|
|
<DT id="309"><B>--no-break</B><DD>
|
|
|
|
|
|
|
|
Control how to deal with multiplication overflow and division by zero.
|
|
<B>--trap</B> or <B>--no-break</B> (which are synonyms) take a trap exception
|
|
(and only work for Instruction Set Architecture level 2 and higher);
|
|
<B>--break</B> or <B>--no-trap</B> (also synonyms, and the default) take a
|
|
break exception.
|
|
<DT id="310"><B>-n</B><DD>
|
|
|
|
|
|
When this option is used, <B>as</B> will issue a warning every
|
|
time it generates a nop instruction from a macro.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for a
|
|
Meta processor.
|
|
<DL COMPACT>
|
|
<DT id="311">"-mcpu=metac11"<DD>
|
|
|
|
|
|
|
|
|
|
Generate code for Meta 1.1.
|
|
<DT id="312">"-mcpu=metac12"<DD>
|
|
|
|
|
|
|
|
|
|
Generate code for Meta 1.2.
|
|
<DT id="313">"-mcpu=metac21"<DD>
|
|
|
|
|
|
|
|
|
|
Generate code for Meta 2.1.
|
|
<DT id="314">"-mfpu=metac21"<DD>
|
|
|
|
|
|
|
|
|
|
Allow code to use <FONT SIZE="-1">FPU</FONT> hardware of Meta 2.1.
|
|
</DL>
|
|
<P>
|
|
|
|
See the info pages for documentation of the MMIX-specific options.
|
|
<P>
|
|
|
|
The following options are available when as is configured for a
|
|
<FONT SIZE="-1">NDS32</FONT> processor.
|
|
<DL COMPACT>
|
|
<DT id="315">"-O1"<DD>
|
|
|
|
|
|
|
|
|
|
Optimize for performance.
|
|
<DT id="316">"-Os"<DD>
|
|
|
|
|
|
|
|
|
|
Optimize for space.
|
|
<DT id="317">"-EL"<DD>
|
|
|
|
|
|
|
|
|
|
Produce little endian data output.
|
|
<DT id="318">"-EB"<DD>
|
|
|
|
|
|
|
|
|
|
Produce little endian data output.
|
|
<DT id="319">"-mpic"<DD>
|
|
|
|
|
|
|
|
|
|
Generate <FONT SIZE="-1">PIC.</FONT>
|
|
<DT id="320">"-mno-fp-as-gp-relax"<DD>
|
|
|
|
|
|
|
|
|
|
Suppress fp-as-gp relaxation for this file.
|
|
<DT id="321">"-mb2bb-relax"<DD>
|
|
|
|
|
|
|
|
|
|
Back-to-back branch optimization.
|
|
<DT id="322">"-mno-all-relax"<DD>
|
|
|
|
|
|
|
|
|
|
Suppress all relaxation for this file.
|
|
<DT id="323">"-march=<arch name>"<DD>
|
|
|
|
|
|
|
|
|
|
Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
|
|
v3s, v2, v2j, v2f, v2s.
|
|
<DT id="324">"-mbaseline=<baseline>"<DD>
|
|
|
|
|
|
|
|
|
|
Assemble for baseline <baseline> which could be v2, v3, v3m.
|
|
<DT id="325">"-mfpu-freg=<I>FREG</I>"<DD>
|
|
|
|
|
|
|
|
|
|
Specify a <FONT SIZE="-1">FPU</FONT> configuration.
|
|
<DL COMPACT><DT id="326"><DD>
|
|
<DL COMPACT>
|
|
<DT id="327">"0 8 SP / 4 DP registers"<DD>
|
|
|
|
|
|
|
|
|
|
|
|
<DT id="328">"1 16 SP / 8 DP registers"<DD>
|
|
|
|
|
|
|
|
|
|
<DT id="329">"2 32 SP / 16 DP registers"<DD>
|
|
|
|
|
|
|
|
|
|
<DT id="330">"3 32 SP / 32 DP registers"<DD>
|
|
|
|
|
|
|
|
|
|
</DL>
|
|
</DL>
|
|
|
|
<DL COMPACT><DT id="331"><DD>
|
|
</DL>
|
|
|
|
<DT id="332">"-mabi=<I>abi</I>"<DD>
|
|
|
|
|
|
|
|
|
|
|
|
Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
|
|
<DT id="333">"-m[no-]mac"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable Multiply instructions support.
|
|
<DT id="334">"-m[no-]div"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable Divide instructions support.
|
|
<DT id="335">"-m[no-]16bit-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable 16-bit extension
|
|
<DT id="336">"-m[no-]dx-regs"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable d0/d1 registers
|
|
<DT id="337">"-m[no-]perf-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable Performance extension
|
|
<DT id="338">"-m[no-]perf2-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable Performance extension 2
|
|
<DT id="339">"-m[no-]string-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable String extension
|
|
<DT id="340">"-m[no-]reduced-regs"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable Reduced Register configuration (<FONT SIZE="-1">GPR16</FONT>) option
|
|
<DT id="341">"-m[no-]audio-isa-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable <FONT SIZE="-1">AUDIO ISA</FONT> extension
|
|
<DT id="342">"-m[no-]fpu-sp-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable <FONT SIZE="-1">FPU SP</FONT> extension
|
|
<DT id="343">"-m[no-]fpu-dp-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable <FONT SIZE="-1">FPU DP</FONT> extension
|
|
<DT id="344">"-m[no-]fpu-fma"<DD>
|
|
|
|
|
|
|
|
|
|
Enable/Disable <FONT SIZE="-1">FPU</FONT> fused-multiply-add instructions
|
|
<DT id="345">"-mall-ext"<DD>
|
|
|
|
|
|
|
|
|
|
Turn on all extensions and instructions support
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for a
|
|
PowerPC processor.
|
|
<DL COMPACT>
|
|
<DT id="346"><B>-a32</B><DD>
|
|
|
|
|
|
Generate <FONT SIZE="-1">ELF32</FONT> or <FONT SIZE="-1">XCOFF32.</FONT>
|
|
<DT id="347"><B>-a64</B><DD>
|
|
|
|
|
|
Generate <FONT SIZE="-1">ELF64</FONT> or <FONT SIZE="-1">XCOFF64.</FONT>
|
|
<DT id="348"><B>-K </B><FONT SIZE="-1"><B>PIC</B></FONT><B></B><DD>
|
|
|
|
|
|
Set <FONT SIZE="-1">EF_PPC_RELOCATABLE_LIB</FONT> in <FONT SIZE="-1">ELF</FONT> flags.
|
|
<DT id="349"><B>-mpwrx | -mpwr2</B><DD>
|
|
|
|
|
|
Generate code for <FONT SIZE="-1">POWER/2</FONT> (<FONT SIZE="-1">RIOS2</FONT>).
|
|
<DT id="350"><B>-mpwr</B><DD>
|
|
|
|
|
|
Generate code for <FONT SIZE="-1">POWER</FONT> (<FONT SIZE="-1">RIOS1</FONT>)
|
|
<DT id="351"><B>-m601</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 601.
|
|
<DT id="352"><B>-mppc, -mppc32, -m603, -m604</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 603/604.
|
|
<DT id="353"><B>-m403, -m405</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 403/405.
|
|
<DT id="354"><B>-m440</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 440. BookE and some 405 instructions.
|
|
<DT id="355"><B>-m464</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 464.
|
|
<DT id="356"><B>-m476</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 476.
|
|
<DT id="357"><B>-m7400, -m7410, -m7450, -m7455</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 7400/7410/7450/7455.
|
|
<DT id="358"><B>-m750cl, -mgekko, -mbroadway</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 750CL/Gekko/Broadway.
|
|
<DT id="359"><B>-m821, -m850, -m860</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 821/850/860.
|
|
<DT id="360"><B>-mppc64, -m620</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 620/625/630.
|
|
<DT id="361"><B>-me500, -me500x2</B><DD>
|
|
|
|
|
|
Generate code for Motorola e500 core complex.
|
|
<DT id="362"><B>-me500mc</B><DD>
|
|
|
|
|
|
Generate code for Freescale e500mc core complex.
|
|
<DT id="363"><B>-me500mc64</B><DD>
|
|
|
|
|
|
Generate code for Freescale e500mc64 core complex.
|
|
<DT id="364"><B>-me5500</B><DD>
|
|
|
|
|
|
Generate code for Freescale e5500 core complex.
|
|
<DT id="365"><B>-me6500</B><DD>
|
|
|
|
|
|
Generate code for Freescale e6500 core complex.
|
|
<DT id="366"><B>-mspe</B><DD>
|
|
|
|
|
|
Generate code for Motorola <FONT SIZE="-1">SPE</FONT> instructions.
|
|
<DT id="367"><B>-mspe2</B><DD>
|
|
|
|
|
|
Generate code for Freescale <FONT SIZE="-1">SPE2</FONT> instructions.
|
|
<DT id="368"><B>-mtitan</B><DD>
|
|
|
|
|
|
Generate code for AppliedMicro Titan core complex.
|
|
<DT id="369"><B>-mppc64bridge</B><DD>
|
|
|
|
|
|
Generate code for PowerPC 64, including bridge insns.
|
|
<DT id="370"><B>-mbooke</B><DD>
|
|
|
|
|
|
Generate code for 32-bit BookE.
|
|
<DT id="371"><B>-ma2</B><DD>
|
|
|
|
|
|
Generate code for A2 architecture.
|
|
<DT id="372"><B>-me300</B><DD>
|
|
|
|
|
|
Generate code for PowerPC e300 family.
|
|
<DT id="373"><B>-maltivec</B><DD>
|
|
|
|
|
|
Generate code for processors with AltiVec instructions.
|
|
<DT id="374"><B>-mvle</B><DD>
|
|
|
|
|
|
Generate code for Freescale PowerPC <FONT SIZE="-1">VLE</FONT> instructions.
|
|
<DT id="375"><B>-mvsx</B><DD>
|
|
|
|
|
|
Generate code for processors with Vector-Scalar (<FONT SIZE="-1">VSX</FONT>) instructions.
|
|
<DT id="376"><B>-mhtm</B><DD>
|
|
|
|
|
|
Generate code for processors with Hardware Transactional Memory instructions.
|
|
<DT id="377"><B>-mpower4, -mpwr4</B><DD>
|
|
|
|
|
|
Generate code for Power4 architecture.
|
|
<DT id="378"><B>-mpower5, -mpwr5, -mpwr5x</B><DD>
|
|
|
|
|
|
Generate code for Power5 architecture.
|
|
<DT id="379"><B>-mpower6, -mpwr6</B><DD>
|
|
|
|
|
|
Generate code for Power6 architecture.
|
|
<DT id="380"><B>-mpower7, -mpwr7</B><DD>
|
|
|
|
|
|
Generate code for Power7 architecture.
|
|
<DT id="381"><B>-mpower8, -mpwr8</B><DD>
|
|
|
|
|
|
Generate code for Power8 architecture.
|
|
<DT id="382"><B>-mpower9, -mpwr9</B><DD>
|
|
|
|
|
|
Generate code for Power9 architecture.
|
|
<DT id="383"><B>-mcell</B><DD>
|
|
|
|
|
|
|
|
<DT id="384"><B>-mcell</B><DD>
|
|
|
|
|
|
|
|
Generate code for Cell Broadband Engine architecture.
|
|
<DT id="385"><B>-mcom</B><DD>
|
|
|
|
|
|
Generate code Power/PowerPC common instructions.
|
|
<DT id="386"><B>-many</B><DD>
|
|
|
|
|
|
Generate code for any architecture (<FONT SIZE="-1">PWR/PWRX/PPC</FONT>).
|
|
<DT id="387"><B>-mregnames</B><DD>
|
|
|
|
|
|
Allow symbolic names for registers.
|
|
<DT id="388"><B>-mno-regnames</B><DD>
|
|
|
|
|
|
Do not allow symbolic names for registers.
|
|
<DT id="389"><B>-mrelocatable</B><DD>
|
|
|
|
|
|
Support for <FONT SIZE="-1">GCC</FONT>'s -mrelocatable option.
|
|
<DT id="390"><B>-mrelocatable-lib</B><DD>
|
|
|
|
|
|
Support for <FONT SIZE="-1">GCC</FONT>'s -mrelocatable-lib option.
|
|
<DT id="391"><B>-memb</B><DD>
|
|
|
|
|
|
Set <FONT SIZE="-1">PPC_EMB</FONT> bit in <FONT SIZE="-1">ELF</FONT> flags.
|
|
<DT id="392"><B>-mlittle, -mlittle-endian, -le</B><DD>
|
|
|
|
|
|
Generate code for a little endian machine.
|
|
<DT id="393"><B>-mbig, -mbig-endian, -be</B><DD>
|
|
|
|
|
|
Generate code for a big endian machine.
|
|
<DT id="394"><B>-msolaris</B><DD>
|
|
|
|
|
|
Generate code for Solaris.
|
|
<DT id="395"><B>-mno-solaris</B><DD>
|
|
|
|
|
|
Do not generate code for Solaris.
|
|
<DT id="396"><B>-nops=</B><I>count</I><DD>
|
|
|
|
|
|
If an alignment directive inserts more than <I>count</I> nops, put a
|
|
branch at the beginning to skip execution of the nops.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for a
|
|
RISC-V processor.
|
|
<DL COMPACT>
|
|
<DT id="397"><B>-fpic</B><DD>
|
|
|
|
|
|
|
|
<DT id="398"><B>-fPIC</B><DD>
|
|
|
|
|
|
|
|
Generate position-independent code
|
|
<DT id="399"><B>-fno-pic</B><DD>
|
|
|
|
|
|
Don't generate position-independent code (default)
|
|
<DT id="400"><B>-march=ISA</B><DD>
|
|
|
|
|
|
Select the base isa, as specified by <FONT SIZE="-1">ISA.</FONT> For example -march=rv32ima.
|
|
<DT id="401"><B>-mabi=ABI</B><DD>
|
|
|
|
|
|
Selects the <FONT SIZE="-1">ABI,</FONT> which is either ``ilp32'' or ``lp64'', optionally followed
|
|
by ``f'', ``d'', or ``q'' to indicate single-precision, double-precision, or
|
|
quad-precision floating-point calling convention, or none to indicate
|
|
the soft-float calling convention. Also, ``ilp32'' can optionally be followed
|
|
by ``e'' to indicate the <FONT SIZE="-1">RVE ABI,</FONT> which is always soft-float.
|
|
<DT id="402"><B>-mrelax</B><DD>
|
|
|
|
|
|
Take advantage of linker relaxations to reduce the number of instructions
|
|
required to materialize symbol addresses. (default)
|
|
<DT id="403"><B>-mno-relax</B><DD>
|
|
|
|
|
|
Don't do linker relaxations.
|
|
</DL>
|
|
<P>
|
|
|
|
See the info pages for documentation of the RX-specific options.
|
|
<P>
|
|
|
|
The following options are available when as is configured for the s390
|
|
processor family.
|
|
<DL COMPACT>
|
|
<DT id="404"><B>-m31</B><DD>
|
|
|
|
|
|
|
|
<DT id="405"><B>-m64</B><DD>
|
|
|
|
|
|
|
|
Select the word size, either 31/32 bits or 64 bits.
|
|
<DT id="406"><B>-mesa</B><DD>
|
|
|
|
|
|
|
|
<DT id="407"><B>-mzarch</B><DD>
|
|
|
|
|
|
|
|
Select the architecture mode, either the Enterprise System
|
|
Architecture (esa) or the z/Architecture mode (zarch).
|
|
<DT id="408"><B>-march=</B><I>processor</I><DD>
|
|
|
|
|
|
Specify which s390 processor variant is the target, <B>g5</B> (or
|
|
<B>arch3</B>), <B>g6</B>, <B>z900</B> (or <B>arch5</B>), <B>z990</B> (or
|
|
<B>arch6</B>), <B>z9-109</B>, <B>z9-ec</B> (or <B>arch7</B>), <B>z10</B> (or
|
|
<B>arch8</B>), <B>z196</B> (or <B>arch9</B>), <B>zEC12</B> (or <B>arch10</B>),
|
|
<B>z13</B> (or <B>arch11</B>), <B>z14</B> (or <B>arch12</B>), or <B>z15</B>
|
|
(or <B>arch13</B>).
|
|
<DT id="409"><B>-mregnames</B><DD>
|
|
|
|
|
|
|
|
<DT id="410"><B>-mno-regnames</B><DD>
|
|
|
|
|
|
|
|
Allow or disallow symbolic names for registers.
|
|
<DT id="411"><B>-mwarn-areg-zero</B><DD>
|
|
|
|
|
|
Warn whenever the operand for a base or index register has been specified
|
|
but evaluates to zero.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for a
|
|
<FONT SIZE="-1">TMS320C6000</FONT> processor.
|
|
<DL COMPACT>
|
|
<DT id="412"><B>-march=</B><I>arch</I><DD>
|
|
|
|
|
|
Enable (only) instructions from architecture <I>arch</I>. By default,
|
|
all instructions are permitted.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
The following values of <I>arch</I> are accepted: <TT>"c62x"</TT>,
|
|
<TT>"c64x"</TT>, <TT>"c64x+"</TT>, <TT>"c67x"</TT>, <TT>"c67x+"</TT>, <TT>"c674x"</TT>.
|
|
<DT id="413"><B>-mdsbt</B><DD>
|
|
|
|
|
|
|
|
<DT id="414"><B>-mno-dsbt</B><DD>
|
|
|
|
|
|
|
|
The <B>-mdsbt</B> option causes the assembler to generate the
|
|
<TT>"Tag_ABI_DSBT"</TT> attribute with a value of 1, indicating that the
|
|
code is using <FONT SIZE="-1">DSBT</FONT> addressing. The <B>-mno-dsbt</B> option, the
|
|
default, causes the tag to have a value of 0, indicating that the code
|
|
does not use <FONT SIZE="-1">DSBT</FONT> addressing. The linker will emit a warning if
|
|
objects of different type (<FONT SIZE="-1">DSBT</FONT> and non-DSBT) are linked together.
|
|
<DT id="415"><B>-mpid=no</B><DD>
|
|
|
|
|
|
|
|
<DT id="416"><B>-mpid=near</B><DD>
|
|
|
|
|
|
<DT id="417"><B>-mpid=far</B><DD>
|
|
|
|
|
|
|
|
The <B>-mpid=</B> option causes the assembler to generate the
|
|
<TT>"Tag_ABI_PID"</TT> attribute with a value indicating the form of data
|
|
addressing used by the code. <B>-mpid=no</B>, the default,
|
|
indicates position-dependent data addressing, <B>-mpid=near</B>
|
|
indicates position-independent addressing with <FONT SIZE="-1">GOT</FONT> accesses using near
|
|
<FONT SIZE="-1">DP</FONT> addressing, and <B>-mpid=far</B> indicates position-independent
|
|
addressing with <FONT SIZE="-1">GOT</FONT> accesses using far <FONT SIZE="-1">DP</FONT> addressing. The linker will
|
|
emit a warning if objects built with different settings of this option
|
|
are linked together.
|
|
<DT id="418"><B>-mpic</B><DD>
|
|
|
|
|
|
|
|
<DT id="419"><B>-mno-pic</B><DD>
|
|
|
|
|
|
|
|
The <B>-mpic</B> option causes the assembler to generate the
|
|
<TT>"Tag_ABI_PIC"</TT> attribute with a value of 1, indicating that the
|
|
code is using position-independent code addressing, The
|
|
<TT>"-mno-pic"</TT> option, the default, causes the tag to have a value of
|
|
0, indicating position-dependent code addressing. The linker will
|
|
emit a warning if objects of different type (position-dependent and
|
|
position-independent) are linked together.
|
|
<DT id="420"><B>-mbig-endian</B><DD>
|
|
|
|
|
|
|
|
<DT id="421"><B>-mlittle-endian</B><DD>
|
|
|
|
|
|
|
|
Generate code for the specified endianness. The default is
|
|
little-endian.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for a TILE-Gx
|
|
processor.
|
|
<DL COMPACT>
|
|
<DT id="422"><B>-m32 | -m64</B><DD>
|
|
|
|
|
|
Select the word size, either 32 bits or 64 bits.
|
|
<DT id="423"><B>-EB | -EL</B><DD>
|
|
|
|
|
|
Select the endianness, either big-endian (-EB) or little-endian (-EL).
|
|
</DL>
|
|
<P>
|
|
|
|
The following option is available when as is configured for a Visium
|
|
processor.
|
|
<DL COMPACT>
|
|
<DT id="424"><B>-mtune=</B><I>arch</I><DD>
|
|
|
|
|
|
This option specifies the target architecture. If an attempt is made to
|
|
assemble an instruction that will not execute on the target architecture,
|
|
the assembler will issue an error message.
|
|
|
|
|
|
<P>
|
|
|
|
|
|
The following names are recognized:
|
|
<TT>"mcm24"</TT>
|
|
<TT>"mcm"</TT>
|
|
<TT>"gr5"</TT>
|
|
<TT>"gr6"</TT>
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for an
|
|
Xtensa processor.
|
|
<DL COMPACT>
|
|
<DT id="425"><B>--text-section-literals | --no-text-section-literals</B><DD>
|
|
|
|
|
|
Control the treatment of literal pools. The default is
|
|
<B>--no-text-section-literals</B>, which places literals in
|
|
separate sections in the output file. This allows the literal pool to be
|
|
placed in a data <FONT SIZE="-1">RAM/ROM.</FONT> With <B>--text-section-literals</B>, the
|
|
literals are interspersed in the text section in order to keep them as
|
|
close as possible to their references. This may be necessary for large
|
|
assembly files, where the literals would otherwise be out of range of the
|
|
<TT>"L32R"</TT> instructions in the text section. Literals are grouped into
|
|
pools following <TT>".literal_position"</TT> directives or preceding
|
|
<TT>"ENTRY"</TT> instructions. These options only affect literals referenced
|
|
via PC-relative <TT>"L32R"</TT> instructions; literals for absolute mode
|
|
<TT>"L32R"</TT> instructions are handled separately.
|
|
<DT id="426"><B>--auto-litpools | --no-auto-litpools</B><DD>
|
|
|
|
|
|
Control the treatment of literal pools. The default is
|
|
<B>--no-auto-litpools</B>, which in the absence of
|
|
<B>--text-section-literals</B> places literals in separate sections
|
|
in the output file. This allows the literal pool to be placed in a data
|
|
<FONT SIZE="-1">RAM/ROM.</FONT> With <B>--auto-litpools</B>, the literals are interspersed
|
|
in the text section in order to keep them as close as possible to their
|
|
references, explicit <TT>".literal_position"</TT> directives are not
|
|
required. This may be necessary for very large functions, where single
|
|
literal pool at the beginning of the function may not be reachable by
|
|
<TT>"L32R"</TT> instructions at the end. These options only affect
|
|
literals referenced via PC-relative <TT>"L32R"</TT> instructions; literals
|
|
for absolute mode <TT>"L32R"</TT> instructions are handled separately.
|
|
When used together with <B>--text-section-literals</B>,
|
|
<B>--auto-litpools</B> takes precedence.
|
|
<DT id="427"><B>--absolute-literals | --no-absolute-literals</B><DD>
|
|
|
|
|
|
Indicate to the assembler whether <TT>"L32R"</TT> instructions use absolute
|
|
or PC-relative addressing. If the processor includes the absolute
|
|
addressing option, the default is to use absolute <TT>"L32R"</TT>
|
|
relocations. Otherwise, only the PC-relative <TT>"L32R"</TT> relocations
|
|
can be used.
|
|
<DT id="428"><B>--target-align | --no-target-align</B><DD>
|
|
|
|
|
|
Enable or disable automatic alignment to reduce branch penalties at some
|
|
expense in code size. This optimization is enabled by default. Note
|
|
that the assembler will always align instructions like <TT>"LOOP"</TT> that
|
|
have fixed alignment requirements.
|
|
<DT id="429"><B>--longcalls | --no-longcalls</B><DD>
|
|
|
|
|
|
Enable or disable transformation of call instructions to allow calls
|
|
across a greater range of addresses. This option should be used when call
|
|
targets can potentially be out of range. It may degrade both code size
|
|
and performance, but the linker can generally optimize away the
|
|
unnecessary overhead when a call ends up within range. The default is
|
|
<B>--no-longcalls</B>.
|
|
<DT id="430"><B>--transform | --no-transform</B><DD>
|
|
|
|
|
|
Enable or disable all assembler transformations of Xtensa instructions,
|
|
including both relaxation and optimization. The default is
|
|
<B>--transform</B>; <B>--no-transform</B> should only be used in the
|
|
rare cases when the instructions must be exactly as specified in the
|
|
assembly source. Using <B>--no-transform</B> causes out of range
|
|
instruction operands to be errors.
|
|
<DT id="431"><B>--rename-section</B> <I>oldname</I><B>=</B><I>newname</I><DD>
|
|
|
|
|
|
Rename the <I>oldname</I> section to <I>newname</I>. This option can be used
|
|
multiple times to rename multiple sections.
|
|
<DT id="432"><B>--trampolines | --no-trampolines</B><DD>
|
|
|
|
|
|
Enable or disable transformation of jump instructions to allow jumps
|
|
across a greater range of addresses. This option should be used when jump targets can
|
|
potentially be out of range. In the absence of such jumps this option
|
|
does not affect code size or performance. The default is
|
|
<B>--trampolines</B>.
|
|
</DL>
|
|
<P>
|
|
|
|
The following options are available when as is configured for an
|
|
Z80 processor.
|
|
<P>
|
|
|
|
<TT>@chapter</TT> Z80 Dependent Features
|
|
<A NAME="lbAI"> </A>
|
|
<H3>Command-line Options</H3>
|
|
|
|
|
|
|
|
<DL COMPACT>
|
|
<DT id="433"><B>-z80</B><DD>
|
|
|
|
|
|
Produce code for the Z80 processor. By default accepted undocumented
|
|
operations with halves of index registers (<TT>"IXL"</TT>, <TT>"IXH"</TT>, <TT>"IYL"</TT>, <TT>"IYH"</TT>) and
|
|
instuction <TT>"IN F,(C)"</TT>. Other useful undocumented instructions produces
|
|
warnings. Undocumented instructions may not work on some CPUs, use
|
|
them on your own risk.
|
|
<DT id="434"><B>-r800</B><DD>
|
|
|
|
|
|
Produce code for the R800 processor.
|
|
<DT id="435"><B>-z180</B><DD>
|
|
|
|
|
|
Produce code for the Z180 processor.
|
|
<DT id="436"><B>-ez80</B><DD>
|
|
|
|
|
|
Produce code for the eZ80 processor in Z80 memory mode by default.
|
|
<DT id="437"><B>-ez80-adl</B><DD>
|
|
|
|
|
|
Produce code for the eZ80 processor in <FONT SIZE="-1">ADL</FONT> memory mode by default.
|
|
<DT id="438"><B>-local-prefix=</B><I>prefix</I><DD>
|
|
|
|
|
|
Mark all labels with specified prefix as local. But such label can be
|
|
marked global explicitly in the code. This option do not change default
|
|
local label prefix <TT>".L"</TT>, it is just adds new one.
|
|
<DT id="439"><B>-colonless</B><DD>
|
|
|
|
|
|
Accept colonless labels. All names at line begin are treated as labels.
|
|
<DT id="440"><B>-sdcc</B><DD>
|
|
|
|
|
|
Accept assembler code produced by <FONT SIZE="-1">SDCC.</FONT>
|
|
<DT id="441"><B>-fp-s=</B><I></I><FONT SIZE="-1"><I>FORMAT</I></FONT><I></I><DD>
|
|
|
|
|
|
Single precision floating point numbers format. Default: ieee754 (32 bit).
|
|
<DT id="442"><B>-fp-d=</B><I></I><FONT SIZE="-1"><I>FORMAT</I></FONT><I></I><DD>
|
|
|
|
|
|
Double precision floating point numbers format. Default: ieee754 (64 bit).
|
|
<DT id="443"><B>-strict</B><DD>
|
|
|
|
|
|
Accept documented instructions only.
|
|
<DT id="444"><B>-full</B><DD>
|
|
|
|
|
|
Accept all known Z80 instructions.
|
|
<DT id="445"><B>-with-inst=</B><I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B><DD>
|
|
|
|
|
|
|
|
<DT id="446"><B>-Wnins</B> <I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B><DD>
|
|
|
|
|
|
|
|
Enable specified undocumented instruction(s).
|
|
<DT id="447"><B>-without-inst=</B><I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B><DD>
|
|
|
|
|
|
|
|
<DT id="448"><B>-Fins</B> <I></I><FONT SIZE="-1"><I>INST</I></FONT><I></I><B>[,...]</B><DD>
|
|
|
|
|
|
|
|
Disable specified undocumented instruction(s).
|
|
<DT id="449"><B>-ignore-undocumented-instructions</B><DD>
|
|
|
|
|
|
|
|
<DT id="450"><B>-Wnud</B><DD>
|
|
|
|
|
|
|
|
Silently assemble undocumented Z80-instructions that have been adopted
|
|
as documented R800-instructions .
|
|
<DT id="451"><B>-ignore-unportable-instructions</B><DD>
|
|
|
|
|
|
|
|
<DT id="452"><B>-Wnup</B><DD>
|
|
|
|
|
|
|
|
Silently assemble all undocumented Z80-instructions.
|
|
<DT id="453"><B>-warn-undocumented-instructions</B><DD>
|
|
|
|
|
|
|
|
<DT id="454"><B>-Wud</B><DD>
|
|
|
|
|
|
|
|
Issue warnings for undocumented Z80-instructions that work on R800, do
|
|
not assemble other undocumented instructions without warning.
|
|
<DT id="455"><B>-warn-unportable-instructions</B><DD>
|
|
|
|
|
|
|
|
<DT id="456"><B>-Wup</B><DD>
|
|
|
|
|
|
|
|
Issue warnings for other undocumented Z80-instructions, do not treat any
|
|
undocumented instructions as errors.
|
|
<DT id="457"><B>-forbid-undocumented-instructions</B><DD>
|
|
|
|
|
|
|
|
<DT id="458"><B>-Fud</B><DD>
|
|
|
|
|
|
|
|
Treat all undocumented z80-instructions as errors.
|
|
<DT id="459"><B>-forbid-unportable-instructions</B><DD>
|
|
|
|
|
|
|
|
<DT id="460"><B>-Fup</B><DD>
|
|
|
|
|
|
|
|
Treat undocumented z80-instructions that do not work on R800 as errors.
|
|
</DL>
|
|
<A NAME="lbAJ"> </A>
|
|
<H2>SEE ALSO</H2>
|
|
|
|
|
|
|
|
<B><A HREF="/cgi-bin/man/man2html?1+gcc">gcc</A></B>(1), <B><A HREF="/cgi-bin/man/man2html?1+ld">ld</A></B>(1), and the Info entries for <I>binutils</I> and <I>ld</I>.
|
|
<A NAME="lbAK"> </A>
|
|
<H2>COPYRIGHT</H2>
|
|
|
|
|
|
|
|
Copyright (c) 1991-2020 Free Software Foundation, Inc.
|
|
<P>
|
|
|
|
Permission is granted to copy, distribute and/or modify this document
|
|
under the terms of the <FONT SIZE="-1">GNU</FONT> Free Documentation License, Version 1.3
|
|
or any later version published by the Free Software Foundation;
|
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
|
Back-Cover Texts. A copy of the license is included in the
|
|
section entitled ``<FONT SIZE="-1">GNU</FONT> Free Documentation License''.
|
|
<P>
|
|
|
|
<HR>
|
|
<A NAME="index"> </A><H2>Index</H2>
|
|
<DL>
|
|
<DT id="461"><A HREF="#lbAB">NAME</A><DD>
|
|
<DT id="462"><A HREF="#lbAC">SYNOPSIS</A><DD>
|
|
<DT id="463"><A HREF="#lbAD">TARGET</A><DD>
|
|
<DT id="464"><A HREF="#lbAE">DESCRIPTION</A><DD>
|
|
<DT id="465"><A HREF="#lbAF">OPTIONS</A><DD>
|
|
<DL>
|
|
<DT id="466"><A HREF="#lbAG">Options</A><DD>
|
|
<DT id="467"><A HREF="#lbAH">Options</A><DD>
|
|
<DT id="468"><A HREF="#lbAI">Command-line Options</A><DD>
|
|
</DL>
|
|
<DT id="469"><A HREF="#lbAJ">SEE ALSO</A><DD>
|
|
<DT id="470"><A HREF="#lbAK">COPYRIGHT</A><DD>
|
|
</DL>
|
|
<HR>
|
|
This document was created by
|
|
<A HREF="/cgi-bin/man/man2html">man2html</A>,
|
|
using the manual pages.<BR>
|
|
Time: 00:05:07 GMT, March 31, 2021
|
|
</BODY>
|
|
</HTML>
|