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fp improvements for x86_64

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Specializations for operands that are the same.

original commit: 9585613deebe83366845c4ab203d1d2a4b9cda00
This commit is contained in:
Matthew Flatt 2020-06-14 15:46:43 -06:00
parent 1bc51a7ba4
commit 4f35f62a89
1 changed files with 8 additions and 3 deletions
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9
s/x86_64.ss
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@ -897,7 +897,8 @@
(define-instruction value (fpmove) (define-instruction value (fpmove)
[(op (x fpmem) (y fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove ,y))] [(op (x fpmem) (y fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove ,y))]
[(op (x fpur) (y fpmem fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove ,y))]) [(op (x fpur) (y fpmem)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove ,y))]
[(op (x fpur) (y fpur)) `(set! ,(make-live-info) ,x ,y)])
(define-instruction value (fpcastto) (define-instruction value (fpcastto)
[(op (x mem) (y fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove ,y))] [(op (x mem) (y fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove ,y))]
@ -2067,8 +2068,12 @@
(emit-it (cons 'reg %Cfparg1) dest-reg code*)))))] (emit-it (cons 'reg %Cfparg1) dest-reg code*)))))]
[else [else
(Trivit (dest-reg src1 src2) (Trivit (dest-reg src1 src2)
(if (equal? src1 src2)
;; avoid redundant load
(emit sse.movsd src1 dest-reg (emit sse.movsd src1 dest-reg
(emit-it src2 dest-reg code*)))])))) (emit-it dest-reg dest-reg code*))
(emit sse.movsd src1 dest-reg
(emit-it src2 dest-reg code*))))]))))
(define asm-fpsqrt (define asm-fpsqrt
(lambda (code* dest-reg src) (lambda (code* dest-reg src)