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add needed store fence in list-bits management

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This commit is contained in:
Matthew Flatt 2020-08-04 15:05:13 +00:00
parent 342e95cf32
commit 65b69a91e5
2 changed files with 13 additions and 2 deletions
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5
racket/src/ChezScheme/c/alloc.c
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@ -475,9 +475,10 @@ void S_list_bits_set(p, bits) ptr p; iptr bits; {
memset(list_bits, 0, segment_bitmap_bytes); memset(list_bits, 0, segment_bitmap_bytes);
/* FIXME: A write fence is needed here to make sure `list_bits` is /* A store fence is needed here to make sure `list_bits` is zeroed
zeroed for everyone who sees it. On x86, TSO takes care of that for everyone who sees it. On x86, TSO takes care of that
ordering already. */ ordering already. */
STORE_FENCE();
/* beware: racy write here */ /* beware: racy write here */
si->list_bits = list_bits; si->list_bits = list_bits;

10
racket/src/ChezScheme/c/version.h
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@ -468,3 +468,13 @@ typedef char tputsputcchar;
/* Use "/dev/urandom" everywhere except Windows */ /* Use "/dev/urandom" everywhere except Windows */
#define USE_DEV_URANDOM_UUID #define USE_DEV_URANDOM_UUID
#if defined(__arm64__) || defined(__arm32__)
# define STORE_FENCE() __asm__ __volatile__ ("dmb ishst" : : : "memory")
#elif defined(__powerpc64__)
# define STORE_FENCE() __asm__ __volatile__ ("lwsync" : : : "memory")
#elif defined(__powerpc__) || defined(__POWERPC__)
# define STORE_FENCE() __asm__ __volatile__ ("sync" : : : "memory")
#else
# define STORE_FENCE() /* empty */
#endif