suzanne.soy/racket
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

try again to fix trouble mfence use for futures

Browse Source
This commit is contained in:
Matthew Flatt 2010-09-16 06:27:55 -06:00
parent 11f6ec1b98
commit d4b0048d42
2 changed files with 18 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/racket/sconfig.h
View File

@ -1347,7 +1347,7 @@
/* MZ_USE_JIT_I386 enables the JIT for x86 */ /* MZ_USE_JIT_I386 enables the JIT for x86 */
/* MZ_USE_JIT_X86_65 enables the JIT for x86_64 */ /* MZ_USE_JIT_X86_64 enables the JIT for x86_64 */
/* MZ_USE_JIT_PPC enables the JIT for PowerPC */ /* MZ_USE_JIT_PPC enables the JIT for PowerPC */

26
src/racket/src/future.c
View File

@ -526,15 +526,23 @@ void scheme_future_block_until_gc()
} }
if (cpucount > 1) { if (cpucount > 1) {
/* `cpucount' is not actually a complete test for whether mfence /* In principle, we need some sort of fence to ensure that future
should work, but the probability of someone using futures threads see the change to the fuel pointer. The MFENCE
on a multiprocessor system without SSE2 seems very low. */ instruction would do that, but it requires SSE2. The CPUID
#ifdef _MSC_VER instruction is a non-privileged serializing instruction that
__asm { should be available on any x86 platform that runs threads. */
mfence #if defined(i386) || defined(__i386__) || defined(__x86_64) || defined(__x86_64__) || defined(__amd64__)
} # ifdef _MSC_VER
#else {
asm("mfence"); int r[4];
__cpuid(r, 0);
}
# else
{
int _eax, _ebx, _ecx, _edx, op = 0;
asm ("cpuid" : "=a" (_eax), "=b" (_ebx), "=c" (_ecx), "=d" (_edx) : "a" (op));
}
# endif
#endif #endif
} }