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Code copyrighted to Broadom Corporation is released under BSD 3-Clause License
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All other code released under GPLv2+
====================================
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Makefile Executable file
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TARGET_BOOTCODE = bootcode.bin
#
# when building bootcode.bin, always ensure start.s is at the top, providing
# the 0x200 byte long header and some init code.
#
SRCS = \
start.s \
romstage.c \
sdram.c \
arm_loader.c \
trap.c \
lib/xprintf.c \
lib/panic.c \
lib/udelay.c \
lib/memcpy.c \
chainloader_inc.s
ARCH = vc4
BUILD_DIR = build
TARGET_BUILD_DIR = $(BUILD_DIR)/$(ARCH)-objects
PRODUCT_DIRECTORY = $(BUILD_DIR)
NO_COLOR=""
OK_COLOR=""
ERROR_COLOR=""
WARN_COLOR=""
.PHONY: default all clean create_build_directory device
default: $(TARGET_BOOTCODE)
OBJ := $(addprefix $(TARGET_BUILD_DIR)/, $(addsuffix .o, $(basename $(SRCS))))
CROSS_COMPILE = /Developer/vc4-toolchain/prefix/bin/vc4-elf-
CC = $(CROSS_COMPILE)gcc
AS = $(CC)
OBJCOPY = $(CROSS_COMPILE)objcopy
LINKFLAGS = -nostdlib -nostartfiles
CFLAGS = -c -nostdlib -std=c11
ASFLAGS = -c -nostdlib -x assembler-with-cpp
HEADERS := \
$(shell find . -type f -name '*.h') \
$(shell find . -type f -name '*.hpp')
create_build_directory:
@mkdir -p $(TARGET_BUILD_DIR)
@mkdir -p $(PRODUCT_DIRECTORY)
CREATE_SUBDIR = \
@DIR="$(dir $@)"; \
if [ ! -d $$DIR ]; then mkdir -p $$DIR; fi
#
# rules to build c/asm files.
#
$(TARGET_BUILD_DIR)/%.o: %.c $(HEADERS)
$(CREATE_SUBDIR)
@echo $(WARN_COLOR)CC $(NO_COLOR) $@
@$(CC) $(CFLAGS) $< -o $@
$(TARGET_BUILD_DIR)/%.o: %.s $(HEADERS)
$(CREATE_SUBDIR)
@echo $(WARN_COLOR)AS $(NO_COLOR) $@
@$(AS) $(ASFLAGS) $< -o $@
.PRECIOUS: $(OBJ)
$(TARGET_BOOTCODE): create_build_directory $(OBJ)
@echo $(WARN_COLOR)LD $(NO_COLOR) $@.elf
@$(CC) $(LINKFLAGS) $(OBJ) -o $(PRODUCT_DIRECTORY)/$@.elf
@echo $(WARN_COLOR)OBJ$(NO_COLOR) $@
@$(OBJCOPY) -O binary $(PRODUCT_DIRECTORY)/$@.elf $(PRODUCT_DIRECTORY)/$@
clean:
@echo $(ERROR_COLOR)CLEAN$(NO_COLOR)
@-rm -rf ./$(BUILD_DIR)

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# Minimal Raspberry Pi VPU firmware
This is a small firmware for RPi VPU (VideoCore4) versions 1/2/3 that is capable of initializing UART, VPU PLL (PLLC) and ARM itself. It's intended to be used instead of stock `bootcode.bin` on RPi's SD card. You **need** to have UART to see anything meaningful as far as output goes.
This has been tested on RPi1 Model B (Hynix PoP DDR), RPi 2 Model B and RPi 3 Model B (both Elpida DDR).
If you want to contact me because you're interested in contributing, you can message `kristina` on Freenode, but I would suggest talking in `#raspberrypi-internals` instead.
## Building
You need Julian Brown's VC4 toolchain to build this (https://github.com/puppeh/vc4-toolchain) as well as a arm-none-eabi-toolchain. You can tweak the paths to it in CROSS_COMPILE in `Makefile` (for VC4) and for ARM in `arm_chainloader/Makefile`. After you've done it, run `buildall.sh` and you should have a blob in `build/bootcode.bin`.
## Technical Details
The firmware is split into two parts, a VC4 part and and ARM part. The VC4 part initializes PLLC and moves VPU over to it, and then brings up UART. It then performs SDRAM initialization, making SDRAM available at `0xC0000000` (uncached alias). The ARM loader will do ARM initialization and then copy the ARM bootloader that's embedded in it to the alias. It will then map it to `0x0` in ARM's memory space and start ARM. The code under `arm_chainloader` is what will run on the ARM.
The current makefiles in the ARM part of it aim at **RPi1** (ie. ARMv6) but they can be changed to ARMv7 if you want to build it for a newer model. I tested it on all RPi models and it works without any issues as far as I can tell (ARM can access peripherals and memory just fine as AXI supervisor).
**Beware:** This doesn't handle SMP at the moment so if you run this on RPi2 and above, all ARM cores will start executing the ARM bootloader code at the start which could cause problems. I will fix this soon.
## Issues
* PLL rate on ARM is slow, it's a bit annoying. Need to tweak the PLL rate later.
* Code that prints SDRAM capacity is a bit wrong, I need to fix it, but it makes no functional difference.
* At the moment the ARM side of the bootloader doesn't do anything aside from printing a line to UART. I'm going to add an SDHOST driver to load the next stage bootloader to it at some point.
* It only maps a small amount of memory at the moment. You can tweak it in `arm_loader.c` if you want.
## Does/Will it boot Linux?
Eventually maybe. Since `start.elf` is responsible for clock and power management (all registers in the `cpr` block), these drivers will have to be rewritten on ARM (or even on the open source VC4) to have any meaningful peripherals working properly (for example HDMI/DMA/Pixel Valve/Whatever). UART and GPIOs do work though.
## Thanks To
* **Herman Hermitage** for his VC4 documentation and for helping me with working out suitable ARM PLL configurations.
* **Julian Brown** for reviewing my code and for his awesome VC4 toolchain.
* **phire** for reviewing my code.
* **Broadcom** for their header release.
* Various other people not mentioned here.

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arm_chainloader/Makefile Executable file
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TARGET_ARM_CHAINLOADER = arm_chainloader.bin
SRCS = \
start.s \
drivers/uart.c \
../lib/xprintf.c \
firmware_rendezvous.c \
main.c
ARCH = armv6zk
BUILD_DIR = build
TARGET_BUILD_DIR = $(BUILD_DIR)/$(ARCH)-objects
PRODUCT_DIRECTORY = $(BUILD_DIR)
NO_COLOR=""
OK_COLOR=""
ERROR_COLOR=""
WARN_COLOR=""
.PHONY: default all clean create_build_directory device
default: $(TARGET_ARM_CHAINLOADER)
OBJ := $(addprefix $(TARGET_BUILD_DIR)/, $(addsuffix .o, $(basename $(SRCS))))
CROSS_COMPILE = arm-none-eabi-
CC = $(CROSS_COMPILE)gcc
AS = $(CC)
OBJCOPY = $(CROSS_COMPILE)objcopy
LINKFLAGS = -nostdlib -march=$(ARCH) -Wl,--build-id=none -T linker.lds
COMMON_FLAGS = -c -nostdlib -nostartfiles -ffreestanding -march=$(ARCH) -I../ -I./ -mfpu=vfp -mfloat-abi=hard -mtune=arm1176jzf-s
CFLAGS = $(COMMON_FLAGS) -std=c11
ASFLAGS = $(COMMON_FLAGS) -x assembler-with-cpp
HEADERS := \
$(shell find . -type f -name '*.h') \
$(shell find . -type f -name '*.hpp')
create_build_directory:
@mkdir -p $(TARGET_BUILD_DIR)
@mkdir -p $(PRODUCT_DIRECTORY)
CREATE_SUBDIR = \
@DIR="$(dir $@)"; \
if [ ! -d $$DIR ]; then mkdir -p $$DIR; fi
#
# rules to build c/asm files.
#
$(TARGET_BUILD_DIR)/%.o: %.c $(HEADERS)
$(CREATE_SUBDIR)
@echo $(WARN_COLOR)CC $(NO_COLOR) $@
@$(CC) $(CFLAGS) $< -o $@
$(TARGET_BUILD_DIR)/%.o: %.s $(HEADERS)
$(CREATE_SUBDIR)
@echo $(WARN_COLOR)AS $(NO_COLOR) $@
@$(AS) $(ASFLAGS) $< -o $@
.PRECIOUS: $(OBJ)
$(TARGET_ARM_CHAINLOADER): create_build_directory $(OBJ)
@echo $(WARN_COLOR)LD $(NO_COLOR) $@.elf
@$(CC) $(LINKFLAGS) $(OBJ) -o $(PRODUCT_DIRECTORY)/$@.elf -lgcc
@echo $(WARN_COLOR)OBJ$(NO_COLOR) $@
@$(OBJCOPY) -O binary $(PRODUCT_DIRECTORY)/$@.elf $(PRODUCT_DIRECTORY)/$@
clean:
@echo $(ERROR_COLOR)CLEAN$(NO_COLOR)
@-rm -rf ./$(BUILD_DIR)

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arm_chainloader/chainloader.h Executable file
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#pragma once
#include <lib/xprintf.h>
#define printf xprintf

10
arm_chainloader/drivers/uart.c Executable file
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#include <hardware.h>
void uart_putc(unsigned int ch)
{
while(1) {
if (mmio_read32(AUX_MU_LSR_REG) & 0x20)
break;
}
mmio_write32(AUX_MU_IO_REG, ch);
}

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arm_chainloader/firmware_rendezvous.c Executable file
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#include <stdint.h>
#include <hardware.h>
#include <chainloader.h>
extern void main();
extern void uart_putc(int c);
void _firmware_rendezvous() {
/* Channels to talk to the firmware */
volatile uint32_t* arm_membase = (volatile uint32_t*)0x0;
volatile uint32_t* comm1 = arm_membase + 8;
volatile uint32_t* comm2 = arm_membase + 9;
volatile uint32_t* comm3 = arm_membase + 10;
volatile uint32_t* comm4 = arm_membase + 11;
*comm1 = 0xCAFEEEEE;
/*
* check if we have peripheral access
* if so, we don't need the VPU anymore
*/
if (ARM_ID != ARM_IDVAL) {
*comm1 = 0xDEADCAFE;
return;
}
*comm4 = VPU_KILL_COMMAND;
/* stall for a bit to let the VPU commit suicide */
for (int i = 0; i < 0x10000; i++)
*comm2 = i;
main();
}

10
arm_chainloader/linker.lds Executable file
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MEMORY
{
ram : ORIGIN = 0x0, LENGTH = 0x100000
}
SECTIONS
{
.text : { *(.text*) } > ram
.bss : { *(.bss*) } > ram
}

7
arm_chainloader/main.c Executable file
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#include <stdint.h>
#include <chainloader.h>
#include <hardware.h>
void main() {
printf("%s: arm_chainloader started on ARM, continuing boot from here ...\n", __FUNCTION__);
}

24
arm_chainloader/start.s Executable file
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.text
.globl _start
_start:
/* vectors */
nop
nop
nop
nop
nop
nop
nop
nop
/* comm chan */
nop
nop
nop
nop
mov sp, #0x2000000
b _firmware_rendezvous
L_deadloop:
b L_deadloop

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arm_loader.c Executable file
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/*=============================================================================
Copyright (C) 2016 Kristina Brooks
All rights reserved.
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
FILE DESCRIPTION
ARM initialization stuff.
=============================================================================*/
#include "lib/common.h"
#include "hardware.h"
extern char L_arm_code_start;
extern char L_arm_code_end;
#define ARM_MEMORY_BASE 0xC0000000
#define ARM_BKPT_OPCODE 0xE1200070
/* XXX: What is this? */
#define PM_UNK_CFG_CLR 0xFFFCFFFF
static bool arm_power_wait_bit(uint32_t bit) {
for (int i = 0; i < 20; i++) {
if (PM_PROC & bit) {
return true;
}
udelay(100);
}
return false;
}
static inline void arm_assert_global_reset() {
printf("%s: RSTN ...\n", __FUNCTION__);
PM_PROC |= PM_PASSWORD | PM_PROC_ARMRSTN_SET;
udelay(300);
}
static void arm_enable_power() {
uint32_t pmv;
printf("%s: INIT PM_PROC: 0x%X\n", __FUNCTION__, PM_PROC);
printf("%s: requesting power up ...\n", __FUNCTION__);
/* deassert all reset lines */
pmv = ((PM_PROC & PM_PROC_ARMRSTN_CLR) & PM_UNK_CFG_CLR) | PM_PASSWORD;
PM_PROC = pmv;
pmv |= PM_PROC_POWUP_SET;
udelay(10);
PM_PROC = pmv;
printf("%s: POWUP PM_PROC: 0x%X\n", __FUNCTION__, PM_PROC);
/* wait for POWOK */
printf("%s: waiting for power up ...\n", __FUNCTION__);
for (int i = 1; i < 5; i++) {
if (!arm_power_wait_bit(PM_PROC_POWOK_SET)) {
/* only go up to 3 */
if (i == 4) {
panic("timed out waiting for power up, state of PM_PROC is: 0x%X", PM_PROC);
}
pmv = (pmv & PM_UNK_CFG_CLR) | (i << PM_PROC_CFG_LSB);
printf("%s: timed out, trying different CFG: 0x%X \n", __FUNCTION__, pmv);
PM_PROC = pmv;
}
}
pmv |= PM_PROC_ISPOW_SET;
PM_PROC = pmv;
pmv |= PM_PROC_MEMREP_SET;
PM_PROC = pmv;
printf("%s: waiting for MRDONE ...\n", __FUNCTION__);
if (!arm_power_wait_bit(PM_PROC_MRDONE_SET)) {
panic("timed out waiting for MRDONE, state of PM_PROC is: 0x%X", PM_PROC);
}
printf("%s: setting ISFUNC ...\n", __FUNCTION__);
pmv |= PM_PROC_ISFUNC_SET;
PM_PROC = pmv;
printf("%s: ARM power domain initialized succesfully, state of PM_PROC is: 0x%X!\n", __FUNCTION__, PM_PROC);
}
static void arm_bresp_cycle_write(uint32_t bits) {
ARM_CONTROL0 = (ARM_CONTROL0 & ~(ARM_C0_BRESP1|ARM_C0_BRESP2)) | bits;
printf("0x%X,", bits);
udelay(30);
}
static uint32_t g_BrespTab[] = {
0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x18, 0x0,
0x10, 0x14, 0x10, 0x1C, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0,
0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x10, 0x14, 0x18, 0x1C, 0x10, 0x14, 0x10, 0x0,
0x10, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0,
0x10, 0x14, 0x18, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x18, 0x0
};
static void arm_bresp_cycle() {
/* my little axi - peripherals are magic */
printf("Cycling AXI bits ...\n\t", __FUNCTION__);
for (int i = 0; i < sizeof(g_BrespTab)/sizeof(g_BrespTab[0]); i++) {
arm_bresp_cycle_write(g_BrespTab[i]);
if (i && ((i % 14) == 0))
printf("\n\t");
}
printf("\n");
}
void arm_setup_bridge(bool bresp_cycle) {
printf("%s: setting up async bridge ...\n", __FUNCTION__);
if (bresp_cycle) {
arm_assert_global_reset();
arm_bresp_cycle();
arm_assert_global_reset();
udelay(300);
}
ARM_CONTROL1 &= ~ARM_C1_REQSTOP;
udelay(300);
if (!bresp_cycle)
arm_assert_global_reset();
printf("%s: bridge init done, PM_PROC is now: 0x%X!\n", __FUNCTION__, PM_PROC);
}
static void arm_set_clock_source(unsigned int source) {
CM_ARMCTL = CM_PASSWORD | source | CM_ARMCTL_ENAB_SET;
}
static void arm_enable_clock() {
printf("%s: initializing PLLB ...\n", __FUNCTION__);
/* oscillator->pllb */
A2W_XOSC_CTRL |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLBEN_SET;
A2W_PLLB_FRAC = A2W_PASSWORD | 0xeaaa8;
A2W_PLLB_CTRL = A2W_PASSWORD | 48 | 0x1000;
CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET;
CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET;
A2W_PLLB_ANA3 = A2W_PASSWORD | 0x100;
A2W_PLLB_ANA2 = A2W_PASSWORD | 0x0;
A2W_PLLB_ANA1 = A2W_PASSWORD | 0x140000;
A2W_PLLB_ANA0 = A2W_PASSWORD | 0x0;
A2W_PLLB_DIG3 = A2W_PASSWORD | 0x0;
A2W_PLLB_DIG2 = A2W_PASSWORD | 0x400000;
A2W_PLLB_DIG1 = A2W_PASSWORD | 0x3a;
A2W_PLLB_DIG0 = A2W_PASSWORD | 48 | 0xAAA000;
A2W_PLLB_CTRL = A2W_PASSWORD | 48 | 0x21000;
A2W_PLLB_DIG3 = A2W_PASSWORD | 0x2;
A2W_PLLB_DIG2 = A2W_PASSWORD | 0x402401;
A2W_PLLB_DIG1 = A2W_PASSWORD | 0x403a;
A2W_PLLB_DIG0 = A2W_PASSWORD | 48 | 0xAAA000;
A2W_PLLB_ARM = A2W_PASSWORD | 2;
CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET | CM_PLLB_LOADARM_SET;
CM_PLLB = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET;
CM_PLLB = CM_PASSWORD;
arm_set_clock_source(4);
printf("KAIP = 0x%X\n", A2W_PLLB_ANA_KAIP);
printf("MULTI = 0x%X\n", A2W_PLLB_ANA_MULTI);
printf("%s: ARM clock succesfully initialized!\n", __FUNCTION__);
}
static void arm_load_code() {
uint32_t* mem = (uint32_t*)(ARM_MEMORY_BASE);
uint8_t* start = &L_arm_code_start;
uint8_t* end = &L_arm_code_end;
uint32_t size = (uint32_t)(end - start);
bcopy(start, mem, size);
printf("%s: copied %d bytes to 0x%X!\n", __FUNCTION__, size, ARM_MEMORY_BASE);
/* verify */
for (int i = 0; i < size; i++) {
uint8_t* mem8 = (uint8_t*)(mem);
if (start[i] != mem8[i])
panic("copy failed at 0x%X expected 0x%X, got 0x%X", (uint32_t)&mem8[i],
*((uint32_t*)&mem8[i]),
*((uint32_t*)&start[i]));
}
}
static void arm_pmap_enter(uint32_t bus_address, uint32_t arm_address) {
volatile uint32_t* tte = &ARM_TRANSLATE;
uint32_t index = arm_address >> 24;
uint32_t pte = bus_address >> 21;
tte[index] = pte;
printf("Translation: [0x%X => 0x%X] 0x%X => 0x%X\n", index * 4, bus_address >> 21, bus_address, arm_address);
}
/*
#define ARM_C0_PRIO_PER 0x00F00000 // per priority mask
#define ARM_C0_PRIO_L2 0x0F000000
#define ARM_C0_PRIO_UC 0xF0000000
*/
void arm_init() {
printf("ARM LOADER: build date %s %s\n", __DATE__, __TIME__);
printf("%s: starting ARM initialization!\n", __FUNCTION__);
arm_load_code();
printf("%s: original memstart: 0x%X\n", __FUNCTION__, *((volatile uint32_t*)ARM_MEMORY_BASE));
for (uint32_t i = 0; i < 6; i++) {
uint32_t offset = i * 0x1000000;
arm_pmap_enter(0xC0000000 + offset, 0x0 + offset);
}
arm_pmap_enter(VC4_PERIPH_BASE, ARM_PERIPH_BASE);
/* see if the ARM block is responding */
printf("%s: ARM ID: 0x%X C0: 0x%X\n", __FUNCTION__, ARM_ID, ARM_CONTROL0);
/*
* enable peripheral access, map arm secure bits to axi secure bits 1:1 and
* set the mem size for who knows what reason.
*/
ARM_CONTROL0 |= 0x000 | ARM_C0_APROTSYST | ARM_C0_SIZ1G | ARM_C0_FULLPERI;
printf("%s: using C0: 0x%X\n", __FUNCTION__, ARM_CONTROL0);
arm_enable_clock();
arm_enable_power();
/* start io bridge */
arm_setup_bridge(true);
printf("%s: polling ARM state ...\n", __FUNCTION__);
volatile uint32_t* arm_membase = (volatile uint32_t*)ARM_MEMORY_BASE;
/* skip vectors and get to comm chan */
arm_membase += 8;
for (;;/*int i = 0; i < 10; i++*/) {
if (arm_membase[3] == VPU_KILL_COMMAND) {
panic("ARM requested VPU halt, gooodbye VPU ...");
}
printf("0x%X 0x%X 0x%X 0x%X\n", arm_membase[0], arm_membase[1], arm_membase[2], arm_membase[3]);
udelay(5000);
}
}

29
bcm2708_chip/README.txt Executable file
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This dir contains all the register map files for the design
The bulk of it is created with the create_regs script (run create_regs) which
parses the *_regs files in the hdl dirs and creates the individual files
The top level file is chip/hdl/bcm2708_regs.tcl which defines the contents
and off sets of the chip level memory map.
Create regs then searches the dir tree for each object mentioned in bcm2708_regs.tcl
and locates its "object_regs.tcl" file
It then generates all the .h .inc ... files.
These are then all lumped together in a register_map.h register_map.inc etc file
The general procedure to modify this is
check out all of chip/verification/code/vcinclude
run create_regs in this dir
revert all unchanged files in vcinclude
check the modified ones and checkl them in if they are ok.
Note:
If create regs cant find a _regs.tcl file it will crash
If it finds two files with the same name it will crash

7
bcm2708_chip/apb_arbiter_control.h Executable file
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// This file was generated by the create_regs script
#define ACR_BASE 0x7e80a000
#define ACR_APB_ID 0x61726272
#define ACR_control HW_REGISTER_RW( 0x7e80a000 )
#define ACR_control_MASK 0x0000ffff
#define ACR_control_WIDTH 16
#define ACR_control_RESET 0000000000

245
bcm2708_chip/apb_async_bridge_ctrl.h Executable file
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// This file was generated by the create_regs script
#define ASB_BASE 0x7e00a000
#define ASB_APB_ID 0x62726467
#define ASB_AXI_BRDG_VERSION HW_REGISTER_RW( 0x7e00a000 )
#define ASB_AXI_BRDG_VERSION_MASK 0x000000ff
#define ASB_AXI_BRDG_VERSION_WIDTH 8
#define ASB_AXI_BRDG_VERSION_RESET 0000000000
#define ASB_CPR_CTRL HW_REGISTER_RW( 0x7e00a004 )
#define ASB_CPR_CTRL_MASK 0x00ffffff
#define ASB_CPR_CTRL_WIDTH 24
#define ASB_CPR_CTRL_RESET 0x00000007
#define ASB_CPR_CTRL_CLR_REQ_BITS 0:0
#define ASB_CPR_CTRL_CLR_REQ_SET 0x00000001
#define ASB_CPR_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_CPR_CTRL_CLR_REQ_MSB 0
#define ASB_CPR_CTRL_CLR_REQ_LSB 0
#define ASB_CPR_CTRL_CLR_ACK_BITS 1:1
#define ASB_CPR_CTRL_CLR_ACK_SET 0x00000002
#define ASB_CPR_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_CPR_CTRL_CLR_ACK_MSB 1
#define ASB_CPR_CTRL_CLR_ACK_LSB 1
#define ASB_CPR_CTRL_EMPTY_BITS 2:2
#define ASB_CPR_CTRL_EMPTY_SET 0x00000004
#define ASB_CPR_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_CPR_CTRL_EMPTY_MSB 2
#define ASB_CPR_CTRL_EMPTY_LSB 2
#define ASB_CPR_CTRL_FULL_BITS 3:3
#define ASB_CPR_CTRL_FULL_SET 0x00000008
#define ASB_CPR_CTRL_FULL_CLR 0xfffffff7
#define ASB_CPR_CTRL_FULL_MSB 3
#define ASB_CPR_CTRL_FULL_LSB 3
#define ASB_CPR_CTRL_RCOUNT_BITS 13:4
#define ASB_CPR_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_CPR_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_CPR_CTRL_RCOUNT_MSB 13
#define ASB_CPR_CTRL_RCOUNT_LSB 4
#define ASB_CPR_CTRL_WCOUNT_BITS 23:14
#define ASB_CPR_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_CPR_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_CPR_CTRL_WCOUNT_MSB 23
#define ASB_CPR_CTRL_WCOUNT_LSB 14
#define ASB_V3D_S_CTRL HW_REGISTER_RW( 0x7e00a008 )
#define ASB_V3D_S_CTRL_MASK 0x00ffffff
#define ASB_V3D_S_CTRL_WIDTH 24
#define ASB_V3D_S_CTRL_RESET 0x00000007
#define ASB_V3D_S_CTRL_CLR_REQ_BITS 0:0
#define ASB_V3D_S_CTRL_CLR_REQ_SET 0x00000001
#define ASB_V3D_S_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_V3D_S_CTRL_CLR_REQ_MSB 0
#define ASB_V3D_S_CTRL_CLR_REQ_LSB 0
#define ASB_V3D_S_CTRL_CLR_ACK_BITS 1:1
#define ASB_V3D_S_CTRL_CLR_ACK_SET 0x00000002
#define ASB_V3D_S_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_V3D_S_CTRL_CLR_ACK_MSB 1
#define ASB_V3D_S_CTRL_CLR_ACK_LSB 1
#define ASB_V3D_S_CTRL_EMPTY_BITS 2:2
#define ASB_V3D_S_CTRL_EMPTY_SET 0x00000004
#define ASB_V3D_S_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_V3D_S_CTRL_EMPTY_MSB 2
#define ASB_V3D_S_CTRL_EMPTY_LSB 2
#define ASB_V3D_S_CTRL_FULL_BITS 3:3
#define ASB_V3D_S_CTRL_FULL_SET 0x00000008
#define ASB_V3D_S_CTRL_FULL_CLR 0xfffffff7
#define ASB_V3D_S_CTRL_FULL_MSB 3
#define ASB_V3D_S_CTRL_FULL_LSB 3
#define ASB_V3D_S_CTRL_RCOUNT_BITS 13:4
#define ASB_V3D_S_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_V3D_S_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_V3D_S_CTRL_RCOUNT_MSB 13
#define ASB_V3D_S_CTRL_RCOUNT_LSB 4
#define ASB_V3D_S_CTRL_WCOUNT_BITS 23:14
#define ASB_V3D_S_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_V3D_S_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_V3D_S_CTRL_WCOUNT_MSB 23
#define ASB_V3D_S_CTRL_WCOUNT_LSB 14
#define ASB_V3D_M_CTRL HW_REGISTER_RW( 0x7e00a00c )
#define ASB_V3D_M_CTRL_MASK 0x00ffffff
#define ASB_V3D_M_CTRL_WIDTH 24
#define ASB_V3D_M_CTRL_RESET 0x00000007
#define ASB_V3D_M_CTRL_CLR_REQ_BITS 0:0
#define ASB_V3D_M_CTRL_CLR_REQ_SET 0x00000001
#define ASB_V3D_M_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_V3D_M_CTRL_CLR_REQ_MSB 0
#define ASB_V3D_M_CTRL_CLR_REQ_LSB 0
#define ASB_V3D_M_CTRL_CLR_ACK_BITS 1:1
#define ASB_V3D_M_CTRL_CLR_ACK_SET 0x00000002
#define ASB_V3D_M_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_V3D_M_CTRL_CLR_ACK_MSB 1
#define ASB_V3D_M_CTRL_CLR_ACK_LSB 1
#define ASB_V3D_M_CTRL_EMPTY_BITS 2:2
#define ASB_V3D_M_CTRL_EMPTY_SET 0x00000004
#define ASB_V3D_M_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_V3D_M_CTRL_EMPTY_MSB 2
#define ASB_V3D_M_CTRL_EMPTY_LSB 2
#define ASB_V3D_M_CTRL_FULL_BITS 3:3
#define ASB_V3D_M_CTRL_FULL_SET 0x00000008
#define ASB_V3D_M_CTRL_FULL_CLR 0xfffffff7
#define ASB_V3D_M_CTRL_FULL_MSB 3
#define ASB_V3D_M_CTRL_FULL_LSB 3
#define ASB_V3D_M_CTRL_RCOUNT_BITS 13:4
#define ASB_V3D_M_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_V3D_M_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_V3D_M_CTRL_RCOUNT_MSB 13
#define ASB_V3D_M_CTRL_RCOUNT_LSB 4
#define ASB_V3D_M_CTRL_WCOUNT_BITS 23:14
#define ASB_V3D_M_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_V3D_M_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_V3D_M_CTRL_WCOUNT_MSB 23
#define ASB_V3D_M_CTRL_WCOUNT_LSB 14
#define ASB_ISP_S_CTRL HW_REGISTER_RW( 0x7e00a010 )
#define ASB_ISP_S_CTRL_MASK 0x00ffffff
#define ASB_ISP_S_CTRL_WIDTH 24
#define ASB_ISP_S_CTRL_RESET 0x00000007
#define ASB_ISP_S_CTRL_CLR_REQ_BITS 0:0
#define ASB_ISP_S_CTRL_CLR_REQ_SET 0x00000001
#define ASB_ISP_S_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_ISP_S_CTRL_CLR_REQ_MSB 0
#define ASB_ISP_S_CTRL_CLR_REQ_LSB 0
#define ASB_ISP_S_CTRL_CLR_ACK_BITS 1:1
#define ASB_ISP_S_CTRL_CLR_ACK_SET 0x00000002
#define ASB_ISP_S_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_ISP_S_CTRL_CLR_ACK_MSB 1
#define ASB_ISP_S_CTRL_CLR_ACK_LSB 1
#define ASB_ISP_S_CTRL_EMPTY_BITS 2:2
#define ASB_ISP_S_CTRL_EMPTY_SET 0x00000004
#define ASB_ISP_S_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_ISP_S_CTRL_EMPTY_MSB 2
#define ASB_ISP_S_CTRL_EMPTY_LSB 2
#define ASB_ISP_S_CTRL_FULL_BITS 3:3
#define ASB_ISP_S_CTRL_FULL_SET 0x00000008
#define ASB_ISP_S_CTRL_FULL_CLR 0xfffffff7
#define ASB_ISP_S_CTRL_FULL_MSB 3
#define ASB_ISP_S_CTRL_FULL_LSB 3
#define ASB_ISP_S_CTRL_RCOUNT_BITS 13:4
#define ASB_ISP_S_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_ISP_S_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_ISP_S_CTRL_RCOUNT_MSB 13
#define ASB_ISP_S_CTRL_RCOUNT_LSB 4
#define ASB_ISP_S_CTRL_WCOUNT_BITS 23:14
#define ASB_ISP_S_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_ISP_S_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_ISP_S_CTRL_WCOUNT_MSB 23
#define ASB_ISP_S_CTRL_WCOUNT_LSB 14
#define ASB_ISP_M_CTRL HW_REGISTER_RW( 0x7e00a014 )
#define ASB_ISP_M_CTRL_MASK 0x00ffffff
#define ASB_ISP_M_CTRL_WIDTH 24
#define ASB_ISP_M_CTRL_RESET 0x00000007
#define ASB_ISP_M_CTRL_CLR_REQ_BITS 0:0
#define ASB_ISP_M_CTRL_CLR_REQ_SET 0x00000001
#define ASB_ISP_M_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_ISP_M_CTRL_CLR_REQ_MSB 0
#define ASB_ISP_M_CTRL_CLR_REQ_LSB 0
#define ASB_ISP_M_CTRL_CLR_ACK_BITS 1:1
#define ASB_ISP_M_CTRL_CLR_ACK_SET 0x00000002
#define ASB_ISP_M_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_ISP_M_CTRL_CLR_ACK_MSB 1
#define ASB_ISP_M_CTRL_CLR_ACK_LSB 1
#define ASB_ISP_M_CTRL_EMPTY_BITS 2:2
#define ASB_ISP_M_CTRL_EMPTY_SET 0x00000004
#define ASB_ISP_M_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_ISP_M_CTRL_EMPTY_MSB 2
#define ASB_ISP_M_CTRL_EMPTY_LSB 2
#define ASB_ISP_M_CTRL_FULL_BITS 3:3
#define ASB_ISP_M_CTRL_FULL_SET 0x00000008
#define ASB_ISP_M_CTRL_FULL_CLR 0xfffffff7
#define ASB_ISP_M_CTRL_FULL_MSB 3
#define ASB_ISP_M_CTRL_FULL_LSB 3
#define ASB_ISP_M_CTRL_RCOUNT_BITS 13:4
#define ASB_ISP_M_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_ISP_M_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_ISP_M_CTRL_RCOUNT_MSB 13
#define ASB_ISP_M_CTRL_RCOUNT_LSB 4
#define ASB_ISP_M_CTRL_WCOUNT_BITS 23:14
#define ASB_ISP_M_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_ISP_M_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_ISP_M_CTRL_WCOUNT_MSB 23
#define ASB_ISP_M_CTRL_WCOUNT_LSB 14
#define ASB_H264_S_CTRL HW_REGISTER_RW( 0x7e00a018 )
#define ASB_H264_S_CTRL_MASK 0x00ffffff
#define ASB_H264_S_CTRL_WIDTH 24
#define ASB_H264_S_CTRL_RESET 0x00000007
#define ASB_H264_S_CTRL_CLR_REQ_BITS 0:0
#define ASB_H264_S_CTRL_CLR_REQ_SET 0x00000001
#define ASB_H264_S_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_H264_S_CTRL_CLR_REQ_MSB 0
#define ASB_H264_S_CTRL_CLR_REQ_LSB 0
#define ASB_H264_S_CTRL_CLR_ACK_BITS 1:1
#define ASB_H264_S_CTRL_CLR_ACK_SET 0x00000002
#define ASB_H264_S_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_H264_S_CTRL_CLR_ACK_MSB 1
#define ASB_H264_S_CTRL_CLR_ACK_LSB 1
#define ASB_H264_S_CTRL_EMPTY_BITS 2:2
#define ASB_H264_S_CTRL_EMPTY_SET 0x00000004
#define ASB_H264_S_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_H264_S_CTRL_EMPTY_MSB 2
#define ASB_H264_S_CTRL_EMPTY_LSB 2
#define ASB_H264_S_CTRL_FULL_BITS 3:3
#define ASB_H264_S_CTRL_FULL_SET 0x00000008
#define ASB_H264_S_CTRL_FULL_CLR 0xfffffff7
#define ASB_H264_S_CTRL_FULL_MSB 3
#define ASB_H264_S_CTRL_FULL_LSB 3
#define ASB_H264_S_CTRL_RCOUNT_BITS 13:4
#define ASB_H264_S_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_H264_S_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_H264_S_CTRL_RCOUNT_MSB 13
#define ASB_H264_S_CTRL_RCOUNT_LSB 4
#define ASB_H264_S_CTRL_WCOUNT_BITS 23:14
#define ASB_H264_S_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_H264_S_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_H264_S_CTRL_WCOUNT_MSB 23
#define ASB_H264_S_CTRL_WCOUNT_LSB 14
#define ASB_H264_M_CTRL HW_REGISTER_RW( 0x7e00a01c )
#define ASB_H264_M_CTRL_MASK 0x00ffffff
#define ASB_H264_M_CTRL_WIDTH 24
#define ASB_H264_M_CTRL_RESET 0x00000007
#define ASB_H264_M_CTRL_CLR_REQ_BITS 0:0
#define ASB_H264_M_CTRL_CLR_REQ_SET 0x00000001
#define ASB_H264_M_CTRL_CLR_REQ_CLR 0xfffffffe
#define ASB_H264_M_CTRL_CLR_REQ_MSB 0
#define ASB_H264_M_CTRL_CLR_REQ_LSB 0
#define ASB_H264_M_CTRL_CLR_ACK_BITS 1:1
#define ASB_H264_M_CTRL_CLR_ACK_SET 0x00000002
#define ASB_H264_M_CTRL_CLR_ACK_CLR 0xfffffffd
#define ASB_H264_M_CTRL_CLR_ACK_MSB 1
#define ASB_H264_M_CTRL_CLR_ACK_LSB 1
#define ASB_H264_M_CTRL_EMPTY_BITS 2:2
#define ASB_H264_M_CTRL_EMPTY_SET 0x00000004
#define ASB_H264_M_CTRL_EMPTY_CLR 0xfffffffb
#define ASB_H264_M_CTRL_EMPTY_MSB 2
#define ASB_H264_M_CTRL_EMPTY_LSB 2
#define ASB_H264_M_CTRL_FULL_BITS 3:3
#define ASB_H264_M_CTRL_FULL_SET 0x00000008
#define ASB_H264_M_CTRL_FULL_CLR 0xfffffff7
#define ASB_H264_M_CTRL_FULL_MSB 3
#define ASB_H264_M_CTRL_FULL_LSB 3
#define ASB_H264_M_CTRL_RCOUNT_BITS 13:4
#define ASB_H264_M_CTRL_RCOUNT_SET 0x00003ff0
#define ASB_H264_M_CTRL_RCOUNT_CLR 0xffffc00f
#define ASB_H264_M_CTRL_RCOUNT_MSB 13
#define ASB_H264_M_CTRL_RCOUNT_LSB 4
#define ASB_H264_M_CTRL_WCOUNT_BITS 23:14
#define ASB_H264_M_CTRL_WCOUNT_SET 0x00ffc000
#define ASB_H264_M_CTRL_WCOUNT_CLR 0xff003fff
#define ASB_H264_M_CTRL_WCOUNT_MSB 23
#define ASB_H264_M_CTRL_WCOUNT_LSB 14

404
bcm2708_chip/arm_control.h Executable file
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//
// Definitions and addresses forthe ARM CONTROL logic
// This file is manually generated.
//
//
#define ARM_BASE 0x7E00B000
// Basic configuration
#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
#define ARM_C0_SIZ128M 0x00000000
#define ARM_C0_SIZ256M 0x00000001
#define ARM_C0_SIZ512M 0x00000002
#define ARM_C0_SIZ1G 0x00000003
#define ARM_C0_BRESP0 0x00000000
#define ARM_C0_BRESP1 0x00000004
#define ARM_C0_BRESP2 0x00000008
#define ARM_C0_BOOTHI 0x00000010
#define ARM_C0_UNUSED05 0x00000020 // free
#define ARM_C0_FULLPERI 0x00000040
#define ARM_C0_UNUSED78 0x00000180 // free
#define ARM_C0_JTAGMASK 0x00000E00
#define ARM_C0_JTAGOFF 0x00000000
#define ARM_C0_JTAGBASH 0x00000800 // Debug on GPIO off
#define ARM_C0_JTAGGPIO 0x00000C00 // Debug on GPIO on
#define ARM_C0_APROTMSK 0x0000F000
#define ARM_C0_DBG0SYNC 0x00010000 // VPU0 halt sync
#define ARM_C0_DBG1SYNC 0x00020000 // VPU1 halt sync
#define ARM_C0_SWDBGREQ 0x00040000 // HW debug request
#define ARM_C0_PASSHALT 0x00080000 // ARM halt passed to debugger
#define ARM_C0_PRIO_PER 0x00F00000 // per priority mask
#define ARM_C0_PRIO_L2 0x0F000000
#define ARM_C0_PRIO_UC 0xF0000000
#define ARM_C0_APROTPASS 0x0000A000 // Translate 1:1
#define ARM_C0_APROTUSER 0x00000000 // Only user mode
#define ARM_C0_APROTSYST 0x0000F000 // Only system mode
#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
#define ARM_C1_TIMER 0x00000001 // re-route timer IRQ to VC
#define ARM_C1_MAIL 0x00000002 // re-route Mail IRQ to VC
#define ARM_C1_BELL0 0x00000004 // re-route Doorbell 0 to VC
#define ARM_C1_BELL1 0x00000008 // re-route Doorbell 1 to VC
#define ARM_C1_PERSON 0x00000100 // peripherals on
#define ARM_C1_REQSTOP 0x00000200 // ASYNC bridge request stop
#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
#define ARM_S_ACKSTOP 0x80000000 // Bridge stopped
#define ARM_S_READPEND 0x000003FF // pending reads counter
#define ARM_S_WRITPEND 0x000FFC00 // pending writes counter
#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
#define ARM_EH_PERIBURST 0x00000001 // Burst write seen on peri bus
#define ARM_EH_ILLADDRS1 0x00000002 // Address bits 25-27 error
#define ARM_EH_ILLADDRS2 0x00000004 // Address bits 31-28 error
#define ARM_EH_VPU0HALT 0x00000008 // VPU0 halted & in debug mode
#define ARM_EH_VPU1HALT 0x00000010 // VPU1 halted & in debug mode
#define ARM_EH_ARMHALT 0x00000020 // ARM in halted debug mode
#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
#define ARM_IDVAL 0x364D5241
// Translation memory
#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
// 32 locations: 0x100.. 0x17F
// 32 spare means we CAN go to 64 pages....
// Interrupts
#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) // Top IRQ bits
#define ARM_I0_TIMER 0x00000001 // timer IRQ
#define ARM_I0_MAIL 0x00000002 // Mail IRQ
#define ARM_I0_BELL0 0x00000004 // Doorbell 0
#define ARM_I0_BELL1 0x00000008 // Doorbell 1
#define ARM_I0_BANK1 0x00000100 // Bank1 IRQ
#define ARM_I0_BANK2 0x00000200 // Bank2 IRQ
#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) // All bank1 IRQ bits
// todo: all I1_interrupt sources
#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) // All bank2 IRQ bits
// todo: all I2_interrupt sources
#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) // FIQ control
#define ARM_IF_INDEX 0x0000007F // FIQ select
#define ARM_IF_ENABLE 0x00000080 // FIQ enable
#define ARM_IF_VCMASK 0x0000003F // FIQ = (index from VC source)
#define ARM_IF_TIMER 0x00000040 // FIQ = ARM timer
#define ARM_IF_MAIL 0x00000041 // FIQ = ARM Mail
#define ARM_IF_BELL0 0x00000042 // FIQ = ARM Doorbell 0
#define ARM_IF_BELL1 0x00000043 // FIQ = ARM Doorbell 1
#define ARM_IF_VP0HALT 0x00000044 // FIQ = VPU0 Halt seen
#define ARM_IF_VP1HALT 0x00000045 // FIQ = VPU1 Halt seen
#define ARM_IF_ILLEGAL 0x00000046 // FIQ = Illegal access seen
#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) // Bank1 enable bits
#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) // Bank2 enable bits
#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) // ARM irqs enable bits
#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) // Bank1 disable bits
#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) // Bank2 disable bits
#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) // ARM irqs disable bits
#define ARM_IE_TIMER 0x00000001 // Timer IRQ
#define ARM_IE_MAIL 0x00000002 // Mail IRQ
#define ARM_IE_BELL0 0x00000004 // Doorbell 0
#define ARM_IE_BELL1 0x00000008 // Doorbell 1
#define ARM_IE_VP0HALT 0x00000010 // VPU0 Halt
#define ARM_IE_VP1HALT 0x00000020 // VPU1 Halt
#define ARM_IE_ILLEGAL 0x00000040 // Illegal access seen
// Timer
// For reg. fields see sp804 spec.
#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
#define TIMER_CTRL_ONESHOT (1 << 0)
#define TIMER_CTRL_32BIT (1 << 1)
#define TIMER_CTRL_DIV1 (0 << 2)
#define TIMER_CTRL_DIV16 (1 << 2)
#define TIMER_CTRL_DIV256 (2 << 2)
#define TIMER_CTRL_IE (1 << 5)
#define TIMER_CTRL_PERIODIC (1 << 6)
#define TIMER_CTRL_ENABLE (1 << 7)
#define TIMER_CTRL_DBGHALT (1 << 8)
#define TIMER_CTRL_ENAFREE (1 << 9)
#define TIMER_CTRL_FREEDIV_SHIFT 16)
#define TIMER_CTRL_FREEDIV_MASK 0xff
//
// Semaphores, Doorbells, Mailboxes
#define ARM_SBM_OWN0 (ARM_BASE+0x800)
#define ARM_SBM_OWN1 (ARM_BASE+0x900)
#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
//
// MAILBOXES
// Register flags are common across all
// owner registers. See end of this section
//=========================================
// Semaphores, Doorbells, Mailboxes Owner 0
//=========================================
#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
// MAILBOX 0 access in Owner 0 area
// Some addresses should ONLY be used by owner 0
#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) // .. 0x8C (4 locations)
#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) // .. 0x8C (4 locations) Normal read
#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) // none-pop read
#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) // Sender read (only LS 2 bits)
#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) // Status read
#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) // Config read/write
// MAILBOX 1 access in Owner 0 area
// Owner 0 should only WRITE to this mailbox
#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) // .. 0xAC (4 locations)
//#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) // DO NOT USE THIS !!!!!
//#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) // DO NOT USE THIS !!!!!
//#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) // DO NOT USE THIS !!!!!
#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) // Status read
//#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) // DO NOT USE THIS !!!!!
// General SEM, BELL, MAIL config/status
#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) // semaphore clear/debug register
#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) // Doorbells clear/debug register
#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) // ALL interrupts
#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) // IRQS pending for owner 0
// Semaphores, Doorbells, Mailboxes Owner 1
//=========================================
#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
// MAILBOX 0 access in Owner 0 area
// Owner 1 should only WRITE to this mailbox
#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) // .. 0x8C (4 locations)
//#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) // DO NOT USE THIS !!!!!
//#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) // DO NOT USE THIS !!!!!
//#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) // DO NOT USE THIS !!!!!
#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) // Status read
//#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) // DO NOT USE THIS !!!!!
// MAILBOX 1 access in Owner 0 area
#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) // .. 0xAC (4 locations)
#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) // .. 0xAC (4 locations) Normal read
#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) // none-pop read
#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) // Sender read (only LS 2 bits)
#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) // Status read
#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
// General SEM, BELL, MAIL config/status
#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) // semaphore clear/debug register
#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) // Doorbells clear/debug register
#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) // IRQS pending for owner 1
#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) // ALL interrupts
// Semaphores, Doorbells, Mailboxes Owner 2
//=========================================
#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
// MAILBOX 0 access in Owner 2 area
// Owner 2 should only WRITE to this mailbox
#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) // .. 0x8C (4 locations)
//#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) // DO NOT USE THIS !!!!!
//#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) // DO NOT USE THIS !!!!!
//#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) // DO NOT USE THIS !!!!!
#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) // Status read
//#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) // DO NOT USE THIS !!!!!
// MAILBOX 1 access in Owner 2 area
// Owner 2 should only WRITE to this mailbox
#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) // .. 0xAC (4 locations)
//#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) // DO NOT USE THIS !!!!!
//#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) // DO NOT USE THIS !!!!!
//#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) // DO NOT USE THIS !!!!!
#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) // Status read
//#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) // DO NOT USE THIS !!!!!
// General SEM, BELL, MAIL config/status
#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) // semaphore clear/debug register
#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) // Doorbells clear/debug register
#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) // IRQS pending for owner 2
#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) // ALL interrupts
// Semaphores, Doorbells, Mailboxes Owner 3
//=========================================
#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
// MAILBOX 0 access in Owner 3 area
// Owner 3 should only WRITE to this mailbox
#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) // .. 0x8C (4 locations)
//#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) // DO NOT USE THIS !!!!!
//#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) // DO NOT USE THIS !!!!!
//#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) // DO NOT USE THIS !!!!!
#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) // Status read
//#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) // DO NOT USE THIS !!!!!
// MAILBOX 1 access in Owner 3 area
// Owner 3 should only WRITE to this mailbox
#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) // .. 0xAC (4 locations)
//#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) // DO NOT USE THIS !!!!!
//#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) // DO NOT USE THIS !!!!!
//#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) // DO NOT USE THIS !!!!!
#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) // Status read
//#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) // DO NOT USE THIS !!!!!
// General SEM, BELL, MAIL config/status
#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) // semaphore clear/debug register
#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) // Doorbells clear/debug register
#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) // IRQS pending for owner 3
#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) // ALL interrupts
///////////////////////////////////////////
// MAILBOX FLAGS. VALID FOR ALL OWNERS //
///////////////////////////////////////////
// MAILBOX status register (...0x98)
#define ARM_MS_FULL 0x80000000
#define ARM_MS_EMPTY 0x40000000
#define ARM_MS_LEVEL 0x400000FF // Max. value depdnds on mailbox depth parameter
// MAILBOX config/status register (...0x9C)
// ANY write to this register clears the error bits!
#define ARM_MC_IHAVEDATAIRQEN 0x00000001 // mailbox irq enable: has data
#define ARM_MC_IHAVESPACEIRQEN 0x00000002 // mailbox irq enable: has space
#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 // mailbox irq enable: Opp. is empty
#define ARM_MC_MAIL_CLEAR 0x00000008 // mailbox clear write 1, then 0
#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 // mailbox irq pending: has space
#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 // mailbox irq pending: Opp. is empty
#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 // mailbox irq pending
// Bit 7 is unused
#define ARM_MC_ERRNOOWN 0x00000100 // error : none owner read from mailbox
#define ARM_MC_ERROVERFLW 0x00000200 // error : write to fill mailbox
#define ARM_MC_ERRUNDRFLW 0x00000400 // error : read from empty mailbox
// Semaphore clear/debug register (...0xE0)
#define ARM_SD_OWN0 0x00000003 // Owner of sem 0
#define ARM_SD_OWN1 0x0000000C // Owner of sem 1
#define ARM_SD_OWN2 0x00000030 // Owner of sem 2
#define ARM_SD_OWN3 0x000000C0 // Owner of sem 3
#define ARM_SD_OWN4 0x00000300 // Owner of sem 4
#define ARM_SD_OWN5 0x00000C00 // Owner of sem 5
#define ARM_SD_OWN6 0x00003000 // Owner of sem 6
#define ARM_SD_OWN7 0x0000C000 // Owner of sem 7
#define ARM_SD_SEM0 0x00010000 // Status of sem 0
#define ARM_SD_SEM1 0x00020000 // Status of sem 1
#define ARM_SD_SEM2 0x00040000 // Status of sem 2
#define ARM_SD_SEM3 0x00080000 // Status of sem 3
#define ARM_SD_SEM4 0x00100000 // Status of sem 4
#define ARM_SD_SEM5 0x00200000 // Status of sem 5
#define ARM_SD_SEM6 0x00400000 // Status of sem 6
#define ARM_SD_SEM7 0x00800000 // Status of sem 7
// Doorbell status registers (...0x40-4C)
#define ARM_DS_ACTIVE 0x00000004 // Doorbell rung since last read?
#define ARM_DS_OWNER 0x00000003 // Owner
// Doorbells clear/debug register (...0xE4)
#define ARM_BD_OWN0 0x00000003 // Owner of doorbell 0
#define ARM_BD_OWN1 0x0000000C // Owner of doorbell 1
#define ARM_BD_OWN2 0x00000030 // Owner of doorbell 2
#define ARM_BD_OWN3 0x000000C0 // Owner of doorbell 3
#define ARM_BD_BELL0 0x00000100 // Status of doorbell 0
#define ARM_BD_BELL1 0x00000200 // Status of doorbell 1
#define ARM_BD_BELL2 0x00000400 // Status of doorbell 2
#define ARM_BD_BELL3 0x00000800 // Status of doorbell 3
// MY IRQS register (...0xF8)
#define ARM_MYIRQ_BELL 0x00000001 // This owner has a doorbell IRQ
#define ARM_MYIRQ_MAIL 0x00000002 // This owner has a mailbox IRQ
// ALL IRQS register (...0xF8)
#define ARM_AIS_BELL0 0x00000001 // Doorbell 0 IRQ pending
#define ARM_AIS_BELL1 0x00000002 // Doorbell 1 IRQ pending
#define ARM_AIS_BELL2 0x00000004 // Doorbell 2 IRQ pending
#define ARM_AIS_BELL3 0x00000008 // Doorbell 3 IRQ pending
#define ARM_AIS0_HAVEDATA 0x00000010 // MAIL 0 has data IRQ pending
#define ARM_AIS0_HAVESPAC 0x00000020 // MAIL 0 has space IRQ pending
#define ARM_AIS0_OPPEMPTY 0x00000040 // MAIL 0 opposite is empty IRQ
#define ARM_AIS1_HAVEDATA 0x00000080 // MAIL 1 has data IRQ pending
#define ARM_AIS1_HAVESPAC 0x00000100 // MAIL 1 has space IRQ pending
#define ARM_AIS1_OPPEMPTY 0x00000200 // MAIL 1 opposite is empty IRQ
// Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM
// Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC
//
// ARM JTAG BASH
//
#define AJB_BASE 0x7e2000c0
#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
#define AJB_BITS0 0x000000
#define AJB_BITS4 0x000004
#define AJB_BITS8 0x000008
#define AJB_BITS12 0x00000C
#define AJB_BITS16 0x000010
#define AJB_BITS20 0x000014
#define AJB_BITS24 0x000018
#define AJB_BITS28 0x00001C
#define AJB_BITS32 0x000020
#define AJB_BITS34 0x000022
#define AJB_OUT_MS 0x000040
#define AJB_OUT_LS 0x000000
#define AJB_INV_CLK 0x000080
#define AJB_D0_RISE 0x000100
#define AJB_D0_FALL 0x000000
#define AJB_D1_RISE 0x000200
#define AJB_D1_FALL 0x000000
#define AJB_IN_RISE 0x000400
#define AJB_IN_FALL 0x000000
#define AJB_ENABLE 0x000800
#define AJB_HOLD0 0x000000
#define AJB_HOLD1 0x001000
#define AJB_HOLD2 0x002000
#define AJB_HOLD3 0x003000
#define AJB_RESETN 0x004000
#define AJB_CLKSHFT 16
#define AJB_BUSY 0x80000000
#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)

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bcm2708_chip/aux_io.h Executable file
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//
// Auxiliary I/O header file
//
#define AUX_IO_BASE 0x7E215000
#define AUX_IRQ (AUX_IO_BASE+0x000)
#define AUX_ENABLES (AUX_IO_BASE+0x004)
#define AUX_ENABLE_MINIUART 0x01
#define AUX_ENABLE_SPI0 0x02
#define AUX_ENABLE_SPI1 0x04
//
// Micro UART
//
// Baud rate = sysclk/(8*(BAUD_REG+1))
#define AUX_MU_IO_REG (AUX_IO_BASE+0x040) // Write=TX read=RX
#define AUX_MU_BDLS_REG (AUX_IO_BASE+0x040) // Baudrate LS
#define AUX_MU_BDMS_REG (AUX_IO_BASE+0x044) // Baudrate MS.
#define AUX_MU_IER_REG (AUX_IO_BASE+0x044) // IRQ enbl. reg.
#define AUX_MU_IER_RXIRQEN 0x01 //
#define AUX_MU_IER_TXIRQEN 0x02 //
// Line interrupts are not supported
#define AUX_MU_IIR_REG (AUX_IO_BASE+0x048) // IRQ status reg
#define AUX_MU_IIR_NOIRQS 0x01 // No irq pending
#define AUX_MU_IIR_IRQ 0x06 // 10 = rec irq, 01 = tx irq
// Timeout is not supported
#define AUX_MU_FCR_REG (AUX_IO_BASE+0x048) // FIFO control reg
#define AUX_MU_FCR_RXCLR 0x02 // Flush receive FF
#define AUX_MU_FCR_TXCLR 0x04 // Flush transmit fifo
#define AUX_MU_LCR_REG (AUX_IO_BASE+0x04C) // Line control reg.
#define AUX_MU_LCR_7BITS 0x02 // 7 bits mode
#define AUX_MU_LCR_8BITS 0x03 // 8 bits mode
#define AUX_MU_LCR_BREAK 0x40 // send break
#define AUX_MU_LCR_DLAB 0x80 // DLAB access
// 5 & 6 bits are not supported
// 2 stop bits are not supported
// Parity bits are not supported
#define AUX_MU_MCR_REG (AUX_IO_BASE+0x050) // Modem control reg.
#define AUX_MU_MCR_RTS 0x02 // Set RTS high
// DTR is not supported
// Out1/2 are not supported
// Loopback is not supported
#define AUX_MU_LSR_REG (AUX_IO_BASE+0x054) // Line status reg.
#define AUX_MU_LSR_DR 0x01 // Receive Data ready
#define AUX_MU_LSR_OE 0x02 // Receiver overrun error
#define AUX_MU_LSR_THRE 0x20 // Transmitter holding register
#define AUX_MU_LSR_TEMT 0x40 // Transmitter empty
// Parity bits (and thus errors) are not supported
// Framing errors are not detected
// Break detect is not (yet) supported
#define AUX_MU_MSR_REG (AUX_IO_BASE+0x058) // Modem status reg.
#define AUX_MU_MSR_CTS 0x10
// Delta CTS not supported
// DCE,DCD not supportred
#define AUX_MU_SCRATCH (AUX_IO_BASE+0x05C) // Scratch reg.
// None 16550 features
#define AUX_MU_CNTL_REG (AUX_IO_BASE+0x060) // AUX control reg.
#define AUX_MU_CNTL_REC_ENBL 0x01 // receiver enable
#define AUX_MU_CNTL_TRN_ENBL 0x02 // transmitter enable
#define AUX_MU_CNTL_AUTO_RTR 0x04 // RTR set by RX FF level
#define AUX_MU_CNTL_AUTO_CTS 0x08 // CTS auto stops transmitter
#define AUX_MU_CNTL_FLOW3 0x00 // Stop on RX FF 3 entries left
#define AUX_MU_CNTL_FLOW2 0x10 // Stop on RX FF 2 entries left
#define AUX_MU_CNTL_FLOW1 0x20 // Stop on RX FF 1 entries left
#define AUX_MU_CNTL_FLOW4 0x30 // Stop on RX FF 4 entries left
#define AUX_MU_CNTL_AURTRINV 0x40 // Invert AUTO RTR polarity
#define AUX_MU_CNTL_AUCTSINV 0x80 // Invert AUTO CTS polarity
#define AUX_MU_STAT_REG (AUX_IO_BASE+0x064) // AUX status reg.
#define AUX_MU_STAT_RX_DATA 0x00000001 // RX FF has value
#define AUX_MU_STAT_TX_SPACE 0x00000002 // TX FF has space (not full)
#define AUX_MU_STAT_RX_IDLE 0x00000004 // Receiver is idle
#define AUX_MU_STAT_TX_IDLE 0x00000008 // Transmitter is idle
#define AUX_MU_STAT_RX_OFLW 0x00000010 // Receiver FF overflow error
#define AUX_MU_STAT_TX_FULL 0x00000020 // Transmit FF full
#define AUX_MU_STAT_RTR 0x00000040 // Status of the RTR line
#define AUX_MU_STAT_CTS 0x00000080 // Status of the CTS line (fully synced)
#define AUX_MU_STAT_TXEMPTY 0x00000100 // TX FF is empty
#define AUX_MU_STAT_TXDONE 0x00000200 // TX FF is empty and TX is idle
#define AUX_MU_STAT_RXFILL 0x00FF0000 // RX FF fill level
#define AUX_MU_STAT_TXFILL 0xFF000000 // TX FF fill level
#define AUX_MU_BAUD_REG (AUX_IO_BASE+0x068) // Baudrate reg (16 bits)
// Baud rate = sysclk/(8*(BAUD_REG+1))
//
// SPI 0 (SPI1 in the device!)
//
#define AUX_SPI0_CNTL0_REG (AUX_IO_BASE+0x080) // control reg 0
#define AUX_SPI_CNTL0_BITS 0x0000003F // Number of bits to send/receive
#define AUX_SPI_CNTL0_OUTMS 0x00000040 // Shift MS bit out first)
#define AUX_SPI_CNTL0_INVCLK 0x00000080 // Invert SPI_CLK
#define AUX_SPI_CNTL0_OUTRISE 0x00000100 // data out leaves on rising clock edge
#define AUX_SPI_CNTL0_OUTFALL 0x00000000 // data out leaves on falling clock edge
#define AUX_SPI_CNTL0_FFCLR 0x00000200 // Reset fifos (Set and clear bit)
#define AUX_SPI_CNTL0_INRISE 0x00000400 // data in on rising clock edge
#define AUX_SPI_CNTL0_INFALL 0x00000000 // data in on falling clock edge
#define AUX_SPI_CNTL0_SERENBL 0x00000800 // Serial enable (does not disable FFs)
#define AUX_SPI_CNTL0_HOLD0 0x00000000 // Dout hold 0 sys clock cycles
#define AUX_SPI_CNTL0_HOLD4 0x00001000 // Dout hold 4 sys clock cycle
#define AUX_SPI_CNTL0_HOLD7 0x00002000 // Dout hold 7 sys clock cycles
#define AUX_SPI_CNTL0_HOLD10 0x00003000 // Dout hold 10 sys clock cycles
#define AUX_SPI_CNTL0_VARWID 0x00004000 // Variable width mode (din[15-12]=bits)
#define AUX_SPI_CNTL0_CSFROMFF 0x00008000 // CS pattern comesfrom MS 3 TX FIFO bits
#define AUX_SPI_CNTL0_POSTIN 0x00010000 // Load last bit after cycles finished
#define AUX_SPI_CNTL0_CS_HIGH 0x000E0000 // All CS are high
#define AUX_SPI_CNTL0_CS0_N 0x000C0000 // CS 0 low
#define AUX_SPI_CNTL0_CS1_N 0x000A0000 // CS 1 low
#define AUX_SPI_CNTL0_CS2_N 0x00060000 // CS 2 low
#define AUX_SPI_CNTL0_CSA_N 0x00000000 // ALL CS low (test only)
#define AUX_SPI_CNTL0_SPEED 0xFFF00000 // SPI clock = sysclock/(2xspeed)
#define AUX_SPI_CNTL0_SPEEDSHFT 20 // Speed shift left value
#define AUX_SPI0_CNTL1_REG (AUX_IO_BASE+0x084) // control reg 1
#define AUX_SPI_CNTL1_HOLDIN 0x00000001 // Do not clear DIN register at start
#define AUX_SPI_CNTL1_INMS 0x00000002 // Shift data in MS first MS--->LS
//#define AUX_SPI_CNTL1_CS_NOW 0x00000004 // Assert CS pattern now
#define AUX_SPI_CNTL1_EMPTYIRQ 0x00000040 // IRQ on TX Fifo empty
#define AUX_SPI_CNTL1_DONEIRQ 0x00000080 // IRQ on IDLE AND TxFifo empty
#define AUX_SPI_CNTL1_CSPLUS1 0x00000100 // CS HI plus 1 bit
#define AUX_SPI_CNTL1_CSPLUS2 0x00000200 // CS HI plus 2 bit
#define AUX_SPI_CNTL1_CSPLUS3 0x00000300 // CS HI plus 3 bit
#define AUX_SPI_CNTL1_CSPLUS4 0x00000400 // CS HI plus 4 bit
#define AUX_SPI_CNTL1_CSPLUS5 0x00000500 // CS HI plus 5 bit
#define AUX_SPI_CNTL1_CSPLUS6 0x00000600 // CS HI plus 6 bit
#define AUX_SPI_CNTL1_CSPLUS7 0x00000700 // CS HI plus 7 bit
#define AUX_SPI0_STAT_REG (AUX_IO_BASE+0x088) // Status reg.
#define AUX_SPI_STAT_BITCNT 0x0000003F // Bits remaining to be shifted out
#define AUX_SPI_STAT_BUSY 0x00000040 // FSM is busy
#define AUX_SPI_STAT_RXEMPTY 0x00000080 // RX FF is empty
#define AUX_SPI_STAT_RXFULL 0x00000100 // RX FF is full
#define AUX_SPI_STAT_TXEMPTY 0x00000200 // TX FF is empyt
#define AUX_SPI_STAT_TXFULL 0x00000400 // TX FF is full
#define AUX_SPI_STAT_RXFILL 0x000F0000 // RX FF fill level
#define AUX_SPI_STAT_TXFILL 0x0F000000 // TX FF fill level
#define AUX_SPI0_PEEK_REG (AUX_IO_BASE+0x08C) // Read but do not take from FF
#define AUX_SPI0_IO_REG (AUX_IO_BASE+0x0A0) // Write = TX, read=RX
#define AUX_SPI0_TXHOLD_REG (AUX_IO_BASE+0x0B0) // Write = TX keep cs, read=RX
//
// SPI 1 (SPI2 in the device!)
//
#define AUX_SPI1_CNTL0_REG (AUX_IO_BASE+0x0C0)
#define AUX_SPI1_CNTL1_REG (AUX_IO_BASE+0x0C4)
#define AUX_SPI1_STAT_REG (AUX_IO_BASE+0x0C8)
#define AUX_SPI1_PEEK_REG (AUX_IO_BASE+0x0CC)
#define AUX_SPI1_IO_REG (AUX_IO_BASE+0x0E0)
#define AUX_SPI1_TXHOLD_REG (AUX_IO_BASE+0x0F0) // Write = TX keep cs, read=RX
//
// Some usefull GPIO macros
//
#define CLR_GPIO(g) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))&= ~(7<<(((g)%10)*3))
#define SET_GPIO_ALT(g,a) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))|= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))

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bcm2708_chip/ave_in.h Executable file
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// This file was generated by the create_regs script
#define AVE_IN_BASE 0x7e910000
#define AVE_IN_APB_ID 0x61766530
#define AVE_IN_CTRL HW_REGISTER_RW( 0x7e910000 )
#define AVE_IN_CTRL_MASK 0x87ffffff
#define AVE_IN_CTRL_WIDTH 32
#define AVE_IN_CTRL_RESET 0x08000080
#define AVE_IN_CTRL_ENABLE_BITS 31:31
#define AVE_IN_CTRL_ENABLE_SET 0x80000000
#define AVE_IN_CTRL_ENABLE_CLR 0x7fffffff
#define AVE_IN_CTRL_ENABLE_MSB 31
#define AVE_IN_CTRL_ENABLE_LSB 31
#define AVE_IN_CTRL_PRIORITY_LIMIT_BITS 26:24
#define AVE_IN_CTRL_PRIORITY_LIMIT_SET 0x07000000
#define AVE_IN_CTRL_PRIORITY_LIMIT_CLR 0xf8ffffff
#define AVE_IN_CTRL_PRIORITY_LIMIT_MSB 26
#define AVE_IN_CTRL_PRIORITY_LIMIT_LSB 24
#define AVE_IN_CTRL_HIGH_PRIORITY_BITS 23:20
#define AVE_IN_CTRL_HIGH_PRIORITY_SET 0x00f00000
#define AVE_IN_CTRL_HIGH_PRIORITY_CLR 0xff0fffff
#define AVE_IN_CTRL_HIGH_PRIORITY_MSB 23
#define AVE_IN_CTRL_HIGH_PRIORITY_LSB 20
#define AVE_IN_CTRL_LOW_PRIORITY_BITS 19:16
#define AVE_IN_CTRL_LOW_PRIORITY_SET 0x000f0000
#define AVE_IN_CTRL_LOW_PRIORITY_CLR 0xfff0ffff
#define AVE_IN_CTRL_LOW_PRIORITY_MSB 19
#define AVE_IN_CTRL_LOW_PRIORITY_LSB 16
#define AVE_IN_CTRL_EN_OVERRUN_ABORT_BITS 15:15
#define AVE_IN_CTRL_EN_OVERRUN_ABORT_SET 0x00008000
#define AVE_IN_CTRL_EN_OVERRUN_ABORT_CLR 0xffff7fff
#define AVE_IN_CTRL_EN_OVERRUN_ABORT_MSB 15
#define AVE_IN_CTRL_EN_OVERRUN_ABORT_LSB 15
#define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_BITS 14:14
#define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_SET 0x00004000
#define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_CLR 0xffffbfff
#define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_MSB 14
#define AVE_IN_CTRL_EN_TRANSFER_MAX_ABORT_LSB 14
#define AVE_IN_CTRL_BYTE_ORDER_BITS 13:11
#define AVE_IN_CTRL_BYTE_ORDER_SET 0x00003800
#define AVE_IN_CTRL_BYTE_ORDER_CLR 0xffffc7ff
#define AVE_IN_CTRL_BYTE_ORDER_MSB 13
#define AVE_IN_CTRL_BYTE_ORDER_LSB 11
#define AVE_IN_CTRL_FRAME_MODE_BITS 10:9
#define AVE_IN_CTRL_FRAME_MODE_SET 0x00000600
#define AVE_IN_CTRL_FRAME_MODE_CLR 0xfffff9ff
#define AVE_IN_CTRL_FRAME_MODE_MSB 10
#define AVE_IN_CTRL_FRAME_MODE_LSB 9
#define AVE_IN_CTRL_LENGTH_IN_PXLS_BITS 8:8
#define AVE_IN_CTRL_LENGTH_IN_PXLS_SET 0x00000100
#define AVE_IN_CTRL_LENGTH_IN_PXLS_CLR 0xfffffeff
#define AVE_IN_CTRL_LENGTH_IN_PXLS_MSB 8
#define AVE_IN_CTRL_LENGTH_IN_PXLS_LSB 8
#define AVE_IN_CTRL_PRIV_MODE_BITS 7:7
#define AVE_IN_CTRL_PRIV_MODE_SET 0x00000080
#define AVE_IN_CTRL_PRIV_MODE_CLR 0xffffff7f
#define AVE_IN_CTRL_PRIV_MODE_MSB 7
#define AVE_IN_CTRL_PRIV_MODE_LSB 7
#define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_BITS 6:6
#define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_SET 0x00000040
#define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_CLR 0xffffffbf
#define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_MSB 6
#define AVE_IN_CTRL_FRAME_RATE_IRQ_EN_LSB 6
#define AVE_IN_CTRL_HSYNC_IRQ_EN_BITS 5:5
#define AVE_IN_CTRL_HSYNC_IRQ_EN_SET 0x00000020
#define AVE_IN_CTRL_HSYNC_IRQ_EN_CLR 0xffffffdf
#define AVE_IN_CTRL_HSYNC_IRQ_EN_MSB 5
#define AVE_IN_CTRL_HSYNC_IRQ_EN_LSB 5
#define AVE_IN_CTRL_LINE_IRQ_EN_BITS 4:4
#define AVE_IN_CTRL_LINE_IRQ_EN_SET 0x00000010
#define AVE_IN_CTRL_LINE_IRQ_EN_CLR 0xffffffef
#define AVE_IN_CTRL_LINE_IRQ_EN_MSB 4
#define AVE_IN_CTRL_LINE_IRQ_EN_LSB 4
#define AVE_IN_CTRL_BUF_SER_IRQ_EN_BITS 3:3
#define AVE_IN_CTRL_BUF_SER_IRQ_EN_SET 0x00000008
#define AVE_IN_CTRL_BUF_SER_IRQ_EN_CLR 0xfffffff7
#define AVE_IN_CTRL_BUF_SER_IRQ_EN_MSB 3
#define AVE_IN_CTRL_BUF_SER_IRQ_EN_LSB 3
#define AVE_IN_CTRL_BUF1_IRQ_EN_BITS 2:2
#define AVE_IN_CTRL_BUF1_IRQ_EN_SET 0x00000004
#define AVE_IN_CTRL_BUF1_IRQ_EN_CLR 0xfffffffb
#define AVE_IN_CTRL_BUF1_IRQ_EN_MSB 2
#define AVE_IN_CTRL_BUF1_IRQ_EN_LSB 2
#define AVE_IN_CTRL_BUF0_IRQ_EN_BITS 1:1
#define AVE_IN_CTRL_BUF0_IRQ_EN_SET 0x00000002
#define AVE_IN_CTRL_BUF0_IRQ_EN_CLR 0xfffffffd
#define AVE_IN_CTRL_BUF0_IRQ_EN_MSB 1
#define AVE_IN_CTRL_BUF0_IRQ_EN_LSB 1
#define AVE_IN_CTRL_OVERRUN_IRQ_EN_BITS 0:0
#define AVE_IN_CTRL_OVERRUN_IRQ_EN_SET 0x00000001
#define AVE_IN_CTRL_OVERRUN_IRQ_EN_CLR 0xfffffffe
#define AVE_IN_CTRL_OVERRUN_IRQ_EN_MSB 0
#define AVE_IN_CTRL_OVERRUN_IRQ_EN_LSB 0
#define AVE_IN_STATUS HW_REGISTER_RW( 0x7e910004 )
#define AVE_IN_STATUS_MASK 0x9f733f7f
#define AVE_IN_STATUS_WIDTH 32
#define AVE_IN_STATUS_RESET 0000000000
#define AVE_IN_STATUS_CAPTURING_BITS 31:31
#define AVE_IN_STATUS_CAPTURING_SET 0x80000000
#define AVE_IN_STATUS_CAPTURING_CLR 0x7fffffff
#define AVE_IN_STATUS_CAPTURING_MSB 31
#define AVE_IN_STATUS_CAPTURING_LSB 31
#define AVE_IN_STATUS_OVERRUN_CNT_BITS 28:24
#define AVE_IN_STATUS_OVERRUN_CNT_SET 0x1f000000
#define AVE_IN_STATUS_OVERRUN_CNT_CLR 0xe0ffffff
#define AVE_IN_STATUS_OVERRUN_CNT_MSB 28
#define AVE_IN_STATUS_OVERRUN_CNT_LSB 24
#define AVE_IN_STATUS_AXI_STATE_BITS 22:20
#define AVE_IN_STATUS_AXI_STATE_SET 0x00700000
#define AVE_IN_STATUS_AXI_STATE_CLR 0xff8fffff
#define AVE_IN_STATUS_AXI_STATE_MSB 22
#define AVE_IN_STATUS_AXI_STATE_LSB 20
#define AVE_IN_STATUS_CURRENT_BUF_BITS 17:17
#define AVE_IN_STATUS_CURRENT_BUF_SET 0x00020000
#define AVE_IN_STATUS_CURRENT_BUF_CLR 0xfffdffff
#define AVE_IN_STATUS_CURRENT_BUF_MSB 17
#define AVE_IN_STATUS_CURRENT_BUF_LSB 17
#define AVE_IN_STATUS_MAX_HIT_BITS 16:16
#define AVE_IN_STATUS_MAX_HIT_SET 0x00010000
#define AVE_IN_STATUS_MAX_HIT_CLR 0xfffeffff
#define AVE_IN_STATUS_MAX_HIT_MSB 16
#define AVE_IN_STATUS_MAX_HIT_LSB 16
#define AVE_IN_STATUS_CSYNC_FIELD_BITS 13:13
#define AVE_IN_STATUS_CSYNC_FIELD_SET 0x00002000
#define AVE_IN_STATUS_CSYNC_FIELD_CLR 0xffffdfff
#define AVE_IN_STATUS_CSYNC_FIELD_MSB 13
#define AVE_IN_STATUS_CSYNC_FIELD_LSB 13
#define AVE_IN_STATUS_VFORM_FIELD_BITS 12:12
#define AVE_IN_STATUS_VFORM_FIELD_SET 0x00001000
#define AVE_IN_STATUS_VFORM_FIELD_CLR 0xffffefff
#define AVE_IN_STATUS_VFORM_FIELD_MSB 12
#define AVE_IN_STATUS_VFORM_FIELD_LSB 12
#define AVE_IN_STATUS_EVEN_FIELD_BITS 11:11
#define AVE_IN_STATUS_EVEN_FIELD_SET 0x00000800
#define AVE_IN_STATUS_EVEN_FIELD_CLR 0xfffff7ff
#define AVE_IN_STATUS_EVEN_FIELD_MSB 11
#define AVE_IN_STATUS_EVEN_FIELD_LSB 11
#define AVE_IN_STATUS_INTERLACED_BITS 10:10
#define AVE_IN_STATUS_INTERLACED_SET 0x00000400
#define AVE_IN_STATUS_INTERLACED_CLR 0xfffffbff
#define AVE_IN_STATUS_INTERLACED_MSB 10
#define AVE_IN_STATUS_INTERLACED_LSB 10
#define AVE_IN_STATUS_FRAME_RATE_BITS 9:8
#define AVE_IN_STATUS_FRAME_RATE_SET 0x00000300
#define AVE_IN_STATUS_FRAME_RATE_CLR 0xfffffcff
#define AVE_IN_STATUS_FRAME_RATE_MSB 9
#define AVE_IN_STATUS_FRAME_RATE_LSB 8
#define AVE_IN_STATUS_FRAME_RATE_DET_BITS 6:6
#define AVE_IN_STATUS_FRAME_RATE_DET_SET 0x00000040
#define AVE_IN_STATUS_FRAME_RATE_DET_CLR 0xffffffbf
#define AVE_IN_STATUS_FRAME_RATE_DET_MSB 6
#define AVE_IN_STATUS_FRAME_RATE_DET_LSB 6
#define AVE_IN_STATUS_HSYNC_DET_BITS 5:5
#define AVE_IN_STATUS_HSYNC_DET_SET 0x00000020
#define AVE_IN_STATUS_HSYNC_DET_CLR 0xffffffdf
#define AVE_IN_STATUS_HSYNC_DET_MSB 5
#define AVE_IN_STATUS_HSYNC_DET_LSB 5
#define AVE_IN_STATUS_LINE_NUM_HIT_BITS 4:4
#define AVE_IN_STATUS_LINE_NUM_HIT_SET 0x00000010
#define AVE_IN_STATUS_LINE_NUM_HIT_CLR 0xffffffef
#define AVE_IN_STATUS_LINE_NUM_HIT_MSB 4
#define AVE_IN_STATUS_LINE_NUM_HIT_LSB 4
#define AVE_IN_STATUS_BUF_NOT_SERV_BITS 3:3
#define AVE_IN_STATUS_BUF_NOT_SERV_SET 0x00000008
#define AVE_IN_STATUS_BUF_NOT_SERV_CLR 0xfffffff7
#define AVE_IN_STATUS_BUF_NOT_SERV_MSB 3
#define AVE_IN_STATUS_BUF_NOT_SERV_LSB 3
#define AVE_IN_STATUS_BUF1_COMPL_BITS 2:2
#define AVE_IN_STATUS_BUF1_COMPL_SET 0x00000004
#define AVE_IN_STATUS_BUF1_COMPL_CLR 0xfffffffb
#define AVE_IN_STATUS_BUF1_COMPL_MSB 2
#define AVE_IN_STATUS_BUF1_COMPL_LSB 2
#define AVE_IN_STATUS_BUF0_COMPL_BITS 1:1
#define AVE_IN_STATUS_BUF0_COMPL_SET 0x00000002
#define AVE_IN_STATUS_BUF0_COMPL_CLR 0xfffffffd
#define AVE_IN_STATUS_BUF0_COMPL_MSB 1
#define AVE_IN_STATUS_BUF0_COMPL_LSB 1
#define AVE_IN_STATUS_OVERRUN_DET_BITS 0:0
#define AVE_IN_STATUS_OVERRUN_DET_SET 0x00000001
#define AVE_IN_STATUS_OVERRUN_DET_CLR 0xfffffffe
#define AVE_IN_STATUS_OVERRUN_DET_MSB 0
#define AVE_IN_STATUS_OVERRUN_DET_LSB 0
#define AVE_IN_BUF0_ADDRESS HW_REGISTER_RW( 0x7e910008 )
#define AVE_IN_BUF0_ADDRESS_MASK 0xffffffff
#define AVE_IN_BUF0_ADDRESS_WIDTH 32
#define AVE_IN_BUF0_ADDRESS_RESET 0000000000
#define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_BITS 31:0
#define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_SET 0xffffffff
#define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_CLR 0x00000000
#define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_MSB 31
#define AVE_IN_BUF0_ADDRESS_BUF0_ADDR_LSB 0
#define AVE_IN_BUF1_ADDRESS HW_REGISTER_RW( 0x7e91000c )
#define AVE_IN_BUF1_ADDRESS_MASK 0xffffffff
#define AVE_IN_BUF1_ADDRESS_WIDTH 32
#define AVE_IN_BUF1_ADDRESS_RESET 0000000000
#define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_BITS 31:0
#define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_SET 0xffffffff
#define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_CLR 0x00000000
#define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_MSB 31
#define AVE_IN_BUF1_ADDRESS_BUF1_ADDR_LSB 0
#define AVE_IN_MAX_TRANSFER HW_REGISTER_RW( 0x7e910010 )
#define AVE_IN_MAX_TRANSFER_MASK 0xffffffff
#define AVE_IN_MAX_TRANSFER_WIDTH 32
#define AVE_IN_MAX_TRANSFER_RESET 0000000000
#define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_BITS 31:0
#define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_SET 0xffffffff
#define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_CLR 0x00000000
#define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_MSB 31
#define AVE_IN_MAX_TRANSFER_MAX_TRANSFER_LSB 0
#define AVE_IN_LINE_LENGTH HW_REGISTER_RW( 0x7e910014 )
#define AVE_IN_LINE_LENGTH_MASK 0x00000fff
#define AVE_IN_LINE_LENGTH_WIDTH 12
#define AVE_IN_LINE_LENGTH_RESET 0000000000
#define AVE_IN_LINE_LENGTH_LINE_LENGTH_BITS 11:0
#define AVE_IN_LINE_LENGTH_LINE_LENGTH_SET 0x00000fff
#define AVE_IN_LINE_LENGTH_LINE_LENGTH_CLR 0xfffff000
#define AVE_IN_LINE_LENGTH_LINE_LENGTH_MSB 11
#define AVE_IN_LINE_LENGTH_LINE_LENGTH_LSB 0
#define AVE_IN_CURRENT_ADDRESS HW_REGISTER_RW( 0x7e910018 )
#define AVE_IN_CURRENT_ADDRESS_MASK 0xffffffff
#define AVE_IN_CURRENT_ADDRESS_WIDTH 32
#define AVE_IN_CURRENT_ADDRESS_RESET 0000000000
#define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_BITS 31:0
#define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_SET 0xffffffff
#define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_CLR 0x00000000
#define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_MSB 31
#define AVE_IN_CURRENT_ADDRESS_CUR_ADDR_LSB 0
#define AVE_IN_CURRENT_LINE_BUF0 HW_REGISTER_RW( 0x7e91001c )
#define AVE_IN_CURRENT_LINE_BUF0_MASK 0x80000fff
#define AVE_IN_CURRENT_LINE_BUF0_WIDTH 32
#define AVE_IN_CURRENT_LINE_BUF0_RESET 0000000000
#define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_BITS 11:0
#define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_SET 0x00000fff
#define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_CLR 0xfffff000
#define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_MSB 11
#define AVE_IN_CURRENT_LINE_BUF0_CURRENT_LINE_LSB 0
#define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_BITS 31:31
#define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_SET 0x80000000
#define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_CLR 0x7fffffff
#define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_MSB 31
#define AVE_IN_CURRENT_LINE_BUF0_EVEN_FIELD_LSB 31
#define AVE_IN_CURRENT_LINE_BUF1 HW_REGISTER_RW( 0x7e910020 )
#define AVE_IN_CURRENT_LINE_BUF1_MASK 0x80000fff
#define AVE_IN_CURRENT_LINE_BUF1_WIDTH 32
#define AVE_IN_CURRENT_LINE_BUF1_RESET 0000000000
#define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_BITS 11:0
#define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_SET 0x00000fff
#define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_CLR 0xfffff000
#define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_MSB 11
#define AVE_IN_CURRENT_LINE_BUF1_CURRENT_LINE_LSB 0
#define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_BITS 31:31
#define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_SET 0x80000000
#define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_CLR 0x7fffffff
#define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_MSB 31
#define AVE_IN_CURRENT_LINE_BUF1_EVEN_FIELD_LSB 31
#define AVE_IN_CURRENT_LINE_NUM HW_REGISTER_RW( 0x7e910024 )
#define AVE_IN_CURRENT_LINE_NUM_MASK 0xe0000fff
#define AVE_IN_CURRENT_LINE_NUM_WIDTH 32
#define AVE_IN_CURRENT_LINE_NUM_RESET 0000000000
#define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_BITS 11:0
#define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_SET 0x00000fff
#define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_CLR 0xfffff000
#define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_MSB 11
#define AVE_IN_CURRENT_LINE_NUM_CURRENT_LINE_LSB 0
#define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_BITS 29:29
#define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_SET 0x20000000
#define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_CLR 0xdfffffff
#define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_MSB 29
#define AVE_IN_CURRENT_LINE_NUM_BUFFER_POINTER_LSB 29
#define AVE_IN_CURRENT_LINE_NUM_INTERLACED_BITS 30:30
#define AVE_IN_CURRENT_LINE_NUM_INTERLACED_SET 0x40000000
#define AVE_IN_CURRENT_LINE_NUM_INTERLACED_CLR 0xbfffffff
#define AVE_IN_CURRENT_LINE_NUM_INTERLACED_MSB 30
#define AVE_IN_CURRENT_LINE_NUM_INTERLACED_LSB 30
#define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_BITS 31:31
#define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_SET 0x80000000
#define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_CLR 0x7fffffff
#define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_MSB 31
#define AVE_IN_CURRENT_LINE_NUM_EVEN_FIELD_LSB 31
#define AVE_IN_OVERRUN_ADDRESS HW_REGISTER_RW( 0x7e910028 )
#define AVE_IN_OVERRUN_ADDRESS_MASK 0xffffffff
#define AVE_IN_OVERRUN_ADDRESS_WIDTH 32
#define AVE_IN_OVERRUN_ADDRESS_RESET 0000000000
#define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_BITS 31:0
#define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_SET 0xffffffff
#define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_CLR 0x00000000
#define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_MSB 31
#define AVE_IN_OVERRUN_ADDRESS_OVERRUN_ADDR_LSB 0
#define AVE_IN_LINE_NUM_INT HW_REGISTER_RW( 0x7e91002c )
#define AVE_IN_LINE_NUM_INT_MASK 0x00000fff
#define AVE_IN_LINE_NUM_INT_WIDTH 12
#define AVE_IN_LINE_NUM_INT_RESET 0000000000
#define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_BITS 11:0
#define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_SET 0x00000fff
#define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_CLR 0xfffff000
#define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_MSB 11
#define AVE_IN_LINE_NUM_INT_LINE_NUM_INT_LSB 0
#define AVE_IN_CALC_LINE_STEP HW_REGISTER_RW( 0x7e910030 )
#define AVE_IN_CALC_LINE_STEP_MASK 0x00000fff
#define AVE_IN_CALC_LINE_STEP_WIDTH 12
#define AVE_IN_CALC_LINE_STEP_RESET 0000000000
#define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_BITS 11:0
#define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_SET 0x00000fff
#define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_CLR 0xfffff000
#define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_MSB 11
#define AVE_IN_CALC_LINE_STEP_CALC_LINE_STEP_LSB 0
#define AVE_IN_OUTSTANDING_BUFF0 HW_REGISTER_RW( 0x7e910034 )
#define AVE_IN_OUTSTANDING_BUFF0_MASK 0x000000ff
#define AVE_IN_OUTSTANDING_BUFF0_WIDTH 8
#define AVE_IN_OUTSTANDING_BUFF0_RESET 0000000000
#define AVE_IN_OUTSTANDING_BUFF1 HW_REGISTER_RW( 0x7e910038 )
#define AVE_IN_OUTSTANDING_BUFF1_MASK 0x000000ff
#define AVE_IN_OUTSTANDING_BUFF1_WIDTH 8
#define AVE_IN_OUTSTANDING_BUFF1_RESET 0000000000
#define AVE_IN_CHAR_CTRL HW_REGISTER_RW( 0x7e91003c )
#define AVE_IN_CHAR_CTRL_MASK 0x8000000f
#define AVE_IN_CHAR_CTRL_WIDTH 32
#define AVE_IN_CHAR_CTRL_RESET 0000000000
#define AVE_IN_SYNC_CTRL HW_REGISTER_RW( 0x7e910040 )
#define AVE_IN_SYNC_CTRL_MASK 0x0000008f
#define AVE_IN_SYNC_CTRL_WIDTH 8
#define AVE_IN_SYNC_CTRL_RESET 0000000000
#define AVE_IN_FRAME_NUM HW_REGISTER_RW( 0x7e910044 )
#define AVE_IN_FRAME_NUM_MASK 0x00000fff
#define AVE_IN_FRAME_NUM_WIDTH 12
#define AVE_IN_FRAME_NUM_RESET 0000000000
#define AVE_IN_FRAME_NUM_FRAME_NUM_BITS 11:0
#define AVE_IN_FRAME_NUM_FRAME_NUM_SET 0x00000fff
#define AVE_IN_FRAME_NUM_FRAME_NUM_CLR 0xfffff000
#define AVE_IN_FRAME_NUM_FRAME_NUM_MSB 11
#define AVE_IN_FRAME_NUM_FRAME_NUM_LSB 0
#define AVE_IN_BLOCK_ID HW_REGISTER_RW( 0x7e910060 )
#define AVE_IN_BLOCK_ID_MASK 0xffffffff
#define AVE_IN_BLOCK_ID_WIDTH 32
#define AVE_IN_BLOCK_ID_RESET 0x61766530

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bcm2708_chip/ave_out.h Executable file
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// This file was generated by the create_regs script
#define AVE_OUT_BASE 0x7e240000
#define AVE_OUT_APB_ID 0x61766538
#define AVE_OUT_CTRL HW_REGISTER_RW( 0x7e240000 )
#define AVE_OUT_CTRL_MASK 0xc0fff13f
#define AVE_OUT_CTRL_WIDTH 32
#define AVE_OUT_CTRL_RESET 0x40000100
#define AVE_OUT_CTRL_ENABLE_BITS 31:31
#define AVE_OUT_CTRL_ENABLE_SET 0x80000000
#define AVE_OUT_CTRL_ENABLE_CLR 0x7fffffff
#define AVE_OUT_CTRL_ENABLE_MSB 31
#define AVE_OUT_CTRL_ENABLE_LSB 31
#define AVE_OUT_CTRL_SOFT_RESET_BITS 30:30
#define AVE_OUT_CTRL_SOFT_RESET_SET 0x40000000
#define AVE_OUT_CTRL_SOFT_RESET_CLR 0xbfffffff
#define AVE_OUT_CTRL_SOFT_RESET_MSB 30
#define AVE_OUT_CTRL_SOFT_RESET_LSB 30
#define AVE_OUT_CTRL_BYTE_SWAP_BITS 23:19
#define AVE_OUT_CTRL_BYTE_SWAP_SET 0x00f80000
#define AVE_OUT_CTRL_BYTE_SWAP_CLR 0xff07ffff
#define AVE_OUT_CTRL_BYTE_SWAP_MSB 23
#define AVE_OUT_CTRL_BYTE_SWAP_LSB 19
#define AVE_OUT_CTRL_INVERT_DSYNC_BITS 18:18
#define AVE_OUT_CTRL_INVERT_DSYNC_SET 0x00040000
#define AVE_OUT_CTRL_INVERT_DSYNC_CLR 0xfffbffff
#define AVE_OUT_CTRL_INVERT_DSYNC_MSB 18
#define AVE_OUT_CTRL_INVERT_DSYNC_LSB 18
#define AVE_OUT_CTRL_INVERT_CSYNC_BITS 17:17
#define AVE_OUT_CTRL_INVERT_CSYNC_SET 0x00020000
#define AVE_OUT_CTRL_INVERT_CSYNC_CLR 0xfffdffff
#define AVE_OUT_CTRL_INVERT_CSYNC_MSB 17
#define AVE_OUT_CTRL_INVERT_CSYNC_LSB 17
#define AVE_OUT_CTRL_INVERT_EVEN_FIELD_BITS 16:16
#define AVE_OUT_CTRL_INVERT_EVEN_FIELD_SET 0x00010000
#define AVE_OUT_CTRL_INVERT_EVEN_FIELD_CLR 0xfffeffff
#define AVE_OUT_CTRL_INVERT_EVEN_FIELD_MSB 16
#define AVE_OUT_CTRL_INVERT_EVEN_FIELD_LSB 16
#define AVE_OUT_CTRL_INVERT_VSYNC_BITS 15:15
#define AVE_OUT_CTRL_INVERT_VSYNC_SET 0x00008000
#define AVE_OUT_CTRL_INVERT_VSYNC_CLR 0xffff7fff
#define AVE_OUT_CTRL_INVERT_VSYNC_MSB 15
#define AVE_OUT_CTRL_INVERT_VSYNC_LSB 15
#define AVE_OUT_CTRL_INVERT_HSYNC_BITS 14:14
#define AVE_OUT_CTRL_INVERT_HSYNC_SET 0x00004000
#define AVE_OUT_CTRL_INVERT_HSYNC_CLR 0xffffbfff
#define AVE_OUT_CTRL_INVERT_HSYNC_MSB 14
#define AVE_OUT_CTRL_INVERT_HSYNC_LSB 14
#define AVE_OUT_CTRL_NTSC_PAL_IDENT_BITS 13:13
#define AVE_OUT_CTRL_NTSC_PAL_IDENT_SET 0x00002000
#define AVE_OUT_CTRL_NTSC_PAL_IDENT_CLR 0xffffdfff
#define AVE_OUT_CTRL_NTSC_PAL_IDENT_MSB 13
#define AVE_OUT_CTRL_NTSC_PAL_IDENT_LSB 13
#define AVE_OUT_CTRL_INTERLEAVE_BITS 12:12
#define AVE_OUT_CTRL_INTERLEAVE_SET 0x00001000
#define AVE_OUT_CTRL_INTERLEAVE_CLR 0xffffefff
#define AVE_OUT_CTRL_INTERLEAVE_MSB 12
#define AVE_OUT_CTRL_INTERLEAVE_LSB 12
#define AVE_OUT_CTRL_PRIV_ACCESS_BITS 8:8
#define AVE_OUT_CTRL_PRIV_ACCESS_SET 0x00000100
#define AVE_OUT_CTRL_PRIV_ACCESS_CLR 0xfffffeff
#define AVE_OUT_CTRL_PRIV_ACCESS_MSB 8
#define AVE_OUT_CTRL_PRIV_ACCESS_LSB 8
#define AVE_OUT_CTRL_MODE_BITS 5:4
#define AVE_OUT_CTRL_MODE_SET 0x00000030
#define AVE_OUT_CTRL_MODE_CLR 0xffffffcf
#define AVE_OUT_CTRL_MODE_MSB 5
#define AVE_OUT_CTRL_MODE_LSB 4
#define AVE_OUT_CTRL_REFRESH_RATE_BITS 3:2
#define AVE_OUT_CTRL_REFRESH_RATE_SET 0x0000000c
#define AVE_OUT_CTRL_REFRESH_RATE_CLR 0xfffffff3
#define AVE_OUT_CTRL_REFRESH_RATE_MSB 3
#define AVE_OUT_CTRL_REFRESH_RATE_LSB 2
#define AVE_OUT_CTRL_COEFF_IRQ_EN_BITS 1:1
#define AVE_OUT_CTRL_COEFF_IRQ_EN_SET 0x00000002
#define AVE_OUT_CTRL_COEFF_IRQ_EN_CLR 0xfffffffd
#define AVE_OUT_CTRL_COEFF_IRQ_EN_MSB 1
#define AVE_OUT_CTRL_COEFF_IRQ_EN_LSB 1
#define AVE_OUT_CTRL_ERROR_IRQ_EN_BITS 0:0
#define AVE_OUT_CTRL_ERROR_IRQ_EN_SET 0x00000001
#define AVE_OUT_CTRL_ERROR_IRQ_EN_CLR 0xfffffffe
#define AVE_OUT_CTRL_ERROR_IRQ_EN_MSB 0
#define AVE_OUT_CTRL_ERROR_IRQ_EN_LSB 0
#define AVE_OUT_STATUS HW_REGISTER_RW( 0x7e240004 )
#define AVE_OUT_STATUS_MASK 0x000003f7
#define AVE_OUT_STATUS_WIDTH 10
#define AVE_OUT_STATUS_RESET 0000000000
#define AVE_OUT_STATUS_VSYNC_BITS 9:9
#define AVE_OUT_STATUS_VSYNC_SET 0x00000200
#define AVE_OUT_STATUS_VSYNC_CLR 0xfffffdff
#define AVE_OUT_STATUS_VSYNC_MSB 9
#define AVE_OUT_STATUS_VSYNC_LSB 9
#define AVE_OUT_STATUS_VBACK_PORCH_BITS 8:8
#define AVE_OUT_STATUS_VBACK_PORCH_SET 0x00000100
#define AVE_OUT_STATUS_VBACK_PORCH_CLR 0xfffffeff
#define AVE_OUT_STATUS_VBACK_PORCH_MSB 8
#define AVE_OUT_STATUS_VBACK_PORCH_LSB 8
#define AVE_OUT_STATUS_VFRONT_PORCH_BITS 7:7
#define AVE_OUT_STATUS_VFRONT_PORCH_SET 0x00000080
#define AVE_OUT_STATUS_VFRONT_PORCH_CLR 0xffffff7f
#define AVE_OUT_STATUS_VFRONT_PORCH_MSB 7
#define AVE_OUT_STATUS_VFRONT_PORCH_LSB 7
#define AVE_OUT_STATUS_HSYNC_BITS 6:6
#define AVE_OUT_STATUS_HSYNC_SET 0x00000040
#define AVE_OUT_STATUS_HSYNC_CLR 0xffffffbf
#define AVE_OUT_STATUS_HSYNC_MSB 6
#define AVE_OUT_STATUS_HSYNC_LSB 6
#define AVE_OUT_STATUS_HBACK_PORCH_BITS 5:5
#define AVE_OUT_STATUS_HBACK_PORCH_SET 0x00000020
#define AVE_OUT_STATUS_HBACK_PORCH_CLR 0xffffffdf
#define AVE_OUT_STATUS_HBACK_PORCH_MSB 5
#define AVE_OUT_STATUS_HBACK_PORCH_LSB 5
#define AVE_OUT_STATUS_HFRONT_PORCH_BITS 4:4
#define AVE_OUT_STATUS_HFRONT_PORCH_SET 0x00000010
#define AVE_OUT_STATUS_HFRONT_PORCH_CLR 0xffffffef
#define AVE_OUT_STATUS_HFRONT_PORCH_MSB 4
#define AVE_OUT_STATUS_HFRONT_PORCH_LSB 4
#define AVE_OUT_STATUS_COEFF_ERROR_BITS 2:2
#define AVE_OUT_STATUS_COEFF_ERROR_SET 0x00000004
#define AVE_OUT_STATUS_COEFF_ERROR_CLR 0xfffffffb
#define AVE_OUT_STATUS_COEFF_ERROR_MSB 2
#define AVE_OUT_STATUS_COEFF_ERROR_LSB 2
#define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_BITS 1:1
#define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_SET 0x00000002
#define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_CLR 0xfffffffd
#define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_MSB 1
#define AVE_OUT_STATUS_PXL_OUTPUT_ERROR_LSB 1
#define AVE_OUT_STATUS_PXL_FORMAT_ERROR_BITS 0:0
#define AVE_OUT_STATUS_PXL_FORMAT_ERROR_SET 0x00000001
#define AVE_OUT_STATUS_PXL_FORMAT_ERROR_CLR 0xfffffffe
#define AVE_OUT_STATUS_PXL_FORMAT_ERROR_MSB 0
#define AVE_OUT_STATUS_PXL_FORMAT_ERROR_LSB 0
#define AVE_OUT_OFFSET HW_REGISTER_RW( 0x7e240008 )
#define AVE_OUT_OFFSET_MASK 0x80ffffff
#define AVE_OUT_OFFSET_WIDTH 32
#define AVE_OUT_OFFSET_RESET 0x80109090
#define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_BITS 31:31
#define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_SET 0x80000000
#define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_CLR 0x7fffffff
#define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_MSB 31
#define AVE_OUT_OFFSET_EN_YCBCR_CLAMPING_LSB 31
#define AVE_OUT_OFFSET_RED_OFFSET_BITS 23:16
#define AVE_OUT_OFFSET_RED_OFFSET_SET 0x00ff0000
#define AVE_OUT_OFFSET_RED_OFFSET_CLR 0xff00ffff
#define AVE_OUT_OFFSET_RED_OFFSET_MSB 23
#define AVE_OUT_OFFSET_RED_OFFSET_LSB 16
#define AVE_OUT_OFFSET_GREEN_OFFSET_BITS 15:8
#define AVE_OUT_OFFSET_GREEN_OFFSET_SET 0x0000ff00
#define AVE_OUT_OFFSET_GREEN_OFFSET_CLR 0xffff00ff
#define AVE_OUT_OFFSET_GREEN_OFFSET_MSB 15
#define AVE_OUT_OFFSET_GREEN_OFFSET_LSB 8
#define AVE_OUT_OFFSET_BLUE_OFFSET_BITS 7:0
#define AVE_OUT_OFFSET_BLUE_OFFSET_SET 0x000000ff
#define AVE_OUT_OFFSET_BLUE_OFFSET_CLR 0xffffff00
#define AVE_OUT_OFFSET_BLUE_OFFSET_MSB 7
#define AVE_OUT_OFFSET_BLUE_OFFSET_LSB 0
#define AVE_OUT_Y_COEFF HW_REGISTER_RW( 0x7e24000c )
#define AVE_OUT_Y_COEFF_MASK 0x3fffffff
#define AVE_OUT_Y_COEFF_WIDTH 30
#define AVE_OUT_Y_COEFF_RESET 0x0994b43a
#define AVE_OUT_Y_COEFF_RED_COEFF_BITS 29:20
#define AVE_OUT_Y_COEFF_RED_COEFF_SET 0x3ff00000
#define AVE_OUT_Y_COEFF_RED_COEFF_CLR 0xc00fffff
#define AVE_OUT_Y_COEFF_RED_COEFF_MSB 29
#define AVE_OUT_Y_COEFF_RED_COEFF_LSB 20
#define AVE_OUT_Y_COEFF_GREEN_COEFF_BITS 19:10
#define AVE_OUT_Y_COEFF_GREEN_COEFF_SET 0x000ffc00
#define AVE_OUT_Y_COEFF_GREEN_COEFF_CLR 0xfff003ff
#define AVE_OUT_Y_COEFF_GREEN_COEFF_MSB 19
#define AVE_OUT_Y_COEFF_GREEN_COEFF_LSB 10
#define AVE_OUT_Y_COEFF_BLUE_COEFF_BITS 9:0
#define AVE_OUT_Y_COEFF_BLUE_COEFF_SET 0x000003ff
#define AVE_OUT_Y_COEFF_BLUE_COEFF_CLR 0xfffffc00
#define AVE_OUT_Y_COEFF_BLUE_COEFF_MSB 9
#define AVE_OUT_Y_COEFF_BLUE_COEFF_LSB 0
#define AVE_OUT_CB_COEFF HW_REGISTER_RW( 0x7e240010 )
#define AVE_OUT_CB_COEFF_MASK 0x3fffffff
#define AVE_OUT_CB_COEFF_WIDTH 30
#define AVE_OUT_CB_COEFF_RESET 0x3a9d5900
#define AVE_OUT_CB_COEFF_RED_COEFF_BITS 29:20
#define AVE_OUT_CB_COEFF_RED_COEFF_SET 0x3ff00000
#define AVE_OUT_CB_COEFF_RED_COEFF_CLR 0xc00fffff
#define AVE_OUT_CB_COEFF_RED_COEFF_MSB 29
#define AVE_OUT_CB_COEFF_RED_COEFF_LSB 20
#define AVE_OUT_CB_COEFF_GREEN_COEFF_BITS 19:10
#define AVE_OUT_CB_COEFF_GREEN_COEFF_SET 0x000ffc00
#define AVE_OUT_CB_COEFF_GREEN_COEFF_CLR 0xfff003ff
#define AVE_OUT_CB_COEFF_GREEN_COEFF_MSB 19
#define AVE_OUT_CB_COEFF_GREEN_COEFF_LSB 10
#define AVE_OUT_CB_COEFF_BLUE_COEFF_BITS 9:0
#define AVE_OUT_CB_COEFF_BLUE_COEFF_SET 0x000003ff
#define AVE_OUT_CB_COEFF_BLUE_COEFF_CLR 0xfffffc00
#define AVE_OUT_CB_COEFF_BLUE_COEFF_MSB 9
#define AVE_OUT_CB_COEFF_BLUE_COEFF_LSB 0
#define AVE_OUT_CR_COEFF HW_REGISTER_RW( 0x7e240014 )
#define AVE_OUT_CR_COEFF_MASK 0x3fffffff
#define AVE_OUT_CR_COEFF_WIDTH 30
#define AVE_OUT_CR_COEFF_RESET 0x100ca7d6
#define AVE_OUT_CR_COEFF_RED_COEFF_BITS 29:20
#define AVE_OUT_CR_COEFF_RED_COEFF_SET 0x3ff00000
#define AVE_OUT_CR_COEFF_RED_COEFF_CLR 0xc00fffff
#define AVE_OUT_CR_COEFF_RED_COEFF_MSB 29
#define AVE_OUT_CR_COEFF_RED_COEFF_LSB 20
#define AVE_OUT_CR_COEFF_GREEN_COEFF_BITS 19:10
#define AVE_OUT_CR_COEFF_GREEN_COEFF_SET 0x000ffc00
#define AVE_OUT_CR_COEFF_GREEN_COEFF_CLR 0xfff003ff
#define AVE_OUT_CR_COEFF_GREEN_COEFF_MSB 19
#define AVE_OUT_CR_COEFF_GREEN_COEFF_LSB 10
#define AVE_OUT_CR_COEFF_BLUE_COEFF_BITS 9:0
#define AVE_OUT_CR_COEFF_BLUE_COEFF_SET 0x000003ff
#define AVE_OUT_CR_COEFF_BLUE_COEFF_CLR 0xfffffc00
#define AVE_OUT_CR_COEFF_BLUE_COEFF_MSB 9
#define AVE_OUT_CR_COEFF_BLUE_COEFF_LSB 0
#define AVE_OUT_BLOCK_ID HW_REGISTER_RW( 0x7e240060 )
#define AVE_OUT_BLOCK_ID_MASK 0xffffffff
#define AVE_OUT_BLOCK_ID_WIDTH 32
#define AVE_OUT_BLOCK_ID_RESET 0x61766538

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bcm2708_chip/axi_dma0.h Executable file
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// This file was generated by the create_regs script
#define DMA0_BASE 0x7e007000
#define DMA0_CS HW_REGISTER_RW( 0x7e007000 )
#define DMA0_CS_MASK 0xf0ff017f
#define DMA0_CS_WIDTH 32
#define DMA0_CS_RESET 0000000000
#define DMA0_CS_RESET_BITS 31:31
#define DMA0_CS_RESET_SET 0x80000000
#define DMA0_CS_RESET_CLR 0x7fffffff
#define DMA0_CS_RESET_MSB 31
#define DMA0_CS_RESET_LSB 31
#define DMA0_CS_ABORT_BITS 30:30
#define DMA0_CS_ABORT_SET 0x40000000
#define DMA0_CS_ABORT_CLR 0xbfffffff
#define DMA0_CS_ABORT_MSB 30
#define DMA0_CS_ABORT_LSB 30
#define DMA0_CS_DISDEBUG_BITS 29:29
#define DMA0_CS_DISDEBUG_SET 0x20000000
#define DMA0_CS_DISDEBUG_CLR 0xdfffffff
#define DMA0_CS_DISDEBUG_MSB 29
#define DMA0_CS_DISDEBUG_LSB 29
#define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA0_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA0_CS_PANIC_PRIORITY_BITS 23:20
#define DMA0_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA0_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA0_CS_PANIC_PRIORITY_MSB 23
#define DMA0_CS_PANIC_PRIORITY_LSB 20
#define DMA0_CS_PRIORITY_BITS 19:16
#define DMA0_CS_PRIORITY_SET 0x000f0000
#define DMA0_CS_PRIORITY_CLR 0xfff0ffff
#define DMA0_CS_PRIORITY_MSB 19
#define DMA0_CS_PRIORITY_LSB 16
#define DMA0_CS_ERROR_BITS 8:8
#define DMA0_CS_ERROR_SET 0x00000100
#define DMA0_CS_ERROR_CLR 0xfffffeff
#define DMA0_CS_ERROR_MSB 8
#define DMA0_CS_ERROR_LSB 8
#define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA0_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA0_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA0_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA0_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA0_CS_DREQ_STOPS_DMA_MSB 5
#define DMA0_CS_DREQ_STOPS_DMA_LSB 5
#define DMA0_CS_PAUSED_BITS 4:4
#define DMA0_CS_PAUSED_SET 0x00000010
#define DMA0_CS_PAUSED_CLR 0xffffffef
#define DMA0_CS_PAUSED_MSB 4
#define DMA0_CS_PAUSED_LSB 4
#define DMA0_CS_DREQ_BITS 3:3
#define DMA0_CS_DREQ_SET 0x00000008
#define DMA0_CS_DREQ_CLR 0xfffffff7
#define DMA0_CS_DREQ_MSB 3
#define DMA0_CS_DREQ_LSB 3
#define DMA0_CS_INT_BITS 2:2
#define DMA0_CS_INT_SET 0x00000004
#define DMA0_CS_INT_CLR 0xfffffffb
#define DMA0_CS_INT_MSB 2
#define DMA0_CS_INT_LSB 2
#define DMA0_CS_END_BITS 1:1
#define DMA0_CS_END_SET 0x00000002
#define DMA0_CS_END_CLR 0xfffffffd
#define DMA0_CS_END_MSB 1
#define DMA0_CS_END_LSB 1
#define DMA0_CS_ACTIVE_BITS 0:0
#define DMA0_CS_ACTIVE_SET 0x00000001
#define DMA0_CS_ACTIVE_CLR 0xfffffffe
#define DMA0_CS_ACTIVE_MSB 0
#define DMA0_CS_ACTIVE_LSB 0
#define DMA0_CONBLK_AD HW_REGISTER_RW( 0x7e007004 )
#define DMA0_CONBLK_AD_MASK 0xffffffe0
#define DMA0_CONBLK_AD_WIDTH 32
#define DMA0_CONBLK_AD_RESET 0000000000
#define DMA0_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA0_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA0_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA0_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA0_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA0_TI HW_REGISTER_RO( 0x7e007008 )
#define DMA0_TI_MASK 0x07fffffb
#define DMA0_TI_WIDTH 27
#define DMA0_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA0_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA0_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA0_TI_NO_WIDE_BURSTS_MSB 26
#define DMA0_TI_NO_WIDE_BURSTS_LSB 26
#define DMA0_TI_WAITS_BITS 25:21
#define DMA0_TI_WAITS_SET 0x03e00000
#define DMA0_TI_WAITS_CLR 0xfc1fffff
#define DMA0_TI_WAITS_MSB 25
#define DMA0_TI_WAITS_LSB 21
#define DMA0_TI_PERMAP_BITS 20:16
#define DMA0_TI_PERMAP_SET 0x001f0000
#define DMA0_TI_PERMAP_CLR 0xffe0ffff
#define DMA0_TI_PERMAP_MSB 20
#define DMA0_TI_PERMAP_LSB 16
#define DMA0_TI_BURST_LENGTH_BITS 15:12
#define DMA0_TI_BURST_LENGTH_SET 0x0000f000
#define DMA0_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA0_TI_BURST_LENGTH_MSB 15
#define DMA0_TI_BURST_LENGTH_LSB 12
#define DMA0_TI_SRC_IGNORE_BITS 11:11
#define DMA0_TI_SRC_IGNORE_SET 0x00000800
#define DMA0_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA0_TI_SRC_IGNORE_MSB 11
#define DMA0_TI_SRC_IGNORE_LSB 11
#define DMA0_TI_SRC_DREQ_BITS 10:10
#define DMA0_TI_SRC_DREQ_SET 0x00000400
#define DMA0_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA0_TI_SRC_DREQ_MSB 10
#define DMA0_TI_SRC_DREQ_LSB 10
#define DMA0_TI_SRC_WIDTH_BITS 9:9
#define DMA0_TI_SRC_WIDTH_SET 0x00000200
#define DMA0_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA0_TI_SRC_WIDTH_MSB 9
#define DMA0_TI_SRC_WIDTH_LSB 9
#define DMA0_TI_SRC_INC_BITS 8:8
#define DMA0_TI_SRC_INC_SET 0x00000100
#define DMA0_TI_SRC_INC_CLR 0xfffffeff
#define DMA0_TI_SRC_INC_MSB 8
#define DMA0_TI_SRC_INC_LSB 8
#define DMA0_TI_DEST_IGNORE_BITS 7:7
#define DMA0_TI_DEST_IGNORE_SET 0x00000080
#define DMA0_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA0_TI_DEST_IGNORE_MSB 7
#define DMA0_TI_DEST_IGNORE_LSB 7
#define DMA0_TI_DEST_DREQ_BITS 6:6
#define DMA0_TI_DEST_DREQ_SET 0x00000040
#define DMA0_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA0_TI_DEST_DREQ_MSB 6
#define DMA0_TI_DEST_DREQ_LSB 6
#define DMA0_TI_DEST_WIDTH_BITS 5:5
#define DMA0_TI_DEST_WIDTH_SET 0x00000020
#define DMA0_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA0_TI_DEST_WIDTH_MSB 5
#define DMA0_TI_DEST_WIDTH_LSB 5
#define DMA0_TI_DEST_INC_BITS 4:4
#define DMA0_TI_DEST_INC_SET 0x00000010
#define DMA0_TI_DEST_INC_CLR 0xffffffef
#define DMA0_TI_DEST_INC_MSB 4
#define DMA0_TI_DEST_INC_LSB 4
#define DMA0_TI_WAIT_RESP_BITS 3:3
#define DMA0_TI_WAIT_RESP_SET 0x00000008
#define DMA0_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA0_TI_WAIT_RESP_MSB 3
#define DMA0_TI_WAIT_RESP_LSB 3
#define DMA0_TI_TDMODE_BITS 1:1
#define DMA0_TI_TDMODE_SET 0x00000002
#define DMA0_TI_TDMODE_CLR 0xfffffffd
#define DMA0_TI_TDMODE_MSB 1
#define DMA0_TI_TDMODE_LSB 1
#define DMA0_TI_INTEN_BITS 0:0
#define DMA0_TI_INTEN_SET 0x00000001
#define DMA0_TI_INTEN_CLR 0xfffffffe
#define DMA0_TI_INTEN_MSB 0
#define DMA0_TI_INTEN_LSB 0
#define DMA0_SOURCE_AD HW_REGISTER_RO( 0x7e00700c )
#define DMA0_SOURCE_AD_MASK 0xffffffff
#define DMA0_SOURCE_AD_WIDTH 32
#define DMA0_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA0_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA0_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA0_SOURCE_AD_S_ADDR_MSB 31
#define DMA0_SOURCE_AD_S_ADDR_LSB 0
#define DMA0_DEST_AD HW_REGISTER_RO( 0x7e007010 )
#define DMA0_DEST_AD_MASK 0xffffffff
#define DMA0_DEST_AD_WIDTH 32
#define DMA0_DEST_AD_D_ADDR_BITS 31:0
#define DMA0_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA0_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA0_DEST_AD_D_ADDR_MSB 31
#define DMA0_DEST_AD_D_ADDR_LSB 0
#define DMA0_TXFR_LEN HW_REGISTER_RO( 0x7e007014 )
#define DMA0_TXFR_LEN_MASK 0x3fffffff
#define DMA0_TXFR_LEN_WIDTH 30
#define DMA0_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA0_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA0_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA0_TXFR_LEN_YLENGTH_MSB 29
#define DMA0_TXFR_LEN_YLENGTH_LSB 16
#define DMA0_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA0_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA0_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA0_TXFR_LEN_XLENGTH_MSB 15
#define DMA0_TXFR_LEN_XLENGTH_LSB 0
#define DMA0_STRIDE HW_REGISTER_RO( 0x7e007018 )
#define DMA0_STRIDE_MASK 0xffffffff
#define DMA0_STRIDE_WIDTH 32
#define DMA0_STRIDE_D_STRIDE_BITS 31:16
#define DMA0_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA0_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA0_STRIDE_D_STRIDE_MSB 31
#define DMA0_STRIDE_D_STRIDE_LSB 16
#define DMA0_STRIDE_S_STRIDE_BITS 15:0
#define DMA0_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA0_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA0_STRIDE_S_STRIDE_MSB 15
#define DMA0_STRIDE_S_STRIDE_LSB 0
#define DMA0_NEXTCONBK HW_REGISTER_RO( 0x7e00701c )
#define DMA0_NEXTCONBK_MASK 0xffffffe0
#define DMA0_NEXTCONBK_WIDTH 32
#define DMA0_NEXTCONBK_ADDR_BITS 31:5
#define DMA0_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA0_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA0_NEXTCONBK_ADDR_MSB 31
#define DMA0_NEXTCONBK_ADDR_LSB 5
#define DMA0_DEBUG HW_REGISTER_RW( 0x7e007020 )
#define DMA0_DEBUG_MASK 0x1ffffff7
#define DMA0_DEBUG_WIDTH 29
#define DMA0_DEBUG_RESET 0000000000
#define DMA0_DEBUG_LITE_BITS 28:28
#define DMA0_DEBUG_LITE_SET 0x10000000
#define DMA0_DEBUG_LITE_CLR 0xefffffff
#define DMA0_DEBUG_LITE_MSB 28
#define DMA0_DEBUG_LITE_LSB 28
#define DMA0_DEBUG_VERSION_BITS 27:25
#define DMA0_DEBUG_VERSION_SET 0x0e000000
#define DMA0_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA0_DEBUG_VERSION_MSB 27
#define DMA0_DEBUG_VERSION_LSB 25
#define DMA0_DEBUG_DMA_STATE_BITS 24:16
#define DMA0_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA0_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA0_DEBUG_DMA_STATE_MSB 24
#define DMA0_DEBUG_DMA_STATE_LSB 16
#define DMA0_DEBUG_DMA_ID_BITS 15:8
#define DMA0_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA0_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA0_DEBUG_DMA_ID_MSB 15
#define DMA0_DEBUG_DMA_ID_LSB 8
#define DMA0_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA0_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA0_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA0_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA0_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA0_DEBUG_READ_ERROR_BITS 2:2
#define DMA0_DEBUG_READ_ERROR_SET 0x00000004
#define DMA0_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA0_DEBUG_READ_ERROR_MSB 2
#define DMA0_DEBUG_READ_ERROR_LSB 2
#define DMA0_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA0_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA0_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA0_DEBUG_FIFO_ERROR_MSB 1
#define DMA0_DEBUG_FIFO_ERROR_LSB 1
#define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA0_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma1.h Executable file
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// This file was generated by the create_regs script
#define DMA1_BASE 0x7e007100
#define DMA1_CS HW_REGISTER_RW( 0x7e007100 )
#define DMA1_CS_MASK 0xf0ff017f
#define DMA1_CS_WIDTH 32
#define DMA1_CS_RESET 0000000000
#define DMA1_CS_RESET_BITS 31:31
#define DMA1_CS_RESET_SET 0x80000000
#define DMA1_CS_RESET_CLR 0x7fffffff
#define DMA1_CS_RESET_MSB 31
#define DMA1_CS_RESET_LSB 31
#define DMA1_CS_ABORT_BITS 30:30
#define DMA1_CS_ABORT_SET 0x40000000
#define DMA1_CS_ABORT_CLR 0xbfffffff
#define DMA1_CS_ABORT_MSB 30
#define DMA1_CS_ABORT_LSB 30
#define DMA1_CS_DISDEBUG_BITS 29:29
#define DMA1_CS_DISDEBUG_SET 0x20000000
#define DMA1_CS_DISDEBUG_CLR 0xdfffffff
#define DMA1_CS_DISDEBUG_MSB 29
#define DMA1_CS_DISDEBUG_LSB 29
#define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA1_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA1_CS_PANIC_PRIORITY_BITS 23:20
#define DMA1_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA1_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA1_CS_PANIC_PRIORITY_MSB 23
#define DMA1_CS_PANIC_PRIORITY_LSB 20
#define DMA1_CS_PRIORITY_BITS 19:16
#define DMA1_CS_PRIORITY_SET 0x000f0000
#define DMA1_CS_PRIORITY_CLR 0xfff0ffff
#define DMA1_CS_PRIORITY_MSB 19
#define DMA1_CS_PRIORITY_LSB 16
#define DMA1_CS_ERROR_BITS 8:8
#define DMA1_CS_ERROR_SET 0x00000100
#define DMA1_CS_ERROR_CLR 0xfffffeff
#define DMA1_CS_ERROR_MSB 8
#define DMA1_CS_ERROR_LSB 8
#define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA1_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA1_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA1_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA1_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA1_CS_DREQ_STOPS_DMA_MSB 5
#define DMA1_CS_DREQ_STOPS_DMA_LSB 5
#define DMA1_CS_PAUSED_BITS 4:4
#define DMA1_CS_PAUSED_SET 0x00000010
#define DMA1_CS_PAUSED_CLR 0xffffffef
#define DMA1_CS_PAUSED_MSB 4
#define DMA1_CS_PAUSED_LSB 4
#define DMA1_CS_DREQ_BITS 3:3
#define DMA1_CS_DREQ_SET 0x00000008
#define DMA1_CS_DREQ_CLR 0xfffffff7
#define DMA1_CS_DREQ_MSB 3
#define DMA1_CS_DREQ_LSB 3
#define DMA1_CS_INT_BITS 2:2
#define DMA1_CS_INT_SET 0x00000004
#define DMA1_CS_INT_CLR 0xfffffffb
#define DMA1_CS_INT_MSB 2
#define DMA1_CS_INT_LSB 2
#define DMA1_CS_END_BITS 1:1
#define DMA1_CS_END_SET 0x00000002
#define DMA1_CS_END_CLR 0xfffffffd
#define DMA1_CS_END_MSB 1
#define DMA1_CS_END_LSB 1
#define DMA1_CS_ACTIVE_BITS 0:0
#define DMA1_CS_ACTIVE_SET 0x00000001
#define DMA1_CS_ACTIVE_CLR 0xfffffffe
#define DMA1_CS_ACTIVE_MSB 0
#define DMA1_CS_ACTIVE_LSB 0
#define DMA1_CONBLK_AD HW_REGISTER_RW( 0x7e007104 )
#define DMA1_CONBLK_AD_MASK 0xffffffe0
#define DMA1_CONBLK_AD_WIDTH 32
#define DMA1_CONBLK_AD_RESET 0000000000
#define DMA1_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA1_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA1_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA1_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA1_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA1_TI HW_REGISTER_RO( 0x7e007108 )
#define DMA1_TI_MASK 0x07fffffb
#define DMA1_TI_WIDTH 27
#define DMA1_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA1_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA1_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA1_TI_NO_WIDE_BURSTS_MSB 26
#define DMA1_TI_NO_WIDE_BURSTS_LSB 26
#define DMA1_TI_WAITS_BITS 25:21
#define DMA1_TI_WAITS_SET 0x03e00000
#define DMA1_TI_WAITS_CLR 0xfc1fffff
#define DMA1_TI_WAITS_MSB 25
#define DMA1_TI_WAITS_LSB 21
#define DMA1_TI_PERMAP_BITS 20:16
#define DMA1_TI_PERMAP_SET 0x001f0000
#define DMA1_TI_PERMAP_CLR 0xffe0ffff
#define DMA1_TI_PERMAP_MSB 20
#define DMA1_TI_PERMAP_LSB 16
#define DMA1_TI_BURST_LENGTH_BITS 15:12
#define DMA1_TI_BURST_LENGTH_SET 0x0000f000
#define DMA1_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA1_TI_BURST_LENGTH_MSB 15
#define DMA1_TI_BURST_LENGTH_LSB 12
#define DMA1_TI_SRC_IGNORE_BITS 11:11
#define DMA1_TI_SRC_IGNORE_SET 0x00000800
#define DMA1_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA1_TI_SRC_IGNORE_MSB 11
#define DMA1_TI_SRC_IGNORE_LSB 11
#define DMA1_TI_SRC_DREQ_BITS 10:10
#define DMA1_TI_SRC_DREQ_SET 0x00000400
#define DMA1_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA1_TI_SRC_DREQ_MSB 10
#define DMA1_TI_SRC_DREQ_LSB 10
#define DMA1_TI_SRC_WIDTH_BITS 9:9
#define DMA1_TI_SRC_WIDTH_SET 0x00000200
#define DMA1_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA1_TI_SRC_WIDTH_MSB 9
#define DMA1_TI_SRC_WIDTH_LSB 9
#define DMA1_TI_SRC_INC_BITS 8:8
#define DMA1_TI_SRC_INC_SET 0x00000100
#define DMA1_TI_SRC_INC_CLR 0xfffffeff
#define DMA1_TI_SRC_INC_MSB 8
#define DMA1_TI_SRC_INC_LSB 8
#define DMA1_TI_DEST_IGNORE_BITS 7:7
#define DMA1_TI_DEST_IGNORE_SET 0x00000080
#define DMA1_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA1_TI_DEST_IGNORE_MSB 7
#define DMA1_TI_DEST_IGNORE_LSB 7
#define DMA1_TI_DEST_DREQ_BITS 6:6
#define DMA1_TI_DEST_DREQ_SET 0x00000040
#define DMA1_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA1_TI_DEST_DREQ_MSB 6
#define DMA1_TI_DEST_DREQ_LSB 6
#define DMA1_TI_DEST_WIDTH_BITS 5:5
#define DMA1_TI_DEST_WIDTH_SET 0x00000020
#define DMA1_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA1_TI_DEST_WIDTH_MSB 5
#define DMA1_TI_DEST_WIDTH_LSB 5
#define DMA1_TI_DEST_INC_BITS 4:4
#define DMA1_TI_DEST_INC_SET 0x00000010
#define DMA1_TI_DEST_INC_CLR 0xffffffef
#define DMA1_TI_DEST_INC_MSB 4
#define DMA1_TI_DEST_INC_LSB 4
#define DMA1_TI_WAIT_RESP_BITS 3:3
#define DMA1_TI_WAIT_RESP_SET 0x00000008
#define DMA1_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA1_TI_WAIT_RESP_MSB 3
#define DMA1_TI_WAIT_RESP_LSB 3
#define DMA1_TI_TDMODE_BITS 1:1
#define DMA1_TI_TDMODE_SET 0x00000002
#define DMA1_TI_TDMODE_CLR 0xfffffffd
#define DMA1_TI_TDMODE_MSB 1
#define DMA1_TI_TDMODE_LSB 1
#define DMA1_TI_INTEN_BITS 0:0
#define DMA1_TI_INTEN_SET 0x00000001
#define DMA1_TI_INTEN_CLR 0xfffffffe
#define DMA1_TI_INTEN_MSB 0
#define DMA1_TI_INTEN_LSB 0
#define DMA1_SOURCE_AD HW_REGISTER_RO( 0x7e00710c )
#define DMA1_SOURCE_AD_MASK 0xffffffff
#define DMA1_SOURCE_AD_WIDTH 32
#define DMA1_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA1_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA1_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA1_SOURCE_AD_S_ADDR_MSB 31
#define DMA1_SOURCE_AD_S_ADDR_LSB 0
#define DMA1_DEST_AD HW_REGISTER_RO( 0x7e007110 )
#define DMA1_DEST_AD_MASK 0xffffffff
#define DMA1_DEST_AD_WIDTH 32
#define DMA1_DEST_AD_D_ADDR_BITS 31:0
#define DMA1_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA1_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA1_DEST_AD_D_ADDR_MSB 31
#define DMA1_DEST_AD_D_ADDR_LSB 0
#define DMA1_TXFR_LEN HW_REGISTER_RO( 0x7e007114 )
#define DMA1_TXFR_LEN_MASK 0x3fffffff
#define DMA1_TXFR_LEN_WIDTH 30
#define DMA1_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA1_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA1_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA1_TXFR_LEN_YLENGTH_MSB 29
#define DMA1_TXFR_LEN_YLENGTH_LSB 16
#define DMA1_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA1_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA1_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA1_TXFR_LEN_XLENGTH_MSB 15
#define DMA1_TXFR_LEN_XLENGTH_LSB 0
#define DMA1_STRIDE HW_REGISTER_RO( 0x7e007118 )
#define DMA1_STRIDE_MASK 0xffffffff
#define DMA1_STRIDE_WIDTH 32
#define DMA1_STRIDE_D_STRIDE_BITS 31:16
#define DMA1_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA1_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA1_STRIDE_D_STRIDE_MSB 31
#define DMA1_STRIDE_D_STRIDE_LSB 16
#define DMA1_STRIDE_S_STRIDE_BITS 15:0
#define DMA1_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA1_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA1_STRIDE_S_STRIDE_MSB 15
#define DMA1_STRIDE_S_STRIDE_LSB 0
#define DMA1_NEXTCONBK HW_REGISTER_RO( 0x7e00711c )
#define DMA1_NEXTCONBK_MASK 0xffffffe0
#define DMA1_NEXTCONBK_WIDTH 32
#define DMA1_NEXTCONBK_ADDR_BITS 31:5
#define DMA1_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA1_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA1_NEXTCONBK_ADDR_MSB 31
#define DMA1_NEXTCONBK_ADDR_LSB 5
#define DMA1_DEBUG HW_REGISTER_RW( 0x7e007120 )
#define DMA1_DEBUG_MASK 0x1ffffff7
#define DMA1_DEBUG_WIDTH 29
#define DMA1_DEBUG_RESET 0000000000
#define DMA1_DEBUG_LITE_BITS 28:28
#define DMA1_DEBUG_LITE_SET 0x10000000
#define DMA1_DEBUG_LITE_CLR 0xefffffff
#define DMA1_DEBUG_LITE_MSB 28
#define DMA1_DEBUG_LITE_LSB 28
#define DMA1_DEBUG_VERSION_BITS 27:25
#define DMA1_DEBUG_VERSION_SET 0x0e000000
#define DMA1_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA1_DEBUG_VERSION_MSB 27
#define DMA1_DEBUG_VERSION_LSB 25
#define DMA1_DEBUG_DMA_STATE_BITS 24:16
#define DMA1_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA1_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA1_DEBUG_DMA_STATE_MSB 24
#define DMA1_DEBUG_DMA_STATE_LSB 16
#define DMA1_DEBUG_DMA_ID_BITS 15:8
#define DMA1_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA1_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA1_DEBUG_DMA_ID_MSB 15
#define DMA1_DEBUG_DMA_ID_LSB 8
#define DMA1_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA1_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA1_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA1_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA1_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA1_DEBUG_READ_ERROR_BITS 2:2
#define DMA1_DEBUG_READ_ERROR_SET 0x00000004
#define DMA1_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA1_DEBUG_READ_ERROR_MSB 2
#define DMA1_DEBUG_READ_ERROR_LSB 2
#define DMA1_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA1_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA1_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA1_DEBUG_FIFO_ERROR_MSB 1
#define DMA1_DEBUG_FIFO_ERROR_LSB 1
#define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA1_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma15.h Executable file
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// This file was generated by the create_regs script
#define DMA15_BASE 0x7ee05000
#define DMA15_CS HW_REGISTER_RW( 0x7ee05000 )
#define DMA15_CS_MASK 0xf0ff017f
#define DMA15_CS_WIDTH 32
#define DMA15_CS_RESET 0000000000
#define DMA15_CS_RESET_BITS 31:31
#define DMA15_CS_RESET_SET 0x80000000
#define DMA15_CS_RESET_CLR 0x7fffffff
#define DMA15_CS_RESET_MSB 31
#define DMA15_CS_RESET_LSB 31
#define DMA15_CS_ABORT_BITS 30:30
#define DMA15_CS_ABORT_SET 0x40000000
#define DMA15_CS_ABORT_CLR 0xbfffffff
#define DMA15_CS_ABORT_MSB 30
#define DMA15_CS_ABORT_LSB 30
#define DMA15_CS_DISDEBUG_BITS 29:29
#define DMA15_CS_DISDEBUG_SET 0x20000000
#define DMA15_CS_DISDEBUG_CLR 0xdfffffff
#define DMA15_CS_DISDEBUG_MSB 29
#define DMA15_CS_DISDEBUG_LSB 29
#define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA15_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA15_CS_PANIC_PRIORITY_BITS 23:20
#define DMA15_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA15_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA15_CS_PANIC_PRIORITY_MSB 23
#define DMA15_CS_PANIC_PRIORITY_LSB 20
#define DMA15_CS_PRIORITY_BITS 19:16
#define DMA15_CS_PRIORITY_SET 0x000f0000
#define DMA15_CS_PRIORITY_CLR 0xfff0ffff
#define DMA15_CS_PRIORITY_MSB 19
#define DMA15_CS_PRIORITY_LSB 16
#define DMA15_CS_ERROR_BITS 8:8
#define DMA15_CS_ERROR_SET 0x00000100
#define DMA15_CS_ERROR_CLR 0xfffffeff
#define DMA15_CS_ERROR_MSB 8
#define DMA15_CS_ERROR_LSB 8
#define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA15_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA15_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA15_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA15_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA15_CS_DREQ_STOPS_DMA_MSB 5
#define DMA15_CS_DREQ_STOPS_DMA_LSB 5
#define DMA15_CS_PAUSED_BITS 4:4
#define DMA15_CS_PAUSED_SET 0x00000010
#define DMA15_CS_PAUSED_CLR 0xffffffef
#define DMA15_CS_PAUSED_MSB 4
#define DMA15_CS_PAUSED_LSB 4
#define DMA15_CS_DREQ_BITS 3:3
#define DMA15_CS_DREQ_SET 0x00000008
#define DMA15_CS_DREQ_CLR 0xfffffff7
#define DMA15_CS_DREQ_MSB 3
#define DMA15_CS_DREQ_LSB 3
#define DMA15_CS_INT_BITS 2:2
#define DMA15_CS_INT_SET 0x00000004
#define DMA15_CS_INT_CLR 0xfffffffb
#define DMA15_CS_INT_MSB 2
#define DMA15_CS_INT_LSB 2
#define DMA15_CS_END_BITS 1:1
#define DMA15_CS_END_SET 0x00000002
#define DMA15_CS_END_CLR 0xfffffffd
#define DMA15_CS_END_MSB 1
#define DMA15_CS_END_LSB 1
#define DMA15_CS_ACTIVE_BITS 0:0
#define DMA15_CS_ACTIVE_SET 0x00000001
#define DMA15_CS_ACTIVE_CLR 0xfffffffe
#define DMA15_CS_ACTIVE_MSB 0
#define DMA15_CS_ACTIVE_LSB 0
#define DMA15_CONBLK_AD HW_REGISTER_RW( 0x7ee05004 )
#define DMA15_CONBLK_AD_MASK 0xffffffe0
#define DMA15_CONBLK_AD_WIDTH 32
#define DMA15_CONBLK_AD_RESET 0000000000
#define DMA15_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA15_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA15_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA15_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA15_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA15_TI HW_REGISTER_RO( 0x7ee05008 )
#define DMA15_TI_MASK 0x07fffffb
#define DMA15_TI_WIDTH 27
#define DMA15_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA15_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA15_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA15_TI_NO_WIDE_BURSTS_MSB 26
#define DMA15_TI_NO_WIDE_BURSTS_LSB 26
#define DMA15_TI_WAITS_BITS 25:21
#define DMA15_TI_WAITS_SET 0x03e00000
#define DMA15_TI_WAITS_CLR 0xfc1fffff
#define DMA15_TI_WAITS_MSB 25
#define DMA15_TI_WAITS_LSB 21
#define DMA15_TI_PERMAP_BITS 20:16
#define DMA15_TI_PERMAP_SET 0x001f0000
#define DMA15_TI_PERMAP_CLR 0xffe0ffff
#define DMA15_TI_PERMAP_MSB 20
#define DMA15_TI_PERMAP_LSB 16
#define DMA15_TI_BURST_LENGTH_BITS 15:12
#define DMA15_TI_BURST_LENGTH_SET 0x0000f000
#define DMA15_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA15_TI_BURST_LENGTH_MSB 15
#define DMA15_TI_BURST_LENGTH_LSB 12
#define DMA15_TI_SRC_IGNORE_BITS 11:11
#define DMA15_TI_SRC_IGNORE_SET 0x00000800
#define DMA15_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA15_TI_SRC_IGNORE_MSB 11
#define DMA15_TI_SRC_IGNORE_LSB 11
#define DMA15_TI_SRC_DREQ_BITS 10:10
#define DMA15_TI_SRC_DREQ_SET 0x00000400
#define DMA15_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA15_TI_SRC_DREQ_MSB 10
#define DMA15_TI_SRC_DREQ_LSB 10
#define DMA15_TI_SRC_WIDTH_BITS 9:9
#define DMA15_TI_SRC_WIDTH_SET 0x00000200
#define DMA15_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA15_TI_SRC_WIDTH_MSB 9
#define DMA15_TI_SRC_WIDTH_LSB 9
#define DMA15_TI_SRC_INC_BITS 8:8
#define DMA15_TI_SRC_INC_SET 0x00000100
#define DMA15_TI_SRC_INC_CLR 0xfffffeff
#define DMA15_TI_SRC_INC_MSB 8
#define DMA15_TI_SRC_INC_LSB 8
#define DMA15_TI_DEST_IGNORE_BITS 7:7
#define DMA15_TI_DEST_IGNORE_SET 0x00000080
#define DMA15_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA15_TI_DEST_IGNORE_MSB 7
#define DMA15_TI_DEST_IGNORE_LSB 7
#define DMA15_TI_DEST_DREQ_BITS 6:6
#define DMA15_TI_DEST_DREQ_SET 0x00000040
#define DMA15_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA15_TI_DEST_DREQ_MSB 6
#define DMA15_TI_DEST_DREQ_LSB 6
#define DMA15_TI_DEST_WIDTH_BITS 5:5
#define DMA15_TI_DEST_WIDTH_SET 0x00000020
#define DMA15_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA15_TI_DEST_WIDTH_MSB 5
#define DMA15_TI_DEST_WIDTH_LSB 5
#define DMA15_TI_DEST_INC_BITS 4:4
#define DMA15_TI_DEST_INC_SET 0x00000010
#define DMA15_TI_DEST_INC_CLR 0xffffffef
#define DMA15_TI_DEST_INC_MSB 4
#define DMA15_TI_DEST_INC_LSB 4
#define DMA15_TI_WAIT_RESP_BITS 3:3
#define DMA15_TI_WAIT_RESP_SET 0x00000008
#define DMA15_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA15_TI_WAIT_RESP_MSB 3
#define DMA15_TI_WAIT_RESP_LSB 3
#define DMA15_TI_TDMODE_BITS 1:1
#define DMA15_TI_TDMODE_SET 0x00000002
#define DMA15_TI_TDMODE_CLR 0xfffffffd
#define DMA15_TI_TDMODE_MSB 1
#define DMA15_TI_TDMODE_LSB 1
#define DMA15_TI_INTEN_BITS 0:0
#define DMA15_TI_INTEN_SET 0x00000001
#define DMA15_TI_INTEN_CLR 0xfffffffe
#define DMA15_TI_INTEN_MSB 0
#define DMA15_TI_INTEN_LSB 0
#define DMA15_SOURCE_AD HW_REGISTER_RO( 0x7ee0500c )
#define DMA15_SOURCE_AD_MASK 0xffffffff
#define DMA15_SOURCE_AD_WIDTH 32
#define DMA15_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA15_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA15_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA15_SOURCE_AD_S_ADDR_MSB 31
#define DMA15_SOURCE_AD_S_ADDR_LSB 0
#define DMA15_DEST_AD HW_REGISTER_RO( 0x7ee05010 )
#define DMA15_DEST_AD_MASK 0xffffffff
#define DMA15_DEST_AD_WIDTH 32
#define DMA15_DEST_AD_D_ADDR_BITS 31:0
#define DMA15_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA15_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA15_DEST_AD_D_ADDR_MSB 31
#define DMA15_DEST_AD_D_ADDR_LSB 0
#define DMA15_TXFR_LEN HW_REGISTER_RO( 0x7ee05014 )
#define DMA15_TXFR_LEN_MASK 0x3fffffff
#define DMA15_TXFR_LEN_WIDTH 30
#define DMA15_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA15_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA15_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA15_TXFR_LEN_YLENGTH_MSB 29
#define DMA15_TXFR_LEN_YLENGTH_LSB 16
#define DMA15_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA15_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA15_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA15_TXFR_LEN_XLENGTH_MSB 15
#define DMA15_TXFR_LEN_XLENGTH_LSB 0
#define DMA15_STRIDE HW_REGISTER_RO( 0x7ee05018 )
#define DMA15_STRIDE_MASK 0xffffffff
#define DMA15_STRIDE_WIDTH 32
#define DMA15_STRIDE_D_STRIDE_BITS 31:16
#define DMA15_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA15_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA15_STRIDE_D_STRIDE_MSB 31
#define DMA15_STRIDE_D_STRIDE_LSB 16
#define DMA15_STRIDE_S_STRIDE_BITS 15:0
#define DMA15_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA15_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA15_STRIDE_S_STRIDE_MSB 15
#define DMA15_STRIDE_S_STRIDE_LSB 0
#define DMA15_NEXTCONBK HW_REGISTER_RO( 0x7ee0501c )
#define DMA15_NEXTCONBK_MASK 0xffffffe0
#define DMA15_NEXTCONBK_WIDTH 32
#define DMA15_NEXTCONBK_ADDR_BITS 31:5
#define DMA15_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA15_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA15_NEXTCONBK_ADDR_MSB 31
#define DMA15_NEXTCONBK_ADDR_LSB 5
#define DMA15_DEBUG HW_REGISTER_RW( 0x7ee05020 )
#define DMA15_DEBUG_MASK 0x1ffffff7
#define DMA15_DEBUG_WIDTH 29
#define DMA15_DEBUG_RESET 0000000000
#define DMA15_DEBUG_LITE_BITS 28:28
#define DMA15_DEBUG_LITE_SET 0x10000000
#define DMA15_DEBUG_LITE_CLR 0xefffffff
#define DMA15_DEBUG_LITE_MSB 28
#define DMA15_DEBUG_LITE_LSB 28
#define DMA15_DEBUG_VERSION_BITS 27:25
#define DMA15_DEBUG_VERSION_SET 0x0e000000
#define DMA15_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA15_DEBUG_VERSION_MSB 27
#define DMA15_DEBUG_VERSION_LSB 25
#define DMA15_DEBUG_DMA_STATE_BITS 24:16
#define DMA15_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA15_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA15_DEBUG_DMA_STATE_MSB 24
#define DMA15_DEBUG_DMA_STATE_LSB 16
#define DMA15_DEBUG_DMA_ID_BITS 15:8
#define DMA15_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA15_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA15_DEBUG_DMA_ID_MSB 15
#define DMA15_DEBUG_DMA_ID_LSB 8
#define DMA15_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA15_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA15_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA15_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA15_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA15_DEBUG_READ_ERROR_BITS 2:2
#define DMA15_DEBUG_READ_ERROR_SET 0x00000004
#define DMA15_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA15_DEBUG_READ_ERROR_MSB 2
#define DMA15_DEBUG_READ_ERROR_LSB 2
#define DMA15_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA15_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA15_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA15_DEBUG_FIFO_ERROR_MSB 1
#define DMA15_DEBUG_FIFO_ERROR_LSB 1
#define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA15_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma2.h Executable file
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// This file was generated by the create_regs script
#define DMA2_BASE 0x7e007200
#define DMA2_CS HW_REGISTER_RW( 0x7e007200 )
#define DMA2_CS_MASK 0xf0ff017f
#define DMA2_CS_WIDTH 32
#define DMA2_CS_RESET 0000000000
#define DMA2_CS_RESET_BITS 31:31
#define DMA2_CS_RESET_SET 0x80000000
#define DMA2_CS_RESET_CLR 0x7fffffff
#define DMA2_CS_RESET_MSB 31
#define DMA2_CS_RESET_LSB 31
#define DMA2_CS_ABORT_BITS 30:30
#define DMA2_CS_ABORT_SET 0x40000000
#define DMA2_CS_ABORT_CLR 0xbfffffff
#define DMA2_CS_ABORT_MSB 30
#define DMA2_CS_ABORT_LSB 30
#define DMA2_CS_DISDEBUG_BITS 29:29
#define DMA2_CS_DISDEBUG_SET 0x20000000
#define DMA2_CS_DISDEBUG_CLR 0xdfffffff
#define DMA2_CS_DISDEBUG_MSB 29
#define DMA2_CS_DISDEBUG_LSB 29
#define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA2_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA2_CS_PANIC_PRIORITY_BITS 23:20
#define DMA2_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA2_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA2_CS_PANIC_PRIORITY_MSB 23
#define DMA2_CS_PANIC_PRIORITY_LSB 20
#define DMA2_CS_PRIORITY_BITS 19:16
#define DMA2_CS_PRIORITY_SET 0x000f0000
#define DMA2_CS_PRIORITY_CLR 0xfff0ffff
#define DMA2_CS_PRIORITY_MSB 19
#define DMA2_CS_PRIORITY_LSB 16
#define DMA2_CS_ERROR_BITS 8:8
#define DMA2_CS_ERROR_SET 0x00000100
#define DMA2_CS_ERROR_CLR 0xfffffeff
#define DMA2_CS_ERROR_MSB 8
#define DMA2_CS_ERROR_LSB 8
#define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA2_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA2_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA2_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA2_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA2_CS_DREQ_STOPS_DMA_MSB 5
#define DMA2_CS_DREQ_STOPS_DMA_LSB 5
#define DMA2_CS_PAUSED_BITS 4:4
#define DMA2_CS_PAUSED_SET 0x00000010
#define DMA2_CS_PAUSED_CLR 0xffffffef
#define DMA2_CS_PAUSED_MSB 4
#define DMA2_CS_PAUSED_LSB 4
#define DMA2_CS_DREQ_BITS 3:3
#define DMA2_CS_DREQ_SET 0x00000008
#define DMA2_CS_DREQ_CLR 0xfffffff7
#define DMA2_CS_DREQ_MSB 3
#define DMA2_CS_DREQ_LSB 3
#define DMA2_CS_INT_BITS 2:2
#define DMA2_CS_INT_SET 0x00000004
#define DMA2_CS_INT_CLR 0xfffffffb
#define DMA2_CS_INT_MSB 2
#define DMA2_CS_INT_LSB 2
#define DMA2_CS_END_BITS 1:1
#define DMA2_CS_END_SET 0x00000002
#define DMA2_CS_END_CLR 0xfffffffd
#define DMA2_CS_END_MSB 1
#define DMA2_CS_END_LSB 1
#define DMA2_CS_ACTIVE_BITS 0:0
#define DMA2_CS_ACTIVE_SET 0x00000001
#define DMA2_CS_ACTIVE_CLR 0xfffffffe
#define DMA2_CS_ACTIVE_MSB 0
#define DMA2_CS_ACTIVE_LSB 0
#define DMA2_CONBLK_AD HW_REGISTER_RW( 0x7e007204 )
#define DMA2_CONBLK_AD_MASK 0xffffffe0
#define DMA2_CONBLK_AD_WIDTH 32
#define DMA2_CONBLK_AD_RESET 0000000000
#define DMA2_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA2_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA2_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA2_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA2_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA2_TI HW_REGISTER_RO( 0x7e007208 )
#define DMA2_TI_MASK 0x07fffffb
#define DMA2_TI_WIDTH 27
#define DMA2_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA2_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA2_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA2_TI_NO_WIDE_BURSTS_MSB 26
#define DMA2_TI_NO_WIDE_BURSTS_LSB 26
#define DMA2_TI_WAITS_BITS 25:21
#define DMA2_TI_WAITS_SET 0x03e00000
#define DMA2_TI_WAITS_CLR 0xfc1fffff
#define DMA2_TI_WAITS_MSB 25
#define DMA2_TI_WAITS_LSB 21
#define DMA2_TI_PERMAP_BITS 20:16
#define DMA2_TI_PERMAP_SET 0x001f0000
#define DMA2_TI_PERMAP_CLR 0xffe0ffff
#define DMA2_TI_PERMAP_MSB 20
#define DMA2_TI_PERMAP_LSB 16
#define DMA2_TI_BURST_LENGTH_BITS 15:12
#define DMA2_TI_BURST_LENGTH_SET 0x0000f000
#define DMA2_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA2_TI_BURST_LENGTH_MSB 15
#define DMA2_TI_BURST_LENGTH_LSB 12
#define DMA2_TI_SRC_IGNORE_BITS 11:11
#define DMA2_TI_SRC_IGNORE_SET 0x00000800
#define DMA2_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA2_TI_SRC_IGNORE_MSB 11
#define DMA2_TI_SRC_IGNORE_LSB 11
#define DMA2_TI_SRC_DREQ_BITS 10:10
#define DMA2_TI_SRC_DREQ_SET 0x00000400
#define DMA2_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA2_TI_SRC_DREQ_MSB 10
#define DMA2_TI_SRC_DREQ_LSB 10
#define DMA2_TI_SRC_WIDTH_BITS 9:9
#define DMA2_TI_SRC_WIDTH_SET 0x00000200
#define DMA2_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA2_TI_SRC_WIDTH_MSB 9
#define DMA2_TI_SRC_WIDTH_LSB 9
#define DMA2_TI_SRC_INC_BITS 8:8
#define DMA2_TI_SRC_INC_SET 0x00000100
#define DMA2_TI_SRC_INC_CLR 0xfffffeff
#define DMA2_TI_SRC_INC_MSB 8
#define DMA2_TI_SRC_INC_LSB 8
#define DMA2_TI_DEST_IGNORE_BITS 7:7
#define DMA2_TI_DEST_IGNORE_SET 0x00000080
#define DMA2_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA2_TI_DEST_IGNORE_MSB 7
#define DMA2_TI_DEST_IGNORE_LSB 7
#define DMA2_TI_DEST_DREQ_BITS 6:6
#define DMA2_TI_DEST_DREQ_SET 0x00000040
#define DMA2_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA2_TI_DEST_DREQ_MSB 6
#define DMA2_TI_DEST_DREQ_LSB 6
#define DMA2_TI_DEST_WIDTH_BITS 5:5
#define DMA2_TI_DEST_WIDTH_SET 0x00000020
#define DMA2_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA2_TI_DEST_WIDTH_MSB 5
#define DMA2_TI_DEST_WIDTH_LSB 5
#define DMA2_TI_DEST_INC_BITS 4:4
#define DMA2_TI_DEST_INC_SET 0x00000010
#define DMA2_TI_DEST_INC_CLR 0xffffffef
#define DMA2_TI_DEST_INC_MSB 4
#define DMA2_TI_DEST_INC_LSB 4
#define DMA2_TI_WAIT_RESP_BITS 3:3
#define DMA2_TI_WAIT_RESP_SET 0x00000008
#define DMA2_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA2_TI_WAIT_RESP_MSB 3
#define DMA2_TI_WAIT_RESP_LSB 3
#define DMA2_TI_TDMODE_BITS 1:1
#define DMA2_TI_TDMODE_SET 0x00000002
#define DMA2_TI_TDMODE_CLR 0xfffffffd
#define DMA2_TI_TDMODE_MSB 1
#define DMA2_TI_TDMODE_LSB 1
#define DMA2_TI_INTEN_BITS 0:0
#define DMA2_TI_INTEN_SET 0x00000001
#define DMA2_TI_INTEN_CLR 0xfffffffe
#define DMA2_TI_INTEN_MSB 0
#define DMA2_TI_INTEN_LSB 0
#define DMA2_SOURCE_AD HW_REGISTER_RO( 0x7e00720c )
#define DMA2_SOURCE_AD_MASK 0xffffffff
#define DMA2_SOURCE_AD_WIDTH 32
#define DMA2_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA2_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA2_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA2_SOURCE_AD_S_ADDR_MSB 31
#define DMA2_SOURCE_AD_S_ADDR_LSB 0
#define DMA2_DEST_AD HW_REGISTER_RO( 0x7e007210 )
#define DMA2_DEST_AD_MASK 0xffffffff
#define DMA2_DEST_AD_WIDTH 32
#define DMA2_DEST_AD_D_ADDR_BITS 31:0
#define DMA2_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA2_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA2_DEST_AD_D_ADDR_MSB 31
#define DMA2_DEST_AD_D_ADDR_LSB 0
#define DMA2_TXFR_LEN HW_REGISTER_RO( 0x7e007214 )
#define DMA2_TXFR_LEN_MASK 0x3fffffff
#define DMA2_TXFR_LEN_WIDTH 30
#define DMA2_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA2_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA2_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA2_TXFR_LEN_YLENGTH_MSB 29
#define DMA2_TXFR_LEN_YLENGTH_LSB 16
#define DMA2_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA2_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA2_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA2_TXFR_LEN_XLENGTH_MSB 15
#define DMA2_TXFR_LEN_XLENGTH_LSB 0
#define DMA2_STRIDE HW_REGISTER_RO( 0x7e007218 )
#define DMA2_STRIDE_MASK 0xffffffff
#define DMA2_STRIDE_WIDTH 32
#define DMA2_STRIDE_D_STRIDE_BITS 31:16
#define DMA2_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA2_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA2_STRIDE_D_STRIDE_MSB 31
#define DMA2_STRIDE_D_STRIDE_LSB 16
#define DMA2_STRIDE_S_STRIDE_BITS 15:0
#define DMA2_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA2_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA2_STRIDE_S_STRIDE_MSB 15
#define DMA2_STRIDE_S_STRIDE_LSB 0
#define DMA2_NEXTCONBK HW_REGISTER_RO( 0x7e00721c )
#define DMA2_NEXTCONBK_MASK 0xffffffe0
#define DMA2_NEXTCONBK_WIDTH 32
#define DMA2_NEXTCONBK_ADDR_BITS 31:5
#define DMA2_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA2_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA2_NEXTCONBK_ADDR_MSB 31
#define DMA2_NEXTCONBK_ADDR_LSB 5
#define DMA2_DEBUG HW_REGISTER_RW( 0x7e007220 )
#define DMA2_DEBUG_MASK 0x1ffffff7
#define DMA2_DEBUG_WIDTH 29
#define DMA2_DEBUG_RESET 0000000000
#define DMA2_DEBUG_LITE_BITS 28:28
#define DMA2_DEBUG_LITE_SET 0x10000000
#define DMA2_DEBUG_LITE_CLR 0xefffffff
#define DMA2_DEBUG_LITE_MSB 28
#define DMA2_DEBUG_LITE_LSB 28
#define DMA2_DEBUG_VERSION_BITS 27:25
#define DMA2_DEBUG_VERSION_SET 0x0e000000
#define DMA2_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA2_DEBUG_VERSION_MSB 27
#define DMA2_DEBUG_VERSION_LSB 25
#define DMA2_DEBUG_DMA_STATE_BITS 24:16
#define DMA2_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA2_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA2_DEBUG_DMA_STATE_MSB 24
#define DMA2_DEBUG_DMA_STATE_LSB 16
#define DMA2_DEBUG_DMA_ID_BITS 15:8
#define DMA2_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA2_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA2_DEBUG_DMA_ID_MSB 15
#define DMA2_DEBUG_DMA_ID_LSB 8
#define DMA2_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA2_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA2_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA2_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA2_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA2_DEBUG_READ_ERROR_BITS 2:2
#define DMA2_DEBUG_READ_ERROR_SET 0x00000004
#define DMA2_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA2_DEBUG_READ_ERROR_MSB 2
#define DMA2_DEBUG_READ_ERROR_LSB 2
#define DMA2_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA2_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA2_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA2_DEBUG_FIFO_ERROR_MSB 1
#define DMA2_DEBUG_FIFO_ERROR_LSB 1
#define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA2_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma3.h Executable file
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// This file was generated by the create_regs script
#define DMA3_BASE 0x7e007300
#define DMA3_CS HW_REGISTER_RW( 0x7e007300 )
#define DMA3_CS_MASK 0xf0ff017f
#define DMA3_CS_WIDTH 32
#define DMA3_CS_RESET 0000000000
#define DMA3_CS_RESET_BITS 31:31
#define DMA3_CS_RESET_SET 0x80000000
#define DMA3_CS_RESET_CLR 0x7fffffff
#define DMA3_CS_RESET_MSB 31
#define DMA3_CS_RESET_LSB 31
#define DMA3_CS_ABORT_BITS 30:30
#define DMA3_CS_ABORT_SET 0x40000000
#define DMA3_CS_ABORT_CLR 0xbfffffff
#define DMA3_CS_ABORT_MSB 30
#define DMA3_CS_ABORT_LSB 30
#define DMA3_CS_DISDEBUG_BITS 29:29
#define DMA3_CS_DISDEBUG_SET 0x20000000
#define DMA3_CS_DISDEBUG_CLR 0xdfffffff
#define DMA3_CS_DISDEBUG_MSB 29
#define DMA3_CS_DISDEBUG_LSB 29
#define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA3_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA3_CS_PANIC_PRIORITY_BITS 23:20
#define DMA3_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA3_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA3_CS_PANIC_PRIORITY_MSB 23
#define DMA3_CS_PANIC_PRIORITY_LSB 20
#define DMA3_CS_PRIORITY_BITS 19:16
#define DMA3_CS_PRIORITY_SET 0x000f0000
#define DMA3_CS_PRIORITY_CLR 0xfff0ffff
#define DMA3_CS_PRIORITY_MSB 19
#define DMA3_CS_PRIORITY_LSB 16
#define DMA3_CS_ERROR_BITS 8:8
#define DMA3_CS_ERROR_SET 0x00000100
#define DMA3_CS_ERROR_CLR 0xfffffeff
#define DMA3_CS_ERROR_MSB 8
#define DMA3_CS_ERROR_LSB 8
#define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA3_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA3_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA3_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA3_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA3_CS_DREQ_STOPS_DMA_MSB 5
#define DMA3_CS_DREQ_STOPS_DMA_LSB 5
#define DMA3_CS_PAUSED_BITS 4:4
#define DMA3_CS_PAUSED_SET 0x00000010
#define DMA3_CS_PAUSED_CLR 0xffffffef
#define DMA3_CS_PAUSED_MSB 4
#define DMA3_CS_PAUSED_LSB 4
#define DMA3_CS_DREQ_BITS 3:3
#define DMA3_CS_DREQ_SET 0x00000008
#define DMA3_CS_DREQ_CLR 0xfffffff7
#define DMA3_CS_DREQ_MSB 3
#define DMA3_CS_DREQ_LSB 3
#define DMA3_CS_INT_BITS 2:2
#define DMA3_CS_INT_SET 0x00000004
#define DMA3_CS_INT_CLR 0xfffffffb
#define DMA3_CS_INT_MSB 2
#define DMA3_CS_INT_LSB 2
#define DMA3_CS_END_BITS 1:1
#define DMA3_CS_END_SET 0x00000002
#define DMA3_CS_END_CLR 0xfffffffd
#define DMA3_CS_END_MSB 1
#define DMA3_CS_END_LSB 1
#define DMA3_CS_ACTIVE_BITS 0:0
#define DMA3_CS_ACTIVE_SET 0x00000001
#define DMA3_CS_ACTIVE_CLR 0xfffffffe
#define DMA3_CS_ACTIVE_MSB 0
#define DMA3_CS_ACTIVE_LSB 0
#define DMA3_CONBLK_AD HW_REGISTER_RW( 0x7e007304 )
#define DMA3_CONBLK_AD_MASK 0xffffffe0
#define DMA3_CONBLK_AD_WIDTH 32
#define DMA3_CONBLK_AD_RESET 0000000000
#define DMA3_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA3_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA3_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA3_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA3_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA3_TI HW_REGISTER_RO( 0x7e007308 )
#define DMA3_TI_MASK 0x07fffffb
#define DMA3_TI_WIDTH 27
#define DMA3_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA3_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA3_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA3_TI_NO_WIDE_BURSTS_MSB 26
#define DMA3_TI_NO_WIDE_BURSTS_LSB 26
#define DMA3_TI_WAITS_BITS 25:21
#define DMA3_TI_WAITS_SET 0x03e00000
#define DMA3_TI_WAITS_CLR 0xfc1fffff
#define DMA3_TI_WAITS_MSB 25
#define DMA3_TI_WAITS_LSB 21
#define DMA3_TI_PERMAP_BITS 20:16
#define DMA3_TI_PERMAP_SET 0x001f0000
#define DMA3_TI_PERMAP_CLR 0xffe0ffff
#define DMA3_TI_PERMAP_MSB 20
#define DMA3_TI_PERMAP_LSB 16
#define DMA3_TI_BURST_LENGTH_BITS 15:12
#define DMA3_TI_BURST_LENGTH_SET 0x0000f000
#define DMA3_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA3_TI_BURST_LENGTH_MSB 15
#define DMA3_TI_BURST_LENGTH_LSB 12
#define DMA3_TI_SRC_IGNORE_BITS 11:11
#define DMA3_TI_SRC_IGNORE_SET 0x00000800
#define DMA3_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA3_TI_SRC_IGNORE_MSB 11
#define DMA3_TI_SRC_IGNORE_LSB 11
#define DMA3_TI_SRC_DREQ_BITS 10:10
#define DMA3_TI_SRC_DREQ_SET 0x00000400
#define DMA3_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA3_TI_SRC_DREQ_MSB 10
#define DMA3_TI_SRC_DREQ_LSB 10
#define DMA3_TI_SRC_WIDTH_BITS 9:9
#define DMA3_TI_SRC_WIDTH_SET 0x00000200
#define DMA3_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA3_TI_SRC_WIDTH_MSB 9
#define DMA3_TI_SRC_WIDTH_LSB 9
#define DMA3_TI_SRC_INC_BITS 8:8
#define DMA3_TI_SRC_INC_SET 0x00000100
#define DMA3_TI_SRC_INC_CLR 0xfffffeff
#define DMA3_TI_SRC_INC_MSB 8
#define DMA3_TI_SRC_INC_LSB 8
#define DMA3_TI_DEST_IGNORE_BITS 7:7
#define DMA3_TI_DEST_IGNORE_SET 0x00000080
#define DMA3_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA3_TI_DEST_IGNORE_MSB 7
#define DMA3_TI_DEST_IGNORE_LSB 7
#define DMA3_TI_DEST_DREQ_BITS 6:6
#define DMA3_TI_DEST_DREQ_SET 0x00000040
#define DMA3_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA3_TI_DEST_DREQ_MSB 6
#define DMA3_TI_DEST_DREQ_LSB 6
#define DMA3_TI_DEST_WIDTH_BITS 5:5
#define DMA3_TI_DEST_WIDTH_SET 0x00000020
#define DMA3_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA3_TI_DEST_WIDTH_MSB 5
#define DMA3_TI_DEST_WIDTH_LSB 5
#define DMA3_TI_DEST_INC_BITS 4:4
#define DMA3_TI_DEST_INC_SET 0x00000010
#define DMA3_TI_DEST_INC_CLR 0xffffffef
#define DMA3_TI_DEST_INC_MSB 4
#define DMA3_TI_DEST_INC_LSB 4
#define DMA3_TI_WAIT_RESP_BITS 3:3
#define DMA3_TI_WAIT_RESP_SET 0x00000008
#define DMA3_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA3_TI_WAIT_RESP_MSB 3
#define DMA3_TI_WAIT_RESP_LSB 3
#define DMA3_TI_TDMODE_BITS 1:1
#define DMA3_TI_TDMODE_SET 0x00000002
#define DMA3_TI_TDMODE_CLR 0xfffffffd
#define DMA3_TI_TDMODE_MSB 1
#define DMA3_TI_TDMODE_LSB 1
#define DMA3_TI_INTEN_BITS 0:0
#define DMA3_TI_INTEN_SET 0x00000001
#define DMA3_TI_INTEN_CLR 0xfffffffe
#define DMA3_TI_INTEN_MSB 0
#define DMA3_TI_INTEN_LSB 0
#define DMA3_SOURCE_AD HW_REGISTER_RO( 0x7e00730c )
#define DMA3_SOURCE_AD_MASK 0xffffffff
#define DMA3_SOURCE_AD_WIDTH 32
#define DMA3_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA3_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA3_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA3_SOURCE_AD_S_ADDR_MSB 31
#define DMA3_SOURCE_AD_S_ADDR_LSB 0
#define DMA3_DEST_AD HW_REGISTER_RO( 0x7e007310 )
#define DMA3_DEST_AD_MASK 0xffffffff
#define DMA3_DEST_AD_WIDTH 32
#define DMA3_DEST_AD_D_ADDR_BITS 31:0
#define DMA3_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA3_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA3_DEST_AD_D_ADDR_MSB 31
#define DMA3_DEST_AD_D_ADDR_LSB 0
#define DMA3_TXFR_LEN HW_REGISTER_RO( 0x7e007314 )
#define DMA3_TXFR_LEN_MASK 0x3fffffff
#define DMA3_TXFR_LEN_WIDTH 30
#define DMA3_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA3_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA3_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA3_TXFR_LEN_YLENGTH_MSB 29
#define DMA3_TXFR_LEN_YLENGTH_LSB 16
#define DMA3_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA3_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA3_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA3_TXFR_LEN_XLENGTH_MSB 15
#define DMA3_TXFR_LEN_XLENGTH_LSB 0
#define DMA3_STRIDE HW_REGISTER_RO( 0x7e007318 )
#define DMA3_STRIDE_MASK 0xffffffff
#define DMA3_STRIDE_WIDTH 32
#define DMA3_STRIDE_D_STRIDE_BITS 31:16
#define DMA3_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA3_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA3_STRIDE_D_STRIDE_MSB 31
#define DMA3_STRIDE_D_STRIDE_LSB 16
#define DMA3_STRIDE_S_STRIDE_BITS 15:0
#define DMA3_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA3_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA3_STRIDE_S_STRIDE_MSB 15
#define DMA3_STRIDE_S_STRIDE_LSB 0
#define DMA3_NEXTCONBK HW_REGISTER_RO( 0x7e00731c )
#define DMA3_NEXTCONBK_MASK 0xffffffe0
#define DMA3_NEXTCONBK_WIDTH 32
#define DMA3_NEXTCONBK_ADDR_BITS 31:5
#define DMA3_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA3_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA3_NEXTCONBK_ADDR_MSB 31
#define DMA3_NEXTCONBK_ADDR_LSB 5
#define DMA3_DEBUG HW_REGISTER_RW( 0x7e007320 )
#define DMA3_DEBUG_MASK 0x1ffffff7
#define DMA3_DEBUG_WIDTH 29
#define DMA3_DEBUG_RESET 0000000000
#define DMA3_DEBUG_LITE_BITS 28:28
#define DMA3_DEBUG_LITE_SET 0x10000000
#define DMA3_DEBUG_LITE_CLR 0xefffffff
#define DMA3_DEBUG_LITE_MSB 28
#define DMA3_DEBUG_LITE_LSB 28
#define DMA3_DEBUG_VERSION_BITS 27:25
#define DMA3_DEBUG_VERSION_SET 0x0e000000
#define DMA3_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA3_DEBUG_VERSION_MSB 27
#define DMA3_DEBUG_VERSION_LSB 25
#define DMA3_DEBUG_DMA_STATE_BITS 24:16
#define DMA3_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA3_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA3_DEBUG_DMA_STATE_MSB 24
#define DMA3_DEBUG_DMA_STATE_LSB 16
#define DMA3_DEBUG_DMA_ID_BITS 15:8
#define DMA3_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA3_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA3_DEBUG_DMA_ID_MSB 15
#define DMA3_DEBUG_DMA_ID_LSB 8
#define DMA3_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA3_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA3_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA3_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA3_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA3_DEBUG_READ_ERROR_BITS 2:2
#define DMA3_DEBUG_READ_ERROR_SET 0x00000004
#define DMA3_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA3_DEBUG_READ_ERROR_MSB 2
#define DMA3_DEBUG_READ_ERROR_LSB 2
#define DMA3_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA3_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA3_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA3_DEBUG_FIFO_ERROR_MSB 1
#define DMA3_DEBUG_FIFO_ERROR_LSB 1
#define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA3_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma4.h Executable file
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// This file was generated by the create_regs script
#define DMA4_BASE 0x7e007400
#define DMA4_CS HW_REGISTER_RW( 0x7e007400 )
#define DMA4_CS_MASK 0xf0ff017f
#define DMA4_CS_WIDTH 32
#define DMA4_CS_RESET 0000000000
#define DMA4_CS_RESET_BITS 31:31
#define DMA4_CS_RESET_SET 0x80000000
#define DMA4_CS_RESET_CLR 0x7fffffff
#define DMA4_CS_RESET_MSB 31
#define DMA4_CS_RESET_LSB 31
#define DMA4_CS_ABORT_BITS 30:30
#define DMA4_CS_ABORT_SET 0x40000000
#define DMA4_CS_ABORT_CLR 0xbfffffff
#define DMA4_CS_ABORT_MSB 30
#define DMA4_CS_ABORT_LSB 30
#define DMA4_CS_DISDEBUG_BITS 29:29
#define DMA4_CS_DISDEBUG_SET 0x20000000
#define DMA4_CS_DISDEBUG_CLR 0xdfffffff
#define DMA4_CS_DISDEBUG_MSB 29
#define DMA4_CS_DISDEBUG_LSB 29
#define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA4_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA4_CS_PANIC_PRIORITY_BITS 23:20
#define DMA4_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA4_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA4_CS_PANIC_PRIORITY_MSB 23
#define DMA4_CS_PANIC_PRIORITY_LSB 20
#define DMA4_CS_PRIORITY_BITS 19:16
#define DMA4_CS_PRIORITY_SET 0x000f0000
#define DMA4_CS_PRIORITY_CLR 0xfff0ffff
#define DMA4_CS_PRIORITY_MSB 19
#define DMA4_CS_PRIORITY_LSB 16
#define DMA4_CS_ERROR_BITS 8:8
#define DMA4_CS_ERROR_SET 0x00000100
#define DMA4_CS_ERROR_CLR 0xfffffeff
#define DMA4_CS_ERROR_MSB 8
#define DMA4_CS_ERROR_LSB 8
#define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA4_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA4_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA4_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA4_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA4_CS_DREQ_STOPS_DMA_MSB 5
#define DMA4_CS_DREQ_STOPS_DMA_LSB 5
#define DMA4_CS_PAUSED_BITS 4:4
#define DMA4_CS_PAUSED_SET 0x00000010
#define DMA4_CS_PAUSED_CLR 0xffffffef
#define DMA4_CS_PAUSED_MSB 4
#define DMA4_CS_PAUSED_LSB 4
#define DMA4_CS_DREQ_BITS 3:3
#define DMA4_CS_DREQ_SET 0x00000008
#define DMA4_CS_DREQ_CLR 0xfffffff7
#define DMA4_CS_DREQ_MSB 3
#define DMA4_CS_DREQ_LSB 3
#define DMA4_CS_INT_BITS 2:2
#define DMA4_CS_INT_SET 0x00000004
#define DMA4_CS_INT_CLR 0xfffffffb
#define DMA4_CS_INT_MSB 2
#define DMA4_CS_INT_LSB 2
#define DMA4_CS_END_BITS 1:1
#define DMA4_CS_END_SET 0x00000002
#define DMA4_CS_END_CLR 0xfffffffd
#define DMA4_CS_END_MSB 1
#define DMA4_CS_END_LSB 1
#define DMA4_CS_ACTIVE_BITS 0:0
#define DMA4_CS_ACTIVE_SET 0x00000001
#define DMA4_CS_ACTIVE_CLR 0xfffffffe
#define DMA4_CS_ACTIVE_MSB 0
#define DMA4_CS_ACTIVE_LSB 0
#define DMA4_CONBLK_AD HW_REGISTER_RW( 0x7e007404 )
#define DMA4_CONBLK_AD_MASK 0xffffffe0
#define DMA4_CONBLK_AD_WIDTH 32
#define DMA4_CONBLK_AD_RESET 0000000000
#define DMA4_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA4_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA4_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA4_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA4_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA4_TI HW_REGISTER_RO( 0x7e007408 )
#define DMA4_TI_MASK 0x07fffffb
#define DMA4_TI_WIDTH 27
#define DMA4_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA4_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA4_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA4_TI_NO_WIDE_BURSTS_MSB 26
#define DMA4_TI_NO_WIDE_BURSTS_LSB 26
#define DMA4_TI_WAITS_BITS 25:21
#define DMA4_TI_WAITS_SET 0x03e00000
#define DMA4_TI_WAITS_CLR 0xfc1fffff
#define DMA4_TI_WAITS_MSB 25
#define DMA4_TI_WAITS_LSB 21
#define DMA4_TI_PERMAP_BITS 20:16
#define DMA4_TI_PERMAP_SET 0x001f0000
#define DMA4_TI_PERMAP_CLR 0xffe0ffff
#define DMA4_TI_PERMAP_MSB 20
#define DMA4_TI_PERMAP_LSB 16
#define DMA4_TI_BURST_LENGTH_BITS 15:12
#define DMA4_TI_BURST_LENGTH_SET 0x0000f000
#define DMA4_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA4_TI_BURST_LENGTH_MSB 15
#define DMA4_TI_BURST_LENGTH_LSB 12
#define DMA4_TI_SRC_IGNORE_BITS 11:11
#define DMA4_TI_SRC_IGNORE_SET 0x00000800
#define DMA4_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA4_TI_SRC_IGNORE_MSB 11
#define DMA4_TI_SRC_IGNORE_LSB 11
#define DMA4_TI_SRC_DREQ_BITS 10:10
#define DMA4_TI_SRC_DREQ_SET 0x00000400
#define DMA4_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA4_TI_SRC_DREQ_MSB 10
#define DMA4_TI_SRC_DREQ_LSB 10
#define DMA4_TI_SRC_WIDTH_BITS 9:9
#define DMA4_TI_SRC_WIDTH_SET 0x00000200
#define DMA4_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA4_TI_SRC_WIDTH_MSB 9
#define DMA4_TI_SRC_WIDTH_LSB 9
#define DMA4_TI_SRC_INC_BITS 8:8
#define DMA4_TI_SRC_INC_SET 0x00000100
#define DMA4_TI_SRC_INC_CLR 0xfffffeff
#define DMA4_TI_SRC_INC_MSB 8
#define DMA4_TI_SRC_INC_LSB 8
#define DMA4_TI_DEST_IGNORE_BITS 7:7
#define DMA4_TI_DEST_IGNORE_SET 0x00000080
#define DMA4_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA4_TI_DEST_IGNORE_MSB 7
#define DMA4_TI_DEST_IGNORE_LSB 7
#define DMA4_TI_DEST_DREQ_BITS 6:6
#define DMA4_TI_DEST_DREQ_SET 0x00000040
#define DMA4_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA4_TI_DEST_DREQ_MSB 6
#define DMA4_TI_DEST_DREQ_LSB 6
#define DMA4_TI_DEST_WIDTH_BITS 5:5
#define DMA4_TI_DEST_WIDTH_SET 0x00000020
#define DMA4_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA4_TI_DEST_WIDTH_MSB 5
#define DMA4_TI_DEST_WIDTH_LSB 5
#define DMA4_TI_DEST_INC_BITS 4:4
#define DMA4_TI_DEST_INC_SET 0x00000010
#define DMA4_TI_DEST_INC_CLR 0xffffffef
#define DMA4_TI_DEST_INC_MSB 4
#define DMA4_TI_DEST_INC_LSB 4
#define DMA4_TI_WAIT_RESP_BITS 3:3
#define DMA4_TI_WAIT_RESP_SET 0x00000008
#define DMA4_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA4_TI_WAIT_RESP_MSB 3
#define DMA4_TI_WAIT_RESP_LSB 3
#define DMA4_TI_TDMODE_BITS 1:1
#define DMA4_TI_TDMODE_SET 0x00000002
#define DMA4_TI_TDMODE_CLR 0xfffffffd
#define DMA4_TI_TDMODE_MSB 1
#define DMA4_TI_TDMODE_LSB 1
#define DMA4_TI_INTEN_BITS 0:0
#define DMA4_TI_INTEN_SET 0x00000001
#define DMA4_TI_INTEN_CLR 0xfffffffe
#define DMA4_TI_INTEN_MSB 0
#define DMA4_TI_INTEN_LSB 0
#define DMA4_SOURCE_AD HW_REGISTER_RO( 0x7e00740c )
#define DMA4_SOURCE_AD_MASK 0xffffffff
#define DMA4_SOURCE_AD_WIDTH 32
#define DMA4_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA4_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA4_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA4_SOURCE_AD_S_ADDR_MSB 31
#define DMA4_SOURCE_AD_S_ADDR_LSB 0
#define DMA4_DEST_AD HW_REGISTER_RO( 0x7e007410 )
#define DMA4_DEST_AD_MASK 0xffffffff
#define DMA4_DEST_AD_WIDTH 32
#define DMA4_DEST_AD_D_ADDR_BITS 31:0
#define DMA4_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA4_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA4_DEST_AD_D_ADDR_MSB 31
#define DMA4_DEST_AD_D_ADDR_LSB 0
#define DMA4_TXFR_LEN HW_REGISTER_RO( 0x7e007414 )
#define DMA4_TXFR_LEN_MASK 0x3fffffff
#define DMA4_TXFR_LEN_WIDTH 30
#define DMA4_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA4_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA4_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA4_TXFR_LEN_YLENGTH_MSB 29
#define DMA4_TXFR_LEN_YLENGTH_LSB 16
#define DMA4_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA4_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA4_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA4_TXFR_LEN_XLENGTH_MSB 15
#define DMA4_TXFR_LEN_XLENGTH_LSB 0
#define DMA4_STRIDE HW_REGISTER_RO( 0x7e007418 )
#define DMA4_STRIDE_MASK 0xffffffff
#define DMA4_STRIDE_WIDTH 32
#define DMA4_STRIDE_D_STRIDE_BITS 31:16
#define DMA4_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA4_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA4_STRIDE_D_STRIDE_MSB 31
#define DMA4_STRIDE_D_STRIDE_LSB 16
#define DMA4_STRIDE_S_STRIDE_BITS 15:0
#define DMA4_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA4_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA4_STRIDE_S_STRIDE_MSB 15
#define DMA4_STRIDE_S_STRIDE_LSB 0
#define DMA4_NEXTCONBK HW_REGISTER_RO( 0x7e00741c )
#define DMA4_NEXTCONBK_MASK 0xffffffe0
#define DMA4_NEXTCONBK_WIDTH 32
#define DMA4_NEXTCONBK_ADDR_BITS 31:5
#define DMA4_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA4_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA4_NEXTCONBK_ADDR_MSB 31
#define DMA4_NEXTCONBK_ADDR_LSB 5
#define DMA4_DEBUG HW_REGISTER_RW( 0x7e007420 )
#define DMA4_DEBUG_MASK 0x1ffffff7
#define DMA4_DEBUG_WIDTH 29
#define DMA4_DEBUG_RESET 0000000000
#define DMA4_DEBUG_LITE_BITS 28:28
#define DMA4_DEBUG_LITE_SET 0x10000000
#define DMA4_DEBUG_LITE_CLR 0xefffffff
#define DMA4_DEBUG_LITE_MSB 28
#define DMA4_DEBUG_LITE_LSB 28
#define DMA4_DEBUG_VERSION_BITS 27:25
#define DMA4_DEBUG_VERSION_SET 0x0e000000
#define DMA4_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA4_DEBUG_VERSION_MSB 27
#define DMA4_DEBUG_VERSION_LSB 25
#define DMA4_DEBUG_DMA_STATE_BITS 24:16
#define DMA4_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA4_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA4_DEBUG_DMA_STATE_MSB 24
#define DMA4_DEBUG_DMA_STATE_LSB 16
#define DMA4_DEBUG_DMA_ID_BITS 15:8
#define DMA4_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA4_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA4_DEBUG_DMA_ID_MSB 15
#define DMA4_DEBUG_DMA_ID_LSB 8
#define DMA4_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA4_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA4_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA4_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA4_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA4_DEBUG_READ_ERROR_BITS 2:2
#define DMA4_DEBUG_READ_ERROR_SET 0x00000004
#define DMA4_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA4_DEBUG_READ_ERROR_MSB 2
#define DMA4_DEBUG_READ_ERROR_LSB 2
#define DMA4_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA4_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA4_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA4_DEBUG_FIFO_ERROR_MSB 1
#define DMA4_DEBUG_FIFO_ERROR_LSB 1
#define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA4_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

257
bcm2708_chip/axi_dma5.h Executable file
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// This file was generated by the create_regs script
#define DMA5_BASE 0x7e007500
#define DMA5_CS HW_REGISTER_RW( 0x7e007500 )
#define DMA5_CS_MASK 0xf0ff017f
#define DMA5_CS_WIDTH 32
#define DMA5_CS_RESET 0000000000
#define DMA5_CS_RESET_BITS 31:31
#define DMA5_CS_RESET_SET 0x80000000
#define DMA5_CS_RESET_CLR 0x7fffffff
#define DMA5_CS_RESET_MSB 31
#define DMA5_CS_RESET_LSB 31
#define DMA5_CS_ABORT_BITS 30:30
#define DMA5_CS_ABORT_SET 0x40000000
#define DMA5_CS_ABORT_CLR 0xbfffffff
#define DMA5_CS_ABORT_MSB 30
#define DMA5_CS_ABORT_LSB 30
#define DMA5_CS_DISDEBUG_BITS 29:29
#define DMA5_CS_DISDEBUG_SET 0x20000000
#define DMA5_CS_DISDEBUG_CLR 0xdfffffff
#define DMA5_CS_DISDEBUG_MSB 29
#define DMA5_CS_DISDEBUG_LSB 29
#define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA5_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA5_CS_PANIC_PRIORITY_BITS 23:20
#define DMA5_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA5_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA5_CS_PANIC_PRIORITY_MSB 23
#define DMA5_CS_PANIC_PRIORITY_LSB 20
#define DMA5_CS_PRIORITY_BITS 19:16
#define DMA5_CS_PRIORITY_SET 0x000f0000
#define DMA5_CS_PRIORITY_CLR 0xfff0ffff
#define DMA5_CS_PRIORITY_MSB 19
#define DMA5_CS_PRIORITY_LSB 16
#define DMA5_CS_ERROR_BITS 8:8
#define DMA5_CS_ERROR_SET 0x00000100
#define DMA5_CS_ERROR_CLR 0xfffffeff
#define DMA5_CS_ERROR_MSB 8
#define DMA5_CS_ERROR_LSB 8
#define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA5_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA5_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA5_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA5_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA5_CS_DREQ_STOPS_DMA_MSB 5
#define DMA5_CS_DREQ_STOPS_DMA_LSB 5
#define DMA5_CS_PAUSED_BITS 4:4
#define DMA5_CS_PAUSED_SET 0x00000010
#define DMA5_CS_PAUSED_CLR 0xffffffef
#define DMA5_CS_PAUSED_MSB 4
#define DMA5_CS_PAUSED_LSB 4
#define DMA5_CS_DREQ_BITS 3:3
#define DMA5_CS_DREQ_SET 0x00000008
#define DMA5_CS_DREQ_CLR 0xfffffff7
#define DMA5_CS_DREQ_MSB 3
#define DMA5_CS_DREQ_LSB 3
#define DMA5_CS_INT_BITS 2:2
#define DMA5_CS_INT_SET 0x00000004
#define DMA5_CS_INT_CLR 0xfffffffb
#define DMA5_CS_INT_MSB 2
#define DMA5_CS_INT_LSB 2
#define DMA5_CS_END_BITS 1:1
#define DMA5_CS_END_SET 0x00000002
#define DMA5_CS_END_CLR 0xfffffffd
#define DMA5_CS_END_MSB 1
#define DMA5_CS_END_LSB 1
#define DMA5_CS_ACTIVE_BITS 0:0
#define DMA5_CS_ACTIVE_SET 0x00000001
#define DMA5_CS_ACTIVE_CLR 0xfffffffe
#define DMA5_CS_ACTIVE_MSB 0
#define DMA5_CS_ACTIVE_LSB 0
#define DMA5_CONBLK_AD HW_REGISTER_RW( 0x7e007504 )
#define DMA5_CONBLK_AD_MASK 0xffffffe0
#define DMA5_CONBLK_AD_WIDTH 32
#define DMA5_CONBLK_AD_RESET 0000000000
#define DMA5_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA5_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA5_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA5_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA5_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA5_TI HW_REGISTER_RO( 0x7e007508 )
#define DMA5_TI_MASK 0x07fffffb
#define DMA5_TI_WIDTH 27
#define DMA5_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA5_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA5_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA5_TI_NO_WIDE_BURSTS_MSB 26
#define DMA5_TI_NO_WIDE_BURSTS_LSB 26
#define DMA5_TI_WAITS_BITS 25:21
#define DMA5_TI_WAITS_SET 0x03e00000
#define DMA5_TI_WAITS_CLR 0xfc1fffff
#define DMA5_TI_WAITS_MSB 25
#define DMA5_TI_WAITS_LSB 21
#define DMA5_TI_PERMAP_BITS 20:16
#define DMA5_TI_PERMAP_SET 0x001f0000
#define DMA5_TI_PERMAP_CLR 0xffe0ffff
#define DMA5_TI_PERMAP_MSB 20
#define DMA5_TI_PERMAP_LSB 16
#define DMA5_TI_BURST_LENGTH_BITS 15:12
#define DMA5_TI_BURST_LENGTH_SET 0x0000f000
#define DMA5_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA5_TI_BURST_LENGTH_MSB 15
#define DMA5_TI_BURST_LENGTH_LSB 12
#define DMA5_TI_SRC_IGNORE_BITS 11:11
#define DMA5_TI_SRC_IGNORE_SET 0x00000800
#define DMA5_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA5_TI_SRC_IGNORE_MSB 11
#define DMA5_TI_SRC_IGNORE_LSB 11
#define DMA5_TI_SRC_DREQ_BITS 10:10
#define DMA5_TI_SRC_DREQ_SET 0x00000400
#define DMA5_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA5_TI_SRC_DREQ_MSB 10
#define DMA5_TI_SRC_DREQ_LSB 10
#define DMA5_TI_SRC_WIDTH_BITS 9:9
#define DMA5_TI_SRC_WIDTH_SET 0x00000200
#define DMA5_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA5_TI_SRC_WIDTH_MSB 9
#define DMA5_TI_SRC_WIDTH_LSB 9
#define DMA5_TI_SRC_INC_BITS 8:8
#define DMA5_TI_SRC_INC_SET 0x00000100
#define DMA5_TI_SRC_INC_CLR 0xfffffeff
#define DMA5_TI_SRC_INC_MSB 8
#define DMA5_TI_SRC_INC_LSB 8
#define DMA5_TI_DEST_IGNORE_BITS 7:7
#define DMA5_TI_DEST_IGNORE_SET 0x00000080
#define DMA5_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA5_TI_DEST_IGNORE_MSB 7
#define DMA5_TI_DEST_IGNORE_LSB 7
#define DMA5_TI_DEST_DREQ_BITS 6:6
#define DMA5_TI_DEST_DREQ_SET 0x00000040
#define DMA5_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA5_TI_DEST_DREQ_MSB 6
#define DMA5_TI_DEST_DREQ_LSB 6
#define DMA5_TI_DEST_WIDTH_BITS 5:5
#define DMA5_TI_DEST_WIDTH_SET 0x00000020
#define DMA5_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA5_TI_DEST_WIDTH_MSB 5
#define DMA5_TI_DEST_WIDTH_LSB 5
#define DMA5_TI_DEST_INC_BITS 4:4
#define DMA5_TI_DEST_INC_SET 0x00000010
#define DMA5_TI_DEST_INC_CLR 0xffffffef
#define DMA5_TI_DEST_INC_MSB 4
#define DMA5_TI_DEST_INC_LSB 4
#define DMA5_TI_WAIT_RESP_BITS 3:3
#define DMA5_TI_WAIT_RESP_SET 0x00000008
#define DMA5_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA5_TI_WAIT_RESP_MSB 3
#define DMA5_TI_WAIT_RESP_LSB 3
#define DMA5_TI_TDMODE_BITS 1:1
#define DMA5_TI_TDMODE_SET 0x00000002
#define DMA5_TI_TDMODE_CLR 0xfffffffd
#define DMA5_TI_TDMODE_MSB 1
#define DMA5_TI_TDMODE_LSB 1
#define DMA5_TI_INTEN_BITS 0:0
#define DMA5_TI_INTEN_SET 0x00000001
#define DMA5_TI_INTEN_CLR 0xfffffffe
#define DMA5_TI_INTEN_MSB 0
#define DMA5_TI_INTEN_LSB 0
#define DMA5_SOURCE_AD HW_REGISTER_RO( 0x7e00750c )
#define DMA5_SOURCE_AD_MASK 0xffffffff
#define DMA5_SOURCE_AD_WIDTH 32
#define DMA5_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA5_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA5_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA5_SOURCE_AD_S_ADDR_MSB 31
#define DMA5_SOURCE_AD_S_ADDR_LSB 0
#define DMA5_DEST_AD HW_REGISTER_RO( 0x7e007510 )
#define DMA5_DEST_AD_MASK 0xffffffff
#define DMA5_DEST_AD_WIDTH 32
#define DMA5_DEST_AD_D_ADDR_BITS 31:0
#define DMA5_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA5_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA5_DEST_AD_D_ADDR_MSB 31
#define DMA5_DEST_AD_D_ADDR_LSB 0
#define DMA5_TXFR_LEN HW_REGISTER_RO( 0x7e007514 )
#define DMA5_TXFR_LEN_MASK 0x3fffffff
#define DMA5_TXFR_LEN_WIDTH 30
#define DMA5_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA5_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA5_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA5_TXFR_LEN_YLENGTH_MSB 29
#define DMA5_TXFR_LEN_YLENGTH_LSB 16
#define DMA5_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA5_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA5_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA5_TXFR_LEN_XLENGTH_MSB 15
#define DMA5_TXFR_LEN_XLENGTH_LSB 0
#define DMA5_STRIDE HW_REGISTER_RO( 0x7e007518 )
#define DMA5_STRIDE_MASK 0xffffffff
#define DMA5_STRIDE_WIDTH 32
#define DMA5_STRIDE_D_STRIDE_BITS 31:16
#define DMA5_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA5_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA5_STRIDE_D_STRIDE_MSB 31
#define DMA5_STRIDE_D_STRIDE_LSB 16
#define DMA5_STRIDE_S_STRIDE_BITS 15:0
#define DMA5_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA5_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA5_STRIDE_S_STRIDE_MSB 15
#define DMA5_STRIDE_S_STRIDE_LSB 0
#define DMA5_NEXTCONBK HW_REGISTER_RO( 0x7e00751c )
#define DMA5_NEXTCONBK_MASK 0xffffffe0
#define DMA5_NEXTCONBK_WIDTH 32
#define DMA5_NEXTCONBK_ADDR_BITS 31:5
#define DMA5_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA5_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA5_NEXTCONBK_ADDR_MSB 31
#define DMA5_NEXTCONBK_ADDR_LSB 5
#define DMA5_DEBUG HW_REGISTER_RW( 0x7e007520 )
#define DMA5_DEBUG_MASK 0x1ffffff7
#define DMA5_DEBUG_WIDTH 29
#define DMA5_DEBUG_RESET 0000000000
#define DMA5_DEBUG_LITE_BITS 28:28
#define DMA5_DEBUG_LITE_SET 0x10000000
#define DMA5_DEBUG_LITE_CLR 0xefffffff
#define DMA5_DEBUG_LITE_MSB 28
#define DMA5_DEBUG_LITE_LSB 28
#define DMA5_DEBUG_VERSION_BITS 27:25
#define DMA5_DEBUG_VERSION_SET 0x0e000000
#define DMA5_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA5_DEBUG_VERSION_MSB 27
#define DMA5_DEBUG_VERSION_LSB 25
#define DMA5_DEBUG_DMA_STATE_BITS 24:16
#define DMA5_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA5_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA5_DEBUG_DMA_STATE_MSB 24
#define DMA5_DEBUG_DMA_STATE_LSB 16
#define DMA5_DEBUG_DMA_ID_BITS 15:8
#define DMA5_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA5_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA5_DEBUG_DMA_ID_MSB 15
#define DMA5_DEBUG_DMA_ID_LSB 8
#define DMA5_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA5_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA5_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA5_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA5_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA5_DEBUG_READ_ERROR_BITS 2:2
#define DMA5_DEBUG_READ_ERROR_SET 0x00000004
#define DMA5_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA5_DEBUG_READ_ERROR_MSB 2
#define DMA5_DEBUG_READ_ERROR_LSB 2
#define DMA5_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA5_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA5_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA5_DEBUG_FIFO_ERROR_MSB 1
#define DMA5_DEBUG_FIFO_ERROR_LSB 1
#define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA5_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

257
bcm2708_chip/axi_dma6.h Executable file
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// This file was generated by the create_regs script
#define DMA6_BASE 0x7e007600
#define DMA6_CS HW_REGISTER_RW( 0x7e007600 )
#define DMA6_CS_MASK 0xf0ff017f
#define DMA6_CS_WIDTH 32
#define DMA6_CS_RESET 0000000000
#define DMA6_CS_RESET_BITS 31:31
#define DMA6_CS_RESET_SET 0x80000000
#define DMA6_CS_RESET_CLR 0x7fffffff
#define DMA6_CS_RESET_MSB 31
#define DMA6_CS_RESET_LSB 31
#define DMA6_CS_ABORT_BITS 30:30
#define DMA6_CS_ABORT_SET 0x40000000
#define DMA6_CS_ABORT_CLR 0xbfffffff
#define DMA6_CS_ABORT_MSB 30
#define DMA6_CS_ABORT_LSB 30
#define DMA6_CS_DISDEBUG_BITS 29:29
#define DMA6_CS_DISDEBUG_SET 0x20000000
#define DMA6_CS_DISDEBUG_CLR 0xdfffffff
#define DMA6_CS_DISDEBUG_MSB 29
#define DMA6_CS_DISDEBUG_LSB 29
#define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA6_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA6_CS_PANIC_PRIORITY_BITS 23:20
#define DMA6_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA6_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA6_CS_PANIC_PRIORITY_MSB 23
#define DMA6_CS_PANIC_PRIORITY_LSB 20
#define DMA6_CS_PRIORITY_BITS 19:16
#define DMA6_CS_PRIORITY_SET 0x000f0000
#define DMA6_CS_PRIORITY_CLR 0xfff0ffff
#define DMA6_CS_PRIORITY_MSB 19
#define DMA6_CS_PRIORITY_LSB 16
#define DMA6_CS_ERROR_BITS 8:8
#define DMA6_CS_ERROR_SET 0x00000100
#define DMA6_CS_ERROR_CLR 0xfffffeff
#define DMA6_CS_ERROR_MSB 8
#define DMA6_CS_ERROR_LSB 8
#define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA6_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA6_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA6_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA6_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA6_CS_DREQ_STOPS_DMA_MSB 5
#define DMA6_CS_DREQ_STOPS_DMA_LSB 5
#define DMA6_CS_PAUSED_BITS 4:4
#define DMA6_CS_PAUSED_SET 0x00000010
#define DMA6_CS_PAUSED_CLR 0xffffffef
#define DMA6_CS_PAUSED_MSB 4
#define DMA6_CS_PAUSED_LSB 4
#define DMA6_CS_DREQ_BITS 3:3
#define DMA6_CS_DREQ_SET 0x00000008
#define DMA6_CS_DREQ_CLR 0xfffffff7
#define DMA6_CS_DREQ_MSB 3
#define DMA6_CS_DREQ_LSB 3
#define DMA6_CS_INT_BITS 2:2
#define DMA6_CS_INT_SET 0x00000004
#define DMA6_CS_INT_CLR 0xfffffffb
#define DMA6_CS_INT_MSB 2
#define DMA6_CS_INT_LSB 2
#define DMA6_CS_END_BITS 1:1
#define DMA6_CS_END_SET 0x00000002
#define DMA6_CS_END_CLR 0xfffffffd
#define DMA6_CS_END_MSB 1
#define DMA6_CS_END_LSB 1
#define DMA6_CS_ACTIVE_BITS 0:0
#define DMA6_CS_ACTIVE_SET 0x00000001
#define DMA6_CS_ACTIVE_CLR 0xfffffffe
#define DMA6_CS_ACTIVE_MSB 0
#define DMA6_CS_ACTIVE_LSB 0
#define DMA6_CONBLK_AD HW_REGISTER_RW( 0x7e007604 )
#define DMA6_CONBLK_AD_MASK 0xffffffe0
#define DMA6_CONBLK_AD_WIDTH 32
#define DMA6_CONBLK_AD_RESET 0000000000
#define DMA6_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA6_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA6_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA6_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA6_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA6_TI HW_REGISTER_RO( 0x7e007608 )
#define DMA6_TI_MASK 0x07fffffb
#define DMA6_TI_WIDTH 27
#define DMA6_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA6_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA6_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA6_TI_NO_WIDE_BURSTS_MSB 26
#define DMA6_TI_NO_WIDE_BURSTS_LSB 26
#define DMA6_TI_WAITS_BITS 25:21
#define DMA6_TI_WAITS_SET 0x03e00000
#define DMA6_TI_WAITS_CLR 0xfc1fffff
#define DMA6_TI_WAITS_MSB 25
#define DMA6_TI_WAITS_LSB 21
#define DMA6_TI_PERMAP_BITS 20:16
#define DMA6_TI_PERMAP_SET 0x001f0000
#define DMA6_TI_PERMAP_CLR 0xffe0ffff
#define DMA6_TI_PERMAP_MSB 20
#define DMA6_TI_PERMAP_LSB 16
#define DMA6_TI_BURST_LENGTH_BITS 15:12
#define DMA6_TI_BURST_LENGTH_SET 0x0000f000
#define DMA6_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA6_TI_BURST_LENGTH_MSB 15
#define DMA6_TI_BURST_LENGTH_LSB 12
#define DMA6_TI_SRC_IGNORE_BITS 11:11
#define DMA6_TI_SRC_IGNORE_SET 0x00000800
#define DMA6_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA6_TI_SRC_IGNORE_MSB 11
#define DMA6_TI_SRC_IGNORE_LSB 11
#define DMA6_TI_SRC_DREQ_BITS 10:10
#define DMA6_TI_SRC_DREQ_SET 0x00000400
#define DMA6_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA6_TI_SRC_DREQ_MSB 10
#define DMA6_TI_SRC_DREQ_LSB 10
#define DMA6_TI_SRC_WIDTH_BITS 9:9
#define DMA6_TI_SRC_WIDTH_SET 0x00000200
#define DMA6_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA6_TI_SRC_WIDTH_MSB 9
#define DMA6_TI_SRC_WIDTH_LSB 9
#define DMA6_TI_SRC_INC_BITS 8:8
#define DMA6_TI_SRC_INC_SET 0x00000100
#define DMA6_TI_SRC_INC_CLR 0xfffffeff
#define DMA6_TI_SRC_INC_MSB 8
#define DMA6_TI_SRC_INC_LSB 8
#define DMA6_TI_DEST_IGNORE_BITS 7:7
#define DMA6_TI_DEST_IGNORE_SET 0x00000080
#define DMA6_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA6_TI_DEST_IGNORE_MSB 7
#define DMA6_TI_DEST_IGNORE_LSB 7
#define DMA6_TI_DEST_DREQ_BITS 6:6
#define DMA6_TI_DEST_DREQ_SET 0x00000040
#define DMA6_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA6_TI_DEST_DREQ_MSB 6
#define DMA6_TI_DEST_DREQ_LSB 6
#define DMA6_TI_DEST_WIDTH_BITS 5:5
#define DMA6_TI_DEST_WIDTH_SET 0x00000020
#define DMA6_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA6_TI_DEST_WIDTH_MSB 5
#define DMA6_TI_DEST_WIDTH_LSB 5
#define DMA6_TI_DEST_INC_BITS 4:4
#define DMA6_TI_DEST_INC_SET 0x00000010
#define DMA6_TI_DEST_INC_CLR 0xffffffef
#define DMA6_TI_DEST_INC_MSB 4
#define DMA6_TI_DEST_INC_LSB 4
#define DMA6_TI_WAIT_RESP_BITS 3:3
#define DMA6_TI_WAIT_RESP_SET 0x00000008
#define DMA6_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA6_TI_WAIT_RESP_MSB 3
#define DMA6_TI_WAIT_RESP_LSB 3
#define DMA6_TI_TDMODE_BITS 1:1
#define DMA6_TI_TDMODE_SET 0x00000002
#define DMA6_TI_TDMODE_CLR 0xfffffffd
#define DMA6_TI_TDMODE_MSB 1
#define DMA6_TI_TDMODE_LSB 1
#define DMA6_TI_INTEN_BITS 0:0
#define DMA6_TI_INTEN_SET 0x00000001
#define DMA6_TI_INTEN_CLR 0xfffffffe
#define DMA6_TI_INTEN_MSB 0
#define DMA6_TI_INTEN_LSB 0
#define DMA6_SOURCE_AD HW_REGISTER_RO( 0x7e00760c )
#define DMA6_SOURCE_AD_MASK 0xffffffff
#define DMA6_SOURCE_AD_WIDTH 32
#define DMA6_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA6_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA6_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA6_SOURCE_AD_S_ADDR_MSB 31
#define DMA6_SOURCE_AD_S_ADDR_LSB 0
#define DMA6_DEST_AD HW_REGISTER_RO( 0x7e007610 )
#define DMA6_DEST_AD_MASK 0xffffffff
#define DMA6_DEST_AD_WIDTH 32
#define DMA6_DEST_AD_D_ADDR_BITS 31:0
#define DMA6_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA6_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA6_DEST_AD_D_ADDR_MSB 31
#define DMA6_DEST_AD_D_ADDR_LSB 0
#define DMA6_TXFR_LEN HW_REGISTER_RO( 0x7e007614 )
#define DMA6_TXFR_LEN_MASK 0x3fffffff
#define DMA6_TXFR_LEN_WIDTH 30
#define DMA6_TXFR_LEN_YLENGTH_BITS 29:16
#define DMA6_TXFR_LEN_YLENGTH_SET 0x3fff0000
#define DMA6_TXFR_LEN_YLENGTH_CLR 0xc000ffff
#define DMA6_TXFR_LEN_YLENGTH_MSB 29
#define DMA6_TXFR_LEN_YLENGTH_LSB 16
#define DMA6_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA6_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA6_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA6_TXFR_LEN_XLENGTH_MSB 15
#define DMA6_TXFR_LEN_XLENGTH_LSB 0
#define DMA6_STRIDE HW_REGISTER_RO( 0x7e007618 )
#define DMA6_STRIDE_MASK 0xffffffff
#define DMA6_STRIDE_WIDTH 32
#define DMA6_STRIDE_D_STRIDE_BITS 31:16
#define DMA6_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA6_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA6_STRIDE_D_STRIDE_MSB 31
#define DMA6_STRIDE_D_STRIDE_LSB 16
#define DMA6_STRIDE_S_STRIDE_BITS 15:0
#define DMA6_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA6_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA6_STRIDE_S_STRIDE_MSB 15
#define DMA6_STRIDE_S_STRIDE_LSB 0
#define DMA6_NEXTCONBK HW_REGISTER_RO( 0x7e00761c )
#define DMA6_NEXTCONBK_MASK 0xffffffe0
#define DMA6_NEXTCONBK_WIDTH 32
#define DMA6_NEXTCONBK_ADDR_BITS 31:5
#define DMA6_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA6_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA6_NEXTCONBK_ADDR_MSB 31
#define DMA6_NEXTCONBK_ADDR_LSB 5
#define DMA6_DEBUG HW_REGISTER_RW( 0x7e007620 )
#define DMA6_DEBUG_MASK 0x1ffffff7
#define DMA6_DEBUG_WIDTH 29
#define DMA6_DEBUG_RESET 0000000000
#define DMA6_DEBUG_LITE_BITS 28:28
#define DMA6_DEBUG_LITE_SET 0x10000000
#define DMA6_DEBUG_LITE_CLR 0xefffffff
#define DMA6_DEBUG_LITE_MSB 28
#define DMA6_DEBUG_LITE_LSB 28
#define DMA6_DEBUG_VERSION_BITS 27:25
#define DMA6_DEBUG_VERSION_SET 0x0e000000
#define DMA6_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA6_DEBUG_VERSION_MSB 27
#define DMA6_DEBUG_VERSION_LSB 25
#define DMA6_DEBUG_DMA_STATE_BITS 24:16
#define DMA6_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA6_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA6_DEBUG_DMA_STATE_MSB 24
#define DMA6_DEBUG_DMA_STATE_LSB 16
#define DMA6_DEBUG_DMA_ID_BITS 15:8
#define DMA6_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA6_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA6_DEBUG_DMA_ID_MSB 15
#define DMA6_DEBUG_DMA_ID_LSB 8
#define DMA6_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA6_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA6_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA6_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA6_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA6_DEBUG_READ_ERROR_BITS 2:2
#define DMA6_DEBUG_READ_ERROR_SET 0x00000004
#define DMA6_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA6_DEBUG_READ_ERROR_MSB 2
#define DMA6_DEBUG_READ_ERROR_LSB 2
#define DMA6_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA6_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA6_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA6_DEBUG_FIFO_ERROR_MSB 1
#define DMA6_DEBUG_FIFO_ERROR_LSB 1
#define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA6_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma7.h Executable file
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// This file was generated by the create_regs script
#define DMA7_BASE 0x7e007700
#define DMA7_CS HW_REGISTER_RW( 0x7e007700 )
#define DMA7_CS_MASK 0xf0ff017f
#define DMA7_CS_WIDTH 32
#define DMA7_CS_RESET 0000000000
#define DMA7_CS_RESET_BITS 31:31
#define DMA7_CS_RESET_SET 0x80000000
#define DMA7_CS_RESET_CLR 0x7fffffff
#define DMA7_CS_RESET_MSB 31
#define DMA7_CS_RESET_LSB 31
#define DMA7_CS_ABORT_BITS 30:30
#define DMA7_CS_ABORT_SET 0x40000000
#define DMA7_CS_ABORT_CLR 0xbfffffff
#define DMA7_CS_ABORT_MSB 30
#define DMA7_CS_ABORT_LSB 30
#define DMA7_CS_DISDEBUG_BITS 29:29
#define DMA7_CS_DISDEBUG_SET 0x20000000
#define DMA7_CS_DISDEBUG_CLR 0xdfffffff
#define DMA7_CS_DISDEBUG_MSB 29
#define DMA7_CS_DISDEBUG_LSB 29
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA7_CS_PANIC_PRIORITY_BITS 23:20
#define DMA7_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA7_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA7_CS_PANIC_PRIORITY_MSB 23
#define DMA7_CS_PANIC_PRIORITY_LSB 20
#define DMA7_CS_PRIORITY_BITS 19:16
#define DMA7_CS_PRIORITY_SET 0x000f0000
#define DMA7_CS_PRIORITY_CLR 0xfff0ffff
#define DMA7_CS_PRIORITY_MSB 19
#define DMA7_CS_PRIORITY_LSB 16
#define DMA7_CS_ERROR_BITS 8:8
#define DMA7_CS_ERROR_SET 0x00000100
#define DMA7_CS_ERROR_CLR 0xfffffeff
#define DMA7_CS_ERROR_MSB 8
#define DMA7_CS_ERROR_LSB 8
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA7_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA7_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA7_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA7_CS_DREQ_STOPS_DMA_MSB 5
#define DMA7_CS_DREQ_STOPS_DMA_LSB 5
#define DMA7_CS_PAUSED_BITS 4:4
#define DMA7_CS_PAUSED_SET 0x00000010
#define DMA7_CS_PAUSED_CLR 0xffffffef
#define DMA7_CS_PAUSED_MSB 4
#define DMA7_CS_PAUSED_LSB 4
#define DMA7_CS_DREQ_BITS 3:3
#define DMA7_CS_DREQ_SET 0x00000008
#define DMA7_CS_DREQ_CLR 0xfffffff7
#define DMA7_CS_DREQ_MSB 3
#define DMA7_CS_DREQ_LSB 3
#define DMA7_CS_INT_BITS 2:2
#define DMA7_CS_INT_SET 0x00000004
#define DMA7_CS_INT_CLR 0xfffffffb
#define DMA7_CS_INT_MSB 2
#define DMA7_CS_INT_LSB 2
#define DMA7_CS_END_BITS 1:1
#define DMA7_CS_END_SET 0x00000002
#define DMA7_CS_END_CLR 0xfffffffd
#define DMA7_CS_END_MSB 1
#define DMA7_CS_END_LSB 1
#define DMA7_CS_ACTIVE_BITS 0:0
#define DMA7_CS_ACTIVE_SET 0x00000001
#define DMA7_CS_ACTIVE_CLR 0xfffffffe
#define DMA7_CS_ACTIVE_MSB 0
#define DMA7_CS_ACTIVE_LSB 0
#define DMA7_CONBLK_AD HW_REGISTER_RW( 0x7e007704 )
#define DMA7_CONBLK_AD_MASK 0xffffffe0
#define DMA7_CONBLK_AD_WIDTH 32
#define DMA7_CONBLK_AD_RESET 0000000000
#define DMA7_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA7_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA7_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA7_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA7_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA7_TI HW_REGISTER_RO( 0x7e007708 )
#define DMA7_TI_MASK 0x07fffffb
#define DMA7_TI_WIDTH 27
#define DMA7_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA7_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA7_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA7_TI_NO_WIDE_BURSTS_MSB 26
#define DMA7_TI_NO_WIDE_BURSTS_LSB 26
#define DMA7_TI_WAITS_BITS 25:21
#define DMA7_TI_WAITS_SET 0x03e00000
#define DMA7_TI_WAITS_CLR 0xfc1fffff
#define DMA7_TI_WAITS_MSB 25
#define DMA7_TI_WAITS_LSB 21
#define DMA7_TI_PERMAP_BITS 20:16
#define DMA7_TI_PERMAP_SET 0x001f0000
#define DMA7_TI_PERMAP_CLR 0xffe0ffff
#define DMA7_TI_PERMAP_MSB 20
#define DMA7_TI_PERMAP_LSB 16
#define DMA7_TI_BURST_LENGTH_BITS 15:12
#define DMA7_TI_BURST_LENGTH_SET 0x0000f000
#define DMA7_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA7_TI_BURST_LENGTH_MSB 15
#define DMA7_TI_BURST_LENGTH_LSB 12
#define DMA7_TI_SRC_IGNORE_BITS 11:11
#define DMA7_TI_SRC_IGNORE_SET 0x00000800
#define DMA7_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA7_TI_SRC_IGNORE_MSB 11
#define DMA7_TI_SRC_IGNORE_LSB 11
#define DMA7_TI_SRC_DREQ_BITS 10:10
#define DMA7_TI_SRC_DREQ_SET 0x00000400
#define DMA7_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA7_TI_SRC_DREQ_MSB 10
#define DMA7_TI_SRC_DREQ_LSB 10
#define DMA7_TI_SRC_WIDTH_BITS 9:9
#define DMA7_TI_SRC_WIDTH_SET 0x00000200
#define DMA7_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA7_TI_SRC_WIDTH_MSB 9
#define DMA7_TI_SRC_WIDTH_LSB 9
#define DMA7_TI_SRC_INC_BITS 8:8
#define DMA7_TI_SRC_INC_SET 0x00000100
#define DMA7_TI_SRC_INC_CLR 0xfffffeff
#define DMA7_TI_SRC_INC_MSB 8
#define DMA7_TI_SRC_INC_LSB 8
#define DMA7_TI_DEST_IGNORE_BITS 7:7
#define DMA7_TI_DEST_IGNORE_SET 0x00000080
#define DMA7_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA7_TI_DEST_IGNORE_MSB 7
#define DMA7_TI_DEST_IGNORE_LSB 7
#define DMA7_TI_DEST_DREQ_BITS 6:6
#define DMA7_TI_DEST_DREQ_SET 0x00000040
#define DMA7_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA7_TI_DEST_DREQ_MSB 6
#define DMA7_TI_DEST_DREQ_LSB 6
#define DMA7_TI_DEST_WIDTH_BITS 5:5
#define DMA7_TI_DEST_WIDTH_SET 0x00000020
#define DMA7_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA7_TI_DEST_WIDTH_MSB 5
#define DMA7_TI_DEST_WIDTH_LSB 5
#define DMA7_TI_DEST_INC_BITS 4:4
#define DMA7_TI_DEST_INC_SET 0x00000010
#define DMA7_TI_DEST_INC_CLR 0xffffffef
#define DMA7_TI_DEST_INC_MSB 4
#define DMA7_TI_DEST_INC_LSB 4
#define DMA7_TI_WAIT_RESP_BITS 3:3
#define DMA7_TI_WAIT_RESP_SET 0x00000008
#define DMA7_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA7_TI_WAIT_RESP_MSB 3
#define DMA7_TI_WAIT_RESP_LSB 3
#define DMA7_TI_TDMODE_BITS 1:1
#define DMA7_TI_TDMODE_SET 0x00000002
#define DMA7_TI_TDMODE_CLR 0xfffffffd
#define DMA7_TI_TDMODE_MSB 1
#define DMA7_TI_TDMODE_LSB 1
#define DMA7_TI_INTEN_BITS 0:0
#define DMA7_TI_INTEN_SET 0x00000001
#define DMA7_TI_INTEN_CLR 0xfffffffe
#define DMA7_TI_INTEN_MSB 0
#define DMA7_TI_INTEN_LSB 0
#define DMA7_SOURCE_AD HW_REGISTER_RO( 0x7e00770c )
#define DMA7_SOURCE_AD_MASK 0xffffffff
#define DMA7_SOURCE_AD_WIDTH 32
#define DMA7_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA7_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA7_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA7_SOURCE_AD_S_ADDR_MSB 31
#define DMA7_SOURCE_AD_S_ADDR_LSB 0
#define DMA7_DEST_AD HW_REGISTER_RO( 0x7e007710 )
#define DMA7_DEST_AD_MASK 0xffffffff
#define DMA7_DEST_AD_WIDTH 32
#define DMA7_DEST_AD_D_ADDR_BITS 31:0
#define DMA7_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA7_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA7_DEST_AD_D_ADDR_MSB 31
#define DMA7_DEST_AD_D_ADDR_LSB 0
#define DMA7_TXFR_LEN HW_REGISTER_RO( 0x7e007714 )
#define DMA7_TXFR_LEN_MASK 0x3fffffff
#define DMA7_TXFR_LEN_WIDTH 30
#define DMA7_TXFR_LEN_ylength_BITS 29:16
#define DMA7_TXFR_LEN_ylength_SET 0x3fff0000
#define DMA7_TXFR_LEN_ylength_CLR 0xc000ffff
#define DMA7_TXFR_LEN_ylength_MSB 29
#define DMA7_TXFR_LEN_ylength_LSB 16
#define DMA7_TXFR_LEN_xlength_BITS 15:0
#define DMA7_TXFR_LEN_xlength_SET 0x0000ffff
#define DMA7_TXFR_LEN_xlength_CLR 0xffff0000
#define DMA7_TXFR_LEN_xlength_MSB 15
#define DMA7_TXFR_LEN_xlength_LSB 0
#define DMA7_STRIDE HW_REGISTER_RO( 0x7e007718 )
#define DMA7_STRIDE_MASK 0xffffffff
#define DMA7_STRIDE_WIDTH 32
#define DMA7_STRIDE_D_STRIDE_BITS 31:16
#define DMA7_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA7_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA7_STRIDE_D_STRIDE_MSB 31
#define DMA7_STRIDE_D_STRIDE_LSB 16
#define DMA7_STRIDE_S_STRIDE_BITS 15:0
#define DMA7_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA7_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA7_STRIDE_S_STRIDE_MSB 15
#define DMA7_STRIDE_S_STRIDE_LSB 0
#define DMA7_NEXTCONBK HW_REGISTER_RO( 0x7e00771c )
#define DMA7_NEXTCONBK_MASK 0xffffffe0
#define DMA7_NEXTCONBK_WIDTH 32
#define DMA7_DEBUG HW_REGISTER_RW( 0x7e007720 )
#define DMA7_DEBUG_MASK 0x0ffffff7
#define DMA7_DEBUG_WIDTH 28
#define DMA7_DEBUG_RESET 0000000000
#define DMA7_DEBUG_VERSION_BITS 27:25
#define DMA7_DEBUG_VERSION_SET 0x0e000000
#define DMA7_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA7_DEBUG_VERSION_MSB 27
#define DMA7_DEBUG_VERSION_LSB 25
#define DMA7_DEBUG_DMA_STATE_BITS 24:16
#define DMA7_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA7_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA7_DEBUG_DMA_STATE_MSB 24
#define DMA7_DEBUG_DMA_STATE_LSB 16
#define DMA7_DEBUG_DMA_ID_BITS 15:8
#define DMA7_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA7_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA7_DEBUG_DMA_ID_MSB 15
#define DMA7_DEBUG_DMA_ID_LSB 8
#define DMA7_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA7_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA7_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA7_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA7_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA7_DEBUG_READ_ERROR_BITS 2:2
#define DMA7_DEBUG_READ_ERROR_SET 0x00000004
#define DMA7_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA7_DEBUG_READ_ERROR_MSB 2
#define DMA7_DEBUG_READ_ERROR_LSB 2
#define DMA7_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA7_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA7_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA7_DEBUG_FIFO_ERROR_MSB 1
#define DMA7_DEBUG_FIFO_ERROR_LSB 1
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma8.h Executable file
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// This file was generated by the create_regs script
#define DMA8_BASE 0x7ee05000
#define DMA8_CS HW_REGISTER_RW( 0x7ee05000 )
#define DMA8_CS_MASK 0xf0ff017f
#define DMA8_CS_WIDTH 32
#define DMA8_CS_RESET 0000000000
#define DMA8_CS_RESET_BITS 31:31
#define DMA8_CS_RESET_SET 0x80000000
#define DMA8_CS_RESET_CLR 0x7fffffff
#define DMA8_CS_RESET_MSB 31
#define DMA8_CS_RESET_LSB 31
#define DMA8_CS_ABORT_BITS 30:30
#define DMA8_CS_ABORT_SET 0x40000000
#define DMA8_CS_ABORT_CLR 0xbfffffff
#define DMA8_CS_ABORT_MSB 30
#define DMA8_CS_ABORT_LSB 30
#define DMA8_CS_DISDEBUG_BITS 29:29
#define DMA8_CS_DISDEBUG_SET 0x20000000
#define DMA8_CS_DISDEBUG_CLR 0xdfffffff
#define DMA8_CS_DISDEBUG_MSB 29
#define DMA8_CS_DISDEBUG_LSB 29
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA8_CS_PANIC_PRIORITY_BITS 23:20
#define DMA8_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA8_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA8_CS_PANIC_PRIORITY_MSB 23
#define DMA8_CS_PANIC_PRIORITY_LSB 20
#define DMA8_CS_PRIORITY_BITS 19:16
#define DMA8_CS_PRIORITY_SET 0x000f0000
#define DMA8_CS_PRIORITY_CLR 0xfff0ffff
#define DMA8_CS_PRIORITY_MSB 19
#define DMA8_CS_PRIORITY_LSB 16
#define DMA8_CS_ERROR_BITS 8:8
#define DMA8_CS_ERROR_SET 0x00000100
#define DMA8_CS_ERROR_CLR 0xfffffeff
#define DMA8_CS_ERROR_MSB 8
#define DMA8_CS_ERROR_LSB 8
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA8_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA8_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA8_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA8_CS_DREQ_STOPS_DMA_MSB 5
#define DMA8_CS_DREQ_STOPS_DMA_LSB 5
#define DMA8_CS_PAUSED_BITS 4:4
#define DMA8_CS_PAUSED_SET 0x00000010
#define DMA8_CS_PAUSED_CLR 0xffffffef
#define DMA8_CS_PAUSED_MSB 4
#define DMA8_CS_PAUSED_LSB 4
#define DMA8_CS_DREQ_BITS 3:3
#define DMA8_CS_DREQ_SET 0x00000008
#define DMA8_CS_DREQ_CLR 0xfffffff7
#define DMA8_CS_DREQ_MSB 3
#define DMA8_CS_DREQ_LSB 3
#define DMA8_CS_INT_BITS 2:2
#define DMA8_CS_INT_SET 0x00000004
#define DMA8_CS_INT_CLR 0xfffffffb
#define DMA8_CS_INT_MSB 2
#define DMA8_CS_INT_LSB 2
#define DMA8_CS_END_BITS 1:1
#define DMA8_CS_END_SET 0x00000002
#define DMA8_CS_END_CLR 0xfffffffd
#define DMA8_CS_END_MSB 1
#define DMA8_CS_END_LSB 1
#define DMA8_CS_ACTIVE_BITS 0:0
#define DMA8_CS_ACTIVE_SET 0x00000001
#define DMA8_CS_ACTIVE_CLR 0xfffffffe
#define DMA8_CS_ACTIVE_MSB 0
#define DMA8_CS_ACTIVE_LSB 0
#define DMA8_CONBLK_AD HW_REGISTER_RW( 0x7ee05004 )
#define DMA8_CONBLK_AD_MASK 0xffffffe0
#define DMA8_CONBLK_AD_WIDTH 32
#define DMA8_CONBLK_AD_RESET 0000000000
#define DMA8_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA8_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA8_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA8_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA8_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA8_TI HW_REGISTER_RO( 0x7ee05008 )
#define DMA8_TI_MASK 0x07fffffb
#define DMA8_TI_WIDTH 27
#define DMA8_TI_NO_WIDE_BURSTS_BITS 26:26
#define DMA8_TI_NO_WIDE_BURSTS_SET 0x04000000
#define DMA8_TI_NO_WIDE_BURSTS_CLR 0xfbffffff
#define DMA8_TI_NO_WIDE_BURSTS_MSB 26
#define DMA8_TI_NO_WIDE_BURSTS_LSB 26
#define DMA8_TI_WAITS_BITS 25:21
#define DMA8_TI_WAITS_SET 0x03e00000
#define DMA8_TI_WAITS_CLR 0xfc1fffff
#define DMA8_TI_WAITS_MSB 25
#define DMA8_TI_WAITS_LSB 21
#define DMA8_TI_PERMAP_BITS 20:16
#define DMA8_TI_PERMAP_SET 0x001f0000
#define DMA8_TI_PERMAP_CLR 0xffe0ffff
#define DMA8_TI_PERMAP_MSB 20
#define DMA8_TI_PERMAP_LSB 16
#define DMA8_TI_BURST_LENGTH_BITS 15:12
#define DMA8_TI_BURST_LENGTH_SET 0x0000f000
#define DMA8_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA8_TI_BURST_LENGTH_MSB 15
#define DMA8_TI_BURST_LENGTH_LSB 12
#define DMA8_TI_SRC_IGNORE_BITS 11:11
#define DMA8_TI_SRC_IGNORE_SET 0x00000800
#define DMA8_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA8_TI_SRC_IGNORE_MSB 11
#define DMA8_TI_SRC_IGNORE_LSB 11
#define DMA8_TI_SRC_DREQ_BITS 10:10
#define DMA8_TI_SRC_DREQ_SET 0x00000400
#define DMA8_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA8_TI_SRC_DREQ_MSB 10
#define DMA8_TI_SRC_DREQ_LSB 10
#define DMA8_TI_SRC_WIDTH_BITS 9:9
#define DMA8_TI_SRC_WIDTH_SET 0x00000200
#define DMA8_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA8_TI_SRC_WIDTH_MSB 9
#define DMA8_TI_SRC_WIDTH_LSB 9
#define DMA8_TI_SRC_INC_BITS 8:8
#define DMA8_TI_SRC_INC_SET 0x00000100
#define DMA8_TI_SRC_INC_CLR 0xfffffeff
#define DMA8_TI_SRC_INC_MSB 8
#define DMA8_TI_SRC_INC_LSB 8
#define DMA8_TI_DEST_IGNORE_BITS 7:7
#define DMA8_TI_DEST_IGNORE_SET 0x00000080
#define DMA8_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA8_TI_DEST_IGNORE_MSB 7
#define DMA8_TI_DEST_IGNORE_LSB 7
#define DMA8_TI_DEST_DREQ_BITS 6:6
#define DMA8_TI_DEST_DREQ_SET 0x00000040
#define DMA8_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA8_TI_DEST_DREQ_MSB 6
#define DMA8_TI_DEST_DREQ_LSB 6
#define DMA8_TI_DEST_WIDTH_BITS 5:5
#define DMA8_TI_DEST_WIDTH_SET 0x00000020
#define DMA8_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA8_TI_DEST_WIDTH_MSB 5
#define DMA8_TI_DEST_WIDTH_LSB 5
#define DMA8_TI_DEST_INC_BITS 4:4
#define DMA8_TI_DEST_INC_SET 0x00000010
#define DMA8_TI_DEST_INC_CLR 0xffffffef
#define DMA8_TI_DEST_INC_MSB 4
#define DMA8_TI_DEST_INC_LSB 4
#define DMA8_TI_WAIT_RESP_BITS 3:3
#define DMA8_TI_WAIT_RESP_SET 0x00000008
#define DMA8_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA8_TI_WAIT_RESP_MSB 3
#define DMA8_TI_WAIT_RESP_LSB 3
#define DMA8_TI_TDMODE_BITS 1:1
#define DMA8_TI_TDMODE_SET 0x00000002
#define DMA8_TI_TDMODE_CLR 0xfffffffd
#define DMA8_TI_TDMODE_MSB 1
#define DMA8_TI_TDMODE_LSB 1
#define DMA8_TI_INTEN_BITS 0:0
#define DMA8_TI_INTEN_SET 0x00000001
#define DMA8_TI_INTEN_CLR 0xfffffffe
#define DMA8_TI_INTEN_MSB 0
#define DMA8_TI_INTEN_LSB 0
#define DMA8_SOURCE_AD HW_REGISTER_RO( 0x7ee0500c )
#define DMA8_SOURCE_AD_MASK 0xffffffff
#define DMA8_SOURCE_AD_WIDTH 32
#define DMA8_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA8_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA8_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA8_SOURCE_AD_S_ADDR_MSB 31
#define DMA8_SOURCE_AD_S_ADDR_LSB 0
#define DMA8_DEST_AD HW_REGISTER_RO( 0x7ee05010 )
#define DMA8_DEST_AD_MASK 0xffffffff
#define DMA8_DEST_AD_WIDTH 32
#define DMA8_DEST_AD_D_ADDR_BITS 31:0
#define DMA8_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA8_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA8_DEST_AD_D_ADDR_MSB 31
#define DMA8_DEST_AD_D_ADDR_LSB 0
#define DMA8_TXFR_LEN HW_REGISTER_RO( 0x7ee05014 )
#define DMA8_TXFR_LEN_MASK 0x3fffffff
#define DMA8_TXFR_LEN_WIDTH 30
#define DMA8_TXFR_LEN_ylength_BITS 29:16
#define DMA8_TXFR_LEN_ylength_SET 0x3fff0000
#define DMA8_TXFR_LEN_ylength_CLR 0xc000ffff
#define DMA8_TXFR_LEN_ylength_MSB 29
#define DMA8_TXFR_LEN_ylength_LSB 16
#define DMA8_TXFR_LEN_xlength_BITS 15:0
#define DMA8_TXFR_LEN_xlength_SET 0x0000ffff
#define DMA8_TXFR_LEN_xlength_CLR 0xffff0000
#define DMA8_TXFR_LEN_xlength_MSB 15
#define DMA8_TXFR_LEN_xlength_LSB 0
#define DMA8_STRIDE HW_REGISTER_RO( 0x7ee05018 )
#define DMA8_STRIDE_MASK 0xffffffff
#define DMA8_STRIDE_WIDTH 32
#define DMA8_STRIDE_D_STRIDE_BITS 31:16
#define DMA8_STRIDE_D_STRIDE_SET 0xffff0000
#define DMA8_STRIDE_D_STRIDE_CLR 0x0000ffff
#define DMA8_STRIDE_D_STRIDE_MSB 31
#define DMA8_STRIDE_D_STRIDE_LSB 16
#define DMA8_STRIDE_S_STRIDE_BITS 15:0
#define DMA8_STRIDE_S_STRIDE_SET 0x0000ffff
#define DMA8_STRIDE_S_STRIDE_CLR 0xffff0000
#define DMA8_STRIDE_S_STRIDE_MSB 15
#define DMA8_STRIDE_S_STRIDE_LSB 0
#define DMA8_NEXTCONBK HW_REGISTER_RO( 0x7ee0501c )
#define DMA8_NEXTCONBK_MASK 0xffffffe0
#define DMA8_NEXTCONBK_WIDTH 32
#define DMA8_DEBUG HW_REGISTER_RW( 0x7ee05020 )
#define DMA8_DEBUG_MASK 0x0ffffff7
#define DMA8_DEBUG_WIDTH 28
#define DMA8_DEBUG_RESET 0000000000
#define DMA8_DEBUG_VERSION_BITS 27:25
#define DMA8_DEBUG_VERSION_SET 0x0e000000
#define DMA8_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA8_DEBUG_VERSION_MSB 27
#define DMA8_DEBUG_VERSION_LSB 25
#define DMA8_DEBUG_DMA_STATE_BITS 24:16
#define DMA8_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA8_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA8_DEBUG_DMA_STATE_MSB 24
#define DMA8_DEBUG_DMA_STATE_LSB 16
#define DMA8_DEBUG_DMA_ID_BITS 15:8
#define DMA8_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA8_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA8_DEBUG_DMA_ID_MSB 15
#define DMA8_DEBUG_DMA_ID_LSB 8
#define DMA8_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA8_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA8_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA8_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA8_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA8_DEBUG_READ_ERROR_BITS 2:2
#define DMA8_DEBUG_READ_ERROR_SET 0x00000004
#define DMA8_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA8_DEBUG_READ_ERROR_MSB 2
#define DMA8_DEBUG_READ_ERROR_LSB 2
#define DMA8_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA8_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA8_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA8_DEBUG_FIFO_ERROR_MSB 1
#define DMA8_DEBUG_FIFO_ERROR_LSB 1
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite10.h Executable file
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// This file was generated by the create_regs script
#define DMA10_BASE 0x7e007a00
#define DMA10_CS HW_REGISTER_RW( 0x7e007a00 )
#define DMA10_CS_MASK 0xf0ff017f
#define DMA10_CS_WIDTH 32
#define DMA10_CS_RESET 0000000000
#define DMA10_CS_RESET_BITS 31:31
#define DMA10_CS_RESET_SET 0x80000000
#define DMA10_CS_RESET_CLR 0x7fffffff
#define DMA10_CS_RESET_MSB 31
#define DMA10_CS_RESET_LSB 31
#define DMA10_CS_ABORT_BITS 30:30
#define DMA10_CS_ABORT_SET 0x40000000
#define DMA10_CS_ABORT_CLR 0xbfffffff
#define DMA10_CS_ABORT_MSB 30
#define DMA10_CS_ABORT_LSB 30
#define DMA10_CS_DISDEBUG_BITS 29:29
#define DMA10_CS_DISDEBUG_SET 0x20000000
#define DMA10_CS_DISDEBUG_CLR 0xdfffffff
#define DMA10_CS_DISDEBUG_MSB 29
#define DMA10_CS_DISDEBUG_LSB 29
#define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA10_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA10_CS_PANIC_PRIORITY_BITS 23:20
#define DMA10_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA10_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA10_CS_PANIC_PRIORITY_MSB 23
#define DMA10_CS_PANIC_PRIORITY_LSB 20
#define DMA10_CS_PRIORITY_BITS 19:16
#define DMA10_CS_PRIORITY_SET 0x000f0000
#define DMA10_CS_PRIORITY_CLR 0xfff0ffff
#define DMA10_CS_PRIORITY_MSB 19
#define DMA10_CS_PRIORITY_LSB 16
#define DMA10_CS_ERROR_BITS 8:8
#define DMA10_CS_ERROR_SET 0x00000100
#define DMA10_CS_ERROR_CLR 0xfffffeff
#define DMA10_CS_ERROR_MSB 8
#define DMA10_CS_ERROR_LSB 8
#define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA10_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA10_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA10_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA10_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA10_CS_DREQ_STOPS_DMA_MSB 5
#define DMA10_CS_DREQ_STOPS_DMA_LSB 5
#define DMA10_CS_PAUSED_BITS 4:4
#define DMA10_CS_PAUSED_SET 0x00000010
#define DMA10_CS_PAUSED_CLR 0xffffffef
#define DMA10_CS_PAUSED_MSB 4
#define DMA10_CS_PAUSED_LSB 4
#define DMA10_CS_DREQ_BITS 3:3
#define DMA10_CS_DREQ_SET 0x00000008
#define DMA10_CS_DREQ_CLR 0xfffffff7
#define DMA10_CS_DREQ_MSB 3
#define DMA10_CS_DREQ_LSB 3
#define DMA10_CS_INT_BITS 2:2
#define DMA10_CS_INT_SET 0x00000004
#define DMA10_CS_INT_CLR 0xfffffffb
#define DMA10_CS_INT_MSB 2
#define DMA10_CS_INT_LSB 2
#define DMA10_CS_END_BITS 1:1
#define DMA10_CS_END_SET 0x00000002
#define DMA10_CS_END_CLR 0xfffffffd
#define DMA10_CS_END_MSB 1
#define DMA10_CS_END_LSB 1
#define DMA10_CS_ACTIVE_BITS 0:0
#define DMA10_CS_ACTIVE_SET 0x00000001
#define DMA10_CS_ACTIVE_CLR 0xfffffffe
#define DMA10_CS_ACTIVE_MSB 0
#define DMA10_CS_ACTIVE_LSB 0
#define DMA10_CONBLK_AD HW_REGISTER_RW( 0x7e007a04 )
#define DMA10_CONBLK_AD_MASK 0xffffffe0
#define DMA10_CONBLK_AD_WIDTH 32
#define DMA10_CONBLK_AD_RESET 0000000000
#define DMA10_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA10_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA10_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA10_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA10_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA10_TI HW_REGISTER_RO( 0x7e007a08 )
#define DMA10_TI_MASK 0x03fffff9
#define DMA10_TI_WIDTH 26
#define DMA10_TI_WAITS_BITS 25:21
#define DMA10_TI_WAITS_SET 0x03e00000
#define DMA10_TI_WAITS_CLR 0xfc1fffff
#define DMA10_TI_WAITS_MSB 25
#define DMA10_TI_WAITS_LSB 21
#define DMA10_TI_PERMAP_BITS 20:16
#define DMA10_TI_PERMAP_SET 0x001f0000
#define DMA10_TI_PERMAP_CLR 0xffe0ffff
#define DMA10_TI_PERMAP_MSB 20
#define DMA10_TI_PERMAP_LSB 16
#define DMA10_TI_BURST_LENGTH_BITS 15:12
#define DMA10_TI_BURST_LENGTH_SET 0x0000f000
#define DMA10_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA10_TI_BURST_LENGTH_MSB 15
#define DMA10_TI_BURST_LENGTH_LSB 12
#define DMA10_TI_SRC_IGNORE_BITS 11:11
#define DMA10_TI_SRC_IGNORE_SET 0x00000800
#define DMA10_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA10_TI_SRC_IGNORE_MSB 11
#define DMA10_TI_SRC_IGNORE_LSB 11
#define DMA10_TI_SRC_DREQ_BITS 10:10
#define DMA10_TI_SRC_DREQ_SET 0x00000400
#define DMA10_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA10_TI_SRC_DREQ_MSB 10
#define DMA10_TI_SRC_DREQ_LSB 10
#define DMA10_TI_SRC_WIDTH_BITS 9:9
#define DMA10_TI_SRC_WIDTH_SET 0x00000200
#define DMA10_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA10_TI_SRC_WIDTH_MSB 9
#define DMA10_TI_SRC_WIDTH_LSB 9
#define DMA10_TI_SRC_INC_BITS 8:8
#define DMA10_TI_SRC_INC_SET 0x00000100
#define DMA10_TI_SRC_INC_CLR 0xfffffeff
#define DMA10_TI_SRC_INC_MSB 8
#define DMA10_TI_SRC_INC_LSB 8
#define DMA10_TI_DEST_IGNORE_BITS 7:7
#define DMA10_TI_DEST_IGNORE_SET 0x00000080
#define DMA10_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA10_TI_DEST_IGNORE_MSB 7
#define DMA10_TI_DEST_IGNORE_LSB 7
#define DMA10_TI_DEST_DREQ_BITS 6:6
#define DMA10_TI_DEST_DREQ_SET 0x00000040
#define DMA10_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA10_TI_DEST_DREQ_MSB 6
#define DMA10_TI_DEST_DREQ_LSB 6
#define DMA10_TI_DEST_WIDTH_BITS 5:5
#define DMA10_TI_DEST_WIDTH_SET 0x00000020
#define DMA10_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA10_TI_DEST_WIDTH_MSB 5
#define DMA10_TI_DEST_WIDTH_LSB 5
#define DMA10_TI_DEST_INC_BITS 4:4
#define DMA10_TI_DEST_INC_SET 0x00000010
#define DMA10_TI_DEST_INC_CLR 0xffffffef
#define DMA10_TI_DEST_INC_MSB 4
#define DMA10_TI_DEST_INC_LSB 4
#define DMA10_TI_WAIT_RESP_BITS 3:3
#define DMA10_TI_WAIT_RESP_SET 0x00000008
#define DMA10_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA10_TI_WAIT_RESP_MSB 3
#define DMA10_TI_WAIT_RESP_LSB 3
#define DMA10_TI_INTEN_BITS 0:0
#define DMA10_TI_INTEN_SET 0x00000001
#define DMA10_TI_INTEN_CLR 0xfffffffe
#define DMA10_TI_INTEN_MSB 0
#define DMA10_TI_INTEN_LSB 0
#define DMA10_SOURCE_AD HW_REGISTER_RO( 0x7e007a0c )
#define DMA10_SOURCE_AD_MASK 0xffffffff
#define DMA10_SOURCE_AD_WIDTH 32
#define DMA10_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA10_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA10_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA10_SOURCE_AD_S_ADDR_MSB 31
#define DMA10_SOURCE_AD_S_ADDR_LSB 0
#define DMA10_DEST_AD HW_REGISTER_RO( 0x7e007a10 )
#define DMA10_DEST_AD_MASK 0xffffffff
#define DMA10_DEST_AD_WIDTH 32
#define DMA10_DEST_AD_D_ADDR_BITS 31:0
#define DMA10_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA10_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA10_DEST_AD_D_ADDR_MSB 31
#define DMA10_DEST_AD_D_ADDR_LSB 0
#define DMA10_TXFR_LEN HW_REGISTER_RO( 0x7e007a14 )
#define DMA10_TXFR_LEN_MASK 0x0000ffff
#define DMA10_TXFR_LEN_WIDTH 16
#define DMA10_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA10_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA10_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA10_TXFR_LEN_XLENGTH_MSB 15
#define DMA10_TXFR_LEN_XLENGTH_LSB 0
#define DMA10_NEXTCONBK HW_REGISTER_RO( 0x7e007a1c )
#define DMA10_NEXTCONBK_MASK 0xffffffe0
#define DMA10_NEXTCONBK_WIDTH 32
#define DMA10_NEXTCONBK_ADDR_BITS 31:5
#define DMA10_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA10_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA10_NEXTCONBK_ADDR_MSB 31
#define DMA10_NEXTCONBK_ADDR_LSB 5
#define DMA10_DEBUG HW_REGISTER_RW( 0x7e007a20 )
#define DMA10_DEBUG_MASK 0x1ffffff7
#define DMA10_DEBUG_WIDTH 29
#define DMA10_DEBUG_RESET 0000000000
#define DMA10_DEBUG_LITE_BITS 28:28
#define DMA10_DEBUG_LITE_SET 0x10000000
#define DMA10_DEBUG_LITE_CLR 0xefffffff
#define DMA10_DEBUG_LITE_MSB 28
#define DMA10_DEBUG_LITE_LSB 28
#define DMA10_DEBUG_VERSION_BITS 27:25
#define DMA10_DEBUG_VERSION_SET 0x0e000000
#define DMA10_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA10_DEBUG_VERSION_MSB 27
#define DMA10_DEBUG_VERSION_LSB 25
#define DMA10_DEBUG_DMA_STATE_BITS 24:16
#define DMA10_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA10_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA10_DEBUG_DMA_STATE_MSB 24
#define DMA10_DEBUG_DMA_STATE_LSB 16
#define DMA10_DEBUG_DMA_ID_BITS 15:8
#define DMA10_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA10_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA10_DEBUG_DMA_ID_MSB 15
#define DMA10_DEBUG_DMA_ID_LSB 8
#define DMA10_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA10_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA10_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA10_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA10_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA10_DEBUG_READ_ERROR_BITS 2:2
#define DMA10_DEBUG_READ_ERROR_SET 0x00000004
#define DMA10_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA10_DEBUG_READ_ERROR_MSB 2
#define DMA10_DEBUG_READ_ERROR_LSB 2
#define DMA10_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA10_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA10_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA10_DEBUG_FIFO_ERROR_MSB 1
#define DMA10_DEBUG_FIFO_ERROR_LSB 1
#define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA10_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite11.h Executable file
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// This file was generated by the create_regs script
#define DMA11_BASE 0x7e007b00
#define DMA11_CS HW_REGISTER_RW( 0x7e007b00 )
#define DMA11_CS_MASK 0xf0ff017f
#define DMA11_CS_WIDTH 32
#define DMA11_CS_RESET 0000000000
#define DMA11_CS_RESET_BITS 31:31
#define DMA11_CS_RESET_SET 0x80000000
#define DMA11_CS_RESET_CLR 0x7fffffff
#define DMA11_CS_RESET_MSB 31
#define DMA11_CS_RESET_LSB 31
#define DMA11_CS_ABORT_BITS 30:30
#define DMA11_CS_ABORT_SET 0x40000000
#define DMA11_CS_ABORT_CLR 0xbfffffff
#define DMA11_CS_ABORT_MSB 30
#define DMA11_CS_ABORT_LSB 30
#define DMA11_CS_DISDEBUG_BITS 29:29
#define DMA11_CS_DISDEBUG_SET 0x20000000
#define DMA11_CS_DISDEBUG_CLR 0xdfffffff
#define DMA11_CS_DISDEBUG_MSB 29
#define DMA11_CS_DISDEBUG_LSB 29
#define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA11_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA11_CS_PANIC_PRIORITY_BITS 23:20
#define DMA11_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA11_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA11_CS_PANIC_PRIORITY_MSB 23
#define DMA11_CS_PANIC_PRIORITY_LSB 20
#define DMA11_CS_PRIORITY_BITS 19:16
#define DMA11_CS_PRIORITY_SET 0x000f0000
#define DMA11_CS_PRIORITY_CLR 0xfff0ffff
#define DMA11_CS_PRIORITY_MSB 19
#define DMA11_CS_PRIORITY_LSB 16
#define DMA11_CS_ERROR_BITS 8:8
#define DMA11_CS_ERROR_SET 0x00000100
#define DMA11_CS_ERROR_CLR 0xfffffeff
#define DMA11_CS_ERROR_MSB 8
#define DMA11_CS_ERROR_LSB 8
#define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA11_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA11_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA11_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA11_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA11_CS_DREQ_STOPS_DMA_MSB 5
#define DMA11_CS_DREQ_STOPS_DMA_LSB 5
#define DMA11_CS_PAUSED_BITS 4:4
#define DMA11_CS_PAUSED_SET 0x00000010
#define DMA11_CS_PAUSED_CLR 0xffffffef
#define DMA11_CS_PAUSED_MSB 4
#define DMA11_CS_PAUSED_LSB 4
#define DMA11_CS_DREQ_BITS 3:3
#define DMA11_CS_DREQ_SET 0x00000008
#define DMA11_CS_DREQ_CLR 0xfffffff7
#define DMA11_CS_DREQ_MSB 3
#define DMA11_CS_DREQ_LSB 3
#define DMA11_CS_INT_BITS 2:2
#define DMA11_CS_INT_SET 0x00000004
#define DMA11_CS_INT_CLR 0xfffffffb
#define DMA11_CS_INT_MSB 2
#define DMA11_CS_INT_LSB 2
#define DMA11_CS_END_BITS 1:1
#define DMA11_CS_END_SET 0x00000002
#define DMA11_CS_END_CLR 0xfffffffd
#define DMA11_CS_END_MSB 1
#define DMA11_CS_END_LSB 1
#define DMA11_CS_ACTIVE_BITS 0:0
#define DMA11_CS_ACTIVE_SET 0x00000001
#define DMA11_CS_ACTIVE_CLR 0xfffffffe
#define DMA11_CS_ACTIVE_MSB 0
#define DMA11_CS_ACTIVE_LSB 0
#define DMA11_CONBLK_AD HW_REGISTER_RW( 0x7e007b04 )
#define DMA11_CONBLK_AD_MASK 0xffffffe0
#define DMA11_CONBLK_AD_WIDTH 32
#define DMA11_CONBLK_AD_RESET 0000000000
#define DMA11_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA11_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA11_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA11_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA11_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA11_TI HW_REGISTER_RO( 0x7e007b08 )
#define DMA11_TI_MASK 0x03fffff9
#define DMA11_TI_WIDTH 26
#define DMA11_TI_WAITS_BITS 25:21
#define DMA11_TI_WAITS_SET 0x03e00000
#define DMA11_TI_WAITS_CLR 0xfc1fffff
#define DMA11_TI_WAITS_MSB 25
#define DMA11_TI_WAITS_LSB 21
#define DMA11_TI_PERMAP_BITS 20:16
#define DMA11_TI_PERMAP_SET 0x001f0000
#define DMA11_TI_PERMAP_CLR 0xffe0ffff
#define DMA11_TI_PERMAP_MSB 20
#define DMA11_TI_PERMAP_LSB 16
#define DMA11_TI_BURST_LENGTH_BITS 15:12
#define DMA11_TI_BURST_LENGTH_SET 0x0000f000
#define DMA11_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA11_TI_BURST_LENGTH_MSB 15
#define DMA11_TI_BURST_LENGTH_LSB 12
#define DMA11_TI_SRC_IGNORE_BITS 11:11
#define DMA11_TI_SRC_IGNORE_SET 0x00000800
#define DMA11_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA11_TI_SRC_IGNORE_MSB 11
#define DMA11_TI_SRC_IGNORE_LSB 11
#define DMA11_TI_SRC_DREQ_BITS 10:10
#define DMA11_TI_SRC_DREQ_SET 0x00000400
#define DMA11_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA11_TI_SRC_DREQ_MSB 10
#define DMA11_TI_SRC_DREQ_LSB 10
#define DMA11_TI_SRC_WIDTH_BITS 9:9
#define DMA11_TI_SRC_WIDTH_SET 0x00000200
#define DMA11_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA11_TI_SRC_WIDTH_MSB 9
#define DMA11_TI_SRC_WIDTH_LSB 9
#define DMA11_TI_SRC_INC_BITS 8:8
#define DMA11_TI_SRC_INC_SET 0x00000100
#define DMA11_TI_SRC_INC_CLR 0xfffffeff
#define DMA11_TI_SRC_INC_MSB 8
#define DMA11_TI_SRC_INC_LSB 8
#define DMA11_TI_DEST_IGNORE_BITS 7:7
#define DMA11_TI_DEST_IGNORE_SET 0x00000080
#define DMA11_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA11_TI_DEST_IGNORE_MSB 7
#define DMA11_TI_DEST_IGNORE_LSB 7
#define DMA11_TI_DEST_DREQ_BITS 6:6
#define DMA11_TI_DEST_DREQ_SET 0x00000040
#define DMA11_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA11_TI_DEST_DREQ_MSB 6
#define DMA11_TI_DEST_DREQ_LSB 6
#define DMA11_TI_DEST_WIDTH_BITS 5:5
#define DMA11_TI_DEST_WIDTH_SET 0x00000020
#define DMA11_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA11_TI_DEST_WIDTH_MSB 5
#define DMA11_TI_DEST_WIDTH_LSB 5
#define DMA11_TI_DEST_INC_BITS 4:4
#define DMA11_TI_DEST_INC_SET 0x00000010
#define DMA11_TI_DEST_INC_CLR 0xffffffef
#define DMA11_TI_DEST_INC_MSB 4
#define DMA11_TI_DEST_INC_LSB 4
#define DMA11_TI_WAIT_RESP_BITS 3:3
#define DMA11_TI_WAIT_RESP_SET 0x00000008
#define DMA11_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA11_TI_WAIT_RESP_MSB 3
#define DMA11_TI_WAIT_RESP_LSB 3
#define DMA11_TI_INTEN_BITS 0:0
#define DMA11_TI_INTEN_SET 0x00000001
#define DMA11_TI_INTEN_CLR 0xfffffffe
#define DMA11_TI_INTEN_MSB 0
#define DMA11_TI_INTEN_LSB 0
#define DMA11_SOURCE_AD HW_REGISTER_RO( 0x7e007b0c )
#define DMA11_SOURCE_AD_MASK 0xffffffff
#define DMA11_SOURCE_AD_WIDTH 32
#define DMA11_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA11_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA11_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA11_SOURCE_AD_S_ADDR_MSB 31
#define DMA11_SOURCE_AD_S_ADDR_LSB 0
#define DMA11_DEST_AD HW_REGISTER_RO( 0x7e007b10 )
#define DMA11_DEST_AD_MASK 0xffffffff
#define DMA11_DEST_AD_WIDTH 32
#define DMA11_DEST_AD_D_ADDR_BITS 31:0
#define DMA11_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA11_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA11_DEST_AD_D_ADDR_MSB 31
#define DMA11_DEST_AD_D_ADDR_LSB 0
#define DMA11_TXFR_LEN HW_REGISTER_RO( 0x7e007b14 )
#define DMA11_TXFR_LEN_MASK 0x0000ffff
#define DMA11_TXFR_LEN_WIDTH 16
#define DMA11_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA11_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA11_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA11_TXFR_LEN_XLENGTH_MSB 15
#define DMA11_TXFR_LEN_XLENGTH_LSB 0
#define DMA11_NEXTCONBK HW_REGISTER_RO( 0x7e007b1c )
#define DMA11_NEXTCONBK_MASK 0xffffffe0
#define DMA11_NEXTCONBK_WIDTH 32
#define DMA11_NEXTCONBK_ADDR_BITS 31:5
#define DMA11_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA11_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA11_NEXTCONBK_ADDR_MSB 31
#define DMA11_NEXTCONBK_ADDR_LSB 5
#define DMA11_DEBUG HW_REGISTER_RW( 0x7e007b20 )
#define DMA11_DEBUG_MASK 0x1ffffff7
#define DMA11_DEBUG_WIDTH 29
#define DMA11_DEBUG_RESET 0000000000
#define DMA11_DEBUG_LITE_BITS 28:28
#define DMA11_DEBUG_LITE_SET 0x10000000
#define DMA11_DEBUG_LITE_CLR 0xefffffff
#define DMA11_DEBUG_LITE_MSB 28
#define DMA11_DEBUG_LITE_LSB 28
#define DMA11_DEBUG_VERSION_BITS 27:25
#define DMA11_DEBUG_VERSION_SET 0x0e000000
#define DMA11_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA11_DEBUG_VERSION_MSB 27
#define DMA11_DEBUG_VERSION_LSB 25
#define DMA11_DEBUG_DMA_STATE_BITS 24:16
#define DMA11_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA11_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA11_DEBUG_DMA_STATE_MSB 24
#define DMA11_DEBUG_DMA_STATE_LSB 16
#define DMA11_DEBUG_DMA_ID_BITS 15:8
#define DMA11_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA11_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA11_DEBUG_DMA_ID_MSB 15
#define DMA11_DEBUG_DMA_ID_LSB 8
#define DMA11_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA11_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA11_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA11_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA11_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA11_DEBUG_READ_ERROR_BITS 2:2
#define DMA11_DEBUG_READ_ERROR_SET 0x00000004
#define DMA11_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA11_DEBUG_READ_ERROR_MSB 2
#define DMA11_DEBUG_READ_ERROR_LSB 2
#define DMA11_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA11_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA11_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA11_DEBUG_FIFO_ERROR_MSB 1
#define DMA11_DEBUG_FIFO_ERROR_LSB 1
#define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA11_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite12.h Executable file
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// This file was generated by the create_regs script
#define DMA12_BASE 0x7e007c00
#define DMA12_CS HW_REGISTER_RW( 0x7e007c00 )
#define DMA12_CS_MASK 0xf0ff017f
#define DMA12_CS_WIDTH 32
#define DMA12_CS_RESET 0000000000
#define DMA12_CS_RESET_BITS 31:31
#define DMA12_CS_RESET_SET 0x80000000
#define DMA12_CS_RESET_CLR 0x7fffffff
#define DMA12_CS_RESET_MSB 31
#define DMA12_CS_RESET_LSB 31
#define DMA12_CS_ABORT_BITS 30:30
#define DMA12_CS_ABORT_SET 0x40000000
#define DMA12_CS_ABORT_CLR 0xbfffffff
#define DMA12_CS_ABORT_MSB 30
#define DMA12_CS_ABORT_LSB 30
#define DMA12_CS_DISDEBUG_BITS 29:29
#define DMA12_CS_DISDEBUG_SET 0x20000000
#define DMA12_CS_DISDEBUG_CLR 0xdfffffff
#define DMA12_CS_DISDEBUG_MSB 29
#define DMA12_CS_DISDEBUG_LSB 29
#define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA12_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA12_CS_PANIC_PRIORITY_BITS 23:20
#define DMA12_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA12_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA12_CS_PANIC_PRIORITY_MSB 23
#define DMA12_CS_PANIC_PRIORITY_LSB 20
#define DMA12_CS_PRIORITY_BITS 19:16
#define DMA12_CS_PRIORITY_SET 0x000f0000
#define DMA12_CS_PRIORITY_CLR 0xfff0ffff
#define DMA12_CS_PRIORITY_MSB 19
#define DMA12_CS_PRIORITY_LSB 16
#define DMA12_CS_ERROR_BITS 8:8
#define DMA12_CS_ERROR_SET 0x00000100
#define DMA12_CS_ERROR_CLR 0xfffffeff
#define DMA12_CS_ERROR_MSB 8
#define DMA12_CS_ERROR_LSB 8
#define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA12_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA12_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA12_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA12_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA12_CS_DREQ_STOPS_DMA_MSB 5
#define DMA12_CS_DREQ_STOPS_DMA_LSB 5
#define DMA12_CS_PAUSED_BITS 4:4
#define DMA12_CS_PAUSED_SET 0x00000010
#define DMA12_CS_PAUSED_CLR 0xffffffef
#define DMA12_CS_PAUSED_MSB 4
#define DMA12_CS_PAUSED_LSB 4
#define DMA12_CS_DREQ_BITS 3:3
#define DMA12_CS_DREQ_SET 0x00000008
#define DMA12_CS_DREQ_CLR 0xfffffff7
#define DMA12_CS_DREQ_MSB 3
#define DMA12_CS_DREQ_LSB 3
#define DMA12_CS_INT_BITS 2:2
#define DMA12_CS_INT_SET 0x00000004
#define DMA12_CS_INT_CLR 0xfffffffb
#define DMA12_CS_INT_MSB 2
#define DMA12_CS_INT_LSB 2
#define DMA12_CS_END_BITS 1:1
#define DMA12_CS_END_SET 0x00000002
#define DMA12_CS_END_CLR 0xfffffffd
#define DMA12_CS_END_MSB 1
#define DMA12_CS_END_LSB 1
#define DMA12_CS_ACTIVE_BITS 0:0
#define DMA12_CS_ACTIVE_SET 0x00000001
#define DMA12_CS_ACTIVE_CLR 0xfffffffe
#define DMA12_CS_ACTIVE_MSB 0
#define DMA12_CS_ACTIVE_LSB 0
#define DMA12_CONBLK_AD HW_REGISTER_RW( 0x7e007c04 )
#define DMA12_CONBLK_AD_MASK 0xffffffe0
#define DMA12_CONBLK_AD_WIDTH 32
#define DMA12_CONBLK_AD_RESET 0000000000
#define DMA12_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA12_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA12_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA12_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA12_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA12_TI HW_REGISTER_RO( 0x7e007c08 )
#define DMA12_TI_MASK 0x03fffff9
#define DMA12_TI_WIDTH 26
#define DMA12_TI_WAITS_BITS 25:21
#define DMA12_TI_WAITS_SET 0x03e00000
#define DMA12_TI_WAITS_CLR 0xfc1fffff
#define DMA12_TI_WAITS_MSB 25
#define DMA12_TI_WAITS_LSB 21
#define DMA12_TI_PERMAP_BITS 20:16
#define DMA12_TI_PERMAP_SET 0x001f0000
#define DMA12_TI_PERMAP_CLR 0xffe0ffff
#define DMA12_TI_PERMAP_MSB 20
#define DMA12_TI_PERMAP_LSB 16
#define DMA12_TI_BURST_LENGTH_BITS 15:12
#define DMA12_TI_BURST_LENGTH_SET 0x0000f000
#define DMA12_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA12_TI_BURST_LENGTH_MSB 15
#define DMA12_TI_BURST_LENGTH_LSB 12
#define DMA12_TI_SRC_IGNORE_BITS 11:11
#define DMA12_TI_SRC_IGNORE_SET 0x00000800
#define DMA12_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA12_TI_SRC_IGNORE_MSB 11
#define DMA12_TI_SRC_IGNORE_LSB 11
#define DMA12_TI_SRC_DREQ_BITS 10:10
#define DMA12_TI_SRC_DREQ_SET 0x00000400
#define DMA12_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA12_TI_SRC_DREQ_MSB 10
#define DMA12_TI_SRC_DREQ_LSB 10
#define DMA12_TI_SRC_WIDTH_BITS 9:9
#define DMA12_TI_SRC_WIDTH_SET 0x00000200
#define DMA12_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA12_TI_SRC_WIDTH_MSB 9
#define DMA12_TI_SRC_WIDTH_LSB 9
#define DMA12_TI_SRC_INC_BITS 8:8
#define DMA12_TI_SRC_INC_SET 0x00000100
#define DMA12_TI_SRC_INC_CLR 0xfffffeff
#define DMA12_TI_SRC_INC_MSB 8
#define DMA12_TI_SRC_INC_LSB 8
#define DMA12_TI_DEST_IGNORE_BITS 7:7
#define DMA12_TI_DEST_IGNORE_SET 0x00000080
#define DMA12_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA12_TI_DEST_IGNORE_MSB 7
#define DMA12_TI_DEST_IGNORE_LSB 7
#define DMA12_TI_DEST_DREQ_BITS 6:6
#define DMA12_TI_DEST_DREQ_SET 0x00000040
#define DMA12_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA12_TI_DEST_DREQ_MSB 6
#define DMA12_TI_DEST_DREQ_LSB 6
#define DMA12_TI_DEST_WIDTH_BITS 5:5
#define DMA12_TI_DEST_WIDTH_SET 0x00000020
#define DMA12_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA12_TI_DEST_WIDTH_MSB 5
#define DMA12_TI_DEST_WIDTH_LSB 5
#define DMA12_TI_DEST_INC_BITS 4:4
#define DMA12_TI_DEST_INC_SET 0x00000010
#define DMA12_TI_DEST_INC_CLR 0xffffffef
#define DMA12_TI_DEST_INC_MSB 4
#define DMA12_TI_DEST_INC_LSB 4
#define DMA12_TI_WAIT_RESP_BITS 3:3
#define DMA12_TI_WAIT_RESP_SET 0x00000008
#define DMA12_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA12_TI_WAIT_RESP_MSB 3
#define DMA12_TI_WAIT_RESP_LSB 3
#define DMA12_TI_INTEN_BITS 0:0
#define DMA12_TI_INTEN_SET 0x00000001
#define DMA12_TI_INTEN_CLR 0xfffffffe
#define DMA12_TI_INTEN_MSB 0
#define DMA12_TI_INTEN_LSB 0
#define DMA12_SOURCE_AD HW_REGISTER_RO( 0x7e007c0c )
#define DMA12_SOURCE_AD_MASK 0xffffffff
#define DMA12_SOURCE_AD_WIDTH 32
#define DMA12_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA12_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA12_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA12_SOURCE_AD_S_ADDR_MSB 31
#define DMA12_SOURCE_AD_S_ADDR_LSB 0
#define DMA12_DEST_AD HW_REGISTER_RO( 0x7e007c10 )
#define DMA12_DEST_AD_MASK 0xffffffff
#define DMA12_DEST_AD_WIDTH 32
#define DMA12_DEST_AD_D_ADDR_BITS 31:0
#define DMA12_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA12_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA12_DEST_AD_D_ADDR_MSB 31
#define DMA12_DEST_AD_D_ADDR_LSB 0
#define DMA12_TXFR_LEN HW_REGISTER_RO( 0x7e007c14 )
#define DMA12_TXFR_LEN_MASK 0x0000ffff
#define DMA12_TXFR_LEN_WIDTH 16
#define DMA12_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA12_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA12_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA12_TXFR_LEN_XLENGTH_MSB 15
#define DMA12_TXFR_LEN_XLENGTH_LSB 0
#define DMA12_NEXTCONBK HW_REGISTER_RO( 0x7e007c1c )
#define DMA12_NEXTCONBK_MASK 0xffffffe0
#define DMA12_NEXTCONBK_WIDTH 32
#define DMA12_NEXTCONBK_ADDR_BITS 31:5
#define DMA12_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA12_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA12_NEXTCONBK_ADDR_MSB 31
#define DMA12_NEXTCONBK_ADDR_LSB 5
#define DMA12_DEBUG HW_REGISTER_RW( 0x7e007c20 )
#define DMA12_DEBUG_MASK 0x1ffffff7
#define DMA12_DEBUG_WIDTH 29
#define DMA12_DEBUG_RESET 0000000000
#define DMA12_DEBUG_LITE_BITS 28:28
#define DMA12_DEBUG_LITE_SET 0x10000000
#define DMA12_DEBUG_LITE_CLR 0xefffffff
#define DMA12_DEBUG_LITE_MSB 28
#define DMA12_DEBUG_LITE_LSB 28
#define DMA12_DEBUG_VERSION_BITS 27:25
#define DMA12_DEBUG_VERSION_SET 0x0e000000
#define DMA12_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA12_DEBUG_VERSION_MSB 27
#define DMA12_DEBUG_VERSION_LSB 25
#define DMA12_DEBUG_DMA_STATE_BITS 24:16
#define DMA12_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA12_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA12_DEBUG_DMA_STATE_MSB 24
#define DMA12_DEBUG_DMA_STATE_LSB 16
#define DMA12_DEBUG_DMA_ID_BITS 15:8
#define DMA12_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA12_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA12_DEBUG_DMA_ID_MSB 15
#define DMA12_DEBUG_DMA_ID_LSB 8
#define DMA12_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA12_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA12_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA12_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA12_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA12_DEBUG_READ_ERROR_BITS 2:2
#define DMA12_DEBUG_READ_ERROR_SET 0x00000004
#define DMA12_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA12_DEBUG_READ_ERROR_MSB 2
#define DMA12_DEBUG_READ_ERROR_LSB 2
#define DMA12_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA12_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA12_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA12_DEBUG_FIFO_ERROR_MSB 1
#define DMA12_DEBUG_FIFO_ERROR_LSB 1
#define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA12_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite13.h Executable file
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// This file was generated by the create_regs script
#define DMA13_BASE 0x7e007d00
#define DMA13_CS HW_REGISTER_RW( 0x7e007d00 )
#define DMA13_CS_MASK 0xf0ff017f
#define DMA13_CS_WIDTH 32
#define DMA13_CS_RESET 0000000000
#define DMA13_CS_RESET_BITS 31:31
#define DMA13_CS_RESET_SET 0x80000000
#define DMA13_CS_RESET_CLR 0x7fffffff
#define DMA13_CS_RESET_MSB 31
#define DMA13_CS_RESET_LSB 31
#define DMA13_CS_ABORT_BITS 30:30
#define DMA13_CS_ABORT_SET 0x40000000
#define DMA13_CS_ABORT_CLR 0xbfffffff
#define DMA13_CS_ABORT_MSB 30
#define DMA13_CS_ABORT_LSB 30
#define DMA13_CS_DISDEBUG_BITS 29:29
#define DMA13_CS_DISDEBUG_SET 0x20000000
#define DMA13_CS_DISDEBUG_CLR 0xdfffffff
#define DMA13_CS_DISDEBUG_MSB 29
#define DMA13_CS_DISDEBUG_LSB 29
#define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA13_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA13_CS_PANIC_PRIORITY_BITS 23:20
#define DMA13_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA13_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA13_CS_PANIC_PRIORITY_MSB 23
#define DMA13_CS_PANIC_PRIORITY_LSB 20
#define DMA13_CS_PRIORITY_BITS 19:16
#define DMA13_CS_PRIORITY_SET 0x000f0000
#define DMA13_CS_PRIORITY_CLR 0xfff0ffff
#define DMA13_CS_PRIORITY_MSB 19
#define DMA13_CS_PRIORITY_LSB 16
#define DMA13_CS_ERROR_BITS 8:8
#define DMA13_CS_ERROR_SET 0x00000100
#define DMA13_CS_ERROR_CLR 0xfffffeff
#define DMA13_CS_ERROR_MSB 8
#define DMA13_CS_ERROR_LSB 8
#define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA13_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA13_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA13_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA13_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA13_CS_DREQ_STOPS_DMA_MSB 5
#define DMA13_CS_DREQ_STOPS_DMA_LSB 5
#define DMA13_CS_PAUSED_BITS 4:4
#define DMA13_CS_PAUSED_SET 0x00000010
#define DMA13_CS_PAUSED_CLR 0xffffffef
#define DMA13_CS_PAUSED_MSB 4
#define DMA13_CS_PAUSED_LSB 4
#define DMA13_CS_DREQ_BITS 3:3
#define DMA13_CS_DREQ_SET 0x00000008
#define DMA13_CS_DREQ_CLR 0xfffffff7
#define DMA13_CS_DREQ_MSB 3
#define DMA13_CS_DREQ_LSB 3
#define DMA13_CS_INT_BITS 2:2
#define DMA13_CS_INT_SET 0x00000004
#define DMA13_CS_INT_CLR 0xfffffffb
#define DMA13_CS_INT_MSB 2
#define DMA13_CS_INT_LSB 2
#define DMA13_CS_END_BITS 1:1
#define DMA13_CS_END_SET 0x00000002
#define DMA13_CS_END_CLR 0xfffffffd
#define DMA13_CS_END_MSB 1
#define DMA13_CS_END_LSB 1
#define DMA13_CS_ACTIVE_BITS 0:0
#define DMA13_CS_ACTIVE_SET 0x00000001
#define DMA13_CS_ACTIVE_CLR 0xfffffffe
#define DMA13_CS_ACTIVE_MSB 0
#define DMA13_CS_ACTIVE_LSB 0
#define DMA13_CONBLK_AD HW_REGISTER_RW( 0x7e007d04 )
#define DMA13_CONBLK_AD_MASK 0xffffffe0
#define DMA13_CONBLK_AD_WIDTH 32
#define DMA13_CONBLK_AD_RESET 0000000000
#define DMA13_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA13_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA13_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA13_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA13_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA13_TI HW_REGISTER_RO( 0x7e007d08 )
#define DMA13_TI_MASK 0x03fffff9
#define DMA13_TI_WIDTH 26
#define DMA13_TI_WAITS_BITS 25:21
#define DMA13_TI_WAITS_SET 0x03e00000
#define DMA13_TI_WAITS_CLR 0xfc1fffff
#define DMA13_TI_WAITS_MSB 25
#define DMA13_TI_WAITS_LSB 21
#define DMA13_TI_PERMAP_BITS 20:16
#define DMA13_TI_PERMAP_SET 0x001f0000
#define DMA13_TI_PERMAP_CLR 0xffe0ffff
#define DMA13_TI_PERMAP_MSB 20
#define DMA13_TI_PERMAP_LSB 16
#define DMA13_TI_BURST_LENGTH_BITS 15:12
#define DMA13_TI_BURST_LENGTH_SET 0x0000f000
#define DMA13_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA13_TI_BURST_LENGTH_MSB 15
#define DMA13_TI_BURST_LENGTH_LSB 12
#define DMA13_TI_SRC_IGNORE_BITS 11:11
#define DMA13_TI_SRC_IGNORE_SET 0x00000800
#define DMA13_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA13_TI_SRC_IGNORE_MSB 11
#define DMA13_TI_SRC_IGNORE_LSB 11
#define DMA13_TI_SRC_DREQ_BITS 10:10
#define DMA13_TI_SRC_DREQ_SET 0x00000400
#define DMA13_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA13_TI_SRC_DREQ_MSB 10
#define DMA13_TI_SRC_DREQ_LSB 10
#define DMA13_TI_SRC_WIDTH_BITS 9:9
#define DMA13_TI_SRC_WIDTH_SET 0x00000200
#define DMA13_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA13_TI_SRC_WIDTH_MSB 9
#define DMA13_TI_SRC_WIDTH_LSB 9
#define DMA13_TI_SRC_INC_BITS 8:8
#define DMA13_TI_SRC_INC_SET 0x00000100
#define DMA13_TI_SRC_INC_CLR 0xfffffeff
#define DMA13_TI_SRC_INC_MSB 8
#define DMA13_TI_SRC_INC_LSB 8
#define DMA13_TI_DEST_IGNORE_BITS 7:7
#define DMA13_TI_DEST_IGNORE_SET 0x00000080
#define DMA13_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA13_TI_DEST_IGNORE_MSB 7
#define DMA13_TI_DEST_IGNORE_LSB 7
#define DMA13_TI_DEST_DREQ_BITS 6:6
#define DMA13_TI_DEST_DREQ_SET 0x00000040
#define DMA13_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA13_TI_DEST_DREQ_MSB 6
#define DMA13_TI_DEST_DREQ_LSB 6
#define DMA13_TI_DEST_WIDTH_BITS 5:5
#define DMA13_TI_DEST_WIDTH_SET 0x00000020
#define DMA13_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA13_TI_DEST_WIDTH_MSB 5
#define DMA13_TI_DEST_WIDTH_LSB 5
#define DMA13_TI_DEST_INC_BITS 4:4
#define DMA13_TI_DEST_INC_SET 0x00000010
#define DMA13_TI_DEST_INC_CLR 0xffffffef
#define DMA13_TI_DEST_INC_MSB 4
#define DMA13_TI_DEST_INC_LSB 4
#define DMA13_TI_WAIT_RESP_BITS 3:3
#define DMA13_TI_WAIT_RESP_SET 0x00000008
#define DMA13_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA13_TI_WAIT_RESP_MSB 3
#define DMA13_TI_WAIT_RESP_LSB 3
#define DMA13_TI_INTEN_BITS 0:0
#define DMA13_TI_INTEN_SET 0x00000001
#define DMA13_TI_INTEN_CLR 0xfffffffe
#define DMA13_TI_INTEN_MSB 0
#define DMA13_TI_INTEN_LSB 0
#define DMA13_SOURCE_AD HW_REGISTER_RO( 0x7e007d0c )
#define DMA13_SOURCE_AD_MASK 0xffffffff
#define DMA13_SOURCE_AD_WIDTH 32
#define DMA13_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA13_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA13_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA13_SOURCE_AD_S_ADDR_MSB 31
#define DMA13_SOURCE_AD_S_ADDR_LSB 0
#define DMA13_DEST_AD HW_REGISTER_RO( 0x7e007d10 )
#define DMA13_DEST_AD_MASK 0xffffffff
#define DMA13_DEST_AD_WIDTH 32
#define DMA13_DEST_AD_D_ADDR_BITS 31:0
#define DMA13_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA13_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA13_DEST_AD_D_ADDR_MSB 31
#define DMA13_DEST_AD_D_ADDR_LSB 0
#define DMA13_TXFR_LEN HW_REGISTER_RO( 0x7e007d14 )
#define DMA13_TXFR_LEN_MASK 0x0000ffff
#define DMA13_TXFR_LEN_WIDTH 16
#define DMA13_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA13_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA13_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA13_TXFR_LEN_XLENGTH_MSB 15
#define DMA13_TXFR_LEN_XLENGTH_LSB 0
#define DMA13_NEXTCONBK HW_REGISTER_RO( 0x7e007d1c )
#define DMA13_NEXTCONBK_MASK 0xffffffe0
#define DMA13_NEXTCONBK_WIDTH 32
#define DMA13_NEXTCONBK_ADDR_BITS 31:5
#define DMA13_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA13_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA13_NEXTCONBK_ADDR_MSB 31
#define DMA13_NEXTCONBK_ADDR_LSB 5
#define DMA13_DEBUG HW_REGISTER_RW( 0x7e007d20 )
#define DMA13_DEBUG_MASK 0x1ffffff7
#define DMA13_DEBUG_WIDTH 29
#define DMA13_DEBUG_RESET 0000000000
#define DMA13_DEBUG_LITE_BITS 28:28
#define DMA13_DEBUG_LITE_SET 0x10000000
#define DMA13_DEBUG_LITE_CLR 0xefffffff
#define DMA13_DEBUG_LITE_MSB 28
#define DMA13_DEBUG_LITE_LSB 28
#define DMA13_DEBUG_VERSION_BITS 27:25
#define DMA13_DEBUG_VERSION_SET 0x0e000000
#define DMA13_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA13_DEBUG_VERSION_MSB 27
#define DMA13_DEBUG_VERSION_LSB 25
#define DMA13_DEBUG_DMA_STATE_BITS 24:16
#define DMA13_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA13_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA13_DEBUG_DMA_STATE_MSB 24
#define DMA13_DEBUG_DMA_STATE_LSB 16
#define DMA13_DEBUG_DMA_ID_BITS 15:8
#define DMA13_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA13_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA13_DEBUG_DMA_ID_MSB 15
#define DMA13_DEBUG_DMA_ID_LSB 8
#define DMA13_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA13_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA13_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA13_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA13_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA13_DEBUG_READ_ERROR_BITS 2:2
#define DMA13_DEBUG_READ_ERROR_SET 0x00000004
#define DMA13_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA13_DEBUG_READ_ERROR_MSB 2
#define DMA13_DEBUG_READ_ERROR_LSB 2
#define DMA13_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA13_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA13_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA13_DEBUG_FIFO_ERROR_MSB 1
#define DMA13_DEBUG_FIFO_ERROR_LSB 1
#define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA13_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite14.h Executable file
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// This file was generated by the create_regs script
#define DMA14_BASE 0x7e007e00
#define DMA14_CS HW_REGISTER_RW( 0x7e007e00 )
#define DMA14_CS_MASK 0xf0ff017f
#define DMA14_CS_WIDTH 32
#define DMA14_CS_RESET 0000000000
#define DMA14_CS_RESET_BITS 31:31
#define DMA14_CS_RESET_SET 0x80000000
#define DMA14_CS_RESET_CLR 0x7fffffff
#define DMA14_CS_RESET_MSB 31
#define DMA14_CS_RESET_LSB 31
#define DMA14_CS_ABORT_BITS 30:30
#define DMA14_CS_ABORT_SET 0x40000000
#define DMA14_CS_ABORT_CLR 0xbfffffff
#define DMA14_CS_ABORT_MSB 30
#define DMA14_CS_ABORT_LSB 30
#define DMA14_CS_DISDEBUG_BITS 29:29
#define DMA14_CS_DISDEBUG_SET 0x20000000
#define DMA14_CS_DISDEBUG_CLR 0xdfffffff
#define DMA14_CS_DISDEBUG_MSB 29
#define DMA14_CS_DISDEBUG_LSB 29
#define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA14_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA14_CS_PANIC_PRIORITY_BITS 23:20
#define DMA14_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA14_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA14_CS_PANIC_PRIORITY_MSB 23
#define DMA14_CS_PANIC_PRIORITY_LSB 20
#define DMA14_CS_PRIORITY_BITS 19:16
#define DMA14_CS_PRIORITY_SET 0x000f0000
#define DMA14_CS_PRIORITY_CLR 0xfff0ffff
#define DMA14_CS_PRIORITY_MSB 19
#define DMA14_CS_PRIORITY_LSB 16
#define DMA14_CS_ERROR_BITS 8:8
#define DMA14_CS_ERROR_SET 0x00000100
#define DMA14_CS_ERROR_CLR 0xfffffeff
#define DMA14_CS_ERROR_MSB 8
#define DMA14_CS_ERROR_LSB 8
#define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA14_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA14_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA14_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA14_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA14_CS_DREQ_STOPS_DMA_MSB 5
#define DMA14_CS_DREQ_STOPS_DMA_LSB 5
#define DMA14_CS_PAUSED_BITS 4:4
#define DMA14_CS_PAUSED_SET 0x00000010
#define DMA14_CS_PAUSED_CLR 0xffffffef
#define DMA14_CS_PAUSED_MSB 4
#define DMA14_CS_PAUSED_LSB 4
#define DMA14_CS_DREQ_BITS 3:3
#define DMA14_CS_DREQ_SET 0x00000008
#define DMA14_CS_DREQ_CLR 0xfffffff7
#define DMA14_CS_DREQ_MSB 3
#define DMA14_CS_DREQ_LSB 3
#define DMA14_CS_INT_BITS 2:2
#define DMA14_CS_INT_SET 0x00000004
#define DMA14_CS_INT_CLR 0xfffffffb
#define DMA14_CS_INT_MSB 2
#define DMA14_CS_INT_LSB 2
#define DMA14_CS_END_BITS 1:1
#define DMA14_CS_END_SET 0x00000002
#define DMA14_CS_END_CLR 0xfffffffd
#define DMA14_CS_END_MSB 1
#define DMA14_CS_END_LSB 1
#define DMA14_CS_ACTIVE_BITS 0:0
#define DMA14_CS_ACTIVE_SET 0x00000001
#define DMA14_CS_ACTIVE_CLR 0xfffffffe
#define DMA14_CS_ACTIVE_MSB 0
#define DMA14_CS_ACTIVE_LSB 0
#define DMA14_CONBLK_AD HW_REGISTER_RW( 0x7e007e04 )
#define DMA14_CONBLK_AD_MASK 0xffffffe0
#define DMA14_CONBLK_AD_WIDTH 32
#define DMA14_CONBLK_AD_RESET 0000000000
#define DMA14_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA14_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA14_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA14_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA14_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA14_TI HW_REGISTER_RO( 0x7e007e08 )
#define DMA14_TI_MASK 0x03fffff9
#define DMA14_TI_WIDTH 26
#define DMA14_TI_WAITS_BITS 25:21
#define DMA14_TI_WAITS_SET 0x03e00000
#define DMA14_TI_WAITS_CLR 0xfc1fffff
#define DMA14_TI_WAITS_MSB 25
#define DMA14_TI_WAITS_LSB 21
#define DMA14_TI_PERMAP_BITS 20:16
#define DMA14_TI_PERMAP_SET 0x001f0000
#define DMA14_TI_PERMAP_CLR 0xffe0ffff
#define DMA14_TI_PERMAP_MSB 20
#define DMA14_TI_PERMAP_LSB 16
#define DMA14_TI_BURST_LENGTH_BITS 15:12
#define DMA14_TI_BURST_LENGTH_SET 0x0000f000
#define DMA14_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA14_TI_BURST_LENGTH_MSB 15
#define DMA14_TI_BURST_LENGTH_LSB 12
#define DMA14_TI_SRC_IGNORE_BITS 11:11
#define DMA14_TI_SRC_IGNORE_SET 0x00000800
#define DMA14_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA14_TI_SRC_IGNORE_MSB 11
#define DMA14_TI_SRC_IGNORE_LSB 11
#define DMA14_TI_SRC_DREQ_BITS 10:10
#define DMA14_TI_SRC_DREQ_SET 0x00000400
#define DMA14_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA14_TI_SRC_DREQ_MSB 10
#define DMA14_TI_SRC_DREQ_LSB 10
#define DMA14_TI_SRC_WIDTH_BITS 9:9
#define DMA14_TI_SRC_WIDTH_SET 0x00000200
#define DMA14_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA14_TI_SRC_WIDTH_MSB 9
#define DMA14_TI_SRC_WIDTH_LSB 9
#define DMA14_TI_SRC_INC_BITS 8:8
#define DMA14_TI_SRC_INC_SET 0x00000100
#define DMA14_TI_SRC_INC_CLR 0xfffffeff
#define DMA14_TI_SRC_INC_MSB 8
#define DMA14_TI_SRC_INC_LSB 8
#define DMA14_TI_DEST_IGNORE_BITS 7:7
#define DMA14_TI_DEST_IGNORE_SET 0x00000080
#define DMA14_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA14_TI_DEST_IGNORE_MSB 7
#define DMA14_TI_DEST_IGNORE_LSB 7
#define DMA14_TI_DEST_DREQ_BITS 6:6
#define DMA14_TI_DEST_DREQ_SET 0x00000040
#define DMA14_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA14_TI_DEST_DREQ_MSB 6
#define DMA14_TI_DEST_DREQ_LSB 6
#define DMA14_TI_DEST_WIDTH_BITS 5:5
#define DMA14_TI_DEST_WIDTH_SET 0x00000020
#define DMA14_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA14_TI_DEST_WIDTH_MSB 5
#define DMA14_TI_DEST_WIDTH_LSB 5
#define DMA14_TI_DEST_INC_BITS 4:4
#define DMA14_TI_DEST_INC_SET 0x00000010
#define DMA14_TI_DEST_INC_CLR 0xffffffef
#define DMA14_TI_DEST_INC_MSB 4
#define DMA14_TI_DEST_INC_LSB 4
#define DMA14_TI_WAIT_RESP_BITS 3:3
#define DMA14_TI_WAIT_RESP_SET 0x00000008
#define DMA14_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA14_TI_WAIT_RESP_MSB 3
#define DMA14_TI_WAIT_RESP_LSB 3
#define DMA14_TI_INTEN_BITS 0:0
#define DMA14_TI_INTEN_SET 0x00000001
#define DMA14_TI_INTEN_CLR 0xfffffffe
#define DMA14_TI_INTEN_MSB 0
#define DMA14_TI_INTEN_LSB 0
#define DMA14_SOURCE_AD HW_REGISTER_RO( 0x7e007e0c )
#define DMA14_SOURCE_AD_MASK 0xffffffff
#define DMA14_SOURCE_AD_WIDTH 32
#define DMA14_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA14_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA14_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA14_SOURCE_AD_S_ADDR_MSB 31
#define DMA14_SOURCE_AD_S_ADDR_LSB 0
#define DMA14_DEST_AD HW_REGISTER_RO( 0x7e007e10 )
#define DMA14_DEST_AD_MASK 0xffffffff
#define DMA14_DEST_AD_WIDTH 32
#define DMA14_DEST_AD_D_ADDR_BITS 31:0
#define DMA14_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA14_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA14_DEST_AD_D_ADDR_MSB 31
#define DMA14_DEST_AD_D_ADDR_LSB 0
#define DMA14_TXFR_LEN HW_REGISTER_RO( 0x7e007e14 )
#define DMA14_TXFR_LEN_MASK 0x0000ffff
#define DMA14_TXFR_LEN_WIDTH 16
#define DMA14_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA14_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA14_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA14_TXFR_LEN_XLENGTH_MSB 15
#define DMA14_TXFR_LEN_XLENGTH_LSB 0
#define DMA14_NEXTCONBK HW_REGISTER_RO( 0x7e007e1c )
#define DMA14_NEXTCONBK_MASK 0xffffffe0
#define DMA14_NEXTCONBK_WIDTH 32
#define DMA14_NEXTCONBK_ADDR_BITS 31:5
#define DMA14_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA14_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA14_NEXTCONBK_ADDR_MSB 31
#define DMA14_NEXTCONBK_ADDR_LSB 5
#define DMA14_DEBUG HW_REGISTER_RW( 0x7e007e20 )
#define DMA14_DEBUG_MASK 0x1ffffff7
#define DMA14_DEBUG_WIDTH 29
#define DMA14_DEBUG_RESET 0000000000
#define DMA14_DEBUG_LITE_BITS 28:28
#define DMA14_DEBUG_LITE_SET 0x10000000
#define DMA14_DEBUG_LITE_CLR 0xefffffff
#define DMA14_DEBUG_LITE_MSB 28
#define DMA14_DEBUG_LITE_LSB 28
#define DMA14_DEBUG_VERSION_BITS 27:25
#define DMA14_DEBUG_VERSION_SET 0x0e000000
#define DMA14_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA14_DEBUG_VERSION_MSB 27
#define DMA14_DEBUG_VERSION_LSB 25
#define DMA14_DEBUG_DMA_STATE_BITS 24:16
#define DMA14_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA14_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA14_DEBUG_DMA_STATE_MSB 24
#define DMA14_DEBUG_DMA_STATE_LSB 16
#define DMA14_DEBUG_DMA_ID_BITS 15:8
#define DMA14_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA14_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA14_DEBUG_DMA_ID_MSB 15
#define DMA14_DEBUG_DMA_ID_LSB 8
#define DMA14_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA14_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA14_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA14_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA14_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA14_DEBUG_READ_ERROR_BITS 2:2
#define DMA14_DEBUG_READ_ERROR_SET 0x00000004
#define DMA14_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA14_DEBUG_READ_ERROR_MSB 2
#define DMA14_DEBUG_READ_ERROR_LSB 2
#define DMA14_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA14_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA14_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA14_DEBUG_FIFO_ERROR_MSB 1
#define DMA14_DEBUG_FIFO_ERROR_LSB 1
#define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA14_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite7.h Executable file
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// This file was generated by the create_regs script
#define DMA7_BASE 0x7e007700
#define DMA7_CS HW_REGISTER_RW( 0x7e007700 )
#define DMA7_CS_MASK 0xf0ff017f
#define DMA7_CS_WIDTH 32
#define DMA7_CS_RESET 0000000000
#define DMA7_CS_RESET_BITS 31:31
#define DMA7_CS_RESET_SET 0x80000000
#define DMA7_CS_RESET_CLR 0x7fffffff
#define DMA7_CS_RESET_MSB 31
#define DMA7_CS_RESET_LSB 31
#define DMA7_CS_ABORT_BITS 30:30
#define DMA7_CS_ABORT_SET 0x40000000
#define DMA7_CS_ABORT_CLR 0xbfffffff
#define DMA7_CS_ABORT_MSB 30
#define DMA7_CS_ABORT_LSB 30
#define DMA7_CS_DISDEBUG_BITS 29:29
#define DMA7_CS_DISDEBUG_SET 0x20000000
#define DMA7_CS_DISDEBUG_CLR 0xdfffffff
#define DMA7_CS_DISDEBUG_MSB 29
#define DMA7_CS_DISDEBUG_LSB 29
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA7_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA7_CS_PANIC_PRIORITY_BITS 23:20
#define DMA7_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA7_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA7_CS_PANIC_PRIORITY_MSB 23
#define DMA7_CS_PANIC_PRIORITY_LSB 20
#define DMA7_CS_PRIORITY_BITS 19:16
#define DMA7_CS_PRIORITY_SET 0x000f0000
#define DMA7_CS_PRIORITY_CLR 0xfff0ffff
#define DMA7_CS_PRIORITY_MSB 19
#define DMA7_CS_PRIORITY_LSB 16
#define DMA7_CS_ERROR_BITS 8:8
#define DMA7_CS_ERROR_SET 0x00000100
#define DMA7_CS_ERROR_CLR 0xfffffeff
#define DMA7_CS_ERROR_MSB 8
#define DMA7_CS_ERROR_LSB 8
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA7_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA7_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA7_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA7_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA7_CS_DREQ_STOPS_DMA_MSB 5
#define DMA7_CS_DREQ_STOPS_DMA_LSB 5
#define DMA7_CS_PAUSED_BITS 4:4
#define DMA7_CS_PAUSED_SET 0x00000010
#define DMA7_CS_PAUSED_CLR 0xffffffef
#define DMA7_CS_PAUSED_MSB 4
#define DMA7_CS_PAUSED_LSB 4
#define DMA7_CS_DREQ_BITS 3:3
#define DMA7_CS_DREQ_SET 0x00000008
#define DMA7_CS_DREQ_CLR 0xfffffff7
#define DMA7_CS_DREQ_MSB 3
#define DMA7_CS_DREQ_LSB 3
#define DMA7_CS_INT_BITS 2:2
#define DMA7_CS_INT_SET 0x00000004
#define DMA7_CS_INT_CLR 0xfffffffb
#define DMA7_CS_INT_MSB 2
#define DMA7_CS_INT_LSB 2
#define DMA7_CS_END_BITS 1:1
#define DMA7_CS_END_SET 0x00000002
#define DMA7_CS_END_CLR 0xfffffffd
#define DMA7_CS_END_MSB 1
#define DMA7_CS_END_LSB 1
#define DMA7_CS_ACTIVE_BITS 0:0
#define DMA7_CS_ACTIVE_SET 0x00000001
#define DMA7_CS_ACTIVE_CLR 0xfffffffe
#define DMA7_CS_ACTIVE_MSB 0
#define DMA7_CS_ACTIVE_LSB 0
#define DMA7_CONBLK_AD HW_REGISTER_RW( 0x7e007704 )
#define DMA7_CONBLK_AD_MASK 0xffffffe0
#define DMA7_CONBLK_AD_WIDTH 32
#define DMA7_CONBLK_AD_RESET 0000000000
#define DMA7_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA7_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA7_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA7_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA7_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA7_TI HW_REGISTER_RO( 0x7e007708 )
#define DMA7_TI_MASK 0x03fffff9
#define DMA7_TI_WIDTH 26
#define DMA7_TI_WAITS_BITS 25:21
#define DMA7_TI_WAITS_SET 0x03e00000
#define DMA7_TI_WAITS_CLR 0xfc1fffff
#define DMA7_TI_WAITS_MSB 25
#define DMA7_TI_WAITS_LSB 21
#define DMA7_TI_PERMAP_BITS 20:16
#define DMA7_TI_PERMAP_SET 0x001f0000
#define DMA7_TI_PERMAP_CLR 0xffe0ffff
#define DMA7_TI_PERMAP_MSB 20
#define DMA7_TI_PERMAP_LSB 16
#define DMA7_TI_BURST_LENGTH_BITS 15:12
#define DMA7_TI_BURST_LENGTH_SET 0x0000f000
#define DMA7_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA7_TI_BURST_LENGTH_MSB 15
#define DMA7_TI_BURST_LENGTH_LSB 12
#define DMA7_TI_SRC_IGNORE_BITS 11:11
#define DMA7_TI_SRC_IGNORE_SET 0x00000800
#define DMA7_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA7_TI_SRC_IGNORE_MSB 11
#define DMA7_TI_SRC_IGNORE_LSB 11
#define DMA7_TI_SRC_DREQ_BITS 10:10
#define DMA7_TI_SRC_DREQ_SET 0x00000400
#define DMA7_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA7_TI_SRC_DREQ_MSB 10
#define DMA7_TI_SRC_DREQ_LSB 10
#define DMA7_TI_SRC_WIDTH_BITS 9:9
#define DMA7_TI_SRC_WIDTH_SET 0x00000200
#define DMA7_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA7_TI_SRC_WIDTH_MSB 9
#define DMA7_TI_SRC_WIDTH_LSB 9
#define DMA7_TI_SRC_INC_BITS 8:8
#define DMA7_TI_SRC_INC_SET 0x00000100
#define DMA7_TI_SRC_INC_CLR 0xfffffeff
#define DMA7_TI_SRC_INC_MSB 8
#define DMA7_TI_SRC_INC_LSB 8
#define DMA7_TI_DEST_IGNORE_BITS 7:7
#define DMA7_TI_DEST_IGNORE_SET 0x00000080
#define DMA7_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA7_TI_DEST_IGNORE_MSB 7
#define DMA7_TI_DEST_IGNORE_LSB 7
#define DMA7_TI_DEST_DREQ_BITS 6:6
#define DMA7_TI_DEST_DREQ_SET 0x00000040
#define DMA7_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA7_TI_DEST_DREQ_MSB 6
#define DMA7_TI_DEST_DREQ_LSB 6
#define DMA7_TI_DEST_WIDTH_BITS 5:5
#define DMA7_TI_DEST_WIDTH_SET 0x00000020
#define DMA7_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA7_TI_DEST_WIDTH_MSB 5
#define DMA7_TI_DEST_WIDTH_LSB 5
#define DMA7_TI_DEST_INC_BITS 4:4
#define DMA7_TI_DEST_INC_SET 0x00000010
#define DMA7_TI_DEST_INC_CLR 0xffffffef
#define DMA7_TI_DEST_INC_MSB 4
#define DMA7_TI_DEST_INC_LSB 4
#define DMA7_TI_WAIT_RESP_BITS 3:3
#define DMA7_TI_WAIT_RESP_SET 0x00000008
#define DMA7_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA7_TI_WAIT_RESP_MSB 3
#define DMA7_TI_WAIT_RESP_LSB 3
#define DMA7_TI_INTEN_BITS 0:0
#define DMA7_TI_INTEN_SET 0x00000001
#define DMA7_TI_INTEN_CLR 0xfffffffe
#define DMA7_TI_INTEN_MSB 0
#define DMA7_TI_INTEN_LSB 0
#define DMA7_SOURCE_AD HW_REGISTER_RO( 0x7e00770c )
#define DMA7_SOURCE_AD_MASK 0xffffffff
#define DMA7_SOURCE_AD_WIDTH 32
#define DMA7_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA7_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA7_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA7_SOURCE_AD_S_ADDR_MSB 31
#define DMA7_SOURCE_AD_S_ADDR_LSB 0
#define DMA7_DEST_AD HW_REGISTER_RO( 0x7e007710 )
#define DMA7_DEST_AD_MASK 0xffffffff
#define DMA7_DEST_AD_WIDTH 32
#define DMA7_DEST_AD_D_ADDR_BITS 31:0
#define DMA7_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA7_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA7_DEST_AD_D_ADDR_MSB 31
#define DMA7_DEST_AD_D_ADDR_LSB 0
#define DMA7_TXFR_LEN HW_REGISTER_RO( 0x7e007714 )
#define DMA7_TXFR_LEN_MASK 0x0000ffff
#define DMA7_TXFR_LEN_WIDTH 16
#define DMA7_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA7_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA7_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA7_TXFR_LEN_XLENGTH_MSB 15
#define DMA7_TXFR_LEN_XLENGTH_LSB 0
#define DMA7_NEXTCONBK HW_REGISTER_RO( 0x7e00771c )
#define DMA7_NEXTCONBK_MASK 0xffffffe0
#define DMA7_NEXTCONBK_WIDTH 32
#define DMA7_NEXTCONBK_ADDR_BITS 31:5
#define DMA7_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA7_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA7_NEXTCONBK_ADDR_MSB 31
#define DMA7_NEXTCONBK_ADDR_LSB 5
#define DMA7_DEBUG HW_REGISTER_RW( 0x7e007720 )
#define DMA7_DEBUG_MASK 0x1ffffff7
#define DMA7_DEBUG_WIDTH 29
#define DMA7_DEBUG_RESET 0000000000
#define DMA7_DEBUG_LITE_BITS 28:28
#define DMA7_DEBUG_LITE_SET 0x10000000
#define DMA7_DEBUG_LITE_CLR 0xefffffff
#define DMA7_DEBUG_LITE_MSB 28
#define DMA7_DEBUG_LITE_LSB 28
#define DMA7_DEBUG_VERSION_BITS 27:25
#define DMA7_DEBUG_VERSION_SET 0x0e000000
#define DMA7_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA7_DEBUG_VERSION_MSB 27
#define DMA7_DEBUG_VERSION_LSB 25
#define DMA7_DEBUG_DMA_STATE_BITS 24:16
#define DMA7_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA7_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA7_DEBUG_DMA_STATE_MSB 24
#define DMA7_DEBUG_DMA_STATE_LSB 16
#define DMA7_DEBUG_DMA_ID_BITS 15:8
#define DMA7_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA7_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA7_DEBUG_DMA_ID_MSB 15
#define DMA7_DEBUG_DMA_ID_LSB 8
#define DMA7_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA7_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA7_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA7_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA7_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA7_DEBUG_READ_ERROR_BITS 2:2
#define DMA7_DEBUG_READ_ERROR_SET 0x00000004
#define DMA7_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA7_DEBUG_READ_ERROR_MSB 2
#define DMA7_DEBUG_READ_ERROR_LSB 2
#define DMA7_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA7_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA7_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA7_DEBUG_FIFO_ERROR_MSB 1
#define DMA7_DEBUG_FIFO_ERROR_LSB 1
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA7_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite8.h Executable file
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// This file was generated by the create_regs script
#define DMA8_BASE 0x7e007800
#define DMA8_CS HW_REGISTER_RW( 0x7e007800 )
#define DMA8_CS_MASK 0xf0ff017f
#define DMA8_CS_WIDTH 32
#define DMA8_CS_RESET 0000000000
#define DMA8_CS_RESET_BITS 31:31
#define DMA8_CS_RESET_SET 0x80000000
#define DMA8_CS_RESET_CLR 0x7fffffff
#define DMA8_CS_RESET_MSB 31
#define DMA8_CS_RESET_LSB 31
#define DMA8_CS_ABORT_BITS 30:30
#define DMA8_CS_ABORT_SET 0x40000000
#define DMA8_CS_ABORT_CLR 0xbfffffff
#define DMA8_CS_ABORT_MSB 30
#define DMA8_CS_ABORT_LSB 30
#define DMA8_CS_DISDEBUG_BITS 29:29
#define DMA8_CS_DISDEBUG_SET 0x20000000
#define DMA8_CS_DISDEBUG_CLR 0xdfffffff
#define DMA8_CS_DISDEBUG_MSB 29
#define DMA8_CS_DISDEBUG_LSB 29
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA8_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA8_CS_PANIC_PRIORITY_BITS 23:20
#define DMA8_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA8_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA8_CS_PANIC_PRIORITY_MSB 23
#define DMA8_CS_PANIC_PRIORITY_LSB 20
#define DMA8_CS_PRIORITY_BITS 19:16
#define DMA8_CS_PRIORITY_SET 0x000f0000
#define DMA8_CS_PRIORITY_CLR 0xfff0ffff
#define DMA8_CS_PRIORITY_MSB 19
#define DMA8_CS_PRIORITY_LSB 16
#define DMA8_CS_ERROR_BITS 8:8
#define DMA8_CS_ERROR_SET 0x00000100
#define DMA8_CS_ERROR_CLR 0xfffffeff
#define DMA8_CS_ERROR_MSB 8
#define DMA8_CS_ERROR_LSB 8
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA8_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA8_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA8_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA8_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA8_CS_DREQ_STOPS_DMA_MSB 5
#define DMA8_CS_DREQ_STOPS_DMA_LSB 5
#define DMA8_CS_PAUSED_BITS 4:4
#define DMA8_CS_PAUSED_SET 0x00000010
#define DMA8_CS_PAUSED_CLR 0xffffffef
#define DMA8_CS_PAUSED_MSB 4
#define DMA8_CS_PAUSED_LSB 4
#define DMA8_CS_DREQ_BITS 3:3
#define DMA8_CS_DREQ_SET 0x00000008
#define DMA8_CS_DREQ_CLR 0xfffffff7
#define DMA8_CS_DREQ_MSB 3
#define DMA8_CS_DREQ_LSB 3
#define DMA8_CS_INT_BITS 2:2
#define DMA8_CS_INT_SET 0x00000004
#define DMA8_CS_INT_CLR 0xfffffffb
#define DMA8_CS_INT_MSB 2
#define DMA8_CS_INT_LSB 2
#define DMA8_CS_END_BITS 1:1
#define DMA8_CS_END_SET 0x00000002
#define DMA8_CS_END_CLR 0xfffffffd
#define DMA8_CS_END_MSB 1
#define DMA8_CS_END_LSB 1
#define DMA8_CS_ACTIVE_BITS 0:0
#define DMA8_CS_ACTIVE_SET 0x00000001
#define DMA8_CS_ACTIVE_CLR 0xfffffffe
#define DMA8_CS_ACTIVE_MSB 0
#define DMA8_CS_ACTIVE_LSB 0
#define DMA8_CONBLK_AD HW_REGISTER_RW( 0x7e007804 )
#define DMA8_CONBLK_AD_MASK 0xffffffe0
#define DMA8_CONBLK_AD_WIDTH 32
#define DMA8_CONBLK_AD_RESET 0000000000
#define DMA8_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA8_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA8_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA8_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA8_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA8_TI HW_REGISTER_RO( 0x7e007808 )
#define DMA8_TI_MASK 0x03fffff9
#define DMA8_TI_WIDTH 26
#define DMA8_TI_WAITS_BITS 25:21
#define DMA8_TI_WAITS_SET 0x03e00000
#define DMA8_TI_WAITS_CLR 0xfc1fffff
#define DMA8_TI_WAITS_MSB 25
#define DMA8_TI_WAITS_LSB 21
#define DMA8_TI_PERMAP_BITS 20:16
#define DMA8_TI_PERMAP_SET 0x001f0000
#define DMA8_TI_PERMAP_CLR 0xffe0ffff
#define DMA8_TI_PERMAP_MSB 20
#define DMA8_TI_PERMAP_LSB 16
#define DMA8_TI_BURST_LENGTH_BITS 15:12
#define DMA8_TI_BURST_LENGTH_SET 0x0000f000
#define DMA8_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA8_TI_BURST_LENGTH_MSB 15
#define DMA8_TI_BURST_LENGTH_LSB 12
#define DMA8_TI_SRC_IGNORE_BITS 11:11
#define DMA8_TI_SRC_IGNORE_SET 0x00000800
#define DMA8_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA8_TI_SRC_IGNORE_MSB 11
#define DMA8_TI_SRC_IGNORE_LSB 11
#define DMA8_TI_SRC_DREQ_BITS 10:10
#define DMA8_TI_SRC_DREQ_SET 0x00000400
#define DMA8_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA8_TI_SRC_DREQ_MSB 10
#define DMA8_TI_SRC_DREQ_LSB 10
#define DMA8_TI_SRC_WIDTH_BITS 9:9
#define DMA8_TI_SRC_WIDTH_SET 0x00000200
#define DMA8_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA8_TI_SRC_WIDTH_MSB 9
#define DMA8_TI_SRC_WIDTH_LSB 9
#define DMA8_TI_SRC_INC_BITS 8:8
#define DMA8_TI_SRC_INC_SET 0x00000100
#define DMA8_TI_SRC_INC_CLR 0xfffffeff
#define DMA8_TI_SRC_INC_MSB 8
#define DMA8_TI_SRC_INC_LSB 8
#define DMA8_TI_DEST_IGNORE_BITS 7:7
#define DMA8_TI_DEST_IGNORE_SET 0x00000080
#define DMA8_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA8_TI_DEST_IGNORE_MSB 7
#define DMA8_TI_DEST_IGNORE_LSB 7
#define DMA8_TI_DEST_DREQ_BITS 6:6
#define DMA8_TI_DEST_DREQ_SET 0x00000040
#define DMA8_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA8_TI_DEST_DREQ_MSB 6
#define DMA8_TI_DEST_DREQ_LSB 6
#define DMA8_TI_DEST_WIDTH_BITS 5:5
#define DMA8_TI_DEST_WIDTH_SET 0x00000020
#define DMA8_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA8_TI_DEST_WIDTH_MSB 5
#define DMA8_TI_DEST_WIDTH_LSB 5
#define DMA8_TI_DEST_INC_BITS 4:4
#define DMA8_TI_DEST_INC_SET 0x00000010
#define DMA8_TI_DEST_INC_CLR 0xffffffef
#define DMA8_TI_DEST_INC_MSB 4
#define DMA8_TI_DEST_INC_LSB 4
#define DMA8_TI_WAIT_RESP_BITS 3:3
#define DMA8_TI_WAIT_RESP_SET 0x00000008
#define DMA8_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA8_TI_WAIT_RESP_MSB 3
#define DMA8_TI_WAIT_RESP_LSB 3
#define DMA8_TI_INTEN_BITS 0:0
#define DMA8_TI_INTEN_SET 0x00000001
#define DMA8_TI_INTEN_CLR 0xfffffffe
#define DMA8_TI_INTEN_MSB 0
#define DMA8_TI_INTEN_LSB 0
#define DMA8_SOURCE_AD HW_REGISTER_RO( 0x7e00780c )
#define DMA8_SOURCE_AD_MASK 0xffffffff
#define DMA8_SOURCE_AD_WIDTH 32
#define DMA8_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA8_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA8_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA8_SOURCE_AD_S_ADDR_MSB 31
#define DMA8_SOURCE_AD_S_ADDR_LSB 0
#define DMA8_DEST_AD HW_REGISTER_RO( 0x7e007810 )
#define DMA8_DEST_AD_MASK 0xffffffff
#define DMA8_DEST_AD_WIDTH 32
#define DMA8_DEST_AD_D_ADDR_BITS 31:0
#define DMA8_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA8_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA8_DEST_AD_D_ADDR_MSB 31
#define DMA8_DEST_AD_D_ADDR_LSB 0
#define DMA8_TXFR_LEN HW_REGISTER_RO( 0x7e007814 )
#define DMA8_TXFR_LEN_MASK 0x0000ffff
#define DMA8_TXFR_LEN_WIDTH 16
#define DMA8_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA8_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA8_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA8_TXFR_LEN_XLENGTH_MSB 15
#define DMA8_TXFR_LEN_XLENGTH_LSB 0
#define DMA8_NEXTCONBK HW_REGISTER_RO( 0x7e00781c )
#define DMA8_NEXTCONBK_MASK 0xffffffe0
#define DMA8_NEXTCONBK_WIDTH 32
#define DMA8_NEXTCONBK_ADDR_BITS 31:5
#define DMA8_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA8_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA8_NEXTCONBK_ADDR_MSB 31
#define DMA8_NEXTCONBK_ADDR_LSB 5
#define DMA8_DEBUG HW_REGISTER_RW( 0x7e007820 )
#define DMA8_DEBUG_MASK 0x1ffffff7
#define DMA8_DEBUG_WIDTH 29
#define DMA8_DEBUG_RESET 0000000000
#define DMA8_DEBUG_LITE_BITS 28:28
#define DMA8_DEBUG_LITE_SET 0x10000000
#define DMA8_DEBUG_LITE_CLR 0xefffffff
#define DMA8_DEBUG_LITE_MSB 28
#define DMA8_DEBUG_LITE_LSB 28
#define DMA8_DEBUG_VERSION_BITS 27:25
#define DMA8_DEBUG_VERSION_SET 0x0e000000
#define DMA8_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA8_DEBUG_VERSION_MSB 27
#define DMA8_DEBUG_VERSION_LSB 25
#define DMA8_DEBUG_DMA_STATE_BITS 24:16
#define DMA8_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA8_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA8_DEBUG_DMA_STATE_MSB 24
#define DMA8_DEBUG_DMA_STATE_LSB 16
#define DMA8_DEBUG_DMA_ID_BITS 15:8
#define DMA8_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA8_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA8_DEBUG_DMA_ID_MSB 15
#define DMA8_DEBUG_DMA_ID_LSB 8
#define DMA8_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA8_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA8_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA8_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA8_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA8_DEBUG_READ_ERROR_BITS 2:2
#define DMA8_DEBUG_READ_ERROR_SET 0x00000004
#define DMA8_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA8_DEBUG_READ_ERROR_MSB 2
#define DMA8_DEBUG_READ_ERROR_LSB 2
#define DMA8_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA8_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA8_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA8_DEBUG_FIFO_ERROR_MSB 1
#define DMA8_DEBUG_FIFO_ERROR_LSB 1
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA8_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_lite9.h Executable file
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// This file was generated by the create_regs script
#define DMA9_BASE 0x7e007900
#define DMA9_CS HW_REGISTER_RW( 0x7e007900 )
#define DMA9_CS_MASK 0xf0ff017f
#define DMA9_CS_WIDTH 32
#define DMA9_CS_RESET 0000000000
#define DMA9_CS_RESET_BITS 31:31
#define DMA9_CS_RESET_SET 0x80000000
#define DMA9_CS_RESET_CLR 0x7fffffff
#define DMA9_CS_RESET_MSB 31
#define DMA9_CS_RESET_LSB 31
#define DMA9_CS_ABORT_BITS 30:30
#define DMA9_CS_ABORT_SET 0x40000000
#define DMA9_CS_ABORT_CLR 0xbfffffff
#define DMA9_CS_ABORT_MSB 30
#define DMA9_CS_ABORT_LSB 30
#define DMA9_CS_DISDEBUG_BITS 29:29
#define DMA9_CS_DISDEBUG_SET 0x20000000
#define DMA9_CS_DISDEBUG_CLR 0xdfffffff
#define DMA9_CS_DISDEBUG_MSB 29
#define DMA9_CS_DISDEBUG_LSB 29
#define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_BITS 28:28
#define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_SET 0x10000000
#define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_CLR 0xefffffff
#define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_MSB 28
#define DMA9_CS_WAIT_FOR_OUTSTANDING_WRITES_LSB 28
#define DMA9_CS_PANIC_PRIORITY_BITS 23:20
#define DMA9_CS_PANIC_PRIORITY_SET 0x00f00000
#define DMA9_CS_PANIC_PRIORITY_CLR 0xff0fffff
#define DMA9_CS_PANIC_PRIORITY_MSB 23
#define DMA9_CS_PANIC_PRIORITY_LSB 20
#define DMA9_CS_PRIORITY_BITS 19:16
#define DMA9_CS_PRIORITY_SET 0x000f0000
#define DMA9_CS_PRIORITY_CLR 0xfff0ffff
#define DMA9_CS_PRIORITY_MSB 19
#define DMA9_CS_PRIORITY_LSB 16
#define DMA9_CS_ERROR_BITS 8:8
#define DMA9_CS_ERROR_SET 0x00000100
#define DMA9_CS_ERROR_CLR 0xfffffeff
#define DMA9_CS_ERROR_MSB 8
#define DMA9_CS_ERROR_LSB 8
#define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_BITS 6:6
#define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_SET 0x00000040
#define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_CLR 0xffffffbf
#define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_MSB 6
#define DMA9_CS_WAITING_FOR_OUTSTANDING_WRITES_LSB 6
#define DMA9_CS_DREQ_STOPS_DMA_BITS 5:5
#define DMA9_CS_DREQ_STOPS_DMA_SET 0x00000020
#define DMA9_CS_DREQ_STOPS_DMA_CLR 0xffffffdf
#define DMA9_CS_DREQ_STOPS_DMA_MSB 5
#define DMA9_CS_DREQ_STOPS_DMA_LSB 5
#define DMA9_CS_PAUSED_BITS 4:4
#define DMA9_CS_PAUSED_SET 0x00000010
#define DMA9_CS_PAUSED_CLR 0xffffffef
#define DMA9_CS_PAUSED_MSB 4
#define DMA9_CS_PAUSED_LSB 4
#define DMA9_CS_DREQ_BITS 3:3
#define DMA9_CS_DREQ_SET 0x00000008
#define DMA9_CS_DREQ_CLR 0xfffffff7
#define DMA9_CS_DREQ_MSB 3
#define DMA9_CS_DREQ_LSB 3
#define DMA9_CS_INT_BITS 2:2
#define DMA9_CS_INT_SET 0x00000004
#define DMA9_CS_INT_CLR 0xfffffffb
#define DMA9_CS_INT_MSB 2
#define DMA9_CS_INT_LSB 2
#define DMA9_CS_END_BITS 1:1
#define DMA9_CS_END_SET 0x00000002
#define DMA9_CS_END_CLR 0xfffffffd
#define DMA9_CS_END_MSB 1
#define DMA9_CS_END_LSB 1
#define DMA9_CS_ACTIVE_BITS 0:0
#define DMA9_CS_ACTIVE_SET 0x00000001
#define DMA9_CS_ACTIVE_CLR 0xfffffffe
#define DMA9_CS_ACTIVE_MSB 0
#define DMA9_CS_ACTIVE_LSB 0
#define DMA9_CONBLK_AD HW_REGISTER_RW( 0x7e007904 )
#define DMA9_CONBLK_AD_MASK 0xffffffe0
#define DMA9_CONBLK_AD_WIDTH 32
#define DMA9_CONBLK_AD_RESET 0000000000
#define DMA9_CONBLK_AD_SCB_ADDR_BITS 31:5
#define DMA9_CONBLK_AD_SCB_ADDR_SET 0xffffffe0
#define DMA9_CONBLK_AD_SCB_ADDR_CLR 0x0000001f
#define DMA9_CONBLK_AD_SCB_ADDR_MSB 31
#define DMA9_CONBLK_AD_SCB_ADDR_LSB 5
#define DMA9_TI HW_REGISTER_RO( 0x7e007908 )
#define DMA9_TI_MASK 0x03fffff9
#define DMA9_TI_WIDTH 26
#define DMA9_TI_WAITS_BITS 25:21
#define DMA9_TI_WAITS_SET 0x03e00000
#define DMA9_TI_WAITS_CLR 0xfc1fffff
#define DMA9_TI_WAITS_MSB 25
#define DMA9_TI_WAITS_LSB 21
#define DMA9_TI_PERMAP_BITS 20:16
#define DMA9_TI_PERMAP_SET 0x001f0000
#define DMA9_TI_PERMAP_CLR 0xffe0ffff
#define DMA9_TI_PERMAP_MSB 20
#define DMA9_TI_PERMAP_LSB 16
#define DMA9_TI_BURST_LENGTH_BITS 15:12
#define DMA9_TI_BURST_LENGTH_SET 0x0000f000
#define DMA9_TI_BURST_LENGTH_CLR 0xffff0fff
#define DMA9_TI_BURST_LENGTH_MSB 15
#define DMA9_TI_BURST_LENGTH_LSB 12
#define DMA9_TI_SRC_IGNORE_BITS 11:11
#define DMA9_TI_SRC_IGNORE_SET 0x00000800
#define DMA9_TI_SRC_IGNORE_CLR 0xfffff7ff
#define DMA9_TI_SRC_IGNORE_MSB 11
#define DMA9_TI_SRC_IGNORE_LSB 11
#define DMA9_TI_SRC_DREQ_BITS 10:10
#define DMA9_TI_SRC_DREQ_SET 0x00000400
#define DMA9_TI_SRC_DREQ_CLR 0xfffffbff
#define DMA9_TI_SRC_DREQ_MSB 10
#define DMA9_TI_SRC_DREQ_LSB 10
#define DMA9_TI_SRC_WIDTH_BITS 9:9
#define DMA9_TI_SRC_WIDTH_SET 0x00000200
#define DMA9_TI_SRC_WIDTH_CLR 0xfffffdff
#define DMA9_TI_SRC_WIDTH_MSB 9
#define DMA9_TI_SRC_WIDTH_LSB 9
#define DMA9_TI_SRC_INC_BITS 8:8
#define DMA9_TI_SRC_INC_SET 0x00000100
#define DMA9_TI_SRC_INC_CLR 0xfffffeff
#define DMA9_TI_SRC_INC_MSB 8
#define DMA9_TI_SRC_INC_LSB 8
#define DMA9_TI_DEST_IGNORE_BITS 7:7
#define DMA9_TI_DEST_IGNORE_SET 0x00000080
#define DMA9_TI_DEST_IGNORE_CLR 0xffffff7f
#define DMA9_TI_DEST_IGNORE_MSB 7
#define DMA9_TI_DEST_IGNORE_LSB 7
#define DMA9_TI_DEST_DREQ_BITS 6:6
#define DMA9_TI_DEST_DREQ_SET 0x00000040
#define DMA9_TI_DEST_DREQ_CLR 0xffffffbf
#define DMA9_TI_DEST_DREQ_MSB 6
#define DMA9_TI_DEST_DREQ_LSB 6
#define DMA9_TI_DEST_WIDTH_BITS 5:5
#define DMA9_TI_DEST_WIDTH_SET 0x00000020
#define DMA9_TI_DEST_WIDTH_CLR 0xffffffdf
#define DMA9_TI_DEST_WIDTH_MSB 5
#define DMA9_TI_DEST_WIDTH_LSB 5
#define DMA9_TI_DEST_INC_BITS 4:4
#define DMA9_TI_DEST_INC_SET 0x00000010
#define DMA9_TI_DEST_INC_CLR 0xffffffef
#define DMA9_TI_DEST_INC_MSB 4
#define DMA9_TI_DEST_INC_LSB 4
#define DMA9_TI_WAIT_RESP_BITS 3:3
#define DMA9_TI_WAIT_RESP_SET 0x00000008
#define DMA9_TI_WAIT_RESP_CLR 0xfffffff7
#define DMA9_TI_WAIT_RESP_MSB 3
#define DMA9_TI_WAIT_RESP_LSB 3
#define DMA9_TI_INTEN_BITS 0:0
#define DMA9_TI_INTEN_SET 0x00000001
#define DMA9_TI_INTEN_CLR 0xfffffffe
#define DMA9_TI_INTEN_MSB 0
#define DMA9_TI_INTEN_LSB 0
#define DMA9_SOURCE_AD HW_REGISTER_RO( 0x7e00790c )
#define DMA9_SOURCE_AD_MASK 0xffffffff
#define DMA9_SOURCE_AD_WIDTH 32
#define DMA9_SOURCE_AD_S_ADDR_BITS 31:0
#define DMA9_SOURCE_AD_S_ADDR_SET 0xffffffff
#define DMA9_SOURCE_AD_S_ADDR_CLR 0x00000000
#define DMA9_SOURCE_AD_S_ADDR_MSB 31
#define DMA9_SOURCE_AD_S_ADDR_LSB 0
#define DMA9_DEST_AD HW_REGISTER_RO( 0x7e007910 )
#define DMA9_DEST_AD_MASK 0xffffffff
#define DMA9_DEST_AD_WIDTH 32
#define DMA9_DEST_AD_D_ADDR_BITS 31:0
#define DMA9_DEST_AD_D_ADDR_SET 0xffffffff
#define DMA9_DEST_AD_D_ADDR_CLR 0x00000000
#define DMA9_DEST_AD_D_ADDR_MSB 31
#define DMA9_DEST_AD_D_ADDR_LSB 0
#define DMA9_TXFR_LEN HW_REGISTER_RO( 0x7e007914 )
#define DMA9_TXFR_LEN_MASK 0x0000ffff
#define DMA9_TXFR_LEN_WIDTH 16
#define DMA9_TXFR_LEN_XLENGTH_BITS 15:0
#define DMA9_TXFR_LEN_XLENGTH_SET 0x0000ffff
#define DMA9_TXFR_LEN_XLENGTH_CLR 0xffff0000
#define DMA9_TXFR_LEN_XLENGTH_MSB 15
#define DMA9_TXFR_LEN_XLENGTH_LSB 0
#define DMA9_NEXTCONBK HW_REGISTER_RO( 0x7e00791c )
#define DMA9_NEXTCONBK_MASK 0xffffffe0
#define DMA9_NEXTCONBK_WIDTH 32
#define DMA9_NEXTCONBK_ADDR_BITS 31:5
#define DMA9_NEXTCONBK_ADDR_SET 0xffffffe0
#define DMA9_NEXTCONBK_ADDR_CLR 0x0000001f
#define DMA9_NEXTCONBK_ADDR_MSB 31
#define DMA9_NEXTCONBK_ADDR_LSB 5
#define DMA9_DEBUG HW_REGISTER_RW( 0x7e007920 )
#define DMA9_DEBUG_MASK 0x1ffffff7
#define DMA9_DEBUG_WIDTH 29
#define DMA9_DEBUG_RESET 0000000000
#define DMA9_DEBUG_LITE_BITS 28:28
#define DMA9_DEBUG_LITE_SET 0x10000000
#define DMA9_DEBUG_LITE_CLR 0xefffffff
#define DMA9_DEBUG_LITE_MSB 28
#define DMA9_DEBUG_LITE_LSB 28
#define DMA9_DEBUG_VERSION_BITS 27:25
#define DMA9_DEBUG_VERSION_SET 0x0e000000
#define DMA9_DEBUG_VERSION_CLR 0xf1ffffff
#define DMA9_DEBUG_VERSION_MSB 27
#define DMA9_DEBUG_VERSION_LSB 25
#define DMA9_DEBUG_DMA_STATE_BITS 24:16
#define DMA9_DEBUG_DMA_STATE_SET 0x01ff0000
#define DMA9_DEBUG_DMA_STATE_CLR 0xfe00ffff
#define DMA9_DEBUG_DMA_STATE_MSB 24
#define DMA9_DEBUG_DMA_STATE_LSB 16
#define DMA9_DEBUG_DMA_ID_BITS 15:8
#define DMA9_DEBUG_DMA_ID_SET 0x0000ff00
#define DMA9_DEBUG_DMA_ID_CLR 0xffff00ff
#define DMA9_DEBUG_DMA_ID_MSB 15
#define DMA9_DEBUG_DMA_ID_LSB 8
#define DMA9_DEBUG_OUTSTANDING_WRITES_BITS 7:4
#define DMA9_DEBUG_OUTSTANDING_WRITES_SET 0x000000f0
#define DMA9_DEBUG_OUTSTANDING_WRITES_CLR 0xffffff0f
#define DMA9_DEBUG_OUTSTANDING_WRITES_MSB 7
#define DMA9_DEBUG_OUTSTANDING_WRITES_LSB 4
#define DMA9_DEBUG_READ_ERROR_BITS 2:2
#define DMA9_DEBUG_READ_ERROR_SET 0x00000004
#define DMA9_DEBUG_READ_ERROR_CLR 0xfffffffb
#define DMA9_DEBUG_READ_ERROR_MSB 2
#define DMA9_DEBUG_READ_ERROR_LSB 2
#define DMA9_DEBUG_FIFO_ERROR_BITS 1:1
#define DMA9_DEBUG_FIFO_ERROR_SET 0x00000002
#define DMA9_DEBUG_FIFO_ERROR_CLR 0xfffffffd
#define DMA9_DEBUG_FIFO_ERROR_MSB 1
#define DMA9_DEBUG_FIFO_ERROR_LSB 1
#define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_BITS 0:0
#define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_SET 0x00000001
#define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_CLR 0xfffffffe
#define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_MSB 0
#define DMA9_DEBUG_READ_LAST_NOT_SET_ERROR_LSB 0

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bcm2708_chip/axi_dma_top.h Executable file
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// This file was generated by the create_regs script
#define DMA_BASE 0x7e007fe0
#define DMA_INT_STATUS HW_REGISTER_RO( 0x7e007fe0 )
#define DMA_INT_STATUS_MASK 0x0000ffff
#define DMA_INT_STATUS_WIDTH 16
#define DMA_INT_STATUS_RESET 0000000000
#define DMA_INT_STATUS_INT0_BITS 0:0
#define DMA_INT_STATUS_INT0_SET 0x00000001
#define DMA_INT_STATUS_INT0_CLR 0xfffffffe
#define DMA_INT_STATUS_INT0_MSB 0
#define DMA_INT_STATUS_INT0_LSB 0
#define DMA_INT_STATUS_INT1_BITS 1:1
#define DMA_INT_STATUS_INT1_SET 0x00000002
#define DMA_INT_STATUS_INT1_CLR 0xfffffffd
#define DMA_INT_STATUS_INT1_MSB 1
#define DMA_INT_STATUS_INT1_LSB 1
#define DMA_INT_STATUS_INT2_BITS 2:2
#define DMA_INT_STATUS_INT2_SET 0x00000004
#define DMA_INT_STATUS_INT2_CLR 0xfffffffb
#define DMA_INT_STATUS_INT2_MSB 2
#define DMA_INT_STATUS_INT2_LSB 2
#define DMA_INT_STATUS_INT3_BITS 3:3
#define DMA_INT_STATUS_INT3_SET 0x00000008
#define DMA_INT_STATUS_INT3_CLR 0xfffffff7
#define DMA_INT_STATUS_INT3_MSB 3
#define DMA_INT_STATUS_INT3_LSB 3
#define DMA_INT_STATUS_INT4_BITS 4:4
#define DMA_INT_STATUS_INT4_SET 0x00000010
#define DMA_INT_STATUS_INT4_CLR 0xffffffef
#define DMA_INT_STATUS_INT4_MSB 4
#define DMA_INT_STATUS_INT4_LSB 4
#define DMA_INT_STATUS_INT5_BITS 5:5
#define DMA_INT_STATUS_INT5_SET 0x00000020
#define DMA_INT_STATUS_INT5_CLR 0xffffffdf
#define DMA_INT_STATUS_INT5_MSB 5
#define DMA_INT_STATUS_INT5_LSB 5
#define DMA_INT_STATUS_INT6_BITS 6:6
#define DMA_INT_STATUS_INT6_SET 0x00000040
#define DMA_INT_STATUS_INT6_CLR 0xffffffbf
#define DMA_INT_STATUS_INT6_MSB 6
#define DMA_INT_STATUS_INT6_LSB 6
#define DMA_INT_STATUS_INT7_BITS 7:7
#define DMA_INT_STATUS_INT7_SET 0x00000080
#define DMA_INT_STATUS_INT7_CLR 0xffffff7f
#define DMA_INT_STATUS_INT7_MSB 7
#define DMA_INT_STATUS_INT7_LSB 7
#define DMA_INT_STATUS_INT8_BITS 8:8
#define DMA_INT_STATUS_INT8_SET 0x00000100
#define DMA_INT_STATUS_INT8_CLR 0xfffffeff
#define DMA_INT_STATUS_INT8_MSB 8
#define DMA_INT_STATUS_INT8_LSB 8
#define DMA_INT_STATUS_INT9_BITS 9:9
#define DMA_INT_STATUS_INT9_SET 0x00000200
#define DMA_INT_STATUS_INT9_CLR 0xfffffdff
#define DMA_INT_STATUS_INT9_MSB 9
#define DMA_INT_STATUS_INT9_LSB 9
#define DMA_INT_STATUS_INT10_BITS 10:10
#define DMA_INT_STATUS_INT10_SET 0x00000400
#define DMA_INT_STATUS_INT10_CLR 0xfffffbff
#define DMA_INT_STATUS_INT10_MSB 10
#define DMA_INT_STATUS_INT10_LSB 10
#define DMA_INT_STATUS_INT11_BITS 11:11
#define DMA_INT_STATUS_INT11_SET 0x00000800
#define DMA_INT_STATUS_INT11_CLR 0xfffff7ff
#define DMA_INT_STATUS_INT11_MSB 11
#define DMA_INT_STATUS_INT11_LSB 11
#define DMA_INT_STATUS_INT12_BITS 12:12
#define DMA_INT_STATUS_INT12_SET 0x00001000
#define DMA_INT_STATUS_INT12_CLR 0xffffefff
#define DMA_INT_STATUS_INT12_MSB 12
#define DMA_INT_STATUS_INT12_LSB 12
#define DMA_INT_STATUS_INT13_BITS 13:13
#define DMA_INT_STATUS_INT13_SET 0x00002000
#define DMA_INT_STATUS_INT13_CLR 0xffffdfff
#define DMA_INT_STATUS_INT13_MSB 13
#define DMA_INT_STATUS_INT13_LSB 13
#define DMA_INT_STATUS_INT14_BITS 14:14
#define DMA_INT_STATUS_INT14_SET 0x00004000
#define DMA_INT_STATUS_INT14_CLR 0xffffbfff
#define DMA_INT_STATUS_INT14_MSB 14
#define DMA_INT_STATUS_INT14_LSB 14
#define DMA_INT_STATUS_INT15_BITS 15:15
#define DMA_INT_STATUS_INT15_SET 0x00008000
#define DMA_INT_STATUS_INT15_CLR 0xffff7fff
#define DMA_INT_STATUS_INT15_MSB 15
#define DMA_INT_STATUS_INT15_LSB 15
#define DMA_ENABLE HW_REGISTER_RW( 0x7e007ff0 )
#define DMA_ENABLE_MASK 0x00007fff
#define DMA_ENABLE_WIDTH 15
#define DMA_ENABLE_RESET 0x00007fff
#define DMA_ENABLE_EN0_BITS 0:0
#define DMA_ENABLE_EN0_SET 0x00000001
#define DMA_ENABLE_EN0_CLR 0xfffffffe
#define DMA_ENABLE_EN0_MSB 0
#define DMA_ENABLE_EN0_LSB 0
#define DMA_ENABLE_EN1_BITS 1:1
#define DMA_ENABLE_EN1_SET 0x00000002
#define DMA_ENABLE_EN1_CLR 0xfffffffd
#define DMA_ENABLE_EN1_MSB 1
#define DMA_ENABLE_EN1_LSB 1
#define DMA_ENABLE_EN2_BITS 2:2
#define DMA_ENABLE_EN2_SET 0x00000004
#define DMA_ENABLE_EN2_CLR 0xfffffffb
#define DMA_ENABLE_EN2_MSB 2
#define DMA_ENABLE_EN2_LSB 2
#define DMA_ENABLE_EN3_BITS 3:3
#define DMA_ENABLE_EN3_SET 0x00000008
#define DMA_ENABLE_EN3_CLR 0xfffffff7
#define DMA_ENABLE_EN3_MSB 3
#define DMA_ENABLE_EN3_LSB 3
#define DMA_ENABLE_EN4_BITS 4:4
#define DMA_ENABLE_EN4_SET 0x00000010
#define DMA_ENABLE_EN4_CLR 0xffffffef
#define DMA_ENABLE_EN4_MSB 4
#define DMA_ENABLE_EN4_LSB 4
#define DMA_ENABLE_EN5_BITS 5:5
#define DMA_ENABLE_EN5_SET 0x00000020
#define DMA_ENABLE_EN5_CLR 0xffffffdf
#define DMA_ENABLE_EN5_MSB 5
#define DMA_ENABLE_EN5_LSB 5
#define DMA_ENABLE_EN6_BITS 6:6
#define DMA_ENABLE_EN6_SET 0x00000040
#define DMA_ENABLE_EN6_CLR 0xffffffbf
#define DMA_ENABLE_EN6_MSB 6
#define DMA_ENABLE_EN6_LSB 6
#define DMA_ENABLE_EN7_BITS 7:7
#define DMA_ENABLE_EN7_SET 0x00000080
#define DMA_ENABLE_EN7_CLR 0xffffff7f
#define DMA_ENABLE_EN7_MSB 7
#define DMA_ENABLE_EN7_LSB 7
#define DMA_ENABLE_EN8_BITS 8:8
#define DMA_ENABLE_EN8_SET 0x00000100
#define DMA_ENABLE_EN8_CLR 0xfffffeff
#define DMA_ENABLE_EN8_MSB 8
#define DMA_ENABLE_EN8_LSB 8
#define DMA_ENABLE_EN9_BITS 9:9
#define DMA_ENABLE_EN9_SET 0x00000200
#define DMA_ENABLE_EN9_CLR 0xfffffdff
#define DMA_ENABLE_EN9_MSB 9
#define DMA_ENABLE_EN9_LSB 9
#define DMA_ENABLE_EN10_BITS 10:10
#define DMA_ENABLE_EN10_SET 0x00000400
#define DMA_ENABLE_EN10_CLR 0xfffffbff
#define DMA_ENABLE_EN10_MSB 10
#define DMA_ENABLE_EN10_LSB 10
#define DMA_ENABLE_EN11_BITS 11:11
#define DMA_ENABLE_EN11_SET 0x00000800
#define DMA_ENABLE_EN11_CLR 0xfffff7ff
#define DMA_ENABLE_EN11_MSB 11
#define DMA_ENABLE_EN11_LSB 11
#define DMA_ENABLE_EN12_BITS 12:12
#define DMA_ENABLE_EN12_SET 0x00001000
#define DMA_ENABLE_EN12_CLR 0xffffefff
#define DMA_ENABLE_EN12_MSB 12
#define DMA_ENABLE_EN12_LSB 12
#define DMA_ENABLE_EN13_BITS 13:13
#define DMA_ENABLE_EN13_SET 0x00002000
#define DMA_ENABLE_EN13_CLR 0xffffdfff
#define DMA_ENABLE_EN13_MSB 13
#define DMA_ENABLE_EN13_LSB 13
#define DMA_ENABLE_EN14_BITS 14:14
#define DMA_ENABLE_EN14_SET 0x00004000
#define DMA_ENABLE_EN14_CLR 0xffffbfff
#define DMA_ENABLE_EN14_MSB 14
#define DMA_ENABLE_EN14_LSB 14

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bcm2708_chip/axi_performance0.h Executable file
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// This file was generated by the create_regs script
#define APERF0_BASE 0x7e009800
#define APERF0_APB_ID 0x41584950
#define APERF0_GEN_CTRL HW_REGISTER_RW( 0x7e009800 )
#define APERF0_GEN_CTRL_MASK 0x00000003
#define APERF0_GEN_CTRL_WIDTH 2
#define APERF0_GEN_CTRL_RESET 0000000000
#define APERF0_GEN_CTRL_ENABLE_BITS 0:0
#define APERF0_GEN_CTRL_ENABLE_SET 0x00000001
#define APERF0_GEN_CTRL_ENABLE_CLR 0xfffffffe
#define APERF0_GEN_CTRL_ENABLE_MSB 0
#define APERF0_GEN_CTRL_ENABLE_LSB 0
#define APERF0_GEN_CTRL_ENABLE_RESET 0x0
#define APERF0_GEN_CTRL_RESET_BITS 1:1
#define APERF0_GEN_CTRL_RESET_SET 0x00000002
#define APERF0_GEN_CTRL_RESET_CLR 0xfffffffd
#define APERF0_GEN_CTRL_RESET_MSB 1
#define APERF0_GEN_CTRL_RESET_LSB 1
#define APERF0_GEN_CTRL_RESET_RESET 0x0
#define APERF0_BW0_CTRL HW_REGISTER_RW( 0x7e009840 )
#define APERF0_BW0_CTRL_MASK 0xf0001f1f
#define APERF0_BW0_CTRL_WIDTH 32
#define APERF0_BW0_CTRL_RESET 0000000000
#define APERF0_BW0_CTRL_BUS_BITS 4:0
#define APERF0_BW0_CTRL_BUS_SET 0x0000001f
#define APERF0_BW0_CTRL_BUS_CLR 0xffffffe0
#define APERF0_BW0_CTRL_BUS_MSB 4
#define APERF0_BW0_CTRL_BUS_LSB 0
#define APERF0_BW0_CTRL_BUS_RESET 0x0
#define APERF0_BW0_CTRL_ID_BITS 12:8
#define APERF0_BW0_CTRL_ID_SET 0x00001f00
#define APERF0_BW0_CTRL_ID_CLR 0xffffe0ff
#define APERF0_BW0_CTRL_ID_MSB 12
#define APERF0_BW0_CTRL_ID_LSB 8
#define APERF0_BW0_CTRL_ID_RESET 0x0
#define APERF0_BW0_CTRL_LATHALT_BITS 28:28
#define APERF0_BW0_CTRL_LATHALT_SET 0x10000000
#define APERF0_BW0_CTRL_LATHALT_CLR 0xefffffff
#define APERF0_BW0_CTRL_LATHALT_MSB 28
#define APERF0_BW0_CTRL_LATHALT_LSB 28
#define APERF0_BW0_CTRL_LATHALT_RESET 0x0
#define APERF0_BW0_CTRL_ID_EN_BITS 29:29
#define APERF0_BW0_CTRL_ID_EN_SET 0x20000000
#define APERF0_BW0_CTRL_ID_EN_CLR 0xdfffffff
#define APERF0_BW0_CTRL_ID_EN_MSB 29
#define APERF0_BW0_CTRL_ID_EN_LSB 29
#define APERF0_BW0_CTRL_ID_EN_RESET 0x0
#define APERF0_BW0_CTRL_EN_BITS 30:30
#define APERF0_BW0_CTRL_EN_SET 0x40000000
#define APERF0_BW0_CTRL_EN_CLR 0xbfffffff
#define APERF0_BW0_CTRL_EN_MSB 30
#define APERF0_BW0_CTRL_EN_LSB 30
#define APERF0_BW0_CTRL_EN_RESET 0x0
#define APERF0_BW0_CTRL_RESET_BITS 31:31
#define APERF0_BW0_CTRL_RESET_SET 0x80000000
#define APERF0_BW0_CTRL_RESET_CLR 0x7fffffff
#define APERF0_BW0_CTRL_RESET_MSB 31
#define APERF0_BW0_CTRL_RESET_LSB 31
#define APERF0_BW0_CTRL_RESET_RESET 0x0
#define APERF0_BW0_ATRANS HW_REGISTER_RO( 0x7e009844 )
#define APERF0_BW0_ATRANS_MASK 0xffffffff
#define APERF0_BW0_ATRANS_WIDTH 32
#define APERF0_BW0_ATRANS_RESET 0000000000
#define APERF0_BW0_ATWAIT HW_REGISTER_RO( 0x7e009848 )
#define APERF0_BW0_ATWAIT_MASK 0xffffffff
#define APERF0_BW0_ATWAIT_WIDTH 32
#define APERF0_BW0_ATWAIT_RESET 0000000000
#define APERF0_BW0_AMAX HW_REGISTER_RO( 0x7e00984c )
#define APERF0_BW0_AMAX_MASK 0x00ffffff
#define APERF0_BW0_AMAX_WIDTH 24
#define APERF0_BW0_AMAX_RESET 0000000000
#define APERF0_BW0_WTRANS HW_REGISTER_RO( 0x7e009850 )
#define APERF0_BW0_WTRANS_MASK 0xffffffff
#define APERF0_BW0_WTRANS_WIDTH 32
#define APERF0_BW0_WTRANS_RESET 0000000000
#define APERF0_BW0_WTWAIT HW_REGISTER_RO( 0x7e009854 )
#define APERF0_BW0_WTWAIT_MASK 0xffffffff
#define APERF0_BW0_WTWAIT_WIDTH 32
#define APERF0_BW0_WTWAIT_RESET 0000000000
#define APERF0_BW0_WMAX HW_REGISTER_RO( 0x7e009858 )
#define APERF0_BW0_WMAX_MASK 0x00ffffff
#define APERF0_BW0_WMAX_WIDTH 24
#define APERF0_BW0_WMAX_RESET 0000000000
#define APERF0_BW0_RTRANS HW_REGISTER_RO( 0x7e00985c )
#define APERF0_BW0_RTRANS_MASK 0xffffffff
#define APERF0_BW0_RTRANS_WIDTH 32
#define APERF0_BW0_RTRANS_RESET 0000000000
#define APERF0_BW0_RTWAIT HW_REGISTER_RO( 0x7e009860 )
#define APERF0_BW0_RTWAIT_MASK 0xffffffff
#define APERF0_BW0_RTWAIT_WIDTH 32
#define APERF0_BW0_RTWAIT_RESET 0000000000
#define APERF0_BW0_RMAX HW_REGISTER_RO( 0x7e009864 )
#define APERF0_BW0_RMAX_MASK 0x00ffffff
#define APERF0_BW0_RMAX_WIDTH 24
#define APERF0_BW0_RMAX_RESET 0000000000
#define APERF0_BW0_RPEND HW_REGISTER_RO( 0x7e009868 )
#define APERF0_BW0_RPEND_MASK 0x000000ff
#define APERF0_BW0_RPEND_WIDTH 8
#define APERF0_BW0_RPEND_RESET 0000000000
#define APERF0_BW1_CTRL HW_REGISTER_RW( 0x7e009880 )
#define APERF0_BW1_CTRL_MASK 0xf0001f1f
#define APERF0_BW1_CTRL_WIDTH 32
#define APERF0_BW1_CTRL_RESET 0000000000
#define APERF0_BW1_CTRL_BUS_BITS 4:0
#define APERF0_BW1_CTRL_BUS_SET 0x0000001f
#define APERF0_BW1_CTRL_BUS_CLR 0xffffffe0
#define APERF0_BW1_CTRL_BUS_MSB 4
#define APERF0_BW1_CTRL_BUS_LSB 0
#define APERF0_BW1_CTRL_BUS_RESET 0x0
#define APERF0_BW1_CTRL_ID_BITS 12:8
#define APERF0_BW1_CTRL_ID_SET 0x00001f00
#define APERF0_BW1_CTRL_ID_CLR 0xffffe0ff
#define APERF0_BW1_CTRL_ID_MSB 12
#define APERF0_BW1_CTRL_ID_LSB 8
#define APERF0_BW1_CTRL_ID_RESET 0x0
#define APERF0_BW1_CTRL_LATHALT_BITS 28:28
#define APERF0_BW1_CTRL_LATHALT_SET 0x10000000
#define APERF0_BW1_CTRL_LATHALT_CLR 0xefffffff
#define APERF0_BW1_CTRL_LATHALT_MSB 28
#define APERF0_BW1_CTRL_LATHALT_LSB 28
#define APERF0_BW1_CTRL_LATHALT_RESET 0x0
#define APERF0_BW1_CTRL_ID_EN_BITS 29:29
#define APERF0_BW1_CTRL_ID_EN_SET 0x20000000
#define APERF0_BW1_CTRL_ID_EN_CLR 0xdfffffff
#define APERF0_BW1_CTRL_ID_EN_MSB 29
#define APERF0_BW1_CTRL_ID_EN_LSB 29
#define APERF0_BW1_CTRL_ID_EN_RESET 0x0
#define APERF0_BW1_CTRL_EN_BITS 30:30
#define APERF0_BW1_CTRL_EN_SET 0x40000000
#define APERF0_BW1_CTRL_EN_CLR 0xbfffffff
#define APERF0_BW1_CTRL_EN_MSB 30
#define APERF0_BW1_CTRL_EN_LSB 30
#define APERF0_BW1_CTRL_EN_RESET 0x0
#define APERF0_BW1_CTRL_RESET_BITS 31:31
#define APERF0_BW1_CTRL_RESET_SET 0x80000000
#define APERF0_BW1_CTRL_RESET_CLR 0x7fffffff
#define APERF0_BW1_CTRL_RESET_MSB 31
#define APERF0_BW1_CTRL_RESET_LSB 31
#define APERF0_BW1_CTRL_RESET_RESET 0x0
#define APERF0_BW1_ATRANS HW_REGISTER_RO( 0x7e009884 )
#define APERF0_BW1_ATRANS_MASK 0xffffffff
#define APERF0_BW1_ATRANS_WIDTH 32
#define APERF0_BW1_ATRANS_RESET 0000000000
#define APERF0_BW1_ATWAIT HW_REGISTER_RO( 0x7e009888 )
#define APERF0_BW1_ATWAIT_MASK 0xffffffff
#define APERF0_BW1_ATWAIT_WIDTH 32
#define APERF0_BW1_ATWAIT_RESET 0000000000
#define APERF0_BW1_AMAX HW_REGISTER_RO( 0x7e00988c )
#define APERF0_BW1_AMAX_MASK 0x00ffffff
#define APERF0_BW1_AMAX_WIDTH 24
#define APERF0_BW1_AMAX_RESET 0000000000
#define APERF0_BW1_WTRANS HW_REGISTER_RO( 0x7e009890 )
#define APERF0_BW1_WTRANS_MASK 0xffffffff
#define APERF0_BW1_WTRANS_WIDTH 32
#define APERF0_BW1_WTRANS_RESET 0000000000
#define APERF0_BW1_WTWAIT HW_REGISTER_RO( 0x7e009894 )
#define APERF0_BW1_WTWAIT_MASK 0xffffffff
#define APERF0_BW1_WTWAIT_WIDTH 32
#define APERF0_BW1_WTWAIT_RESET 0000000000
#define APERF0_BW1_WMAX HW_REGISTER_RO( 0x7e009898 )
#define APERF0_BW1_WMAX_MASK 0x0000ffff
#define APERF0_BW1_WMAX_WIDTH 16
#define APERF0_BW1_WMAX_RESET 0000000000
#define APERF0_BW1_RTRANS HW_REGISTER_RO( 0x7e00989c )
#define APERF0_BW1_RTRANS_MASK 0xffffffff
#define APERF0_BW1_RTRANS_WIDTH 32
#define APERF0_BW1_RTRANS_RESET 0000000000
#define APERF0_BW1_RTWAIT HW_REGISTER_RO( 0x7e0098a0 )
#define APERF0_BW1_RTWAIT_MASK 0xffffffff
#define APERF0_BW1_RTWAIT_WIDTH 32
#define APERF0_BW1_RTWAIT_RESET 0000000000
#define APERF0_BW1_RMAX HW_REGISTER_RO( 0x7e0098a4 )
#define APERF0_BW1_RMAX_MASK 0x00ffffff
#define APERF0_BW1_RMAX_WIDTH 24
#define APERF0_BW1_RMAX_RESET 0000000000
#define APERF0_BW1_RPEND HW_REGISTER_RO( 0x7e009868 )
#define APERF0_BW1_RPEND_MASK 0x000000ff
#define APERF0_BW1_RPEND_WIDTH 8
#define APERF0_BW1_RPEND_RESET 0000000000
#define APERF0_BW2_CTRL HW_REGISTER_RW( 0x7e0098c0 )
#define APERF0_BW2_CTRL_MASK 0xf0001f1f
#define APERF0_BW2_CTRL_WIDTH 32
#define APERF0_BW2_CTRL_RESET 0000000000
#define APERF0_BW2_CTRL_BUS_BITS 4:0
#define APERF0_BW2_CTRL_BUS_SET 0x0000001f
#define APERF0_BW2_CTRL_BUS_CLR 0xffffffe0
#define APERF0_BW2_CTRL_BUS_MSB 4
#define APERF0_BW2_CTRL_BUS_LSB 0
#define APERF0_BW2_CTRL_BUS_RESET 0x0
#define APERF0_BW2_CTRL_ID_BITS 12:8
#define APERF0_BW2_CTRL_ID_SET 0x00001f00
#define APERF0_BW2_CTRL_ID_CLR 0xffffe0ff
#define APERF0_BW2_CTRL_ID_MSB 12
#define APERF0_BW2_CTRL_ID_LSB 8
#define APERF0_BW2_CTRL_ID_RESET 0x0
#define APERF0_BW2_CTRL_LATHALT_BITS 28:28
#define APERF0_BW2_CTRL_LATHALT_SET 0x10000000
#define APERF0_BW2_CTRL_LATHALT_CLR 0xefffffff
#define APERF0_BW2_CTRL_LATHALT_MSB 28
#define APERF0_BW2_CTRL_LATHALT_LSB 28
#define APERF0_BW2_CTRL_LATHALT_RESET 0x0
#define APERF0_BW2_CTRL_ID_EN_BITS 29:29
#define APERF0_BW2_CTRL_ID_EN_SET 0x20000000
#define APERF0_BW2_CTRL_ID_EN_CLR 0xdfffffff
#define APERF0_BW2_CTRL_ID_EN_MSB 29
#define APERF0_BW2_CTRL_ID_EN_LSB 29
#define APERF0_BW2_CTRL_ID_EN_RESET 0x0
#define APERF0_BW2_CTRL_EN_BITS 30:30
#define APERF0_BW2_CTRL_EN_SET 0x40000000
#define APERF0_BW2_CTRL_EN_CLR 0xbfffffff
#define APERF0_BW2_CTRL_EN_MSB 30
#define APERF0_BW2_CTRL_EN_LSB 30
#define APERF0_BW2_CTRL_EN_RESET 0x0
#define APERF0_BW2_CTRL_RESET_BITS 31:31
#define APERF0_BW2_CTRL_RESET_SET 0x80000000
#define APERF0_BW2_CTRL_RESET_CLR 0x7fffffff
#define APERF0_BW2_CTRL_RESET_MSB 31
#define APERF0_BW2_CTRL_RESET_LSB 31
#define APERF0_BW2_CTRL_RESET_RESET 0x0
#define APERF0_BW2_ATRANS HW_REGISTER_RO( 0x7e0098c4 )
#define APERF0_BW2_ATRANS_MASK 0xffffffff
#define APERF0_BW2_ATRANS_WIDTH 32
#define APERF0_BW2_ATRANS_RESET 0000000000
#define APERF0_BW2_ATWAIT HW_REGISTER_RO( 0x7e0098c8 )
#define APERF0_BW2_ATWAIT_MASK 0xffffffff
#define APERF0_BW2_ATWAIT_WIDTH 32
#define APERF0_BW2_ATWAIT_RESET 0000000000
#define APERF0_BW2_AMAX HW_REGISTER_RO( 0x7e0098cc )
#define APERF0_BW2_AMAX_MASK 0x00ffffff
#define APERF0_BW2_AMAX_WIDTH 24
#define APERF0_BW2_AMAX_RESET 0000000000
#define APERF0_BW2_WTRANS HW_REGISTER_RO( 0x7e0098d0 )
#define APERF0_BW2_WTRANS_MASK 0xffffffff
#define APERF0_BW2_WTRANS_WIDTH 32
#define APERF0_BW2_WTRANS_RESET 0000000000
#define APERF0_BW2_WTWAIT HW_REGISTER_RO( 0x7e0098d4 )
#define APERF0_BW2_WTWAIT_MASK 0xffffffff
#define APERF0_BW2_WTWAIT_WIDTH 32
#define APERF0_BW2_WTWAIT_RESET 0000000000
#define APERF0_BW2_WMAX HW_REGISTER_RO( 0x7e0098d8 )
#define APERF0_BW2_WMAX_MASK 0x0ff0ffff
#define APERF0_BW2_WMAX_WIDTH 28
#define APERF0_BW2_WMAX_RESET 0000000000
#define APERF0_BW2_RTRANS HW_REGISTER_RO( 0x7e0098dc )
#define APERF0_BW2_RTRANS_MASK 0xffffffff
#define APERF0_BW2_RTRANS_WIDTH 32
#define APERF0_BW2_RTRANS_RESET 0000000000
#define APERF0_BW2_RTWAIT HW_REGISTER_RO( 0x7e0098e0 )
#define APERF0_BW2_RTWAIT_MASK 0xffffffff
#define APERF0_BW2_RTWAIT_WIDTH 32
#define APERF0_BW2_RTWAIT_RESET 0000000000
#define APERF0_BW2_RMAX HW_REGISTER_RO( 0x7e0098e4 )
#define APERF0_BW2_RMAX_MASK 0x00ffffff
#define APERF0_BW2_RMAX_WIDTH 24
#define APERF0_BW2_RMAX_RESET 0000000000
#define APERF0_BW2_RPEND HW_REGISTER_RO( 0x7e009868 )
#define APERF0_BW2_RPEND_MASK 0x000000ff
#define APERF0_BW2_RPEND_WIDTH 8
#define APERF0_BW2_RPEND_RESET 0000000000

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bcm2708_chip/axi_performance1.h Executable file
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// This file was generated by the create_regs script
#define APERF1_BASE 0x7ee08000
#define APERF1_APB_ID 0x41584950
#define APERF1_GEN_CTRL HW_REGISTER_RW( 0x7ee08000 )
#define APERF1_GEN_CTRL_MASK 0x00000003
#define APERF1_GEN_CTRL_WIDTH 2
#define APERF1_GEN_CTRL_RESET 0000000000
#define APERF1_GEN_CTRL_ENABLE_BITS 0:0
#define APERF1_GEN_CTRL_ENABLE_SET 0x00000001
#define APERF1_GEN_CTRL_ENABLE_CLR 0xfffffffe
#define APERF1_GEN_CTRL_ENABLE_MSB 0
#define APERF1_GEN_CTRL_ENABLE_LSB 0
#define APERF1_GEN_CTRL_ENABLE_RESET 0x0
#define APERF1_GEN_CTRL_RESET_BITS 1:1
#define APERF1_GEN_CTRL_RESET_SET 0x00000002
#define APERF1_GEN_CTRL_RESET_CLR 0xfffffffd
#define APERF1_GEN_CTRL_RESET_MSB 1
#define APERF1_GEN_CTRL_RESET_LSB 1
#define APERF1_GEN_CTRL_RESET_RESET 0x0
#define APERF1_BW0_CTRL HW_REGISTER_RW( 0x7ee08040 )
#define APERF1_BW0_CTRL_MASK 0xf0001f1f
#define APERF1_BW0_CTRL_WIDTH 32
#define APERF1_BW0_CTRL_RESET 0000000000
#define APERF1_BW0_CTRL_BUS_BITS 4:0
#define APERF1_BW0_CTRL_BUS_SET 0x0000001f
#define APERF1_BW0_CTRL_BUS_CLR 0xffffffe0
#define APERF1_BW0_CTRL_BUS_MSB 4
#define APERF1_BW0_CTRL_BUS_LSB 0
#define APERF1_BW0_CTRL_BUS_RESET 0x0
#define APERF1_BW0_CTRL_ID_BITS 12:8
#define APERF1_BW0_CTRL_ID_SET 0x00001f00
#define APERF1_BW0_CTRL_ID_CLR 0xffffe0ff
#define APERF1_BW0_CTRL_ID_MSB 12
#define APERF1_BW0_CTRL_ID_LSB 8
#define APERF1_BW0_CTRL_ID_RESET 0x0
#define APERF1_BW0_CTRL_LATHALT_BITS 28:28
#define APERF1_BW0_CTRL_LATHALT_SET 0x10000000
#define APERF1_BW0_CTRL_LATHALT_CLR 0xefffffff
#define APERF1_BW0_CTRL_LATHALT_MSB 28
#define APERF1_BW0_CTRL_LATHALT_LSB 28
#define APERF1_BW0_CTRL_LATHALT_RESET 0x0
#define APERF1_BW0_CTRL_ID_EN_BITS 29:29
#define APERF1_BW0_CTRL_ID_EN_SET 0x20000000
#define APERF1_BW0_CTRL_ID_EN_CLR 0xdfffffff
#define APERF1_BW0_CTRL_ID_EN_MSB 29
#define APERF1_BW0_CTRL_ID_EN_LSB 29
#define APERF1_BW0_CTRL_ID_EN_RESET 0x0
#define APERF1_BW0_CTRL_EN_BITS 30:30
#define APERF1_BW0_CTRL_EN_SET 0x40000000
#define APERF1_BW0_CTRL_EN_CLR 0xbfffffff
#define APERF1_BW0_CTRL_EN_MSB 30
#define APERF1_BW0_CTRL_EN_LSB 30
#define APERF1_BW0_CTRL_EN_RESET 0x0
#define APERF1_BW0_CTRL_RESET_BITS 31:31
#define APERF1_BW0_CTRL_RESET_SET 0x80000000
#define APERF1_BW0_CTRL_RESET_CLR 0x7fffffff
#define APERF1_BW0_CTRL_RESET_MSB 31
#define APERF1_BW0_CTRL_RESET_LSB 31
#define APERF1_BW0_CTRL_RESET_RESET 0x0
#define APERF1_BW0_ATRANS HW_REGISTER_RO( 0x7ee08044 )
#define APERF1_BW0_ATRANS_MASK 0xffffffff
#define APERF1_BW0_ATRANS_WIDTH 32
#define APERF1_BW0_ATRANS_RESET 0000000000
#define APERF1_BW0_ATWAIT HW_REGISTER_RO( 0x7ee08048 )
#define APERF1_BW0_ATWAIT_MASK 0xffffffff
#define APERF1_BW0_ATWAIT_WIDTH 32
#define APERF1_BW0_ATWAIT_RESET 0000000000
#define APERF1_BW0_AMAX HW_REGISTER_RO( 0x7ee0804c )
#define APERF1_BW0_AMAX_MASK 0x00ffffff
#define APERF1_BW0_AMAX_WIDTH 24
#define APERF1_BW0_AMAX_RESET 0000000000
#define APERF1_BW0_WTRANS HW_REGISTER_RO( 0x7ee08050 )
#define APERF1_BW0_WTRANS_MASK 0xffffffff
#define APERF1_BW0_WTRANS_WIDTH 32
#define APERF1_BW0_WTRANS_RESET 0000000000
#define APERF1_BW0_WTWAIT HW_REGISTER_RO( 0x7ee08054 )
#define APERF1_BW0_WTWAIT_MASK 0xffffffff
#define APERF1_BW0_WTWAIT_WIDTH 32
#define APERF1_BW0_WTWAIT_RESET 0000000000
#define APERF1_BW0_WMAX HW_REGISTER_RO( 0x7ee08058 )
#define APERF1_BW0_WMAX_MASK 0x00ffffff
#define APERF1_BW0_WMAX_WIDTH 24
#define APERF1_BW0_WMAX_RESET 0000000000
#define APERF1_BW0_RTRANS HW_REGISTER_RO( 0x7ee0805c )
#define APERF1_BW0_RTRANS_MASK 0xffffffff
#define APERF1_BW0_RTRANS_WIDTH 32
#define APERF1_BW0_RTRANS_RESET 0000000000
#define APERF1_BW0_RTWAIT HW_REGISTER_RO( 0x7ee08060 )
#define APERF1_BW0_RTWAIT_MASK 0xffffffff
#define APERF1_BW0_RTWAIT_WIDTH 32
#define APERF1_BW0_RTWAIT_RESET 0000000000
#define APERF1_BW0_RMAX HW_REGISTER_RO( 0x7ee08064 )
#define APERF1_BW0_RMAX_MASK 0x00ffffff
#define APERF1_BW0_RMAX_WIDTH 24
#define APERF1_BW0_RMAX_RESET 0000000000
#define APERF1_BW0_RPEND HW_REGISTER_RO( 0x7ee08068 )
#define APERF1_BW0_RPEND_MASK 0x000000ff
#define APERF1_BW0_RPEND_WIDTH 8
#define APERF1_BW0_RPEND_RESET 0000000000
#define APERF1_BW1_CTRL HW_REGISTER_RW( 0x7ee08080 )
#define APERF1_BW1_CTRL_MASK 0xf0001f1f
#define APERF1_BW1_CTRL_WIDTH 32
#define APERF1_BW1_CTRL_RESET 0000000000
#define APERF1_BW1_CTRL_BUS_BITS 4:0
#define APERF1_BW1_CTRL_BUS_SET 0x0000001f
#define APERF1_BW1_CTRL_BUS_CLR 0xffffffe0
#define APERF1_BW1_CTRL_BUS_MSB 4
#define APERF1_BW1_CTRL_BUS_LSB 0
#define APERF1_BW1_CTRL_BUS_RESET 0x0
#define APERF1_BW1_CTRL_ID_BITS 12:8
#define APERF1_BW1_CTRL_ID_SET 0x00001f00
#define APERF1_BW1_CTRL_ID_CLR 0xffffe0ff
#define APERF1_BW1_CTRL_ID_MSB 12
#define APERF1_BW1_CTRL_ID_LSB 8
#define APERF1_BW1_CTRL_ID_RESET 0x0
#define APERF1_BW1_CTRL_LATHALT_BITS 28:28
#define APERF1_BW1_CTRL_LATHALT_SET 0x10000000
#define APERF1_BW1_CTRL_LATHALT_CLR 0xefffffff
#define APERF1_BW1_CTRL_LATHALT_MSB 28
#define APERF1_BW1_CTRL_LATHALT_LSB 28
#define APERF1_BW1_CTRL_LATHALT_RESET 0x0
#define APERF1_BW1_CTRL_ID_EN_BITS 29:29
#define APERF1_BW1_CTRL_ID_EN_SET 0x20000000
#define APERF1_BW1_CTRL_ID_EN_CLR 0xdfffffff
#define APERF1_BW1_CTRL_ID_EN_MSB 29
#define APERF1_BW1_CTRL_ID_EN_LSB 29
#define APERF1_BW1_CTRL_ID_EN_RESET 0x0
#define APERF1_BW1_CTRL_EN_BITS 30:30
#define APERF1_BW1_CTRL_EN_SET 0x40000000
#define APERF1_BW1_CTRL_EN_CLR 0xbfffffff
#define APERF1_BW1_CTRL_EN_MSB 30
#define APERF1_BW1_CTRL_EN_LSB 30
#define APERF1_BW1_CTRL_EN_RESET 0x0
#define APERF1_BW1_CTRL_RESET_BITS 31:31
#define APERF1_BW1_CTRL_RESET_SET 0x80000000
#define APERF1_BW1_CTRL_RESET_CLR 0x7fffffff
#define APERF1_BW1_CTRL_RESET_MSB 31
#define APERF1_BW1_CTRL_RESET_LSB 31
#define APERF1_BW1_CTRL_RESET_RESET 0x0
#define APERF1_BW1_ATRANS HW_REGISTER_RO( 0x7ee08084 )
#define APERF1_BW1_ATRANS_MASK 0xffffffff
#define APERF1_BW1_ATRANS_WIDTH 32
#define APERF1_BW1_ATRANS_RESET 0000000000
#define APERF1_BW1_ATWAIT HW_REGISTER_RO( 0x7ee08088 )
#define APERF1_BW1_ATWAIT_MASK 0xffffffff
#define APERF1_BW1_ATWAIT_WIDTH 32
#define APERF1_BW1_ATWAIT_RESET 0000000000
#define APERF1_BW1_AMAX HW_REGISTER_RO( 0x7ee0808c )
#define APERF1_BW1_AMAX_MASK 0x00ffffff
#define APERF1_BW1_AMAX_WIDTH 24
#define APERF1_BW1_AMAX_RESET 0000000000
#define APERF1_BW1_WTRANS HW_REGISTER_RO( 0x7ee08090 )
#define APERF1_BW1_WTRANS_MASK 0xffffffff
#define APERF1_BW1_WTRANS_WIDTH 32
#define APERF1_BW1_WTRANS_RESET 0000000000
#define APERF1_BW1_WTWAIT HW_REGISTER_RO( 0x7ee08094 )
#define APERF1_BW1_WTWAIT_MASK 0xffffffff
#define APERF1_BW1_WTWAIT_WIDTH 32
#define APERF1_BW1_WTWAIT_RESET 0000000000
#define APERF1_BW1_WMAX HW_REGISTER_RO( 0x7ee08098 )
#define APERF1_BW1_WMAX_MASK 0x0000ffff
#define APERF1_BW1_WMAX_WIDTH 16
#define APERF1_BW1_WMAX_RESET 0000000000
#define APERF1_BW1_RTRANS HW_REGISTER_RO( 0x7ee0809c )
#define APERF1_BW1_RTRANS_MASK 0xffffffff
#define APERF1_BW1_RTRANS_WIDTH 32
#define APERF1_BW1_RTRANS_RESET 0000000000
#define APERF1_BW1_RTWAIT HW_REGISTER_RO( 0x7ee080a0 )
#define APERF1_BW1_RTWAIT_MASK 0xffffffff
#define APERF1_BW1_RTWAIT_WIDTH 32
#define APERF1_BW1_RTWAIT_RESET 0000000000
#define APERF1_BW1_RMAX HW_REGISTER_RO( 0x7ee080a4 )
#define APERF1_BW1_RMAX_MASK 0x00ffffff
#define APERF1_BW1_RMAX_WIDTH 24
#define APERF1_BW1_RMAX_RESET 0000000000
#define APERF1_BW1_RPEND HW_REGISTER_RO( 0x7ee08068 )
#define APERF1_BW1_RPEND_MASK 0x000000ff
#define APERF1_BW1_RPEND_WIDTH 8
#define APERF1_BW1_RPEND_RESET 0000000000
#define APERF1_BW2_CTRL HW_REGISTER_RW( 0x7ee080c0 )
#define APERF1_BW2_CTRL_MASK 0xf0001f1f
#define APERF1_BW2_CTRL_WIDTH 32
#define APERF1_BW2_CTRL_RESET 0000000000
#define APERF1_BW2_CTRL_BUS_BITS 4:0
#define APERF1_BW2_CTRL_BUS_SET 0x0000001f
#define APERF1_BW2_CTRL_BUS_CLR 0xffffffe0
#define APERF1_BW2_CTRL_BUS_MSB 4
#define APERF1_BW2_CTRL_BUS_LSB 0
#define APERF1_BW2_CTRL_BUS_RESET 0x0
#define APERF1_BW2_CTRL_ID_BITS 12:8
#define APERF1_BW2_CTRL_ID_SET 0x00001f00
#define APERF1_BW2_CTRL_ID_CLR 0xffffe0ff
#define APERF1_BW2_CTRL_ID_MSB 12
#define APERF1_BW2_CTRL_ID_LSB 8
#define APERF1_BW2_CTRL_ID_RESET 0x0
#define APERF1_BW2_CTRL_LATHALT_BITS 28:28
#define APERF1_BW2_CTRL_LATHALT_SET 0x10000000
#define APERF1_BW2_CTRL_LATHALT_CLR 0xefffffff
#define APERF1_BW2_CTRL_LATHALT_MSB 28
#define APERF1_BW2_CTRL_LATHALT_LSB 28
#define APERF1_BW2_CTRL_LATHALT_RESET 0x0
#define APERF1_BW2_CTRL_ID_EN_BITS 29:29
#define APERF1_BW2_CTRL_ID_EN_SET 0x20000000
#define APERF1_BW2_CTRL_ID_EN_CLR 0xdfffffff
#define APERF1_BW2_CTRL_ID_EN_MSB 29
#define APERF1_BW2_CTRL_ID_EN_LSB 29
#define APERF1_BW2_CTRL_ID_EN_RESET 0x0
#define APERF1_BW2_CTRL_EN_BITS 30:30
#define APERF1_BW2_CTRL_EN_SET 0x40000000
#define APERF1_BW2_CTRL_EN_CLR 0xbfffffff
#define APERF1_BW2_CTRL_EN_MSB 30
#define APERF1_BW2_CTRL_EN_LSB 30
#define APERF1_BW2_CTRL_EN_RESET 0x0
#define APERF1_BW2_CTRL_RESET_BITS 31:31
#define APERF1_BW2_CTRL_RESET_SET 0x80000000
#define APERF1_BW2_CTRL_RESET_CLR 0x7fffffff
#define APERF1_BW2_CTRL_RESET_MSB 31
#define APERF1_BW2_CTRL_RESET_LSB 31
#define APERF1_BW2_CTRL_RESET_RESET 0x0
#define APERF1_BW2_ATRANS HW_REGISTER_RO( 0x7ee080c4 )
#define APERF1_BW2_ATRANS_MASK 0xffffffff
#define APERF1_BW2_ATRANS_WIDTH 32
#define APERF1_BW2_ATRANS_RESET 0000000000
#define APERF1_BW2_ATWAIT HW_REGISTER_RO( 0x7ee080c8 )
#define APERF1_BW2_ATWAIT_MASK 0xffffffff
#define APERF1_BW2_ATWAIT_WIDTH 32
#define APERF1_BW2_ATWAIT_RESET 0000000000
#define APERF1_BW2_AMAX HW_REGISTER_RO( 0x7ee080cc )
#define APERF1_BW2_AMAX_MASK 0x00ffffff
#define APERF1_BW2_AMAX_WIDTH 24
#define APERF1_BW2_AMAX_RESET 0000000000
#define APERF1_BW2_WTRANS HW_REGISTER_RO( 0x7ee080d0 )
#define APERF1_BW2_WTRANS_MASK 0xffffffff
#define APERF1_BW2_WTRANS_WIDTH 32
#define APERF1_BW2_WTRANS_RESET 0000000000
#define APERF1_BW2_WTWAIT HW_REGISTER_RO( 0x7ee080d4 )
#define APERF1_BW2_WTWAIT_MASK 0xffffffff
#define APERF1_BW2_WTWAIT_WIDTH 32
#define APERF1_BW2_WTWAIT_RESET 0000000000
#define APERF1_BW2_WMAX HW_REGISTER_RO( 0x7ee080d8 )
#define APERF1_BW2_WMAX_MASK 0x0ff0ffff
#define APERF1_BW2_WMAX_WIDTH 28
#define APERF1_BW2_WMAX_RESET 0000000000
#define APERF1_BW2_RTRANS HW_REGISTER_RO( 0x7ee080dc )
#define APERF1_BW2_RTRANS_MASK 0xffffffff
#define APERF1_BW2_RTRANS_WIDTH 32
#define APERF1_BW2_RTRANS_RESET 0000000000
#define APERF1_BW2_RTWAIT HW_REGISTER_RO( 0x7ee080e0 )
#define APERF1_BW2_RTWAIT_MASK 0xffffffff
#define APERF1_BW2_RTWAIT_WIDTH 32
#define APERF1_BW2_RTWAIT_RESET 0000000000
#define APERF1_BW2_RMAX HW_REGISTER_RO( 0x7ee080e4 )
#define APERF1_BW2_RMAX_MASK 0x00ffffff
#define APERF1_BW2_RMAX_WIDTH 24
#define APERF1_BW2_RMAX_RESET 0000000000
#define APERF1_BW2_RPEND HW_REGISTER_RO( 0x7ee08068 )
#define APERF1_BW2_RPEND_MASK 0x000000ff
#define APERF1_BW2_RPEND_WIDTH 8
#define APERF1_BW2_RPEND_RESET 0000000000

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bcm2708_chip/cam0.h Executable file
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// This file was generated by the create_regs script
#define CAM0_BASE 0x7e800000
#define CAM0_APB_ID 0x7563616d
#define CAM0_CAMCTL HW_REGISTER_RW( 0x7e800000 )
#define CAM0_CAMCTL_MASK 0xffffffff
#define CAM0_CAMCTL_WIDTH 32
#define CAM0_CAMCTL_RESET 0000000000
#define CAM0_CAMSTA HW_REGISTER_RW( 0x7e800004 )
#define CAM0_CAMSTA_MASK 0xffffffff
#define CAM0_CAMSTA_WIDTH 32
#define CAM0_CAMSTA_RESET 0000000000
#define CAM0_CAMANA HW_REGISTER_RW( 0x7e800008 )
#define CAM0_CAMANA_MASK 0xffffffff
#define CAM0_CAMANA_WIDTH 32
#define CAM0_CAMANA_RESET 0x00000777
#define CAM0_CAMPRI HW_REGISTER_RW( 0x7e80000c )
#define CAM0_CAMPRI_MASK 0xffffffff
#define CAM0_CAMPRI_WIDTH 32
#define CAM0_CAMPRI_RESET 0000000000
#define CAM0_CAMCLK HW_REGISTER_RW( 0x7e800010 )
#define CAM0_CAMCLK_MASK 0xffffffff
#define CAM0_CAMCLK_WIDTH 32
#define CAM0_CAMCLK_RESET 0x00000002
#define CAM0_CAMCLT HW_REGISTER_RW( 0x7e800014 )
#define CAM0_CAMCLT_MASK 0xffffffff
#define CAM0_CAMCLT_WIDTH 32
#define CAM0_CAMCLT_RESET 0000000000
#define CAM0_CAMDAT0 HW_REGISTER_RW( 0x7e800018 )
#define CAM0_CAMDAT0_MASK 0xffffffff
#define CAM0_CAMDAT0_WIDTH 32
#define CAM0_CAMDAT0_RESET 0x00000002
#define CAM0_CAMDAT1 HW_REGISTER_RW( 0x7e80001c )
#define CAM0_CAMDAT1_MASK 0xffffffff
#define CAM0_CAMDAT1_WIDTH 32
#define CAM0_CAMDAT1_RESET 0x00000002
#define CAM0_CAMDAT2 HW_REGISTER_RW( 0x7e800020 )
#define CAM0_CAMDAT2_MASK 0xffffffff
#define CAM0_CAMDAT2_WIDTH 32
#define CAM0_CAMDAT2_RESET 0x00000002
#define CAM0_CAMDAT3 HW_REGISTER_RW( 0x7e800024 )
#define CAM0_CAMDAT3_MASK 0xffffffff
#define CAM0_CAMDAT3_WIDTH 32
#define CAM0_CAMDAT3_RESET 0x00000002
#define CAM0_CAMDLT HW_REGISTER_RW( 0x7e800028 )
#define CAM0_CAMDLT_MASK 0xffffffff
#define CAM0_CAMDLT_WIDTH 32
#define CAM0_CAMDLT_RESET 0000000000
#define CAM0_CAMCMP0 HW_REGISTER_RW( 0x7e80002c )
#define CAM0_CAMCMP0_MASK 0xffffffff
#define CAM0_CAMCMP0_WIDTH 32
#define CAM0_CAMCMP0_RESET 0000000000
#define CAM0_CAMCMP1 HW_REGISTER_RW( 0x7e800030 )
#define CAM0_CAMCMP1_MASK 0xffffffff
#define CAM0_CAMCMP1_WIDTH 32
#define CAM0_CAMCMP1_RESET 0000000000
#define CAM0_CAMCAP0 HW_REGISTER_RW( 0x7e800034 )
#define CAM0_CAMCAP0_MASK 0xffffffff
#define CAM0_CAMCAP0_WIDTH 32
#define CAM0_CAMCAP0_RESET 0000000000
#define CAM0_CAMCAP1 HW_REGISTER_RW( 0x7e800038 )
#define CAM0_CAMCAP1_MASK 0xffffffff
#define CAM0_CAMCAP1_WIDTH 32
#define CAM0_CAMCAP1_RESET 0000000000
#define CAM0_CAMDBG0 HW_REGISTER_RW( 0x7e8000f0 )
#define CAM0_CAMDBG0_MASK 0xffffffff
#define CAM0_CAMDBG0_WIDTH 32
#define CAM0_CAMDBG0_RESET 0000000000
#define CAM0_CAMDBG1 HW_REGISTER_RW( 0x7e8000f4 )
#define CAM0_CAMDBG1_MASK 0xffffffff
#define CAM0_CAMDBG1_WIDTH 32
#define CAM0_CAMDBG1_RESET 0000000000
#define CAM0_CAMDBG2 HW_REGISTER_RW( 0x7e8000f8 )
#define CAM0_CAMDBG2_MASK 0xffffffff
#define CAM0_CAMDBG2_WIDTH 32
#define CAM0_CAMDBG2_RESET 0000000000
#define CAM0_CAMDBG3 HW_REGISTER_RW( 0x7e8000fc )
#define CAM0_CAMDBG3_MASK 0xffffffff
#define CAM0_CAMDBG3_WIDTH 32
#define CAM0_CAMDBG3_RESET 0000000000
#define CAM0_CAMICTL HW_REGISTER_RW( 0x7e800100 )
#define CAM0_CAMICTL_MASK 0xffffffff
#define CAM0_CAMICTL_WIDTH 32
#define CAM0_CAMICTL_RESET 0000000000
#define CAM0_CAMISTA HW_REGISTER_RW( 0x7e800104 )
#define CAM0_CAMISTA_MASK 0xffffffff
#define CAM0_CAMISTA_WIDTH 32
#define CAM0_CAMISTA_RESET 0000000000
#define CAM0_CAMIDI0 HW_REGISTER_RW( 0x7e800108 )
#define CAM0_CAMIDI0_MASK 0xffffffff
#define CAM0_CAMIDI0_WIDTH 32
#define CAM0_CAMIDI0_RESET 0000000000
#define CAM0_CAMIPIPE HW_REGISTER_RW( 0x7e80010c )
#define CAM0_CAMIPIPE_MASK 0xffffffff
#define CAM0_CAMIPIPE_WIDTH 32
#define CAM0_CAMIPIPE_RESET 0000000000
#define CAM0_CAMIBSA0 HW_REGISTER_RW( 0x7e800110 )
#define CAM0_CAMIBSA0_MASK 0xffffffff
#define CAM0_CAMIBSA0_WIDTH 32
#define CAM0_CAMIBSA0_RESET 0000000000
#define CAM0_CAMIBEA0 HW_REGISTER_RW( 0x7e800114 )
#define CAM0_CAMIBEA0_MASK 0xffffffff
#define CAM0_CAMIBEA0_WIDTH 32
#define CAM0_CAMIBEA0_RESET 0000000000
#define CAM0_CAMIBLS HW_REGISTER_RW( 0x7e800118 )
#define CAM0_CAMIBLS_MASK 0xffffffff
#define CAM0_CAMIBLS_WIDTH 32
#define CAM0_CAMIBLS_RESET 0000000000
#define CAM0_CAMIBWP HW_REGISTER_RW( 0x7e80011c )
#define CAM0_CAMIBWP_MASK 0xffffffff
#define CAM0_CAMIBWP_WIDTH 32
#define CAM0_CAMIBWP_RESET 0000000000
#define CAM0_CAMIHWIN HW_REGISTER_RW( 0x7e800120 )
#define CAM0_CAMIHWIN_MASK 0xffffffff
#define CAM0_CAMIHWIN_WIDTH 32
#define CAM0_CAMIHWIN_RESET 0000000000
#define CAM0_CAMIHSTA HW_REGISTER_RW( 0x7e800124 )
#define CAM0_CAMIHSTA_MASK 0xffffffff
#define CAM0_CAMIHSTA_WIDTH 32
#define CAM0_CAMIHSTA_RESET 0000000000
#define CAM0_CAMIVWIN HW_REGISTER_RW( 0x7e800128 )
#define CAM0_CAMIVWIN_MASK 0xffffffff
#define CAM0_CAMIVWIN_WIDTH 32
#define CAM0_CAMIVWIN_RESET 0000000000
#define CAM0_CAMIVSTA HW_REGISTER_RW( 0x7e80012c )
#define CAM0_CAMIVSTA_MASK 0xffffffff
#define CAM0_CAMIVSTA_WIDTH 32
#define CAM0_CAMIVSTA_RESET 0000000000
#define CAM0_CAMICC HW_REGISTER_RW( 0x7e800130 )
#define CAM0_CAMICC_MASK 0xffffffff
#define CAM0_CAMICC_WIDTH 32
#define CAM0_CAMICC_RESET 0000000000
#define CAM0_CAMICS HW_REGISTER_RW( 0x7e800134 )
#define CAM0_CAMICS_MASK 0xffffffff
#define CAM0_CAMICS_WIDTH 32
#define CAM0_CAMICS_RESET 0000000000
#define CAM0_CAMIDC HW_REGISTER_RW( 0x7e800138 )
#define CAM0_CAMIDC_MASK 0xffffffff
#define CAM0_CAMIDC_WIDTH 32
#define CAM0_CAMIDC_RESET 0000000000
#define CAM0_CAMIDPO HW_REGISTER_RW( 0x7e80013c )
#define CAM0_CAMIDPO_MASK 0xffffffff
#define CAM0_CAMIDPO_WIDTH 32
#define CAM0_CAMIDPO_RESET 0000000000
#define CAM0_CAMIDCA HW_REGISTER_RW( 0x7e800140 )
#define CAM0_CAMIDCA_MASK 0xffffffff
#define CAM0_CAMIDCA_WIDTH 32
#define CAM0_CAMIDCA_RESET 0000000000
#define CAM0_CAMIDCD HW_REGISTER_RW( 0x7e800144 )
#define CAM0_CAMIDCD_MASK 0xffffffff
#define CAM0_CAMIDCD_WIDTH 32
#define CAM0_CAMIDCD_RESET 0000000000
#define CAM0_CAMIDS HW_REGISTER_RW( 0x7e800148 )
#define CAM0_CAMIDS_MASK 0xffffffff
#define CAM0_CAMIDS_WIDTH 32
#define CAM0_CAMIDS_RESET 0000000000
#define CAM0_CAMDCS HW_REGISTER_RW( 0x7e800200 )
#define CAM0_CAMDCS_MASK 0xffffffff
#define CAM0_CAMDCS_WIDTH 32
#define CAM0_CAMDCS_RESET 0000000000
#define CAM0_CAMDBSA0 HW_REGISTER_RW( 0x7e800204 )
#define CAM0_CAMDBSA0_MASK 0xffffffff
#define CAM0_CAMDBSA0_WIDTH 32
#define CAM0_CAMDBSA0_RESET 0000000000
#define CAM0_CAMDBEA0 HW_REGISTER_RW( 0x7e800208 )
#define CAM0_CAMDBEA0_MASK 0xffffffff
#define CAM0_CAMDBEA0_WIDTH 32
#define CAM0_CAMDBEA0_RESET 0000000000
#define CAM0_CAMDBWP HW_REGISTER_RW( 0x7e80020c )
#define CAM0_CAMDBWP_MASK 0xffffffff
#define CAM0_CAMDBWP_WIDTH 32
#define CAM0_CAMDBWP_RESET 0000000000
#define CAM0_CAMDBCTL HW_REGISTER_RW( 0x7e800300 )
#define CAM0_CAMDBCTL_MASK 0xffffffff
#define CAM0_CAMDBCTL_WIDTH 32
#define CAM0_CAMDBCTL_RESET 0000000000
#define CAM0_CAMIBSA1 HW_REGISTER_RW( 0x7e800304 )
#define CAM0_CAMIBSA1_MASK 0xffffffff
#define CAM0_CAMIBSA1_WIDTH 32
#define CAM0_CAMIBSA1_RESET 0000000000
#define CAM0_CAMIBEA1 HW_REGISTER_RW( 0x7e800308 )
#define CAM0_CAMIBEA1_MASK 0xffffffff
#define CAM0_CAMIBEA1_WIDTH 32
#define CAM0_CAMIBEA1_RESET 0000000000
#define CAM0_CAMIDI1 HW_REGISTER_RW( 0x7e80030c )
#define CAM0_CAMIDI1_MASK 0xffffffff
#define CAM0_CAMIDI1_WIDTH 32
#define CAM0_CAMIDI1_RESET 0000000000
#define CAM0_CAMDBSA1 HW_REGISTER_RW( 0x7e800310 )
#define CAM0_CAMDBSA1_MASK 0xffffffff
#define CAM0_CAMDBSA1_WIDTH 32
#define CAM0_CAMDBSA1_RESET 0000000000
#define CAM0_CAMDBEA1 HW_REGISTER_RW( 0x7e800314 )
#define CAM0_CAMDBEA1_MASK 0xffffffff
#define CAM0_CAMDBEA1_WIDTH 32
#define CAM0_CAMDBEA1_RESET 0000000000
#define CAM0_CAMMISC HW_REGISTER_RW( 0x7e800400 )
#define CAM0_CAMMISC_MASK 0xffffffff
#define CAM0_CAMMISC_WIDTH 32
#define CAM0_CAMMISC_RESET 0000000000

131
bcm2708_chip/cam0_a0.h Executable file
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// This file was generated by the create_regs script
#define CAM0_BASE 0x7e800000
#define CAM0_APB_ID 0x7563616d
#define CAM0_CTL HW_REGISTER_RW( 0x7e800000 )
#define CAM0_CTL_MASK 0xffffffff
#define CAM0_CTL_WIDTH 32
#define CAM0_CTL_RESET 0000000000
#define CAM0_STA HW_REGISTER_RW( 0x7e800004 )
#define CAM0_STA_MASK 0xffffffff
#define CAM0_STA_WIDTH 32
#define CAM0_STA_RESET 0000000000
#define CAM0_ANA HW_REGISTER_RW( 0x7e800008 )
#define CAM0_ANA_MASK 0xffffffff
#define CAM0_ANA_WIDTH 32
#define CAM0_ANA_RESET 0000000000
#define CAM0_PRI HW_REGISTER_RW( 0x7e80000c )
#define CAM0_PRI_MASK 0xffffffff
#define CAM0_PRI_WIDTH 32
#define CAM0_PRI_RESET 0000000000
#define CAM0_CLK HW_REGISTER_RW( 0x7e800010 )
#define CAM0_CLK_MASK 0xffffffff
#define CAM0_CLK_WIDTH 32
#define CAM0_CLK_RESET 0000000000
#define CAM0_DAT0 HW_REGISTER_RW( 0x7e800014 )
#define CAM0_DAT0_MASK 0xffffffff
#define CAM0_DAT0_WIDTH 32
#define CAM0_DAT0_RESET 0000000000
#define CAM0_DAT1 HW_REGISTER_RW( 0x7e800018 )
#define CAM0_DAT1_MASK 0xffffffff
#define CAM0_DAT1_WIDTH 32
#define CAM0_DAT1_RESET 0000000000
#define CAM0_DAT2 HW_REGISTER_RW( 0x7e80001c )
#define CAM0_DAT2_MASK 0xffffffff
#define CAM0_DAT2_WIDTH 32
#define CAM0_DAT2_RESET 0000000000
#define CAM0_DAT3 HW_REGISTER_RW( 0x7e800020 )
#define CAM0_DAT3_MASK 0xffffffff
#define CAM0_DAT3_WIDTH 32
#define CAM0_DAT3_RESET 0000000000
#define CAM0_CMP0 HW_REGISTER_RW( 0x7e800024 )
#define CAM0_CMP0_MASK 0xffffffff
#define CAM0_CMP0_WIDTH 32
#define CAM0_CMP0_RESET 0000000000
#define CAM0_CMP1 HW_REGISTER_RW( 0x7e800028 )
#define CAM0_CMP1_MASK 0xffffffff
#define CAM0_CMP1_WIDTH 32
#define CAM0_CMP1_RESET 0000000000
#define CAM0_CAP0 HW_REGISTER_RW( 0x7e80002c )
#define CAM0_CAP0_MASK 0xffffffff
#define CAM0_CAP0_WIDTH 32
#define CAM0_CAP0_RESET 0000000000
#define CAM0_CAP1 HW_REGISTER_RW( 0x7e800030 )
#define CAM0_CAP1_MASK 0xffffffff
#define CAM0_CAP1_WIDTH 32
#define CAM0_CAP1_RESET 0000000000
#define CAM0_DBG0 HW_REGISTER_RW( 0x7e8000f0 )
#define CAM0_DBG0_MASK 0xffffffff
#define CAM0_DBG0_WIDTH 32
#define CAM0_DBG0_RESET 0000000000
#define CAM0_DBG1 HW_REGISTER_RW( 0x7e8000f4 )
#define CAM0_DBG1_MASK 0xffffffff
#define CAM0_DBG1_WIDTH 32
#define CAM0_DBG1_RESET 0000000000
#define CAM0_DBG2 HW_REGISTER_RW( 0x7e8000f8 )
#define CAM0_DBG2_MASK 0xffffffff
#define CAM0_DBG2_WIDTH 32
#define CAM0_DBG2_RESET 0000000000
#define CAM0_ICTL HW_REGISTER_RW( 0x7e800100 )
#define CAM0_ICTL_MASK 0xffffffff
#define CAM0_ICTL_WIDTH 32
#define CAM0_ICTL_RESET 0000000000
#define CAM0_ISTA HW_REGISTER_RW( 0x7e800104 )
#define CAM0_ISTA_MASK 0xffffffff
#define CAM0_ISTA_WIDTH 32
#define CAM0_ISTA_RESET 0000000000
#define CAM0_IDI HW_REGISTER_RW( 0x7e800108 )
#define CAM0_IDI_MASK 0xffffffff
#define CAM0_IDI_WIDTH 32
#define CAM0_IDI_RESET 0000000000
#define CAM0_IPIPE HW_REGISTER_RW( 0x7e80010c )
#define CAM0_IPIPE_MASK 0xffffffff
#define CAM0_IPIPE_WIDTH 32
#define CAM0_IPIPE_RESET 0000000000
#define CAM0_IBSA HW_REGISTER_RW( 0x7e800110 )
#define CAM0_IBSA_MASK 0xffffffff
#define CAM0_IBSA_WIDTH 32
#define CAM0_IBSA_RESET 0000000000
#define CAM0_IBEA HW_REGISTER_RW( 0x7e800114 )
#define CAM0_IBEA_MASK 0xffffffff
#define CAM0_IBEA_WIDTH 32
#define CAM0_IBEA_RESET 0000000000
#define CAM0_IBLS HW_REGISTER_RW( 0x7e800118 )
#define CAM0_IBLS_MASK 0xffffffff
#define CAM0_IBLS_WIDTH 32
#define CAM0_IBLS_RESET 0000000000
#define CAM0_IBWP HW_REGISTER_RW( 0x7e80011c )
#define CAM0_IBWP_MASK 0xffffffff
#define CAM0_IBWP_WIDTH 32
#define CAM0_IBWP_RESET 0000000000
#define CAM0_IHWIN HW_REGISTER_RW( 0x7e800120 )
#define CAM0_IHWIN_MASK 0xffffffff
#define CAM0_IHWIN_WIDTH 32
#define CAM0_IHWIN_RESET 0000000000
#define CAM0_IHSTA HW_REGISTER_RW( 0x7e800124 )
#define CAM0_IHSTA_MASK 0xffffffff
#define CAM0_IHSTA_WIDTH 32
#define CAM0_IHSTA_RESET 0000000000
#define CAM0_IVWIN HW_REGISTER_RW( 0x7e800128 )
#define CAM0_IVWIN_MASK 0xffffffff
#define CAM0_IVWIN_WIDTH 32
#define CAM0_IVWIN_RESET 0000000000
#define CAM0_IVSTA HW_REGISTER_RW( 0x7e80012c )
#define CAM0_IVSTA_MASK 0xffffffff
#define CAM0_IVSTA_WIDTH 32
#define CAM0_IVSTA_RESET 0000000000
#define CAM0_DCS HW_REGISTER_RW( 0x7e800200 )
#define CAM0_DCS_MASK 0xffffffff
#define CAM0_DCS_WIDTH 32
#define CAM0_DCS_RESET 0000000000
#define CAM0_DBSA HW_REGISTER_RW( 0x7e800204 )
#define CAM0_DBSA_MASK 0xffffffff
#define CAM0_DBSA_WIDTH 32
#define CAM0_DBSA_RESET 0000000000
#define CAM0_DBEA HW_REGISTER_RW( 0x7e800208 )
#define CAM0_DBEA_MASK 0xffffffff
#define CAM0_DBEA_WIDTH 32
#define CAM0_DBEA_RESET 0000000000
#define CAM0_DBWP HW_REGISTER_RW( 0x7e800208 )
#define CAM0_DBWP_MASK 0xffffffff
#define CAM0_DBWP_WIDTH 32
#define CAM0_DBWP_RESET 0000000000

199
bcm2708_chip/cam1.h Executable file
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// This file was generated by the create_regs script
#define CAM1_BASE 0x7e801000
#define CAM1_APB_ID 0x7563616d
#define CAM1_CAMCTL HW_REGISTER_RW( 0x7e801000 )
#define CAM1_CAMCTL_MASK 0xffffffff
#define CAM1_CAMCTL_WIDTH 32
#define CAM1_CAMCTL_RESET 0000000000
#define CAM1_CAMSTA HW_REGISTER_RW( 0x7e801004 )
#define CAM1_CAMSTA_MASK 0xffffffff
#define CAM1_CAMSTA_WIDTH 32
#define CAM1_CAMSTA_RESET 0000000000
#define CAM1_CAMANA HW_REGISTER_RW( 0x7e801008 )
#define CAM1_CAMANA_MASK 0xffffffff
#define CAM1_CAMANA_WIDTH 32
#define CAM1_CAMANA_RESET 0x00000777
#define CAM1_CAMPRI HW_REGISTER_RW( 0x7e80100c )
#define CAM1_CAMPRI_MASK 0xffffffff
#define CAM1_CAMPRI_WIDTH 32
#define CAM1_CAMPRI_RESET 0000000000
#define CAM1_CAMCLK HW_REGISTER_RW( 0x7e801010 )
#define CAM1_CAMCLK_MASK 0xffffffff
#define CAM1_CAMCLK_WIDTH 32
#define CAM1_CAMCLK_RESET 0x00000002
#define CAM1_CAMCLT HW_REGISTER_RW( 0x7e801014 )
#define CAM1_CAMCLT_MASK 0xffffffff
#define CAM1_CAMCLT_WIDTH 32
#define CAM1_CAMCLT_RESET 0000000000
#define CAM1_CAMDAT0 HW_REGISTER_RW( 0x7e801018 )
#define CAM1_CAMDAT0_MASK 0xffffffff
#define CAM1_CAMDAT0_WIDTH 32
#define CAM1_CAMDAT0_RESET 0x00000002
#define CAM1_CAMDAT1 HW_REGISTER_RW( 0x7e80101c )
#define CAM1_CAMDAT1_MASK 0xffffffff
#define CAM1_CAMDAT1_WIDTH 32
#define CAM1_CAMDAT1_RESET 0x00000002
#define CAM1_CAMDAT2 HW_REGISTER_RW( 0x7e801020 )
#define CAM1_CAMDAT2_MASK 0xffffffff
#define CAM1_CAMDAT2_WIDTH 32
#define CAM1_CAMDAT2_RESET 0x00000002
#define CAM1_CAMDAT3 HW_REGISTER_RW( 0x7e801024 )
#define CAM1_CAMDAT3_MASK 0xffffffff
#define CAM1_CAMDAT3_WIDTH 32
#define CAM1_CAMDAT3_RESET 0x00000002
#define CAM1_CAMDLT HW_REGISTER_RW( 0x7e801028 )
#define CAM1_CAMDLT_MASK 0xffffffff
#define CAM1_CAMDLT_WIDTH 32
#define CAM1_CAMDLT_RESET 0000000000
#define CAM1_CAMCMP0 HW_REGISTER_RW( 0x7e80102c )
#define CAM1_CAMCMP0_MASK 0xffffffff
#define CAM1_CAMCMP0_WIDTH 32
#define CAM1_CAMCMP0_RESET 0000000000
#define CAM1_CAMCMP1 HW_REGISTER_RW( 0x7e801030 )
#define CAM1_CAMCMP1_MASK 0xffffffff
#define CAM1_CAMCMP1_WIDTH 32
#define CAM1_CAMCMP1_RESET 0000000000
#define CAM1_CAMCAP0 HW_REGISTER_RW( 0x7e801034 )
#define CAM1_CAMCAP0_MASK 0xffffffff
#define CAM1_CAMCAP0_WIDTH 32
#define CAM1_CAMCAP0_RESET 0000000000
#define CAM1_CAMCAP1 HW_REGISTER_RW( 0x7e801038 )
#define CAM1_CAMCAP1_MASK 0xffffffff
#define CAM1_CAMCAP1_WIDTH 32
#define CAM1_CAMCAP1_RESET 0000000000
#define CAM1_CAMDBG0 HW_REGISTER_RW( 0x7e8010f0 )
#define CAM1_CAMDBG0_MASK 0xffffffff
#define CAM1_CAMDBG0_WIDTH 32
#define CAM1_CAMDBG0_RESET 0000000000
#define CAM1_CAMDBG1 HW_REGISTER_RW( 0x7e8010f4 )
#define CAM1_CAMDBG1_MASK 0xffffffff
#define CAM1_CAMDBG1_WIDTH 32
#define CAM1_CAMDBG1_RESET 0000000000
#define CAM1_CAMDBG2 HW_REGISTER_RW( 0x7e8010f8 )
#define CAM1_CAMDBG2_MASK 0xffffffff
#define CAM1_CAMDBG2_WIDTH 32
#define CAM1_CAMDBG2_RESET 0000000000
#define CAM1_CAMDBG3 HW_REGISTER_RW( 0x7e8010fc )
#define CAM1_CAMDBG3_MASK 0xffffffff
#define CAM1_CAMDBG3_WIDTH 32
#define CAM1_CAMDBG3_RESET 0000000000
#define CAM1_CAMICTL HW_REGISTER_RW( 0x7e801100 )
#define CAM1_CAMICTL_MASK 0xffffffff
#define CAM1_CAMICTL_WIDTH 32
#define CAM1_CAMICTL_RESET 0000000000
#define CAM1_CAMISTA HW_REGISTER_RW( 0x7e801104 )
#define CAM1_CAMISTA_MASK 0xffffffff
#define CAM1_CAMISTA_WIDTH 32
#define CAM1_CAMISTA_RESET 0000000000
#define CAM1_CAMIDI0 HW_REGISTER_RW( 0x7e801108 )
#define CAM1_CAMIDI0_MASK 0xffffffff
#define CAM1_CAMIDI0_WIDTH 32
#define CAM1_CAMIDI0_RESET 0000000000
#define CAM1_CAMIPIPE HW_REGISTER_RW( 0x7e80110c )
#define CAM1_CAMIPIPE_MASK 0xffffffff
#define CAM1_CAMIPIPE_WIDTH 32
#define CAM1_CAMIPIPE_RESET 0000000000
#define CAM1_CAMIBSA0 HW_REGISTER_RW( 0x7e801110 )
#define CAM1_CAMIBSA0_MASK 0xffffffff
#define CAM1_CAMIBSA0_WIDTH 32
#define CAM1_CAMIBSA0_RESET 0000000000
#define CAM1_CAMIBEA0 HW_REGISTER_RW( 0x7e801114 )
#define CAM1_CAMIBEA0_MASK 0xffffffff
#define CAM1_CAMIBEA0_WIDTH 32
#define CAM1_CAMIBEA0_RESET 0000000000
#define CAM1_CAMIBLS HW_REGISTER_RW( 0x7e801118 )
#define CAM1_CAMIBLS_MASK 0xffffffff
#define CAM1_CAMIBLS_WIDTH 32
#define CAM1_CAMIBLS_RESET 0000000000
#define CAM1_CAMIBWP HW_REGISTER_RW( 0x7e80111c )
#define CAM1_CAMIBWP_MASK 0xffffffff
#define CAM1_CAMIBWP_WIDTH 32
#define CAM1_CAMIBWP_RESET 0000000000
#define CAM1_CAMIHWIN HW_REGISTER_RW( 0x7e801120 )
#define CAM1_CAMIHWIN_MASK 0xffffffff
#define CAM1_CAMIHWIN_WIDTH 32
#define CAM1_CAMIHWIN_RESET 0000000000
#define CAM1_CAMIHSTA HW_REGISTER_RW( 0x7e801124 )
#define CAM1_CAMIHSTA_MASK 0xffffffff
#define CAM1_CAMIHSTA_WIDTH 32
#define CAM1_CAMIHSTA_RESET 0000000000
#define CAM1_CAMIVWIN HW_REGISTER_RW( 0x7e801128 )
#define CAM1_CAMIVWIN_MASK 0xffffffff
#define CAM1_CAMIVWIN_WIDTH 32
#define CAM1_CAMIVWIN_RESET 0000000000
#define CAM1_CAMIVSTA HW_REGISTER_RW( 0x7e80112c )
#define CAM1_CAMIVSTA_MASK 0xffffffff
#define CAM1_CAMIVSTA_WIDTH 32
#define CAM1_CAMIVSTA_RESET 0000000000
#define CAM1_CAMICC HW_REGISTER_RW( 0x7e801130 )
#define CAM1_CAMICC_MASK 0xffffffff
#define CAM1_CAMICC_WIDTH 32
#define CAM1_CAMICC_RESET 0000000000
#define CAM1_CAMICS HW_REGISTER_RW( 0x7e801134 )
#define CAM1_CAMICS_MASK 0xffffffff
#define CAM1_CAMICS_WIDTH 32
#define CAM1_CAMICS_RESET 0000000000
#define CAM1_CAMIDC HW_REGISTER_RW( 0x7e801138 )
#define CAM1_CAMIDC_MASK 0xffffffff
#define CAM1_CAMIDC_WIDTH 32
#define CAM1_CAMIDC_RESET 0000000000
#define CAM1_CAMIDPO HW_REGISTER_RW( 0x7e80113c )
#define CAM1_CAMIDPO_MASK 0xffffffff
#define CAM1_CAMIDPO_WIDTH 32
#define CAM1_CAMIDPO_RESET 0000000000
#define CAM1_CAMIDCA HW_REGISTER_RW( 0x7e801140 )
#define CAM1_CAMIDCA_MASK 0xffffffff
#define CAM1_CAMIDCA_WIDTH 32
#define CAM1_CAMIDCA_RESET 0000000000
#define CAM1_CAMIDCD HW_REGISTER_RW( 0x7e801144 )
#define CAM1_CAMIDCD_MASK 0xffffffff
#define CAM1_CAMIDCD_WIDTH 32
#define CAM1_CAMIDCD_RESET 0000000000
#define CAM1_CAMIDS HW_REGISTER_RW( 0x7e801148 )
#define CAM1_CAMIDS_MASK 0xffffffff
#define CAM1_CAMIDS_WIDTH 32
#define CAM1_CAMIDS_RESET 0000000000
#define CAM1_CAMDCS HW_REGISTER_RW( 0x7e801200 )
#define CAM1_CAMDCS_MASK 0xffffffff
#define CAM1_CAMDCS_WIDTH 32
#define CAM1_CAMDCS_RESET 0000000000
#define CAM1_CAMDBSA0 HW_REGISTER_RW( 0x7e801204 )
#define CAM1_CAMDBSA0_MASK 0xffffffff
#define CAM1_CAMDBSA0_WIDTH 32
#define CAM1_CAMDBSA0_RESET 0000000000
#define CAM1_CAMDBEA0 HW_REGISTER_RW( 0x7e801208 )
#define CAM1_CAMDBEA0_MASK 0xffffffff
#define CAM1_CAMDBEA0_WIDTH 32
#define CAM1_CAMDBEA0_RESET 0000000000
#define CAM1_CAMDBWP HW_REGISTER_RW( 0x7e80120c )
#define CAM1_CAMDBWP_MASK 0xffffffff
#define CAM1_CAMDBWP_WIDTH 32
#define CAM1_CAMDBWP_RESET 0000000000
#define CAM1_CAMDBCTL HW_REGISTER_RW( 0x7e801300 )
#define CAM1_CAMDBCTL_MASK 0xffffffff
#define CAM1_CAMDBCTL_WIDTH 32
#define CAM1_CAMDBCTL_RESET 0000000000
#define CAM1_CAMIBSA1 HW_REGISTER_RW( 0x7e801304 )
#define CAM1_CAMIBSA1_MASK 0xffffffff
#define CAM1_CAMIBSA1_WIDTH 32
#define CAM1_CAMIBSA1_RESET 0000000000
#define CAM1_CAMIBEA1 HW_REGISTER_RW( 0x7e801308 )
#define CAM1_CAMIBEA1_MASK 0xffffffff
#define CAM1_CAMIBEA1_WIDTH 32
#define CAM1_CAMIBEA1_RESET 0000000000
#define CAM1_CAMIDI1 HW_REGISTER_RW( 0x7e80130c )
#define CAM1_CAMIDI1_MASK 0xffffffff
#define CAM1_CAMIDI1_WIDTH 32
#define CAM1_CAMIDI1_RESET 0000000000
#define CAM1_CAMDBSA1 HW_REGISTER_RW( 0x7e801310 )
#define CAM1_CAMDBSA1_MASK 0xffffffff
#define CAM1_CAMDBSA1_WIDTH 32
#define CAM1_CAMDBSA1_RESET 0000000000
#define CAM1_CAMDBEA1 HW_REGISTER_RW( 0x7e801314 )
#define CAM1_CAMDBEA1_MASK 0xffffffff
#define CAM1_CAMDBEA1_WIDTH 32
#define CAM1_CAMDBEA1_RESET 0000000000
#define CAM1_CAMMISC HW_REGISTER_RW( 0x7e801400 )
#define CAM1_CAMMISC_MASK 0xffffffff
#define CAM1_CAMMISC_WIDTH 32
#define CAM1_CAMMISC_RESET 0000000000

131
bcm2708_chip/cam1_a0.h Executable file
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// This file was generated by the create_regs script
#define CAM1_BASE 0x7e801000
#define CAM1_APB_ID 0x7563616d
#define CAM1_CTL HW_REGISTER_RW( 0x7e801000 )
#define CAM1_CTL_MASK 0xffffffff
#define CAM1_CTL_WIDTH 32
#define CAM1_CTL_RESET 0000000000
#define CAM1_STA HW_REGISTER_RW( 0x7e801004 )
#define CAM1_STA_MASK 0xffffffff
#define CAM1_STA_WIDTH 32
#define CAM1_STA_RESET 0000000000
#define CAM1_ANA HW_REGISTER_RW( 0x7e801008 )
#define CAM1_ANA_MASK 0xffffffff
#define CAM1_ANA_WIDTH 32
#define CAM1_ANA_RESET 0000000000
#define CAM1_PRI HW_REGISTER_RW( 0x7e80100c )
#define CAM1_PRI_MASK 0xffffffff
#define CAM1_PRI_WIDTH 32
#define CAM1_PRI_RESET 0000000000
#define CAM1_CLK HW_REGISTER_RW( 0x7e801010 )
#define CAM1_CLK_MASK 0xffffffff
#define CAM1_CLK_WIDTH 32
#define CAM1_CLK_RESET 0000000000
#define CAM1_DAT0 HW_REGISTER_RW( 0x7e801014 )
#define CAM1_DAT0_MASK 0xffffffff
#define CAM1_DAT0_WIDTH 32
#define CAM1_DAT0_RESET 0000000000
#define CAM1_DAT1 HW_REGISTER_RW( 0x7e801018 )
#define CAM1_DAT1_MASK 0xffffffff
#define CAM1_DAT1_WIDTH 32
#define CAM1_DAT1_RESET 0000000000
#define CAM1_DAT2 HW_REGISTER_RW( 0x7e80101c )
#define CAM1_DAT2_MASK 0xffffffff
#define CAM1_DAT2_WIDTH 32
#define CAM1_DAT2_RESET 0000000000
#define CAM1_DAT3 HW_REGISTER_RW( 0x7e801020 )
#define CAM1_DAT3_MASK 0xffffffff
#define CAM1_DAT3_WIDTH 32
#define CAM1_DAT3_RESET 0000000000
#define CAM1_CMP0 HW_REGISTER_RW( 0x7e801024 )
#define CAM1_CMP0_MASK 0xffffffff
#define CAM1_CMP0_WIDTH 32
#define CAM1_CMP0_RESET 0000000000
#define CAM1_CMP1 HW_REGISTER_RW( 0x7e801028 )
#define CAM1_CMP1_MASK 0xffffffff
#define CAM1_CMP1_WIDTH 32
#define CAM1_CMP1_RESET 0000000000
#define CAM1_CAP0 HW_REGISTER_RW( 0x7e80102c )
#define CAM1_CAP0_MASK 0xffffffff
#define CAM1_CAP0_WIDTH 32
#define CAM1_CAP0_RESET 0000000000
#define CAM1_CAP1 HW_REGISTER_RW( 0x7e801030 )
#define CAM1_CAP1_MASK 0xffffffff
#define CAM1_CAP1_WIDTH 32
#define CAM1_CAP1_RESET 0000000000
#define CAM1_DBG0 HW_REGISTER_RW( 0x7e8010f0 )
#define CAM1_DBG0_MASK 0xffffffff
#define CAM1_DBG0_WIDTH 32
#define CAM1_DBG0_RESET 0000000000
#define CAM1_DBG1 HW_REGISTER_RW( 0x7e8010f4 )
#define CAM1_DBG1_MASK 0xffffffff
#define CAM1_DBG1_WIDTH 32
#define CAM1_DBG1_RESET 0000000000
#define CAM1_DBG2 HW_REGISTER_RW( 0x7e8010f8 )
#define CAM1_DBG2_MASK 0xffffffff
#define CAM1_DBG2_WIDTH 32
#define CAM1_DBG2_RESET 0000000000
#define CAM1_ICTL HW_REGISTER_RW( 0x7e801100 )
#define CAM1_ICTL_MASK 0xffffffff
#define CAM1_ICTL_WIDTH 32
#define CAM1_ICTL_RESET 0000000000
#define CAM1_ISTA HW_REGISTER_RW( 0x7e801104 )
#define CAM1_ISTA_MASK 0xffffffff
#define CAM1_ISTA_WIDTH 32
#define CAM1_ISTA_RESET 0000000000
#define CAM1_IDI HW_REGISTER_RW( 0x7e801108 )
#define CAM1_IDI_MASK 0xffffffff
#define CAM1_IDI_WIDTH 32
#define CAM1_IDI_RESET 0000000000
#define CAM1_IPIPE HW_REGISTER_RW( 0x7e80110c )
#define CAM1_IPIPE_MASK 0xffffffff
#define CAM1_IPIPE_WIDTH 32
#define CAM1_IPIPE_RESET 0000000000
#define CAM1_IBSA HW_REGISTER_RW( 0x7e801110 )
#define CAM1_IBSA_MASK 0xffffffff
#define CAM1_IBSA_WIDTH 32
#define CAM1_IBSA_RESET 0000000000
#define CAM1_IBEA HW_REGISTER_RW( 0x7e801114 )
#define CAM1_IBEA_MASK 0xffffffff
#define CAM1_IBEA_WIDTH 32
#define CAM1_IBEA_RESET 0000000000
#define CAM1_IBLS HW_REGISTER_RW( 0x7e801118 )
#define CAM1_IBLS_MASK 0xffffffff
#define CAM1_IBLS_WIDTH 32
#define CAM1_IBLS_RESET 0000000000
#define CAM1_IBWP HW_REGISTER_RW( 0x7e80111c )
#define CAM1_IBWP_MASK 0xffffffff
#define CAM1_IBWP_WIDTH 32
#define CAM1_IBWP_RESET 0000000000
#define CAM1_IHWIN HW_REGISTER_RW( 0x7e801120 )
#define CAM1_IHWIN_MASK 0xffffffff
#define CAM1_IHWIN_WIDTH 32
#define CAM1_IHWIN_RESET 0000000000
#define CAM1_IHSTA HW_REGISTER_RW( 0x7e801124 )
#define CAM1_IHSTA_MASK 0xffffffff
#define CAM1_IHSTA_WIDTH 32
#define CAM1_IHSTA_RESET 0000000000
#define CAM1_IVWIN HW_REGISTER_RW( 0x7e801128 )
#define CAM1_IVWIN_MASK 0xffffffff
#define CAM1_IVWIN_WIDTH 32
#define CAM1_IVWIN_RESET 0000000000
#define CAM1_IVSTA HW_REGISTER_RW( 0x7e80112c )
#define CAM1_IVSTA_MASK 0xffffffff
#define CAM1_IVSTA_WIDTH 32
#define CAM1_IVSTA_RESET 0000000000
#define CAM1_DCS HW_REGISTER_RW( 0x7e801200 )
#define CAM1_DCS_MASK 0xffffffff
#define CAM1_DCS_WIDTH 32
#define CAM1_DCS_RESET 0000000000
#define CAM1_DBSA HW_REGISTER_RW( 0x7e801204 )
#define CAM1_DBSA_MASK 0xffffffff
#define CAM1_DBSA_WIDTH 32
#define CAM1_DBSA_RESET 0000000000
#define CAM1_DBEA HW_REGISTER_RW( 0x7e801208 )
#define CAM1_DBEA_MASK 0xffffffff
#define CAM1_DBEA_WIDTH 32
#define CAM1_DBEA_RESET 0000000000
#define CAM1_DBWP HW_REGISTER_RW( 0x7e801208 )
#define CAM1_DBWP_MASK 0xffffffff
#define CAM1_DBWP_WIDTH 32
#define CAM1_DBWP_RESET 0000000000

138
bcm2708_chip/camccp.h Executable file
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// This file was generated by the create_regs script
#define CCP_BASE 0x7e801000
#define CCP_APB_ID 0x63637032
#define CCP_RC HW_REGISTER_RW( 0x7e801000 )
#define CCP_RC_MASK 0xffffffff
#define CCP_RC_WIDTH 32
#define CCP_RC__MSB 31
#define CCP_RC__LSB 0
#define CCP_RS HW_REGISTER_RW( 0x7e801004 )
#define CCP_RS_MASK 0xffffffff
#define CCP_RS_WIDTH 32
#define CCP_RS__MSB 31
#define CCP_RS__LSB 0
#define CCP_RDR1 HW_REGISTER_RW( 0x7e801080 )
#define CCP_RDR1_MASK 0xffffffff
#define CCP_RDR1_WIDTH 32
#define CCP_RDR1__MSB 31
#define CCP_RDR1__LSB 0
#define CCP_RDR2 HW_REGISTER_RW( 0x7e801084 )
#define CCP_RDR2_MASK 0xffffffff
#define CCP_RDR2_WIDTH 32
#define CCP_RDR2__MSB 31
#define CCP_RDR2__LSB 0
#define CCP_RDR3 HW_REGISTER_RW( 0x7e801088 )
#define CCP_RDR3_MASK 0xffffffff
#define CCP_RDR3_WIDTH 32
#define CCP_RDR3__MSB 31
#define CCP_RDR3__LSB 0
#define CCP_RC0 HW_REGISTER_RW( 0x7e801100 )
#define CCP_RC0_MASK 0xffffffff
#define CCP_RC0_WIDTH 32
#define CCP_RC0__MSB 31
#define CCP_RC0__LSB 0
#define CCP_RPC0 HW_REGISTER_RW( 0x7e801104 )
#define CCP_RPC0_MASK 0xffffffff
#define CCP_RPC0_WIDTH 32
#define CCP_RPC0__MSB 31
#define CCP_RPC0__LSB 0
#define CCP_RS0 HW_REGISTER_RW( 0x7e801108 )
#define CCP_RS0_MASK 0xffffffff
#define CCP_RS0_WIDTH 32
#define CCP_RS0__MSB 31
#define CCP_RS0__LSB 0
#define CCP_RSA0 HW_REGISTER_RW( 0x7e80110c )
#define CCP_RSA0_MASK 0xffffffff
#define CCP_RSA0_WIDTH 32
#define CCP_RSA0__MSB 31
#define CCP_RSA0__LSB 0
#define CCP_REA0 HW_REGISTER_RW( 0x7e801110 )
#define CCP_REA0_MASK 0xffffffff
#define CCP_REA0_WIDTH 32
#define CCP_REA0__MSB 31
#define CCP_REA0__LSB 0
#define CCP_RWP0 HW_REGISTER_RW( 0x7e801114 )
#define CCP_RWP0_MASK 0xffffffff
#define CCP_RWP0_WIDTH 32
#define CCP_RWP0__MSB 31
#define CCP_RWP0__LSB 0
#define CCP_RBC0 HW_REGISTER_RW( 0x7e801118 )
#define CCP_RBC0_MASK 0xffffffff
#define CCP_RBC0_WIDTH 32
#define CCP_RBC0__MSB 31
#define CCP_RBC0__LSB 0
#define CCP_RLS0 HW_REGISTER_RW( 0x7e80111c )
#define CCP_RLS0_MASK 0xffffffff
#define CCP_RLS0_WIDTH 32
#define CCP_RLS0__MSB 31
#define CCP_RLS0__LSB 0
#define CCP_RDSA0 HW_REGISTER_RW( 0x7e801120 )
#define CCP_RDSA0_MASK 0xffffffff
#define CCP_RDSA0_WIDTH 32
#define CCP_RDSA0__MSB 31
#define CCP_RDSA0__LSB 0
#define CCP_RDEA0 HW_REGISTER_RW( 0x7e801124 )
#define CCP_RDEA0_MASK 0xffffffff
#define CCP_RDEA0_WIDTH 32
#define CCP_RDEA0__MSB 31
#define CCP_RDEA0__LSB 0
#define CCP_RDS0 HW_REGISTER_RW( 0x7e801128 )
#define CCP_RDS0_MASK 0xffffffff
#define CCP_RDS0_WIDTH 32
#define CCP_RDS0__MSB 31
#define CCP_RDS0__LSB 0
#define CCP_RC1 HW_REGISTER_RW( 0x7e801200 )
#define CCP_RC1_MASK 0xffffffff
#define CCP_RC1_WIDTH 32
#define CCP_RC1__MSB 31
#define CCP_RC1__LSB 0
#define CCP_RPC1 HW_REGISTER_RW( 0x7e801204 )
#define CCP_RPC1_MASK 0xffffffff
#define CCP_RPC1_WIDTH 32
#define CCP_RPC1__MSB 31
#define CCP_RPC1__LSB 0
#define CCP_RS1 HW_REGISTER_RW( 0x7e801208 )
#define CCP_RS1_MASK 0xffffffff
#define CCP_RS1_WIDTH 32
#define CCP_RS1__MSB 31
#define CCP_RS1__LSB 0
#define CCP_RSA1 HW_REGISTER_RW( 0x7e80120c )
#define CCP_RSA1_MASK 0xffffffff
#define CCP_RSA1_WIDTH 32
#define CCP_RSA1__MSB 31
#define CCP_RSA1__LSB 0
#define CCP_REA1 HW_REGISTER_RW( 0x7e801210 )
#define CCP_REA1_MASK 0xffffffff
#define CCP_REA1_WIDTH 32
#define CCP_REA1__MSB 31
#define CCP_REA1__LSB 0
#define CCP_RWP1 HW_REGISTER_RW( 0x7e801214 )
#define CCP_RWP1_MASK 0xffffffff
#define CCP_RWP1_WIDTH 32
#define CCP_RWP1__MSB 31
#define CCP_RWP1__LSB 0
#define CCP_RBC1 HW_REGISTER_RW( 0x7e801218 )
#define CCP_RBC1_MASK 0xffffffff
#define CCP_RBC1_WIDTH 32
#define CCP_RBC1__MSB 31
#define CCP_RBC1__LSB 0
#define CCP_RLS1 HW_REGISTER_RW( 0x7e80121c )
#define CCP_RLS1_MASK 0xffffffff
#define CCP_RLS1_WIDTH 32
#define CCP_RLS1__MSB 31
#define CCP_RLS1__LSB 0
#define CCP_RDSA1 HW_REGISTER_RW( 0x7e801220 )
#define CCP_RDSA1_MASK 0xffffffff
#define CCP_RDSA1_WIDTH 32
#define CCP_RDSA1__MSB 31
#define CCP_RDSA1__LSB 0
#define CCP_RDEA1 HW_REGISTER_RW( 0x7e801224 )
#define CCP_RDEA1_MASK 0xffffffff
#define CCP_RDEA1_WIDTH 32
#define CCP_RDEA1__MSB 31
#define CCP_RDEA1__LSB 0
#define CCP_RDS1 HW_REGISTER_RW( 0x7e801228 )
#define CCP_RDS1_MASK 0xffffffff
#define CCP_RDS1_WIDTH 32
#define CCP_RDS1__MSB 31
#define CCP_RDS1__LSB 0

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bcm2708_chip/ccp2tx.h Executable file
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// This file was generated by the create_regs script
#define CCP2TX_BASE 0x7e001000
#define CCP2TX_APB_ID 0x63637032
#define CCP2TX_TC HW_REGISTER_RW( 0x7e001000 )
#define CCP2TX_TC_MASK 0x8000ff07
#define CCP2TX_TC_WIDTH 32
#define CCP2TX_TC_RESET 0x0000ff00
#define CCP2TX_TC_SWR_BITS 31:31
#define CCP2TX_TC_SWR_SET 0x80000000
#define CCP2TX_TC_SWR_CLR 0x7fffffff
#define CCP2TX_TC_SWR_MSB 31
#define CCP2TX_TC_SWR_LSB 31
#define CCP2TX_TC_TIP_BITS 15:8
#define CCP2TX_TC_TIP_SET 0x0000ff00
#define CCP2TX_TC_TIP_CLR 0xffff00ff
#define CCP2TX_TC_TIP_MSB 15
#define CCP2TX_TC_TIP_LSB 8
#define CCP2TX_TC_CLKM_BITS 2:2
#define CCP2TX_TC_CLKM_SET 0x00000004
#define CCP2TX_TC_CLKM_CLR 0xfffffffb
#define CCP2TX_TC_CLKM_MSB 2
#define CCP2TX_TC_CLKM_LSB 2
#define CCP2TX_TC_MEN_BITS 1:1
#define CCP2TX_TC_MEN_SET 0x00000002
#define CCP2TX_TC_MEN_CLR 0xfffffffd
#define CCP2TX_TC_MEN_MSB 1
#define CCP2TX_TC_MEN_LSB 1
#define CCP2TX_TC_TEN_BITS 0:0
#define CCP2TX_TC_TEN_SET 0x00000001
#define CCP2TX_TC_TEN_CLR 0xfffffffe
#define CCP2TX_TC_TEN_MSB 0
#define CCP2TX_TC_TEN_LSB 0
#define CCP2TX_TS HW_REGISTER_RW( 0x7e001004 )
#define CCP2TX_TS_MASK 0x000f1f7f
#define CCP2TX_TS_WIDTH 20
#define CCP2TX_TS_RESET 0000000000
#define CCP2TX_TS_TQI_BITS 19:19
#define CCP2TX_TS_TQI_SET 0x00080000
#define CCP2TX_TS_TQI_CLR 0xfff7ffff
#define CCP2TX_TS_TQI_MSB 19
#define CCP2TX_TS_TQI_LSB 19
#define CCP2TX_TS_TEI_BITS 18:18
#define CCP2TX_TS_TEI_SET 0x00040000
#define CCP2TX_TS_TEI_CLR 0xfffbffff
#define CCP2TX_TS_TEI_MSB 18
#define CCP2TX_TS_TEI_LSB 18
#define CCP2TX_TS_TII_BITS 17:17
#define CCP2TX_TS_TII_SET 0x00020000
#define CCP2TX_TS_TII_CLR 0xfffdffff
#define CCP2TX_TS_TII_MSB 17
#define CCP2TX_TS_TII_LSB 17
#define CCP2TX_TS_IS_BITS 16:16
#define CCP2TX_TS_IS_SET 0x00010000
#define CCP2TX_TS_IS_CLR 0xfffeffff
#define CCP2TX_TS_IS_MSB 16
#define CCP2TX_TS_IS_LSB 16
#define CCP2TX_TS_TQL_BITS 12:8
#define CCP2TX_TS_TQL_SET 0x00001f00
#define CCP2TX_TS_TQL_CLR 0xffffe0ff
#define CCP2TX_TS_TQL_MSB 12
#define CCP2TX_TS_TQL_LSB 8
#define CCP2TX_TS_TFP_BITS 6:6
#define CCP2TX_TS_TFP_SET 0x00000040
#define CCP2TX_TS_TFP_CLR 0xffffffbf
#define CCP2TX_TS_TFP_MSB 6
#define CCP2TX_TS_TFP_LSB 6
#define CCP2TX_TS_TFF_BITS 5:5
#define CCP2TX_TS_TFF_SET 0x00000020
#define CCP2TX_TS_TFF_CLR 0xffffffdf
#define CCP2TX_TS_TFF_MSB 5
#define CCP2TX_TS_TFF_LSB 5
#define CCP2TX_TS_TFE_BITS 4:4
#define CCP2TX_TS_TFE_SET 0x00000010
#define CCP2TX_TS_TFE_CLR 0xffffffef
#define CCP2TX_TS_TFE_MSB 4
#define CCP2TX_TS_TFE_LSB 4
#define CCP2TX_TS_TUE_BITS 3:3
#define CCP2TX_TS_TUE_SET 0x00000008
#define CCP2TX_TS_TUE_CLR 0xfffffff7
#define CCP2TX_TS_TUE_MSB 3
#define CCP2TX_TS_TUE_LSB 3
#define CCP2TX_TS_ARE_BITS 2:2
#define CCP2TX_TS_ARE_SET 0x00000004
#define CCP2TX_TS_ARE_CLR 0xfffffffb
#define CCP2TX_TS_ARE_MSB 2
#define CCP2TX_TS_ARE_LSB 2
#define CCP2TX_TS_IEB_BITS 1:1
#define CCP2TX_TS_IEB_SET 0x00000002
#define CCP2TX_TS_IEB_CLR 0xfffffffd
#define CCP2TX_TS_IEB_MSB 1
#define CCP2TX_TS_IEB_LSB 1
#define CCP2TX_TS_TXB_BITS 0:0
#define CCP2TX_TS_TXB_SET 0x00000001
#define CCP2TX_TS_TXB_CLR 0xfffffffe
#define CCP2TX_TS_TXB_MSB 0
#define CCP2TX_TS_TXB_LSB 0
#define CCP2TX_TAC HW_REGISTER_RW( 0x7e001008 )
#define CCP2TX_TAC_MASK 0xffffff0f
#define CCP2TX_TAC_WIDTH 32
#define CCP2TX_TAC_RESET 0x77434307
#define CCP2TX_TAC_CTATADJ_BITS 31:28
#define CCP2TX_TAC_CTATADJ_SET 0xf0000000
#define CCP2TX_TAC_CTATADJ_CLR 0x0fffffff
#define CCP2TX_TAC_CTATADJ_MSB 31
#define CCP2TX_TAC_CTATADJ_LSB 28
#define CCP2TX_TAC_PTATADJ_BITS 27:24
#define CCP2TX_TAC_PTATADJ_SET 0x0f000000
#define CCP2TX_TAC_PTATADJ_CLR 0xf0ffffff
#define CCP2TX_TAC_PTATADJ_MSB 27
#define CCP2TX_TAC_PTATADJ_LSB 24
#define CCP2TX_TAC_CLAC_BITS 23:16
#define CCP2TX_TAC_CLAC_SET 0x00ff0000
#define CCP2TX_TAC_CLAC_CLR 0xff00ffff
#define CCP2TX_TAC_CLAC_MSB 23
#define CCP2TX_TAC_CLAC_LSB 16
#define CCP2TX_TAC_DLAC_BITS 15:8
#define CCP2TX_TAC_DLAC_SET 0x0000ff00
#define CCP2TX_TAC_DLAC_CLR 0xffff00ff
#define CCP2TX_TAC_DLAC_MSB 15
#define CCP2TX_TAC_DLAC_LSB 8
#define CCP2TX_TAC_TPC_BITS 3:3
#define CCP2TX_TAC_TPC_SET 0x00000008
#define CCP2TX_TAC_TPC_CLR 0xfffffff7
#define CCP2TX_TAC_TPC_MSB 3
#define CCP2TX_TAC_TPC_LSB 3
#define CCP2TX_TAC_BPD_BITS 2:2
#define CCP2TX_TAC_BPD_SET 0x00000004
#define CCP2TX_TAC_BPD_CLR 0xfffffffb
#define CCP2TX_TAC_BPD_MSB 2
#define CCP2TX_TAC_BPD_LSB 2
#define CCP2TX_TAC_APD_BITS 1:1
#define CCP2TX_TAC_APD_SET 0x00000002
#define CCP2TX_TAC_APD_CLR 0xfffffffd
#define CCP2TX_TAC_APD_MSB 1
#define CCP2TX_TAC_APD_LSB 1
#define CCP2TX_TAC_ARST_BITS 0:0
#define CCP2TX_TAC_ARST_SET 0x00000001
#define CCP2TX_TAC_ARST_CLR 0xfffffffe
#define CCP2TX_TAC_ARST_MSB 0
#define CCP2TX_TAC_ARST_LSB 0
#define CCP2TX_TPC HW_REGISTER_RW( 0x7e00100c )
#define CCP2TX_TPC_MASK 0x0000ffff
#define CCP2TX_TPC_WIDTH 16
#define CCP2TX_TPC_RESET 0000000000
#define CCP2TX_TPC_TPT_BITS 15:8
#define CCP2TX_TPC_TPT_SET 0x0000ff00
#define CCP2TX_TPC_TPT_CLR 0xffff00ff
#define CCP2TX_TPC_TPT_MSB 15
#define CCP2TX_TPC_TPT_LSB 8
#define CCP2TX_TPC_TPP_BITS 7:4
#define CCP2TX_TPC_TPP_SET 0x000000f0
#define CCP2TX_TPC_TPP_CLR 0xffffff0f
#define CCP2TX_TPC_TPP_MSB 7
#define CCP2TX_TPC_TPP_LSB 4
#define CCP2TX_TPC_TNP_BITS 3:0
#define CCP2TX_TPC_TNP_SET 0x0000000f
#define CCP2TX_TPC_TNP_CLR 0xfffffff0
#define CCP2TX_TPC_TNP_MSB 3
#define CCP2TX_TPC_TNP_LSB 0
#define CCP2TX_TSC HW_REGISTER_RW( 0x7e001010 )
#define CCP2TX_TSC_MASK 0x0000000f
#define CCP2TX_TSC_WIDTH 4
#define CCP2TX_TSC_RESET 0x00000002
#define CCP2TX_TSC_TSM_BITS 3:0
#define CCP2TX_TSC_TSM_SET 0x0000000f
#define CCP2TX_TSC_TSM_CLR 0xfffffff0
#define CCP2TX_TSC_TSM_MSB 3
#define CCP2TX_TSC_TSM_LSB 0
#define CCP2TX_TIC HW_REGISTER_RW( 0x7e001014 )
#define CCP2TX_TIC_MASK 0x000000f7
#define CCP2TX_TIC_WIDTH 8
#define CCP2TX_TIC_RESET 0000000000
#define CCP2TX_TIC_TQIT_BITS 7:4
#define CCP2TX_TIC_TQIT_SET 0x000000f0
#define CCP2TX_TIC_TQIT_CLR 0xffffff0f
#define CCP2TX_TIC_TQIT_MSB 7
#define CCP2TX_TIC_TQIT_LSB 4
#define CCP2TX_TIC_TQIE_BITS 2:2
#define CCP2TX_TIC_TQIE_SET 0x00000004
#define CCP2TX_TIC_TQIE_CLR 0xfffffffb
#define CCP2TX_TIC_TQIE_MSB 2
#define CCP2TX_TIC_TQIE_LSB 2
#define CCP2TX_TIC_TEIE_BITS 1:1
#define CCP2TX_TIC_TEIE_SET 0x00000002
#define CCP2TX_TIC_TEIE_CLR 0xfffffffd
#define CCP2TX_TIC_TEIE_MSB 1
#define CCP2TX_TIC_TEIE_LSB 1
#define CCP2TX_TIC_TIIE_BITS 0:0
#define CCP2TX_TIC_TIIE_SET 0x00000001
#define CCP2TX_TIC_TIIE_CLR 0xfffffffe
#define CCP2TX_TIC_TIIE_MSB 0
#define CCP2TX_TIC_TIIE_LSB 0
#define CCP2TX_TTC HW_REGISTER_RW( 0x7e001018 )
#define CCP2TX_TTC_MASK 0x80ff1fff
#define CCP2TX_TTC_WIDTH 32
#define CCP2TX_TTC_RESET 0x00000100
#define CCP2TX_TTC_ATX_BITS 31:31
#define CCP2TX_TTC_ATX_SET 0x80000000
#define CCP2TX_TTC_ATX_CLR 0x7fffffff
#define CCP2TX_TTC_ATX_MSB 31
#define CCP2TX_TTC_ATX_LSB 31
#define CCP2TX_TTC_BI_BITS 23:16
#define CCP2TX_TTC_BI_SET 0x00ff0000
#define CCP2TX_TTC_BI_CLR 0xff00ffff
#define CCP2TX_TTC_BI_MSB 23
#define CCP2TX_TTC_BI_LSB 16
#define CCP2TX_TTC_FSP_BITS 12:12
#define CCP2TX_TTC_FSP_SET 0x00001000
#define CCP2TX_TTC_FSP_CLR 0xffffefff
#define CCP2TX_TTC_FSP_MSB 12
#define CCP2TX_TTC_FSP_LSB 12
#define CCP2TX_TTC_LEC_BITS 11:8
#define CCP2TX_TTC_LEC_SET 0x00000f00
#define CCP2TX_TTC_LEC_CLR 0xfffff0ff
#define CCP2TX_TTC_LEC_MSB 11
#define CCP2TX_TTC_LEC_LSB 8
#define CCP2TX_TTC_LSC_BITS 7:4
#define CCP2TX_TTC_LSC_SET 0x000000f0
#define CCP2TX_TTC_LSC_CLR 0xffffff0f
#define CCP2TX_TTC_LSC_MSB 7
#define CCP2TX_TTC_LSC_LSB 4
#define CCP2TX_TTC_LCN_BITS 3:0
#define CCP2TX_TTC_LCN_SET 0x0000000f
#define CCP2TX_TTC_LCN_CLR 0xfffffff0
#define CCP2TX_TTC_LCN_MSB 3
#define CCP2TX_TTC_LCN_LSB 0
#define CCP2TX_TBA HW_REGISTER_RW( 0x7e00101c )
#define CCP2TX_TBA_MASK 0x3fffffff
#define CCP2TX_TBA_WIDTH 30
#define CCP2TX_TBA_RESET 0000000000
#define CCP2TX_TBA_ADDR_BITS 29:0
#define CCP2TX_TBA_ADDR_SET 0x3fffffff
#define CCP2TX_TBA_ADDR_CLR 0xc0000000
#define CCP2TX_TBA_ADDR_MSB 29
#define CCP2TX_TBA_ADDR_LSB 0
#define CCP2TX_TDL HW_REGISTER_RW( 0x7e001020 )
#define CCP2TX_TDL_MASK 0x3fffffff
#define CCP2TX_TDL_WIDTH 30
#define CCP2TX_TDL_RESET 0000000000
#define CCP2TX_TDL_LEN_BITS 29:0
#define CCP2TX_TDL_LEN_SET 0x3fffffff
#define CCP2TX_TDL_LEN_CLR 0xc0000000
#define CCP2TX_TDL_LEN_MSB 29
#define CCP2TX_TDL_LEN_LSB 0
#define CCP2TX_TD HW_REGISTER_RW( 0x7e001024 )
#define CCP2TX_TD_MASK 0x000000ff
#define CCP2TX_TD_WIDTH 8
#define CCP2TX_TD_IES_BITS 6:5
#define CCP2TX_TD_IES_SET 0x00000060
#define CCP2TX_TD_IES_CLR 0xffffff9f
#define CCP2TX_TD_IES_MSB 6
#define CCP2TX_TD_IES_LSB 5
#define CCP2TX_TD_TCS_BITS 4:0
#define CCP2TX_TD_TCS_SET 0x0000001f
#define CCP2TX_TD_TCS_CLR 0xffffffe0
#define CCP2TX_TD_TCS_MSB 4
#define CCP2TX_TD_TCS_LSB 0
#define CCP2TX_TSPARE HW_REGISTER_RW( 0x7e001028 )
#define CCP2TX_TSPARE_MASK 0xffffffff
#define CCP2TX_TSPARE_WIDTH 32

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bcm2708_chip/ccp2tx_a0.h Executable file
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// This file was generated by the create_regs script
#define CCP2TX_BASE 0x7e001000
#define CCP2TX_APB_ID 0x63637032
#define CCP2TX_TC HW_REGISTER_RW( 0x7e001000 )
#define CCP2TX_TC_MASK 0xffffffff
#define CCP2TX_TC_WIDTH 32
#define CCP2TX_TS HW_REGISTER_RW( 0x7e001004 )
#define CCP2TX_TS_MASK 0xffffffff
#define CCP2TX_TS_WIDTH 32
#define CCP2TX_TPC HW_REGISTER_RW( 0x7e001008 )
#define CCP2TX_TPC_MASK 0xffffffff
#define CCP2TX_TPC_WIDTH 32
#define CCP2TX_TSC HW_REGISTER_RW( 0x7e00100c )
#define CCP2TX_TSC_MASK 0xffffffff
#define CCP2TX_TSC_WIDTH 32
#define CCP2TX_TIC HW_REGISTER_RW( 0x7e001010 )
#define CCP2TX_TIC_MASK 0xffffffff
#define CCP2TX_TIC_WIDTH 32
#define CCP2TX_TTC HW_REGISTER_RW( 0x7e001014 )
#define CCP2TX_TTC_MASK 0xffffffff
#define CCP2TX_TTC_WIDTH 32
#define CCP2TX_TBA HW_REGISTER_RW( 0x7e001018 )
#define CCP2TX_TBA_MASK 0xffffffff
#define CCP2TX_TBA_WIDTH 32
#define CCP2TX_TDL HW_REGISTER_RW( 0x7e00101c )
#define CCP2TX_TDL_MASK 0xffffffff
#define CCP2TX_TDL_WIDTH 32
#define CCP2TX_TD HW_REGISTER_RW( 0x7e001020 )
#define CCP2TX_TD_MASK 0xffffffff
#define CCP2TX_TD_WIDTH 32

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bcm2708_chip/cdp.h Executable file
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// This file was generated by the create_regs script
#define CD_BASE 0x1820b000
#define CD_APB_ID 0x43445000
#define CD_CS HW_REGISTER_RW( 0x1820b000 )
#define CD_CS__MASK 0xffffffff
#define CD_CS__WIDTH 32
#define CD_CS__RESET 0000000000
#define CD_CS__MSB 31
#define CD_CS__LSB 0
#define CD_PHYADJ HW_REGISTER_RW( 0x1820b004 )
#define CD_PHYADJ__MASK 0x0000ffff
#define CD_PHYADJ__WIDTH 16
#define CD_PHYADJ__MSB 15
#define CD_PHYADJ__LSB 0
#define CD_PHYDAT HW_REGISTER_RO( 0x1820b008 )
#define CD_PHYDAT__MASK 0xffffffff
#define CD_PHYDAT__WIDTH 32
#define CD_PHYDAT__MSB 31
#define CD_PHYDAT__LSB 0

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bcm2708_chip/clkman_image.h Executable file
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// This file was generated by the create_regs script
#define CMI_PASSWORD 0x5a000000
#define CMI_BASE 0x7e802000
#define CMI_APB_ID 0x00636d69
#define CMI_CAM0 HW_REGISTER_RW( 0x7e802000 )
#define CMI_CAM0_MASK 0x0000003f
#define CMI_CAM0_WIDTH 6
#define CMI_CAM0_RESET 0000000000
#define CMI_CAM0_RX1SRC_BITS 5:4
#define CMI_CAM0_RX1SRC_SET 0x00000030
#define CMI_CAM0_RX1SRC_CLR 0xffffffcf
#define CMI_CAM0_RX1SRC_MSB 5
#define CMI_CAM0_RX1SRC_LSB 4
#define CMI_CAM0_RX0SRC_BITS 3:2
#define CMI_CAM0_RX0SRC_SET 0x0000000c
#define CMI_CAM0_RX0SRC_CLR 0xfffffff3
#define CMI_CAM0_RX0SRC_MSB 3
#define CMI_CAM0_RX0SRC_LSB 2
#define CMI_CAM0_HSSRC_BITS 1:0
#define CMI_CAM0_HSSRC_SET 0x00000003
#define CMI_CAM0_HSSRC_CLR 0xfffffffc
#define CMI_CAM0_HSSRC_MSB 1
#define CMI_CAM0_HSSRC_LSB 0
#define CMI_CAM1 HW_REGISTER_RW( 0x7e802004 )
#define CMI_CAM1_MASK 0x000003ff
#define CMI_CAM1_WIDTH 10
#define CMI_CAM1_RESET 0000000000
#define CMI_CAM1_RX3SRC_BITS 9:8
#define CMI_CAM1_RX3SRC_SET 0x00000300
#define CMI_CAM1_RX3SRC_CLR 0xfffffcff
#define CMI_CAM1_RX3SRC_MSB 9
#define CMI_CAM1_RX3SRC_LSB 8
#define CMI_CAM1_RX2SRC_BITS 7:6
#define CMI_CAM1_RX2SRC_SET 0x000000c0
#define CMI_CAM1_RX2SRC_CLR 0xffffff3f
#define CMI_CAM1_RX2SRC_MSB 7
#define CMI_CAM1_RX2SRC_LSB 6
#define CMI_CAM1_RX1SRC_BITS 5:4
#define CMI_CAM1_RX1SRC_SET 0x00000030
#define CMI_CAM1_RX1SRC_CLR 0xffffffcf
#define CMI_CAM1_RX1SRC_MSB 5
#define CMI_CAM1_RX1SRC_LSB 4
#define CMI_CAM1_RX0SRC_BITS 3:2
#define CMI_CAM1_RX0SRC_SET 0x0000000c
#define CMI_CAM1_RX0SRC_CLR 0xfffffff3
#define CMI_CAM1_RX0SRC_MSB 3
#define CMI_CAM1_RX0SRC_LSB 2
#define CMI_CAM1_HSSRC_BITS 1:0
#define CMI_CAM1_HSSRC_SET 0x00000003
#define CMI_CAM1_HSSRC_CLR 0xfffffffc
#define CMI_CAM1_HSSRC_MSB 1
#define CMI_CAM1_HSSRC_LSB 0
#define CMI_CAMTEST HW_REGISTER_RW( 0x7e802008 )
#define CMI_CAMTEST_MASK 0x0000001f
#define CMI_CAMTEST_WIDTH 5
#define CMI_CAMTEST_RESET 0000000000
#define CMI_CAMTEST_ENAB_BITS 4:4
#define CMI_CAMTEST_ENAB_SET 0x00000010
#define CMI_CAMTEST_ENAB_CLR 0xffffffef
#define CMI_CAMTEST_ENAB_MSB 4
#define CMI_CAMTEST_ENAB_LSB 4
#define CMI_CAMTEST_SRC_BITS 3:0
#define CMI_CAMTEST_SRC_SET 0x0000000f
#define CMI_CAMTEST_SRC_CLR 0xfffffff0
#define CMI_CAMTEST_SRC_MSB 3
#define CMI_CAMTEST_SRC_LSB 0
#define CMI_USBCTL HW_REGISTER_RW( 0x7e802010 )
#define CMI_USBCTL_MASK 0x00000040
#define CMI_USBCTL_WIDTH 7
#define CMI_USBCTL_RESET 0x00000040
#define CMI_USBCTL_GATE_BITS 6:6
#define CMI_USBCTL_GATE_SET 0x00000040
#define CMI_USBCTL_GATE_CLR 0xffffffbf
#define CMI_USBCTL_GATE_MSB 6
#define CMI_USBCTL_GATE_LSB 6

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bcm2708_chip/cpg.h Executable file
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// This file was generated by the create_regs script
#define CPG_BASE 0x7e211000
#define CPG_APB_ID 0x67706320
#define CPG_Config HW_REGISTER_RW( 0x7e211000 )
#define CPG_Config_MASK 0xffffffff
#define CPG_Config_WIDTH 32
#define CPG_IntStatus HW_REGISTER_RW( 0x7e211004 )
#define CPG_IntStatus_MASK 0xffffffff
#define CPG_IntStatus_WIDTH 32
#define CPG_Trigger HW_REGISTER_RW( 0x7e211008 )
#define CPG_Trigger_MASK 0x00000003
#define CPG_Trigger_WIDTH 2
#define CPG_Param0 HW_REGISTER_RW( 0x7e211010 )
#define CPG_Param0_MASK 0xffffffff
#define CPG_Param0_WIDTH 32
#define CPG_Param1 HW_REGISTER_RW( 0x7e211014 )
#define CPG_Param1_MASK 0xffffffff
#define CPG_Param1_WIDTH 32
#define CPG_Param2 HW_REGISTER_RW( 0x7e211018 )
#define CPG_Param2_MASK 0xffffffff
#define CPG_Param2_WIDTH 32
#define CPG_Param3 HW_REGISTER_RW( 0x7e21101c )
#define CPG_Param3_MASK 0xffffffff
#define CPG_Param3_WIDTH 32
#define CPG_Debug0 HW_REGISTER_RW( 0x7e211040 )
#define CPG_Debug0_MASK 0xffffffff
#define CPG_Debug0_WIDTH 32
#define CPG_Debug1 HW_REGISTER_RW( 0x7e211044 )
#define CPG_Debug1_MASK 0xffffffff
#define CPG_Debug1_WIDTH 32
#define CPG_Debug2 HW_REGISTER_RW( 0x7e211048 )
#define CPG_Debug2_MASK 0xffffffff
#define CPG_Debug2_WIDTH 32
#define CPG_Debug3 HW_REGISTER_RW( 0x7e21104c )
#define CPG_Debug3_MASK 0xffffffff
#define CPG_Debug3_WIDTH 32

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bcm2708_chip/cpi.h Executable file
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// This file was generated by the create_regs script
#define CPI_BASE 0x7e800000
#define CPI_APB_ID 0x20637069
#define CPI_CPIS HW_REGISTER_RW( 0x7e800000 )
#define CPI_CPIS_MASK 0xc0000007
#define CPI_CPIS_WIDTH 32
#define CPI_CPIS__MSB 31
#define CPI_CPIS__LSB 0
#define CPI_CPIR HW_REGISTER_RW( 0x7e800004 )
#define CPI_CPIR_MASK 0xffffffff
#define CPI_CPIR_WIDTH 32
#define CPI_CPIR__MSB 31
#define CPI_CPIR__LSB 0
#define CPI_CPIF HW_REGISTER_RW( 0x7e800008 )
#define CPI_CPIF_MASK 0xffffffff
#define CPI_CPIF_WIDTH 32
#define CPI_CPIF__MSB 31
#define CPI_CPIF__LSB 0
#define CPI_CPIW HW_REGISTER_RW( 0x7e80000c )
#define CPI_CPIW_MASK 0xffffffff
#define CPI_CPIW_WIDTH 32
#define CPI_CPIW__MSB 31
#define CPI_CPIW__LSB 0
#define CPI_CPIWVC HW_REGISTER_RW( 0x7e800010 )
#define CPI_CPIWVC_MASK 0xffffffff
#define CPI_CPIWVC_WIDTH 32
#define CPI_CPIWVC__MSB 31
#define CPI_CPIWVC__LSB 0
#define CPI_CPIWVS HW_REGISTER_RW( 0x7e800014 )
#define CPI_CPIWVS_MASK 0xffffffff
#define CPI_CPIWVS_WIDTH 32
#define CPI_CPIWVS__MSB 31
#define CPI_CPIWVS__LSB 0
#define CPI_CPIWHC HW_REGISTER_RW( 0x7e800018 )
#define CPI_CPIWHC_MASK 0xffffffff
#define CPI_CPIWHC_WIDTH 32
#define CPI_CPIWHC__MSB 31
#define CPI_CPIWHC__LSB 0
#define CPI_CPIWHS HW_REGISTER_RW( 0x7e80001c )
#define CPI_CPIWHS_MASK 0xffffffff
#define CPI_CPIWHS_WIDTH 32
#define CPI_CPIWHS__MSB 31
#define CPI_CPIWHS__LSB 0
#define CPI_CPIB HW_REGISTER_RW( 0x7e800020 )
#define CPI_CPIB_MASK 0xffffffff
#define CPI_CPIB_WIDTH 32
#define CPI_CPIB__MSB 31
#define CPI_CPIB__LSB 0

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bcm2708_chip/cpr_apb2wtap.h Executable file
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bcm2708_chip/cpr_apb2wtap_a0.h Executable file
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// This file was generated by the create_regs script
#define A2W_PASSWORD 0x5a000000
#define A2W_BASE 0x7e102000
#define A2W_APB_ID 0x00613277
#define A2W_PLLA_DIG0 HW_REGISTER_RW( 0x7e102000 )
#define A2W_PLLA_DIG0_MASK 0x00ffffff
#define A2W_PLLA_DIG0_WIDTH 24
#define A2W_PLLA_DIG0_RESET 0000000000
#define A2W_PLLA_DIG1 HW_REGISTER_RW( 0x7e102004 )
#define A2W_PLLA_DIG1_MASK 0x00ffffff
#define A2W_PLLA_DIG1_WIDTH 24
#define A2W_PLLA_DIG1_RESET 0000000000
#define A2W_PLLA_DIG2 HW_REGISTER_RW( 0x7e102008 )
#define A2W_PLLA_DIG2_MASK 0x00ffffff
#define A2W_PLLA_DIG2_WIDTH 24
#define A2W_PLLA_DIG2_RESET 0000000000
#define A2W_PLLA_DIG3 HW_REGISTER_RW( 0x7e10200c )
#define A2W_PLLA_DIG3_MASK 0x00ffffff
#define A2W_PLLA_DIG3_WIDTH 24
#define A2W_PLLA_DIG3_RESET 0000000000
#define A2W_PLLA_ANA0 HW_REGISTER_RW( 0x7e102010 )
#define A2W_PLLA_ANA0_MASK 0x00ffffff
#define A2W_PLLA_ANA0_WIDTH 24
#define A2W_PLLA_ANA0_RESET 0000000000
#define A2W_PLLA_ANA1 HW_REGISTER_RW( 0x7e102014 )
#define A2W_PLLA_ANA1_MASK 0x00ffffff
#define A2W_PLLA_ANA1_WIDTH 24
#define A2W_PLLA_ANA1_RESET 0000000000
#define A2W_PLLA_ANA2 HW_REGISTER_RW( 0x7e102018 )
#define A2W_PLLA_ANA2_MASK 0x00ffffff
#define A2W_PLLA_ANA2_WIDTH 24
#define A2W_PLLA_ANA2_RESET 0000000000
#define A2W_PLLA_ANA3 HW_REGISTER_RW( 0x7e10201c )
#define A2W_PLLA_ANA3_MASK 0x00ffffff
#define A2W_PLLA_ANA3_WIDTH 24
#define A2W_PLLA_ANA3_RESET 0000000000
#define A2W_PLLC_DIG0 HW_REGISTER_RW( 0x7e102020 )
#define A2W_PLLC_DIG0_MASK 0x00ffffff
#define A2W_PLLC_DIG0_WIDTH 24
#define A2W_PLLC_DIG0_RESET 0000000000
#define A2W_PLLC_DIG1 HW_REGISTER_RW( 0x7e102024 )
#define A2W_PLLC_DIG1_MASK 0x00ffffff
#define A2W_PLLC_DIG1_WIDTH 24
#define A2W_PLLC_DIG1_RESET 0000000000
#define A2W_PLLC_DIG2 HW_REGISTER_RW( 0x7e102028 )
#define A2W_PLLC_DIG2_MASK 0x00ffffff
#define A2W_PLLC_DIG2_WIDTH 24
#define A2W_PLLC_DIG2_RESET 0000000000
#define A2W_PLLC_DIG3 HW_REGISTER_RW( 0x7e10202c )
#define A2W_PLLC_DIG3_MASK 0x00ffffff
#define A2W_PLLC_DIG3_WIDTH 24
#define A2W_PLLC_DIG3_RESET 0000000000
#define A2W_PLLC_ANA0 HW_REGISTER_RW( 0x7e102030 )
#define A2W_PLLC_ANA0_MASK 0x00ffffff
#define A2W_PLLC_ANA0_WIDTH 24
#define A2W_PLLC_ANA0_RESET 0000000000
#define A2W_PLLC_ANA1 HW_REGISTER_RW( 0x7e102034 )
#define A2W_PLLC_ANA1_MASK 0x00ffffff
#define A2W_PLLC_ANA1_WIDTH 24
#define A2W_PLLC_ANA1_RESET 0000000000
#define A2W_PLLC_ANA2 HW_REGISTER_RW( 0x7e102038 )
#define A2W_PLLC_ANA2_MASK 0x00ffffff
#define A2W_PLLC_ANA2_WIDTH 24
#define A2W_PLLC_ANA2_RESET 0000000000
#define A2W_PLLC_ANA3 HW_REGISTER_RW( 0x7e10203c )
#define A2W_PLLC_ANA3_MASK 0x00ffffff
#define A2W_PLLC_ANA3_WIDTH 24
#define A2W_PLLC_ANA3_RESET 0000000000
#define A2W_PLLD_DIG0 HW_REGISTER_RW( 0x7e102040 )
#define A2W_PLLD_DIG0_MASK 0x00ffffff
#define A2W_PLLD_DIG0_WIDTH 24
#define A2W_PLLD_DIG0_RESET 0000000000
#define A2W_PLLD_DIG1 HW_REGISTER_RW( 0x7e102044 )
#define A2W_PLLD_DIG1_MASK 0x00ffffff
#define A2W_PLLD_DIG1_WIDTH 24
#define A2W_PLLD_DIG1_RESET 0000000000
#define A2W_PLLD_DIG2 HW_REGISTER_RW( 0x7e102048 )
#define A2W_PLLD_DIG2_MASK 0x00ffffff
#define A2W_PLLD_DIG2_WIDTH 24
#define A2W_PLLD_DIG2_RESET 0000000000
#define A2W_PLLD_DIG3 HW_REGISTER_RW( 0x7e10204c )
#define A2W_PLLD_DIG3_MASK 0x00ffffff
#define A2W_PLLD_DIG3_WIDTH 24
#define A2W_PLLD_DIG3_RESET 0000000000
#define A2W_PLLD_ANA0 HW_REGISTER_RW( 0x7e102050 )
#define A2W_PLLD_ANA0_MASK 0x00ffffff
#define A2W_PLLD_ANA0_WIDTH 24
#define A2W_PLLD_ANA0_RESET 0000000000
#define A2W_PLLD_ANA1 HW_REGISTER_RW( 0x7e102054 )
#define A2W_PLLD_ANA1_MASK 0x00ffffff
#define A2W_PLLD_ANA1_WIDTH 24
#define A2W_PLLD_ANA1_RESET 0000000000
#define A2W_PLLD_ANA2 HW_REGISTER_RW( 0x7e102058 )
#define A2W_PLLD_ANA2_MASK 0x00ffffff
#define A2W_PLLD_ANA2_WIDTH 24
#define A2W_PLLD_ANA2_RESET 0000000000
#define A2W_PLLD_ANA3 HW_REGISTER_RW( 0x7e10205c )
#define A2W_PLLD_ANA3_MASK 0x00ffffff
#define A2W_PLLD_ANA3_WIDTH 24
#define A2W_PLLD_ANA3_RESET 0000000000
#define A2W_PLLH_DIG0 HW_REGISTER_RW( 0x7e102060 )
#define A2W_PLLH_DIG0_MASK 0x00ffffff
#define A2W_PLLH_DIG0_WIDTH 24
#define A2W_PLLH_DIG0_RESET 0000000000
#define A2W_PLLH_DIG1 HW_REGISTER_RW( 0x7e102064 )
#define A2W_PLLH_DIG1_MASK 0x00ffffff
#define A2W_PLLH_DIG1_WIDTH 24
#define A2W_PLLH_DIG1_RESET 0000000000
#define A2W_PLLH_DIG2 HW_REGISTER_RW( 0x7e102068 )
#define A2W_PLLH_DIG2_MASK 0x00ffffff
#define A2W_PLLH_DIG2_WIDTH 24
#define A2W_PLLH_DIG2_RESET 0000000000
#define A2W_PLLH_DIG3 HW_REGISTER_RW( 0x7e10206c )
#define A2W_PLLH_DIG3_MASK 0x00ffffff
#define A2W_PLLH_DIG3_WIDTH 24
#define A2W_PLLH_DIG3_RESET 0000000000
#define A2W_PLLH_ANA0 HW_REGISTER_RW( 0x7e102070 )
#define A2W_PLLH_ANA0_MASK 0x00ffffff
#define A2W_PLLH_ANA0_WIDTH 24
#define A2W_PLLH_ANA0_RESET 0000000000
#define A2W_PLLH_ANA1 HW_REGISTER_RW( 0x7e102074 )
#define A2W_PLLH_ANA1_MASK 0x00ffffff
#define A2W_PLLH_ANA1_WIDTH 24
#define A2W_PLLH_ANA1_RESET 0000000000
#define A2W_PLLH_ANA2 HW_REGISTER_RW( 0x7e102078 )
#define A2W_PLLH_ANA2_MASK 0x00ffffff
#define A2W_PLLH_ANA2_WIDTH 24
#define A2W_PLLH_ANA2_RESET 0000000000
#define A2W_PLLH_ANA3 HW_REGISTER_RW( 0x7e10207c )
#define A2W_PLLH_ANA3_MASK 0x00ffffff
#define A2W_PLLH_ANA3_WIDTH 24
#define A2W_PLLH_ANA3_RESET 0000000000
#define A2W_HDMI_CTL0 HW_REGISTER_RW( 0x7e102080 )
#define A2W_HDMI_CTL0_MASK 0x00ffffff
#define A2W_HDMI_CTL0_WIDTH 24
#define A2W_HDMI_CTL0_RESET 0000000000
#define A2W_HDMI_CTL1 HW_REGISTER_RW( 0x7e102084 )
#define A2W_HDMI_CTL1_MASK 0x00ffffff
#define A2W_HDMI_CTL1_WIDTH 24
#define A2W_HDMI_CTL1_RESET 0000000000
#define A2W_HDMI_CTL2 HW_REGISTER_RW( 0x7e102088 )
#define A2W_HDMI_CTL2_MASK 0x00ffffff
#define A2W_HDMI_CTL2_WIDTH 24
#define A2W_HDMI_CTL2_RESET 0000000000
#define A2W_HDMI_CTL3 HW_REGISTER_RW( 0x7e10208c )
#define A2W_HDMI_CTL3_MASK 0x00ffffff
#define A2W_HDMI_CTL3_WIDTH 24
#define A2W_HDMI_CTL3_RESET 0000000000
#define A2W_XOSC0 HW_REGISTER_RW( 0x7e102090 )
#define A2W_XOSC0_MASK 0x00ffffff
#define A2W_XOSC0_WIDTH 24
#define A2W_XOSC0_RESET 0000000000
#define A2W_XOSC1 HW_REGISTER_RW( 0x7e102094 )
#define A2W_XOSC1_MASK 0x00ffffff
#define A2W_XOSC1_WIDTH 24
#define A2W_XOSC1_RESET 0000000000
#define A2W_SMPS_CTLA0 HW_REGISTER_RW( 0x7e1020a0 )
#define A2W_SMPS_CTLA0_MASK 0x00ffffff
#define A2W_SMPS_CTLA0_WIDTH 24
#define A2W_SMPS_CTLA0_RESET 0000000000
#define A2W_SMPS_CTLA1 HW_REGISTER_RW( 0x7e1020a4 )
#define A2W_SMPS_CTLA1_MASK 0x00ffffff
#define A2W_SMPS_CTLA1_WIDTH 24
#define A2W_SMPS_CTLA1_RESET 0000000000
#define A2W_SMPS_CTLA2 HW_REGISTER_RW( 0x7e1020a8 )
#define A2W_SMPS_CTLA2_MASK 0x00ffffff
#define A2W_SMPS_CTLA2_WIDTH 24
#define A2W_SMPS_CTLA2_RESET 0000000000
#define A2W_SMPS_CTLB0 HW_REGISTER_RW( 0x7e1020b0 )
#define A2W_SMPS_CTLB0_MASK 0x00ffffff
#define A2W_SMPS_CTLB0_WIDTH 24
#define A2W_SMPS_CTLB0_RESET 0000000000
#define A2W_SMPS_CTLB1 HW_REGISTER_RW( 0x7e1020b4 )
#define A2W_SMPS_CTLB1_MASK 0x00ffffff
#define A2W_SMPS_CTLB1_WIDTH 24
#define A2W_SMPS_CTLB1_RESET 0000000000
#define A2W_SMPS_CTLB2 HW_REGISTER_RW( 0x7e1020b8 )
#define A2W_SMPS_CTLB2_MASK 0x00ffffff
#define A2W_SMPS_CTLB2_WIDTH 24
#define A2W_SMPS_CTLB2_RESET 0000000000
#define A2W_SMPS_CTLC0 HW_REGISTER_RW( 0x7e1020c0 )
#define A2W_SMPS_CTLC0_MASK 0x00ffffff
#define A2W_SMPS_CTLC0_WIDTH 24
#define A2W_SMPS_CTLC0_RESET 0000000000
#define A2W_SMPS_CTLC1 HW_REGISTER_RW( 0x7e1020c4 )
#define A2W_SMPS_CTLC1_MASK 0x00ffffff
#define A2W_SMPS_CTLC1_WIDTH 24
#define A2W_SMPS_CTLC1_RESET 0000000000
#define A2W_SMPS_CTLC2 HW_REGISTER_RW( 0x7e1020c8 )
#define A2W_SMPS_CTLC2_MASK 0x00ffffff
#define A2W_SMPS_CTLC2_WIDTH 24
#define A2W_SMPS_CTLC2_RESET 0000000000
#define A2W_SMPS_CTLC3 HW_REGISTER_RW( 0x7e1020cc )
#define A2W_SMPS_CTLC3_MASK 0x00ffffff
#define A2W_SMPS_CTLC3_WIDTH 24
#define A2W_SMPS_CTLC3_RESET 0000000000
#define A2W_SMPS_LDO0 HW_REGISTER_RW( 0x7e1020d0 )
#define A2W_SMPS_LDO0_MASK 0x00ffffff
#define A2W_SMPS_LDO0_WIDTH 24
#define A2W_SMPS_LDO0_RESET 0000000000
#define A2W_SMPS_LDO1 HW_REGISTER_RW( 0x7e1020d4 )
#define A2W_SMPS_LDO1_MASK 0x00ffffff
#define A2W_SMPS_LDO1_WIDTH 24
#define A2W_SMPS_LDO1_RESET 0000000000
#define A2W_PLLA_CTRL HW_REGISTER_RW( 0x7e102100 )
#define A2W_PLLA_CTRL_MASK 0x000373ff
#define A2W_PLLA_CTRL_WIDTH 18
#define A2W_PLLA_CTRL_RESET 0000000000
#define A2W_PLLA_CTRL_PRSTN_BITS 17:17
#define A2W_PLLA_CTRL_PRSTN_SET 0x00020000
#define A2W_PLLA_CTRL_PRSTN_CLR 0xfffdffff
#define A2W_PLLA_CTRL_PRSTN_MSB 17
#define A2W_PLLA_CTRL_PRSTN_LSB 17
#define A2W_PLLA_CTRL_PWRDN_BITS 16:16
#define A2W_PLLA_CTRL_PWRDN_SET 0x00010000
#define A2W_PLLA_CTRL_PWRDN_CLR 0xfffeffff
#define A2W_PLLA_CTRL_PWRDN_MSB 16
#define A2W_PLLA_CTRL_PWRDN_LSB 16
#define A2W_PLLA_CTRL_PDIV_BITS 14:12
#define A2W_PLLA_CTRL_PDIV_SET 0x00007000
#define A2W_PLLA_CTRL_PDIV_CLR 0xffff8fff
#define A2W_PLLA_CTRL_PDIV_MSB 14
#define A2W_PLLA_CTRL_PDIV_LSB 12
#define A2W_PLLA_CTRL_NDIV_BITS 9:0
#define A2W_PLLA_CTRL_NDIV_SET 0x000003ff
#define A2W_PLLA_CTRL_NDIV_CLR 0xfffffc00
#define A2W_PLLA_CTRL_NDIV_MSB 9
#define A2W_PLLA_CTRL_NDIV_LSB 0
#define A2W_PLLA_FRAC HW_REGISTER_RW( 0x7e102200 )
#define A2W_PLLA_FRAC_MASK 0x000fffff
#define A2W_PLLA_FRAC_WIDTH 20
#define A2W_PLLA_FRAC_RESET 0000000000
#define A2W_PLLA_FRAC_FRAC_BITS 19:0
#define A2W_PLLA_FRAC_FRAC_SET 0x000fffff
#define A2W_PLLA_FRAC_FRAC_CLR 0xfff00000
#define A2W_PLLA_FRAC_FRAC_MSB 19
#define A2W_PLLA_FRAC_FRAC_LSB 0
#define A2W_PLLA_DSI0 HW_REGISTER_RW( 0x7e102300 )
#define A2W_PLLA_DSI0_MASK 0x000003ff
#define A2W_PLLA_DSI0_WIDTH 10
#define A2W_PLLA_DSI0_RESET 0000000000
#define A2W_PLLA_DSI0_BYPEN_BITS 9:9
#define A2W_PLLA_DSI0_BYPEN_SET 0x00000200
#define A2W_PLLA_DSI0_BYPEN_CLR 0xfffffdff
#define A2W_PLLA_DSI0_BYPEN_MSB 9
#define A2W_PLLA_DSI0_BYPEN_LSB 9
#define A2W_PLLA_DSI0_CHENB_BITS 8:8
#define A2W_PLLA_DSI0_CHENB_SET 0x00000100
#define A2W_PLLA_DSI0_CHENB_CLR 0xfffffeff
#define A2W_PLLA_DSI0_CHENB_MSB 8
#define A2W_PLLA_DSI0_CHENB_LSB 8
#define A2W_PLLA_DSI0_DIV_BITS 7:0
#define A2W_PLLA_DSI0_DIV_SET 0x000000ff
#define A2W_PLLA_DSI0_DIV_CLR 0xffffff00
#define A2W_PLLA_DSI0_DIV_MSB 7
#define A2W_PLLA_DSI0_DIV_LSB 0
#define A2W_PLLA_CORE HW_REGISTER_RW( 0x7e102400 )
#define A2W_PLLA_CORE_MASK 0x000003ff
#define A2W_PLLA_CORE_WIDTH 10
#define A2W_PLLA_CORE_RESET 0000000000
#define A2W_PLLA_CORE_BYPEN_BITS 9:9
#define A2W_PLLA_CORE_BYPEN_SET 0x00000200
#define A2W_PLLA_CORE_BYPEN_CLR 0xfffffdff
#define A2W_PLLA_CORE_BYPEN_MSB 9
#define A2W_PLLA_CORE_BYPEN_LSB 9
#define A2W_PLLA_CORE_CHENB_BITS 8:8
#define A2W_PLLA_CORE_CHENB_SET 0x00000100
#define A2W_PLLA_CORE_CHENB_CLR 0xfffffeff
#define A2W_PLLA_CORE_CHENB_MSB 8
#define A2W_PLLA_CORE_CHENB_LSB 8
#define A2W_PLLA_CORE_DIV_BITS 7:0
#define A2W_PLLA_CORE_DIV_SET 0x000000ff
#define A2W_PLLA_CORE_DIV_CLR 0xffffff00
#define A2W_PLLA_CORE_DIV_MSB 7
#define A2W_PLLA_CORE_DIV_LSB 0
#define A2W_PLLA_PER HW_REGISTER_RW( 0x7e102500 )
#define A2W_PLLA_PER_MASK 0x000003ff
#define A2W_PLLA_PER_WIDTH 10
#define A2W_PLLA_PER_RESET 0000000000
#define A2W_PLLA_PER_BYPEN_BITS 9:9
#define A2W_PLLA_PER_BYPEN_SET 0x00000200
#define A2W_PLLA_PER_BYPEN_CLR 0xfffffdff
#define A2W_PLLA_PER_BYPEN_MSB 9
#define A2W_PLLA_PER_BYPEN_LSB 9
#define A2W_PLLA_PER_CHENB_BITS 8:8
#define A2W_PLLA_PER_CHENB_SET 0x00000100
#define A2W_PLLA_PER_CHENB_CLR 0xfffffeff
#define A2W_PLLA_PER_CHENB_MSB 8
#define A2W_PLLA_PER_CHENB_LSB 8
#define A2W_PLLA_PER_DIV_BITS 7:0
#define A2W_PLLA_PER_DIV_SET 0x000000ff
#define A2W_PLLA_PER_DIV_CLR 0xffffff00
#define A2W_PLLA_PER_DIV_MSB 7
#define A2W_PLLA_PER_DIV_LSB 0
#define A2W_PLLA_CCP2 HW_REGISTER_RW( 0x7e102600 )
#define A2W_PLLA_CCP2_MASK 0x000003ff
#define A2W_PLLA_CCP2_WIDTH 10
#define A2W_PLLA_CCP2_RESET 0000000000
#define A2W_PLLA_CCP2_BYPEN_BITS 9:9
#define A2W_PLLA_CCP2_BYPEN_SET 0x00000200
#define A2W_PLLA_CCP2_BYPEN_CLR 0xfffffdff
#define A2W_PLLA_CCP2_BYPEN_MSB 9
#define A2W_PLLA_CCP2_BYPEN_LSB 9
#define A2W_PLLA_CCP2_CHENB_BITS 8:8
#define A2W_PLLA_CCP2_CHENB_SET 0x00000100
#define A2W_PLLA_CCP2_CHENB_CLR 0xfffffeff
#define A2W_PLLA_CCP2_CHENB_MSB 8
#define A2W_PLLA_CCP2_CHENB_LSB 8
#define A2W_PLLA_CCP2_DIV_BITS 7:0
#define A2W_PLLA_CCP2_DIV_SET 0x000000ff
#define A2W_PLLA_CCP2_DIV_CLR 0xffffff00
#define A2W_PLLA_CCP2_DIV_MSB 7
#define A2W_PLLA_CCP2_DIV_LSB 0
#define A2W_PLLC_CTRL HW_REGISTER_RW( 0x7e102120 )
#define A2W_PLLC_CTRL_MASK 0x000373ff
#define A2W_PLLC_CTRL_WIDTH 18
#define A2W_PLLC_CTRL_RESET 0000000000
#define A2W_PLLC_CTRL_PRSTN_BITS 17:17
#define A2W_PLLC_CTRL_PRSTN_SET 0x00020000
#define A2W_PLLC_CTRL_PRSTN_CLR 0xfffdffff
#define A2W_PLLC_CTRL_PRSTN_MSB 17
#define A2W_PLLC_CTRL_PRSTN_LSB 17
#define A2W_PLLC_CTRL_PWRDN_BITS 16:16
#define A2W_PLLC_CTRL_PWRDN_SET 0x00010000
#define A2W_PLLC_CTRL_PWRDN_CLR 0xfffeffff
#define A2W_PLLC_CTRL_PWRDN_MSB 16
#define A2W_PLLC_CTRL_PWRDN_LSB 16
#define A2W_PLLC_CTRL_PDIV_BITS 14:12
#define A2W_PLLC_CTRL_PDIV_SET 0x00007000
#define A2W_PLLC_CTRL_PDIV_CLR 0xffff8fff
#define A2W_PLLC_CTRL_PDIV_MSB 14
#define A2W_PLLC_CTRL_PDIV_LSB 12
#define A2W_PLLC_CTRL_NDIV_BITS 9:0
#define A2W_PLLC_CTRL_NDIV_SET 0x000003ff
#define A2W_PLLC_CTRL_NDIV_CLR 0xfffffc00
#define A2W_PLLC_CTRL_NDIV_MSB 9
#define A2W_PLLC_CTRL_NDIV_LSB 0
#define A2W_PLLC_FRAC HW_REGISTER_RW( 0x7e102220 )
#define A2W_PLLC_FRAC_MASK 0x000fffff
#define A2W_PLLC_FRAC_WIDTH 20
#define A2W_PLLC_FRAC_RESET 0000000000
#define A2W_PLLC_FRAC_FRAC_BITS 19:0
#define A2W_PLLC_FRAC_FRAC_SET 0x000fffff
#define A2W_PLLC_FRAC_FRAC_CLR 0xfff00000
#define A2W_PLLC_FRAC_FRAC_MSB 19
#define A2W_PLLC_FRAC_FRAC_LSB 0
#define A2W_PLLC_CORE2 HW_REGISTER_RW( 0x7e102320 )
#define A2W_PLLC_CORE2_MASK 0x000003ff
#define A2W_PLLC_CORE2_WIDTH 10
#define A2W_PLLC_CORE2_RESET 0000000000
#define A2W_PLLC_CORE2_BYPEN_BITS 9:9
#define A2W_PLLC_CORE2_BYPEN_SET 0x00000200
#define A2W_PLLC_CORE2_BYPEN_CLR 0xfffffdff
#define A2W_PLLC_CORE2_BYPEN_MSB 9
#define A2W_PLLC_CORE2_BYPEN_LSB 9
#define A2W_PLLC_CORE2_CHENB_BITS 8:8
#define A2W_PLLC_CORE2_CHENB_SET 0x00000100
#define A2W_PLLC_CORE2_CHENB_CLR 0xfffffeff
#define A2W_PLLC_CORE2_CHENB_MSB 8
#define A2W_PLLC_CORE2_CHENB_LSB 8
#define A2W_PLLC_CORE2_DIV_BITS 7:0
#define A2W_PLLC_CORE2_DIV_SET 0x000000ff
#define A2W_PLLC_CORE2_DIV_CLR 0xffffff00
#define A2W_PLLC_CORE2_DIV_MSB 7
#define A2W_PLLC_CORE2_DIV_LSB 0
#define A2W_PLLC_CORE1 HW_REGISTER_RW( 0x7e102420 )
#define A2W_PLLC_CORE1_MASK 0x000003ff
#define A2W_PLLC_CORE1_WIDTH 10
#define A2W_PLLC_CORE1_RESET 0000000000
#define A2W_PLLC_CORE1_BYPEN_BITS 9:9
#define A2W_PLLC_CORE1_BYPEN_SET 0x00000200
#define A2W_PLLC_CORE1_BYPEN_CLR 0xfffffdff
#define A2W_PLLC_CORE1_BYPEN_MSB 9
#define A2W_PLLC_CORE1_BYPEN_LSB 9
#define A2W_PLLC_CORE1_CHENB_BITS 8:8
#define A2W_PLLC_CORE1_CHENB_SET 0x00000100
#define A2W_PLLC_CORE1_CHENB_CLR 0xfffffeff
#define A2W_PLLC_CORE1_CHENB_MSB 8
#define A2W_PLLC_CORE1_CHENB_LSB 8
#define A2W_PLLC_CORE1_DIV_BITS 7:0
#define A2W_PLLC_CORE1_DIV_SET 0x000000ff
#define A2W_PLLC_CORE1_DIV_CLR 0xffffff00
#define A2W_PLLC_CORE1_DIV_MSB 7
#define A2W_PLLC_CORE1_DIV_LSB 0
#define A2W_PLLC_PER HW_REGISTER_RW( 0x7e102520 )
#define A2W_PLLC_PER_MASK 0x000003ff
#define A2W_PLLC_PER_WIDTH 10
#define A2W_PLLC_PER_RESET 0000000000
#define A2W_PLLC_PER_BYPEN_BITS 9:9
#define A2W_PLLC_PER_BYPEN_SET 0x00000200
#define A2W_PLLC_PER_BYPEN_CLR 0xfffffdff
#define A2W_PLLC_PER_BYPEN_MSB 9
#define A2W_PLLC_PER_BYPEN_LSB 9
#define A2W_PLLC_PER_CHENB_BITS 8:8
#define A2W_PLLC_PER_CHENB_SET 0x00000100
#define A2W_PLLC_PER_CHENB_CLR 0xfffffeff
#define A2W_PLLC_PER_CHENB_MSB 8
#define A2W_PLLC_PER_CHENB_LSB 8
#define A2W_PLLC_PER_DIV_BITS 7:0
#define A2W_PLLC_PER_DIV_SET 0x000000ff
#define A2W_PLLC_PER_DIV_CLR 0xffffff00
#define A2W_PLLC_PER_DIV_MSB 7
#define A2W_PLLC_PER_DIV_LSB 0
#define A2W_PLLC_CORE0 HW_REGISTER_RW( 0x7e102620 )
#define A2W_PLLC_CORE0_MASK 0x000003ff
#define A2W_PLLC_CORE0_WIDTH 10
#define A2W_PLLC_CORE0_RESET 0000000000
#define A2W_PLLC_CORE0_BYPEN_BITS 9:9
#define A2W_PLLC_CORE0_BYPEN_SET 0x00000200
#define A2W_PLLC_CORE0_BYPEN_CLR 0xfffffdff
#define A2W_PLLC_CORE0_BYPEN_MSB 9
#define A2W_PLLC_CORE0_BYPEN_LSB 9
#define A2W_PLLC_CORE0_CHENB_BITS 8:8
#define A2W_PLLC_CORE0_CHENB_SET 0x00000100
#define A2W_PLLC_CORE0_CHENB_CLR 0xfffffeff
#define A2W_PLLC_CORE0_CHENB_MSB 8
#define A2W_PLLC_CORE0_CHENB_LSB 8
#define A2W_PLLC_CORE0_DIV_BITS 7:0
#define A2W_PLLC_CORE0_DIV_SET 0x000000ff
#define A2W_PLLC_CORE0_DIV_CLR 0xffffff00
#define A2W_PLLC_CORE0_DIV_MSB 7
#define A2W_PLLC_CORE0_DIV_LSB 0
#define A2W_PLLD_CTRL HW_REGISTER_RW( 0x7e102140 )
#define A2W_PLLD_CTRL_MASK 0x000373ff
#define A2W_PLLD_CTRL_WIDTH 18
#define A2W_PLLD_CTRL_RESET 0000000000
#define A2W_PLLD_CTRL_PRSTN_BITS 17:17
#define A2W_PLLD_CTRL_PRSTN_SET 0x00020000
#define A2W_PLLD_CTRL_PRSTN_CLR 0xfffdffff
#define A2W_PLLD_CTRL_PRSTN_MSB 17
#define A2W_PLLD_CTRL_PRSTN_LSB 17
#define A2W_PLLD_CTRL_PWRDN_BITS 16:16
#define A2W_PLLD_CTRL_PWRDN_SET 0x00010000
#define A2W_PLLD_CTRL_PWRDN_CLR 0xfffeffff
#define A2W_PLLD_CTRL_PWRDN_MSB 16
#define A2W_PLLD_CTRL_PWRDN_LSB 16
#define A2W_PLLD_CTRL_PDIV_BITS 14:12
#define A2W_PLLD_CTRL_PDIV_SET 0x00007000
#define A2W_PLLD_CTRL_PDIV_CLR 0xffff8fff
#define A2W_PLLD_CTRL_PDIV_MSB 14
#define A2W_PLLD_CTRL_PDIV_LSB 12
#define A2W_PLLD_CTRL_NDIV_BITS 9:0
#define A2W_PLLD_CTRL_NDIV_SET 0x000003ff
#define A2W_PLLD_CTRL_NDIV_CLR 0xfffffc00
#define A2W_PLLD_CTRL_NDIV_MSB 9
#define A2W_PLLD_CTRL_NDIV_LSB 0
#define A2W_PLLD_FRAC HW_REGISTER_RW( 0x7e102240 )
#define A2W_PLLD_FRAC_MASK 0x000fffff
#define A2W_PLLD_FRAC_WIDTH 20
#define A2W_PLLD_FRAC_RESET 0000000000
#define A2W_PLLD_FRAC_FRAC_BITS 19:0
#define A2W_PLLD_FRAC_FRAC_SET 0x000fffff
#define A2W_PLLD_FRAC_FRAC_CLR 0xfff00000
#define A2W_PLLD_FRAC_FRAC_MSB 19
#define A2W_PLLD_FRAC_FRAC_LSB 0
#define A2W_PLLD_DSI0 HW_REGISTER_RW( 0x7e102340 )
#define A2W_PLLD_DSI0_MASK 0x000003ff
#define A2W_PLLD_DSI0_WIDTH 10
#define A2W_PLLD_DSI0_RESET 0000000000
#define A2W_PLLD_DSI0_BYPEN_BITS 9:9
#define A2W_PLLD_DSI0_BYPEN_SET 0x00000200
#define A2W_PLLD_DSI0_BYPEN_CLR 0xfffffdff
#define A2W_PLLD_DSI0_BYPEN_MSB 9
#define A2W_PLLD_DSI0_BYPEN_LSB 9
#define A2W_PLLD_DSI0_CHENB_BITS 8:8
#define A2W_PLLD_DSI0_CHENB_SET 0x00000100
#define A2W_PLLD_DSI0_CHENB_CLR 0xfffffeff
#define A2W_PLLD_DSI0_CHENB_MSB 8
#define A2W_PLLD_DSI0_CHENB_LSB 8
#define A2W_PLLD_DSI0_DIV_BITS 7:0
#define A2W_PLLD_DSI0_DIV_SET 0x000000ff
#define A2W_PLLD_DSI0_DIV_CLR 0xffffff00
#define A2W_PLLD_DSI0_DIV_MSB 7
#define A2W_PLLD_DSI0_DIV_LSB 0
#define A2W_PLLD_CORE HW_REGISTER_RW( 0x7e102440 )
#define A2W_PLLD_CORE_MASK 0x000003ff
#define A2W_PLLD_CORE_WIDTH 10
#define A2W_PLLD_CORE_RESET 0000000000
#define A2W_PLLD_CORE_BYPEN_BITS 9:9
#define A2W_PLLD_CORE_BYPEN_SET 0x00000200
#define A2W_PLLD_CORE_BYPEN_CLR 0xfffffdff
#define A2W_PLLD_CORE_BYPEN_MSB 9
#define A2W_PLLD_CORE_BYPEN_LSB 9
#define A2W_PLLD_CORE_CHENB_BITS 8:8
#define A2W_PLLD_CORE_CHENB_SET 0x00000100
#define A2W_PLLD_CORE_CHENB_CLR 0xfffffeff
#define A2W_PLLD_CORE_CHENB_MSB 8
#define A2W_PLLD_CORE_CHENB_LSB 8
#define A2W_PLLD_CORE_DIV_BITS 7:0
#define A2W_PLLD_CORE_DIV_SET 0x000000ff
#define A2W_PLLD_CORE_DIV_CLR 0xffffff00
#define A2W_PLLD_CORE_DIV_MSB 7
#define A2W_PLLD_CORE_DIV_LSB 0
#define A2W_PLLD_PER HW_REGISTER_RW( 0x7e102540 )
#define A2W_PLLD_PER_MASK 0x000003ff
#define A2W_PLLD_PER_WIDTH 10
#define A2W_PLLD_PER_RESET 0000000000
#define A2W_PLLD_PER_BYPEN_BITS 9:9
#define A2W_PLLD_PER_BYPEN_SET 0x00000200
#define A2W_PLLD_PER_BYPEN_CLR 0xfffffdff
#define A2W_PLLD_PER_BYPEN_MSB 9
#define A2W_PLLD_PER_BYPEN_LSB 9
#define A2W_PLLD_PER_CHENB_BITS 8:8
#define A2W_PLLD_PER_CHENB_SET 0x00000100
#define A2W_PLLD_PER_CHENB_CLR 0xfffffeff
#define A2W_PLLD_PER_CHENB_MSB 8
#define A2W_PLLD_PER_CHENB_LSB 8
#define A2W_PLLD_PER_DIV_BITS 7:0
#define A2W_PLLD_PER_DIV_SET 0x000000ff
#define A2W_PLLD_PER_DIV_CLR 0xffffff00
#define A2W_PLLD_PER_DIV_MSB 7
#define A2W_PLLD_PER_DIV_LSB 0
#define A2W_PLLD_DSI1 HW_REGISTER_RW( 0x7e102640 )
#define A2W_PLLD_DSI1_MASK 0x000003ff
#define A2W_PLLD_DSI1_WIDTH 10
#define A2W_PLLD_DSI1_RESET 0000000000
#define A2W_PLLD_DSI1_BYPEN_BITS 9:9
#define A2W_PLLD_DSI1_BYPEN_SET 0x00000200
#define A2W_PLLD_DSI1_BYPEN_CLR 0xfffffdff
#define A2W_PLLD_DSI1_BYPEN_MSB 9
#define A2W_PLLD_DSI1_BYPEN_LSB 9
#define A2W_PLLD_DSI1_CHENB_BITS 8:8
#define A2W_PLLD_DSI1_CHENB_SET 0x00000100
#define A2W_PLLD_DSI1_CHENB_CLR 0xfffffeff
#define A2W_PLLD_DSI1_CHENB_MSB 8
#define A2W_PLLD_DSI1_CHENB_LSB 8
#define A2W_PLLD_DSI1_DIV_BITS 7:0
#define A2W_PLLD_DSI1_DIV_SET 0x000000ff
#define A2W_PLLD_DSI1_DIV_CLR 0xffffff00
#define A2W_PLLD_DSI1_DIV_MSB 7
#define A2W_PLLD_DSI1_DIV_LSB 0
#define A2W_PLLH_CTRL HW_REGISTER_RW( 0x7e102160 )
#define A2W_PLLH_CTRL_MASK 0x000370ff
#define A2W_PLLH_CTRL_WIDTH 18
#define A2W_PLLH_CTRL_RESET 0000000000
#define A2W_PLLH_CTRL_PRSTN_BITS 17:17
#define A2W_PLLH_CTRL_PRSTN_SET 0x00020000
#define A2W_PLLH_CTRL_PRSTN_CLR 0xfffdffff
#define A2W_PLLH_CTRL_PRSTN_MSB 17
#define A2W_PLLH_CTRL_PRSTN_LSB 17
#define A2W_PLLH_CTRL_PWRDN_BITS 16:16
#define A2W_PLLH_CTRL_PWRDN_SET 0x00010000
#define A2W_PLLH_CTRL_PWRDN_CLR 0xfffeffff
#define A2W_PLLH_CTRL_PWRDN_MSB 16
#define A2W_PLLH_CTRL_PWRDN_LSB 16
#define A2W_PLLH_CTRL_PDIV_BITS 14:12
#define A2W_PLLH_CTRL_PDIV_SET 0x00007000
#define A2W_PLLH_CTRL_PDIV_CLR 0xffff8fff
#define A2W_PLLH_CTRL_PDIV_MSB 14
#define A2W_PLLH_CTRL_PDIV_LSB 12
#define A2W_PLLH_CTRL_NDIV_BITS 7:0
#define A2W_PLLH_CTRL_NDIV_SET 0x000000ff
#define A2W_PLLH_CTRL_NDIV_CLR 0xffffff00
#define A2W_PLLH_CTRL_NDIV_MSB 7
#define A2W_PLLH_CTRL_NDIV_LSB 0
#define A2W_PLLH_FRAC HW_REGISTER_RW( 0x7e102260 )
#define A2W_PLLH_FRAC_MASK 0x000fffff
#define A2W_PLLH_FRAC_WIDTH 20
#define A2W_PLLH_FRAC_RESET 0000000000
#define A2W_PLLH_FRAC_FRAC_BITS 19:0
#define A2W_PLLH_FRAC_FRAC_SET 0x000fffff
#define A2W_PLLH_FRAC_FRAC_CLR 0xfff00000
#define A2W_PLLH_FRAC_FRAC_MSB 19
#define A2W_PLLH_FRAC_FRAC_LSB 0
#define A2W_PLLH_AUX HW_REGISTER_RW( 0x7e102360 )
#define A2W_PLLH_AUX_MASK 0x000003ff
#define A2W_PLLH_AUX_WIDTH 10
#define A2W_PLLH_AUX_RESET 0000000000
#define A2W_PLLH_AUX_BYPEN_BITS 9:9
#define A2W_PLLH_AUX_BYPEN_SET 0x00000200
#define A2W_PLLH_AUX_BYPEN_CLR 0xfffffdff
#define A2W_PLLH_AUX_BYPEN_MSB 9
#define A2W_PLLH_AUX_BYPEN_LSB 9
#define A2W_PLLH_AUX_CHENB_BITS 8:8
#define A2W_PLLH_AUX_CHENB_SET 0x00000100
#define A2W_PLLH_AUX_CHENB_CLR 0xfffffeff
#define A2W_PLLH_AUX_CHENB_MSB 8
#define A2W_PLLH_AUX_CHENB_LSB 8
#define A2W_PLLH_AUX_DIV_BITS 7:0
#define A2W_PLLH_AUX_DIV_SET 0x000000ff
#define A2W_PLLH_AUX_DIV_CLR 0xffffff00
#define A2W_PLLH_AUX_DIV_MSB 7
#define A2W_PLLH_AUX_DIV_LSB 0
#define A2W_PLLH_RCAL HW_REGISTER_RW( 0x7e102460 )
#define A2W_PLLH_RCAL_MASK 0x000003ff
#define A2W_PLLH_RCAL_WIDTH 10
#define A2W_PLLH_RCAL_RESET 0000000000
#define A2W_PLLH_RCAL_BYPEN_BITS 9:9
#define A2W_PLLH_RCAL_BYPEN_SET 0x00000200
#define A2W_PLLH_RCAL_BYPEN_CLR 0xfffffdff
#define A2W_PLLH_RCAL_BYPEN_MSB 9
#define A2W_PLLH_RCAL_BYPEN_LSB 9
#define A2W_PLLH_RCAL_CHENB_BITS 8:8
#define A2W_PLLH_RCAL_CHENB_SET 0x00000100
#define A2W_PLLH_RCAL_CHENB_CLR 0xfffffeff
#define A2W_PLLH_RCAL_CHENB_MSB 8
#define A2W_PLLH_RCAL_CHENB_LSB 8
#define A2W_PLLH_RCAL_DIV_BITS 7:0
#define A2W_PLLH_RCAL_DIV_SET 0x000000ff
#define A2W_PLLH_RCAL_DIV_CLR 0xffffff00
#define A2W_PLLH_RCAL_DIV_MSB 7
#define A2W_PLLH_RCAL_DIV_LSB 0
#define A2W_PLLH_PIX HW_REGISTER_RW( 0x7e102560 )
#define A2W_PLLH_PIX_MASK 0x000003ff
#define A2W_PLLH_PIX_WIDTH 10
#define A2W_PLLH_PIX_RESET 0000000000
#define A2W_PLLH_PIX_BYPEN_BITS 9:9
#define A2W_PLLH_PIX_BYPEN_SET 0x00000200
#define A2W_PLLH_PIX_BYPEN_CLR 0xfffffdff
#define A2W_PLLH_PIX_BYPEN_MSB 9
#define A2W_PLLH_PIX_BYPEN_LSB 9
#define A2W_PLLH_PIX_CHENB_BITS 8:8
#define A2W_PLLH_PIX_CHENB_SET 0x00000100
#define A2W_PLLH_PIX_CHENB_CLR 0xfffffeff
#define A2W_PLLH_PIX_CHENB_MSB 8
#define A2W_PLLH_PIX_CHENB_LSB 8
#define A2W_PLLH_PIX_DIV_BITS 7:0
#define A2W_PLLH_PIX_DIV_SET 0x000000ff
#define A2W_PLLH_PIX_DIV_CLR 0xffffff00
#define A2W_PLLH_PIX_DIV_MSB 7
#define A2W_PLLH_PIX_DIV_LSB 0
#define A2W_PLLH_STS HW_REGISTER_RW( 0x7e102660 )
#define A2W_PLLH_STS_MASK 0xffffffff
#define A2W_PLLH_STS_WIDTH 32
#define A2W_PLLH_STS_RESET 0000000000
#define A2W_XOSC_CTRL HW_REGISTER_RW( 0x7e102190 )
#define A2W_XOSC_CTRL_MASK 0x0000037f
#define A2W_XOSC_CTRL_WIDTH 10
#define A2W_XOSC_CTRL_RESET 0000000000
#define A2W_XOSC_CTRL_DIV_BITS 9:8
#define A2W_XOSC_CTRL_DIV_SET 0x00000300
#define A2W_XOSC_CTRL_DIV_CLR 0xfffffcff
#define A2W_XOSC_CTRL_DIV_MSB 9
#define A2W_XOSC_CTRL_DIV_LSB 8
#define A2W_XOSC_CTRL_PLLAEN_BITS 6:6
#define A2W_XOSC_CTRL_PLLAEN_SET 0x00000040
#define A2W_XOSC_CTRL_PLLAEN_CLR 0xffffffbf
#define A2W_XOSC_CTRL_PLLAEN_MSB 6
#define A2W_XOSC_CTRL_PLLAEN_LSB 6
#define A2W_XOSC_CTRL_PLLDEN_BITS 5:5
#define A2W_XOSC_CTRL_PLLDEN_SET 0x00000020
#define A2W_XOSC_CTRL_PLLDEN_CLR 0xffffffdf
#define A2W_XOSC_CTRL_PLLDEN_MSB 5
#define A2W_XOSC_CTRL_PLLDEN_LSB 5
#define A2W_XOSC_CTRL_DDREN_BITS 4:4
#define A2W_XOSC_CTRL_DDREN_SET 0x00000010
#define A2W_XOSC_CTRL_DDREN_CLR 0xffffffef
#define A2W_XOSC_CTRL_DDREN_MSB 4
#define A2W_XOSC_CTRL_DDREN_LSB 4
#define A2W_XOSC_CTRL_CPR1EN_BITS 3:3
#define A2W_XOSC_CTRL_CPR1EN_SET 0x00000008
#define A2W_XOSC_CTRL_CPR1EN_CLR 0xfffffff7
#define A2W_XOSC_CTRL_CPR1EN_MSB 3
#define A2W_XOSC_CTRL_CPR1EN_LSB 3
#define A2W_XOSC_CTRL_USBEN_BITS 2:2
#define A2W_XOSC_CTRL_USBEN_SET 0x00000004
#define A2W_XOSC_CTRL_USBEN_CLR 0xfffffffb
#define A2W_XOSC_CTRL_USBEN_MSB 2
#define A2W_XOSC_CTRL_USBEN_LSB 2
#define A2W_XOSC_CTRL_HDMIEN_BITS 1:1
#define A2W_XOSC_CTRL_HDMIEN_SET 0x00000002
#define A2W_XOSC_CTRL_HDMIEN_CLR 0xfffffffd
#define A2W_XOSC_CTRL_HDMIEN_MSB 1
#define A2W_XOSC_CTRL_HDMIEN_LSB 1
#define A2W_XOSC_CTRL_PLLCEN_BITS 0:0
#define A2W_XOSC_CTRL_PLLCEN_SET 0x00000001
#define A2W_XOSC_CTRL_PLLCEN_CLR 0xfffffffe
#define A2W_XOSC_CTRL_PLLCEN_MSB 0
#define A2W_XOSC_CTRL_PLLCEN_LSB 0
#define A2W_PLLA_DIG0R HW_REGISTER_RW( 0x7e102800 )
#define A2W_PLLA_DIG0R_MASK 0x00ffffff
#define A2W_PLLA_DIG0R_WIDTH 24
#define A2W_PLLA_DIG0R_RESET 0000000000
#define A2W_PLLA_DIG1R HW_REGISTER_RW( 0x7e102804 )
#define A2W_PLLA_DIG1R_MASK 0x00ffffff
#define A2W_PLLA_DIG1R_WIDTH 24
#define A2W_PLLA_DIG1R_RESET 0000000000
#define A2W_PLLA_DIG2R HW_REGISTER_RW( 0x7e102808 )
#define A2W_PLLA_DIG2R_MASK 0x00ffffff
#define A2W_PLLA_DIG2R_WIDTH 24
#define A2W_PLLA_DIG2R_RESET 0000000000
#define A2W_PLLA_DIG3R HW_REGISTER_RW( 0x7e10280c )
#define A2W_PLLA_DIG3R_MASK 0x00ffffff
#define A2W_PLLA_DIG3R_WIDTH 24
#define A2W_PLLA_DIG3R_RESET 0000000000
#define A2W_PLLA_ANA0R HW_REGISTER_RW( 0x7e102810 )
#define A2W_PLLA_ANA0R_MASK 0x00ffffff
#define A2W_PLLA_ANA0R_WIDTH 24
#define A2W_PLLA_ANA0R_RESET 0000000000
#define A2W_PLLA_ANA1R HW_REGISTER_RW( 0x7e102814 )
#define A2W_PLLA_ANA1R_MASK 0x00ffffff
#define A2W_PLLA_ANA1R_WIDTH 24
#define A2W_PLLA_ANA1R_RESET 0000000000
#define A2W_PLLA_ANA2R HW_REGISTER_RW( 0x7e102818 )
#define A2W_PLLA_ANA2R_MASK 0x00ffffff
#define A2W_PLLA_ANA2R_WIDTH 24
#define A2W_PLLA_ANA2R_RESET 0000000000
#define A2W_PLLA_ANA3R HW_REGISTER_RW( 0x7e10281c )
#define A2W_PLLA_ANA3R_MASK 0x00ffffff
#define A2W_PLLA_ANA3R_WIDTH 24
#define A2W_PLLA_ANA3R_RESET 0000000000
#define A2W_PLLC_DIG0R HW_REGISTER_RW( 0x7e102820 )
#define A2W_PLLC_DIG0R_MASK 0x00ffffff
#define A2W_PLLC_DIG0R_WIDTH 24
#define A2W_PLLC_DIG0R_RESET 0000000000
#define A2W_PLLC_DIG1R HW_REGISTER_RW( 0x7e102824 )
#define A2W_PLLC_DIG1R_MASK 0x00ffffff
#define A2W_PLLC_DIG1R_WIDTH 24
#define A2W_PLLC_DIG1R_RESET 0000000000
#define A2W_PLLC_DIG2R HW_REGISTER_RW( 0x7e102828 )
#define A2W_PLLC_DIG2R_MASK 0x00ffffff
#define A2W_PLLC_DIG2R_WIDTH 24
#define A2W_PLLC_DIG2R_RESET 0000000000
#define A2W_PLLC_DIG3R HW_REGISTER_RW( 0x7e10282c )
#define A2W_PLLC_DIG3R_MASK 0x00ffffff
#define A2W_PLLC_DIG3R_WIDTH 24
#define A2W_PLLC_DIG3R_RESET 0000000000
#define A2W_PLLC_ANA0R HW_REGISTER_RW( 0x7e102830 )
#define A2W_PLLC_ANA0R_MASK 0x00ffffff
#define A2W_PLLC_ANA0R_WIDTH 24
#define A2W_PLLC_ANA0R_RESET 0000000000
#define A2W_PLLC_ANA1R HW_REGISTER_RW( 0x7e102834 )
#define A2W_PLLC_ANA1R_MASK 0x00ffffff
#define A2W_PLLC_ANA1R_WIDTH 24
#define A2W_PLLC_ANA1R_RESET 0000000000
#define A2W_PLLC_ANA2R HW_REGISTER_RW( 0x7e102838 )
#define A2W_PLLC_ANA2R_MASK 0x00ffffff
#define A2W_PLLC_ANA2R_WIDTH 24
#define A2W_PLLC_ANA2R_RESET 0000000000
#define A2W_PLLC_ANA3R HW_REGISTER_RW( 0x7e10283c )
#define A2W_PLLC_ANA3R_MASK 0x00ffffff
#define A2W_PLLC_ANA3R_WIDTH 24
#define A2W_PLLC_ANA3R_RESET 0000000000
#define A2W_PLLD_DIG0R HW_REGISTER_RW( 0x7e102840 )
#define A2W_PLLD_DIG0R_MASK 0x00ffffff
#define A2W_PLLD_DIG0R_WIDTH 24
#define A2W_PLLD_DIG0R_RESET 0000000000
#define A2W_PLLD_DIG1R HW_REGISTER_RW( 0x7e102844 )
#define A2W_PLLD_DIG1R_MASK 0x00ffffff
#define A2W_PLLD_DIG1R_WIDTH 24
#define A2W_PLLD_DIG1R_RESET 0000000000
#define A2W_PLLD_DIG2R HW_REGISTER_RW( 0x7e102848 )
#define A2W_PLLD_DIG2R_MASK 0x00ffffff
#define A2W_PLLD_DIG2R_WIDTH 24
#define A2W_PLLD_DIG2R_RESET 0000000000
#define A2W_PLLD_DIG3R HW_REGISTER_RW( 0x7e10284c )
#define A2W_PLLD_DIG3R_MASK 0x00ffffff
#define A2W_PLLD_DIG3R_WIDTH 24
#define A2W_PLLD_DIG3R_RESET 0000000000
#define A2W_PLLD_ANA0R HW_REGISTER_RW( 0x7e102850 )
#define A2W_PLLD_ANA0R_MASK 0x00ffffff
#define A2W_PLLD_ANA0R_WIDTH 24
#define A2W_PLLD_ANA0R_RESET 0000000000
#define A2W_PLLD_ANA1R HW_REGISTER_RW( 0x7e102854 )
#define A2W_PLLD_ANA1R_MASK 0x00ffffff
#define A2W_PLLD_ANA1R_WIDTH 24
#define A2W_PLLD_ANA1R_RESET 0000000000
#define A2W_PLLD_ANA2R HW_REGISTER_RW( 0x7e102858 )
#define A2W_PLLD_ANA2R_MASK 0x00ffffff
#define A2W_PLLD_ANA2R_WIDTH 24
#define A2W_PLLD_ANA2R_RESET 0000000000
#define A2W_PLLD_ANA3R HW_REGISTER_RW( 0x7e10285c )
#define A2W_PLLD_ANA3R_MASK 0x00ffffff
#define A2W_PLLD_ANA3R_WIDTH 24
#define A2W_PLLD_ANA3R_RESET 0000000000
#define A2W_PLLH_DIG0R HW_REGISTER_RW( 0x7e102860 )
#define A2W_PLLH_DIG0R_MASK 0x00ffffff
#define A2W_PLLH_DIG0R_WIDTH 24
#define A2W_PLLH_DIG0R_RESET 0000000000
#define A2W_PLLH_DIG1R HW_REGISTER_RW( 0x7e102864 )
#define A2W_PLLH_DIG1R_MASK 0x00ffffff
#define A2W_PLLH_DIG1R_WIDTH 24
#define A2W_PLLH_DIG1R_RESET 0000000000
#define A2W_PLLH_DIG2R HW_REGISTER_RW( 0x7e102868 )
#define A2W_PLLH_DIG2R_MASK 0x00ffffff
#define A2W_PLLH_DIG2R_WIDTH 24
#define A2W_PLLH_DIG2R_RESET 0000000000
#define A2W_PLLH_DIG3R HW_REGISTER_RW( 0x7e10286c )
#define A2W_PLLH_DIG3R_MASK 0x00ffffff
#define A2W_PLLH_DIG3R_WIDTH 24
#define A2W_PLLH_DIG3R_RESET 0000000000
#define A2W_PLLH_ANA0R HW_REGISTER_RW( 0x7e102870 )
#define A2W_PLLH_ANA0R_MASK 0x00ffffff
#define A2W_PLLH_ANA0R_WIDTH 24
#define A2W_PLLH_ANA0R_RESET 0000000000
#define A2W_PLLH_ANA1R HW_REGISTER_RW( 0x7e102874 )
#define A2W_PLLH_ANA1R_MASK 0x00ffffff
#define A2W_PLLH_ANA1R_WIDTH 24
#define A2W_PLLH_ANA1R_RESET 0000000000
#define A2W_PLLH_ANA2R HW_REGISTER_RW( 0x7e102878 )
#define A2W_PLLH_ANA2R_MASK 0x00ffffff
#define A2W_PLLH_ANA2R_WIDTH 24
#define A2W_PLLH_ANA2R_RESET 0000000000
#define A2W_PLLH_ANA3R HW_REGISTER_RW( 0x7e10287c )
#define A2W_PLLH_ANA3R_MASK 0x00ffffff
#define A2W_PLLH_ANA3R_WIDTH 24
#define A2W_PLLH_ANA3R_RESET 0000000000
#define A2W_HDMI_CTL0R HW_REGISTER_RW( 0x7e102880 )
#define A2W_HDMI_CTL0R_MASK 0x00ffffff
#define A2W_HDMI_CTL0R_WIDTH 24
#define A2W_HDMI_CTL0R_RESET 0000000000
#define A2W_HDMI_CTL1R HW_REGISTER_RW( 0x7e102884 )
#define A2W_HDMI_CTL1R_MASK 0x00ffffff
#define A2W_HDMI_CTL1R_WIDTH 24
#define A2W_HDMI_CTL1R_RESET 0000000000
#define A2W_HDMI_CTL2R HW_REGISTER_RW( 0x7e102888 )
#define A2W_HDMI_CTL2R_MASK 0x00ffffff
#define A2W_HDMI_CTL2R_WIDTH 24
#define A2W_HDMI_CTL2R_RESET 0000000000
#define A2W_HDMI_CTL3R HW_REGISTER_RW( 0x7e10288c )
#define A2W_HDMI_CTL3R_MASK 0x00ffffff
#define A2W_HDMI_CTL3R_WIDTH 24
#define A2W_HDMI_CTL3R_RESET 0000000000
#define A2W_XOSC0R HW_REGISTER_RW( 0x7e102890 )
#define A2W_XOSC0R_MASK 0x00ffffff
#define A2W_XOSC0R_WIDTH 24
#define A2W_XOSC0R_RESET 0000000000
#define A2W_XOSC1R HW_REGISTER_RW( 0x7e102894 )
#define A2W_XOSC1R_MASK 0x00ffffff
#define A2W_XOSC1R_WIDTH 24
#define A2W_XOSC1R_RESET 0000000000
#define A2W_SMPS_CTLA0R HW_REGISTER_RW( 0x7e1028a0 )
#define A2W_SMPS_CTLA0R_MASK 0x00ffffff
#define A2W_SMPS_CTLA0R_WIDTH 24
#define A2W_SMPS_CTLA0R_RESET 0000000000
#define A2W_SMPS_CTLA1R HW_REGISTER_RW( 0x7e1028a4 )
#define A2W_SMPS_CTLA1R_MASK 0x00ffffff
#define A2W_SMPS_CTLA1R_WIDTH 24
#define A2W_SMPS_CTLA1R_RESET 0000000000
#define A2W_SMPS_CTLA2R HW_REGISTER_RW( 0x7e1028a8 )
#define A2W_SMPS_CTLA2R_MASK 0x00ffffff
#define A2W_SMPS_CTLA2R_WIDTH 24
#define A2W_SMPS_CTLA2R_RESET 0000000000
#define A2W_SMPS_CTLB0R HW_REGISTER_RW( 0x7e1028b0 )
#define A2W_SMPS_CTLB0R_MASK 0x00ffffff
#define A2W_SMPS_CTLB0R_WIDTH 24
#define A2W_SMPS_CTLB0R_RESET 0000000000
#define A2W_SMPS_CTLB1R HW_REGISTER_RW( 0x7e1028b4 )
#define A2W_SMPS_CTLB1R_MASK 0x00ffffff
#define A2W_SMPS_CTLB1R_WIDTH 24
#define A2W_SMPS_CTLB1R_RESET 0000000000
#define A2W_SMPS_CTLB2R HW_REGISTER_RW( 0x7e1028b8 )
#define A2W_SMPS_CTLB2R_MASK 0x00ffffff
#define A2W_SMPS_CTLB2R_WIDTH 24
#define A2W_SMPS_CTLB2R_RESET 0000000000
#define A2W_SMPS_CTLC0R HW_REGISTER_RW( 0x7e1028c0 )
#define A2W_SMPS_CTLC0R_MASK 0x00ffffff
#define A2W_SMPS_CTLC0R_WIDTH 24
#define A2W_SMPS_CTLC0R_RESET 0000000000
#define A2W_SMPS_CTLC1R HW_REGISTER_RW( 0x7e1028c4 )
#define A2W_SMPS_CTLC1R_MASK 0x00ffffff
#define A2W_SMPS_CTLC1R_WIDTH 24
#define A2W_SMPS_CTLC1R_RESET 0000000000
#define A2W_SMPS_CTLC2R HW_REGISTER_RW( 0x7e1028c8 )
#define A2W_SMPS_CTLC2R_MASK 0x00ffffff
#define A2W_SMPS_CTLC2R_WIDTH 24
#define A2W_SMPS_CTLC2R_RESET 0000000000
#define A2W_SMPS_CTLC3R HW_REGISTER_RW( 0x7e1028cc )
#define A2W_SMPS_CTLC3R_MASK 0x00ffffff
#define A2W_SMPS_CTLC3R_WIDTH 24
#define A2W_SMPS_CTLC3R_RESET 0000000000
#define A2W_SMPS_LDO0R HW_REGISTER_RW( 0x7e1028d0 )
#define A2W_SMPS_LDO0R_MASK 0x00ffffff
#define A2W_SMPS_LDO0R_WIDTH 24
#define A2W_SMPS_LDO0R_RESET 0000000000
#define A2W_SMPS_LDO1R HW_REGISTER_RW( 0x7e1028d4 )
#define A2W_SMPS_LDO1R_MASK 0x00ffffff
#define A2W_SMPS_LDO1R_WIDTH 24
#define A2W_SMPS_LDO1R_RESET 0000000000
#define A2W_PLLA_CTRLR HW_REGISTER_RW( 0x7e102900 )
#define A2W_PLLA_CTRLR_MASK 0x000373ff
#define A2W_PLLA_CTRLR_WIDTH 18
#define A2W_PLLA_CTRLR_RESET 0000000000
#define A2W_PLLA_FRACR HW_REGISTER_RW( 0x7e102a00 )
#define A2W_PLLA_FRACR_MASK 0x000fffff
#define A2W_PLLA_FRACR_WIDTH 20
#define A2W_PLLA_FRACR_RESET 0000000000
#define A2W_PLLA_DSI0R HW_REGISTER_RW( 0x7e102b00 )
#define A2W_PLLA_DSI0R_MASK 0x000003ff
#define A2W_PLLA_DSI0R_WIDTH 10
#define A2W_PLLA_DSI0R_RESET 0000000000
#define A2W_PLLA_CORER HW_REGISTER_RW( 0x7e102c00 )
#define A2W_PLLA_CORER_MASK 0x000003ff
#define A2W_PLLA_CORER_WIDTH 10
#define A2W_PLLA_CORER_RESET 0000000000
#define A2W_PLLA_PERR HW_REGISTER_RW( 0x7e102d00 )
#define A2W_PLLA_PERR_MASK 0x000003ff
#define A2W_PLLA_PERR_WIDTH 10
#define A2W_PLLA_PERR_RESET 0000000000
#define A2W_PLLA_CCP2R HW_REGISTER_RW( 0x7e102e00 )
#define A2W_PLLA_CCP2R_MASK 0x000003ff
#define A2W_PLLA_CCP2R_WIDTH 10
#define A2W_PLLA_CCP2R_RESET 0000000000
#define A2W_PLLA_MULTI HW_REGISTER_RW( 0x7e102f00 )
#define A2W_PLLA_MULTI_MASK 0000000000
#define A2W_PLLA_MULTI_WIDTH 0
#define A2W_PLLA_MULTI_RESET 0000000000
#define A2W_PLLC_CTRLR HW_REGISTER_RW( 0x7e102920 )
#define A2W_PLLC_CTRLR_MASK 0x000373ff
#define A2W_PLLC_CTRLR_WIDTH 18
#define A2W_PLLC_CTRLR_RESET 0000000000
#define A2W_PLLC_FRACR HW_REGISTER_RW( 0x7e102a20 )
#define A2W_PLLC_FRACR_MASK 0x000fffff
#define A2W_PLLC_FRACR_WIDTH 20
#define A2W_PLLC_FRACR_RESET 0000000000
#define A2W_PLLC_CORE2R HW_REGISTER_RW( 0x7e102b20 )
#define A2W_PLLC_CORE2R_MASK 0x000003ff
#define A2W_PLLC_CORE2R_WIDTH 10
#define A2W_PLLC_CORE2R_RESET 0000000000
#define A2W_PLLC_CORE1R HW_REGISTER_RW( 0x7e102c20 )
#define A2W_PLLC_CORE1R_MASK 0x000003ff
#define A2W_PLLC_CORE1R_WIDTH 10
#define A2W_PLLC_CORE1R_RESET 0000000000
#define A2W_PLLC_PERR HW_REGISTER_RW( 0x7e102d20 )
#define A2W_PLLC_PERR_MASK 0x000003ff
#define A2W_PLLC_PERR_WIDTH 10
#define A2W_PLLC_PERR_RESET 0000000000
#define A2W_PLLC_CORE0R HW_REGISTER_RW( 0x7e102e20 )
#define A2W_PLLC_CORE0R_MASK 0x000003ff
#define A2W_PLLC_CORE0R_WIDTH 10
#define A2W_PLLC_CORE0R_RESET 0000000000
#define A2W_PLLC_MULTI HW_REGISTER_RW( 0x7e102f20 )
#define A2W_PLLC_MULTI_MASK 0000000000
#define A2W_PLLC_MULTI_WIDTH 0
#define A2W_PLLC_MULTI_RESET 0000000000
#define A2W_PLLD_CTRLR HW_REGISTER_RW( 0x7e102940 )
#define A2W_PLLD_CTRLR_MASK 0x000373ff
#define A2W_PLLD_CTRLR_WIDTH 18
#define A2W_PLLD_CTRLR_RESET 0000000000
#define A2W_PLLD_FRACR HW_REGISTER_RW( 0x7e102a40 )
#define A2W_PLLD_FRACR_MASK 0x000fffff
#define A2W_PLLD_FRACR_WIDTH 20
#define A2W_PLLD_FRACR_RESET 0000000000
#define A2W_PLLD_DSI0R HW_REGISTER_RW( 0x7e102b40 )
#define A2W_PLLD_DSI0R_MASK 0x000003ff
#define A2W_PLLD_DSI0R_WIDTH 10
#define A2W_PLLD_DSI0R_RESET 0000000000
#define A2W_PLLD_CORER HW_REGISTER_RW( 0x7e102c40 )
#define A2W_PLLD_CORER_MASK 0x000003ff
#define A2W_PLLD_CORER_WIDTH 10
#define A2W_PLLD_CORER_RESET 0000000000
#define A2W_PLLD_PERR HW_REGISTER_RW( 0x7e102d40 )
#define A2W_PLLD_PERR_MASK 0x000003ff
#define A2W_PLLD_PERR_WIDTH 10
#define A2W_PLLD_PERR_RESET 0000000000
#define A2W_PLLD_DSI1R HW_REGISTER_RW( 0x7e102e40 )
#define A2W_PLLD_DSI1R_MASK 0x000003ff
#define A2W_PLLD_DSI1R_WIDTH 10
#define A2W_PLLD_DSI1R_RESET 0000000000
#define A2W_PLLD_MULTI HW_REGISTER_RW( 0x7e102f40 )
#define A2W_PLLD_MULTI_MASK 0000000000
#define A2W_PLLD_MULTI_WIDTH 0
#define A2W_PLLD_MULTI_RESET 0000000000
#define A2W_PLLH_CTRLR HW_REGISTER_RW( 0x7e102960 )
#define A2W_PLLH_CTRLR_MASK 0x000370ff
#define A2W_PLLH_CTRLR_WIDTH 18
#define A2W_PLLH_CTRLR_RESET 0000000000
#define A2W_PLLH_FRACR HW_REGISTER_RW( 0x7e102a60 )
#define A2W_PLLH_FRACR_MASK 0x000fffff
#define A2W_PLLH_FRACR_WIDTH 20
#define A2W_PLLH_FRACR_RESET 0000000000
#define A2W_PLLH_AUXR HW_REGISTER_RW( 0x7e102b60 )
#define A2W_PLLH_AUXR_MASK 0x000003ff
#define A2W_PLLH_AUXR_WIDTH 10
#define A2W_PLLH_AUXR_RESET 0000000000
#define A2W_PLLH_RCALR HW_REGISTER_RW( 0x7e102c60 )
#define A2W_PLLH_RCALR_MASK 0x000003ff
#define A2W_PLLH_RCALR_WIDTH 10
#define A2W_PLLH_RCALR_RESET 0000000000
#define A2W_PLLH_PIXR HW_REGISTER_RW( 0x7e102d60 )
#define A2W_PLLH_PIXR_MASK 0x000003ff
#define A2W_PLLH_PIXR_WIDTH 10
#define A2W_PLLH_PIXR_RESET 0000000000
#define A2W_PLLH_STSR HW_REGISTER_RW( 0x7e102e60 )
#define A2W_PLLH_STSR_MASK 0xffffffff
#define A2W_PLLH_STSR_WIDTH 32
#define A2W_PLLH_STSR_RESET 0000000000
#define A2W_XOSC_CTRLR HW_REGISTER_RW( 0x7e102990 )
#define A2W_XOSC_CTRLR_MASK 0x0000037f
#define A2W_XOSC_CTRLR_WIDTH 10
#define A2W_XOSC_CTRLR_RESET 0000000000
#define A2W_PLLH_MULTI HW_REGISTER_RW( 0x7e102f60 )
#define A2W_PLLH_MULTI_MASK 0000000000
#define A2W_PLLH_MULTI_WIDTH 0
#define A2W_PLLH_MULTI_RESET 0000000000

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bcm2708_chip/cpr_clkman.h Executable file
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bcm2708_chip/cpr_clkman_a0.h Executable file
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bcm2708_chip/cpr_powman.h Executable file
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// This file was generated by the create_regs script
#define PM_PASSWORD 0x5a000000
#define PM_BASE 0x7e100000
#define PM_APB_ID 0x0000706d
#define PM_GNRIC HW_REGISTER_RW( 0x7e100000 )
#define PM_GNRIC_MASK 0x007f1fff
#define PM_GNRIC_WIDTH 23
#define PM_GNRIC_RESET 0000000000
#define PM_GNRIC_CFG_BITS 22:16
#define PM_GNRIC_CFG_SET 0x007f0000
#define PM_GNRIC_CFG_CLR 0xff80ffff
#define PM_GNRIC_CFG_MSB 22
#define PM_GNRIC_CFG_LSB 16
#define PM_GNRIC_ENAB_BITS 12:12
#define PM_GNRIC_ENAB_SET 0x00001000
#define PM_GNRIC_ENAB_CLR 0xffffefff
#define PM_GNRIC_ENAB_MSB 12
#define PM_GNRIC_ENAB_LSB 12
#define PM_GNRIC_RSTN_BITS 11:6
#define PM_GNRIC_RSTN_SET 0x00000fc0
#define PM_GNRIC_RSTN_CLR 0xfffff03f
#define PM_GNRIC_RSTN_MSB 11
#define PM_GNRIC_RSTN_LSB 6
#define PM_GNRIC_ISFUNC_BITS 5:5
#define PM_GNRIC_ISFUNC_SET 0x00000020
#define PM_GNRIC_ISFUNC_CLR 0xffffffdf
#define PM_GNRIC_ISFUNC_MSB 5
#define PM_GNRIC_ISFUNC_LSB 5
#define PM_GNRIC_MRDONE_BITS 4:4
#define PM_GNRIC_MRDONE_SET 0x00000010
#define PM_GNRIC_MRDONE_CLR 0xffffffef
#define PM_GNRIC_MRDONE_MSB 4
#define PM_GNRIC_MRDONE_LSB 4
#define PM_GNRIC_MEMREP_BITS 3:3
#define PM_GNRIC_MEMREP_SET 0x00000008
#define PM_GNRIC_MEMREP_CLR 0xfffffff7
#define PM_GNRIC_MEMREP_MSB 3
#define PM_GNRIC_MEMREP_LSB 3
#define PM_GNRIC_ISPOW_BITS 2:2
#define PM_GNRIC_ISPOW_SET 0x00000004
#define PM_GNRIC_ISPOW_CLR 0xfffffffb
#define PM_GNRIC_ISPOW_MSB 2
#define PM_GNRIC_ISPOW_LSB 2
#define PM_GNRIC_POWOK_BITS 1:1
#define PM_GNRIC_POWOK_SET 0x00000002
#define PM_GNRIC_POWOK_CLR 0xfffffffd
#define PM_GNRIC_POWOK_MSB 1
#define PM_GNRIC_POWOK_LSB 1
#define PM_GNRIC_POWUP_BITS 0:0
#define PM_GNRIC_POWUP_SET 0x00000001
#define PM_GNRIC_POWUP_CLR 0xfffffffe
#define PM_GNRIC_POWUP_MSB 0
#define PM_GNRIC_POWUP_LSB 0
#define PM_AUDIO HW_REGISTER_RW( 0x7e100004 )
#define PM_AUDIO_MASK 0x003fffff
#define PM_AUDIO_WIDTH 22
#define PM_AUDIO_RESET 0x003000ff
#define PM_AUDIO_RSTN_BITS 21:21
#define PM_AUDIO_RSTN_SET 0x00200000
#define PM_AUDIO_RSTN_CLR 0xffdfffff
#define PM_AUDIO_RSTN_MSB 21
#define PM_AUDIO_RSTN_LSB 21
#define PM_AUDIO_CTRLEN_BITS 20:20
#define PM_AUDIO_CTRLEN_SET 0x00100000
#define PM_AUDIO_CTRLEN_CLR 0xffefffff
#define PM_AUDIO_CTRLEN_MSB 20
#define PM_AUDIO_CTRLEN_LSB 20
#define PM_AUDIO_APSM_BITS 19:0
#define PM_AUDIO_APSM_SET 0x000fffff
#define PM_AUDIO_APSM_CLR 0xfff00000
#define PM_AUDIO_APSM_MSB 19
#define PM_AUDIO_APSM_LSB 0
#define PM_STATUS HW_REGISTER_RO( 0x7e100018 )
#define PM_STATUS_MASK 0x00ffffff
#define PM_STATUS_WIDTH 24
#define PM_STATUS_RESET 0000000000
#define PM_IMAGE HW_REGISTER_RW( 0x7e100108 )
#define PM_IMAGE_MASK 0x007f11ff
#define PM_IMAGE_WIDTH 23
#define PM_IMAGE_RESET 0x00001000
#define PM_IMAGE_CFG_BITS 22:16
#define PM_IMAGE_CFG_SET 0x007f0000
#define PM_IMAGE_CFG_CLR 0xff80ffff
#define PM_IMAGE_CFG_MSB 22
#define PM_IMAGE_CFG_LSB 16
#define PM_IMAGE_ENAB_BITS 12:12
#define PM_IMAGE_ENAB_SET 0x00001000
#define PM_IMAGE_ENAB_CLR 0xffffefff
#define PM_IMAGE_ENAB_MSB 12
#define PM_IMAGE_ENAB_LSB 12
#define PM_IMAGE_ISPRSTN_BITS 8:8
#define PM_IMAGE_ISPRSTN_SET 0x00000100
#define PM_IMAGE_ISPRSTN_CLR 0xfffffeff
#define PM_IMAGE_ISPRSTN_MSB 8
#define PM_IMAGE_ISPRSTN_LSB 8
#define PM_IMAGE_H264RSTN_BITS 7:7
#define PM_IMAGE_H264RSTN_SET 0x00000080
#define PM_IMAGE_H264RSTN_CLR 0xffffff7f
#define PM_IMAGE_H264RSTN_MSB 7
#define PM_IMAGE_H264RSTN_LSB 7
#define PM_IMAGE_PERIRSTN_BITS 6:6
#define PM_IMAGE_PERIRSTN_SET 0x00000040
#define PM_IMAGE_PERIRSTN_CLR 0xffffffbf
#define PM_IMAGE_PERIRSTN_MSB 6
#define PM_IMAGE_PERIRSTN_LSB 6
#define PM_IMAGE_ISFUNC_BITS 5:5
#define PM_IMAGE_ISFUNC_SET 0x00000020
#define PM_IMAGE_ISFUNC_CLR 0xffffffdf
#define PM_IMAGE_ISFUNC_MSB 5
#define PM_IMAGE_ISFUNC_LSB 5
#define PM_IMAGE_MRDONE_BITS 4:4
#define PM_IMAGE_MRDONE_SET 0x00000010
#define PM_IMAGE_MRDONE_CLR 0xffffffef
#define PM_IMAGE_MRDONE_MSB 4
#define PM_IMAGE_MRDONE_LSB 4
#define PM_IMAGE_MEMREP_BITS 3:3
#define PM_IMAGE_MEMREP_SET 0x00000008
#define PM_IMAGE_MEMREP_CLR 0xfffffff7
#define PM_IMAGE_MEMREP_MSB 3
#define PM_IMAGE_MEMREP_LSB 3
#define PM_IMAGE_ISPOW_BITS 2:2
#define PM_IMAGE_ISPOW_SET 0x00000004
#define PM_IMAGE_ISPOW_CLR 0xfffffffb
#define PM_IMAGE_ISPOW_MSB 2
#define PM_IMAGE_ISPOW_LSB 2
#define PM_IMAGE_POWOK_BITS 1:1
#define PM_IMAGE_POWOK_SET 0x00000002
#define PM_IMAGE_POWOK_CLR 0xfffffffd
#define PM_IMAGE_POWOK_MSB 1
#define PM_IMAGE_POWOK_LSB 1
#define PM_IMAGE_POWUP_BITS 0:0
#define PM_IMAGE_POWUP_SET 0x00000001
#define PM_IMAGE_POWUP_CLR 0xfffffffe
#define PM_IMAGE_POWUP_MSB 0
#define PM_IMAGE_POWUP_LSB 0
#define PM_GRAFX HW_REGISTER_RW( 0x7e10010c )
#define PM_GRAFX_MASK 0x007f107f
#define PM_GRAFX_WIDTH 23
#define PM_GRAFX_RESET 0x00001000
#define PM_GRAFX_CFG_BITS 22:16
#define PM_GRAFX_CFG_SET 0x007f0000
#define PM_GRAFX_CFG_CLR 0xff80ffff
#define PM_GRAFX_CFG_MSB 22
#define PM_GRAFX_CFG_LSB 16
#define PM_GRAFX_ENAB_BITS 12:12
#define PM_GRAFX_ENAB_SET 0x00001000
#define PM_GRAFX_ENAB_CLR 0xffffefff
#define PM_GRAFX_ENAB_MSB 12
#define PM_GRAFX_ENAB_LSB 12
#define PM_GRAFX_V3DRSTN_BITS 6:6
#define PM_GRAFX_V3DRSTN_SET 0x00000040
#define PM_GRAFX_V3DRSTN_CLR 0xffffffbf
#define PM_GRAFX_V3DRSTN_MSB 6
#define PM_GRAFX_V3DRSTN_LSB 6
#define PM_GRAFX_ISFUNC_BITS 5:5
#define PM_GRAFX_ISFUNC_SET 0x00000020
#define PM_GRAFX_ISFUNC_CLR 0xffffffdf
#define PM_GRAFX_ISFUNC_MSB 5
#define PM_GRAFX_ISFUNC_LSB 5
#define PM_GRAFX_MRDONE_BITS 4:4
#define PM_GRAFX_MRDONE_SET 0x00000010
#define PM_GRAFX_MRDONE_CLR 0xffffffef
#define PM_GRAFX_MRDONE_MSB 4
#define PM_GRAFX_MRDONE_LSB 4
#define PM_GRAFX_MEMREP_BITS 3:3
#define PM_GRAFX_MEMREP_SET 0x00000008
#define PM_GRAFX_MEMREP_CLR 0xfffffff7
#define PM_GRAFX_MEMREP_MSB 3
#define PM_GRAFX_MEMREP_LSB 3
#define PM_GRAFX_ISPOW_BITS 2:2
#define PM_GRAFX_ISPOW_SET 0x00000004
#define PM_GRAFX_ISPOW_CLR 0xfffffffb
#define PM_GRAFX_ISPOW_MSB 2
#define PM_GRAFX_ISPOW_LSB 2
#define PM_GRAFX_POWOK_BITS 1:1
#define PM_GRAFX_POWOK_SET 0x00000002
#define PM_GRAFX_POWOK_CLR 0xfffffffd
#define PM_GRAFX_POWOK_MSB 1
#define PM_GRAFX_POWOK_LSB 1
#define PM_GRAFX_POWUP_BITS 0:0
#define PM_GRAFX_POWUP_SET 0x00000001
#define PM_GRAFX_POWUP_CLR 0xfffffffe
#define PM_GRAFX_POWUP_MSB 0
#define PM_GRAFX_POWUP_LSB 0
#define PM_PROC HW_REGISTER_RW( 0x7e100110 )
#define PM_PROC_MASK 0x007f107f
#define PM_PROC_WIDTH 23
#define PM_PROC_RESET 0000000000
#define PM_PROC_CFG_BITS 22:16
#define PM_PROC_CFG_SET 0x007f0000
#define PM_PROC_CFG_CLR 0xff80ffff
#define PM_PROC_CFG_MSB 22
#define PM_PROC_CFG_LSB 16
#define PM_PROC_ENAB_BITS 12:12
#define PM_PROC_ENAB_SET 0x00001000
#define PM_PROC_ENAB_CLR 0xffffefff
#define PM_PROC_ENAB_MSB 12
#define PM_PROC_ENAB_LSB 12
#define PM_PROC_ARMRSTN_BITS 6:6
#define PM_PROC_ARMRSTN_SET 0x00000040
#define PM_PROC_ARMRSTN_CLR 0xffffffbf
#define PM_PROC_ARMRSTN_MSB 6
#define PM_PROC_ARMRSTN_LSB 6
#define PM_PROC_ISFUNC_BITS 5:5
#define PM_PROC_ISFUNC_SET 0x00000020
#define PM_PROC_ISFUNC_CLR 0xffffffdf
#define PM_PROC_ISFUNC_MSB 5
#define PM_PROC_ISFUNC_LSB 5
#define PM_PROC_MRDONE_BITS 4:4
#define PM_PROC_MRDONE_SET 0x00000010
#define PM_PROC_MRDONE_CLR 0xffffffef
#define PM_PROC_MRDONE_MSB 4
#define PM_PROC_MRDONE_LSB 4
#define PM_PROC_MEMREP_BITS 3:3
#define PM_PROC_MEMREP_SET 0x00000008
#define PM_PROC_MEMREP_CLR 0xfffffff7
#define PM_PROC_MEMREP_MSB 3
#define PM_PROC_MEMREP_LSB 3
#define PM_PROC_ISPOW_BITS 2:2
#define PM_PROC_ISPOW_SET 0x00000004
#define PM_PROC_ISPOW_CLR 0xfffffffb
#define PM_PROC_ISPOW_MSB 2
#define PM_PROC_ISPOW_LSB 2
#define PM_PROC_POWOK_BITS 1:1
#define PM_PROC_POWOK_SET 0x00000002
#define PM_PROC_POWOK_CLR 0xfffffffd
#define PM_PROC_POWOK_MSB 1
#define PM_PROC_POWOK_LSB 1
#define PM_PROC_POWUP_BITS 0:0
#define PM_PROC_POWUP_SET 0x00000001
#define PM_PROC_POWUP_CLR 0xfffffffe
#define PM_PROC_POWUP_MSB 0
#define PM_PROC_POWUP_LSB 0
#define PM_RSTC HW_REGISTER_RW( 0x7e10001c )
#define PM_RSTC_MASK 0x00333333
#define PM_RSTC_WIDTH 22
#define PM_RSTC_RESET 0x00000102
#define PM_RSTC_HRCFG_BITS 21:20
#define PM_RSTC_HRCFG_SET 0x00300000
#define PM_RSTC_HRCFG_CLR 0xffcfffff
#define PM_RSTC_HRCFG_MSB 21
#define PM_RSTC_HRCFG_LSB 20
#define PM_RSTC_FRCFG_BITS 17:16
#define PM_RSTC_FRCFG_SET 0x00030000
#define PM_RSTC_FRCFG_CLR 0xfffcffff
#define PM_RSTC_FRCFG_MSB 17
#define PM_RSTC_FRCFG_LSB 16
#define PM_RSTC_QRCFG_BITS 13:12
#define PM_RSTC_QRCFG_SET 0x00003000
#define PM_RSTC_QRCFG_CLR 0xffffcfff
#define PM_RSTC_QRCFG_MSB 13
#define PM_RSTC_QRCFG_LSB 12
#define PM_RSTC_SRCFG_BITS 9:8
#define PM_RSTC_SRCFG_SET 0x00000300
#define PM_RSTC_SRCFG_CLR 0xfffffcff
#define PM_RSTC_SRCFG_MSB 9
#define PM_RSTC_SRCFG_LSB 8
#define PM_RSTC_WRCFG_BITS 5:4
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTC_WRCFG_MSB 5
#define PM_RSTC_WRCFG_LSB 4
#define PM_RSTC_DRCFG_BITS 1:0
#define PM_RSTC_DRCFG_SET 0x00000003
#define PM_RSTC_DRCFG_CLR 0xfffffffc
#define PM_RSTC_DRCFG_MSB 1
#define PM_RSTC_DRCFG_LSB 0
#define PM_RSTS HW_REGISTER_RW( 0x7e100020 )
#define PM_RSTS_MASK 0x00001777
#define PM_RSTS_WIDTH 13
#define PM_RSTS_RESET 0x00001000
#define PM_RSTS_HADPOR_BITS 12:12
#define PM_RSTS_HADPOR_SET 0x00001000
#define PM_RSTS_HADPOR_CLR 0xffffefff
#define PM_RSTS_HADPOR_MSB 12
#define PM_RSTS_HADPOR_LSB 12
#define PM_RSTS_HADSRH_BITS 10:10
#define PM_RSTS_HADSRH_SET 0x00000400
#define PM_RSTS_HADSRH_CLR 0xfffffbff
#define PM_RSTS_HADSRH_MSB 10
#define PM_RSTS_HADSRH_LSB 10
#define PM_RSTS_HADSRF_BITS 9:9
#define PM_RSTS_HADSRF_SET 0x00000200
#define PM_RSTS_HADSRF_CLR 0xfffffdff
#define PM_RSTS_HADSRF_MSB 9
#define PM_RSTS_HADSRF_LSB 9
#define PM_RSTS_HADSRQ_BITS 8:8
#define PM_RSTS_HADSRQ_SET 0x00000100
#define PM_RSTS_HADSRQ_CLR 0xfffffeff
#define PM_RSTS_HADSRQ_MSB 8
#define PM_RSTS_HADSRQ_LSB 8
#define PM_RSTS_HADWRH_BITS 6:6
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTS_HADWRH_CLR 0xffffffbf
#define PM_RSTS_HADWRH_MSB 6
#define PM_RSTS_HADWRH_LSB 6
#define PM_RSTS_HADWRF_BITS 5:5
#define PM_RSTS_HADWRF_SET 0x00000020
#define PM_RSTS_HADWRF_CLR 0xffffffdf
#define PM_RSTS_HADWRF_MSB 5
#define PM_RSTS_HADWRF_LSB 5
#define PM_RSTS_HADWRQ_BITS 4:4
#define PM_RSTS_HADWRQ_SET 0x00000010
#define PM_RSTS_HADWRQ_CLR 0xffffffef
#define PM_RSTS_HADWRQ_MSB 4
#define PM_RSTS_HADWRQ_LSB 4
#define PM_RSTS_HADDRH_BITS 2:2
#define PM_RSTS_HADDRH_SET 0x00000004
#define PM_RSTS_HADDRH_CLR 0xfffffffb
#define PM_RSTS_HADDRH_MSB 2
#define PM_RSTS_HADDRH_LSB 2
#define PM_RSTS_HADDRF_BITS 1:1
#define PM_RSTS_HADDRF_SET 0x00000002
#define PM_RSTS_HADDRF_CLR 0xfffffffd
#define PM_RSTS_HADDRF_MSB 1
#define PM_RSTS_HADDRF_LSB 1
#define PM_RSTS_HADDRQ_BITS 0:0
#define PM_RSTS_HADDRQ_SET 0x00000001
#define PM_RSTS_HADDRQ_CLR 0xfffffffe
#define PM_RSTS_HADDRQ_MSB 0
#define PM_RSTS_HADDRQ_LSB 0
#define PM_WDOG HW_REGISTER_RW( 0x7e100024 )
#define PM_WDOG_MASK 0x000fffff
#define PM_WDOG_WIDTH 20
#define PM_WDOG_RESET 0000000000
#define PM_WDOG_TIME_BITS 19:0
#define PM_WDOG_TIME_SET 0x000fffff
#define PM_WDOG_TIME_CLR 0xfff00000
#define PM_WDOG_TIME_MSB 19
#define PM_WDOG_TIME_LSB 0
#define PM_PADS0 HW_REGISTER_RW( 0x7e100028 )
#define PM_PADS0_MASK 0x0000003f
#define PM_PADS0_WIDTH 6
#define PM_PADS0_RESET 0x0000001b
#define PM_PADS0_DRIVE_BITS 2:0
#define PM_PADS0_DRIVE_SET 0x00000007
#define PM_PADS0_DRIVE_CLR 0xfffffff8
#define PM_PADS0_DRIVE_MSB 2
#define PM_PADS0_DRIVE_LSB 0
#define PM_PADS0_HYST_BITS 3:3
#define PM_PADS0_HYST_SET 0x00000008
#define PM_PADS0_HYST_CLR 0xfffffff7
#define PM_PADS0_HYST_MSB 3
#define PM_PADS0_HYST_LSB 3
#define PM_PADS0_SLEW_BITS 4:4
#define PM_PADS0_SLEW_SET 0x00000010
#define PM_PADS0_SLEW_CLR 0xffffffef
#define PM_PADS0_SLEW_MSB 4
#define PM_PADS0_SLEW_LSB 4
#define PM_PADS0_POWOK_BITS 5:5
#define PM_PADS0_POWOK_SET 0x00000020
#define PM_PADS0_POWOK_CLR 0xffffffdf
#define PM_PADS0_POWOK_MSB 5
#define PM_PADS0_POWOK_LSB 5
#define PM_PADS2 HW_REGISTER_RW( 0x7e10002c )
#define PM_PADS2_MASK 0x0000003f
#define PM_PADS2_WIDTH 6
#define PM_PADS2_RESET 0x0000001b
#define PM_PADS2_DRIVE_BITS 2:0
#define PM_PADS2_DRIVE_SET 0x00000007
#define PM_PADS2_DRIVE_CLR 0xfffffff8
#define PM_PADS2_DRIVE_MSB 2
#define PM_PADS2_DRIVE_LSB 0
#define PM_PADS2_HYST_BITS 3:3
#define PM_PADS2_HYST_SET 0x00000008
#define PM_PADS2_HYST_CLR 0xfffffff7
#define PM_PADS2_HYST_MSB 3
#define PM_PADS2_HYST_LSB 3
#define PM_PADS2_SLEW_BITS 4:4
#define PM_PADS2_SLEW_SET 0x00000010
#define PM_PADS2_SLEW_CLR 0xffffffef
#define PM_PADS2_SLEW_MSB 4
#define PM_PADS2_SLEW_LSB 4
#define PM_PADS2_POWOK_BITS 5:5
#define PM_PADS2_POWOK_SET 0x00000020
#define PM_PADS2_POWOK_CLR 0xffffffdf
#define PM_PADS2_POWOK_MSB 5
#define PM_PADS2_POWOK_LSB 5
#define PM_PADS3 HW_REGISTER_RW( 0x7e100030 )
#define PM_PADS3_MASK 0x0000003f
#define PM_PADS3_WIDTH 6
#define PM_PADS3_RESET 0x0000001b
#define PM_PADS3_DRIVE_BITS 2:0
#define PM_PADS3_DRIVE_SET 0x00000007
#define PM_PADS3_DRIVE_CLR 0xfffffff8
#define PM_PADS3_DRIVE_MSB 2
#define PM_PADS3_DRIVE_LSB 0
#define PM_PADS3_HYST_BITS 3:3
#define PM_PADS3_HYST_SET 0x00000008
#define PM_PADS3_HYST_CLR 0xfffffff7
#define PM_PADS3_HYST_MSB 3
#define PM_PADS3_HYST_LSB 3
#define PM_PADS3_SLEW_BITS 4:4
#define PM_PADS3_SLEW_SET 0x00000010
#define PM_PADS3_SLEW_CLR 0xffffffef
#define PM_PADS3_SLEW_MSB 4
#define PM_PADS3_SLEW_LSB 4
#define PM_PADS3_POWOK_BITS 5:5
#define PM_PADS3_POWOK_SET 0x00000020
#define PM_PADS3_POWOK_CLR 0xffffffdf
#define PM_PADS3_POWOK_MSB 5
#define PM_PADS3_POWOK_LSB 5
#define PM_PADS4 HW_REGISTER_RW( 0x7e100034 )
#define PM_PADS4_MASK 0x0000003f
#define PM_PADS4_WIDTH 6
#define PM_PADS4_RESET 0x0000001b
#define PM_PADS4_DRIVE_BITS 2:0
#define PM_PADS4_DRIVE_SET 0x00000007
#define PM_PADS4_DRIVE_CLR 0xfffffff8
#define PM_PADS4_DRIVE_MSB 2
#define PM_PADS4_DRIVE_LSB 0
#define PM_PADS4_HYST_BITS 3:3
#define PM_PADS4_HYST_SET 0x00000008
#define PM_PADS4_HYST_CLR 0xfffffff7
#define PM_PADS4_HYST_MSB 3
#define PM_PADS4_HYST_LSB 3
#define PM_PADS4_SPARE_BITS 4:4
#define PM_PADS4_SPARE_SET 0x00000010
#define PM_PADS4_SPARE_CLR 0xffffffef
#define PM_PADS4_SPARE_MSB 4
#define PM_PADS4_SPARE_LSB 4
#define PM_PADS4_POWOK_BITS 5:5
#define PM_PADS4_POWOK_SET 0x00000020
#define PM_PADS4_POWOK_CLR 0xffffffdf
#define PM_PADS4_POWOK_MSB 5
#define PM_PADS4_POWOK_LSB 5
#define PM_PADS5 HW_REGISTER_RW( 0x7e100038 )
#define PM_PADS5_MASK 0x0000007f
#define PM_PADS5_WIDTH 7
#define PM_PADS5_RESET 0x0000001b
#define PM_PADS5_DRIVE_BITS 2:0
#define PM_PADS5_DRIVE_SET 0x00000007
#define PM_PADS5_DRIVE_CLR 0xfffffff8
#define PM_PADS5_DRIVE_MSB 2
#define PM_PADS5_DRIVE_LSB 0
#define PM_PADS5_HYST_BITS 3:3
#define PM_PADS5_HYST_SET 0x00000008
#define PM_PADS5_HYST_CLR 0xfffffff7
#define PM_PADS5_HYST_MSB 3
#define PM_PADS5_HYST_LSB 3
#define PM_PADS5_SLEW_BITS 4:4
#define PM_PADS5_SLEW_SET 0x00000010
#define PM_PADS5_SLEW_CLR 0xffffffef
#define PM_PADS5_SLEW_MSB 4
#define PM_PADS5_SLEW_LSB 4
#define PM_PADS5_POWOK_BITS 5:5
#define PM_PADS5_POWOK_SET 0x00000020
#define PM_PADS5_POWOK_CLR 0xffffffdf
#define PM_PADS5_POWOK_MSB 5
#define PM_PADS5_POWOK_LSB 5
#define PM_PADS5_I2CMODE_BITS 6:6
#define PM_PADS5_I2CMODE_SET 0x00000040
#define PM_PADS5_I2CMODE_CLR 0xffffffbf
#define PM_PADS5_I2CMODE_MSB 6
#define PM_PADS5_I2CMODE_LSB 6
#define PM_PADS6 HW_REGISTER_RW( 0x7e10003c )
#define PM_PADS6_MASK 0x00000123
#define PM_PADS6_WIDTH 9
#define PM_PADS6_RESET 0000000000
#define PM_PADS6_DRIVE_BITS 1:0
#define PM_PADS6_DRIVE_SET 0x00000003
#define PM_PADS6_DRIVE_CLR 0xfffffffc
#define PM_PADS6_DRIVE_MSB 1
#define PM_PADS6_DRIVE_LSB 0
#define PM_PADS6_POWOK_BITS 5:5
#define PM_PADS6_POWOK_SET 0x00000020
#define PM_PADS6_POWOK_CLR 0xffffffdf
#define PM_PADS6_POWOK_MSB 5
#define PM_PADS6_POWOK_LSB 5
#define PM_PADS6_PD_BITS 8:8
#define PM_PADS6_PD_SET 0x00000100
#define PM_PADS6_PD_CLR 0xfffffeff
#define PM_PADS6_PD_MSB 8
#define PM_PADS6_PD_LSB 8
#define PM_CAM0 HW_REGISTER_RW( 0x7e100044 )
#define PM_CAM0_MASK 0x001fffff
#define PM_CAM0_WIDTH 21
#define PM_CAM0_RESET 0000000000
#define PM_CAM0_CTRLEN_BITS 0:0
#define PM_CAM0_CTRLEN_SET 0x00000001
#define PM_CAM0_CTRLEN_CLR 0xfffffffe
#define PM_CAM0_CTRLEN_MSB 0
#define PM_CAM0_CTRLEN_LSB 0
#define PM_CAM0_LDOLPEN_BITS 1:1
#define PM_CAM0_LDOLPEN_SET 0x00000002
#define PM_CAM0_LDOLPEN_CLR 0xfffffffd
#define PM_CAM0_LDOLPEN_MSB 1
#define PM_CAM0_LDOLPEN_LSB 1
#define PM_CAM0_LDOHPEN_BITS 2:2
#define PM_CAM0_LDOHPEN_SET 0x00000004
#define PM_CAM0_LDOHPEN_CLR 0xfffffffb
#define PM_CAM0_LDOHPEN_MSB 2
#define PM_CAM0_LDOHPEN_LSB 2
#define PM_CAM0_LDOCTRL_BITS 20:3
#define PM_CAM0_LDOCTRL_SET 0x001ffff8
#define PM_CAM0_LDOCTRL_CLR 0xffe00007
#define PM_CAM0_LDOCTRL_MSB 20
#define PM_CAM0_LDOCTRL_LSB 3
#define PM_CAM1 HW_REGISTER_RW( 0x7e100048 )
#define PM_CAM1_MASK 0x001fffff
#define PM_CAM1_WIDTH 21
#define PM_CAM1_RESET 0000000000
#define PM_CAM1_CTRLEN_BITS 0:0
#define PM_CAM1_CTRLEN_SET 0x00000001
#define PM_CAM1_CTRLEN_CLR 0xfffffffe
#define PM_CAM1_CTRLEN_MSB 0
#define PM_CAM1_CTRLEN_LSB 0
#define PM_CAM1_LDOLPEN_BITS 1:1
#define PM_CAM1_LDOLPEN_SET 0x00000002
#define PM_CAM1_LDOLPEN_CLR 0xfffffffd
#define PM_CAM1_LDOLPEN_MSB 1
#define PM_CAM1_LDOLPEN_LSB 1
#define PM_CAM1_LDOHPEN_BITS 2:2
#define PM_CAM1_LDOHPEN_SET 0x00000004
#define PM_CAM1_LDOHPEN_CLR 0xfffffffb
#define PM_CAM1_LDOHPEN_MSB 2
#define PM_CAM1_LDOHPEN_LSB 2
#define PM_CAM1_LDOCTRL_BITS 20:3
#define PM_CAM1_LDOCTRL_SET 0x001ffff8
#define PM_CAM1_LDOCTRL_CLR 0xffe00007
#define PM_CAM1_LDOCTRL_MSB 20
#define PM_CAM1_LDOCTRL_LSB 3
#define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c )
#define PM_CCP2TX_MASK 0x0007ffff
#define PM_CCP2TX_WIDTH 19
#define PM_CCP2TX_RESET 0000000000
#define PM_CCP2TX_CTRLEN_BITS 0:0
#define PM_CCP2TX_CTRLEN_SET 0x00000001
#define PM_CCP2TX_CTRLEN_CLR 0xfffffffe
#define PM_CCP2TX_CTRLEN_MSB 0
#define PM_CCP2TX_CTRLEN_LSB 0
#define PM_CCP2TX_LDOEN_BITS 1:1
#define PM_CCP2TX_LDOEN_SET 0x00000002
#define PM_CCP2TX_LDOEN_CLR 0xfffffffd
#define PM_CCP2TX_LDOEN_MSB 1
#define PM_CCP2TX_LDOEN_LSB 1
#define PM_CCP2TX_LDOCTRL_BITS 18:2
#define PM_CCP2TX_LDOCTRL_SET 0x0007fffc
#define PM_CCP2TX_LDOCTRL_CLR 0xfff80003
#define PM_CCP2TX_LDOCTRL_MSB 18
#define PM_CCP2TX_LDOCTRL_LSB 2
#define PM_DSI0 HW_REGISTER_RW( 0x7e100050 )
#define PM_DSI0_MASK 0x001fffff
#define PM_DSI0_WIDTH 21
#define PM_DSI0_RESET 0000000000
#define PM_DSI0_CTRLEN_BITS 0:0
#define PM_DSI0_CTRLEN_SET 0x00000001
#define PM_DSI0_CTRLEN_CLR 0xfffffffe
#define PM_DSI0_CTRLEN_MSB 0
#define PM_DSI0_CTRLEN_LSB 0
#define PM_DSI0_LDOLPEN_BITS 1:1
#define PM_DSI0_LDOLPEN_SET 0x00000002
#define PM_DSI0_LDOLPEN_CLR 0xfffffffd
#define PM_DSI0_LDOLPEN_MSB 1
#define PM_DSI0_LDOLPEN_LSB 1
#define PM_DSI0_LDOHPEN_BITS 2:2
#define PM_DSI0_LDOHPEN_SET 0x00000004
#define PM_DSI0_LDOHPEN_CLR 0xfffffffb
#define PM_DSI0_LDOHPEN_MSB 2
#define PM_DSI0_LDOHPEN_LSB 2
#define PM_DSI0_LDOCTRL_BITS 20:3
#define PM_DSI0_LDOCTRL_SET 0x001ffff8
#define PM_DSI0_LDOCTRL_CLR 0xffe00007
#define PM_DSI0_LDOCTRL_MSB 20
#define PM_DSI0_LDOCTRL_LSB 3
#define PM_DSI1 HW_REGISTER_RW( 0x7e100054 )
#define PM_DSI1_MASK 0x001fffff
#define PM_DSI1_WIDTH 21
#define PM_DSI1_RESET 0000000000
#define PM_DSI1_CTRLEN_BITS 0:0
#define PM_DSI1_CTRLEN_SET 0x00000001
#define PM_DSI1_CTRLEN_CLR 0xfffffffe
#define PM_DSI1_CTRLEN_MSB 0
#define PM_DSI1_CTRLEN_LSB 0
#define PM_DSI1_LDOLPEN_BITS 1:1
#define PM_DSI1_LDOLPEN_SET 0x00000002
#define PM_DSI1_LDOLPEN_CLR 0xfffffffd
#define PM_DSI1_LDOLPEN_MSB 1
#define PM_DSI1_LDOLPEN_LSB 1
#define PM_DSI1_LDOHPEN_BITS 2:2
#define PM_DSI1_LDOHPEN_SET 0x00000004
#define PM_DSI1_LDOHPEN_CLR 0xfffffffb
#define PM_DSI1_LDOHPEN_MSB 2
#define PM_DSI1_LDOHPEN_LSB 2
#define PM_DSI1_LDOCTRL_BITS 20:3
#define PM_DSI1_LDOCTRL_SET 0x001ffff8
#define PM_DSI1_LDOCTRL_CLR 0xffe00007
#define PM_DSI1_LDOCTRL_MSB 20
#define PM_DSI1_LDOCTRL_LSB 3
#define PM_HDMI HW_REGISTER_RW( 0x7e100058 )
#define PM_HDMI_MASK 0x000fffff
#define PM_HDMI_WIDTH 20
#define PM_HDMI_RESET 0x00080002
#define PM_HDMI_CTRLEN_BITS 0:0
#define PM_HDMI_CTRLEN_SET 0x00000001
#define PM_HDMI_CTRLEN_CLR 0xfffffffe
#define PM_HDMI_CTRLEN_MSB 0
#define PM_HDMI_CTRLEN_LSB 0
#define PM_HDMI_LDOPD_BITS 1:1
#define PM_HDMI_LDOPD_SET 0x00000002
#define PM_HDMI_LDOPD_CLR 0xfffffffd
#define PM_HDMI_LDOPD_MSB 1
#define PM_HDMI_LDOPD_LSB 1
#define PM_HDMI_LDOCTRL_BITS 18:2
#define PM_HDMI_LDOCTRL_SET 0x0007fffc
#define PM_HDMI_LDOCTRL_CLR 0xfff80003
#define PM_HDMI_LDOCTRL_MSB 18
#define PM_HDMI_LDOCTRL_LSB 2
#define PM_HDMI_RSTDR_BITS 19:19
#define PM_HDMI_RSTDR_SET 0x00080000
#define PM_HDMI_RSTDR_CLR 0xfff7ffff
#define PM_HDMI_RSTDR_MSB 19
#define PM_HDMI_RSTDR_LSB 19
#define PM_USB HW_REGISTER_RW( 0x7e10005c )
#define PM_USB_MASK 0x00000001
#define PM_USB_WIDTH 1
#define PM_USB_RESET 0000000000
#define PM_USB_CTRLEN_BITS 0:0
#define PM_USB_CTRLEN_SET 0x00000001
#define PM_USB_CTRLEN_CLR 0xfffffffe
#define PM_USB_CTRLEN_MSB 0
#define PM_USB_CTRLEN_LSB 0
#define PM_PXLDO HW_REGISTER_RW( 0x7e100060 )
#define PM_PXLDO_MASK 0x0003ffff
#define PM_PXLDO_WIDTH 18
#define PM_PXLDO_RESET 0000000000
#define PM_PXLDO_CTRL_BITS 15:0
#define PM_PXLDO_CTRL_SET 0x0000ffff
#define PM_PXLDO_CTRL_CLR 0xffff0000
#define PM_PXLDO_CTRL_MSB 15
#define PM_PXLDO_CTRL_LSB 0
#define PM_PXLDO_RSTOSCDR_BITS 16:16
#define PM_PXLDO_RSTOSCDR_SET 0x00010000
#define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff
#define PM_PXLDO_RSTOSCDR_MSB 16
#define PM_PXLDO_RSTOSCDR_LSB 16
#define PM_PXLDO_RSTPLLDR_BITS 17:17
#define PM_PXLDO_RSTPLLDR_SET 0x00020000
#define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff
#define PM_PXLDO_RSTPLLDR_MSB 17
#define PM_PXLDO_RSTPLLDR_LSB 17
#define PM_PXBG HW_REGISTER_RW( 0x7e100064 )
#define PM_PXBG_MASK 0x0000ffff
#define PM_PXBG_WIDTH 16
#define PM_PXBG_RESET 0000000000
#define PM_PXBG_CTRL_BITS 15:0
#define PM_PXBG_CTRL_SET 0x0000ffff
#define PM_PXBG_CTRL_CLR 0xffff0000
#define PM_PXBG_CTRL_MSB 15
#define PM_PXBG_CTRL_LSB 0
#define PM_DFT HW_REGISTER_RW( 0x7e100068 )
#define PM_DFT_MASK 0x00000003
#define PM_DFT_WIDTH 2
#define PM_DFT_RESET 0000000000
#define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0
#define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001
#define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe
#define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0
#define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0
#define PM_DFT_STOPALLCLOCKS_BITS 1:1
#define PM_DFT_STOPALLCLOCKS_SET 0x00000002
#define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd
#define PM_DFT_STOPALLCLOCKS_MSB 1
#define PM_DFT_STOPALLCLOCKS_LSB 1
#define PM_SMPS HW_REGISTER_RW( 0x7e10006c )
#define PM_SMPS_MASK 0x00000007
#define PM_SMPS_WIDTH 3
#define PM_SMPS_RESET 0000000000
#define PM_SMPS_CTRLEN_BITS 0:0
#define PM_SMPS_CTRLEN_SET 0x00000001
#define PM_SMPS_CTRLEN_CLR 0xfffffffe
#define PM_SMPS_CTRLEN_MSB 0
#define PM_SMPS_CTRLEN_LSB 0
#define PM_SMPS_RSTDR_BITS 1:1
#define PM_SMPS_RSTDR_SET 0x00000002
#define PM_SMPS_RSTDR_CLR 0xfffffffd
#define PM_SMPS_RSTDR_MSB 1
#define PM_SMPS_RSTDR_LSB 1
#define PM_SMPS_UPEN_BITS 2:2
#define PM_SMPS_UPEN_SET 0x00000004
#define PM_SMPS_UPEN_CLR 0xfffffffb
#define PM_SMPS_UPEN_MSB 2
#define PM_SMPS_UPEN_LSB 2
#define PM_XOSC HW_REGISTER_RW( 0x7e100070 )
#define PM_XOSC_MASK 0x00000001
#define PM_XOSC_WIDTH 1
#define PM_XOSC_RESET 0000000000
#define PM_XOSC_USESEC_BITS 0:0
#define PM_XOSC_USESEC_SET 0x00000001
#define PM_XOSC_USESEC_CLR 0xfffffffe
#define PM_XOSC_USESEC_MSB 0
#define PM_XOSC_USESEC_LSB 0
#define PM_SPAREW HW_REGISTER_RW( 0x7e100074 )
#define PM_SPAREW_MASK 0x00ffffff
#define PM_SPAREW_WIDTH 24
#define PM_SPAREW_RESET 0000000000
#define PM_SPAREW_SPARE_BITS 23:0
#define PM_SPAREW_SPARE_SET 0x00ffffff
#define PM_SPAREW_SPARE_CLR 0xff000000
#define PM_SPAREW_SPARE_MSB 23
#define PM_SPAREW_SPARE_LSB 0
#define PM_SPARER HW_REGISTER_RO( 0x7e100078 )
#define PM_SPARER_MASK 0x00ffffff
#define PM_SPARER_WIDTH 24
#define PM_SPARER_RESET 0000000000
#define PM_SPARER_SPARE_BITS 23:0
#define PM_SPARER_SPARE_SET 0x00ffffff
#define PM_SPARER_SPARE_CLR 0xff000000
#define PM_SPARER_SPARE_MSB 23
#define PM_SPARER_SPARE_LSB 0
#define PM_AVS_RSTDR HW_REGISTER_RW( 0x7e10007c )
#define PM_AVS_RSTDR_MASK 0x0000003f
#define PM_AVS_RSTDR_WIDTH 6
#define PM_AVS_RSTDR_RESET 0000000000
#define PM_AVS_RSTDR_PERI_A_BITS 0:0
#define PM_AVS_RSTDR_PERI_A_SET 0x00000001
#define PM_AVS_RSTDR_PERI_A_CLR 0xfffffffe
#define PM_AVS_RSTDR_PERI_A_MSB 0
#define PM_AVS_RSTDR_PERI_A_LSB 0
#define PM_AVS_RSTDR_SYSTEM_A_BITS 1:1
#define PM_AVS_RSTDR_SYSTEM_A_SET 0x00000002
#define PM_AVS_RSTDR_SYSTEM_A_CLR 0xfffffffd
#define PM_AVS_RSTDR_SYSTEM_A_MSB 1
#define PM_AVS_RSTDR_SYSTEM_A_LSB 1
#define PM_AVS_RSTDR_H264_I_BITS 2:2
#define PM_AVS_RSTDR_H264_I_SET 0x00000004
#define PM_AVS_RSTDR_H264_I_CLR 0xfffffffb
#define PM_AVS_RSTDR_H264_I_MSB 2
#define PM_AVS_RSTDR_H264_I_LSB 2
#define PM_AVS_RSTDR_V3D_G_BITS 3:3
#define PM_AVS_RSTDR_V3D_G_SET 0x00000008
#define PM_AVS_RSTDR_V3D_G_CLR 0xfffffff7
#define PM_AVS_RSTDR_V3D_G_MSB 3
#define PM_AVS_RSTDR_V3D_G_LSB 3
#define PM_AVS_RSTDR_ARM_P_BITS 4:4
#define PM_AVS_RSTDR_ARM_P_SET 0x00000010
#define PM_AVS_RSTDR_ARM_P_CLR 0xffffffef
#define PM_AVS_RSTDR_ARM_P_MSB 4
#define PM_AVS_RSTDR_ARM_P_LSB 4
#define PM_AVS_RSTDR_ROSC_BITS 5:5
#define PM_AVS_RSTDR_ROSC_SET 0x00000020
#define PM_AVS_RSTDR_ROSC_CLR 0xffffffdf
#define PM_AVS_RSTDR_ROSC_MSB 5
#define PM_AVS_RSTDR_ROSC_LSB 5
#define PM_AVS_STAT HW_REGISTER_RW( 0x7e100080 )
#define PM_AVS_STAT_MASK 0x0000001f
#define PM_AVS_STAT_WIDTH 5
#define PM_AVS_STAT_RESET 0000000000
#define PM_AVS_STAT_ALERT_PERI_A_BITS 0:0
#define PM_AVS_STAT_ALERT_PERI_A_SET 0x00000001
#define PM_AVS_STAT_ALERT_PERI_A_CLR 0xfffffffe
#define PM_AVS_STAT_ALERT_PERI_A_MSB 0
#define PM_AVS_STAT_ALERT_PERI_A_LSB 0
#define PM_AVS_STAT_ALERT_SYSTEM_A_BITS 1:1
#define PM_AVS_STAT_ALERT_SYSTEM_A_SET 0x00000002
#define PM_AVS_STAT_ALERT_SYSTEM_A_CLR 0xfffffffd
#define PM_AVS_STAT_ALERT_SYSTEM_A_MSB 1
#define PM_AVS_STAT_ALERT_SYSTEM_A_LSB 1
#define PM_AVS_STAT_ALERT_H264_I_BITS 2:2
#define PM_AVS_STAT_ALERT_H264_I_SET 0x00000004
#define PM_AVS_STAT_ALERT_H264_I_CLR 0xfffffffb
#define PM_AVS_STAT_ALERT_H264_I_MSB 2
#define PM_AVS_STAT_ALERT_H264_I_LSB 2
#define PM_AVS_STAT_ALERT_V3D_G_BITS 3:3
#define PM_AVS_STAT_ALERT_V3D_G_SET 0x00000008
#define PM_AVS_STAT_ALERT_V3D_G_CLR 0xfffffff7
#define PM_AVS_STAT_ALERT_V3D_G_MSB 3
#define PM_AVS_STAT_ALERT_V3D_G_LSB 3
#define PM_AVS_STAT_ALERT_ARM_P_BITS 4:4
#define PM_AVS_STAT_ALERT_ARM_P_SET 0x00000010
#define PM_AVS_STAT_ALERT_ARM_P_CLR 0xffffffef
#define PM_AVS_STAT_ALERT_ARM_P_MSB 4
#define PM_AVS_STAT_ALERT_ARM_P_LSB 4
#define PM_AVS_EVENT HW_REGISTER_RW( 0x7e100084 )
#define PM_AVS_EVENT_MASK 0x0000001f
#define PM_AVS_EVENT_WIDTH 5
#define PM_AVS_EVENT_RESET 0000000000
#define PM_AVS_EVENT_ALERT_PERI_A_BITS 0:0
#define PM_AVS_EVENT_ALERT_PERI_A_SET 0x00000001
#define PM_AVS_EVENT_ALERT_PERI_A_CLR 0xfffffffe
#define PM_AVS_EVENT_ALERT_PERI_A_MSB 0
#define PM_AVS_EVENT_ALERT_PERI_A_LSB 0
#define PM_AVS_EVENT_ALERT_SYSTEM_A_BITS 1:1
#define PM_AVS_EVENT_ALERT_SYSTEM_A_SET 0x00000002
#define PM_AVS_EVENT_ALERT_SYSTEM_A_CLR 0xfffffffd
#define PM_AVS_EVENT_ALERT_SYSTEM_A_MSB 1
#define PM_AVS_EVENT_ALERT_SYSTEM_A_LSB 1
#define PM_AVS_EVENT_ALERT_H264_I_BITS 2:2
#define PM_AVS_EVENT_ALERT_H264_I_SET 0x00000004
#define PM_AVS_EVENT_ALERT_H264_I_CLR 0xfffffffb
#define PM_AVS_EVENT_ALERT_H264_I_MSB 2
#define PM_AVS_EVENT_ALERT_H264_I_LSB 2
#define PM_AVS_EVENT_ALERT_V3D_G_BITS 3:3
#define PM_AVS_EVENT_ALERT_V3D_G_SET 0x00000008
#define PM_AVS_EVENT_ALERT_V3D_G_CLR 0xfffffff7
#define PM_AVS_EVENT_ALERT_V3D_G_MSB 3
#define PM_AVS_EVENT_ALERT_V3D_G_LSB 3
#define PM_AVS_EVENT_ALERT_ARM_P_BITS 4:4
#define PM_AVS_EVENT_ALERT_ARM_P_SET 0x00000010
#define PM_AVS_EVENT_ALERT_ARM_P_CLR 0xffffffef
#define PM_AVS_EVENT_ALERT_ARM_P_MSB 4
#define PM_AVS_EVENT_ALERT_ARM_P_LSB 4
#define PM_AVS_INTEN HW_REGISTER_RW( 0x7e100088 )
#define PM_AVS_INTEN_MASK 0x0000001f
#define PM_AVS_INTEN_WIDTH 5
#define PM_AVS_INTEN_RESET 0000000000
#define PM_AVS_INTEN_ALERT_PERI_A_BITS 0:0
#define PM_AVS_INTEN_ALERT_PERI_A_SET 0x00000001
#define PM_AVS_INTEN_ALERT_PERI_A_CLR 0xfffffffe
#define PM_AVS_INTEN_ALERT_PERI_A_MSB 0
#define PM_AVS_INTEN_ALERT_PERI_A_LSB 0
#define PM_AVS_INTEN_ALERT_SYSTEM_A_BITS 1:1
#define PM_AVS_INTEN_ALERT_SYSTEM_A_SET 0x00000002
#define PM_AVS_INTEN_ALERT_SYSTEM_A_CLR 0xfffffffd
#define PM_AVS_INTEN_ALERT_SYSTEM_A_MSB 1
#define PM_AVS_INTEN_ALERT_SYSTEM_A_LSB 1
#define PM_AVS_INTEN_ALERT_H264_I_BITS 2:2
#define PM_AVS_INTEN_ALERT_H264_I_SET 0x00000004
#define PM_AVS_INTEN_ALERT_H264_I_CLR 0xfffffffb
#define PM_AVS_INTEN_ALERT_H264_I_MSB 2
#define PM_AVS_INTEN_ALERT_H264_I_LSB 2
#define PM_AVS_INTEN_ALERT_V3D_G_BITS 3:3
#define PM_AVS_INTEN_ALERT_V3D_G_SET 0x00000008
#define PM_AVS_INTEN_ALERT_V3D_G_CLR 0xfffffff7
#define PM_AVS_INTEN_ALERT_V3D_G_MSB 3
#define PM_AVS_INTEN_ALERT_V3D_G_LSB 3
#define PM_AVS_INTEN_ALERT_ARM_P_BITS 4:4
#define PM_AVS_INTEN_ALERT_ARM_P_SET 0x00000010
#define PM_AVS_INTEN_ALERT_ARM_P_CLR 0xffffffef
#define PM_AVS_INTEN_ALERT_ARM_P_MSB 4
#define PM_AVS_INTEN_ALERT_ARM_P_LSB 4
#define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc )
#define PM_DUMMY_MASK 0x00000001
#define PM_DUMMY_WIDTH 1
#define PM_DUMMY_RESET 0x00000001
#define PM_DUMMY_ONE_BITS 0:0
#define PM_DUMMY_ONE_SET 0x00000001
#define PM_DUMMY_ONE_CLR 0xfffffffe
#define PM_DUMMY_ONE_MSB 0
#define PM_DUMMY_ONE_LSB 0

809
bcm2708_chip/cpr_powman_a0.h Executable file
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@ -0,0 +1,809 @@
// This file was generated by the create_regs script
#define PM_PASSWORD 0x5a000000
#define PM_BASE 0x7e100000
#define PM_APB_ID 0x0000706d
#define PM_GNRIC HW_REGISTER_RW( 0x7e100000 )
#define PM_GNRIC_MASK 0x007f0fff
#define PM_GNRIC_WIDTH 23
#define PM_GNRIC_RESET 0000000000
#define PM_GNRIC_CFG_BITS 22:16
#define PM_GNRIC_CFG_SET 0x007f0000
#define PM_GNRIC_CFG_CLR 0xff80ffff
#define PM_GNRIC_CFG_MSB 22
#define PM_GNRIC_CFG_LSB 16
#define PM_GNRIC_RSTN_BITS 11:6
#define PM_GNRIC_RSTN_SET 0x00000fc0
#define PM_GNRIC_RSTN_CLR 0xfffff03f
#define PM_GNRIC_RSTN_MSB 11
#define PM_GNRIC_RSTN_LSB 6
#define PM_GNRIC_ISFUNC_BITS 5:5
#define PM_GNRIC_ISFUNC_SET 0x00000020
#define PM_GNRIC_ISFUNC_CLR 0xffffffdf
#define PM_GNRIC_ISFUNC_MSB 5
#define PM_GNRIC_ISFUNC_LSB 5
#define PM_GNRIC_MRDONE_BITS 4:4
#define PM_GNRIC_MRDONE_SET 0x00000010
#define PM_GNRIC_MRDONE_CLR 0xffffffef
#define PM_GNRIC_MRDONE_MSB 4
#define PM_GNRIC_MRDONE_LSB 4
#define PM_GNRIC_MEMREP_BITS 3:3
#define PM_GNRIC_MEMREP_SET 0x00000008
#define PM_GNRIC_MEMREP_CLR 0xfffffff7
#define PM_GNRIC_MEMREP_MSB 3
#define PM_GNRIC_MEMREP_LSB 3
#define PM_GNRIC_ISPOW_BITS 2:2
#define PM_GNRIC_ISPOW_SET 0x00000004
#define PM_GNRIC_ISPOW_CLR 0xfffffffb
#define PM_GNRIC_ISPOW_MSB 2
#define PM_GNRIC_ISPOW_LSB 2
#define PM_GNRIC_POWOK_BITS 1:1
#define PM_GNRIC_POWOK_SET 0x00000002
#define PM_GNRIC_POWOK_CLR 0xfffffffd
#define PM_GNRIC_POWOK_MSB 1
#define PM_GNRIC_POWOK_LSB 1
#define PM_GNRIC_POWUP_BITS 0:0
#define PM_GNRIC_POWUP_SET 0x00000001
#define PM_GNRIC_POWUP_CLR 0xfffffffe
#define PM_GNRIC_POWUP_MSB 0
#define PM_GNRIC_POWUP_LSB 0
#define PM_AUDIO HW_REGISTER_RW( 0x7e100004 )
#define PM_AUDIO_MASK 0x000101ff
#define PM_AUDIO_WIDTH 17
#define PM_AUDIO_RESET 0x00010000
#define PM_AUDIO_RSTN_BITS 16:16
#define PM_AUDIO_RSTN_SET 0x00010000
#define PM_AUDIO_RSTN_CLR 0xfffeffff
#define PM_AUDIO_RSTN_MSB 16
#define PM_AUDIO_RSTN_LSB 16
#define PM_AUDIO_CTRLEN_BITS 8:8
#define PM_AUDIO_CTRLEN_SET 0x00000100
#define PM_AUDIO_CTRLEN_CLR 0xfffffeff
#define PM_AUDIO_CTRLEN_MSB 8
#define PM_AUDIO_CTRLEN_LSB 8
#define PM_AUDIO_APSM_BITS 7:0
#define PM_AUDIO_APSM_SET 0x000000ff
#define PM_AUDIO_APSM_CLR 0xffffff00
#define PM_AUDIO_APSM_MSB 7
#define PM_AUDIO_APSM_LSB 0
#define PM_OLDIMAGE HW_REGISTER_RW( 0x7e100008 )
#define PM_OLDIMAGE_MASK 0x007f007f
#define PM_OLDIMAGE_WIDTH 23
#define PM_OLDIMAGE_RESET 0000000000
#define PM_OLDIMAGE_CFG_BITS 22:16
#define PM_OLDIMAGE_CFG_SET 0x007f0000
#define PM_OLDIMAGE_CFG_CLR 0xff80ffff
#define PM_OLDIMAGE_CFG_MSB 22
#define PM_OLDIMAGE_CFG_LSB 16
#define PM_OLDIMAGE_ISPRSTN_BITS 6:6
#define PM_OLDIMAGE_ISPRSTN_SET 0x00000040
#define PM_OLDIMAGE_ISPRSTN_CLR 0xffffffbf
#define PM_OLDIMAGE_ISPRSTN_MSB 6
#define PM_OLDIMAGE_ISPRSTN_LSB 6
#define PM_OLDIMAGE_H264RSTN_BITS 5:5
#define PM_OLDIMAGE_H264RSTN_SET 0x00000020
#define PM_OLDIMAGE_H264RSTN_CLR 0xffffffdf
#define PM_OLDIMAGE_H264RSTN_MSB 5
#define PM_OLDIMAGE_H264RSTN_LSB 5
#define PM_OLDIMAGE_PERIRSTN_BITS 4:4
#define PM_OLDIMAGE_PERIRSTN_SET 0x00000010
#define PM_OLDIMAGE_PERIRSTN_CLR 0xffffffef
#define PM_OLDIMAGE_PERIRSTN_MSB 4
#define PM_OLDIMAGE_PERIRSTN_LSB 4
#define PM_OLDIMAGE_ISFUNC_BITS 3:3
#define PM_OLDIMAGE_ISFUNC_SET 0x00000008
#define PM_OLDIMAGE_ISFUNC_CLR 0xfffffff7
#define PM_OLDIMAGE_ISFUNC_MSB 3
#define PM_OLDIMAGE_ISFUNC_LSB 3
#define PM_OLDIMAGE_ISPOW_BITS 2:2
#define PM_OLDIMAGE_ISPOW_SET 0x00000004
#define PM_OLDIMAGE_ISPOW_CLR 0xfffffffb
#define PM_OLDIMAGE_ISPOW_MSB 2
#define PM_OLDIMAGE_ISPOW_LSB 2
#define PM_OLDIMAGE_POWOK_BITS 1:1
#define PM_OLDIMAGE_POWOK_SET 0x00000002
#define PM_OLDIMAGE_POWOK_CLR 0xfffffffd
#define PM_OLDIMAGE_POWOK_MSB 1
#define PM_OLDIMAGE_POWOK_LSB 1
#define PM_OLDIMAGE_POWUP_BITS 0:0
#define PM_OLDIMAGE_POWUP_SET 0x00000001
#define PM_OLDIMAGE_POWUP_CLR 0xfffffffe
#define PM_OLDIMAGE_POWUP_MSB 0
#define PM_OLDIMAGE_POWUP_LSB 0
#define PM_OLDGRAFX HW_REGISTER_RW( 0x7e10000c )
#define PM_OLDGRAFX_MASK 0x007f008f
#define PM_OLDGRAFX_WIDTH 23
#define PM_OLDGRAFX_RESET 0000000000
#define PM_OLDGRAFX_CFG_BITS 22:16
#define PM_OLDGRAFX_CFG_SET 0x007f0000
#define PM_OLDGRAFX_CFG_CLR 0xff80ffff
#define PM_OLDGRAFX_CFG_MSB 22
#define PM_OLDGRAFX_CFG_LSB 16
#define PM_OLDGRAFX_V3DRSTN_BITS 7:7
#define PM_OLDGRAFX_V3DRSTN_SET 0x00000080
#define PM_OLDGRAFX_V3DRSTN_CLR 0xffffff7f
#define PM_OLDGRAFX_V3DRSTN_MSB 7
#define PM_OLDGRAFX_V3DRSTN_LSB 7
#define PM_OLDGRAFX_ISFUNC_BITS 3:3
#define PM_OLDGRAFX_ISFUNC_SET 0x00000008
#define PM_OLDGRAFX_ISFUNC_CLR 0xfffffff7
#define PM_OLDGRAFX_ISFUNC_MSB 3
#define PM_OLDGRAFX_ISFUNC_LSB 3
#define PM_OLDGRAFX_ISPOW_BITS 2:2
#define PM_OLDGRAFX_ISPOW_SET 0x00000004
#define PM_OLDGRAFX_ISPOW_CLR 0xfffffffb
#define PM_OLDGRAFX_ISPOW_MSB 2
#define PM_OLDGRAFX_ISPOW_LSB 2
#define PM_OLDGRAFX_POWOK_BITS 1:1
#define PM_OLDGRAFX_POWOK_SET 0x00000002
#define PM_OLDGRAFX_POWOK_CLR 0xfffffffd
#define PM_OLDGRAFX_POWOK_MSB 1
#define PM_OLDGRAFX_POWOK_LSB 1
#define PM_OLDGRAFX_POWUP_BITS 0:0
#define PM_OLDGRAFX_POWUP_SET 0x00000001
#define PM_OLDGRAFX_POWUP_CLR 0xfffffffe
#define PM_OLDGRAFX_POWUP_MSB 0
#define PM_OLDGRAFX_POWUP_LSB 0
#define PM_IMAGE HW_REGISTER_RW( 0x7e100108 )
#define PM_IMAGE_MASK 0x007f01ff
#define PM_IMAGE_WIDTH 23
#define PM_IMAGE_RESET 0000000000
#define PM_IMAGE_CFG_BITS 22:16
#define PM_IMAGE_CFG_SET 0x007f0000
#define PM_IMAGE_CFG_CLR 0xff80ffff
#define PM_IMAGE_CFG_MSB 22
#define PM_IMAGE_CFG_LSB 16
#define PM_IMAGE_ISPRSTN_BITS 8:8
#define PM_IMAGE_ISPRSTN_SET 0x00000100
#define PM_IMAGE_ISPRSTN_CLR 0xfffffeff
#define PM_IMAGE_ISPRSTN_MSB 8
#define PM_IMAGE_ISPRSTN_LSB 8
#define PM_IMAGE_H264RSTN_BITS 7:7
#define PM_IMAGE_H264RSTN_SET 0x00000080
#define PM_IMAGE_H264RSTN_CLR 0xffffff7f
#define PM_IMAGE_H264RSTN_MSB 7
#define PM_IMAGE_H264RSTN_LSB 7
#define PM_IMAGE_PERIRSTN_BITS 6:6
#define PM_IMAGE_PERIRSTN_SET 0x00000040
#define PM_IMAGE_PERIRSTN_CLR 0xffffffbf
#define PM_IMAGE_PERIRSTN_MSB 6
#define PM_IMAGE_PERIRSTN_LSB 6
#define PM_IMAGE_ISFUNC_BITS 5:5
#define PM_IMAGE_ISFUNC_SET 0x00000020
#define PM_IMAGE_ISFUNC_CLR 0xffffffdf
#define PM_IMAGE_ISFUNC_MSB 5
#define PM_IMAGE_ISFUNC_LSB 5
#define PM_IMAGE_MRDONE_BITS 4:4
#define PM_IMAGE_MRDONE_SET 0x00000010
#define PM_IMAGE_MRDONE_CLR 0xffffffef
#define PM_IMAGE_MRDONE_MSB 4
#define PM_IMAGE_MRDONE_LSB 4
#define PM_IMAGE_MEMREP_BITS 3:3
#define PM_IMAGE_MEMREP_SET 0x00000008
#define PM_IMAGE_MEMREP_CLR 0xfffffff7
#define PM_IMAGE_MEMREP_MSB 3
#define PM_IMAGE_MEMREP_LSB 3
#define PM_IMAGE_ISPOW_BITS 2:2
#define PM_IMAGE_ISPOW_SET 0x00000004
#define PM_IMAGE_ISPOW_CLR 0xfffffffb
#define PM_IMAGE_ISPOW_MSB 2
#define PM_IMAGE_ISPOW_LSB 2
#define PM_IMAGE_POWOK_BITS 1:1
#define PM_IMAGE_POWOK_SET 0x00000002
#define PM_IMAGE_POWOK_CLR 0xfffffffd
#define PM_IMAGE_POWOK_MSB 1
#define PM_IMAGE_POWOK_LSB 1
#define PM_IMAGE_POWUP_BITS 0:0
#define PM_IMAGE_POWUP_SET 0x00000001
#define PM_IMAGE_POWUP_CLR 0xfffffffe
#define PM_IMAGE_POWUP_MSB 0
#define PM_IMAGE_POWUP_LSB 0
#define PM_GRAFX HW_REGISTER_RW( 0x7e10010c )
#define PM_GRAFX_MASK 0x007f007f
#define PM_GRAFX_WIDTH 23
#define PM_GRAFX_RESET 0000000000
#define PM_GRAFX_CFG_BITS 22:16
#define PM_GRAFX_CFG_SET 0x007f0000
#define PM_GRAFX_CFG_CLR 0xff80ffff
#define PM_GRAFX_CFG_MSB 22
#define PM_GRAFX_CFG_LSB 16
#define PM_GRAFX_V3DRSTN_BITS 6:6
#define PM_GRAFX_V3DRSTN_SET 0x00000040
#define PM_GRAFX_V3DRSTN_CLR 0xffffffbf
#define PM_GRAFX_V3DRSTN_MSB 6
#define PM_GRAFX_V3DRSTN_LSB 6
#define PM_GRAFX_ISFUNC_BITS 5:5
#define PM_GRAFX_ISFUNC_SET 0x00000020
#define PM_GRAFX_ISFUNC_CLR 0xffffffdf
#define PM_GRAFX_ISFUNC_MSB 5
#define PM_GRAFX_ISFUNC_LSB 5
#define PM_GRAFX_MRDONE_BITS 4:4
#define PM_GRAFX_MRDONE_SET 0x00000010
#define PM_GRAFX_MRDONE_CLR 0xffffffef
#define PM_GRAFX_MRDONE_MSB 4
#define PM_GRAFX_MRDONE_LSB 4
#define PM_GRAFX_MEMREP_BITS 3:3
#define PM_GRAFX_MEMREP_SET 0x00000008
#define PM_GRAFX_MEMREP_CLR 0xfffffff7
#define PM_GRAFX_MEMREP_MSB 3
#define PM_GRAFX_MEMREP_LSB 3
#define PM_GRAFX_ISPOW_BITS 2:2
#define PM_GRAFX_ISPOW_SET 0x00000004
#define PM_GRAFX_ISPOW_CLR 0xfffffffb
#define PM_GRAFX_ISPOW_MSB 2
#define PM_GRAFX_ISPOW_LSB 2
#define PM_GRAFX_POWOK_BITS 1:1
#define PM_GRAFX_POWOK_SET 0x00000002
#define PM_GRAFX_POWOK_CLR 0xfffffffd
#define PM_GRAFX_POWOK_MSB 1
#define PM_GRAFX_POWOK_LSB 1
#define PM_GRAFX_POWUP_BITS 0:0
#define PM_GRAFX_POWUP_SET 0x00000001
#define PM_GRAFX_POWUP_CLR 0xfffffffe
#define PM_GRAFX_POWUP_MSB 0
#define PM_GRAFX_POWUP_LSB 0
#define PM_PROC HW_REGISTER_RW( 0x7e100110 )
#define PM_PROC_MASK 0x007f107f
#define PM_PROC_WIDTH 23
#define PM_PROC_RESET 0000000000
#define PM_PROC_CFG_BITS 22:16
#define PM_PROC_CFG_SET 0x007f0000
#define PM_PROC_CFG_CLR 0xff80ffff
#define PM_PROC_CFG_MSB 22
#define PM_PROC_CFG_LSB 16
#define PM_PROC_ENAB_BITS 12:12
#define PM_PROC_ENAB_SET 0x00001000
#define PM_PROC_ENAB_CLR 0xffffefff
#define PM_PROC_ENAB_MSB 12
#define PM_PROC_ENAB_LSB 12
#define PM_PROC_ARMRSTN_BITS 6:6
#define PM_PROC_ARMRSTN_SET 0x00000040
#define PM_PROC_ARMRSTN_CLR 0xffffffbf
#define PM_PROC_ARMRSTN_MSB 6
#define PM_PROC_ARMRSTN_LSB 6
#define PM_PROC_ISFUNC_BITS 5:5
#define PM_PROC_ISFUNC_SET 0x00000020
#define PM_PROC_ISFUNC_CLR 0xffffffdf
#define PM_PROC_ISFUNC_MSB 5
#define PM_PROC_ISFUNC_LSB 5
#define PM_PROC_MRDONE_BITS 4:4
#define PM_PROC_MRDONE_SET 0x00000010
#define PM_PROC_MRDONE_CLR 0xffffffef
#define PM_PROC_MRDONE_MSB 4
#define PM_PROC_MRDONE_LSB 4
#define PM_PROC_MEMREP_BITS 3:3
#define PM_PROC_MEMREP_SET 0x00000008
#define PM_PROC_MEMREP_CLR 0xfffffff7
#define PM_PROC_MEMREP_MSB 3
#define PM_PROC_MEMREP_LSB 3
#define PM_PROC_ISPOW_BITS 2:2
#define PM_PROC_ISPOW_SET 0x00000004
#define PM_PROC_ISPOW_CLR 0xfffffffb
#define PM_PROC_ISPOW_MSB 2
#define PM_PROC_ISPOW_LSB 2
#define PM_PROC_POWOK_BITS 1:1
#define PM_PROC_POWOK_SET 0x00000002
#define PM_PROC_POWOK_CLR 0xfffffffd
#define PM_PROC_POWOK_MSB 1
#define PM_PROC_POWOK_LSB 1
#define PM_PROC_POWUP_BITS 0:0
#define PM_PROC_POWUP_SET 0x00000001
#define PM_PROC_POWUP_CLR 0xfffffffe
#define PM_PROC_POWUP_MSB 0
#define PM_PROC_POWUP_LSB 0
#define PM_OTPPOR HW_REGISTER_RW( 0x7e100010 )
#define PM_OTPPOR_MASK 0x00ffffff
#define PM_OTPPOR_WIDTH 24
#define PM_OTPPOR_RESET 0000000000
#define PM_OTPPOR_KEY_BITS 23:0
#define PM_OTPPOR_KEY_SET 0x00ffffff
#define PM_OTPPOR_KEY_CLR 0xff000000
#define PM_OTPPOR_KEY_MSB 23
#define PM_OTPPOR_KEY_LSB 0
#define PM_AUDIOPOR HW_REGISTER_RW( 0x7e100014 )
#define PM_AUDIOPOR_MASK 0x00ffffff
#define PM_AUDIOPOR_WIDTH 24
#define PM_AUDIOPOR_RESET 0000000000
#define PM_AUDIOPOR_KEY_BITS 23:0
#define PM_AUDIOPOR_KEY_SET 0x00ffffff
#define PM_AUDIOPOR_KEY_CLR 0xff000000
#define PM_AUDIOPOR_KEY_MSB 23
#define PM_AUDIOPOR_KEY_LSB 0
#define PM_POR HW_REGISTER_RO( 0x7e100018 )
#define PM_POR_MASK 0x000007ff
#define PM_POR_WIDTH 11
#define PM_POR_RESET 0000000000
#define PM_POR_STATUS_BITS 10:0
#define PM_POR_STATUS_SET 0x000007ff
#define PM_POR_STATUS_CLR 0xfffff800
#define PM_POR_STATUS_MSB 10
#define PM_POR_STATUS_LSB 0
#define PM_RSTC HW_REGISTER_RW( 0x7e10001c )
#define PM_RSTC_MASK 0x00333333
#define PM_RSTC_WIDTH 22
#define PM_RSTC_RESET 0x00000102
#define PM_RSTC_HRCFG_BITS 21:20
#define PM_RSTC_HRCFG_SET 0x00300000
#define PM_RSTC_HRCFG_CLR 0xffcfffff
#define PM_RSTC_HRCFG_MSB 21
#define PM_RSTC_HRCFG_LSB 20
#define PM_RSTC_FRCFG_BITS 17:16
#define PM_RSTC_FRCFG_SET 0x00030000
#define PM_RSTC_FRCFG_CLR 0xfffcffff
#define PM_RSTC_FRCFG_MSB 17
#define PM_RSTC_FRCFG_LSB 16
#define PM_RSTC_QRCFG_BITS 13:12
#define PM_RSTC_QRCFG_SET 0x00003000
#define PM_RSTC_QRCFG_CLR 0xffffcfff
#define PM_RSTC_QRCFG_MSB 13
#define PM_RSTC_QRCFG_LSB 12
#define PM_RSTC_SRCFG_BITS 9:8
#define PM_RSTC_SRCFG_SET 0x00000300
#define PM_RSTC_SRCFG_CLR 0xfffffcff
#define PM_RSTC_SRCFG_MSB 9
#define PM_RSTC_SRCFG_LSB 8
#define PM_RSTC_WRCFG_BITS 5:4
#define PM_RSTC_WRCFG_SET 0x00000030
#define PM_RSTC_WRCFG_CLR 0xffffffcf
#define PM_RSTC_WRCFG_MSB 5
#define PM_RSTC_WRCFG_LSB 4
#define PM_RSTC_DRCFG_BITS 1:0
#define PM_RSTC_DRCFG_SET 0x00000003
#define PM_RSTC_DRCFG_CLR 0xfffffffc
#define PM_RSTC_DRCFG_MSB 1
#define PM_RSTC_DRCFG_LSB 0
#define PM_RSTS HW_REGISTER_RW( 0x7e100020 )
#define PM_RSTS_MASK 0x00001777
#define PM_RSTS_WIDTH 13
#define PM_RSTS_RESET 0x00001000
#define PM_RSTS_HADPOR_BITS 12:12
#define PM_RSTS_HADPOR_SET 0x00001000
#define PM_RSTS_HADPOR_CLR 0xffffefff
#define PM_RSTS_HADPOR_MSB 12
#define PM_RSTS_HADPOR_LSB 12
#define PM_RSTS_HADSRH_BITS 10:10
#define PM_RSTS_HADSRH_SET 0x00000400
#define PM_RSTS_HADSRH_CLR 0xfffffbff
#define PM_RSTS_HADSRH_MSB 10
#define PM_RSTS_HADSRH_LSB 10
#define PM_RSTS_HADSRF_BITS 9:9
#define PM_RSTS_HADSRF_SET 0x00000200
#define PM_RSTS_HADSRF_CLR 0xfffffdff
#define PM_RSTS_HADSRF_MSB 9
#define PM_RSTS_HADSRF_LSB 9
#define PM_RSTS_HADSRQ_BITS 8:8
#define PM_RSTS_HADSRQ_SET 0x00000100
#define PM_RSTS_HADSRQ_CLR 0xfffffeff
#define PM_RSTS_HADSRQ_MSB 8
#define PM_RSTS_HADSRQ_LSB 8
#define PM_RSTS_HADWRH_BITS 6:6
#define PM_RSTS_HADWRH_SET 0x00000040
#define PM_RSTS_HADWRH_CLR 0xffffffbf
#define PM_RSTS_HADWRH_MSB 6
#define PM_RSTS_HADWRH_LSB 6
#define PM_RSTS_HADWRF_BITS 5:5
#define PM_RSTS_HADWRF_SET 0x00000020
#define PM_RSTS_HADWRF_CLR 0xffffffdf
#define PM_RSTS_HADWRF_MSB 5
#define PM_RSTS_HADWRF_LSB 5
#define PM_RSTS_HADWRQ_BITS 4:4
#define PM_RSTS_HADWRQ_SET 0x00000010
#define PM_RSTS_HADWRQ_CLR 0xffffffef
#define PM_RSTS_HADWRQ_MSB 4
#define PM_RSTS_HADWRQ_LSB 4
#define PM_RSTS_HADDRH_BITS 2:2
#define PM_RSTS_HADDRH_SET 0x00000004
#define PM_RSTS_HADDRH_CLR 0xfffffffb
#define PM_RSTS_HADDRH_MSB 2
#define PM_RSTS_HADDRH_LSB 2
#define PM_RSTS_HADDRF_BITS 1:1
#define PM_RSTS_HADDRF_SET 0x00000002
#define PM_RSTS_HADDRF_CLR 0xfffffffd
#define PM_RSTS_HADDRF_MSB 1
#define PM_RSTS_HADDRF_LSB 1
#define PM_RSTS_HADDRQ_BITS 0:0
#define PM_RSTS_HADDRQ_SET 0x00000001
#define PM_RSTS_HADDRQ_CLR 0xfffffffe
#define PM_RSTS_HADDRQ_MSB 0
#define PM_RSTS_HADDRQ_LSB 0
#define PM_WDOG HW_REGISTER_RW( 0x7e100024 )
#define PM_WDOG_MASK 0x00000fff
#define PM_WDOG_WIDTH 12
#define PM_WDOG_RESET 0000000000
#define PM_WDOG_TIME_BITS 11:0
#define PM_WDOG_TIME_SET 0x00000fff
#define PM_WDOG_TIME_CLR 0xfffff000
#define PM_WDOG_TIME_MSB 11
#define PM_WDOG_TIME_LSB 0
#define PM_PADS0 HW_REGISTER_RW( 0x7e100028 )
#define PM_PADS0_MASK 0x0000003f
#define PM_PADS0_WIDTH 6
#define PM_PADS0_RESET 0x0000001b
#define PM_PADS0_DRIVE_BITS 2:0
#define PM_PADS0_DRIVE_SET 0x00000007
#define PM_PADS0_DRIVE_CLR 0xfffffff8
#define PM_PADS0_DRIVE_MSB 2
#define PM_PADS0_DRIVE_LSB 0
#define PM_PADS0_HYST_BITS 3:3
#define PM_PADS0_HYST_SET 0x00000008
#define PM_PADS0_HYST_CLR 0xfffffff7
#define PM_PADS0_HYST_MSB 3
#define PM_PADS0_HYST_LSB 3
#define PM_PADS0_SLEW_BITS 4:4
#define PM_PADS0_SLEW_SET 0x00000010
#define PM_PADS0_SLEW_CLR 0xffffffef
#define PM_PADS0_SLEW_MSB 4
#define PM_PADS0_SLEW_LSB 4
#define PM_PADS0_POWOK_BITS 5:5
#define PM_PADS0_POWOK_SET 0x00000020
#define PM_PADS0_POWOK_CLR 0xffffffdf
#define PM_PADS0_POWOK_MSB 5
#define PM_PADS0_POWOK_LSB 5
#define PM_PADS2 HW_REGISTER_RW( 0x7e10002c )
#define PM_PADS2_MASK 0x0000003f
#define PM_PADS2_WIDTH 6
#define PM_PADS2_RESET 0x0000001b
#define PM_PADS2_DRIVE_BITS 2:0
#define PM_PADS2_DRIVE_SET 0x00000007
#define PM_PADS2_DRIVE_CLR 0xfffffff8
#define PM_PADS2_DRIVE_MSB 2
#define PM_PADS2_DRIVE_LSB 0
#define PM_PADS2_HYST_BITS 3:3
#define PM_PADS2_HYST_SET 0x00000008
#define PM_PADS2_HYST_CLR 0xfffffff7
#define PM_PADS2_HYST_MSB 3
#define PM_PADS2_HYST_LSB 3
#define PM_PADS2_SLEW_BITS 4:4
#define PM_PADS2_SLEW_SET 0x00000010
#define PM_PADS2_SLEW_CLR 0xffffffef
#define PM_PADS2_SLEW_MSB 4
#define PM_PADS2_SLEW_LSB 4
#define PM_PADS2_POWOK_BITS 5:5
#define PM_PADS2_POWOK_SET 0x00000020
#define PM_PADS2_POWOK_CLR 0xffffffdf
#define PM_PADS2_POWOK_MSB 5
#define PM_PADS2_POWOK_LSB 5
#define PM_PADS3 HW_REGISTER_RW( 0x7e100030 )
#define PM_PADS3_MASK 0x0000003f
#define PM_PADS3_WIDTH 6
#define PM_PADS3_RESET 0x0000001b
#define PM_PADS3_DRIVE_BITS 2:0
#define PM_PADS3_DRIVE_SET 0x00000007
#define PM_PADS3_DRIVE_CLR 0xfffffff8
#define PM_PADS3_DRIVE_MSB 2
#define PM_PADS3_DRIVE_LSB 0
#define PM_PADS3_HYST_BITS 3:3
#define PM_PADS3_HYST_SET 0x00000008
#define PM_PADS3_HYST_CLR 0xfffffff7
#define PM_PADS3_HYST_MSB 3
#define PM_PADS3_HYST_LSB 3
#define PM_PADS3_SLEW_BITS 4:4
#define PM_PADS3_SLEW_SET 0x00000010
#define PM_PADS3_SLEW_CLR 0xffffffef
#define PM_PADS3_SLEW_MSB 4
#define PM_PADS3_SLEW_LSB 4
#define PM_PADS3_POWOK_BITS 5:5
#define PM_PADS3_POWOK_SET 0x00000020
#define PM_PADS3_POWOK_CLR 0xffffffdf
#define PM_PADS3_POWOK_MSB 5
#define PM_PADS3_POWOK_LSB 5
#define PM_PADS4 HW_REGISTER_RW( 0x7e100034 )
#define PM_PADS4_MASK 0x0000003f
#define PM_PADS4_WIDTH 6
#define PM_PADS4_RESET 0x0000001b
#define PM_PADS4_DRIVE_BITS 2:0
#define PM_PADS4_DRIVE_SET 0x00000007
#define PM_PADS4_DRIVE_CLR 0xfffffff8
#define PM_PADS4_DRIVE_MSB 2
#define PM_PADS4_DRIVE_LSB 0
#define PM_PADS4_HYST_BITS 3:3
#define PM_PADS4_HYST_SET 0x00000008
#define PM_PADS4_HYST_CLR 0xfffffff7
#define PM_PADS4_HYST_MSB 3
#define PM_PADS4_HYST_LSB 3
#define PM_PADS4_SLEW_BITS 4:4
#define PM_PADS4_SLEW_SET 0x00000010
#define PM_PADS4_SLEW_CLR 0xffffffef
#define PM_PADS4_SLEW_MSB 4
#define PM_PADS4_SLEW_LSB 4
#define PM_PADS4_POWOK_BITS 5:5
#define PM_PADS4_POWOK_SET 0x00000020
#define PM_PADS4_POWOK_CLR 0xffffffdf
#define PM_PADS4_POWOK_MSB 5
#define PM_PADS4_POWOK_LSB 5
#define PM_PADS5 HW_REGISTER_RW( 0x7e100038 )
#define PM_PADS5_MASK 0x0000007f
#define PM_PADS5_WIDTH 7
#define PM_PADS5_RESET 0x0000001b
#define PM_PADS5_DRIVE_BITS 2:0
#define PM_PADS5_DRIVE_SET 0x00000007
#define PM_PADS5_DRIVE_CLR 0xfffffff8
#define PM_PADS5_DRIVE_MSB 2
#define PM_PADS5_DRIVE_LSB 0
#define PM_PADS5_HYST_BITS 3:3
#define PM_PADS5_HYST_SET 0x00000008
#define PM_PADS5_HYST_CLR 0xfffffff7
#define PM_PADS5_HYST_MSB 3
#define PM_PADS5_HYST_LSB 3
#define PM_PADS5_SLEW_BITS 4:4
#define PM_PADS5_SLEW_SET 0x00000010
#define PM_PADS5_SLEW_CLR 0xffffffef
#define PM_PADS5_SLEW_MSB 4
#define PM_PADS5_SLEW_LSB 4
#define PM_PADS5_POWOK_BITS 5:5
#define PM_PADS5_POWOK_SET 0x00000020
#define PM_PADS5_POWOK_CLR 0xffffffdf
#define PM_PADS5_POWOK_MSB 5
#define PM_PADS5_POWOK_LSB 5
#define PM_PADS5_I2CMODE_BITS 6:6
#define PM_PADS5_I2CMODE_SET 0x00000040
#define PM_PADS5_I2CMODE_CLR 0xffffffbf
#define PM_PADS5_I2CMODE_MSB 6
#define PM_PADS5_I2CMODE_LSB 6
#define PM_PADS6 HW_REGISTER_RW( 0x7e10003c )
#define PM_PADS6_MASK 0x00000023
#define PM_PADS6_WIDTH 6
#define PM_PADS6_RESET 0000000000
#define PM_PADS6_DRIVE_BITS 1:0
#define PM_PADS6_DRIVE_SET 0x00000003
#define PM_PADS6_DRIVE_CLR 0xfffffffc
#define PM_PADS6_DRIVE_MSB 1
#define PM_PADS6_DRIVE_LSB 0
#define PM_PADS6_POWOK_BITS 5:5
#define PM_PADS6_POWOK_SET 0x00000020
#define PM_PADS6_POWOK_CLR 0xffffffdf
#define PM_PADS6_POWOK_MSB 5
#define PM_PADS6_POWOK_LSB 5
#define PM_MEMS HW_REGISTER_RW( 0x7e100040 )
#define PM_MEMS_MASK 0x00000001
#define PM_MEMS_WIDTH 1
#define PM_MEMS_RESET 0000000000
#define PM_MEMS_LOWVOLT_BITS 0:0
#define PM_MEMS_LOWVOLT_SET 0x00000001
#define PM_MEMS_LOWVOLT_CLR 0xfffffffe
#define PM_MEMS_LOWVOLT_MSB 0
#define PM_MEMS_LOWVOLT_LSB 0
#define PM_CAM0 HW_REGISTER_RW( 0x7e100044 )
#define PM_CAM0_MASK 0x001fffff
#define PM_CAM0_WIDTH 21
#define PM_CAM0_RESET 0000000000
#define PM_CAM0_CTRLEN_BITS 0:0
#define PM_CAM0_CTRLEN_SET 0x00000001
#define PM_CAM0_CTRLEN_CLR 0xfffffffe
#define PM_CAM0_CTRLEN_MSB 0
#define PM_CAM0_CTRLEN_LSB 0
#define PM_CAM0_LDOLPEN_BITS 1:1
#define PM_CAM0_LDOLPEN_SET 0x00000002
#define PM_CAM0_LDOLPEN_CLR 0xfffffffd
#define PM_CAM0_LDOLPEN_MSB 1
#define PM_CAM0_LDOLPEN_LSB 1
#define PM_CAM0_LDOHPEN_BITS 2:2
#define PM_CAM0_LDOHPEN_SET 0x00000004
#define PM_CAM0_LDOHPEN_CLR 0xfffffffb
#define PM_CAM0_LDOHPEN_MSB 2
#define PM_CAM0_LDOHPEN_LSB 2
#define PM_CAM0_LDOCTRL_BITS 20:3
#define PM_CAM0_LDOCTRL_SET 0x001ffff8
#define PM_CAM0_LDOCTRL_CLR 0xffe00007
#define PM_CAM0_LDOCTRL_MSB 20
#define PM_CAM0_LDOCTRL_LSB 3
#define PM_CAM1 HW_REGISTER_RW( 0x7e100048 )
#define PM_CAM1_MASK 0x001fffff
#define PM_CAM1_WIDTH 21
#define PM_CAM1_RESET 0000000000
#define PM_CAM1_CTRLEN_BITS 0:0
#define PM_CAM1_CTRLEN_SET 0x00000001
#define PM_CAM1_CTRLEN_CLR 0xfffffffe
#define PM_CAM1_CTRLEN_MSB 0
#define PM_CAM1_CTRLEN_LSB 0
#define PM_CAM1_LDOLPEN_BITS 1:1
#define PM_CAM1_LDOLPEN_SET 0x00000002
#define PM_CAM1_LDOLPEN_CLR 0xfffffffd
#define PM_CAM1_LDOLPEN_MSB 1
#define PM_CAM1_LDOLPEN_LSB 1
#define PM_CAM1_LDOHPEN_BITS 2:2
#define PM_CAM1_LDOHPEN_SET 0x00000004
#define PM_CAM1_LDOHPEN_CLR 0xfffffffb
#define PM_CAM1_LDOHPEN_MSB 2
#define PM_CAM1_LDOHPEN_LSB 2
#define PM_CAM1_LDOCTRL_BITS 20:3
#define PM_CAM1_LDOCTRL_SET 0x001ffff8
#define PM_CAM1_LDOCTRL_CLR 0xffe00007
#define PM_CAM1_LDOCTRL_MSB 20
#define PM_CAM1_LDOCTRL_LSB 3
#define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c )
#define PM_CCP2TX_MASK 0x0007ffff
#define PM_CCP2TX_WIDTH 19
#define PM_CCP2TX_RESET 0000000000
#define PM_CCP2TX_CTRLEN_BITS 0:0
#define PM_CCP2TX_CTRLEN_SET 0x00000001
#define PM_CCP2TX_CTRLEN_CLR 0xfffffffe
#define PM_CCP2TX_CTRLEN_MSB 0
#define PM_CCP2TX_CTRLEN_LSB 0
#define PM_CCP2TX_LDOEN_BITS 1:1
#define PM_CCP2TX_LDOEN_SET 0x00000002
#define PM_CCP2TX_LDOEN_CLR 0xfffffffd
#define PM_CCP2TX_LDOEN_MSB 1
#define PM_CCP2TX_LDOEN_LSB 1
#define PM_CCP2TX_LDOCTRL_BITS 18:2
#define PM_CCP2TX_LDOCTRL_SET 0x0007fffc
#define PM_CCP2TX_LDOCTRL_CLR 0xfff80003
#define PM_CCP2TX_LDOCTRL_MSB 18
#define PM_CCP2TX_LDOCTRL_LSB 2
#define PM_DSI0 HW_REGISTER_RW( 0x7e100050 )
#define PM_DSI0_MASK 0x001fffff
#define PM_DSI0_WIDTH 21
#define PM_DSI0_RESET 0000000000
#define PM_DSI0_CTRLEN_BITS 0:0
#define PM_DSI0_CTRLEN_SET 0x00000001
#define PM_DSI0_CTRLEN_CLR 0xfffffffe
#define PM_DSI0_CTRLEN_MSB 0
#define PM_DSI0_CTRLEN_LSB 0
#define PM_DSI0_LDOLPEN_BITS 1:1
#define PM_DSI0_LDOLPEN_SET 0x00000002
#define PM_DSI0_LDOLPEN_CLR 0xfffffffd
#define PM_DSI0_LDOLPEN_MSB 1
#define PM_DSI0_LDOLPEN_LSB 1
#define PM_DSI0_LDOHPEN_BITS 2:2
#define PM_DSI0_LDOHPEN_SET 0x00000004
#define PM_DSI0_LDOHPEN_CLR 0xfffffffb
#define PM_DSI0_LDOHPEN_MSB 2
#define PM_DSI0_LDOHPEN_LSB 2
#define PM_DSI0_LDOCTRL_BITS 20:3
#define PM_DSI0_LDOCTRL_SET 0x001ffff8
#define PM_DSI0_LDOCTRL_CLR 0xffe00007
#define PM_DSI0_LDOCTRL_MSB 20
#define PM_DSI0_LDOCTRL_LSB 3
#define PM_DSI1 HW_REGISTER_RW( 0x7e100054 )
#define PM_DSI1_MASK 0x001fffff
#define PM_DSI1_WIDTH 21
#define PM_DSI1_RESET 0000000000
#define PM_DSI1_CTRLEN_BITS 0:0
#define PM_DSI1_CTRLEN_SET 0x00000001
#define PM_DSI1_CTRLEN_CLR 0xfffffffe
#define PM_DSI1_CTRLEN_MSB 0
#define PM_DSI1_CTRLEN_LSB 0
#define PM_DSI1_LDOLPEN_BITS 1:1
#define PM_DSI1_LDOLPEN_SET 0x00000002
#define PM_DSI1_LDOLPEN_CLR 0xfffffffd
#define PM_DSI1_LDOLPEN_MSB 1
#define PM_DSI1_LDOLPEN_LSB 1
#define PM_DSI1_LDOHPEN_BITS 2:2
#define PM_DSI1_LDOHPEN_SET 0x00000004
#define PM_DSI1_LDOHPEN_CLR 0xfffffffb
#define PM_DSI1_LDOHPEN_MSB 2
#define PM_DSI1_LDOHPEN_LSB 2
#define PM_DSI1_LDOCTRL_BITS 20:3
#define PM_DSI1_LDOCTRL_SET 0x001ffff8
#define PM_DSI1_LDOCTRL_CLR 0xffe00007
#define PM_DSI1_LDOCTRL_MSB 20
#define PM_DSI1_LDOCTRL_LSB 3
#define PM_HDMI HW_REGISTER_RW( 0x7e100058 )
#define PM_HDMI_MASK 0x000fffff
#define PM_HDMI_WIDTH 20
#define PM_HDMI_RESET 0x00000002
#define PM_HDMI_CTRLEN_BITS 0:0
#define PM_HDMI_CTRLEN_SET 0x00000001
#define PM_HDMI_CTRLEN_CLR 0xfffffffe
#define PM_HDMI_CTRLEN_MSB 0
#define PM_HDMI_CTRLEN_LSB 0
#define PM_HDMI_LDOPD_BITS 1:1
#define PM_HDMI_LDOPD_SET 0x00000002
#define PM_HDMI_LDOPD_CLR 0xfffffffd
#define PM_HDMI_LDOPD_MSB 1
#define PM_HDMI_LDOPD_LSB 1
#define PM_HDMI_LDOCTRL_BITS 18:2
#define PM_HDMI_LDOCTRL_SET 0x0007fffc
#define PM_HDMI_LDOCTRL_CLR 0xfff80003
#define PM_HDMI_LDOCTRL_MSB 18
#define PM_HDMI_LDOCTRL_LSB 2
#define PM_HDMI_RSTDR_BITS 19:19
#define PM_HDMI_RSTDR_SET 0x00080000
#define PM_HDMI_RSTDR_CLR 0xfff7ffff
#define PM_HDMI_RSTDR_MSB 19
#define PM_HDMI_RSTDR_LSB 19
#define PM_USB HW_REGISTER_RW( 0x7e10005c )
#define PM_USB_MASK 0x00000001
#define PM_USB_WIDTH 1
#define PM_USB_RESET 0000000000
#define PM_USB_CTRLEN_BITS 0:0
#define PM_USB_CTRLEN_SET 0x00000001
#define PM_USB_CTRLEN_CLR 0xfffffffe
#define PM_USB_CTRLEN_MSB 0
#define PM_USB_CTRLEN_LSB 0
#define PM_PXLDO HW_REGISTER_RW( 0x7e100060 )
#define PM_PXLDO_MASK 0x0003ffff
#define PM_PXLDO_WIDTH 18
#define PM_PXLDO_RESET 0000000000
#define PM_PXLDO_CTRL_BITS 15:0
#define PM_PXLDO_CTRL_SET 0x0000ffff
#define PM_PXLDO_CTRL_CLR 0xffff0000
#define PM_PXLDO_CTRL_MSB 15
#define PM_PXLDO_CTRL_LSB 0
#define PM_PXLDO_RSTOSCDR_BITS 16:16
#define PM_PXLDO_RSTOSCDR_SET 0x00010000
#define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff
#define PM_PXLDO_RSTOSCDR_MSB 16
#define PM_PXLDO_RSTOSCDR_LSB 16
#define PM_PXLDO_RSTPLLDR_BITS 17:17
#define PM_PXLDO_RSTPLLDR_SET 0x00020000
#define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff
#define PM_PXLDO_RSTPLLDR_MSB 17
#define PM_PXLDO_RSTPLLDR_LSB 17
#define PM_PXBG HW_REGISTER_RW( 0x7e100064 )
#define PM_PXBG_MASK 0x0000ffff
#define PM_PXBG_WIDTH 16
#define PM_PXBG_RESET 0000000000
#define PM_PXBG_CTRL_BITS 15:0
#define PM_PXBG_CTRL_SET 0x0000ffff
#define PM_PXBG_CTRL_CLR 0xffff0000
#define PM_PXBG_CTRL_MSB 15
#define PM_PXBG_CTRL_LSB 0
#define PM_DFT HW_REGISTER_RW( 0x7e100068 )
#define PM_DFT_MASK 0x00000003
#define PM_DFT_WIDTH 2
#define PM_DFT_RESET 0000000000
#define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0
#define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001
#define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe
#define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0
#define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0
#define PM_DFT_STOPALLCLOCKS_BITS 1:1
#define PM_DFT_STOPALLCLOCKS_SET 0x00000002
#define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd
#define PM_DFT_STOPALLCLOCKS_MSB 1
#define PM_DFT_STOPALLCLOCKS_LSB 1
#define PM_SMPS HW_REGISTER_RW( 0x7e10006c )
#define PM_SMPS_MASK 0x00000007
#define PM_SMPS_WIDTH 3
#define PM_SMPS_RESET 0000000000
#define PM_SMPS_CTRLEN_BITS 0:0
#define PM_SMPS_CTRLEN_SET 0x00000001
#define PM_SMPS_CTRLEN_CLR 0xfffffffe
#define PM_SMPS_CTRLEN_MSB 0
#define PM_SMPS_CTRLEN_LSB 0
#define PM_SMPS_RSTDR_BITS 1:1
#define PM_SMPS_RSTDR_SET 0x00000002
#define PM_SMPS_RSTDR_CLR 0xfffffffd
#define PM_SMPS_RSTDR_MSB 1
#define PM_SMPS_RSTDR_LSB 1
#define PM_SMPS_UPEN_BITS 2:2
#define PM_SMPS_UPEN_SET 0x00000004
#define PM_SMPS_UPEN_CLR 0xfffffffb
#define PM_SMPS_UPEN_MSB 2
#define PM_SMPS_UPEN_LSB 2
#define PM_XOSC HW_REGISTER_RW( 0x7e100070 )
#define PM_XOSC_MASK 0x00000001
#define PM_XOSC_WIDTH 1
#define PM_XOSC_RESET 0000000000
#define PM_XOSC_USESEC_BITS 0:0
#define PM_XOSC_USESEC_SET 0x00000001
#define PM_XOSC_USESEC_CLR 0xfffffffe
#define PM_XOSC_USESEC_MSB 0
#define PM_XOSC_USESEC_LSB 0
#define PM_SPAREW HW_REGISTER_RW( 0x7e100074 )
#define PM_SPAREW_MASK 0x00ffffff
#define PM_SPAREW_WIDTH 24
#define PM_SPAREW_RESET 0000000000
#define PM_SPAREW_SPARE_BITS 23:0
#define PM_SPAREW_SPARE_SET 0x00ffffff
#define PM_SPAREW_SPARE_CLR 0xff000000
#define PM_SPAREW_SPARE_MSB 23
#define PM_SPAREW_SPARE_LSB 0
#define PM_SPARER HW_REGISTER_RO( 0x7e100078 )
#define PM_SPARER_MASK 0x00ffffff
#define PM_SPARER_WIDTH 24
#define PM_SPARER_RESET 0000000000
#define PM_SPARER_SPARE_BITS 23:0
#define PM_SPARER_SPARE_SET 0x00ffffff
#define PM_SPARER_SPARE_CLR 0xff000000
#define PM_SPARER_SPARE_MSB 23
#define PM_SPARER_SPARE_LSB 0
#define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc )
#define PM_DUMMY_MASK 0x00000001
#define PM_DUMMY_WIDTH 1
#define PM_DUMMY_RESET 0x00000001
#define PM_DUMMY_ONE_BITS 0:0
#define PM_DUMMY_ONE_SET 0x00000001
#define PM_DUMMY_ONE_CLR 0xfffffffe
#define PM_DUMMY_ONE_MSB 0
#define PM_DUMMY_ONE_LSB 0

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bcm2708_chip/cryptohw.h Executable file
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/*=============================================================================
Copyright (c) 2007 Broadcom Europe Limited. All rights reserved.
Project : BCM2707
Module : CRYPTO wrapper hardware header
File : $RCSfile: cryptohw.h,v $
Revision : $Revision: 1.2 $
FILE DESCRIPTION
Definition of bits within CRYPTO hardware registers.
=============================================================================*/
#ifndef CRYPTOHW_H
#define CRYPTOHW_H
#define CRYPTO_READFIELD(_w,_f) (((unsigned long)(_w) / _f) & (_f##_MASK))
enum
{
// BCM2707 has no crypto hardware but supports RNG interrupt
// CRYPTO_ISR_RNG_INT = (1 << 2),
CRYPTO_ISR_PKA_INT = (1 << 1),
CRYPTO_ISR_SPU_INT = (1 << 0),
// CRYPTO_IMR_RNG_INT_EN = (1 << 2),
CRYPTO_IMR_PKA_INT_EN = (1 << 1),
CRYPTO_IMR_SPU_INT_EN = (1 << 0),
CRYPTO_CLK_CFG_PKA_CLK = (1 << 8),
CRYPTO_CLK_CFG_PKA_CLK_MASK = 3,
CRYPTO_CLK_CFG_PKA_CLK_FULL = 0,
CRYPTO_CLK_CFG_PKA_CLK_HALF = 1,
CRYPTO_CLK_CFG_PKA_CLK_THIRD = 2,
CRYPTO_CLK_CFG_PKA_CLK_DISABLED = 3,
CRYPTO_CLK_CFG_SPU_CLK = (1 << 4),
CRYPTO_CLK_CFG_SPU_CLK_MASK = 3,
CRYPTO_CLK_CFG_SPU_CLK_FULL = 0,
CRYPTO_CLK_CFG_SPU_CLK_HALF = 1,
CRYPTO_CLK_CFG_SPU_CLK_THIRD = 2,
CRYPTO_CLK_CFG_SPU_CLK_DISABLED = 3,
CRYPTO_CLK_CFG_OTP_CLKDIV = (1 << 0),
CRYPTO_CLK_CFG_OTP_CLKDIV_MASK = 0xf,
CRYPTO_CLK_CFG_OTP_CLKDIV_2 = 0x0,
CRYPTO_CLK_CFG_OTP_CLKDIV_4 = 0x1,
CRYPTO_CLK_CFG_OTP_CLKDIV_6 = 0x2,
CRYPTO_CLK_CFG_OTP_CLKDIV_8 = 0x3,
CRYPTO_CLK_CFG_OTP_CLKDIV_10 = 0x4,
CRYPTO_CLK_CFG_OTP_CLKDIV_12 = 0x5,
CRYPTO_CLK_CFG_OTP_CLKDIV_14 = 0x6,
CRYPTO_CLK_CFG_OTP_CLKDIV_16 = 0x7,
CRYPTO_CLK_CFG_OTP_CLKDIV_18 = 0x8,
CRYPTO_CLK_CFG_OTP_CLKDIV_20 = 0x9,
CRYPTO_CLK_CFG_OTP_CLKDIV_22 = 0xa,
CRYPTO_CLK_CFG_OTP_CLKDIV_24 = 0xb,
CRYPTO_CLK_CFG_OTP_CLKDIV_26 = 0xc,
CRYPTO_CLK_CFG_OTP_CLKDIV_28 = 0xd,
CRYPTO_CLK_CFG_OTP_CLKDIV_30 = 0xe,
CRYPTO_CLK_CFG_OTP_CLKDIV_32 = 0xf,
CRYPTO_SIMCTRL_DEBUG = (1 << 0),
CRYPTO_SIMCTRL_SECURE = (1 << 1)
};
#endif

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bcm2708_chip/csi2.h Executable file
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// This file was generated by the create_regs script
#define CS_BASE 0x7e802000
#define CS_APB_ID 0x43534932
#define CS_RC HW_REGISTER_RW( 0x7e802000 )
#define CS_RC_MASK 0xffffc07f
#define CS_RC_WIDTH 32
#define CS_RC_RESET 0x77ce0000
#define CS_RC_CTATADJ_MSB 31
#define CS_RC_CTATADJ_LSB 28
#define CS_RC_PTATADJ_MSB 27
#define CS_RC_PTATADJ_LSB 24
#define CS_RC_RPP_MSB 23
#define CS_RC_RPP_LSB 20
#define CS_RC_RNP_MSB 19
#define CS_RC_RNP_LSB 19
#define CS_RC_BPD_MSB 18
#define CS_RC_BPD_LSB 18
#define CS_RC_APD_MSB 17
#define CS_RC_APD_LSB 17
#define CS_RC_FOE_MSB 16
#define CS_RC_FOE_LSB 16
#define CS_RC_FOF_MSB 15
#define CS_RC_FOF_LSB 15
#define CS_RC_RSYN_MSB 14
#define CS_RC_RSYN_LSB 14
#define CS_RC_F16B_MSB 6
#define CS_RC_F16B_LSB 6
#define CS_RC_GEN_MSB 5
#define CS_RC_GEN_LSB 5
#define CS_RC_LENC_MSB 4
#define CS_RC_LENC_LSB 4
#define CS_RC_LEN4_MSB 3
#define CS_RC_LEN4_LSB 3
#define CS_RC_LEN3_MSB 2
#define CS_RC_LEN3_LSB 2
#define CS_RC_LEN2_MSB 1
#define CS_RC_LEN2_LSB 1
#define CS_RC_LEN1_MSB 0
#define CS_RC_LEN1_LSB 0
#define CS_RS HW_REGISTER_RW( 0x7e802004 )
#define CS_RS_MASK 0x0000033f
#define CS_RS_WIDTH 10
#define CS_RS_RESET 0000000000
#define CS_RS_IS1_MSB 9
#define CS_RS_IS1_LSB 9
#define CS_RS_IS0_MSB 8
#define CS_RS_IS0_LSB 8
#define CS_RS_OFF_MSB 5
#define CS_RS_OFF_LSB 5
#define CS_RS_OFP_MSB 4
#define CS_RS_OFP_LSB 4
#define CS_RS_PEC_MSB 3
#define CS_RS_PEC_LSB 3
#define CS_RS_PED_MSB 2
#define CS_RS_PED_LSB 2
#define CS_RS_OEB_MSB 1
#define CS_RS_OEB_LSB 1
#define CS_RS_GEF_MSB 0
#define CS_RS_GEF_LSB 0
#define CS_RDLS HW_REGISTER_RW( 0x7e802008 )
#define CS_RDLS_MASK 0x3fffffff
#define CS_RDLS_WIDTH 30
#define CS_RDLS_RESET 0000000000
#define CS_RDLS_CEC_MSB 29
#define CS_RDLS_CEC_LSB 29
#define CS_RDLS_ESEC_MSB 28
#define CS_RDLS_ESEC_LSB 28
#define CS_RDLS_EEEC_MSB 27
#define CS_RDLS_EEEC_LSB 27
#define CS_RDLS_SOTSEC_MSB 26
#define CS_RDLS_SOTSEC_LSB 26
#define CS_RDLS_SOTEC_MSB 25
#define CS_RDLS_SOTEC_LSB 25
#define CS_RDLS_ULPSC_MSB 24
#define CS_RDLS_ULPSC_LSB 24
#define CS_RDLS_CE4_MSB 23
#define CS_RDLS_CE4_LSB 23
#define CS_RDLS_ESE4_MSB 22
#define CS_RDLS_ESE4_LSB 22
#define CS_RDLS_EEE4_MSB 21
#define CS_RDLS_EEE4_LSB 21
#define CS_RDLS_SOTSE4_MSB 20
#define CS_RDLS_SOTSE4_LSB 20
#define CS_RDLS_SOTE4_MSB 19
#define CS_RDLS_SOTE4_LSB 19
#define CS_RDLS_ULPS4_MSB 18
#define CS_RDLS_ULPS4_LSB 18
#define CS_RDLS_CE3_MSB 17
#define CS_RDLS_CE3_LSB 17
#define CS_RDLS_ESE3_MSB 16
#define CS_RDLS_ESE3_LSB 16
#define CS_RDLS_EEE3_MSB 15
#define CS_RDLS_EEE3_LSB 15
#define CS_RDLS_SOTSE3_MSB 14
#define CS_RDLS_SOTSE3_LSB 14
#define CS_RDLS_SOTE3_MSB 13
#define CS_RDLS_SOTE3_LSB 13
#define CS_RDLS_ULPS3_MSB 12
#define CS_RDLS_ULPS3_LSB 12
#define CS_RDLS_CE2_MSB 11
#define CS_RDLS_CE2_LSB 11
#define CS_RDLS_ESE2_MSB 10
#define CS_RDLS_ESE2_LSB 10
#define CS_RDLS_EEE2_MSB 9
#define CS_RDLS_EEE2_LSB 9
#define CS_RDLS_SOTSE2_MSB 8
#define CS_RDLS_SOTSE2_LSB 8
#define CS_RDLS_SOTE2_MSB 7
#define CS_RDLS_SOTE2_LSB 7
#define CS_RDLS_ULPS2_MSB 6
#define CS_RDLS_ULPS2_LSB 6
#define CS_RDLS_CE1_MSB 5
#define CS_RDLS_CE1_LSB 5
#define CS_RDLS_ESE1_MSB 4
#define CS_RDLS_ESE1_LSB 4
#define CS_RDLS_EEE1_MSB 3
#define CS_RDLS_EEE1_LSB 3
#define CS_RDLS_SOTSE1_MSB 2
#define CS_RDLS_SOTSE1_LSB 2
#define CS_RDLS_SOTE1_MSB 1
#define CS_RDLS_SOTE1_LSB 1
#define CS_RDLS_ULPS1_MSB 0
#define CS_RDLS_ULPS1_LSB 0
#define CS_RGSP HW_REGISTER_RO( 0x7e80200c )
#define CS_RGSP_MASK 0x00ffffff
#define CS_RGSP_WIDTH 24
#define CS_RGSP_DATA_MSB 23
#define CS_RGSP_DATA_LSB 8
#define CS_RGSP_VC_MSB 7
#define CS_RGSP_VC_LSB 6
#define CS_RGSP_DT_MSB 5
#define CS_RGSP_DT_LSB 0
#define CS_TREN HW_REGISTER_RW( 0x7e802010 )
#define CS_TREN_MASK 0x000003ff
#define CS_TREN_WIDTH 10
#define CS_TREN_RESET 0000000000
#define CS_TREN_TROVC_MSB 9
#define CS_TREN_TROVC_LSB 9
#define CS_TREN_TROV4_MSB 8
#define CS_TREN_TROV4_LSB 8
#define CS_TREN_TROV3_MSB 7
#define CS_TREN_TROV3_LSB 7
#define CS_TREN_TROV2_MSB 6
#define CS_TREN_TROV2_LSB 6
#define CS_TREN_TROV1_MSB 5
#define CS_TREN_TROV1_LSB 5
#define CS_TREN_TRENC_MSB 4
#define CS_TREN_TRENC_LSB 4
#define CS_TREN_TREN4_MSB 3
#define CS_TREN_TREN4_LSB 3
#define CS_TREN_TREN3_MSB 2
#define CS_TREN_TREN3_LSB 2
#define CS_TREN_TREN2_MSB 1
#define CS_TREN_TREN2_LSB 1
#define CS_TREN_TREN1_MSB 0
#define CS_TREN_TREN1_LSB 0
#define CS_THSSTO HW_REGISTER_RW( 0x7e802014 )
#define CS_THSSTO_MASK 0x0000ffff
#define CS_THSSTO_WIDTH 16
#define CS_THSSTO_RESET 0000000000
#define CS_THSSTO_THSSTO_MSB 15
#define CS_THSSTO_THSSTO_LSB 0
#define CS_THSSET HW_REGISTER_RW( 0x7e802018 )
#define CS_THSSET_MASK 0x00000fff
#define CS_THSSET_WIDTH 12
#define CS_THSSET_RESET 0000000000
#define CS_THSSET_TD_MSB 11
#define CS_THSSET_TD_LSB 8
#define CS_THSSET_HSMC_MSB 7
#define CS_THSSET_HSMC_LSB 0
#define CS_THSCKTO HW_REGISTER_RW( 0x7e80201c )
#define CS_THSCKTO_MASK 0x0000ffff
#define CS_THSCKTO_WIDTH 16
#define CS_THSCKTO_RESET 0000000000
#define CS_THSCKTO_THSCKTO_MSB 15
#define CS_THSCKTO_THSCKTO_LSB 0
#define CS_DBGDPHY HW_REGISTER_RO( 0x7e802080 )
#define CS_DBGDPHY_MASK 0x000fffff
#define CS_DBGDPHY_WIDTH 20
#define CS_DBGDPHY__MSB 19
#define CS_DBGDPHY__LSB 0
#define CS_DBGMISC HW_REGISTER_RO( 0x7e802084 )
#define CS_DBGMISC_MASK 0x000001ff
#define CS_DBGMISC_WIDTH 9
#define CS_DBGMISC__MSB 8
#define CS_DBGMISC__LSB 0
#define CS_TRIG HW_REGISTER_RO( 0x7e802088 )
#define CS_TRIG_MASK 0x000fffff
#define CS_TRIG_WIDTH 20
#define CS_TRIG__MSB 19
#define CS_TRIG__LSB 0
#define CS_SRST HW_REGISTER_RW( 0x7e802090 )
#define CS_SRST_MASK 0x00000001
#define CS_SRST_WIDTH 1
#define CS_SRST__MSB 0
#define CS_SRST__LSB 0
#define CS_RDR3 HW_REGISTER_RO( 0x7e802094 )
#define CS_RDR3_MASK 0x00001fff
#define CS_RDR3_WIDTH 13
#define CS_RDR3__MSB 12
#define CS_RDR3__LSB 0
#define CS_RC0 HW_REGISTER_RW( 0x7e802100 )
#define CS_RC0_MASK 0x1fff1f07
#define CS_RC0_WIDTH 29
#define CS_RC0_RESET 0000000000
#define CS_RC0_LCIE_MSB 28
#define CS_RC0_LCIE_LSB 16
#define CS_RC0_GSPIE_MSB 12
#define CS_RC0_GSPIE_LSB 12
#define CS_RC0_LEIE_MSB 11
#define CS_RC0_LEIE_LSB 11
#define CS_RC0_LSIE_MSB 10
#define CS_RC0_LSIE_LSB 10
#define CS_RC0_FEIE_MSB 9
#define CS_RC0_FEIE_LSB 9
#define CS_RC0_FSIE_MSB 8
#define CS_RC0_FSIE_LSB 8
#define CS_RC0_VC_MSB 2
#define CS_RC0_VC_LSB 1
#define CS_RC0_CHEN_MSB 0
#define CS_RC0_CHEN_LSB 0
#define CS_RPC0 HW_REGISTER_RW( 0x7e802104 )
#define CS_RPC0_MASK 0x01ff1f1f
#define CS_RPC0_WIDTH 25
#define CS_RPC0_RESET 0x00200000
#define CS_RPC0_EBL_MSB 24
#define CS_RPC0_EBL_LSB 16
#define CS_RPC0_EAP_MSB 12
#define CS_RPC0_EAP_LSB 12
#define CS_RPC0_EP_MSB 11
#define CS_RPC0_EP_LSB 8
#define CS_RPC0_DAP_MSB 4
#define CS_RPC0_DAP_LSB 4
#define CS_RPC0_DP_MSB 3
#define CS_RPC0_DP_LSB 0
#define CS_RS0 HW_REGISTER_RW( 0x7e802108 )
#define CS_RS0_MASK 0x01ffffff
#define CS_RS0_WIDTH 25
#define CS_RS0_RESET 0000000000
#define CS_RS0_DBO_MSB 24
#define CS_RS0_DBO_LSB 24
#define CS_RS0_IBO_MSB 23
#define CS_RS0_IBO_LSB 23
#define CS_RS0_CRCE_MSB 22
#define CS_RS0_CRCE_LSB 22
#define CS_RS0_LCI_MSB 21
#define CS_RS0_LCI_LSB 21
#define CS_RS0_GSPI_MSB 20
#define CS_RS0_GSPI_LSB 20
#define CS_RS0_LEI_MSB 19
#define CS_RS0_LEI_LSB 19
#define CS_RS0_LSI_MSB 18
#define CS_RS0_LSI_LSB 18
#define CS_RS0_FEI_MSB 17
#define CS_RS0_FEI_LSB 17
#define CS_RS0_FSI_MSB 16
#define CS_RS0_FSI_LSB 16
#define CS_RS0_FNUM_MSB 15
#define CS_RS0_FNUM_LSB 0
#define CS_RSA0 HW_REGISTER_RW( 0x7e80210c )
#define CS_RSA0_MASK 0x3fffffff
#define CS_RSA0_WIDTH 30
#define CS_RSA0_RESET 0000000000
#define CS_RSA0__MSB 29
#define CS_RSA0__LSB 0
#define CS_REA0 HW_REGISTER_RW( 0x7e802110 )
#define CS_REA0_MASK 0x3fffffff
#define CS_REA0_WIDTH 30
#define CS_REA0_RESET 0000000000
#define CS_REA0__MSB 29
#define CS_REA0__LSB 0
#define CS_RWP0 HW_REGISTER_RO( 0x7e802114 )
#define CS_RWP0_MASK 0x3fffffff
#define CS_RWP0_WIDTH 30
#define CS_RWP0__MSB 29
#define CS_RWP0__LSB 0
#define CS_RBC0 HW_REGISTER_RO( 0x7e802118 )
#define CS_RBC0_MASK 0xffffffff
#define CS_RBC0_WIDTH 32
#define CS_RBC0__MSB 31
#define CS_RBC0__LSB 0
#define CS_RLS0 HW_REGISTER_RW( 0x7e80211c )
#define CS_RLS0_MASK 0x0000ffff
#define CS_RLS0_WIDTH 16
#define CS_RLS0_RESET 0000000000
#define CS_RLS0__MSB 15
#define CS_RLS0__LSB 0
#define CS_RDSA0 HW_REGISTER_RW( 0x7e802120 )
#define CS_RDSA0_MASK 0x3fffffff
#define CS_RDSA0_WIDTH 30
#define CS_RDSA0_RESET 0000000000
#define CS_RDSA0__MSB 29
#define CS_RDSA0__LSB 0
#define CS_RDEA0 HW_REGISTER_RW( 0x7e802124 )
#define CS_RDEA0_MASK 0x3fffffff
#define CS_RDEA0_WIDTH 30
#define CS_RDEA0_RESET 0000000000
#define CS_RDEA0__MSB 29
#define CS_RDEA0__LSB 0
#define CS_RDS0 HW_REGISTER_RW( 0x7e802128 )
#define CS_RDS0_MASK 0x0000ffff
#define CS_RDS0_WIDTH 16
#define CS_RDS0_RESET 0000000000
#define CS_RDS0__MSB 15
#define CS_RDS0__LSB 0
#define CS_DTOV0 HW_REGISTER_RW( 0x7e80212c )
#define CS_DTOV0_MASK 0x00007f7f
#define CS_DTOV0_WIDTH 15
#define CS_DTOV0_RESET 0000000000
#define CS_DTOV0_IMEN_MSB 14
#define CS_DTOV0_IMEN_LSB 14
#define CS_DTOV0_IMDT_MSB 13
#define CS_DTOV0_IMDT_LSB 8
#define CS_DTOV0_EMEN_MSB 6
#define CS_DTOV0_EMEN_LSB 6
#define CS_DTOV0_EMDT_MSB 5
#define CS_DTOV0_EMDT_LSB 0
#define CS_RC1 HW_REGISTER_RW( 0x7e802200 )
#define CS_RC1_MASK 0x1fff1f07
#define CS_RC1_WIDTH 29
#define CS_RC1_RESET 0000000000
#define CS_RC1_LCIE_MSB 28
#define CS_RC1_LCIE_LSB 16
#define CS_RC1_GSPIE_MSB 12
#define CS_RC1_GSPIE_LSB 12
#define CS_RC1_LEIE_MSB 11
#define CS_RC1_LEIE_LSB 11
#define CS_RC1_LSIE_MSB 10
#define CS_RC1_LSIE_LSB 10
#define CS_RC1_FEIE_MSB 9
#define CS_RC1_FEIE_LSB 9
#define CS_RC1_FSIE_MSB 8
#define CS_RC1_FSIE_LSB 8
#define CS_RC1_VC_MSB 2
#define CS_RC1_VC_LSB 1
#define CS_RC1_CHEN_MSB 0
#define CS_RC1_CHEN_LSB 0
#define CS_RPC1 HW_REGISTER_RW( 0x7e802204 )
#define CS_RPC1_MASK 0x01ff1f1f
#define CS_RPC1_WIDTH 25
#define CS_RPC1_RESET 0x00200000
#define CS_RPC1_EBL_MSB 24
#define CS_RPC1_EBL_LSB 16
#define CS_RPC1_EAP_MSB 12
#define CS_RPC1_EAP_LSB 12
#define CS_RPC1_EP_MSB 11
#define CS_RPC1_EP_LSB 8
#define CS_RPC1_DAP_MSB 4
#define CS_RPC1_DAP_LSB 4
#define CS_RPC1_DP_MSB 3
#define CS_RPC1_DP_LSB 0
#define CS_RS1 HW_REGISTER_RW( 0x7e802208 )
#define CS_RS1_MASK 0x01ffffff
#define CS_RS1_WIDTH 25
#define CS_RS1_RESET 0000000000
#define CS_RS1_DBO_MSB 24
#define CS_RS1_DBO_LSB 24
#define CS_RS1_IBO_MSB 23
#define CS_RS1_IBO_LSB 23
#define CS_RS1_CRCE_MSB 22
#define CS_RS1_CRCE_LSB 22
#define CS_RS1_LCI_MSB 21
#define CS_RS1_LCI_LSB 21
#define CS_RS1_GSPI_MSB 20
#define CS_RS1_GSPI_LSB 20
#define CS_RS1_LEI_MSB 19
#define CS_RS1_LEI_LSB 19
#define CS_RS1_LSI_MSB 18
#define CS_RS1_LSI_LSB 18
#define CS_RS1_FEI_MSB 17
#define CS_RS1_FEI_LSB 17
#define CS_RS1_FSI_MSB 16
#define CS_RS1_FSI_LSB 16
#define CS_RS1_FNUM_MSB 15
#define CS_RS1_FNUM_LSB 0
#define CS_RSA1 HW_REGISTER_RW( 0x7e80220c )
#define CS_RSA1_MASK 0x3fffffff
#define CS_RSA1_WIDTH 30
#define CS_RSA1_RESET 0000000000
#define CS_RSA1__MSB 29
#define CS_RSA1__LSB 0
#define CS_REA1 HW_REGISTER_RW( 0x7e802210 )
#define CS_REA1_MASK 0x3fffffff
#define CS_REA1_WIDTH 30
#define CS_REA1_RESET 0000000000
#define CS_REA1__MSB 29
#define CS_REA1__LSB 0
#define CS_RWP1 HW_REGISTER_RO( 0x7e802214 )
#define CS_RWP1_MASK 0x3fffffff
#define CS_RWP1_WIDTH 30
#define CS_RWP1__MSB 29
#define CS_RWP1__LSB 0
#define CS_RBC1 HW_REGISTER_RO( 0x7e802218 )
#define CS_RBC1_MASK 0xffffffff
#define CS_RBC1_WIDTH 32
#define CS_RBC1__MSB 31
#define CS_RBC1__LSB 0
#define CS_RLS1 HW_REGISTER_RW( 0x7e80221c )
#define CS_RLS1_MASK 0x0000ffff
#define CS_RLS1_WIDTH 16
#define CS_RLS1_RESET 0000000000
#define CS_RLS1__MSB 15
#define CS_RLS1__LSB 0
#define CS_RDSA1 HW_REGISTER_RW( 0x7e802220 )
#define CS_RDSA1_MASK 0x3fffffff
#define CS_RDSA1_WIDTH 30
#define CS_RDSA1_RESET 0000000000
#define CS_RDSA1__MSB 29
#define CS_RDSA1__LSB 0
#define CS_RDEA1 HW_REGISTER_RW( 0x7e802224 )
#define CS_RDEA1_MASK 0x3fffffff
#define CS_RDEA1_WIDTH 30
#define CS_RDEA1_RESET 0000000000
#define CS_RDEA1__MSB 29
#define CS_RDEA1__LSB 0
#define CS_RDS1 HW_REGISTER_RW( 0x7e802228 )
#define CS_RDS1_MASK 0x0000ffff
#define CS_RDS1_WIDTH 16
#define CS_RDS1_RESET 0000000000
#define CS_RDS1__MSB 15
#define CS_RDS1__LSB 0
#define CS_DTOV1 HW_REGISTER_RW( 0x7e80222c )
#define CS_DTOV1_MASK 0x00007f7f
#define CS_DTOV1_WIDTH 15
#define CS_DTOV1_RESET 0000000000
#define CS_DTOV1_IMEN_MSB 14
#define CS_DTOV1_IMEN_LSB 14
#define CS_DTOV1_IMDT_MSB 13
#define CS_DTOV1_IMDT_LSB 8
#define CS_DTOV1_EMEN_MSB 6
#define CS_DTOV1_EMEN_LSB 6
#define CS_DTOV1_EMDT_MSB 5
#define CS_DTOV1_EMDT_LSB 0

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bcm2708_chip/dpi.h Executable file
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// This file was generated by the create_regs script
#define DPI_BASE 0x7e208000
#define DPI_APB_ID 0x44504920
#define DPI_C HW_REGISTER_RW( 0x7e208000 )
#define DPI_C_MASK 0x0000ffff
#define DPI_C_WIDTH 16
#define DPI_C_RESET 0x00003000

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bcm2708_chip/dsi.h Executable file
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// This file was generated by the create_regs script
#define DSI0_BASE 0x7e209000
#define DSI0_APB_ID 0x00647369
#define DSI0_CTRL HW_REGISTER_RW( 0x7e209000 )
#define DSI0_CTRL_MASK 0x00000007
#define DSI0_CTRL_WIDTH 3
#define DSI0_CTRL_RESET 0000000000
#define DSI0_CTRL_CTRL2_BITS 2:2
#define DSI0_CTRL_CTRL2_SET 0x00000004
#define DSI0_CTRL_CTRL2_CLR 0xfffffffb
#define DSI0_CTRL_CTRL2_MSB 2
#define DSI0_CTRL_CTRL2_LSB 2
#define DSI0_CTRL_CTRL1_BITS 1:1
#define DSI0_CTRL_CTRL1_SET 0x00000002
#define DSI0_CTRL_CTRL1_CLR 0xfffffffd
#define DSI0_CTRL_CTRL1_MSB 1
#define DSI0_CTRL_CTRL1_LSB 1
#define DSI0_CTRL_CTRL0_BITS 0:0
#define DSI0_CTRL_CTRL0_SET 0x00000001
#define DSI0_CTRL_CTRL0_CLR 0xfffffffe
#define DSI0_CTRL_CTRL0_MSB 0
#define DSI0_CTRL_CTRL0_LSB 0
#define DSI0_CMD_PKTC HW_REGISTER_RW( 0x7e209004 )
#define DSI0_CMD_PKTC_MASK 0xffffffff
#define DSI0_CMD_PKTC_WIDTH 32
#define DSI0_CMD_PKTC_RESET 0000000000
#define DSI0_CMD_PKTH HW_REGISTER_RW( 0x7e209008 )
#define DSI0_CMD_PKTH_MASK 0xffffffff
#define DSI0_CMD_PKTH_WIDTH 32
#define DSI0_CMD_PKTH_RESET 0000000000
#define DSI0_RX1_PKTH HW_REGISTER_RO( 0x7e20900c )
#define DSI0_RX1_PKTH_MASK 0xffffffff
#define DSI0_RX1_PKTH_WIDTH 32
#define DSI0_RX2_PKTH HW_REGISTER_RO( 0x7e209010 )
#define DSI0_RX2_PKTH_MASK 0xffffffff
#define DSI0_RX2_PKTH_WIDTH 32
#define DSI0_CMD_DATAF HW_REGISTER_RW( 0x7e209014 )
#define DSI0_CMD_DATAF_MASK 0x000000ff
#define DSI0_CMD_DATAF_WIDTH 8
#define DSI0_DISP0_CTR HW_REGISTER_RW( 0x7e209018 )
#define DSI0_DISP0_CTR_MASK 0xffffffff
#define DSI0_DISP0_CTR_WIDTH 32
#define DSI0_DISP0_CTR_RESET 0000000000
#define DSI0_DISP1_CTR HW_REGISTER_RW( 0x7e20901c )
#define DSI0_DISP1_CTR_MASK 0xffffffff
#define DSI0_DISP1_CTR_WIDTH 32
#define DSI0_DISP1_CTR_RESET 0000000000
#define DSI0_PIX_FIFO HW_REGISTER_RW( 0x7e209020 )
#define DSI0_PIX_FIFO_MASK 0xffffffff
#define DSI0_PIX_FIFO_WIDTH 32
#define DSI0_INT_STAT HW_REGISTER_RW( 0x7e209024 )
#define DSI0_INT_STAT_MASK 0xffffffff
#define DSI0_INT_STAT_WIDTH 32
#define DSI0_INT_EN HW_REGISTER_RW( 0x7e209028 )
#define DSI0_INT_EN_MASK 0x0fffffff
#define DSI0_INT_EN_WIDTH 28
#define DSI0_INT_EN_RESET 0000000000
#define DSI0_STAT HW_REGISTER_RW( 0x7e20902c )
#define DSI0_STAT_MASK 0xffffffff
#define DSI0_STAT_WIDTH 32
#define DSI0_HSTX_TO_C HW_REGISTER_RW( 0x7e209030 )
#define DSI0_HSTX_TO_C_MASK 0x00ffffff
#define DSI0_HSTX_TO_C_WIDTH 24
#define DSI0_HSTX_TO_C_RESET 0000000000
#define DSI0_LPRX_TO_C HW_REGISTER_RW( 0x7e209034 )
#define DSI0_LPRX_TO_C_MASK 0xffffffff
#define DSI0_LPRX_TO_C_WIDTH 32
#define DSI0_LPRX_TO_C_RESET 0000000000
#define DSI0_TA_TO_CNT HW_REGISTER_RW( 0x7e209038 )
#define DSI0_TA_TO_CNT_MASK 0xffffffff
#define DSI0_TA_TO_CNT_WIDTH 32
#define DSI0_TA_TO_CNT_RESET 0000000000
#define DSI0_PR_TO_CNT HW_REGISTER_RW( 0x7e20903c )
#define DSI0_PR_TO_CNT_MASK 0xffffffff
#define DSI0_PR_TO_CNT_WIDTH 32
#define DSI0_PR_TO_CNT_RESET 0000000000
#define DSI0_PHYC HW_REGISTER_RW( 0x7e209040 )
#define DSI0_PHYC_MASK 0x0003f777
#define DSI0_PHYC_WIDTH 18
#define DSI0_PHYC_RESET 0000000000
#define DSI0_PHYC_dsi_esc_lpdt_BITS 17:12
#define DSI0_PHYC_dsi_esc_lpdt_SET 0x0003f000
#define DSI0_PHYC_dsi_esc_lpdt_CLR 0xfffc0fff
#define DSI0_PHYC_dsi_esc_lpdt_MSB 17
#define DSI0_PHYC_dsi_esc_lpdt_LSB 12
#define DSI0_PHYC_txhsclk_cont_sync_BITS 10:10
#define DSI0_PHYC_txhsclk_cont_sync_SET 0x00000400
#define DSI0_PHYC_txhsclk_cont_sync_CLR 0xfffffbff
#define DSI0_PHYC_txhsclk_cont_sync_MSB 10
#define DSI0_PHYC_txhsclk_cont_sync_LSB 10
#define DSI0_PHYC_txulps_clk_sync_BITS 9:9
#define DSI0_PHYC_txulps_clk_sync_SET 0x00000200
#define DSI0_PHYC_txulps_clk_sync_CLR 0xfffffdff
#define DSI0_PHYC_txulps_clk_sync_MSB 9
#define DSI0_PHYC_txulps_clk_sync_LSB 9
#define DSI0_PHYC_clane_hsen_sync_BITS 8:8
#define DSI0_PHYC_clane_hsen_sync_SET 0x00000100
#define DSI0_PHYC_clane_hsen_sync_CLR 0xfffffeff
#define DSI0_PHYC_clane_hsen_sync_MSB 8
#define DSI0_PHYC_clane_hsen_sync_LSB 8
#define DSI0_PHYC_txulpshs_1_sync_BITS 6:6
#define DSI0_PHYC_txulpshs_1_sync_SET 0x00000040
#define DSI0_PHYC_txulpshs_1_sync_CLR 0xffffffbf
#define DSI0_PHYC_txulpshs_1_sync_MSB 6
#define DSI0_PHYC_txulpshs_1_sync_LSB 6
#define DSI0_PHYC_dlane_hsen_1_sync_BITS 5:5
#define DSI0_PHYC_dlane_hsen_1_sync_SET 0x00000020
#define DSI0_PHYC_dlane_hsen_1_sync_CLR 0xffffffdf
#define DSI0_PHYC_dlane_hsen_1_sync_MSB 5
#define DSI0_PHYC_dlane_hsen_1_sync_LSB 5
#define DSI0_PHYC_unused_BITS 4:4
#define DSI0_PHYC_unused_SET 0x00000010
#define DSI0_PHYC_unused_CLR 0xffffffef
#define DSI0_PHYC_unused_MSB 4
#define DSI0_PHYC_unused_LSB 4
#define DSI0_PHYC_forcehsstop_sync_BITS 2:2
#define DSI0_PHYC_forcehsstop_sync_SET 0x00000004
#define DSI0_PHYC_forcehsstop_sync_CLR 0xfffffffb
#define DSI0_PHYC_forcehsstop_sync_MSB 2
#define DSI0_PHYC_forcehsstop_sync_LSB 2
#define DSI0_PHYC_txulpshs_0_sync_BITS 1:1
#define DSI0_PHYC_txulpshs_0_sync_SET 0x00000002
#define DSI0_PHYC_txulpshs_0_sync_CLR 0xfffffffd
#define DSI0_PHYC_txulpshs_0_sync_MSB 1
#define DSI0_PHYC_txulpshs_0_sync_LSB 1
#define DSI0_PHYC_dlane_hsen_0_sync_BITS 0:0
#define DSI0_PHYC_dlane_hsen_0_sync_SET 0x00000001
#define DSI0_PHYC_dlane_hsen_0_sync_CLR 0xfffffffe
#define DSI0_PHYC_dlane_hsen_0_sync_MSB 0
#define DSI0_PHYC_dlane_hsen_0_sync_LSB 0
#define DSI0_HS_CLT0 HW_REGISTER_RW( 0x7e209044 )
#define DSI0_HS_CLT0_MASK 0xfffffffc
#define DSI0_HS_CLT0_WIDTH 32
#define DSI0_HS_CLT0_RESET 0000000000
#define DSI0_HS_CLT1 HW_REGISTER_RW( 0x7e209048 )
#define DSI0_HS_CLT1_MASK 0x000003fc
#define DSI0_HS_CLT1_WIDTH 10
#define DSI0_HS_CLT1_RESET 0000000000
#define DSI0_HS_CLT2 HW_REGISTER_RW( 0x7e20904c )
#define DSI0_HS_CLT2_MASK 0x000003fc
#define DSI0_HS_CLT2_WIDTH 10
#define DSI0_HS_CLT2_RESET 0000000000
#define DSI0_HS_DLT3 HW_REGISTER_RW( 0x7e209050 )
#define DSI0_HS_DLT3_MASK 0x000003fc
#define DSI0_HS_DLT3_WIDTH 10
#define DSI0_HS_DLT3_RESET 0000000000
#define DSI0_HS_DLT4 HW_REGISTER_RW( 0x7e209054 )
#define DSI0_HS_DLT4_MASK 0x000003fc
#define DSI0_HS_DLT4_WIDTH 10
#define DSI0_HS_DLT4_RESET 0000000000
#define DSI0_HS_DLT5 HW_REGISTER_RW( 0x7e209058 )
#define DSI0_HS_DLT5_MASK 0x000003fc
#define DSI0_HS_DLT5_WIDTH 10
#define DSI0_HS_DLT5_RESET 0000000000
#define DSI0_LP_DLT6 HW_REGISTER_RW( 0x7e20905c )
#define DSI0_LP_DLT6_MASK 0x000003fc
#define DSI0_LP_DLT6_WIDTH 10
#define DSI0_LP_DLT6_RESET 0000000000
#define DSI0_LP_DLT7 HW_REGISTER_RW( 0x7e209060 )
#define DSI0_LP_DLT7_MASK 0x000003fc
#define DSI0_LP_DLT7_WIDTH 10
#define DSI0_LP_DLT7_RESET 0000000000
#define DSI0_PHY_AFEC0 HW_REGISTER_RW( 0x7e209064 )
#define DSI0_PHY_AFEC0_MASK 0x000000ff
#define DSI0_PHY_AFEC0_WIDTH 8
#define DSI0_PHY_AFEC0_RESET 0000000000
#define DSI0_PHY_AFEC1 HW_REGISTER_RW( 0x7e209068 )
#define DSI0_PHY_AFEC1_MASK 0xffffffff
#define DSI0_PHY_AFEC1_WIDTH 32
#define DSI0_PHY_AFEC1_RESET 0000000000
#define DSI0_TST_SEL HW_REGISTER_RW( 0x7e20906c )
#define DSI0_TST_SEL_MASK 0x000000ff
#define DSI0_TST_SEL_WIDTH 8
#define DSI0_TST_SEL_RESET 0000000000
#define DSI0_TST_MON HW_REGISTER_RW( 0x7e209070 )
#define DSI0_TST_MON_MASK 0x000000ff
#define DSI0_TST_MON_WIDTH 8
#define DSI0_TST_MON_RESET 0000000000

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bcm2708_chip/dsi4.h Executable file
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// This file was generated by the create_regs script
#define DSI1_BASE 0x7e700000
#define DSI1_APB_ID 0x64736934
#define DSI1_CTRL HW_REGISTER_RW( 0x7e700000 )
#define DSI1_CTRL_MASK 0xffffffff
#define DSI1_CTRL_WIDTH 32
#define DSI1_CTRL_RESET 0000000000
#define DSI1_TXPKT1_C HW_REGISTER_RW( 0x7e700004 )
#define DSI1_TXPKT1_C_MASK 0xffffffff
#define DSI1_TXPKT1_C_WIDTH 32
#define DSI1_TXPKT1_C_RESET 0000000000
#define DSI1_TXPKT1_H HW_REGISTER_RW( 0x7e700008 )
#define DSI1_TXPKT1_H_MASK 0xffffffff
#define DSI1_TXPKT1_H_WIDTH 32
#define DSI1_TXPKT1_H_RESET 0000000000
#define DSI1_TXPKT2_C HW_REGISTER_RW( 0x7e70000c )
#define DSI1_TXPKT2_C_MASK 0xffffffff
#define DSI1_TXPKT2_C_WIDTH 32
#define DSI1_TXPKT2_C_RESET 0000000000
#define DSI1_TXPKT2_H HW_REGISTER_RW( 0x7e700010 )
#define DSI1_TXPKT2_H_MASK 0xffffffff
#define DSI1_TXPKT2_H_WIDTH 32
#define DSI1_TXPKT2_H_RESET 0000000000
#define DSI1_RXPKT1_H HW_REGISTER_RO( 0x7e700014 )
#define DSI1_RXPKT1_H_MASK 0xffffffff
#define DSI1_RXPKT1_H_WIDTH 32
#define DSI1_RXPKT2_H HW_REGISTER_RO( 0x7e700018 )
#define DSI1_RXPKT2_H_MASK 0xffffffff
#define DSI1_RXPKT2_H_WIDTH 32
#define DSI1_TXPKT_CMD_FIFO HW_REGISTER_RW( 0x7e70001c )
#define DSI1_TXPKT_CMD_FIFO_MASK 0x000000ff
#define DSI1_TXPKT_CMD_FIFO_WIDTH 8
#define DSI1_TXPKT_PIXD_FIFO HW_REGISTER_RW( 0x7e700020 )
#define DSI1_TXPKT_PIXD_FIFO_MASK 0xffffffff
#define DSI1_TXPKT_PIXD_FIFO_WIDTH 32
#define DSI1_TXPKT_PIXD_FIFO_RESET 0000000000
#define DSI1_RXPKT_FIFO HW_REGISTER_RW( 0x7e700024 )
#define DSI1_RXPKT_FIFO_MASK 0xffffffff
#define DSI1_RXPKT_FIFO_WIDTH 32
#define DSI1_RXPKT_FIFO_RESET 0000000000
#define DSI1_DISP0_CTRL HW_REGISTER_RW( 0x7e700028 )
#define DSI1_DISP0_CTRL_MASK 0xffffffff
#define DSI1_DISP0_CTRL_WIDTH 32
#define DSI1_DISP1_CTRL HW_REGISTER_RW( 0x7e70002c )
#define DSI1_DISP1_CTRL_MASK 0xffffffff
#define DSI1_DISP1_CTRL_WIDTH 32
#define DSI1_INT_STAT HW_REGISTER_RW( 0x7e700030 )
#define DSI1_INT_STAT_MASK 0xffffffff
#define DSI1_INT_STAT_WIDTH 32
#define DSI1_INT_EN HW_REGISTER_RW( 0x7e700034 )
#define DSI1_INT_EN_MASK 0x0fffffff
#define DSI1_INT_EN_WIDTH 28
#define DSI1_INT_EN_RESET 0000000000
#define DSI1_STAT HW_REGISTER_RW( 0x7e700038 )
#define DSI1_STAT_MASK 0xffffffff
#define DSI1_STAT_WIDTH 32
#define DSI1_HSTX_TO_CNT HW_REGISTER_RW( 0x7e70003c )
#define DSI1_HSTX_TO_CNT_MASK 0x00ffffff
#define DSI1_HSTX_TO_CNT_WIDTH 24
#define DSI1_HSTX_TO_CNT_RESET 0000000000
#define DSI1_LPRX_TO_CNT HW_REGISTER_RW( 0x7e700040 )
#define DSI1_LPRX_TO_CNT_MASK 0xffffffff
#define DSI1_LPRX_TO_CNT_WIDTH 32
#define DSI1_LPRX_TO_CNT_RESET 0000000000
#define DSI1_TA_TO_CNT HW_REGISTER_RW( 0x7e700044 )
#define DSI1_TA_TO_CNT_MASK 0xffffffff
#define DSI1_TA_TO_CNT_WIDTH 32
#define DSI1_TA_TO_CNT_RESET 0000000000
#define DSI1_PR_TO_CNT HW_REGISTER_RW( 0x7e700048 )
#define DSI1_PR_TO_CNT_MASK 0xffffffff
#define DSI1_PR_TO_CNT_WIDTH 32
#define DSI1_PR_TO_CNT_RESET 0000000000
#define DSI1_PHYC HW_REGISTER_RW( 0x7e70004c )
#define DSI1_PHYC_MASK 0xffffffff
#define DSI1_PHYC_WIDTH 32
#define DSI1_PHYC_RESET 0000000000
#define DSI1_HS_CLT0 HW_REGISTER_RW( 0x7e700050 )
#define DSI1_HS_CLT0_MASK 0xffffffff
#define DSI1_HS_CLT0_WIDTH 32
#define DSI1_HS_CLT0_RESET 0000000000
#define DSI1_HS_CLT1 HW_REGISTER_RW( 0x7e700054 )
#define DSI1_HS_CLT1_MASK 0xffffffff
#define DSI1_HS_CLT1_WIDTH 32
#define DSI1_HS_CLT1_RESET 0000000000
#define DSI1_HS_CLT2 HW_REGISTER_RW( 0x7e700058 )
#define DSI1_HS_CLT2_MASK 0xffffffff
#define DSI1_HS_CLT2_WIDTH 32
#define DSI1_HS_CLT2_RESET 0000000000
#define DSI1_HS_DLT3 HW_REGISTER_RW( 0x7e70005c )
#define DSI1_HS_DLT3_MASK 0xffffffff
#define DSI1_HS_DLT3_WIDTH 32
#define DSI1_HS_DLT3_RESET 0000000000
#define DSI1_HS_DLT4 HW_REGISTER_RW( 0x7e700060 )
#define DSI1_HS_DLT4_MASK 0xffffffff
#define DSI1_HS_DLT4_WIDTH 32
#define DSI1_HS_DLT4_RESET 0000000000
#define DSI1_HS_DLT5 HW_REGISTER_RW( 0x7e700064 )
#define DSI1_HS_DLT5_MASK 0xffffffff
#define DSI1_HS_DLT5_WIDTH 32
#define DSI1_HS_DLT5_RESET 0000000000
#define DSI1_LP_DLT6 HW_REGISTER_RW( 0x7e700068 )
#define DSI1_LP_DLT6_MASK 0xffffffff
#define DSI1_LP_DLT6_WIDTH 32
#define DSI1_LP_DLT6_RESET 0000000000
#define DSI1_LP_DLT7 HW_REGISTER_RW( 0x7e70006c )
#define DSI1_LP_DLT7_MASK 0xffffffff
#define DSI1_LP_DLT7_WIDTH 32
#define DSI1_LP_DLT7_RESET 0000000000
#define DSI1_PHY_AFEC0 HW_REGISTER_RW( 0x7e700070 )
#define DSI1_PHY_AFEC0_MASK 0xffffffff
#define DSI1_PHY_AFEC0_WIDTH 32
#define DSI1_PHY_AFEC0_RESET 0000000000
#define DSI1_PHY_AFEC1 HW_REGISTER_RW( 0x7e700074 )
#define DSI1_PHY_AFEC1_MASK 0xffffffff
#define DSI1_PHY_AFEC1_WIDTH 32
#define DSI1_PHY_AFEC1_RESET 0000000000
#define DSI1_TST_SEL HW_REGISTER_RW( 0x7e700078 )
#define DSI1_TST_SEL_MASK 0xffffffff
#define DSI1_TST_SEL_WIDTH 32
#define DSI1_TST_SEL_RESET 0000000000
#define DSI1_TST_MON HW_REGISTER_RW( 0x7e70007c )
#define DSI1_TST_MON_MASK 0xffffffff
#define DSI1_TST_MON_WIDTH 32
#define DSI1_TST_MON_RESET 0000000000

1276
bcm2708_chip/emmc.h Executable file
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2
bcm2708_chip/flow_config.tcl Executable file
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enable_flow create_regs

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bcm2708_chip/fpga_microblaze.h Executable file
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// This file was generated by the create_regs script
#define FPGA_MB_BASE 0x7e20b700
#define FPGA_MB_XSYS_BUILD_NUM HW_REGISTER_RO( 0x7e20b700 )
#define FPGA_MB_XSYS_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XSYS_BUILD_NUM_WIDTH 32
#define FPGA_MB_XC0_BUILD_NUM HW_REGISTER_RO( 0x7e20b704 )
#define FPGA_MB_XC0_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XC0_BUILD_NUM_WIDTH 32
#define FPGA_MB_XC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b708 )
#define FPGA_MB_XC1_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XC1_BUILD_NUM_WIDTH 32
#define FPGA_MB_XPERI_BUILD_NUM HW_REGISTER_RO( 0x7e20b70c )
#define FPGA_MB_XPERI_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XPERI_BUILD_NUM_WIDTH 32
#define FPGA_MB_XH264_BUILD_NUM HW_REGISTER_RO( 0x7e20b710 )
#define FPGA_MB_XH264_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XH264_BUILD_NUM_WIDTH 32
#define FPGA_MB_XV3D_BUILD_NUM HW_REGISTER_RO( 0x7e20b714 )
#define FPGA_MB_XV3D_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XV3D_BUILD_NUM_WIDTH 32
#define FPGA_MB_XSLC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b718 )
#define FPGA_MB_XSLC1_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XSLC1_BUILD_NUM_WIDTH 32
#define FPGA_MB_XSLC2_BUILD_NUM HW_REGISTER_RO( 0x7e20b71c )
#define FPGA_MB_XSLC2_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XSLC2_BUILD_NUM_WIDTH 32
#define FPGA_MB_XSLC3_BUILD_NUM HW_REGISTER_RO( 0x7e20b720 )
#define FPGA_MB_XSLC3_BUILD_NUM_MASK 0xffffffff
#define FPGA_MB_XSLC3_BUILD_NUM_WIDTH 32
#define FPGA_MB_CORE_CLK_FREQ HW_REGISTER_RO( 0x7e20b724 )
#define FPGA_MB_CORE_CLK_FREQ_MASK 0xffffffff
#define FPGA_MB_CORE_CLK_FREQ_WIDTH 32
#define FPGA_MB_SDC_CLK_FREQ HW_REGISTER_RO( 0x7e20b728 )
#define FPGA_MB_SDC_CLK_FREQ_MASK 0xffffffff
#define FPGA_MB_SDC_CLK_FREQ_WIDTH 32
#define FPGA_MB_SDC_H264_FREQ HW_REGISTER_RO( 0x7e20b72c )
#define FPGA_MB_SDC_H264_FREQ_MASK 0xffffffff
#define FPGA_MB_SDC_H264_FREQ_WIDTH 32
#define FPGA_MB_SDC_V3D_FREQ HW_REGISTER_RO( 0x7e20b730 )
#define FPGA_MB_SDC_V3D_FREQ_MASK 0xffffffff
#define FPGA_MB_SDC_V3D_FREQ_WIDTH 32
#define FPGA_MB_SDC_ISP_FREQ HW_REGISTER_RO( 0x7e20b734 )
#define FPGA_MB_SDC_ISP_FREQ_MASK 0xffffffff
#define FPGA_MB_SDC_ISP_FREQ_WIDTH 32

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bcm2708_chip/fpga_peripheral.h Executable file
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#define FPGA_A0_BASE 0x7e213000
#define FPGA_B0_BASE 0x7e214000
#define FPGA_CTRL0_OFFSET 0x08
#define FPGA_STATUS0_OFFSET 0x0C
// This file was generated by the create_regs script
#define FPGA_BASE 0x7e20b600
#define FPGA_APB_ID 0x66706761
#define FPGA_VERSION HW_REGISTER_RO( 0x7e20b600 )
#define FPGA_VERSION_MASK 0xffffffff
#define FPGA_VERSION_WIDTH 32
#define FPGA_SCRATCH HW_REGISTER_RW( 0x7e20b604 )
#define FPGA_SCRATCH_MASK 0xffffffff
#define FPGA_SCRATCH_WIDTH 32
#define FPGA_CTRL0 HW_REGISTER_RW( 0x7e20b608 )
#define FPGA_CTRL0_MASK 0xfffff3fff
#define FPGA_CTRL0_WIDTH 36
#define FPGA_CTRL0_SPARE_OUT_BITS 31:20
#define FPGA_CTRL0_SPARE_OUT_SET 0xfff00000
#define FPGA_CTRL0_SPARE_OUT_CLR 0x000fffff
#define FPGA_CTRL0_SPARE_OUT_MSB 31
#define FPGA_CTRL0_SPARE_OUT_LSB 20
#define FPGA_CTRL0_LV_SPARE_OUT_BITS 19:18
#define FPGA_CTRL0_LV_SPARE_OUT_SET 0x000c0000
#define FPGA_CTRL0_LV_SPARE_OUT_CLR 0xfff3ffff
#define FPGA_CTRL0_LV_SPARE_OUT_MSB 19
#define FPGA_CTRL0_LV_SPARE_OUT_LSB 18
#define FPGA_CTRL0_TERMEN_CLK_BITS 17:17
#define FPGA_CTRL0_TERMEN_CLK_SET 0x00020000
#define FPGA_CTRL0_TERMEN_CLK_CLR 0xfffdffff
#define FPGA_CTRL0_TERMEN_CLK_MSB 17
#define FPGA_CTRL0_TERMEN_CLK_LSB 17
#define FPGA_CTRL0_TERMEN_DO_BITS 16:16
#define FPGA_CTRL0_TERMEN_DO_SET 0x00010000
#define FPGA_CTRL0_TERMEN_DO_CLR 0xfffeffff
#define FPGA_CTRL0_TERMEN_DO_MSB 16
#define FPGA_CTRL0_TERMEN_DO_LSB 16
#define FPGA_CTRL0_TV_ACTIVITY_BITS 13:13
#define FPGA_CTRL0_TV_ACTIVITY_SET 0x00002000
#define FPGA_CTRL0_TV_ACTIVITY_CLR 0xffffdfff
#define FPGA_CTRL0_TV_ACTIVITY_MSB 13
#define FPGA_CTRL0_TV_ACTIVITY_LSB 13
#define FPGA_CTRL0_SPI0_SEL_B_BITS 12:12
#define FPGA_CTRL0_SPI0_SEL_B_SET 0x00001000
#define FPGA_CTRL0_SPI0_SEL_B_CLR 0xffffefff
#define FPGA_CTRL0_SPI0_SEL_B_MSB 12
#define FPGA_CTRL0_SPI0_SEL_B_LSB 12
#define FPGA_CTRL0_DISP_BUFFER_BITS 11:11
#define FPGA_CTRL0_DISP_BUFFER_SET 0x00000800
#define FPGA_CTRL0_DISP_BUFFER_CLR 0xfffff7ff
#define FPGA_CTRL0_DISP_BUFFER_MSB 11
#define FPGA_CTRL0_DISP_BUFFER_LSB 11
#define FPGA_CTRL0_SPI1_SEL_BITS 10:10
#define FPGA_CTRL0_SPI1_SEL_SET 0x00000400
#define FPGA_CTRL0_SPI1_SEL_CLR 0xfffffbff
#define FPGA_CTRL0_SPI1_SEL_MSB 10
#define FPGA_CTRL0_SPI1_SEL_LSB 10
#define FPGA_CTRL0_SPI0_SEL_A_BITS 9:9
#define FPGA_CTRL0_SPI0_SEL_A_SET 0x00000200
#define FPGA_CTRL0_SPI0_SEL_A_CLR 0xfffffdff
#define FPGA_CTRL0_SPI0_SEL_A_MSB 9
#define FPGA_CTRL0_SPI0_SEL_A_LSB 9
#define FPGA_CTRL0_SW_SPI_CS_BITS 8:8
#define FPGA_CTRL0_SW_SPI_CS_SET 0x00000100
#define FPGA_CTRL0_SW_SPI_CS_CLR 0xfffffeff
#define FPGA_CTRL0_SW_SPI_CS_MSB 8
#define FPGA_CTRL0_SW_SPI_CS_LSB 8
#define FPGA_CTRL0_SW_SPI_SDA_O_BITS 7:7
#define FPGA_CTRL0_SW_SPI_SDA_O_SET 0x00000080
#define FPGA_CTRL0_SW_SPI_SDA_O_CLR 0xffffff7f
#define FPGA_CTRL0_SW_SPI_SDA_O_MSB 7
#define FPGA_CTRL0_SW_SPI_SDA_O_LSB 7
#define FPGA_CTRL0_SW_SPI_SCL_BITS 6:6
#define FPGA_CTRL0_SW_SPI_SCL_SET 0x00000040
#define FPGA_CTRL0_SW_SPI_SCL_CLR 0xffffffbf
#define FPGA_CTRL0_SW_SPI_SCL_MSB 6
#define FPGA_CTRL0_SW_SPI_SCL_LSB 6
#define FPGA_CTRL0_DIS_SW_SPI_BITS 5:5
#define FPGA_CTRL0_DIS_SW_SPI_SET 0x00000020
#define FPGA_CTRL0_DIS_SW_SPI_CLR 0xffffffdf
#define FPGA_CTRL0_DIS_SW_SPI_MSB 5
#define FPGA_CTRL0_DIS_SW_SPI_LSB 5
#define FPGA_CTRL0_SD_PSU_EN_BITS 4:4
#define FPGA_CTRL0_SD_PSU_EN_SET 0x00000010
#define FPGA_CTRL0_SD_PSU_EN_CLR 0xffffffef
#define FPGA_CTRL0_SD_PSU_EN_MSB 4
#define FPGA_CTRL0_SD_PSU_EN_LSB 4
#define FPGA_CTRL0_DIS_RST_BITS 3:3
#define FPGA_CTRL0_DIS_RST_SET 0x00000008
#define FPGA_CTRL0_DIS_RST_CLR 0xfffffff7
#define FPGA_CTRL0_DIS_RST_MSB 3
#define FPGA_CTRL0_DIS_RST_LSB 3
#define FPGA_CTRL0_DIS_CTL2_BITS 2:2
#define FPGA_CTRL0_DIS_CTL2_SET 0x00000004
#define FPGA_CTRL0_DIS_CTL2_CLR 0xfffffffb
#define FPGA_CTRL0_DIS_CTL2_MSB 2
#define FPGA_CTRL0_DIS_CTL2_LSB 2
#define FPGA_CTRL0_DIS_BL_BITS 1:1
#define FPGA_CTRL0_DIS_BL_SET 0x00000002
#define FPGA_CTRL0_DIS_BL_CLR 0xfffffffd
#define FPGA_CTRL0_DIS_BL_MSB 1
#define FPGA_CTRL0_DIS_BL_LSB 1
#define FPGA_CTRL0_DIS_CTL0_BITS 0:0
#define FPGA_CTRL0_DIS_CTL0_SET 0x00000001
#define FPGA_CTRL0_DIS_CTL0_CLR 0xfffffffe
#define FPGA_CTRL0_DIS_CTL0_MSB 0
#define FPGA_CTRL0_DIS_CTL0_LSB 0
#define FPGA_CTRL0_CAM_CTL2_BITS 2:2
#define FPGA_CTRL0_CAM_CTL2_SET 0x00000004
#define FPGA_CTRL0_CAM_CTL2_CLR 0xfffffffb
#define FPGA_CTRL0_CAM_CTL2_MSB 2
#define FPGA_CTRL0_CAM_CTL2_LSB 2
#define FPGA_CTRL0_CAM_CTL1_BITS 1:1
#define FPGA_CTRL0_CAM_CTL1_SET 0x00000002
#define FPGA_CTRL0_CAM_CTL1_CLR 0xfffffffd
#define FPGA_CTRL0_CAM_CTL1_MSB 1
#define FPGA_CTRL0_CAM_CTL1_LSB 1
#define FPGA_CTRL0_CAM_CTL0_BITS 0:0
#define FPGA_CTRL0_CAM_CTL0_SET 0x00000001
#define FPGA_CTRL0_CAM_CTL0_CLR 0xfffffffe
#define FPGA_CTRL0_CAM_CTL0_MSB 0
#define FPGA_CTRL0_CAM_CTL0_LSB 0
#define FPGA_STATUS0 HW_REGISTER_RO( 0x7e20b60c )
#define FPGA_STATUS0_MASK 0xfff800ff
#define FPGA_STATUS0_WIDTH 32
#define FPGA_STATUS0_SPARE_IN_BITS 31:19
#define FPGA_STATUS0_SPARE_IN_SET 0xfff80000
#define FPGA_STATUS0_SPARE_IN_CLR 0x0007ffff
#define FPGA_STATUS0_SPARE_IN_MSB 31
#define FPGA_STATUS0_SPARE_IN_LSB 19
#define FPGA_STATUS0_SW_SPI_SPI_IN_BITS 7:7
#define FPGA_STATUS0_SW_SPI_SPI_IN_SET 0x00000080
#define FPGA_STATUS0_SW_SPI_SPI_IN_CLR 0xffffff7f
#define FPGA_STATUS0_SW_SPI_SPI_IN_MSB 7
#define FPGA_STATUS0_SW_SPI_SPI_IN_LSB 7
#define FPGA_STATUS0_NAND_RNB_BITS 6:6
#define FPGA_STATUS0_NAND_RNB_SET 0x00000040
#define FPGA_STATUS0_NAND_RNB_CLR 0xffffffbf
#define FPGA_STATUS0_NAND_RNB_MSB 6
#define FPGA_STATUS0_NAND_RNB_LSB 6
#define FPGA_STATUS0_SD_CD_BITS 5:5
#define FPGA_STATUS0_SD_CD_SET 0x00000020
#define FPGA_STATUS0_SD_CD_CLR 0xffffffdf
#define FPGA_STATUS0_SD_CD_MSB 5
#define FPGA_STATUS0_SD_CD_LSB 5
#define FPGA_STATUS0_SD_WP_BITS 4:4
#define FPGA_STATUS0_SD_WP_SET 0x00000010
#define FPGA_STATUS0_SD_WP_CLR 0xffffffef
#define FPGA_STATUS0_SD_WP_MSB 4
#define FPGA_STATUS0_SD_WP_LSB 4
#define FPGA_STATUS0_HW_ID_BITS 3:0
#define FPGA_STATUS0_HW_ID_SET 0x0000000f
#define FPGA_STATUS0_HW_ID_CLR 0xfffffff0
#define FPGA_STATUS0_HW_ID_MSB 3
#define FPGA_STATUS0_HW_ID_LSB 0
#define FPGA_DCM_WR_DATA HW_REGISTER_RW( 0x7e20b610 )
#define FPGA_DCM_WR_DATA_MASK 0x00ffffff
#define FPGA_DCM_WR_DATA_WIDTH 24
#define FPGA_DCM_WR_DATA_ADDRESS_BITS 23:16
#define FPGA_DCM_WR_DATA_ADDRESS_SET 0x00ff0000
#define FPGA_DCM_WR_DATA_ADDRESS_CLR 0xff00ffff
#define FPGA_DCM_WR_DATA_ADDRESS_MSB 23
#define FPGA_DCM_WR_DATA_ADDRESS_LSB 16
#define FPGA_DCM_WR_DATA_DATA_BITS 15:0
#define FPGA_DCM_WR_DATA_DATA_SET 0x0000ffff
#define FPGA_DCM_WR_DATA_DATA_CLR 0xffff0000
#define FPGA_DCM_WR_DATA_DATA_MSB 15
#define FPGA_DCM_WR_DATA_DATA_LSB 0
#define FPGA_DCM_CTRL HW_REGISTER_RW( 0x7e20b614 )
#define FPGA_DCM_CTRL_MASK 0xff0fffff
#define FPGA_DCM_CTRL_WIDTH 32
#define FPGA_DCM_CTRL_PERI_WR_EN_BITS 31:28
#define FPGA_DCM_CTRL_PERI_WR_EN_SET 0xf0000000
#define FPGA_DCM_CTRL_PERI_WR_EN_CLR 0x0fffffff
#define FPGA_DCM_CTRL_PERI_WR_EN_MSB 31
#define FPGA_DCM_CTRL_PERI_WR_EN_LSB 28
#define FPGA_DCM_CTRL_PERI_EN_BITS 27:24
#define FPGA_DCM_CTRL_PERI_EN_SET 0x0f000000
#define FPGA_DCM_CTRL_PERI_EN_CLR 0xf0ffffff
#define FPGA_DCM_CTRL_PERI_EN_MSB 27
#define FPGA_DCM_CTRL_PERI_EN_LSB 24
#define FPGA_DCM_CTRL_PERI_RST_BITS 19:16
#define FPGA_DCM_CTRL_PERI_RST_SET 0x000f0000
#define FPGA_DCM_CTRL_PERI_RST_CLR 0xfff0ffff
#define FPGA_DCM_CTRL_PERI_RST_MSB 19
#define FPGA_DCM_CTRL_PERI_RST_LSB 16
#define FPGA_DCM_CTRL_REMOTE_EN_BITS 12:8
#define FPGA_DCM_CTRL_REMOTE_EN_SET 0x00001f00
#define FPGA_DCM_CTRL_REMOTE_EN_CLR 0xffffe0ff
#define FPGA_DCM_CTRL_REMOTE_EN_MSB 12
#define FPGA_DCM_CTRL_REMOTE_EN_LSB 8
#define FPGA_DCM_CTRL_REMOTE_RST_BITS 4:0
#define FPGA_DCM_CTRL_REMOTE_RST_SET 0x0000001f
#define FPGA_DCM_CTRL_REMOTE_RST_CLR 0xffffffe0
#define FPGA_DCM_CTRL_REMOTE_RST_MSB 4
#define FPGA_DCM_CTRL_REMOTE_RST_LSB 0
#define FPGA_DCM_RD_DATA HW_REGISTER_RO( 0x7e20b618 )
#define FPGA_DCM_RD_DATA_MASK 0x0000ffff
#define FPGA_DCM_RD_DATA_WIDTH 16
#define FPGA_DCM_RD_DATA_DATA_BITS 15:0
#define FPGA_DCM_RD_DATA_DATA_SET 0x0000ffff
#define FPGA_DCM_RD_DATA_DATA_CLR 0xffff0000
#define FPGA_DCM_RD_DATA_DATA_MSB 15
#define FPGA_DCM_RD_DATA_DATA_LSB 0

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bcm2708_chip/gpio.h Executable file
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// This file was generated by the create_regs script
#define GP_BASE 0x7e200000
#define GP_APB_ID 0x6770696f
#define GP_FSEL0 HW_REGISTER_RW( 0x7e200000 )
#define GP_FSEL0_MASK 0x3fffffff
#define GP_FSEL0_WIDTH 30
#define GP_FSEL0_RESET 0000000000
#define GP_FSEL0_FSEL09_BITS 29:27
#define GP_FSEL0_FSEL09_SET 0x38000000
#define GP_FSEL0_FSEL09_CLR 0xc7ffffff
#define GP_FSEL0_FSEL09_MSB 29
#define GP_FSEL0_FSEL09_LSB 27
#define GP_FSEL0_FSEL08_BITS 26:24
#define GP_FSEL0_FSEL08_SET 0x07000000
#define GP_FSEL0_FSEL08_CLR 0xf8ffffff
#define GP_FSEL0_FSEL08_MSB 26
#define GP_FSEL0_FSEL08_LSB 24
#define GP_FSEL0_FSEL07_BITS 23:21
#define GP_FSEL0_FSEL07_SET 0x00e00000
#define GP_FSEL0_FSEL07_CLR 0xff1fffff
#define GP_FSEL0_FSEL07_MSB 23
#define GP_FSEL0_FSEL07_LSB 21
#define GP_FSEL0_FSEL06_BITS 20:18
#define GP_FSEL0_FSEL06_SET 0x001c0000
#define GP_FSEL0_FSEL06_CLR 0xffe3ffff
#define GP_FSEL0_FSEL06_MSB 20
#define GP_FSEL0_FSEL06_LSB 18
#define GP_FSEL0_FSEL05_BITS 17:15
#define GP_FSEL0_FSEL05_SET 0x00038000
#define GP_FSEL0_FSEL05_CLR 0xfffc7fff
#define GP_FSEL0_FSEL05_MSB 17
#define GP_FSEL0_FSEL05_LSB 15
#define GP_FSEL0_FSEL04_BITS 14:12
#define GP_FSEL0_FSEL04_SET 0x00007000
#define GP_FSEL0_FSEL04_CLR 0xffff8fff
#define GP_FSEL0_FSEL04_MSB 14
#define GP_FSEL0_FSEL04_LSB 12
#define GP_FSEL0_FSEL03_BITS 11:9
#define GP_FSEL0_FSEL03_SET 0x00000e00
#define GP_FSEL0_FSEL03_CLR 0xfffff1ff
#define GP_FSEL0_FSEL03_MSB 11
#define GP_FSEL0_FSEL03_LSB 9
#define GP_FSEL0_FSEL02_BITS 8:6
#define GP_FSEL0_FSEL02_SET 0x000001c0
#define GP_FSEL0_FSEL02_CLR 0xfffffe3f
#define GP_FSEL0_FSEL02_MSB 8
#define GP_FSEL0_FSEL02_LSB 6
#define GP_FSEL0_FSEL01_BITS 5:3
#define GP_FSEL0_FSEL01_SET 0x00000038
#define GP_FSEL0_FSEL01_CLR 0xffffffc7
#define GP_FSEL0_FSEL01_MSB 5
#define GP_FSEL0_FSEL01_LSB 3
#define GP_FSEL0_FSEL00_BITS 2:0
#define GP_FSEL0_FSEL00_SET 0x00000007
#define GP_FSEL0_FSEL00_CLR 0xfffffff8
#define GP_FSEL0_FSEL00_MSB 2
#define GP_FSEL0_FSEL00_LSB 0
#define GP_FSEL1 HW_REGISTER_RW( 0x7e200004 )
#define GP_FSEL1_MASK 0x3fffffff
#define GP_FSEL1_WIDTH 30
#define GP_FSEL1_RESET 0000000000
#define GP_FSEL1_FSEL19_BITS 29:27
#define GP_FSEL1_FSEL19_SET 0x38000000
#define GP_FSEL1_FSEL19_CLR 0xc7ffffff
#define GP_FSEL1_FSEL19_MSB 29
#define GP_FSEL1_FSEL19_LSB 27
#define GP_FSEL1_FSEL18_BITS 26:24
#define GP_FSEL1_FSEL18_SET 0x07000000
#define GP_FSEL1_FSEL18_CLR 0xf8ffffff
#define GP_FSEL1_FSEL18_MSB 26
#define GP_FSEL1_FSEL18_LSB 24
#define GP_FSEL1_FSEL17_BITS 23:21
#define GP_FSEL1_FSEL17_SET 0x00e00000
#define GP_FSEL1_FSEL17_CLR 0xff1fffff
#define GP_FSEL1_FSEL17_MSB 23
#define GP_FSEL1_FSEL17_LSB 21
#define GP_FSEL1_FSEL16_BITS 20:18
#define GP_FSEL1_FSEL16_SET 0x001c0000
#define GP_FSEL1_FSEL16_CLR 0xffe3ffff
#define GP_FSEL1_FSEL16_MSB 20
#define GP_FSEL1_FSEL16_LSB 18
#define GP_FSEL1_FSEL15_BITS 17:15
#define GP_FSEL1_FSEL15_SET 0x00038000
#define GP_FSEL1_FSEL15_CLR 0xfffc7fff
#define GP_FSEL1_FSEL15_MSB 17
#define GP_FSEL1_FSEL15_LSB 15
#define GP_FSEL1_FSEL14_BITS 14:12
#define GP_FSEL1_FSEL14_SET 0x00007000
#define GP_FSEL1_FSEL14_CLR 0xffff8fff
#define GP_FSEL1_FSEL14_MSB 14
#define GP_FSEL1_FSEL14_LSB 12
#define GP_FSEL1_FSEL13_BITS 11:9
#define GP_FSEL1_FSEL13_SET 0x00000e00
#define GP_FSEL1_FSEL13_CLR 0xfffff1ff
#define GP_FSEL1_FSEL13_MSB 11
#define GP_FSEL1_FSEL13_LSB 9
#define GP_FSEL1_FSEL12_BITS 8:6
#define GP_FSEL1_FSEL12_SET 0x000001c0
#define GP_FSEL1_FSEL12_CLR 0xfffffe3f
#define GP_FSEL1_FSEL12_MSB 8
#define GP_FSEL1_FSEL12_LSB 6
#define GP_FSEL1_FSEL11_BITS 5:3
#define GP_FSEL1_FSEL11_SET 0x00000038
#define GP_FSEL1_FSEL11_CLR 0xffffffc7
#define GP_FSEL1_FSEL11_MSB 5
#define GP_FSEL1_FSEL11_LSB 3
#define GP_FSEL1_FSEL10_BITS 2:0
#define GP_FSEL1_FSEL10_SET 0x00000007
#define GP_FSEL1_FSEL10_CLR 0xfffffff8
#define GP_FSEL1_FSEL10_MSB 2
#define GP_FSEL1_FSEL10_LSB 0
#define GP_FSEL2 HW_REGISTER_RW( 0x7e200008 )
#define GP_FSEL2_MASK 0x3fffffff
#define GP_FSEL2_WIDTH 30
#define GP_FSEL2_RESET 0000000000
#define GP_FSEL2_FSEL29_BITS 29:27
#define GP_FSEL2_FSEL29_SET 0x38000000
#define GP_FSEL2_FSEL29_CLR 0xc7ffffff
#define GP_FSEL2_FSEL29_MSB 29
#define GP_FSEL2_FSEL29_LSB 27
#define GP_FSEL2_FSEL28_BITS 26:24
#define GP_FSEL2_FSEL28_SET 0x07000000
#define GP_FSEL2_FSEL28_CLR 0xf8ffffff
#define GP_FSEL2_FSEL28_MSB 26
#define GP_FSEL2_FSEL28_LSB 24
#define GP_FSEL2_FSEL27_BITS 23:21
#define GP_FSEL2_FSEL27_SET 0x00e00000
#define GP_FSEL2_FSEL27_CLR 0xff1fffff
#define GP_FSEL2_FSEL27_MSB 23
#define GP_FSEL2_FSEL27_LSB 21
#define GP_FSEL2_FSEL26_BITS 20:18
#define GP_FSEL2_FSEL26_SET 0x001c0000
#define GP_FSEL2_FSEL26_CLR 0xffe3ffff
#define GP_FSEL2_FSEL26_MSB 20
#define GP_FSEL2_FSEL26_LSB 18
#define GP_FSEL2_FSEL25_BITS 17:15
#define GP_FSEL2_FSEL25_SET 0x00038000
#define GP_FSEL2_FSEL25_CLR 0xfffc7fff
#define GP_FSEL2_FSEL25_MSB 17
#define GP_FSEL2_FSEL25_LSB 15
#define GP_FSEL2_FSEL24_BITS 14:12
#define GP_FSEL2_FSEL24_SET 0x00007000
#define GP_FSEL2_FSEL24_CLR 0xffff8fff
#define GP_FSEL2_FSEL24_MSB 14
#define GP_FSEL2_FSEL24_LSB 12
#define GP_FSEL2_FSEL23_BITS 11:9
#define GP_FSEL2_FSEL23_SET 0x00000e00
#define GP_FSEL2_FSEL23_CLR 0xfffff1ff
#define GP_FSEL2_FSEL23_MSB 11
#define GP_FSEL2_FSEL23_LSB 9
#define GP_FSEL2_FSEL22_BITS 8:6
#define GP_FSEL2_FSEL22_SET 0x000001c0
#define GP_FSEL2_FSEL22_CLR 0xfffffe3f
#define GP_FSEL2_FSEL22_MSB 8
#define GP_FSEL2_FSEL22_LSB 6
#define GP_FSEL2_FSEL21_BITS 5:3
#define GP_FSEL2_FSEL21_SET 0x00000038
#define GP_FSEL2_FSEL21_CLR 0xffffffc7
#define GP_FSEL2_FSEL21_MSB 5
#define GP_FSEL2_FSEL21_LSB 3
#define GP_FSEL2_FSEL20_BITS 2:0
#define GP_FSEL2_FSEL20_SET 0x00000007
#define GP_FSEL2_FSEL20_CLR 0xfffffff8
#define GP_FSEL2_FSEL20_MSB 2
#define GP_FSEL2_FSEL20_LSB 0
#define GP_FSEL3 HW_REGISTER_RW( 0x7e20000c )
#define GP_FSEL3_MASK 0x3fffffff
#define GP_FSEL3_WIDTH 30
#define GP_FSEL3_RESET 0000000000
#define GP_FSEL3_FSEL39_BITS 29:27
#define GP_FSEL3_FSEL39_SET 0x38000000
#define GP_FSEL3_FSEL39_CLR 0xc7ffffff
#define GP_FSEL3_FSEL39_MSB 29
#define GP_FSEL3_FSEL39_LSB 27
#define GP_FSEL3_FSEL38_BITS 26:24
#define GP_FSEL3_FSEL38_SET 0x07000000
#define GP_FSEL3_FSEL38_CLR 0xf8ffffff
#define GP_FSEL3_FSEL38_MSB 26
#define GP_FSEL3_FSEL38_LSB 24
#define GP_FSEL3_FSEL37_BITS 23:21
#define GP_FSEL3_FSEL37_SET 0x00e00000
#define GP_FSEL3_FSEL37_CLR 0xff1fffff
#define GP_FSEL3_FSEL37_MSB 23
#define GP_FSEL3_FSEL37_LSB 21
#define GP_FSEL3_FSEL36_BITS 20:18
#define GP_FSEL3_FSEL36_SET 0x001c0000
#define GP_FSEL3_FSEL36_CLR 0xffe3ffff
#define GP_FSEL3_FSEL36_MSB 20
#define GP_FSEL3_FSEL36_LSB 18
#define GP_FSEL3_FSEL35_BITS 17:15
#define GP_FSEL3_FSEL35_SET 0x00038000
#define GP_FSEL3_FSEL35_CLR 0xfffc7fff
#define GP_FSEL3_FSEL35_MSB 17
#define GP_FSEL3_FSEL35_LSB 15
#define GP_FSEL3_FSEL34_BITS 14:12
#define GP_FSEL3_FSEL34_SET 0x00007000
#define GP_FSEL3_FSEL34_CLR 0xffff8fff
#define GP_FSEL3_FSEL34_MSB 14
#define GP_FSEL3_FSEL34_LSB 12
#define GP_FSEL3_FSEL33_BITS 11:9
#define GP_FSEL3_FSEL33_SET 0x00000e00
#define GP_FSEL3_FSEL33_CLR 0xfffff1ff
#define GP_FSEL3_FSEL33_MSB 11
#define GP_FSEL3_FSEL33_LSB 9
#define GP_FSEL3_FSEL32_BITS 8:6
#define GP_FSEL3_FSEL32_SET 0x000001c0
#define GP_FSEL3_FSEL32_CLR 0xfffffe3f
#define GP_FSEL3_FSEL32_MSB 8
#define GP_FSEL3_FSEL32_LSB 6
#define GP_FSEL3_FSEL31_BITS 5:3
#define GP_FSEL3_FSEL31_SET 0x00000038
#define GP_FSEL3_FSEL31_CLR 0xffffffc7
#define GP_FSEL3_FSEL31_MSB 5
#define GP_FSEL3_FSEL31_LSB 3
#define GP_FSEL3_FSEL30_BITS 2:0
#define GP_FSEL3_FSEL30_SET 0x00000007
#define GP_FSEL3_FSEL30_CLR 0xfffffff8
#define GP_FSEL3_FSEL30_MSB 2
#define GP_FSEL3_FSEL30_LSB 0
#define GP_FSEL4 HW_REGISTER_RW( 0x7e200010 )
#define GP_FSEL4_MASK 0x3fffffff
#define GP_FSEL4_WIDTH 30
#define GP_FSEL4_RESET 0000000000
#define GP_FSEL4_FSEL49_BITS 29:27
#define GP_FSEL4_FSEL49_SET 0x38000000
#define GP_FSEL4_FSEL49_CLR 0xc7ffffff
#define GP_FSEL4_FSEL49_MSB 29
#define GP_FSEL4_FSEL49_LSB 27
#define GP_FSEL4_FSEL48_BITS 26:24
#define GP_FSEL4_FSEL48_SET 0x07000000
#define GP_FSEL4_FSEL48_CLR 0xf8ffffff
#define GP_FSEL4_FSEL48_MSB 26
#define GP_FSEL4_FSEL48_LSB 24
#define GP_FSEL4_FSEL47_BITS 23:21
#define GP_FSEL4_FSEL47_SET 0x00e00000
#define GP_FSEL4_FSEL47_CLR 0xff1fffff
#define GP_FSEL4_FSEL47_MSB 23
#define GP_FSEL4_FSEL47_LSB 21
#define GP_FSEL4_FSEL46_BITS 20:18
#define GP_FSEL4_FSEL46_SET 0x001c0000
#define GP_FSEL4_FSEL46_CLR 0xffe3ffff
#define GP_FSEL4_FSEL46_MSB 20
#define GP_FSEL4_FSEL46_LSB 18
#define GP_FSEL4_FSEL45_BITS 17:15
#define GP_FSEL4_FSEL45_SET 0x00038000
#define GP_FSEL4_FSEL45_CLR 0xfffc7fff
#define GP_FSEL4_FSEL45_MSB 17
#define GP_FSEL4_FSEL45_LSB 15
#define GP_FSEL4_FSEL44_BITS 14:12
#define GP_FSEL4_FSEL44_SET 0x00007000
#define GP_FSEL4_FSEL44_CLR 0xffff8fff
#define GP_FSEL4_FSEL44_MSB 14
#define GP_FSEL4_FSEL44_LSB 12
#define GP_FSEL4_FSEL43_BITS 11:9
#define GP_FSEL4_FSEL43_SET 0x00000e00
#define GP_FSEL4_FSEL43_CLR 0xfffff1ff
#define GP_FSEL4_FSEL43_MSB 11
#define GP_FSEL4_FSEL43_LSB 9
#define GP_FSEL4_FSEL42_BITS 8:6
#define GP_FSEL4_FSEL42_SET 0x000001c0
#define GP_FSEL4_FSEL42_CLR 0xfffffe3f
#define GP_FSEL4_FSEL42_MSB 8
#define GP_FSEL4_FSEL42_LSB 6
#define GP_FSEL4_FSEL41_BITS 5:3
#define GP_FSEL4_FSEL41_SET 0x00000038
#define GP_FSEL4_FSEL41_CLR 0xffffffc7
#define GP_FSEL4_FSEL41_MSB 5
#define GP_FSEL4_FSEL41_LSB 3
#define GP_FSEL4_FSEL40_BITS 2:0
#define GP_FSEL4_FSEL40_SET 0x00000007
#define GP_FSEL4_FSEL40_CLR 0xfffffff8
#define GP_FSEL4_FSEL40_MSB 2
#define GP_FSEL4_FSEL40_LSB 0
#define GP_FSEL5 HW_REGISTER_RW( 0x7e200014 )
#define GP_FSEL5_MASK 0x3fffffff
#define GP_FSEL5_WIDTH 30
#define GP_FSEL5_RESET 0000000000
#define GP_FSEL5_FSEL59_BITS 29:27
#define GP_FSEL5_FSEL59_SET 0x38000000
#define GP_FSEL5_FSEL59_CLR 0xc7ffffff
#define GP_FSEL5_FSEL59_MSB 29
#define GP_FSEL5_FSEL59_LSB 27
#define GP_FSEL5_FSEL58_BITS 26:24
#define GP_FSEL5_FSEL58_SET 0x07000000
#define GP_FSEL5_FSEL58_CLR 0xf8ffffff
#define GP_FSEL5_FSEL58_MSB 26
#define GP_FSEL5_FSEL58_LSB 24
#define GP_FSEL5_FSEL57_BITS 23:21
#define GP_FSEL5_FSEL57_SET 0x00e00000
#define GP_FSEL5_FSEL57_CLR 0xff1fffff
#define GP_FSEL5_FSEL57_MSB 23
#define GP_FSEL5_FSEL57_LSB 21
#define GP_FSEL5_FSEL56_BITS 20:18
#define GP_FSEL5_FSEL56_SET 0x001c0000
#define GP_FSEL5_FSEL56_CLR 0xffe3ffff
#define GP_FSEL5_FSEL56_MSB 20
#define GP_FSEL5_FSEL56_LSB 18
#define GP_FSEL5_FSEL55_BITS 17:15
#define GP_FSEL5_FSEL55_SET 0x00038000
#define GP_FSEL5_FSEL55_CLR 0xfffc7fff
#define GP_FSEL5_FSEL55_MSB 17
#define GP_FSEL5_FSEL55_LSB 15
#define GP_FSEL5_FSEL54_BITS 14:12
#define GP_FSEL5_FSEL54_SET 0x00007000
#define GP_FSEL5_FSEL54_CLR 0xffff8fff
#define GP_FSEL5_FSEL54_MSB 14
#define GP_FSEL5_FSEL54_LSB 12
#define GP_FSEL5_FSEL53_BITS 11:9
#define GP_FSEL5_FSEL53_SET 0x00000e00
#define GP_FSEL5_FSEL53_CLR 0xfffff1ff
#define GP_FSEL5_FSEL53_MSB 11
#define GP_FSEL5_FSEL53_LSB 9
#define GP_FSEL5_FSEL52_BITS 8:6
#define GP_FSEL5_FSEL52_SET 0x000001c0
#define GP_FSEL5_FSEL52_CLR 0xfffffe3f
#define GP_FSEL5_FSEL52_MSB 8
#define GP_FSEL5_FSEL52_LSB 6
#define GP_FSEL5_FSEL51_BITS 5:3
#define GP_FSEL5_FSEL51_SET 0x00000038
#define GP_FSEL5_FSEL51_CLR 0xffffffc7
#define GP_FSEL5_FSEL51_MSB 5
#define GP_FSEL5_FSEL51_LSB 3
#define GP_FSEL5_FSEL50_BITS 2:0
#define GP_FSEL5_FSEL50_SET 0x00000007
#define GP_FSEL5_FSEL50_CLR 0xfffffff8
#define GP_FSEL5_FSEL50_MSB 2
#define GP_FSEL5_FSEL50_LSB 0
#define GP_FSEL6 HW_REGISTER_RW( 0x7e200018 )
#define GP_FSEL6_MASK 0x3fffffff
#define GP_FSEL6_WIDTH 30
#define GP_FSEL6_RESET 0000000000
#define GP_FSEL6_FSEL69_BITS 29:27
#define GP_FSEL6_FSEL69_SET 0x38000000
#define GP_FSEL6_FSEL69_CLR 0xc7ffffff
#define GP_FSEL6_FSEL69_MSB 29
#define GP_FSEL6_FSEL69_LSB 27
#define GP_FSEL6_FSEL68_BITS 26:24
#define GP_FSEL6_FSEL68_SET 0x07000000
#define GP_FSEL6_FSEL68_CLR 0xf8ffffff
#define GP_FSEL6_FSEL68_MSB 26
#define GP_FSEL6_FSEL68_LSB 24
#define GP_FSEL6_FSEL67_BITS 23:21
#define GP_FSEL6_FSEL67_SET 0x00e00000
#define GP_FSEL6_FSEL67_CLR 0xff1fffff
#define GP_FSEL6_FSEL67_MSB 23
#define GP_FSEL6_FSEL67_LSB 21
#define GP_FSEL6_FSEL66_BITS 20:18
#define GP_FSEL6_FSEL66_SET 0x001c0000
#define GP_FSEL6_FSEL66_CLR 0xffe3ffff
#define GP_FSEL6_FSEL66_MSB 20
#define GP_FSEL6_FSEL66_LSB 18
#define GP_FSEL6_FSEL65_BITS 17:15
#define GP_FSEL6_FSEL65_SET 0x00038000
#define GP_FSEL6_FSEL65_CLR 0xfffc7fff
#define GP_FSEL6_FSEL65_MSB 17
#define GP_FSEL6_FSEL65_LSB 15
#define GP_FSEL6_FSEL64_BITS 14:12
#define GP_FSEL6_FSEL64_SET 0x00007000
#define GP_FSEL6_FSEL64_CLR 0xffff8fff
#define GP_FSEL6_FSEL64_MSB 14
#define GP_FSEL6_FSEL64_LSB 12
#define GP_FSEL6_FSEL63_BITS 11:9
#define GP_FSEL6_FSEL63_SET 0x00000e00
#define GP_FSEL6_FSEL63_CLR 0xfffff1ff
#define GP_FSEL6_FSEL63_MSB 11
#define GP_FSEL6_FSEL63_LSB 9
#define GP_FSEL6_FSEL62_BITS 8:6
#define GP_FSEL6_FSEL62_SET 0x000001c0
#define GP_FSEL6_FSEL62_CLR 0xfffffe3f
#define GP_FSEL6_FSEL62_MSB 8
#define GP_FSEL6_FSEL62_LSB 6
#define GP_FSEL6_FSEL61_BITS 5:3
#define GP_FSEL6_FSEL61_SET 0x00000038
#define GP_FSEL6_FSEL61_CLR 0xffffffc7
#define GP_FSEL6_FSEL61_MSB 5
#define GP_FSEL6_FSEL61_LSB 3
#define GP_FSEL6_FSEL60_BITS 2:0
#define GP_FSEL6_FSEL60_SET 0x00000007
#define GP_FSEL6_FSEL60_CLR 0xfffffff8
#define GP_FSEL6_FSEL60_MSB 2
#define GP_FSEL6_FSEL60_LSB 0
#define GP_SET0 HW_REGISTER_RW( 0x7e20001c )
#define GP_SET0_MASK 0xffffffff
#define GP_SET0_WIDTH 32
#define GP_SET0_RESET 0000000000
#define GP_SET0_SETn0_BITS 31:0
#define GP_SET0_SETn0_SET 0xffffffff
#define GP_SET0_SETn0_CLR 0x00000000
#define GP_SET0_SETn0_MSB 31
#define GP_SET0_SETn0_LSB 0
#define GP_SET1 HW_REGISTER_RW( 0x7e200020 )
#define GP_SET1_MASK 0xffffffff
#define GP_SET1_WIDTH 32
#define GP_SET1_RESET 0000000000
#define GP_SET1_SETn32_BITS 31:0
#define GP_SET1_SETn32_SET 0xffffffff
#define GP_SET1_SETn32_CLR 0x00000000
#define GP_SET1_SETn32_MSB 31
#define GP_SET1_SETn32_LSB 0
#define GP_SET2 HW_REGISTER_RW( 0x7e200024 )
#define GP_SET2_MASK 0x0000003f
#define GP_SET2_WIDTH 6
#define GP_SET2_RESET 0000000000
#define GP_SET2_SETn64_BITS 5:0
#define GP_SET2_SETn64_SET 0x0000003f
#define GP_SET2_SETn64_CLR 0xffffffc0
#define GP_SET2_SETn64_MSB 5
#define GP_SET2_SETn64_LSB 0
#define GP_CLR0 HW_REGISTER_RW( 0x7e200028 )
#define GP_CLR0_MASK 0xffffffff
#define GP_CLR0_WIDTH 32
#define GP_CLR0_RESET 0000000000
#define GP_CLR0_CLRn0_BITS 31:0
#define GP_CLR0_CLRn0_SET 0xffffffff
#define GP_CLR0_CLRn0_CLR 0x00000000
#define GP_CLR0_CLRn0_MSB 31
#define GP_CLR0_CLRn0_LSB 0
#define GP_CLR1 HW_REGISTER_RW( 0x7e20002c )
#define GP_CLR1_MASK 0xffffffff
#define GP_CLR1_WIDTH 32
#define GP_CLR1_RESET 0000000000
#define GP_CLR1_CLRn32_BITS 31:0
#define GP_CLR1_CLRn32_SET 0xffffffff
#define GP_CLR1_CLRn32_CLR 0x00000000
#define GP_CLR1_CLRn32_MSB 31
#define GP_CLR1_CLRn32_LSB 0
#define GP_CLR2 HW_REGISTER_RW( 0x7e200030 )
#define GP_CLR2_MASK 0x0000003f
#define GP_CLR2_WIDTH 6
#define GP_CLR2_RESET 0000000000
#define GP_CLR2_CLRn64_BITS 5:0
#define GP_CLR2_CLRn64_SET 0x0000003f
#define GP_CLR2_CLRn64_CLR 0xffffffc0
#define GP_CLR2_CLRn64_MSB 5
#define GP_CLR2_CLRn64_LSB 0
#define GP_LEV0 HW_REGISTER_RO( 0x7e200034 )
#define GP_LEV0_MASK 0xffffffff
#define GP_LEV0_WIDTH 32
#define GP_LEV0_RESET 0000000000
#define GP_LEV0_LEVn0_BITS 31:0
#define GP_LEV0_LEVn0_SET 0xffffffff
#define GP_LEV0_LEVn0_CLR 0x00000000
#define GP_LEV0_LEVn0_MSB 31
#define GP_LEV0_LEVn0_LSB 0
#define GP_LEV1 HW_REGISTER_RO( 0x7e200038 )
#define GP_LEV1_MASK 0xffffffff
#define GP_LEV1_WIDTH 32
#define GP_LEV1_RESET 0000000000
#define GP_LEV1_LEVn32_BITS 31:0
#define GP_LEV1_LEVn32_SET 0xffffffff
#define GP_LEV1_LEVn32_CLR 0x00000000
#define GP_LEV1_LEVn32_MSB 31
#define GP_LEV1_LEVn32_LSB 0
#define GP_LEV2 HW_REGISTER_RO( 0x7e20003c )
#define GP_LEV2_MASK 0x0000003f
#define GP_LEV2_WIDTH 6
#define GP_LEV2_RESET 0000000000
#define GP_LEV2_LEVn64_BITS 5:0
#define GP_LEV2_LEVn64_SET 0x0000003f
#define GP_LEV2_LEVn64_CLR 0xffffffc0
#define GP_LEV2_LEVn64_MSB 5
#define GP_LEV2_LEVn64_LSB 0
#define GP_EDS0 HW_REGISTER_RW( 0x7e200040 )
#define GP_EDS0_MASK 0xffffffff
#define GP_EDS0_WIDTH 32
#define GP_EDS0_RESET 0000000000
#define GP_EDS0_EDSn0_BITS 31:0
#define GP_EDS0_EDSn0_SET 0xffffffff
#define GP_EDS0_EDSn0_CLR 0x00000000
#define GP_EDS0_EDSn0_MSB 31
#define GP_EDS0_EDSn0_LSB 0
#define GP_EDS1 HW_REGISTER_RW( 0x7e200044 )
#define GP_EDS1_MASK 0xffffffff
#define GP_EDS1_WIDTH 32
#define GP_EDS1_RESET 0000000000
#define GP_EDS1_EDSn32_BITS 31:0
#define GP_EDS1_EDSn32_SET 0xffffffff
#define GP_EDS1_EDSn32_CLR 0x00000000
#define GP_EDS1_EDSn32_MSB 31
#define GP_EDS1_EDSn32_LSB 0
#define GP_EDS2 HW_REGISTER_RW( 0x7e200048 )
#define GP_EDS2_MASK 0x0000003f
#define GP_EDS2_WIDTH 6
#define GP_EDS2_RESET 0000000000
#define GP_EDS2_EDSn64_BITS 5:0
#define GP_EDS2_EDSn64_SET 0x0000003f
#define GP_EDS2_EDSn64_CLR 0xffffffc0
#define GP_EDS2_EDSn64_MSB 5
#define GP_EDS2_EDSn64_LSB 0
#define GP_REN0 HW_REGISTER_RW( 0x7e20004c )
#define GP_REN0_MASK 0xffffffff
#define GP_REN0_WIDTH 32
#define GP_REN0_RESET 0000000000
#define GP_REN0_RENn0_BITS 31:0
#define GP_REN0_RENn0_SET 0xffffffff
#define GP_REN0_RENn0_CLR 0x00000000
#define GP_REN0_RENn0_MSB 31
#define GP_REN0_RENn0_LSB 0
#define GP_REN1 HW_REGISTER_RW( 0x7e200050 )
#define GP_REN1_MASK 0xffffffff
#define GP_REN1_WIDTH 32
#define GP_REN1_RESET 0000000000
#define GP_REN1_RENn32_BITS 31:0
#define GP_REN1_RENn32_SET 0xffffffff
#define GP_REN1_RENn32_CLR 0x00000000
#define GP_REN1_RENn32_MSB 31
#define GP_REN1_RENn32_LSB 0
#define GP_REN2 HW_REGISTER_RW( 0x7e200054 )
#define GP_REN2_MASK 0x0000003f
#define GP_REN2_WIDTH 6
#define GP_REN2_RESET 0000000000
#define GP_REN2_RENn64_BITS 5:0
#define GP_REN2_RENn64_SET 0x0000003f
#define GP_REN2_RENn64_CLR 0xffffffc0
#define GP_REN2_RENn64_MSB 5
#define GP_REN2_RENn64_LSB 0
#define GP_FEN0 HW_REGISTER_RW( 0x7e200058 )
#define GP_FEN0_MASK 0xffffffff
#define GP_FEN0_WIDTH 32
#define GP_FEN0_RESET 0000000000
#define GP_FEN0_FENn0_BITS 31:0
#define GP_FEN0_FENn0_SET 0xffffffff
#define GP_FEN0_FENn0_CLR 0x00000000
#define GP_FEN0_FENn0_MSB 31
#define GP_FEN0_FENn0_LSB 0
#define GP_FEN1 HW_REGISTER_RW( 0x7e20005c )
#define GP_FEN1_MASK 0xffffffff
#define GP_FEN1_WIDTH 32
#define GP_FEN1_RESET 0000000000
#define GP_FEN1_FENn32_BITS 31:0
#define GP_FEN1_FENn32_SET 0xffffffff
#define GP_FEN1_FENn32_CLR 0x00000000
#define GP_FEN1_FENn32_MSB 31
#define GP_FEN1_FENn32_LSB 0
#define GP_FEN2 HW_REGISTER_RW( 0x7e200060 )
#define GP_FEN2_MASK 0x0000003f
#define GP_FEN2_WIDTH 6
#define GP_FEN2_RESET 0000000000
#define GP_FEN2_FENn64_BITS 5:0
#define GP_FEN2_FENn64_SET 0x0000003f
#define GP_FEN2_FENn64_CLR 0xffffffc0
#define GP_FEN2_FENn64_MSB 5
#define GP_FEN2_FENn64_LSB 0
#define GP_HEN0 HW_REGISTER_RW( 0x7e200064 )
#define GP_HEN0_MASK 0xffffffff
#define GP_HEN0_WIDTH 32
#define GP_HEN0_RESET 0000000000
#define GP_HEN0_HENn0_BITS 31:0
#define GP_HEN0_HENn0_SET 0xffffffff
#define GP_HEN0_HENn0_CLR 0x00000000
#define GP_HEN0_HENn0_MSB 31
#define GP_HEN0_HENn0_LSB 0
#define GP_HEN1 HW_REGISTER_RW( 0x7e200068 )
#define GP_HEN1_MASK 0xffffffff
#define GP_HEN1_WIDTH 32
#define GP_HEN1_RESET 0000000000
#define GP_HEN1_HENn32_BITS 31:0
#define GP_HEN1_HENn32_SET 0xffffffff
#define GP_HEN1_HENn32_CLR 0x00000000
#define GP_HEN1_HENn32_MSB 31
#define GP_HEN1_HENn32_LSB 0
#define GP_HEN2 HW_REGISTER_RW( 0x7e20006c )
#define GP_HEN2_MASK 0x0000003f
#define GP_HEN2_WIDTH 6
#define GP_HEN2_RESET 0000000000
#define GP_HEN2_HENn64_BITS 5:0
#define GP_HEN2_HENn64_SET 0x0000003f
#define GP_HEN2_HENn64_CLR 0xffffffc0
#define GP_HEN2_HENn64_MSB 5
#define GP_HEN2_HENn64_LSB 0
#define GP_LEN0 HW_REGISTER_RW( 0x7e200070 )
#define GP_LEN0_MASK 0xffffffff
#define GP_LEN0_WIDTH 32
#define GP_LEN0_RESET 0000000000
#define GP_LEN0_LENn0_BITS 31:0
#define GP_LEN0_LENn0_SET 0xffffffff
#define GP_LEN0_LENn0_CLR 0x00000000
#define GP_LEN0_LENn0_MSB 31
#define GP_LEN0_LENn0_LSB 0
#define GP_LEN1 HW_REGISTER_RW( 0x7e200074 )
#define GP_LEN1_MASK 0xffffffff
#define GP_LEN1_WIDTH 32
#define GP_LEN1_RESET 0000000000
#define GP_LEN1_LENn32_BITS 31:0
#define GP_LEN1_LENn32_SET 0xffffffff
#define GP_LEN1_LENn32_CLR 0x00000000
#define GP_LEN1_LENn32_MSB 31
#define GP_LEN1_LENn32_LSB 0
#define GP_LEN2 HW_REGISTER_RW( 0x7e200078 )
#define GP_LEN2_MASK 0x0000003f
#define GP_LEN2_WIDTH 6
#define GP_LEN2_RESET 0000000000
#define GP_LEN2_LENn64_BITS 5:0
#define GP_LEN2_LENn64_SET 0x0000003f
#define GP_LEN2_LENn64_CLR 0xffffffc0
#define GP_LEN2_LENn64_MSB 5
#define GP_LEN2_LENn64_LSB 0
#define GP_AREN0 HW_REGISTER_RW( 0x7e20007c )
#define GP_AREN0_MASK 0xffffffff
#define GP_AREN0_WIDTH 32
#define GP_AREN0_RESET 0000000000
#define GP_AREN0_ARENn0_BITS 31:0
#define GP_AREN0_ARENn0_SET 0xffffffff
#define GP_AREN0_ARENn0_CLR 0x00000000
#define GP_AREN0_ARENn0_MSB 31
#define GP_AREN0_ARENn0_LSB 0
#define GP_AREN1 HW_REGISTER_RW( 0x7e200080 )
#define GP_AREN1_MASK 0xffffffff
#define GP_AREN1_WIDTH 32
#define GP_AREN1_RESET 0000000000
#define GP_AREN1_ARENn32_BITS 31:0
#define GP_AREN1_ARENn32_SET 0xffffffff
#define GP_AREN1_ARENn32_CLR 0x00000000
#define GP_AREN1_ARENn32_MSB 31
#define GP_AREN1_ARENn32_LSB 0
#define GP_AREN2 HW_REGISTER_RW( 0x7e200084 )
#define GP_AREN2_MASK 0x0000003f
#define GP_AREN2_WIDTH 6
#define GP_AREN2_RESET 0000000000
#define GP_AREN2_ARENn64_BITS 5:0
#define GP_AREN2_ARENn64_SET 0x0000003f
#define GP_AREN2_ARENn64_CLR 0xffffffc0
#define GP_AREN2_ARENn64_MSB 5
#define GP_AREN2_ARENn64_LSB 0
#define GP_AFEN0 HW_REGISTER_RW( 0x7e200088 )
#define GP_AFEN0_MASK 0xffffffff
#define GP_AFEN0_WIDTH 32
#define GP_AFEN0_RESET 0000000000
#define GP_AFEN0_AFENn0_BITS 31:0
#define GP_AFEN0_AFENn0_SET 0xffffffff
#define GP_AFEN0_AFENn0_CLR 0x00000000
#define GP_AFEN0_AFENn0_MSB 31
#define GP_AFEN0_AFENn0_LSB 0
#define GP_AFEN1 HW_REGISTER_RW( 0x7e20008c )
#define GP_AFEN1_MASK 0xffffffff
#define GP_AFEN1_WIDTH 32
#define GP_AFEN1_RESET 0000000000
#define GP_AFEN1_AFENn32_BITS 31:0
#define GP_AFEN1_AFENn32_SET 0xffffffff
#define GP_AFEN1_AFENn32_CLR 0x00000000
#define GP_AFEN1_AFENn32_MSB 31
#define GP_AFEN1_AFENn32_LSB 0
#define GP_AFEN2 HW_REGISTER_RW( 0x7e200090 )
#define GP_AFEN2_MASK 0x0000003f
#define GP_AFEN2_WIDTH 6
#define GP_AFEN2_RESET 0000000000
#define GP_AFEN2_AFENn64_BITS 5:0
#define GP_AFEN2_AFENn64_SET 0x0000003f
#define GP_AFEN2_AFENn64_CLR 0xffffffc0
#define GP_AFEN2_AFENn64_MSB 5
#define GP_AFEN2_AFENn64_LSB 0
#define GP_PUD HW_REGISTER_RW( 0x7e200094 )
#define GP_PUD_MASK 0x00000003
#define GP_PUD_WIDTH 2
#define GP_PUD_RESET 0000000000
#define GP_PUD_PUD_BITS 1:0
#define GP_PUD_PUD_SET 0x00000003
#define GP_PUD_PUD_CLR 0xfffffffc
#define GP_PUD_PUD_MSB 1
#define GP_PUD_PUD_LSB 0
#define GP_PUDCLK0 HW_REGISTER_RW( 0x7e200098 )
#define GP_PUDCLK0_MASK 0xffffffff
#define GP_PUDCLK0_WIDTH 32
#define GP_PUDCLK0_RESET 0000000000
#define GP_PUDCLK0_PUDCLKn0_BITS 31:0
#define GP_PUDCLK0_PUDCLKn0_SET 0xffffffff
#define GP_PUDCLK0_PUDCLKn0_CLR 0x00000000
#define GP_PUDCLK0_PUDCLKn0_MSB 31
#define GP_PUDCLK0_PUDCLKn0_LSB 0
#define GP_PUDCLK1 HW_REGISTER_RW( 0x7e20009c )
#define GP_PUDCLK1_MASK 0xffffffff
#define GP_PUDCLK1_WIDTH 32
#define GP_PUDCLK1_RESET 0000000000
#define GP_PUDCLK1_PUDCLKn32_BITS 31:0
#define GP_PUDCLK1_PUDCLKn32_SET 0xffffffff
#define GP_PUDCLK1_PUDCLKn32_CLR 0x00000000
#define GP_PUDCLK1_PUDCLKn32_MSB 31
#define GP_PUDCLK1_PUDCLKn32_LSB 0
#define GP_PUDCLK2 HW_REGISTER_RW( 0x7e2000a0 )
#define GP_PUDCLK2_MASK 0x0000003f
#define GP_PUDCLK2_WIDTH 6
#define GP_PUDCLK2_RESET 0000000000
#define GP_PUDCLK2_PUDCLKn64_BITS 5:0
#define GP_PUDCLK2_PUDCLKn64_SET 0x0000003f
#define GP_PUDCLK2_PUDCLKn64_CLR 0xffffffc0
#define GP_PUDCLK2_PUDCLKn64_MSB 5
#define GP_PUDCLK2_PUDCLKn64_LSB 0
#define GP_SEN0 HW_REGISTER_RW( 0x7e2000a4 )
#define GP_SEN0_MASK 0xffffffff
#define GP_SEN0_WIDTH 32
#define GP_SEN0_RESET 0xffffffff
#define GP_SEN0_SEN_BITS 31:0
#define GP_SEN0_SEN_SET 0xffffffff
#define GP_SEN0_SEN_CLR 0x00000000
#define GP_SEN0_SEN_MSB 31
#define GP_SEN0_SEN_LSB 0
#define GP_SEN1 HW_REGISTER_RW( 0x7e2000a8 )
#define GP_SEN1_MASK 0x003fffff
#define GP_SEN1_WIDTH 22
#define GP_SEN1_RESET 0x003fffff
#define GP_SEN1_SEN_BITS 21:0
#define GP_SEN1_SEN_SET 0x003fffff
#define GP_SEN1_SEN_CLR 0xffc00000
#define GP_SEN1_SEN_MSB 21
#define GP_SEN1_SEN_LSB 0
#define GP_GPTEST HW_REGISTER_RW( 0x7e2000b0 )
#define GP_GPTEST_MASK 0x0000000f
#define GP_GPTEST_WIDTH 4
#define GP_GPTEST_RESET 0000000000
#define GP_GPTEST_SMPS_BITS 0:0
#define GP_GPTEST_SMPS_SET 0x00000001
#define GP_GPTEST_SMPS_CLR 0xfffffffe
#define GP_GPTEST_SMPS_MSB 0
#define GP_GPTEST_SMPS_LSB 0
#define GP_GPTEST_SPARE_BITS 3:1
#define GP_GPTEST_SPARE_SET 0x0000000e
#define GP_GPTEST_SPARE_CLR 0xfffffff1
#define GP_GPTEST_SPARE_MSB 3
#define GP_GPTEST_SPARE_LSB 1
#define GP_AJBCONF HW_REGISTER_RW( 0x7e2000c0 )
#define GP_AJBCONF_MASK 0x80ffffff
#define GP_AJBCONF_WIDTH 32
#define GP_AJBCONF_RESET 0000000000
#define GP_AJBTMS HW_REGISTER_RW( 0x7e2000c4 )
#define GP_AJBTMS_MASK 0xffffffff
#define GP_AJBTMS_WIDTH 32
#define GP_AJBTMS_RESET 0000000000
#define GP_AJBTDI HW_REGISTER_RW( 0x7e2000c8 )
#define GP_AJBTDI_MASK 0xffffffff
#define GP_AJBTDI_WIDTH 32
#define GP_AJBTDI_RESET 0000000000
#define GP_AJBTDO HW_REGISTER_RW( 0x7e2000cc )
#define GP_AJBTDO_MASK 0xffffffff
#define GP_AJBTDO_WIDTH 32
#define GP_AJBTDO_RESET 0000000000

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bcm2708_chip/h264.h Executable file
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// This file was generated by the create_regs script
#define H264_BASE 0x7f000000
#define H264_APB_ID 0x68323634
#define H264_RC HW_REGISTER_RW( 0x7f000000 )
#define H264_RC_MASK 0xffffffff
#define H264_RC_WIDTH 32

142
bcm2708_chip/hardware.h Executable file
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// macro definitions plus aliases to maintain some old reg names
// Commented out to reveal fake defines
//#include "register_map_macros.h"
// Necessary macros to make C code understand registers
#if defined(_ATHENA_)
#define HW_REGISTER_RW(addr) ((addr))
#else
#define HW_REGISTER_RW(addr) (*(volatile unsigned long *)(addr))
#endif
#define HW_REGISTER_RO(addr) (*(const volatile unsigned long *)(addr))
#define HW_POINTER_TO_ADDRESS(pointer) ((uint32_t)(void *)&(pointer))
//interrupt definitions
#define INTERRUPT_HW_NUM (64)
#define INTERRUPT_HW_OFFSET (64)
#define INTERRUPT_SW_OFFSET (32)
#define INTERRUPT_SW_NUM (32)
#define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 )
#define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 )
#define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 )
#define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 )
#define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 )
#define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 )
#define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 )
#define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 )
#define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 )
#define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 )
#define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 )
#define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 )
#define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 )
#define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 )
#define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 )
#define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 )
#define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 )
#define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 )
#define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 )
#define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 )
#define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 )
#define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 )
#define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 )
#define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 )
#define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 )
#define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 )
#define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 )
#define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 )
#define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 )
#define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 )
#define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 )
#define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 )
#define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 )
#define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 )
#define INTERRUPT_CCP2TX (INTERRUPT_HW_OFFSET + 34 )
#define INTERRUPT_SDC (INTERRUPT_HW_OFFSET + 35 )
#define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 )
#define INTERRUPT_SPARE2 (INTERRUPT_HW_OFFSET + 37 )
#define INTERRUPT_CAM0 (INTERRUPT_HW_OFFSET + 38 )
#define INTERRUPT_CAM1 (INTERRUPT_HW_OFFSET + 39 )
#define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 )
#define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 )
#define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 )
#define INTERRUPT_SPARE3 (INTERRUPT_HW_OFFSET + 43 )
#define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 44 )
#define INTERRUPT_PWA0 (INTERRUPT_HW_OFFSET + 45 )
#define INTERRUPT_PWA1 (INTERRUPT_HW_OFFSET + 46 )
#define INTERRUPT_CPR (INTERRUPT_HW_OFFSET + 47 )
#define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 48 )
#define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 49 )
#define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 50 )
#define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 51 )
#define INTERRUPT_GPIO3 (INTERRUPT_HW_OFFSET + 52 )
#define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 )
#define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 )
#define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 )
#define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 )
#define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 )
#define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 58 )
#define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 )
#define INTERRUPT_CPG (INTERRUPT_HW_OFFSET + 60 )
#define INTERRUPT_RNG (INTERRUPT_HW_OFFSET + 61 )
#define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 )
#define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 )
#define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 )
#define ISRC0_0 IC0_SRC0
#define ISRC0_1 IC1_SRC0
#define ISRC1_0 IC0_SRC1
#define ISRC1_1 IC1_SRC1
/*---------------------------------------------------------------------------*/
// auto generated regestermap
#include "register_map.h"
/*---------------------------------------------------------------------------*/
/* DMA Source Definitions */
// port 0 is wired as permanently on inside the DMA
#define CAM_DMA (0<<DMA0_TI_PERMAP_LSB)
#define DISP_DMA (0<<DMA0_TI_PERMAP_LSB)
#define MS_DMA (0<<DMA0_TI_PERMAP_LSB)
#define BIT_STREAM_DMA (0<<DMA0_TI_PERMAP_LSB)
#define ACIS_DMA (0<<DMA0_TI_PERMAP_LSB)
#define SDRAM_CTRL_DMA (0<<DMA0_TI_PERMAP_LSB)
#define DSI_DMA ( 1<<DMA0_TI_PERMAP_LSB)
#define PCM_TX_DMA ( 2<<DMA0_TI_PERMAP_LSB)
#define PCM_RX_DMA ( 3<<DMA0_TI_PERMAP_LSB)
#define SMI_DMA ( 4<<DMA0_TI_PERMAP_LSB)
#define PWM_DMA ( 5<<DMA0_TI_PERMAP_LSB)
#define SPI_TX_DMA ( 6<<DMA0_TI_PERMAP_LSB)
#define SPI_RX_DMA ( 7<<DMA0_TI_PERMAP_LSB)
#define SLIM_DTX_DMA ( 8<<DMA0_TI_PERMAP_LSB)
#define SLIM_DRX_DMA ( 9<<DMA0_TI_PERMAP_LSB)
#define SLIM_CTX_DMA (10<<DMA0_TI_PERMAP_LSB)
#define SLIM_CRX_DMA (11<<DMA0_TI_PERMAP_LSB)
#define UNUSED_DMA_12 (12<<DMA0_TI_PERMAP_LSB)
#define SD_HOST_DMA (13<<DMA0_TI_PERMAP_LSB)
#define UNUSED_DMA_14 (14<<DMA0_TI_PERMAP_LSB)
#define DSI1_DMA (15<<DMA0_TI_PERMAP_LSB)
#define UNUSED_DMA_16 (16<<DMA0_TI_PERMAP_LSB)
#define HDMI_DMA (17<<DMA0_TI_PERMAP_LSB)
#define UNUSED_DMA_18 (18<<DMA0_TI_PERMAP_LSB)
#define CRYPTO_IP_DMA (19<<DMA0_TI_PERMAP_LSB)
#define CRYPTO_OP_DMA (20<<DMA0_TI_PERMAP_LSB)
#define SCALER_0_DMA (21<<DMA0_TI_PERMAP_LSB)
#define SCALER_1_DMA (22<<DMA0_TI_PERMAP_LSB)
#define SCALER_2_DMA (23<<DMA0_TI_PERMAP_LSB)
#define SMI_SCALER_0_DMA (24<<DMA0_TI_PERMAP_LSB)
#define SMI_SCALER_1_DMA (25<<DMA0_TI_PERMAP_LSB)
#define SMI_SCALER_2_DMA (26<<DMA0_TI_PERMAP_LSB)
// 27-32 unused
#define DMA_TI_S_128 (1<<9)
#define DMA_TI_S_INC (1<<8)
#define DMA_TI_D_32 0
#define DMA_TI_D_DREQ (1<<6)
#define DMA_TI_PER_MAP(n) (((n) & 0x1f) <<16)

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bcm2708_chip/hdcp.h Executable file
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// This file was generated by the create_regs script
#define HDCP_BASE 0x7e809000
#define HDCP_APB_ID 0x48444350
#define HDCP_KEY_CTL HW_REGISTER_RW( 0x7e809000 )
#define HDCP_KEY_CTL_MASK 0x00000007
#define HDCP_KEY_CTL_WIDTH 3
#define HDCP_KEY_CTL_RESET 0000000000
#define HDCP_KEY_CTL_START_BITS 0:0
#define HDCP_KEY_CTL_START_SET 0x00000001
#define HDCP_KEY_CTL_START_CLR 0xfffffffe
#define HDCP_KEY_CTL_START_MSB 0
#define HDCP_KEY_CTL_START_LSB 0
#define HDCP_KEY_CTL_START_RESET 0x0
#define HDCP_KEY_CTL_DONE_BITS 1:1
#define HDCP_KEY_CTL_DONE_SET 0x00000002
#define HDCP_KEY_CTL_DONE_CLR 0xfffffffd
#define HDCP_KEY_CTL_DONE_MSB 1
#define HDCP_KEY_CTL_DONE_LSB 1
#define HDCP_KEY_CTL_DONE_RESET 0x0
#define HDCP_KEY_CTL_DISHDCP_BITS 2:2
#define HDCP_KEY_CTL_DISHDCP_SET 0x00000004
#define HDCP_KEY_CTL_DISHDCP_CLR 0xfffffffb
#define HDCP_KEY_CTL_DISHDCP_MSB 2
#define HDCP_KEY_CTL_DISHDCP_LSB 2
#define HDCP_KEY_CTL_DISHDCP_RESET 0x0
#define HDCP_KEY_ADR HW_REGISTER_RW( 0x7e809004 )
#define HDCP_KEY_ADR_MASK 0x000000ff
#define HDCP_KEY_ADR_WIDTH 8
#define HDCP_KEY_ADR_RESET 0000000000
#define HDCP_KEY_KY0 HW_REGISTER_RW( 0x7e809008 )
#define HDCP_KEY_KY0_MASK 0xffffffff
#define HDCP_KEY_KY0_WIDTH 32
#define HDCP_KEY_KY0_RESET 0000000000
#define HDCP_KEY_KY1 HW_REGISTER_RW( 0x7e80900c )
#define HDCP_KEY_KY1_MASK 0x00ffffff
#define HDCP_KEY_KY1_WIDTH 24
#define HDCP_KEY_KY1_RESET 0000000000

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bcm2708_chip/hdmi.h Executable file
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// This file was generated by the create_regs script
#define HD_BASE 0x7e808000
#define HD_APB_ID 0x48444d49
#define HD_HDM_CTL HW_REGISTER_RW( 0x7e80800c )
#define HD_HDM_CTL_MASK 0x000003f7
#define HD_HDM_CTL_WIDTH 10
#define HD_HDM_CTL_RESET 0x000000f0
#define HD_HDM_CTL_ENABLE_BITS 0:0
#define HD_HDM_CTL_ENABLE_SET 0x00000001
#define HD_HDM_CTL_ENABLE_CLR 0xfffffffe
#define HD_HDM_CTL_ENABLE_MSB 0
#define HD_HDM_CTL_ENABLE_LSB 0
#define HD_HDM_CTL_ENABLE_RESET 0x0
#define HD_HDM_CTL_ENDIAN_BITS 1:1
#define HD_HDM_CTL_ENDIAN_SET 0x00000002
#define HD_HDM_CTL_ENDIAN_CLR 0xfffffffd
#define HD_HDM_CTL_ENDIAN_MSB 1
#define HD_HDM_CTL_ENDIAN_LSB 1
#define HD_HDM_CTL_ENDIAN_RESET 0x0
#define HD_HDM_CTL_SW_RST_BITS 2:2
#define HD_HDM_CTL_SW_RST_SET 0x00000004
#define HD_HDM_CTL_SW_RST_CLR 0xfffffffb
#define HD_HDM_CTL_SW_RST_MSB 2
#define HD_HDM_CTL_SW_RST_LSB 2
#define HD_HDM_CTL_SW_RST_RESET 0x0
#define HD_HDM_CTL_PDSTBY_BITS 5:4
#define HD_HDM_CTL_PDSTBY_SET 0x00000030
#define HD_HDM_CTL_PDSTBY_CLR 0xffffffcf
#define HD_HDM_CTL_PDSTBY_MSB 5
#define HD_HDM_CTL_PDSTBY_LSB 4
#define HD_HDM_CTL_PDSTBY_RESET 0x3
#define HD_HDM_CTL_RFSTBY_BITS 7:6
#define HD_HDM_CTL_RFSTBY_SET 0x000000c0
#define HD_HDM_CTL_RFSTBY_CLR 0xffffff3f
#define HD_HDM_CTL_RFSTBY_MSB 7
#define HD_HDM_CTL_RFSTBY_LSB 6
#define HD_HDM_CTL_RFSTBY_RESET 0x3
#define HD_HDM_CTL_CECOVR_BITS 8:8
#define HD_HDM_CTL_CECOVR_SET 0x00000100
#define HD_HDM_CTL_CECOVR_CLR 0xfffffeff
#define HD_HDM_CTL_CECOVR_MSB 8
#define HD_HDM_CTL_CECOVR_LSB 8
#define HD_HDM_CTL_CECOVR_RESET 0x0
#define HD_HDM_CTL_CECRXD_BITS 9:9
#define HD_HDM_CTL_CECRXD_SET 0x00000200
#define HD_HDM_CTL_CECRXD_CLR 0xfffffdff
#define HD_HDM_CTL_CECRXD_MSB 9
#define HD_HDM_CTL_CECRXD_LSB 9
#define HD_HDM_CTL_CECRXD_RESET 0x0
#define HD_MAI_CTL HW_REGISTER_RW( 0x7e808014 )
#define HD_MAI_CTL_MASK 0x0000ffff
#define HD_MAI_CTL_WIDTH 16
#define HD_MAI_CTL_RESET 0x00000020
#define HD_MAI_CTL_RST_MAI_BITS 0:0
#define HD_MAI_CTL_RST_MAI_SET 0x00000001
#define HD_MAI_CTL_RST_MAI_CLR 0xfffffffe
#define HD_MAI_CTL_RST_MAI_MSB 0
#define HD_MAI_CTL_RST_MAI_LSB 0
#define HD_MAI_CTL_RST_MAI_RESET 0x0
#define HD_MAI_CTL_ERRORF_BITS 1:1
#define HD_MAI_CTL_ERRORF_SET 0x00000002
#define HD_MAI_CTL_ERRORF_CLR 0xfffffffd
#define HD_MAI_CTL_ERRORF_MSB 1
#define HD_MAI_CTL_ERRORF_LSB 1
#define HD_MAI_CTL_ERRORF_RESET 0x0
#define HD_MAI_CTL_ERRORE_BITS 2:2
#define HD_MAI_CTL_ERRORE_SET 0x00000004
#define HD_MAI_CTL_ERRORE_CLR 0xfffffffb
#define HD_MAI_CTL_ERRORE_MSB 2
#define HD_MAI_CTL_ERRORE_LSB 2
#define HD_MAI_CTL_ERRORE_RESET 0x0
#define HD_MAI_CTL_ENABLE_BITS 3:3
#define HD_MAI_CTL_ENABLE_SET 0x00000008
#define HD_MAI_CTL_ENABLE_CLR 0xfffffff7
#define HD_MAI_CTL_ENABLE_MSB 3
#define HD_MAI_CTL_ENABLE_LSB 3
#define HD_MAI_CTL_ENABLE_RESET 0x0
#define HD_MAI_CTL_CHNUM_BITS 7:4
#define HD_MAI_CTL_CHNUM_SET 0x000000f0
#define HD_MAI_CTL_CHNUM_CLR 0xffffff0f
#define HD_MAI_CTL_CHNUM_MSB 7
#define HD_MAI_CTL_CHNUM_LSB 4
#define HD_MAI_CTL_CHNUM_RESET 0x2
#define HD_MAI_CTL_PAREN_BITS 8:8
#define HD_MAI_CTL_PAREN_SET 0x00000100
#define HD_MAI_CTL_PAREN_CLR 0xfffffeff
#define HD_MAI_CTL_PAREN_MSB 8
#define HD_MAI_CTL_PAREN_LSB 8
#define HD_MAI_CTL_PAREN_RESET 0x0
#define HD_MAI_CTL_FLUSH_BITS 9:9
#define HD_MAI_CTL_FLUSH_SET 0x00000200
#define HD_MAI_CTL_FLUSH_CLR 0xfffffdff
#define HD_MAI_CTL_FLUSH_MSB 9
#define HD_MAI_CTL_FLUSH_LSB 9
#define HD_MAI_CTL_FLUSH_RESET 0x0
#define HD_MAI_CTL_EMPTY_BITS 10:10
#define HD_MAI_CTL_EMPTY_SET 0x00000400
#define HD_MAI_CTL_EMPTY_CLR 0xfffffbff
#define HD_MAI_CTL_EMPTY_MSB 10
#define HD_MAI_CTL_EMPTY_LSB 10
#define HD_MAI_CTL_EMPTY_RESET 0x0
#define HD_MAI_CTL_FULL_BITS 11:11
#define HD_MAI_CTL_FULL_SET 0x00000800
#define HD_MAI_CTL_FULL_CLR 0xfffff7ff
#define HD_MAI_CTL_FULL_MSB 11
#define HD_MAI_CTL_FULL_LSB 11
#define HD_MAI_CTL_FULL_RESET 0x0
#define HD_MAI_CTL_WHOLSMP_BITS 12:12
#define HD_MAI_CTL_WHOLSMP_SET 0x00001000
#define HD_MAI_CTL_WHOLSMP_CLR 0xffffefff
#define HD_MAI_CTL_WHOLSMP_MSB 12
#define HD_MAI_CTL_WHOLSMP_LSB 12
#define HD_MAI_CTL_WHOLSMP_RESET 0x0
#define HD_MAI_CTL_CHALIGN_BITS 13:13
#define HD_MAI_CTL_CHALIGN_SET 0x00002000
#define HD_MAI_CTL_CHALIGN_CLR 0xffffdfff
#define HD_MAI_CTL_CHALIGN_MSB 13
#define HD_MAI_CTL_CHALIGN_LSB 13
#define HD_MAI_CTL_CHALIGN_RESET 0x0
#define HD_MAI_CTL_BUSY_BITS 14:14
#define HD_MAI_CTL_BUSY_SET 0x00004000
#define HD_MAI_CTL_BUSY_CLR 0xffffbfff
#define HD_MAI_CTL_BUSY_MSB 14
#define HD_MAI_CTL_BUSY_LSB 14
#define HD_MAI_CTL_BUSY_RESET 0x0
#define HD_MAI_CTL_DLATE_BITS 15:15
#define HD_MAI_CTL_DLATE_SET 0x00008000
#define HD_MAI_CTL_DLATE_CLR 0xffff7fff
#define HD_MAI_CTL_DLATE_MSB 15
#define HD_MAI_CTL_DLATE_LSB 15
#define HD_MAI_CTL_DLATE_RESET 0x0
#define HD_MAI_THR HW_REGISTER_RW( 0x7e808018 )
#define HD_MAI_THR_MASK 0xffffffff
#define HD_MAI_THR_WIDTH 32
#define HD_MAI_THR_RESET 0x01010101
#define HD_MAI_THR_DREQLOW_BITS 5:0
#define HD_MAI_THR_DREQLOW_SET 0x0000003f
#define HD_MAI_THR_DREQLOW_CLR 0xffffffc0
#define HD_MAI_THR_DREQLOW_MSB 5
#define HD_MAI_THR_DREQLOW_LSB 0
#define HD_MAI_THR_DREQLOW_RESET 0x1
#define HD_MAI_THR_DREQHIGH_BITS 13:8
#define HD_MAI_THR_DREQHIGH_SET 0x00003f00
#define HD_MAI_THR_DREQHIGH_CLR 0xffffc0ff
#define HD_MAI_THR_DREQHIGH_MSB 13
#define HD_MAI_THR_DREQHIGH_LSB 8
#define HD_MAI_THR_DREQHIGH_RESET 0x1
#define HD_MAI_THR_PANICLOW_BITS 21:16
#define HD_MAI_THR_PANICLOW_SET 0x003f0000
#define HD_MAI_THR_PANICLOW_CLR 0xffc0ffff
#define HD_MAI_THR_PANICLOW_MSB 21
#define HD_MAI_THR_PANICLOW_LSB 16
#define HD_MAI_THR_PANICLOW_RESET 0x1
#define HD_MAI_THR_PANICHIGH_BITS 29:24
#define HD_MAI_THR_PANICHIGH_SET 0x3f000000
#define HD_MAI_THR_PANICHIGH_CLR 0xc0ffffff
#define HD_MAI_THR_PANICHIGH_MSB 29
#define HD_MAI_THR_PANICHIGH_LSB 24
#define HD_MAI_THR_PANICHIGH_RESET 0x1
#define HD_MAI_FMT HW_REGISTER_RW( 0x7e80801c )
#define HD_MAI_FMT_MASK 0xffffffff
#define HD_MAI_FMT_WIDTH 32
#define HD_MAI_FMT_RESET 0000000000
#define HD_MAI_DAT HW_REGISTER_RW( 0x7e808020 )
#define HD_MAI_DAT_MASK 0xffffffff
#define HD_MAI_DAT_WIDTH 32
#define HD_MAI_DAT_RESET 0000000000
#define HD_SPARE HW_REGISTER_RW( 0x7e808024 )
#define HD_SPARE_MASK 0xffffffff
#define HD_SPARE_WIDTH 32
#define HD_SPARE_RESET 0000000000
#define HD_MAI_SMP HW_REGISTER_RW( 0x7e80802c )
#define HD_MAI_SMP_MASK 0xffffffff
#define HD_MAI_SMP_WIDTH 32
#define HD_MAI_SMP_RESET 0000000000
#define HD_VID_CTL HW_REGISTER_RW( 0x7e808038 )
#define HD_VID_CTL_MASK 0xfffc0000
#define HD_VID_CTL_WIDTH 32
#define HD_VID_CTL_RESET 0x00040000
#define HD_VID_CTL_BLANKPIX_BITS 18:18
#define HD_VID_CTL_BLANKPIX_SET 0x00040000
#define HD_VID_CTL_BLANKPIX_CLR 0xfffbffff
#define HD_VID_CTL_BLANKPIX_MSB 18
#define HD_VID_CTL_BLANKPIX_LSB 18
#define HD_VID_CTL_BLANKPIX_RESET 0x1
#define HD_VID_CTL_EMPRGB_BITS 19:19
#define HD_VID_CTL_EMPRGB_SET 0x00080000
#define HD_VID_CTL_EMPRGB_CLR 0xfff7ffff
#define HD_VID_CTL_EMPRGB_MSB 19
#define HD_VID_CTL_EMPRGB_LSB 19
#define HD_VID_CTL_EMPRGB_RESET 0x0
#define HD_VID_CTL_EMPSYNC_BITS 20:20
#define HD_VID_CTL_EMPSYNC_SET 0x00100000
#define HD_VID_CTL_EMPSYNC_CLR 0xffefffff
#define HD_VID_CTL_EMPSYNC_MSB 20
#define HD_VID_CTL_EMPSYNC_LSB 20
#define HD_VID_CTL_EMPSYNC_RESET 0x0
#define HD_VID_CTL_FULRGB_BITS 21:21
#define HD_VID_CTL_FULRGB_SET 0x00200000
#define HD_VID_CTL_FULRGB_CLR 0xffdfffff
#define HD_VID_CTL_FULRGB_MSB 21
#define HD_VID_CTL_FULRGB_LSB 21
#define HD_VID_CTL_FULRGB_RESET 0x0
#define HD_VID_CTL_FULSYNC_BITS 22:22
#define HD_VID_CTL_FULSYNC_SET 0x00400000
#define HD_VID_CTL_FULSYNC_CLR 0xffbfffff
#define HD_VID_CTL_FULSYNC_MSB 22
#define HD_VID_CTL_FULSYNC_LSB 22
#define HD_VID_CTL_FULSYNC_RESET 0x0
#define HD_VID_CTL_CLRRGB_BITS 23:23
#define HD_VID_CTL_CLRRGB_SET 0x00800000
#define HD_VID_CTL_CLRRGB_CLR 0xff7fffff
#define HD_VID_CTL_CLRRGB_MSB 23
#define HD_VID_CTL_CLRRGB_LSB 23
#define HD_VID_CTL_CLRRGB_RESET 0x0
#define HD_VID_CTL_CLRSYNC_BITS 24:24
#define HD_VID_CTL_CLRSYNC_SET 0x01000000
#define HD_VID_CTL_CLRSYNC_CLR 0xfeffffff
#define HD_VID_CTL_CLRSYNC_MSB 24
#define HD_VID_CTL_CLRSYNC_LSB 24
#define HD_VID_CTL_CLRSYNC_RESET 0x0
#define HD_VID_CTL_ERROR_BITS 26:25
#define HD_VID_CTL_ERROR_SET 0x06000000
#define HD_VID_CTL_ERROR_CLR 0xf9ffffff
#define HD_VID_CTL_ERROR_MSB 26
#define HD_VID_CTL_ERROR_LSB 25
#define HD_VID_CTL_ERROR_RESET 0x0
#define HD_VID_CTL_HPOL_BITS 27:27
#define HD_VID_CTL_HPOL_SET 0x08000000
#define HD_VID_CTL_HPOL_CLR 0xf7ffffff
#define HD_VID_CTL_HPOL_MSB 27
#define HD_VID_CTL_HPOL_LSB 27
#define HD_VID_CTL_HPOL_RESET 0x0
#define HD_VID_CTL_VPOL_BITS 28:28
#define HD_VID_CTL_VPOL_SET 0x10000000
#define HD_VID_CTL_VPOL_CLR 0xefffffff
#define HD_VID_CTL_VPOL_MSB 28
#define HD_VID_CTL_VPOL_LSB 28
#define HD_VID_CTL_VPOL_RESET 0x0
#define HD_VID_CTL_RST_FRAMEC_BITS 29:29
#define HD_VID_CTL_RST_FRAMEC_SET 0x20000000
#define HD_VID_CTL_RST_FRAMEC_CLR 0xdfffffff
#define HD_VID_CTL_RST_FRAMEC_MSB 29
#define HD_VID_CTL_RST_FRAMEC_LSB 29
#define HD_VID_CTL_RST_FRAMEC_RESET 0x0
#define HD_VID_CTL_UFEN_BITS 30:30
#define HD_VID_CTL_UFEN_SET 0x40000000
#define HD_VID_CTL_UFEN_CLR 0xbfffffff
#define HD_VID_CTL_UFEN_MSB 30
#define HD_VID_CTL_UFEN_LSB 30
#define HD_VID_CTL_UFEN_RESET 0x0
#define HD_VID_CTL_ENABLE_BITS 31:31
#define HD_VID_CTL_ENABLE_SET 0x80000000
#define HD_VID_CTL_ENABLE_CLR 0x7fffffff
#define HD_VID_CTL_ENABLE_MSB 31
#define HD_VID_CTL_ENABLE_LSB 31
#define HD_VID_CTL_ENABLE_RESET 0x0
#define HD_CSC_CTL HW_REGISTER_RW( 0x7e808040 )
#define HD_CSC_CTL_MASK 0x000000ff
#define HD_CSC_CTL_WIDTH 8
#define HD_CSC_CTL_RESET 0000000000
#define HD_CSC_CTL_ENABLE_BITS 0:0
#define HD_CSC_CTL_ENABLE_SET 0x00000001
#define HD_CSC_CTL_ENABLE_CLR 0xfffffffe
#define HD_CSC_CTL_ENABLE_MSB 0
#define HD_CSC_CTL_ENABLE_LSB 0
#define HD_CSC_CTL_ENABLE_RESET 0x0
#define HD_CSC_CTL_USERGB2YCC_BITS 1:1
#define HD_CSC_CTL_USERGB2YCC_SET 0x00000002
#define HD_CSC_CTL_USERGB2YCC_CLR 0xfffffffd
#define HD_CSC_CTL_USERGB2YCC_MSB 1
#define HD_CSC_CTL_USERGB2YCC_LSB 1
#define HD_CSC_CTL_USERGB2YCC_RESET 0x0
#define HD_CSC_CTL_MODE_BITS 3:2
#define HD_CSC_CTL_MODE_SET 0x0000000c
#define HD_CSC_CTL_MODE_CLR 0xfffffff3
#define HD_CSC_CTL_MODE_MSB 3
#define HD_CSC_CTL_MODE_LSB 2
#define HD_CSC_CTL_MODE_RESET 0x0
#define HD_CSC_CTL_PADMSB_BITS 4:4
#define HD_CSC_CTL_PADMSB_SET 0x00000010
#define HD_CSC_CTL_PADMSB_CLR 0xffffffef
#define HD_CSC_CTL_PADMSB_MSB 4
#define HD_CSC_CTL_PADMSB_LSB 4
#define HD_CSC_CTL_PADMSB_RESET 0x0
#define HD_CSC_CTL_COLORD_BITS 7:5
#define HD_CSC_CTL_COLORD_SET 0x000000e0
#define HD_CSC_CTL_COLORD_CLR 0xffffff1f
#define HD_CSC_CTL_COLORD_MSB 7
#define HD_CSC_CTL_COLORD_LSB 5
#define HD_CSC_CTL_COLORD_RESET 0x0
#define HD_CSC_12_11 HW_REGISTER_RW( 0x7e808044 )
#define HD_CSC_12_11_MASK 0xffffffff
#define HD_CSC_12_11_WIDTH 32
#define HD_CSC_12_11_RESET 0000000000
#define HD_CSC_14_13 HW_REGISTER_RW( 0x7e808048 )
#define HD_CSC_14_13_MASK 0xffffffff
#define HD_CSC_14_13_WIDTH 32
#define HD_CSC_14_13_RESET 0000000000
#define HD_CSC_22_21 HW_REGISTER_RW( 0x7e80804c )
#define HD_CSC_22_21_MASK 0xffffffff
#define HD_CSC_22_21_WIDTH 32
#define HD_CSC_22_21_RESET 0000000000
#define HD_CSC_24_23 HW_REGISTER_RW( 0x7e808050 )
#define HD_CSC_24_23_MASK 0xffffffff
#define HD_CSC_24_23_WIDTH 32
#define HD_CSC_24_23_RESET 0000000000
#define HD_CSC_32_31 HW_REGISTER_RW( 0x7e808054 )
#define HD_CSC_32_31_MASK 0xffffffff
#define HD_CSC_32_31_WIDTH 32
#define HD_CSC_32_31_RESET 0000000000
#define HD_CSC_34_33 HW_REGISTER_RW( 0x7e808058 )
#define HD_CSC_34_33_MASK 0xffffffff
#define HD_CSC_34_33_WIDTH 32
#define HD_CSC_34_33_RESET 0000000000
#define HD_FRAME_CNT HW_REGISTER_RW( 0x7e808068 )
#define HD_FRAME_CNT_MASK 0xffffffff
#define HD_FRAME_CNT_WIDTH 32
#define HD_FRAME_CNT_RESET 0000000000

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bcm2708_chip/hdmicore.h Executable file
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bcm2708_chip/hvs.h Executable file
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// This file was generated by the create_regs script
#define SCALER_BASE 0x7e400000
#define SCALER_APB_ID 0x64647276
#define SCALER_DISPCTRL HW_REGISTER_RW( 0x7e400000 )
#define SCALER_DISPCTRL_MASK 0xffffffff
#define SCALER_DISPCTRL_WIDTH 32
#define SCALER_DISPCTRL_HVS_EN_BITS 31:31
#define SCALER_DISPCTRL_HVS_EN_SET 0x80000000
#define SCALER_DISPCTRL_HVS_EN_CLR 0x7fffffff
#define SCALER_DISPCTRL_HVS_EN_MSB 31
#define SCALER_DISPCTRL_HVS_EN_LSB 31
#define SCALER_DISPCTRL_VSCL_DIS_BITS 31:30
#define SCALER_DISPCTRL_VSCL_DIS_SET 0xc0000000
#define SCALER_DISPCTRL_VSCL_DIS_CLR 0x3fffffff
#define SCALER_DISPCTRL_VSCL_DIS_MSB 31
#define SCALER_DISPCTRL_VSCL_DIS_LSB 30
#define SCALER_DISPCTRL_DSP2_PANIC_BITS 29:28
#define SCALER_DISPCTRL_DSP2_PANIC_SET 0x30000000
#define SCALER_DISPCTRL_DSP2_PANIC_CLR 0xcfffffff
#define SCALER_DISPCTRL_DSP2_PANIC_MSB 29
#define SCALER_DISPCTRL_DSP2_PANIC_LSB 28
#define SCALER_DISPCTRL_DSP1_PANIC_BITS 27:26
#define SCALER_DISPCTRL_DSP1_PANIC_SET 0x0c000000
#define SCALER_DISPCTRL_DSP1_PANIC_CLR 0xf3ffffff
#define SCALER_DISPCTRL_DSP1_PANIC_MSB 27
#define SCALER_DISPCTRL_DSP1_PANIC_LSB 26
#define SCALER_DISPCTRL_DSP0_PANIC_BITS 25:24
#define SCALER_DISPCTRL_DSP0_PANIC_SET 0x03000000
#define SCALER_DISPCTRL_DSP0_PANIC_CLR 0xfcffffff
#define SCALER_DISPCTRL_DSP0_PANIC_MSB 25
#define SCALER_DISPCTRL_DSP0_PANIC_LSB 24
#define SCALER_DISPCTRL_DSP3_MUX_BITS 19:18
#define SCALER_DISPCTRL_DSP3_MUX_SET 0x000c0000
#define SCALER_DISPCTRL_DSP3_MUX_CLR 0xfff3ffff
#define SCALER_DISPCTRL_DSP3_MUX_MSB 19
#define SCALER_DISPCTRL_DSP3_MUX_LSB 18
#define SCALER_DISPCTRL_TILE_WID_BITS 17:16
#define SCALER_DISPCTRL_TILE_WID_SET 0x00030000
#define SCALER_DISPCTRL_TILE_WID_CLR 0xfffcffff
#define SCALER_DISPCTRL_TILE_WID_MSB 17
#define SCALER_DISPCTRL_TILE_WID_LSB 16
#define SCALER_DISPCTRL_DSP2_IRQ_CTRL_BITS 12:11
#define SCALER_DISPCTRL_DSP2_IRQ_CTRL_SET 0x00001800
#define SCALER_DISPCTRL_DSP2_IRQ_CTRL_CLR 0xffffe7ff
#define SCALER_DISPCTRL_DSP2_IRQ_CTRL_MSB 12
#define SCALER_DISPCTRL_DSP2_IRQ_CTRL_LSB 11
#define SCALER_DISPCTRL_DSP1_IRQ_CTRL_BITS 10:9
#define SCALER_DISPCTRL_DSP1_IRQ_CTRL_SET 0x00000600
#define SCALER_DISPCTRL_DSP1_IRQ_CTRL_CLR 0xfffff9ff
#define SCALER_DISPCTRL_DSP1_IRQ_CTRL_MSB 10
#define SCALER_DISPCTRL_DSP1_IRQ_CTRL_LSB 9
#define SCALER_DISPCTRL_IRQ_EN_BITS 6:0
#define SCALER_DISPCTRL_IRQ_EN_SET 0x0000007f
#define SCALER_DISPCTRL_IRQ_EN_CLR 0xffffff80
#define SCALER_DISPCTRL_IRQ_EN_MSB 6
#define SCALER_DISPCTRL_IRQ_EN_LSB 0
#define SCALER_DISPSTAT HW_REGISTER_RW( 0x7e400004 )
#define SCALER_DISPSTAT_MASK 0xffffffff
#define SCALER_DISPSTAT_WIDTH 32
#define SCALER_DISPSTAT_PROF_IRQ_BITS 31:0
#define SCALER_DISPSTAT_PROF_IRQ_SET 0xffffffff
#define SCALER_DISPSTAT_PROF_IRQ_CLR 0x00000000
#define SCALER_DISPSTAT_PROF_IRQ_MSB 31
#define SCALER_DISPSTAT_PROF_IRQ_LSB 0
#define SCALER_DISPSTAT_DSP0_IRQ_BITS 31:1
#define SCALER_DISPSTAT_DSP0_IRQ_SET 0xfffffffe
#define SCALER_DISPSTAT_DSP0_IRQ_CLR 0x00000001
#define SCALER_DISPSTAT_DSP0_IRQ_MSB 31
#define SCALER_DISPSTAT_DSP0_IRQ_LSB 1
#define SCALER_DISPSTAT_DSP1_IRQ_BITS 31:2
#define SCALER_DISPSTAT_DSP1_IRQ_SET 0xfffffffc
#define SCALER_DISPSTAT_DSP1_IRQ_CLR 0x00000003
#define SCALER_DISPSTAT_DSP1_IRQ_MSB 31
#define SCALER_DISPSTAT_DSP1_IRQ_LSB 2
#define SCALER_DISPSTAT_DSP2_IRQ_BITS 31:3
#define SCALER_DISPSTAT_DSP2_IRQ_SET 0xfffffff8
#define SCALER_DISPSTAT_DSP2_IRQ_CLR 0x00000007
#define SCALER_DISPSTAT_DSP2_IRQ_MSB 31
#define SCALER_DISPSTAT_DSP2_IRQ_LSB 3
#define SCALER_DISPSTAT_DMA_IRQ_BITS 31:4
#define SCALER_DISPSTAT_DMA_IRQ_SET 0xfffffff0
#define SCALER_DISPSTAT_DMA_IRQ_CLR 0x0000000f
#define SCALER_DISPSTAT_DMA_IRQ_MSB 31
#define SCALER_DISPSTAT_DMA_IRQ_LSB 4
#define SCALER_DISPSTAT_WR_IRQ_BITS 31:5
#define SCALER_DISPSTAT_WR_IRQ_SET 0xffffffe0
#define SCALER_DISPSTAT_WR_IRQ_CLR 0x0000001f
#define SCALER_DISPSTAT_WR_IRQ_MSB 31
#define SCALER_DISPSTAT_WR_IRQ_LSB 5
#define SCALER_DISPSTAT_RD_IRQ_BITS 31:6
#define SCALER_DISPSTAT_RD_IRQ_SET 0xffffffc0
#define SCALER_DISPSTAT_RD_IRQ_CLR 0x0000003f
#define SCALER_DISPSTAT_RD_IRQ_MSB 31
#define SCALER_DISPSTAT_RD_IRQ_LSB 6
#define SCALER_DISPSTAT_DMA_ERR_BIT2_BITS 31:7
#define SCALER_DISPSTAT_DMA_ERR_BIT2_SET 0xffffff80
#define SCALER_DISPSTAT_DMA_ERR_BIT2_CLR 0x0000007f
#define SCALER_DISPSTAT_DMA_ERR_BIT2_MSB 31
#define SCALER_DISPSTAT_DMA_ERR_BIT2_LSB 7
#define SCALER_DISPSTAT_DSP0_STATUS_BITS 13:8
#define SCALER_DISPSTAT_DSP0_STATUS_SET 0x00003f00
#define SCALER_DISPSTAT_DSP0_STATUS_CLR 0xffffc0ff
#define SCALER_DISPSTAT_DSP0_STATUS_MSB 13
#define SCALER_DISPSTAT_DSP0_STATUS_LSB 8
#define SCALER_DISPSTAT_DMA_ERR_BIT0_BITS 31:14
#define SCALER_DISPSTAT_DMA_ERR_BIT0_SET 0xffffc000
#define SCALER_DISPSTAT_DMA_ERR_BIT0_CLR 0x00003fff
#define SCALER_DISPSTAT_DMA_ERR_BIT0_MSB 31
#define SCALER_DISPSTAT_DMA_ERR_BIT0_LSB 14
#define SCALER_DISPSTAT_DMA_ERR_BIT1_BITS 31:15
#define SCALER_DISPSTAT_DMA_ERR_BIT1_SET 0xffff8000
#define SCALER_DISPSTAT_DMA_ERR_BIT1_CLR 0x00007fff
#define SCALER_DISPSTAT_DMA_ERR_BIT1_MSB 31
#define SCALER_DISPSTAT_DMA_ERR_BIT1_LSB 15
#define SCALER_DISPSTAT_DSP1_STATUS_BITS 21:16
#define SCALER_DISPSTAT_DSP1_STATUS_SET 0x003f0000
#define SCALER_DISPSTAT_DSP1_STATUS_CLR 0xffc0ffff
#define SCALER_DISPSTAT_DSP1_STATUS_MSB 21
#define SCALER_DISPSTAT_DSP1_STATUS_LSB 16
#define SCALER_DISPSTAT_DSP2_STATUS_BITS 29:24
#define SCALER_DISPSTAT_DSP2_STATUS_SET 0x3f000000
#define SCALER_DISPSTAT_DSP2_STATUS_CLR 0xc0ffffff
#define SCALER_DISPSTAT_DSP2_STATUS_MSB 29
#define SCALER_DISPSTAT_DSP2_STATUS_LSB 24
#define SCALER_DISPID HW_REGISTER_RW( 0x7e400008 )
#define SCALER_DISPID_MASK 0xffffffff
#define SCALER_DISPID_WIDTH 32
#define SCALER_DISPID_RESET 0x64647276
#define SCALER_DISPECTRL HW_REGISTER_RW( 0x7e40000c )
#define SCALER_DISPECTRL_MASK 0xffffffff
#define SCALER_DISPECTRL_WIDTH 32
#define SCALER_DISPECTRL_PANIC_CTRL_BITS 6:0
#define SCALER_DISPECTRL_PANIC_CTRL_SET 0x0000007f
#define SCALER_DISPECTRL_PANIC_CTRL_CLR 0xffffff80
#define SCALER_DISPECTRL_PANIC_CTRL_MSB 6
#define SCALER_DISPECTRL_PANIC_CTRL_LSB 0
#define SCALER_DISPECTRL_BUSY_STATUS_BITS 31:8
#define SCALER_DISPECTRL_BUSY_STATUS_SET 0xffffff00
#define SCALER_DISPECTRL_BUSY_STATUS_CLR 0x000000ff
#define SCALER_DISPECTRL_BUSY_STATUS_MSB 31
#define SCALER_DISPECTRL_BUSY_STATUS_LSB 8
#define SCALER_DISPECTRL_Y_BUSY_BITS 31:9
#define SCALER_DISPECTRL_Y_BUSY_SET 0xfffffe00
#define SCALER_DISPECTRL_Y_BUSY_CLR 0x000001ff
#define SCALER_DISPECTRL_Y_BUSY_MSB 31
#define SCALER_DISPECTRL_Y_BUSY_LSB 9
#define SCALER_DISPECTRL_CB_BUSY_BITS 31:10
#define SCALER_DISPECTRL_CB_BUSY_SET 0xfffffc00
#define SCALER_DISPECTRL_CB_BUSY_CLR 0x000003ff
#define SCALER_DISPECTRL_CB_BUSY_MSB 31
#define SCALER_DISPECTRL_CB_BUSY_LSB 10
#define SCALER_DISPECTRL_CR_BUSY_BITS 31:11
#define SCALER_DISPECTRL_CR_BUSY_SET 0xfffff800
#define SCALER_DISPECTRL_CR_BUSY_CLR 0x000007ff
#define SCALER_DISPECTRL_CR_BUSY_MSB 31
#define SCALER_DISPECTRL_CR_BUSY_LSB 11
#define SCALER_DISPECTRL_POSTED_STATUS_BITS 14:12
#define SCALER_DISPECTRL_POSTED_STATUS_SET 0x00007000
#define SCALER_DISPECTRL_POSTED_STATUS_CLR 0xffff8fff
#define SCALER_DISPECTRL_POSTED_STATUS_MSB 14
#define SCALER_DISPECTRL_POSTED_STATUS_LSB 12
#define SCALER_DISPECTRL_POSTED_CTRL_BITS 21:16
#define SCALER_DISPECTRL_POSTED_CTRL_SET 0x003f0000
#define SCALER_DISPECTRL_POSTED_CTRL_CLR 0xffc0ffff
#define SCALER_DISPECTRL_POSTED_CTRL_MSB 21
#define SCALER_DISPECTRL_POSTED_CTRL_LSB 16
#define SCALER_DISPECTRL_GT8_BURST_BITS 31:24
#define SCALER_DISPECTRL_GT8_BURST_SET 0xff000000
#define SCALER_DISPECTRL_GT8_BURST_CLR 0x00ffffff
#define SCALER_DISPECTRL_GT8_BURST_MSB 31
#define SCALER_DISPECTRL_GT8_BURST_LSB 24
#define SCALER_DISPECTRL_TWOD_SINGLE_BITS 31:25
#define SCALER_DISPECTRL_TWOD_SINGLE_SET 0xfe000000
#define SCALER_DISPECTRL_TWOD_SINGLE_CLR 0x01ffffff
#define SCALER_DISPECTRL_TWOD_SINGLE_MSB 31
#define SCALER_DISPECTRL_TWOD_SINGLE_LSB 25
#define SCALER_DISPECTRL_PROF_TYPE_BITS 27:26
#define SCALER_DISPECTRL_PROF_TYPE_SET 0x0c000000
#define SCALER_DISPECTRL_PROF_TYPE_CLR 0xf3ffffff
#define SCALER_DISPECTRL_PROF_TYPE_MSB 27
#define SCALER_DISPECTRL_PROF_TYPE_LSB 26
#define SCALER_DISPECTRL_Y_NE_CTRL_BITS 31:28
#define SCALER_DISPECTRL_Y_NE_CTRL_SET 0xf0000000
#define SCALER_DISPECTRL_Y_NE_CTRL_CLR 0x0fffffff
#define SCALER_DISPECTRL_Y_NE_CTRL_MSB 31
#define SCALER_DISPECTRL_Y_NE_CTRL_LSB 28
#define SCALER_DISPECTRL_CB_NE_CTRL_BITS 31:29
#define SCALER_DISPECTRL_CB_NE_CTRL_SET 0xe0000000
#define SCALER_DISPECTRL_CB_NE_CTRL_CLR 0x1fffffff
#define SCALER_DISPECTRL_CB_NE_CTRL_MSB 31
#define SCALER_DISPECTRL_CB_NE_CTRL_LSB 29
#define SCALER_DISPECTRL_CR_NE_CTRL_BITS 31:30
#define SCALER_DISPECTRL_CR_NE_CTRL_SET 0xc0000000
#define SCALER_DISPECTRL_CR_NE_CTRL_CLR 0x3fffffff
#define SCALER_DISPECTRL_CR_NE_CTRL_MSB 31
#define SCALER_DISPECTRL_CR_NE_CTRL_LSB 30
#define SCALER_DISPECTRL_SECURE_MODE_BITS 31:31
#define SCALER_DISPECTRL_SECURE_MODE_SET 0x80000000
#define SCALER_DISPECTRL_SECURE_MODE_CLR 0x7fffffff
#define SCALER_DISPECTRL_SECURE_MODE_MSB 31
#define SCALER_DISPECTRL_SECURE_MODE_LSB 31
#define SCALER_DISPPROF HW_REGISTER_RW( 0x7e400010 )
#define SCALER_DISPPROF_MASK 0xffffffff
#define SCALER_DISPPROF_WIDTH 32
#define SCALER_DISPDITHER HW_REGISTER_RW( 0x7e400014 )
#define SCALER_DISPDITHER_MASK 0xffffffff
#define SCALER_DISPDITHER_WIDTH 32
#define SCALER_DISPEOLN HW_REGISTER_RW( 0x7e400018 )
#define SCALER_DISPEOLN_MASK 0xffffffff
#define SCALER_DISPEOLN_WIDTH 32
#define SCALER_DISPLIST0 HW_REGISTER_RW( 0x7e400020 )
#define SCALER_DISPLIST0_MASK 0xffffffff
#define SCALER_DISPLIST0_WIDTH 32
#define SCALER_DISPLIST1 HW_REGISTER_RW( 0x7e400024 )
#define SCALER_DISPLIST1_MASK 0xffffffff
#define SCALER_DISPLIST1_WIDTH 32
#define SCALER_DISPLIST2 HW_REGISTER_RW( 0x7e400028 )
#define SCALER_DISPLIST2_MASK 0xffffffff
#define SCALER_DISPLIST2_WIDTH 32
#define SCALER_DISPLSTAT HW_REGISTER_RW( 0x7e40002c )
#define SCALER_DISPLSTAT_MASK 0xffffffff
#define SCALER_DISPLSTAT_WIDTH 32
#define SCALER_DISPLACT0 HW_REGISTER_RW( 0x7e400030 )
#define SCALER_DISPLACT0_MASK 0xffffffff
#define SCALER_DISPLACT0_WIDTH 32
#define SCALER_DISPLACT1 HW_REGISTER_RW( 0x7e400034 )
#define SCALER_DISPLACT1_MASK 0xffffffff
#define SCALER_DISPLACT1_WIDTH 32
#define SCALER_DISPLACT2 HW_REGISTER_RW( 0x7e400038 )
#define SCALER_DISPLACT2_MASK 0xffffffff
#define SCALER_DISPLACT2_WIDTH 32
#define SCALER_DISPCTRL0 HW_REGISTER_RW( 0x7e400040 )
#define SCALER_DISPCTRL0_MASK 0xffffffff
#define SCALER_DISPCTRL0_WIDTH 32
#define SCALER_DISPBKGND0 HW_REGISTER_RW( 0x7e400044 )
#define SCALER_DISPBKGND0_MASK 0xffffffff
#define SCALER_DISPBKGND0_WIDTH 32
#define SCALER_DISPSTAT0 HW_REGISTER_RW( 0x7e400048 )
#define SCALER_DISPSTAT0_MASK 0xffffffff
#define SCALER_DISPSTAT0_WIDTH 32
#define SCALER_DISPBASE0 HW_REGISTER_RW( 0x7e40004c )
#define SCALER_DISPBASE0_MASK 0xffffffff
#define SCALER_DISPBASE0_WIDTH 32
#define SCALER_DISPCTRL1 HW_REGISTER_RW( 0x7e400050 )
#define SCALER_DISPCTRL1_MASK 0xffffffff
#define SCALER_DISPCTRL1_WIDTH 32
#define SCALER_DISPBKGND1 HW_REGISTER_RW( 0x7e400054 )
#define SCALER_DISPBKGND1_MASK 0xffffffff
#define SCALER_DISPBKGND1_WIDTH 32
#define SCALER_DISPSTAT1 HW_REGISTER_RW( 0x7e400058 )
#define SCALER_DISPSTAT1_MASK 0xffffffff
#define SCALER_DISPSTAT1_WIDTH 32
#define SCALER_DISPBASE1 HW_REGISTER_RW( 0x7e40005c )
#define SCALER_DISPBASE1_MASK 0xffffffff
#define SCALER_DISPBASE1_WIDTH 32
#define SCALER_DISPCTRL2 HW_REGISTER_RW( 0x7e400060 )
#define SCALER_DISPCTRL2_MASK 0xffffffff
#define SCALER_DISPCTRL2_WIDTH 32
#define SCALER_DISPBKGND2 HW_REGISTER_RW( 0x7e400064 )
#define SCALER_DISPBKGND2_MASK 0xffffffff
#define SCALER_DISPBKGND2_WIDTH 32
#define SCALER_DISPSTAT2 HW_REGISTER_RW( 0x7e400068 )
#define SCALER_DISPSTAT2_MASK 0xffffffff
#define SCALER_DISPSTAT2_WIDTH 32
#define SCALER_DISPBASE2 HW_REGISTER_RW( 0x7e40006c )
#define SCALER_DISPBASE2_MASK 0xffffffff
#define SCALER_DISPBASE2_WIDTH 32
#define SCALER_DISPALPHA2 HW_REGISTER_RW( 0x7e400070 )
#define SCALER_DISPALPHA2_MASK 0xffffffff
#define SCALER_DISPALPHA2_WIDTH 32
#define SCALER_DISPGAMADR HW_REGISTER_RW( 0x7e400078 )
#define SCALER_DISPGAMADR_MASK 0xffffffff
#define SCALER_DISPGAMADR_WIDTH 32
#define SCALER_OLEDOFFS HW_REGISTER_RW( 0x7e400080 )
#define SCALER_OLEDOFFS_MASK 0xffffffff
#define SCALER_OLEDOFFS_WIDTH 32
#define SCALER_OLEDCOEF0 HW_REGISTER_RW( 0x7e400084 )
#define SCALER_OLEDCOEF0_MASK 0xffffffff
#define SCALER_OLEDCOEF0_WIDTH 32
#define SCALER_OLEDCOEF1 HW_REGISTER_RW( 0x7e400088 )
#define SCALER_OLEDCOEF1_MASK 0xffffffff
#define SCALER_OLEDCOEF1_WIDTH 32
#define SCALER_OLEDCOEF2 HW_REGISTER_RW( 0x7e40008c )
#define SCALER_OLEDCOEF2_MASK 0xffffffff
#define SCALER_OLEDCOEF2_WIDTH 32
#define SCALER_DISPSLAVE0 HW_REGISTER_RW( 0x7e4000c0 )
#define SCALER_DISPSLAVE0_MASK 0xffffffff
#define SCALER_DISPSLAVE0_WIDTH 32
#define SCALER_DISPSLAVE1 HW_REGISTER_RW( 0x7e4000c8 )
#define SCALER_DISPSLAVE1_MASK 0xffffffff
#define SCALER_DISPSLAVE1_WIDTH 32
#define SCALER_DISPSLAVE2 HW_REGISTER_RW( 0x7e4000d0 )
#define SCALER_DISPSLAVE2_MASK 0xffffffff
#define SCALER_DISPSLAVE2_WIDTH 32
#define SCALER_DISPGAMDAT HW_REGISTER_RW( 0x7e4000e0 )
#define SCALER_DISPGAMDAT_MASK 0xffffffff
#define SCALER_DISPGAMDAT_WIDTH 32

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bcm2708_chip/i2c0.h Executable file
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// This file was generated by the create_regs script
#define I2C0_BASE 0x7e205000
#define I2C0_C HW_REGISTER_RW( 0x7e205000 )
#define I2C0_C_MASK 0x00008701
#define I2C0_C_WIDTH 16
#define I2C0_C_RESET 0000000000
#define I2C0_S HW_REGISTER_RW( 0x7e205004 )
#define I2C0_S_MASK 0xffffffff
#define I2C0_S_WIDTH 32
#define I2C0_S_RESET 0x00000050
#define I2C0_DLEN HW_REGISTER_RW( 0x7e205008 )
#define I2C0_DLEN_MASK 0x0000ffff
#define I2C0_DLEN_WIDTH 16
#define I2C0_DLEN_RESET 0000000000
#define I2C0_A HW_REGISTER_RW( 0x7e20500c )
#define I2C0_A_MASK 0x0000007f
#define I2C0_A_WIDTH 7
#define I2C0_A_RESET 0000000000
#define I2C0_FIFO HW_REGISTER_RW( 0x7e205010 )
#define I2C0_FIFO_MASK 0x000000ff
#define I2C0_FIFO_WIDTH 8
#define I2C0_FIFO_RESET 0000000000
#define I2C0_DIV HW_REGISTER_RW( 0x7e205014 )
#define I2C0_DIV_MASK 0x0000ffff
#define I2C0_DIV_WIDTH 16
#define I2C0_DIV_RESET 0x000005dc
#define I2C0_DEL HW_REGISTER_RW( 0x7e205018 )
#define I2C0_DEL_MASK 0xffffffff
#define I2C0_DEL_WIDTH 32
#define I2C0_DEL_RESET 0x00300030
#define I2C0_CLKT HW_REGISTER_RW( 0x7e20501c )
#define I2C0_CLKT_MASK 0x0000ffff
#define I2C0_CLKT_WIDTH 16
#define I2C0_CLKT_RESET 0x00000040

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bcm2708_chip/i2c1.h Executable file
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// This file was generated by the create_regs script
#define I2C1_BASE 0x7e804000
#define I2C1_C HW_REGISTER_RW( 0x7e804000 )
#define I2C1_C_MASK 0x00008701
#define I2C1_C_WIDTH 16
#define I2C1_C_RESET 0000000000
#define I2C1_S HW_REGISTER_RW( 0x7e804004 )
#define I2C1_S_MASK 0xffffffff
#define I2C1_S_WIDTH 32
#define I2C1_S_RESET 0x00000050
#define I2C1_DLEN HW_REGISTER_RW( 0x7e804008 )
#define I2C1_DLEN_MASK 0x0000ffff
#define I2C1_DLEN_WIDTH 16
#define I2C1_DLEN_RESET 0000000000
#define I2C1_A HW_REGISTER_RW( 0x7e80400c )
#define I2C1_A_MASK 0x0000007f
#define I2C1_A_WIDTH 7
#define I2C1_A_RESET 0000000000
#define I2C1_FIFO HW_REGISTER_RW( 0x7e804010 )
#define I2C1_FIFO_MASK 0x000000ff
#define I2C1_FIFO_WIDTH 8
#define I2C1_FIFO_RESET 0000000000
#define I2C1_DIV HW_REGISTER_RW( 0x7e804014 )
#define I2C1_DIV_MASK 0x0000ffff
#define I2C1_DIV_WIDTH 16
#define I2C1_DIV_RESET 0x000005dc
#define I2C1_DEL HW_REGISTER_RW( 0x7e804018 )
#define I2C1_DEL_MASK 0xffffffff
#define I2C1_DEL_WIDTH 32
#define I2C1_DEL_RESET 0x00300030
#define I2C1_CLKT HW_REGISTER_RW( 0x7e80401c )
#define I2C1_CLKT_MASK 0x0000ffff
#define I2C1_CLKT_WIDTH 16
#define I2C1_CLKT_RESET 0x00000040

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bcm2708_chip/i2c2.h Executable file
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// This file was generated by the create_regs script
#define I2C2_BASE 0x7e805000
#define I2C2_C HW_REGISTER_RW( 0x7e805000 )
#define I2C2_C_MASK 0x00008701
#define I2C2_C_WIDTH 16
#define I2C2_C_RESET 0000000000
#define I2C2_S HW_REGISTER_RW( 0x7e805004 )
#define I2C2_S_MASK 0xffffffff
#define I2C2_S_WIDTH 32
#define I2C2_S_RESET 0x00000050
#define I2C2_DLEN HW_REGISTER_RW( 0x7e805008 )
#define I2C2_DLEN_MASK 0x0000ffff
#define I2C2_DLEN_WIDTH 16
#define I2C2_DLEN_RESET 0000000000
#define I2C2_A HW_REGISTER_RW( 0x7e80500c )
#define I2C2_A_MASK 0x0000007f
#define I2C2_A_WIDTH 7
#define I2C2_A_RESET 0000000000
#define I2C2_FIFO HW_REGISTER_RW( 0x7e805010 )
#define I2C2_FIFO_MASK 0x000000ff
#define I2C2_FIFO_WIDTH 8
#define I2C2_FIFO_RESET 0000000000
#define I2C2_DIV HW_REGISTER_RW( 0x7e805014 )
#define I2C2_DIV_MASK 0x0000ffff
#define I2C2_DIV_WIDTH 16
#define I2C2_DIV_RESET 0x000005dc
#define I2C2_DEL HW_REGISTER_RW( 0x7e805018 )
#define I2C2_DEL_MASK 0xffffffff
#define I2C2_DEL_WIDTH 32
#define I2C2_DEL_RESET 0x00300030
#define I2C2_CLKT HW_REGISTER_RW( 0x7e80501c )
#define I2C2_CLKT_MASK 0x0000ffff
#define I2C2_CLKT_WIDTH 16
#define I2C2_CLKT_RESET 0x00000040

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bcm2708_chip/i2c_spi_slv.h Executable file
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// This file was generated by the create_regs script
#define I2C_SPI_SLV_BASE 0x7e214000
#define I2C_SPI_SLV_APB_ID 0x73506783
#define I2C_SPI_SLV_DR HW_REGISTER_RW( 0x7e214000 )
#define I2C_SPI_SLV_DR_MASK 0xffff3fff
#define I2C_SPI_SLV_DR_WIDTH 32
#define I2C_SPI_SLV_DR_RESET 0x00120000
#define I2C_SPI_SLV_DR_DATA_BITS 7:0
#define I2C_SPI_SLV_DR_DATA_SET 0x000000ff
#define I2C_SPI_SLV_DR_DATA_CLR 0xffffff00
#define I2C_SPI_SLV_DR_DATA_MSB 7
#define I2C_SPI_SLV_DR_DATA_LSB 0
#define I2C_SPI_SLV_DR_OE_BITS 8:8
#define I2C_SPI_SLV_DR_OE_SET 0x00000100
#define I2C_SPI_SLV_DR_OE_CLR 0xfffffeff
#define I2C_SPI_SLV_DR_OE_MSB 8
#define I2C_SPI_SLV_DR_OE_LSB 8
#define I2C_SPI_SLV_DR_UE_BITS 9:9
#define I2C_SPI_SLV_DR_UE_SET 0x00000200
#define I2C_SPI_SLV_DR_UE_CLR 0xfffffdff
#define I2C_SPI_SLV_DR_UE_MSB 9
#define I2C_SPI_SLV_DR_UE_LSB 9
#define I2C_SPI_SLV_DR_TXDMAPREQ_BITS 10:10
#define I2C_SPI_SLV_DR_TXDMAPREQ_SET 0x00000400
#define I2C_SPI_SLV_DR_TXDMAPREQ_CLR 0xfffffbff
#define I2C_SPI_SLV_DR_TXDMAPREQ_MSB 10
#define I2C_SPI_SLV_DR_TXDMAPREQ_LSB 10
#define I2C_SPI_SLV_DR_TXDMABREQ_BITS 11:11
#define I2C_SPI_SLV_DR_TXDMABREQ_SET 0x00000800
#define I2C_SPI_SLV_DR_TXDMABREQ_CLR 0xfffff7ff
#define I2C_SPI_SLV_DR_TXDMABREQ_MSB 11
#define I2C_SPI_SLV_DR_TXDMABREQ_LSB 11
#define I2C_SPI_SLV_DR_RXDMAPREQ_BITS 12:12
#define I2C_SPI_SLV_DR_RXDMAPREQ_SET 0x00001000
#define I2C_SPI_SLV_DR_RXDMAPREQ_CLR 0xffffefff
#define I2C_SPI_SLV_DR_RXDMAPREQ_MSB 12
#define I2C_SPI_SLV_DR_RXDMAPREQ_LSB 12
#define I2C_SPI_SLV_DR_RXDMABREQ_BITS 13:13
#define I2C_SPI_SLV_DR_RXDMABREQ_SET 0x00002000
#define I2C_SPI_SLV_DR_RXDMABREQ_CLR 0xffffdfff
#define I2C_SPI_SLV_DR_RXDMABREQ_MSB 13
#define I2C_SPI_SLV_DR_RXDMABREQ_LSB 13
#define I2C_SPI_SLV_DR_TXBUSY_BITS 16:16
#define I2C_SPI_SLV_DR_TXBUSY_SET 0x00010000
#define I2C_SPI_SLV_DR_TXBUSY_CLR 0xfffeffff
#define I2C_SPI_SLV_DR_TXBUSY_MSB 16
#define I2C_SPI_SLV_DR_TXBUSY_LSB 16
#define I2C_SPI_SLV_DR_RXFE_BITS 17:17
#define I2C_SPI_SLV_DR_RXFE_SET 0x00020000
#define I2C_SPI_SLV_DR_RXFE_CLR 0xfffdffff
#define I2C_SPI_SLV_DR_RXFE_MSB 17
#define I2C_SPI_SLV_DR_RXFE_LSB 17
#define I2C_SPI_SLV_DR_TXFF_BITS 18:18
#define I2C_SPI_SLV_DR_TXFF_SET 0x00040000
#define I2C_SPI_SLV_DR_TXFF_CLR 0xfffbffff
#define I2C_SPI_SLV_DR_TXFF_MSB 18
#define I2C_SPI_SLV_DR_TXFF_LSB 18
#define I2C_SPI_SLV_DR_RXFF_BITS 19:19
#define I2C_SPI_SLV_DR_RXFF_SET 0x00080000
#define I2C_SPI_SLV_DR_RXFF_CLR 0xfff7ffff
#define I2C_SPI_SLV_DR_RXFF_MSB 19
#define I2C_SPI_SLV_DR_RXFF_LSB 19
#define I2C_SPI_SLV_DR_TXFE_BITS 20:20
#define I2C_SPI_SLV_DR_TXFE_SET 0x00100000
#define I2C_SPI_SLV_DR_TXFE_CLR 0xffefffff
#define I2C_SPI_SLV_DR_TXFE_MSB 20
#define I2C_SPI_SLV_DR_TXFE_LSB 20
#define I2C_SPI_SLV_DR_RXBUSY_BITS 21:21
#define I2C_SPI_SLV_DR_RXBUSY_SET 0x00200000
#define I2C_SPI_SLV_DR_RXBUSY_CLR 0xffdfffff
#define I2C_SPI_SLV_DR_RXBUSY_MSB 21
#define I2C_SPI_SLV_DR_RXBUSY_LSB 21
#define I2C_SPI_SLV_DR_TXFLEVEL_BITS 26:22
#define I2C_SPI_SLV_DR_TXFLEVEL_SET 0x07c00000
#define I2C_SPI_SLV_DR_TXFLEVEL_CLR 0xf83fffff
#define I2C_SPI_SLV_DR_TXFLEVEL_MSB 26
#define I2C_SPI_SLV_DR_TXFLEVEL_LSB 22
#define I2C_SPI_SLV_DR_RXFLEVEL_BITS 31:27
#define I2C_SPI_SLV_DR_RXFLEVEL_SET 0xf8000000
#define I2C_SPI_SLV_DR_RXFLEVEL_CLR 0x07ffffff
#define I2C_SPI_SLV_DR_RXFLEVEL_MSB 31
#define I2C_SPI_SLV_DR_RXFLEVEL_LSB 27
#define I2C_SPI_SLV_RSR HW_REGISTER_RW( 0x7e214004 )
#define I2C_SPI_SLV_RSR_MASK 0x0000003f
#define I2C_SPI_SLV_RSR_WIDTH 6
#define I2C_SPI_SLV_RSR_RESET 0000000000
#define I2C_SPI_SLV_RSR_OE_BITS 0:0
#define I2C_SPI_SLV_RSR_OE_SET 0x00000001
#define I2C_SPI_SLV_RSR_OE_CLR 0xfffffffe
#define I2C_SPI_SLV_RSR_OE_MSB 0
#define I2C_SPI_SLV_RSR_OE_LSB 0
#define I2C_SPI_SLV_RSR_UE_BITS 1:1
#define I2C_SPI_SLV_RSR_UE_SET 0x00000002
#define I2C_SPI_SLV_RSR_UE_CLR 0xfffffffd
#define I2C_SPI_SLV_RSR_UE_MSB 1
#define I2C_SPI_SLV_RSR_UE_LSB 1
#define I2C_SPI_SLV_RSR_TXDMAPREQ_BITS 2:2
#define I2C_SPI_SLV_RSR_TXDMAPREQ_SET 0x00000004
#define I2C_SPI_SLV_RSR_TXDMAPREQ_CLR 0xfffffffb
#define I2C_SPI_SLV_RSR_TXDMAPREQ_MSB 2
#define I2C_SPI_SLV_RSR_TXDMAPREQ_LSB 2
#define I2C_SPI_SLV_RSR_TXDMABREQ_BITS 3:3
#define I2C_SPI_SLV_RSR_TXDMABREQ_SET 0x00000008
#define I2C_SPI_SLV_RSR_TXDMABREQ_CLR 0xfffffff7
#define I2C_SPI_SLV_RSR_TXDMABREQ_MSB 3
#define I2C_SPI_SLV_RSR_TXDMABREQ_LSB 3
#define I2C_SPI_SLV_RSR_RXDMAPREQ_BITS 4:4
#define I2C_SPI_SLV_RSR_RXDMAPREQ_SET 0x00000010
#define I2C_SPI_SLV_RSR_RXDMAPREQ_CLR 0xffffffef
#define I2C_SPI_SLV_RSR_RXDMAPREQ_MSB 4
#define I2C_SPI_SLV_RSR_RXDMAPREQ_LSB 4
#define I2C_SPI_SLV_RSR_RXDMABREQ_BITS 5:5
#define I2C_SPI_SLV_RSR_RXDMABREQ_SET 0x00000020
#define I2C_SPI_SLV_RSR_RXDMABREQ_CLR 0xffffffdf
#define I2C_SPI_SLV_RSR_RXDMABREQ_MSB 5
#define I2C_SPI_SLV_RSR_RXDMABREQ_LSB 5
#define I2C_SPI_SLV_SLV HW_REGISTER_RW( 0x7e214008 )
#define I2C_SPI_SLV_SLV_MASK 0x0000007f
#define I2C_SPI_SLV_SLV_WIDTH 7
#define I2C_SPI_SLV_SLV_RESET 0000000000
#define I2C_SPI_SLV_SLV_ADDR_BITS 6:0
#define I2C_SPI_SLV_SLV_ADDR_SET 0x0000007f
#define I2C_SPI_SLV_SLV_ADDR_CLR 0xffffff80
#define I2C_SPI_SLV_SLV_ADDR_MSB 6
#define I2C_SPI_SLV_SLV_ADDR_LSB 0
#define I2C_SPI_SLV_CR HW_REGISTER_RW( 0x7e21400c )
#define I2C_SPI_SLV_CR_MASK 0x0001ffff
#define I2C_SPI_SLV_CR_WIDTH 17
#define I2C_SPI_SLV_CR_RESET 0000000000
#define I2C_SPI_SLV_CR_EN_BITS 0:0
#define I2C_SPI_SLV_CR_EN_SET 0x00000001
#define I2C_SPI_SLV_CR_EN_CLR 0xfffffffe
#define I2C_SPI_SLV_CR_EN_MSB 0
#define I2C_SPI_SLV_CR_EN_LSB 0
#define I2C_SPI_SLV_CR_SPI_BITS 1:1
#define I2C_SPI_SLV_CR_SPI_SET 0x00000002
#define I2C_SPI_SLV_CR_SPI_CLR 0xfffffffd
#define I2C_SPI_SLV_CR_SPI_MSB 1
#define I2C_SPI_SLV_CR_SPI_LSB 1
#define I2C_SPI_SLV_CR_I2C_BITS 2:2
#define I2C_SPI_SLV_CR_I2C_SET 0x00000004
#define I2C_SPI_SLV_CR_I2C_CLR 0xfffffffb
#define I2C_SPI_SLV_CR_I2C_MSB 2
#define I2C_SPI_SLV_CR_I2C_LSB 2
#define I2C_SPI_SLV_CR_CPHA_BITS 3:3
#define I2C_SPI_SLV_CR_CPHA_SET 0x00000008
#define I2C_SPI_SLV_CR_CPHA_CLR 0xfffffff7
#define I2C_SPI_SLV_CR_CPHA_MSB 3
#define I2C_SPI_SLV_CR_CPHA_LSB 3
#define I2C_SPI_SLV_CR_CPOL_BITS 4:4
#define I2C_SPI_SLV_CR_CPOL_SET 0x00000010
#define I2C_SPI_SLV_CR_CPOL_CLR 0xffffffef
#define I2C_SPI_SLV_CR_CPOL_MSB 4
#define I2C_SPI_SLV_CR_CPOL_LSB 4
#define I2C_SPI_SLV_CR_ENSTAT_BITS 5:5
#define I2C_SPI_SLV_CR_ENSTAT_SET 0x00000020
#define I2C_SPI_SLV_CR_ENSTAT_CLR 0xffffffdf
#define I2C_SPI_SLV_CR_ENSTAT_MSB 5
#define I2C_SPI_SLV_CR_ENSTAT_LSB 5
#define I2C_SPI_SLV_CR_ENCTRL_BITS 6:6
#define I2C_SPI_SLV_CR_ENCTRL_SET 0x00000040
#define I2C_SPI_SLV_CR_ENCTRL_CLR 0xffffffbf
#define I2C_SPI_SLV_CR_ENCTRL_MSB 6
#define I2C_SPI_SLV_CR_ENCTRL_LSB 6
#define I2C_SPI_SLV_CR_BRK_BITS 7:7
#define I2C_SPI_SLV_CR_BRK_SET 0x00000080
#define I2C_SPI_SLV_CR_BRK_CLR 0xffffff7f
#define I2C_SPI_SLV_CR_BRK_MSB 7
#define I2C_SPI_SLV_CR_BRK_LSB 7
#define I2C_SPI_SLV_CR_TXE_BITS 8:8
#define I2C_SPI_SLV_CR_TXE_SET 0x00000100
#define I2C_SPI_SLV_CR_TXE_CLR 0xfffffeff
#define I2C_SPI_SLV_CR_TXE_MSB 8
#define I2C_SPI_SLV_CR_TXE_LSB 8
#define I2C_SPI_SLV_CR_RXE_BITS 9:9
#define I2C_SPI_SLV_CR_RXE_SET 0x00000200
#define I2C_SPI_SLV_CR_RXE_CLR 0xfffffdff
#define I2C_SPI_SLV_CR_RXE_MSB 9
#define I2C_SPI_SLV_CR_RXE_LSB 9
#define I2C_SPI_SLV_CR_INV_RXF_BITS 10:10
#define I2C_SPI_SLV_CR_INV_RXF_SET 0x00000400
#define I2C_SPI_SLV_CR_INV_RXF_CLR 0xfffffbff
#define I2C_SPI_SLV_CR_INV_RXF_MSB 10
#define I2C_SPI_SLV_CR_INV_RXF_LSB 10
#define I2C_SPI_SLV_CR_TESTFIFO_BITS 11:11
#define I2C_SPI_SLV_CR_TESTFIFO_SET 0x00000800
#define I2C_SPI_SLV_CR_TESTFIFO_CLR 0xfffff7ff
#define I2C_SPI_SLV_CR_TESTFIFO_MSB 11
#define I2C_SPI_SLV_CR_TESTFIFO_LSB 11
#define I2C_SPI_SLV_CR_HOSTCTRLEN_BITS 12:12
#define I2C_SPI_SLV_CR_HOSTCTRLEN_SET 0x00001000
#define I2C_SPI_SLV_CR_HOSTCTRLEN_CLR 0xffffefff
#define I2C_SPI_SLV_CR_HOSTCTRLEN_MSB 12
#define I2C_SPI_SLV_CR_HOSTCTRLEN_LSB 12
#define I2C_SPI_SLV_CR_INV_TXF_BITS 13:13
#define I2C_SPI_SLV_CR_INV_TXF_SET 0x00002000
#define I2C_SPI_SLV_CR_INV_TXF_CLR 0xffffdfff
#define I2C_SPI_SLV_CR_INV_TXF_MSB 13
#define I2C_SPI_SLV_CR_INV_TXF_LSB 13
#define I2C_SPI_SLV_FR HW_REGISTER_RW( 0x7e214010 )
#define I2C_SPI_SLV_FR_MASK 0x0000ffff
#define I2C_SPI_SLV_FR_WIDTH 16
#define I2C_SPI_SLV_FR_RESET 0x00000012
#define I2C_SPI_SLV_FR_TXBUSY_BITS 0:0
#define I2C_SPI_SLV_FR_TXBUSY_SET 0x00000001
#define I2C_SPI_SLV_FR_TXBUSY_CLR 0xfffffffe
#define I2C_SPI_SLV_FR_TXBUSY_MSB 0
#define I2C_SPI_SLV_FR_TXBUSY_LSB 0
#define I2C_SPI_SLV_FR_RXFE_BITS 1:1
#define I2C_SPI_SLV_FR_RXFE_SET 0x00000002
#define I2C_SPI_SLV_FR_RXFE_CLR 0xfffffffd
#define I2C_SPI_SLV_FR_RXFE_MSB 1
#define I2C_SPI_SLV_FR_RXFE_LSB 1
#define I2C_SPI_SLV_FR_TXFF_BITS 2:2
#define I2C_SPI_SLV_FR_TXFF_SET 0x00000004
#define I2C_SPI_SLV_FR_TXFF_CLR 0xfffffffb
#define I2C_SPI_SLV_FR_TXFF_MSB 2
#define I2C_SPI_SLV_FR_TXFF_LSB 2
#define I2C_SPI_SLV_FR_RXFF_BITS 3:3
#define I2C_SPI_SLV_FR_RXFF_SET 0x00000008
#define I2C_SPI_SLV_FR_RXFF_CLR 0xfffffff7
#define I2C_SPI_SLV_FR_RXFF_MSB 3
#define I2C_SPI_SLV_FR_RXFF_LSB 3
#define I2C_SPI_SLV_FR_TXFE_BITS 4:4
#define I2C_SPI_SLV_FR_TXFE_SET 0x00000010
#define I2C_SPI_SLV_FR_TXFE_CLR 0xffffffef
#define I2C_SPI_SLV_FR_TXFE_MSB 4
#define I2C_SPI_SLV_FR_TXFE_LSB 4
#define I2C_SPI_SLV_FR_RXBUSY_BITS 5:5
#define I2C_SPI_SLV_FR_RXBUSY_SET 0x00000020
#define I2C_SPI_SLV_FR_RXBUSY_CLR 0xffffffdf
#define I2C_SPI_SLV_FR_RXBUSY_MSB 5
#define I2C_SPI_SLV_FR_RXBUSY_LSB 5
#define I2C_SPI_SLV_FR_TXFLEVEL_BITS 6:10
#define I2C_SPI_SLV_FR_TXFLEVEL_SET 0x00000000000
#define I2C_SPI_SLV_FR_TXFLEVEL_CLR 0xffffffff111
#define I2C_SPI_SLV_FR_TXFLEVEL_MSB 6
#define I2C_SPI_SLV_FR_TXFLEVEL_LSB 10
#define I2C_SPI_SLV_FR_RXFLEVEL_BITS 15:11
#define I2C_SPI_SLV_FR_RXFLEVEL_SET 0x0000f800
#define I2C_SPI_SLV_FR_RXFLEVEL_CLR 0xffff07ff
#define I2C_SPI_SLV_FR_RXFLEVEL_MSB 15
#define I2C_SPI_SLV_FR_RXFLEVEL_LSB 11
#define I2C_SPI_SLV_IFLS HW_REGISTER_RW( 0x7e214014 )
#define I2C_SPI_SLV_IFLS_MASK 0x00000fff
#define I2C_SPI_SLV_IFLS_WIDTH 12
#define I2C_SPI_SLV_IFLS_RESET 0x00000492
#define I2C_SPI_SLV_IFLS_TXIFLSEL_BITS 2:0
#define I2C_SPI_SLV_IFLS_TXIFLSEL_SET 0x00000007
#define I2C_SPI_SLV_IFLS_TXIFLSEL_CLR 0xfffffff8
#define I2C_SPI_SLV_IFLS_TXIFLSEL_MSB 2
#define I2C_SPI_SLV_IFLS_TXIFLSEL_LSB 0
#define I2C_SPI_SLV_IFLS_RXIFLSEL_BITS 5:3
#define I2C_SPI_SLV_IFLS_RXIFLSEL_SET 0x00000038
#define I2C_SPI_SLV_IFLS_RXIFLSEL_CLR 0xffffffc7
#define I2C_SPI_SLV_IFLS_RXIFLSEL_MSB 5
#define I2C_SPI_SLV_IFLS_RXIFLSEL_LSB 3
#define I2C_SPI_SLV_IFLS_TXIFPSEL_BITS 8:6
#define I2C_SPI_SLV_IFLS_TXIFPSEL_SET 0x000001c0
#define I2C_SPI_SLV_IFLS_TXIFPSEL_CLR 0xfffffe3f
#define I2C_SPI_SLV_IFLS_TXIFPSEL_MSB 8
#define I2C_SPI_SLV_IFLS_TXIFPSEL_LSB 6
#define I2C_SPI_SLV_IFLS_RXIFPSEL_BITS 11:9
#define I2C_SPI_SLV_IFLS_RXIFPSEL_SET 0x00000e00
#define I2C_SPI_SLV_IFLS_RXIFPSEL_CLR 0xfffff1ff
#define I2C_SPI_SLV_IFLS_RXIFPSEL_MSB 11
#define I2C_SPI_SLV_IFLS_RXIFPSEL_LSB 9
#define I2C_SPI_SLV_IMSC HW_REGISTER_RW( 0x7e214018 )
#define I2C_SPI_SLV_IMSC_MASK 0x0000000f
#define I2C_SPI_SLV_IMSC_WIDTH 4
#define I2C_SPI_SLV_IMSC_RESET 0000000000
#define I2C_SPI_SLV_IMSC_RXIM_BITS 0:0
#define I2C_SPI_SLV_IMSC_RXIM_SET 0x00000001
#define I2C_SPI_SLV_IMSC_RXIM_CLR 0xfffffffe
#define I2C_SPI_SLV_IMSC_RXIM_MSB 0
#define I2C_SPI_SLV_IMSC_RXIM_LSB 0
#define I2C_SPI_SLV_IMSC_TXIM_BITS 1:1
#define I2C_SPI_SLV_IMSC_TXIM_SET 0x00000002
#define I2C_SPI_SLV_IMSC_TXIM_CLR 0xfffffffd
#define I2C_SPI_SLV_IMSC_TXIM_MSB 1
#define I2C_SPI_SLV_IMSC_TXIM_LSB 1
#define I2C_SPI_SLV_IMSC_BEIM_BITS 2:2
#define I2C_SPI_SLV_IMSC_BEIM_SET 0x00000004
#define I2C_SPI_SLV_IMSC_BEIM_CLR 0xfffffffb
#define I2C_SPI_SLV_IMSC_BEIM_MSB 2
#define I2C_SPI_SLV_IMSC_BEIM_LSB 2
#define I2C_SPI_SLV_IMSC_OEIM_BITS 3:3
#define I2C_SPI_SLV_IMSC_OEIM_SET 0x00000008
#define I2C_SPI_SLV_IMSC_OEIM_CLR 0xfffffff7
#define I2C_SPI_SLV_IMSC_OEIM_MSB 3
#define I2C_SPI_SLV_IMSC_OEIM_LSB 3
#define I2C_SPI_SLV_RIS HW_REGISTER_RW( 0x7e21401c )
#define I2C_SPI_SLV_RIS_MASK 0x0000000f
#define I2C_SPI_SLV_RIS_WIDTH 4
#define I2C_SPI_SLV_RIS_RESET 0x00000002
#define I2C_SPI_SLV_RIS_RXRIS_BITS 0:0
#define I2C_SPI_SLV_RIS_RXRIS_SET 0x00000001
#define I2C_SPI_SLV_RIS_RXRIS_CLR 0xfffffffe
#define I2C_SPI_SLV_RIS_RXRIS_MSB 0
#define I2C_SPI_SLV_RIS_RXRIS_LSB 0
#define I2C_SPI_SLV_RIS_TXRIS_BITS 1:1
#define I2C_SPI_SLV_RIS_TXRIS_SET 0x00000002
#define I2C_SPI_SLV_RIS_TXRIS_CLR 0xfffffffd
#define I2C_SPI_SLV_RIS_TXRIS_MSB 1
#define I2C_SPI_SLV_RIS_TXRIS_LSB 1
#define I2C_SPI_SLV_RIS_BERIS_BITS 2:2
#define I2C_SPI_SLV_RIS_BERIS_SET 0x00000004
#define I2C_SPI_SLV_RIS_BERIS_CLR 0xfffffffb
#define I2C_SPI_SLV_RIS_BERIS_MSB 2
#define I2C_SPI_SLV_RIS_BERIS_LSB 2
#define I2C_SPI_SLV_RIS_OERIS_BITS 3:3
#define I2C_SPI_SLV_RIS_OERIS_SET 0x00000008
#define I2C_SPI_SLV_RIS_OERIS_CLR 0xfffffff7
#define I2C_SPI_SLV_RIS_OERIS_MSB 3
#define I2C_SPI_SLV_RIS_OERIS_LSB 3
#define I2C_SPI_SLV_MIS HW_REGISTER_RW( 0x7e214020 )
#define I2C_SPI_SLV_MIS_MASK 0x0000000f
#define I2C_SPI_SLV_MIS_WIDTH 4
#define I2C_SPI_SLV_MIS_RESET 0000000000
#define I2C_SPI_SLV_MIS_RXMIS_BITS 0:0
#define I2C_SPI_SLV_MIS_RXMIS_SET 0x00000001
#define I2C_SPI_SLV_MIS_RXMIS_CLR 0xfffffffe
#define I2C_SPI_SLV_MIS_RXMIS_MSB 0
#define I2C_SPI_SLV_MIS_RXMIS_LSB 0
#define I2C_SPI_SLV_MIS_TXMIS_BITS 1:1
#define I2C_SPI_SLV_MIS_TXMIS_SET 0x00000002
#define I2C_SPI_SLV_MIS_TXMIS_CLR 0xfffffffd
#define I2C_SPI_SLV_MIS_TXMIS_MSB 1
#define I2C_SPI_SLV_MIS_TXMIS_LSB 1
#define I2C_SPI_SLV_MIS_BEMIS_BITS 2:2
#define I2C_SPI_SLV_MIS_BEMIS_SET 0x00000004
#define I2C_SPI_SLV_MIS_BEMIS_CLR 0xfffffffb
#define I2C_SPI_SLV_MIS_BEMIS_MSB 2
#define I2C_SPI_SLV_MIS_BEMIS_LSB 2
#define I2C_SPI_SLV_MIS_OEMIS_BITS 3:3
#define I2C_SPI_SLV_MIS_OEMIS_SET 0x00000008
#define I2C_SPI_SLV_MIS_OEMIS_CLR 0xfffffff7
#define I2C_SPI_SLV_MIS_OEMIS_MSB 3
#define I2C_SPI_SLV_MIS_OEMIS_LSB 3
#define I2C_SPI_SLV_ICR HW_REGISTER_RW( 0x7e214024 )
#define I2C_SPI_SLV_ICR_MASK 0x0000000f
#define I2C_SPI_SLV_ICR_WIDTH 4
#define I2C_SPI_SLV_ICR_RESET 0000000000
#define I2C_SPI_SLV_ICR_RXIC_BITS 0:0
#define I2C_SPI_SLV_ICR_RXIC_SET 0x00000001
#define I2C_SPI_SLV_ICR_RXIC_CLR 0xfffffffe
#define I2C_SPI_SLV_ICR_RXIC_MSB 0
#define I2C_SPI_SLV_ICR_RXIC_LSB 0
#define I2C_SPI_SLV_ICR_TXIC_BITS 1:1
#define I2C_SPI_SLV_ICR_TXIC_SET 0x00000002
#define I2C_SPI_SLV_ICR_TXIC_CLR 0xfffffffd
#define I2C_SPI_SLV_ICR_TXIC_MSB 1
#define I2C_SPI_SLV_ICR_TXIC_LSB 1
#define I2C_SPI_SLV_ICR_BEIC_BITS 2:2
#define I2C_SPI_SLV_ICR_BEIC_SET 0x00000004
#define I2C_SPI_SLV_ICR_BEIC_CLR 0xfffffffb
#define I2C_SPI_SLV_ICR_BEIC_MSB 2
#define I2C_SPI_SLV_ICR_BEIC_LSB 2
#define I2C_SPI_SLV_ICR_OEIC_BITS 3:3
#define I2C_SPI_SLV_ICR_OEIC_SET 0x00000008
#define I2C_SPI_SLV_ICR_OEIC_CLR 0xfffffff7
#define I2C_SPI_SLV_ICR_OEIC_MSB 3
#define I2C_SPI_SLV_ICR_OEIC_LSB 3
#define I2C_SPI_SLV_DMACR HW_REGISTER_RW( 0x7e214028 )
#define I2C_SPI_SLV_DMACR_MASK 0x00000007
#define I2C_SPI_SLV_DMACR_WIDTH 3
#define I2C_SPI_SLV_DMACR_RESET 0000000000
#define I2C_SPI_SLV_DMACR_RXDMAE_BITS 0:0
#define I2C_SPI_SLV_DMACR_RXDMAE_SET 0x00000001
#define I2C_SPI_SLV_DMACR_RXDMAE_CLR 0xfffffffe
#define I2C_SPI_SLV_DMACR_RXDMAE_MSB 0
#define I2C_SPI_SLV_DMACR_RXDMAE_LSB 0
#define I2C_SPI_SLV_DMACR_TXDMAE_BITS 1:1
#define I2C_SPI_SLV_DMACR_TXDMAE_SET 0x00000002
#define I2C_SPI_SLV_DMACR_TXDMAE_CLR 0xfffffffd
#define I2C_SPI_SLV_DMACR_TXDMAE_MSB 1
#define I2C_SPI_SLV_DMACR_TXDMAE_LSB 1
#define I2C_SPI_SLV_DMACR_DMAONERR_BITS 2:2
#define I2C_SPI_SLV_DMACR_DMAONERR_SET 0x00000004
#define I2C_SPI_SLV_DMACR_DMAONERR_CLR 0xfffffffb
#define I2C_SPI_SLV_DMACR_DMAONERR_MSB 2
#define I2C_SPI_SLV_DMACR_DMAONERR_LSB 2
#define I2C_SPI_SLV_TDR HW_REGISTER_RW( 0x7e21402c )
#define I2C_SPI_SLV_TDR_MASK 0x000000ff
#define I2C_SPI_SLV_TDR_WIDTH 8
#define I2C_SPI_SLV_TDR_RESET 0000000000
#define I2C_SPI_SLV_TDR_DATA_BITS 7:0
#define I2C_SPI_SLV_TDR_DATA_SET 0x000000ff
#define I2C_SPI_SLV_TDR_DATA_CLR 0xffffff00
#define I2C_SPI_SLV_TDR_DATA_MSB 7
#define I2C_SPI_SLV_TDR_DATA_LSB 0
#define I2C_SPI_SLV_VCSTAT HW_REGISTER_RW( 0x7e214030 )
#define I2C_SPI_SLV_VCSTAT_MASK 0x0000000f
#define I2C_SPI_SLV_VCSTAT_WIDTH 4
#define I2C_SPI_SLV_VCSTAT_RESET 0000000000
#define I2C_SPI_SLV_VCSTAT_DATA_BITS 3:0
#define I2C_SPI_SLV_VCSTAT_DATA_SET 0x0000000f
#define I2C_SPI_SLV_VCSTAT_DATA_CLR 0xfffffff0
#define I2C_SPI_SLV_VCSTAT_DATA_MSB 3
#define I2C_SPI_SLV_VCSTAT_DATA_LSB 0
#define I2C_SPI_SLV_HCTRL HW_REGISTER_RW( 0x7e214034 )
#define I2C_SPI_SLV_HCTRL_MASK 0x000000ff
#define I2C_SPI_SLV_HCTRL_WIDTH 8
#define I2C_SPI_SLV_HCTRL_RESET 0000000000
#define I2C_SPI_SLV_HCTRL_DATA_BITS 7:0
#define I2C_SPI_SLV_HCTRL_DATA_SET 0x000000ff
#define I2C_SPI_SLV_HCTRL_DATA_CLR 0xffffff00
#define I2C_SPI_SLV_HCTRL_DATA_MSB 7
#define I2C_SPI_SLV_HCTRL_DATA_LSB 0
#define I2C_SPI_SLV_DEBUG1 HW_REGISTER_RW( 0x7e214038 )
#define I2C_SPI_SLV_DEBUG1_MASK 0x03ffffff
#define I2C_SPI_SLV_DEBUG1_WIDTH 26
#define I2C_SPI_SLV_DEBUG1_RESET 0x0000000e
#define I2C_SPI_SLV_DEBUG1_DATA_BITS 25:0
#define I2C_SPI_SLV_DEBUG1_DATA_SET 0x03ffffff
#define I2C_SPI_SLV_DEBUG1_DATA_CLR 0xfc000000
#define I2C_SPI_SLV_DEBUG1_DATA_MSB 25
#define I2C_SPI_SLV_DEBUG1_DATA_LSB 0
#define I2C_SPI_SLV_DEBUG2 HW_REGISTER_RW( 0x7e21403c )
#define I2C_SPI_SLV_DEBUG2_MASK 0x00ffffff
#define I2C_SPI_SLV_DEBUG2_WIDTH 24
#define I2C_SPI_SLV_DEBUG2_RESET 0x00400000
#define I2C_SPI_SLV_DEBUG2_DATA_BITS 23:0
#define I2C_SPI_SLV_DEBUG2_DATA_SET 0x00ffffff
#define I2C_SPI_SLV_DEBUG2_DATA_CLR 0xff000000
#define I2C_SPI_SLV_DEBUG2_DATA_MSB 23
#define I2C_SPI_SLV_DEBUG2_DATA_LSB 0

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bcm2708_chip/intctrl0.h Executable file
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// This file was generated by the create_regs script
#define IC0_BASE 0x7e002000
#define IC0_APB_ID 0x494e5445
#define IC0_C HW_REGISTER_RW( 0x7e002000 )
#define IC0_C_MASK 0x0000000f
#define IC0_C_WIDTH 4
#define IC0_C_RESET 0000000000
#define IC0_S HW_REGISTER_RO( 0x7e002004 )
#define IC0_S_MASK 0x073f073f
#define IC0_S_WIDTH 27
#define IC0_SRC0 HW_REGISTER_RO( 0x7e002008 )
#define IC0_SRC0_MASK 0xffffffff
#define IC0_SRC0_WIDTH 32
#define IC0_SRC1 HW_REGISTER_RO( 0x7e00200c )
#define IC0_SRC1_MASK 0xffffffff
#define IC0_SRC1_WIDTH 32
#define IC0_MASK0 HW_REGISTER_RW( 0x7e002010 )
#define IC0_MASK0_MASK 0x77777777
#define IC0_MASK0_WIDTH 31
#define IC0_MASK0_RESET 0000000000
#define IC0_MASK1 HW_REGISTER_RW( 0x7e002014 )
#define IC0_MASK1_MASK 0x77777777
#define IC0_MASK1_WIDTH 31
#define IC0_MASK1_RESET 0000000000
#define IC0_MASK2 HW_REGISTER_RW( 0x7e002018 )
#define IC0_MASK2_MASK 0x77777777
#define IC0_MASK2_WIDTH 31
#define IC0_MASK2_RESET 0000000000
#define IC0_MASK3 HW_REGISTER_RW( 0x7e00201c )
#define IC0_MASK3_MASK 0x77777777
#define IC0_MASK3_WIDTH 31
#define IC0_MASK3_RESET 0000000000
#define IC0_MASK4 HW_REGISTER_RW( 0x7e002020 )
#define IC0_MASK4_MASK 0x77777777
#define IC0_MASK4_WIDTH 31
#define IC0_MASK4_RESET 0000000000
#define IC0_MASK5 HW_REGISTER_RW( 0x7e002024 )
#define IC0_MASK5_MASK 0x77777777
#define IC0_MASK5_WIDTH 31
#define IC0_MASK5_RESET 0000000000
#define IC0_MASK6 HW_REGISTER_RW( 0x7e002028 )
#define IC0_MASK6_MASK 0x77777777
#define IC0_MASK6_WIDTH 31
#define IC0_MASK6_RESET 0000000000
#define IC0_MASK7 HW_REGISTER_RW( 0x7e00202c )
#define IC0_MASK7_MASK 0x77777777
#define IC0_MASK7_WIDTH 31
#define IC0_MASK7_RESET 0000000000
#define IC0_VADDR HW_REGISTER_RW( 0x7e002030 )
#define IC0_VADDR_MASK 0xfffffe00
#define IC0_VADDR_WIDTH 32
#define IC0_VADDR_RESET 0000000000
#define IC0_WAKEUP HW_REGISTER_RW( 0x7e002034 )
#define IC0_WAKEUP_MASK 0xfffffffe
#define IC0_WAKEUP_WIDTH 32
#define IC0_WAKEUP_RESET 0x10000000
#define IC0_PROFILE HW_REGISTER_RW( 0x7e002038 )
#define IC0_PROFILE_MASK 0x0000ffff
#define IC0_PROFILE_WIDTH 16
#define IC0_FORCE0 HW_REGISTER_RW( 0x7e002040 )
#define IC0_FORCE0_MASK 0xffffffff
#define IC0_FORCE0_WIDTH 32
#define IC0_FORCE0_RESET 0000000000
#define IC0_FORCE1 HW_REGISTER_RW( 0x7e002044 )
#define IC0_FORCE1_MASK 0xffffffff
#define IC0_FORCE1_WIDTH 32
#define IC0_FORCE1_RESET 0000000000
#define IC0_FORCE0_SET HW_REGISTER_RW( 0x7e002048 )
#define IC0_FORCE0_SET_MASK 0xffffffff
#define IC0_FORCE0_SET_WIDTH 32
#define IC0_FORCE0_SET_RESET 0000000000
#define IC0_FORCE1_SET HW_REGISTER_RW( 0x7e00204c )
#define IC0_FORCE1_SET_MASK 0xffffffff
#define IC0_FORCE1_SET_WIDTH 32
#define IC0_FORCE1_SET_RESET 0000000000
#define IC0_FORCE0_CLR HW_REGISTER_RW( 0x7e002050 )
#define IC0_FORCE0_CLR_MASK 0xffffffff
#define IC0_FORCE0_CLR_WIDTH 32
#define IC0_FORCE0_CLR_RESET 0000000000
#define IC0_FORCE1_CLR HW_REGISTER_RW( 0x7e002054 )
#define IC0_FORCE1_CLR_MASK 0xffffffff
#define IC0_FORCE1_CLR_WIDTH 32
#define IC0_FORCE1_CLR_RESET 0000000000

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bcm2708_chip/intctrl1.h Executable file
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// This file was generated by the create_regs script
#define IC1_BASE 0x7e002800
#define IC1_APB_ID 0x494e5445
#define IC1_C HW_REGISTER_RW( 0x7e002800 )
#define IC1_C_MASK 0x0000000f
#define IC1_C_WIDTH 4
#define IC1_C_RESET 0000000000
#define IC1_S HW_REGISTER_RO( 0x7e002804 )
#define IC1_S_MASK 0x073f073f
#define IC1_S_WIDTH 27
#define IC1_SRC0 HW_REGISTER_RO( 0x7e002808 )
#define IC1_SRC0_MASK 0xffffffff
#define IC1_SRC0_WIDTH 32
#define IC1_SRC1 HW_REGISTER_RO( 0x7e00280c )
#define IC1_SRC1_MASK 0xffffffff
#define IC1_SRC1_WIDTH 32
#define IC1_MASK0 HW_REGISTER_RW( 0x7e002810 )
#define IC1_MASK0_MASK 0x77777777
#define IC1_MASK0_WIDTH 31
#define IC1_MASK0_RESET 0000000000
#define IC1_MASK1 HW_REGISTER_RW( 0x7e002814 )
#define IC1_MASK1_MASK 0x77777777
#define IC1_MASK1_WIDTH 31
#define IC1_MASK1_RESET 0000000000
#define IC1_MASK2 HW_REGISTER_RW( 0x7e002818 )
#define IC1_MASK2_MASK 0x77777777
#define IC1_MASK2_WIDTH 31
#define IC1_MASK2_RESET 0000000000
#define IC1_MASK3 HW_REGISTER_RW( 0x7e00281c )
#define IC1_MASK3_MASK 0x77777777
#define IC1_MASK3_WIDTH 31
#define IC1_MASK3_RESET 0000000000
#define IC1_MASK4 HW_REGISTER_RW( 0x7e002820 )
#define IC1_MASK4_MASK 0x77777777
#define IC1_MASK4_WIDTH 31
#define IC1_MASK4_RESET 0000000000
#define IC1_MASK5 HW_REGISTER_RW( 0x7e002824 )
#define IC1_MASK5_MASK 0x77777777
#define IC1_MASK5_WIDTH 31
#define IC1_MASK5_RESET 0000000000
#define IC1_MASK6 HW_REGISTER_RW( 0x7e002828 )
#define IC1_MASK6_MASK 0x77777777
#define IC1_MASK6_WIDTH 31
#define IC1_MASK6_RESET 0000000000
#define IC1_MASK7 HW_REGISTER_RW( 0x7e00282c )
#define IC1_MASK7_MASK 0x77777777
#define IC1_MASK7_WIDTH 31
#define IC1_MASK7_RESET 0000000000
#define IC1_VADDR HW_REGISTER_RW( 0x7e002830 )
#define IC1_VADDR_MASK 0xfffffe00
#define IC1_VADDR_WIDTH 32
#define IC1_VADDR_RESET 0000000000
#define IC1_WAKEUP HW_REGISTER_RW( 0x7e002834 )
#define IC1_WAKEUP_MASK 0xfffffffe
#define IC1_WAKEUP_WIDTH 32
#define IC1_WAKEUP_RESET 0x10000000
#define IC1_PROFILE HW_REGISTER_RW( 0x7e002838 )
#define IC1_PROFILE_MASK 0x0000ffff
#define IC1_PROFILE_WIDTH 16
#define IC1_FORCE0 HW_REGISTER_RW( 0x7e002840 )
#define IC1_FORCE0_MASK 0xffffffff
#define IC1_FORCE0_WIDTH 32
#define IC1_FORCE0_RESET 0000000000
#define IC1_FORCE1 HW_REGISTER_RW( 0x7e002844 )
#define IC1_FORCE1_MASK 0xffffffff
#define IC1_FORCE1_WIDTH 32
#define IC1_FORCE1_RESET 0000000000
#define IC1_FORCE0_SET HW_REGISTER_RW( 0x7e002848 )
#define IC1_FORCE0_SET_MASK 0xffffffff
#define IC1_FORCE0_SET_WIDTH 32
#define IC1_FORCE0_SET_RESET 0000000000
#define IC1_FORCE1_SET HW_REGISTER_RW( 0x7e00284c )
#define IC1_FORCE1_SET_MASK 0xffffffff
#define IC1_FORCE1_SET_WIDTH 32
#define IC1_FORCE1_SET_RESET 0000000000
#define IC1_FORCE0_CLR HW_REGISTER_RW( 0x7e002850 )
#define IC1_FORCE0_CLR_MASK 0xffffffff
#define IC1_FORCE0_CLR_WIDTH 32
#define IC1_FORCE0_CLR_RESET 0000000000
#define IC1_FORCE1_CLR HW_REGISTER_RW( 0x7e002854 )
#define IC1_FORCE1_CLR_MASK 0xffffffff
#define IC1_FORCE1_CLR_WIDTH 32
#define IC1_FORCE1_CLR_RESET 0000000000

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bcm2708_chip/isp.h Executable file
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// This file was generated by the create_regs script
#define ISP_BASE 0x7ea00000
#define ISP_APB_ID 0x20697370
#define ISP_RC HW_REGISTER_RW( 0x7ea00000 )
#define ISP_RC_MASK 0xffffffff
#define ISP_RC_WIDTH 32

8284
bcm2708_chip/israel_bg_dctram.h Executable file
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608
bcm2708_chip/israel_bg_instr.h Executable file
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/***************************************************************************
* Copyright (c) 1999-2005, Broadcom Corporation
* All Rights Reserved
* Confidential Property of Broadcom Corporation
*
*
* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
*
* $brcm_Workfile: $
* $brcm_Revision: $
* $brcm_Date: $
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Mon Mar 28 16:48:47 2005
* MD5 Checksum ba913b07d554347688609e8e66f4943f
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.006
* Operating System solaris
*
* Spec Versions: BG 01
* BVN_MFD 1
* CAP 1
* DSP_CTRL 03
* IN656 1
* ITFP 03
* LBG 1
* NET 1
* SCL 1
* VBI_DEC 03
* VD_TOP 5
* VIDEO_DEC 03
* VIP_CTRL 03
* VIP_L2 03
* VPP 03
*
* RDB Files: /projects/BCM7043/A0/work/gelias/bcm7043_a0/design/chip/rdb/bcm7043_a0.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vip_tops/rdb/vip_top_blockdef.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/cap/rdb/bvn_cap.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/mfd/rdb/bvn_mfd.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/scl/rdb/bvn_scl.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vpp/rdb/vpp.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/video_decoder_top.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/vd_major_revid.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/video_decoder/rdb/vd_minor_revid.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/656_dec/rdb/in656.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/656_dec/rdb/in656_revid.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/l2/rdb/vip_intr_ctrl2.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vnet/rdb/bvn_net.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/lbg/rdb/vip_lbg.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/vib_top.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/video_dec.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vbi_dec/rdb/vbi_dec.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/itfp/rdb/itfp.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bvn/common/rdb/bvb_lite_general.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/vip_tops/rdb/vip_ctrl.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bsm/rdb/bg_top.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/bsm/rdb/bg_ctrl.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/dsp/rdb/dsp_top.rdb
* /projects/BCM7043/A0/snapshot/bcm7043_a0/design/dsp/rdb/dsp_ctrl.rdb
*
* Revision History:
*
* $brcm_Log: $
*
***************************************************************************/
#ifndef BCM7043_A0_BG_INSTR_H__
#define BCM7043_A0_BG_INSTR_H__
/***************************************************************************
*BG_INSTR - BG Instructions
***************************************************************************/
#define BG_INSTR_DCT_WRITE 0x005f0000 /* DCT_WRITE command */
#define BG_INSTR_PUTAC_RESET 0x005f0004 /* PUT AC command */
#define BG_INSTR_INIT_MPEGTYPE 0x005f0008 /* INIT MPEGTYPE */
#define BG_INSTR_INTRA_MAXRUN 0x005f000c /* INTRA MAX RUN */
#define BG_INSTR_INTER_MAXRUN 0x005f0010 /* INTER MAX RUN */
#define BG_INSTR_INTRA_LAST_MAXRUN 0x005f0014 /* INTRA LAST MAX RUN */
#define BG_INSTR_INTER_LAST_MAXRUN 0x005f0018 /* INTER LAST MAX RUN */
#define BG_INSTR_INTRA_MAXLEVEL 0x005f001c /* INTRA MAX LEVEL */
#define BG_INSTR_INTER_MAXLEVEL 0x005f0020 /* INTER MAX LEVEL */
#define BG_INSTR_INTRA_LAST_MAXLEVEL 0x005f0024 /* INTRA LAST MAX LEVEL */
#define BG_INSTR_INTER_LAST_MAXLEVEL 0x005f0028 /* INTER LAST MAX LEVEL */
#define BG_INSTR_INTRA_RUN_RAM_BASE 0x005f002c /* INTRA RUN RAM BASE */
#define BG_INSTR_INTER_RUN_RAM_BASE 0x005f0030 /* INTER RUN RAM BASE */
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE 0x005f0034 /* INTRA LAST RUN RAM BASE */
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE 0x005f0038 /* INTER LAST RUN RAM BASE */
#define BG_INSTR_INTRA_LEVEL_RAM_BASE 0x005f003c /* INTRA LEVEL RAM BASE */
#define BG_INSTR_INTER_LEVEL_RAM_BASE 0x005f0040 /* INTER LEVEL RAM BASE */
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE 0x005f0044 /* INTRA LAST LEVEL RAM BASE */
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE 0x005f0048 /* INTER LAST LEVEL RAM BASE */
#define BG_INSTR_LAST_AC_LEVEL 0x005f004c /* LAST AC LEVEL */
#define BG_INSTR_DSP_STOP_ADDR 0x005f0050 /* DSP STOP ADDRESS */
#define BG_INSTR_CBP_REG 0x005f0054 /* CBP REG VALUE */
#define BG_INSTR_PUTBIT_COUNTER 0x005f0058 /* PUTBIT COUNTER */
#define BG_INSTR_INIT_COMMAND 0x005f005c /* INIT COMMAND */
#define BG_INSTR_OUT_POINTER 0x005f0060 /* READ OUTPOINTER VALUE */
#define BG_INSTR_PUTBIT_10 0x005f0064 /* PUT BIT COMMAND */
#define BG_INSTR_PUTBIT_16 0x005f0068 /* PUT BIT COMMAND */
#define BG_INSTR_PUTAC 0x005f006c /* PUT AC */
#define BG_INSTR_EXECSTATUS 0x005f0070 /* EXEC STATUS */
#define BG_INSTR_REVISION_ID 0x005f0074 /* Letter Box Generator Revision register */
#define BG_INSTR_PUTAC_ACCEL 0x005f0078 // added temporary by ilyam 13/09/05
/***************************************************************************
*DCT_WRITE - DCT_WRITE command
***************************************************************************/
/* BG_INSTR :: DCT_WRITE :: reserved0 [31:01] */
#define BG_INSTR_DCT_WRITE_reserved0_MASK 0xfffffffe
#define BG_INSTR_DCT_WRITE_reserved0_ALIGN 0
#define BG_INSTR_DCT_WRITE_reserved0_BITS 31
#define BG_INSTR_DCT_WRITE_reserved0_SHIFT 1
/* BG_INSTR :: DCT_WRITE :: DCT_WRITE [00:00] */
#define BG_INSTR_DCT_WRITE_DCT_WRITE_MASK 0x00000001
#define BG_INSTR_DCT_WRITE_DCT_WRITE_ALIGN 0
#define BG_INSTR_DCT_WRITE_DCT_WRITE_BITS 1
#define BG_INSTR_DCT_WRITE_DCT_WRITE_SHIFT 0
/***************************************************************************
*PUTAC_RESET - PUT AC command
***************************************************************************/
/* BG_INSTR :: PUTAC_RESET :: reserved0 [31:01] */
#define BG_INSTR_PUTAC_RESET_reserved0_MASK 0xfffffffe
#define BG_INSTR_PUTAC_RESET_reserved0_ALIGN 0
#define BG_INSTR_PUTAC_RESET_reserved0_BITS 31
#define BG_INSTR_PUTAC_RESET_reserved0_SHIFT 1
/* BG_INSTR :: PUTAC_RESET :: PUTAC_RESET [00:00] */
#define BG_INSTR_PUTAC_RESET_PUTAC_RESET_MASK 0x00000001
#define BG_INSTR_PUTAC_RESET_PUTAC_RESET_ALIGN 0
#define BG_INSTR_PUTAC_RESET_PUTAC_RESET_BITS 1
#define BG_INSTR_PUTAC_RESET_PUTAC_RESET_SHIFT 0
/***************************************************************************
*INIT_MPEGTYPE - INIT MPEGTYPE
***************************************************************************/
/* BG_INSTR :: INIT_MPEGTYPE :: reserved0 [31:05] */
#define BG_INSTR_INIT_MPEGTYPE_reserved0_MASK 0xffffffe0
#define BG_INSTR_INIT_MPEGTYPE_reserved0_ALIGN 0
#define BG_INSTR_INIT_MPEGTYPE_reserved0_BITS 27
#define BG_INSTR_INIT_MPEGTYPE_reserved0_SHIFT 5
/* BG_INSTR :: INIT_MPEGTYPE :: CBP_MODE [04:04] */
#define BG_INSTR_INIT_MPEGTYPE_CBP_MODE_MASK 0x00000010
#define BG_INSTR_INIT_MPEGTYPE_CBP_MODE_ALIGN 0
#define BG_INSTR_INIT_MPEGTYPE_CBP_MODE_BITS 1
#define BG_INSTR_INIT_MPEGTYPE_CBP_MODE_SHIFT 4
/* BG_INSTR :: INIT_MPEGTYPE :: INTRA [03:03] */
#define BG_INSTR_INIT_MPEGTYPE_INTRA_MASK 0x00000008
#define BG_INSTR_INIT_MPEGTYPE_INTRA_ALIGN 0
#define BG_INSTR_INIT_MPEGTYPE_INTRA_BITS 1
#define BG_INSTR_INIT_MPEGTYPE_INTRA_SHIFT 3
/* BG_INSTR :: INIT_MPEGTYPE :: MPEG4 [02:02] */
#define BG_INSTR_INIT_MPEGTYPE_MPEG4_MASK 0x00000004
#define BG_INSTR_INIT_MPEGTYPE_MPEG4_ALIGN 0
#define BG_INSTR_INIT_MPEGTYPE_MPEG4_BITS 1
#define BG_INSTR_INIT_MPEGTYPE_MPEG4_SHIFT 2
/* BG_INSTR :: INIT_MPEGTYPE :: MPEG2 [01:01] */
#define BG_INSTR_INIT_MPEGTYPE_MPEG2_MASK 0x00000002
#define BG_INSTR_INIT_MPEGTYPE_MPEG2_ALIGN 0
#define BG_INSTR_INIT_MPEGTYPE_MPEG2_BITS 1
#define BG_INSTR_INIT_MPEGTYPE_MPEG2_SHIFT 1
/* BG_INSTR :: INIT_MPEGTYPE :: MPEG1 [00:00] */
#define BG_INSTR_INIT_MPEGTYPE_MPEG1_MASK 0x00000001
#define BG_INSTR_INIT_MPEGTYPE_MPEG1_ALIGN 0
#define BG_INSTR_INIT_MPEGTYPE_MPEG1_BITS 1
#define BG_INSTR_INIT_MPEGTYPE_MPEG1_SHIFT 0
/***************************************************************************
*INTRA_MAXRUN - INTRA MAX RUN
***************************************************************************/
/* BG_INSTR :: INTRA_MAXRUN :: reserved0 [31:06] */
#define BG_INSTR_INTRA_MAXRUN_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTRA_MAXRUN_reserved0_ALIGN 0
#define BG_INSTR_INTRA_MAXRUN_reserved0_BITS 26
#define BG_INSTR_INTRA_MAXRUN_reserved0_SHIFT 6
/* BG_INSTR :: INTRA_MAXRUN :: MAXRUN_VALUE [05:00] */
#define BG_INSTR_INTRA_MAXRUN_MAXRUN_VALUE_MASK 0x0000003f
#define BG_INSTR_INTRA_MAXRUN_MAXRUN_VALUE_ALIGN 0
#define BG_INSTR_INTRA_MAXRUN_MAXRUN_VALUE_BITS 6
#define BG_INSTR_INTRA_MAXRUN_MAXRUN_VALUE_SHIFT 0
/***************************************************************************
*INTER_MAXRUN - INTER MAX RUN
***************************************************************************/
/* BG_INSTR :: INTER_MAXRUN :: reserved0 [31:06] */
#define BG_INSTR_INTER_MAXRUN_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTER_MAXRUN_reserved0_ALIGN 0
#define BG_INSTR_INTER_MAXRUN_reserved0_BITS 26
#define BG_INSTR_INTER_MAXRUN_reserved0_SHIFT 6
/* BG_INSTR :: INTER_MAXRUN :: MAXRUN_VALUE [05:00] */
#define BG_INSTR_INTER_MAXRUN_MAXRUN_VALUE_MASK 0x0000003f
#define BG_INSTR_INTER_MAXRUN_MAXRUN_VALUE_ALIGN 0
#define BG_INSTR_INTER_MAXRUN_MAXRUN_VALUE_BITS 6
#define BG_INSTR_INTER_MAXRUN_MAXRUN_VALUE_SHIFT 0
/***************************************************************************
*INTRA_LAST_MAXRUN - INTRA LAST MAX RUN
***************************************************************************/
/* BG_INSTR :: INTRA_LAST_MAXRUN :: reserved0 [31:06] */
#define BG_INSTR_INTRA_LAST_MAXRUN_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTRA_LAST_MAXRUN_reserved0_ALIGN 0
#define BG_INSTR_INTRA_LAST_MAXRUN_reserved0_BITS 26
#define BG_INSTR_INTRA_LAST_MAXRUN_reserved0_SHIFT 6
/* BG_INSTR :: INTRA_LAST_MAXRUN :: MAXRUN_VALUE [05:00] */
#define BG_INSTR_INTRA_LAST_MAXRUN_MAXRUN_VALUE_MASK 0x0000003f
#define BG_INSTR_INTRA_LAST_MAXRUN_MAXRUN_VALUE_ALIGN 0
#define BG_INSTR_INTRA_LAST_MAXRUN_MAXRUN_VALUE_BITS 6
#define BG_INSTR_INTRA_LAST_MAXRUN_MAXRUN_VALUE_SHIFT 0
/***************************************************************************
*INTER_LAST_MAXRUN - INTER LAST MAX RUN
***************************************************************************/
/* BG_INSTR :: INTER_LAST_MAXRUN :: reserved0 [31:06] */
#define BG_INSTR_INTER_LAST_MAXRUN_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTER_LAST_MAXRUN_reserved0_ALIGN 0
#define BG_INSTR_INTER_LAST_MAXRUN_reserved0_BITS 26
#define BG_INSTR_INTER_LAST_MAXRUN_reserved0_SHIFT 6
/* BG_INSTR :: INTER_LAST_MAXRUN :: MAXRUN_VALUE [05:00] */
#define BG_INSTR_INTER_LAST_MAXRUN_MAXRUN_VALUE_MASK 0x0000003f
#define BG_INSTR_INTER_LAST_MAXRUN_MAXRUN_VALUE_ALIGN 0
#define BG_INSTR_INTER_LAST_MAXRUN_MAXRUN_VALUE_BITS 6
#define BG_INSTR_INTER_LAST_MAXRUN_MAXRUN_VALUE_SHIFT 0
/***************************************************************************
*INTRA_MAXLEVEL - INTRA MAX LEVEL
***************************************************************************/
/* BG_INSTR :: INTRA_MAXLEVEL :: reserved0 [31:06] */
#define BG_INSTR_INTRA_MAXLEVEL_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTRA_MAXLEVEL_reserved0_ALIGN 0
#define BG_INSTR_INTRA_MAXLEVEL_reserved0_BITS 26
#define BG_INSTR_INTRA_MAXLEVEL_reserved0_SHIFT 6
/* BG_INSTR :: INTRA_MAXLEVEL :: MAX_LEVEL_VALUE [05:00] */
#define BG_INSTR_INTRA_MAXLEVEL_MAX_LEVEL_VALUE_MASK 0x0000003f
#define BG_INSTR_INTRA_MAXLEVEL_MAX_LEVEL_VALUE_ALIGN 0
#define BG_INSTR_INTRA_MAXLEVEL_MAX_LEVEL_VALUE_BITS 6
#define BG_INSTR_INTRA_MAXLEVEL_MAX_LEVEL_VALUE_SHIFT 0
/***************************************************************************
*INTER_MAXLEVEL - INTER MAX LEVEL
***************************************************************************/
/* BG_INSTR :: INTER_MAXLEVEL :: reserved0 [31:06] */
#define BG_INSTR_INTER_MAXLEVEL_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTER_MAXLEVEL_reserved0_ALIGN 0
#define BG_INSTR_INTER_MAXLEVEL_reserved0_BITS 26
#define BG_INSTR_INTER_MAXLEVEL_reserved0_SHIFT 6
/* BG_INSTR :: INTER_MAXLEVEL :: MAX_LEVEL_VALUE [05:00] */
#define BG_INSTR_INTER_MAXLEVEL_MAX_LEVEL_VALUE_MASK 0x0000003f
#define BG_INSTR_INTER_MAXLEVEL_MAX_LEVEL_VALUE_ALIGN 0
#define BG_INSTR_INTER_MAXLEVEL_MAX_LEVEL_VALUE_BITS 6
#define BG_INSTR_INTER_MAXLEVEL_MAX_LEVEL_VALUE_SHIFT 0
/***************************************************************************
*INTRA_LAST_MAXLEVEL - INTRA LAST MAX LEVEL
***************************************************************************/
/* BG_INSTR :: INTRA_LAST_MAXLEVEL :: reserved0 [31:06] */
#define BG_INSTR_INTRA_LAST_MAXLEVEL_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTRA_LAST_MAXLEVEL_reserved0_ALIGN 0
#define BG_INSTR_INTRA_LAST_MAXLEVEL_reserved0_BITS 26
#define BG_INSTR_INTRA_LAST_MAXLEVEL_reserved0_SHIFT 6
/* BG_INSTR :: INTRA_LAST_MAXLEVEL :: MAX_LEVEL_VALUE [05:00] */
#define BG_INSTR_INTRA_LAST_MAXLEVEL_MAX_LEVEL_VALUE_MASK 0x0000003f
#define BG_INSTR_INTRA_LAST_MAXLEVEL_MAX_LEVEL_VALUE_ALIGN 0
#define BG_INSTR_INTRA_LAST_MAXLEVEL_MAX_LEVEL_VALUE_BITS 6
#define BG_INSTR_INTRA_LAST_MAXLEVEL_MAX_LEVEL_VALUE_SHIFT 0
/***************************************************************************
*INTER_LAST_MAXLEVEL - INTER LAST MAX LEVEL
***************************************************************************/
/* BG_INSTR :: INTER_LAST_MAXLEVEL :: reserved0 [31:06] */
#define BG_INSTR_INTER_LAST_MAXLEVEL_reserved0_MASK 0xffffffc0
#define BG_INSTR_INTER_LAST_MAXLEVEL_reserved0_ALIGN 0
#define BG_INSTR_INTER_LAST_MAXLEVEL_reserved0_BITS 26
#define BG_INSTR_INTER_LAST_MAXLEVEL_reserved0_SHIFT 6
/* BG_INSTR :: INTER_LAST_MAXLEVEL :: MAX_LEVEL_VALUE [05:00] */
#define BG_INSTR_INTER_LAST_MAXLEVEL_MAX_LEVEL_VALUE_MASK 0x0000003f
#define BG_INSTR_INTER_LAST_MAXLEVEL_MAX_LEVEL_VALUE_ALIGN 0
#define BG_INSTR_INTER_LAST_MAXLEVEL_MAX_LEVEL_VALUE_BITS 6
#define BG_INSTR_INTER_LAST_MAXLEVEL_MAX_LEVEL_VALUE_SHIFT 0
/***************************************************************************
*INTRA_RUN_RAM_BASE - INTRA RUN RAM BASE
***************************************************************************/
/* BG_INSTR :: INTRA_RUN_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTRA_RUN_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTRA_RUN_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTRA_RUN_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTRA_RUN_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTRA_RUN_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTRA_RUN_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTRA_RUN_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTRA_RUN_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTRA_RUN_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTER_RUN_RAM_BASE - INTER RUN RAM BASE
***************************************************************************/
/* BG_INSTR :: INTER_RUN_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTER_RUN_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTER_RUN_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTER_RUN_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTER_RUN_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTER_RUN_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTER_RUN_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTER_RUN_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTER_RUN_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTER_RUN_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTRA_LAST_RUN_RAM_BASE - INTRA LAST RUN RAM BASE
***************************************************************************/
/* BG_INSTR :: INTRA_LAST_RUN_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTRA_LAST_RUN_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTRA_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTER_LAST_RUN_RAM_BASE - INTER LAST RUN RAM BASE
***************************************************************************/
/* BG_INSTR :: INTER_LAST_RUN_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTER_LAST_RUN_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTER_LAST_RUN_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTRA_LEVEL_RAM_BASE - INTRA LEVEL RAM BASE
***************************************************************************/
/* BG_INSTR :: INTRA_LEVEL_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTRA_LEVEL_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTRA_LEVEL_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTER_LEVEL_RAM_BASE - INTER LEVEL RAM BASE
***************************************************************************/
/* BG_INSTR :: INTER_LEVEL_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTER_LEVEL_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTER_LEVEL_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTER_LEVEL_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTER_LEVEL_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTER_LEVEL_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTER_LEVEL_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTER_LEVEL_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTER_LEVEL_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTER_LEVEL_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTRA_LAST_LEVEL_RAM_BASE - INTRA LAST LEVEL RAM BASE
***************************************************************************/
/* BG_INSTR :: INTRA_LAST_LEVEL_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTRA_LAST_LEVEL_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTRA_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*INTER_LAST_LEVEL_RAM_BASE - INTER LAST LEVEL RAM BASE
***************************************************************************/
/* BG_INSTR :: INTER_LAST_LEVEL_RAM_BASE :: reserved0 [31:09] */
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_reserved0_MASK 0xfffffe00
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_reserved0_ALIGN 0
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_reserved0_BITS 23
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_reserved0_SHIFT 9
/* BG_INSTR :: INTER_LAST_LEVEL_RAM_BASE :: RAM_BASE_VALUE [08:00] */
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_MASK 0x000001ff
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_ALIGN 0
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_BITS 9
#define BG_INSTR_INTER_LAST_LEVEL_RAM_BASE_RAM_BASE_VALUE_SHIFT 0
/***************************************************************************
*LAST_AC_LEVEL - LAST AC LEVEL
***************************************************************************/
/* BG_INSTR :: LAST_AC_LEVEL :: reserved0 [31:07] */
#define BG_INSTR_LAST_AC_LEVEL_reserved0_MASK 0xffffff80
#define BG_INSTR_LAST_AC_LEVEL_reserved0_ALIGN 0
#define BG_INSTR_LAST_AC_LEVEL_reserved0_BITS 25
#define BG_INSTR_LAST_AC_LEVEL_reserved0_SHIFT 7
/* BG_INSTR :: LAST_AC_LEVEL :: LAST_AC_LEVEL [06:00] */
#define BG_INSTR_LAST_AC_LEVEL_LAST_AC_LEVEL_MASK 0x0000007f
#define BG_INSTR_LAST_AC_LEVEL_LAST_AC_LEVEL_ALIGN 0
#define BG_INSTR_LAST_AC_LEVEL_LAST_AC_LEVEL_BITS 7
#define BG_INSTR_LAST_AC_LEVEL_LAST_AC_LEVEL_SHIFT 0
/***************************************************************************
*DSP_STOP_ADDR - DSP STOP ADDRESS
***************************************************************************/
/* BG_INSTR :: DSP_STOP_ADDR :: reserved0 [31:07] */
#define BG_INSTR_DSP_STOP_ADDR_reserved0_MASK 0xffffff80
#define BG_INSTR_DSP_STOP_ADDR_reserved0_ALIGN 0
#define BG_INSTR_DSP_STOP_ADDR_reserved0_BITS 25
#define BG_INSTR_DSP_STOP_ADDR_reserved0_SHIFT 7
/* BG_INSTR :: DSP_STOP_ADDR :: DSP_STOP_ADDR [06:00] */
#define BG_INSTR_DSP_STOP_ADDR_DSP_STOP_ADDR_MASK 0x0000007f
#define BG_INSTR_DSP_STOP_ADDR_DSP_STOP_ADDR_ALIGN 0
#define BG_INSTR_DSP_STOP_ADDR_DSP_STOP_ADDR_BITS 7
#define BG_INSTR_DSP_STOP_ADDR_DSP_STOP_ADDR_SHIFT 0
/***************************************************************************
*CBP_REG - CBP REG VALUE
***************************************************************************/
/* BG_INSTR :: CBP_REG :: reserved0 [31:06] */
#define BG_INSTR_CBP_REG_reserved0_MASK 0xffffffc0
#define BG_INSTR_CBP_REG_reserved0_ALIGN 0
#define BG_INSTR_CBP_REG_reserved0_BITS 26
#define BG_INSTR_CBP_REG_reserved0_SHIFT 6
/* BG_INSTR :: CBP_REG :: CBP_REG [05:00] */
#define BG_INSTR_CBP_REG_CBP_REG_MASK 0x0000003f
#define BG_INSTR_CBP_REG_CBP_REG_ALIGN 0
#define BG_INSTR_CBP_REG_CBP_REG_BITS 6
#define BG_INSTR_CBP_REG_CBP_REG_SHIFT 0
/***************************************************************************
*PUTBIT_COUNTER - PUTBIT COUNTER
***************************************************************************/
/* BG_INSTR :: PUTBIT_COUNTER :: BIT_COUNTER_VALUE [31:00] */
#define BG_INSTR_PUTBIT_COUNTER_BIT_COUNTER_VALUE_MASK 0xffffffff
#define BG_INSTR_PUTBIT_COUNTER_BIT_COUNTER_VALUE_ALIGN 0
#define BG_INSTR_PUTBIT_COUNTER_BIT_COUNTER_VALUE_BITS 32
#define BG_INSTR_PUTBIT_COUNTER_BIT_COUNTER_VALUE_SHIFT 0
/***************************************************************************
*INIT_COMMAND - INIT COMMAND
***************************************************************************/
/* BG_INSTR :: INIT_COMMAND :: reserved0 [31:01] */
#define BG_INSTR_INIT_COMMAND_reserved0_MASK 0xfffffffe
#define BG_INSTR_INIT_COMMAND_reserved0_ALIGN 0
#define BG_INSTR_INIT_COMMAND_reserved0_BITS 31
#define BG_INSTR_INIT_COMMAND_reserved0_SHIFT 1
/* BG_INSTR :: INIT_COMMAND :: INIT [00:00] */
#define BG_INSTR_INIT_COMMAND_INIT_MASK 0x00000001
#define BG_INSTR_INIT_COMMAND_INIT_ALIGN 0
#define BG_INSTR_INIT_COMMAND_INIT_BITS 1
#define BG_INSTR_INIT_COMMAND_INIT_SHIFT 0
/***************************************************************************
*OUT_POINTER - READ OUTPOINTER VALUE
***************************************************************************/
/* BG_INSTR :: OUT_POINTER :: reserved0 [31:06] */
#define BG_INSTR_OUT_POINTER_reserved0_MASK 0xffffffc0
#define BG_INSTR_OUT_POINTER_reserved0_ALIGN 0
#define BG_INSTR_OUT_POINTER_reserved0_BITS 26
#define BG_INSTR_OUT_POINTER_reserved0_SHIFT 6
/* BG_INSTR :: OUT_POINTER :: OUT_POINTER [05:00] */
#define BG_INSTR_OUT_POINTER_OUT_POINTER_MASK 0x0000003f
#define BG_INSTR_OUT_POINTER_OUT_POINTER_ALIGN 0
#define BG_INSTR_OUT_POINTER_OUT_POINTER_BITS 6
#define BG_INSTR_OUT_POINTER_OUT_POINTER_SHIFT 0
/***************************************************************************
*PUTBIT_10 - PUT BIT COMMAND
***************************************************************************/
/* BG_INSTR :: PUTBIT_10 :: reserved0 [31:16] */
#define BG_INSTR_PUTBIT_10_reserved0_MASK 0xffff0000
#define BG_INSTR_PUTBIT_10_reserved0_ALIGN 0
#define BG_INSTR_PUTBIT_10_reserved0_BITS 16
#define BG_INSTR_PUTBIT_10_reserved0_SHIFT 16
/* BG_INSTR :: PUTBIT_10 :: CLEN [15:10] */
#define BG_INSTR_PUTBIT_10_CLEN_MASK 0x0000fc00
#define BG_INSTR_PUTBIT_10_CLEN_ALIGN 0
#define BG_INSTR_PUTBIT_10_CLEN_BITS 6
#define BG_INSTR_PUTBIT_10_CLEN_SHIFT 10
/* BG_INSTR :: PUTBIT_10 :: CWORD [09:00] */
#define BG_INSTR_PUTBIT_10_CWORD_MASK 0x000003ff
#define BG_INSTR_PUTBIT_10_CWORD_ALIGN 0
#define BG_INSTR_PUTBIT_10_CWORD_BITS 10
#define BG_INSTR_PUTBIT_10_CWORD_SHIFT 0
/***************************************************************************
*PUTBIT_16 - PUT BIT COMMAND
***************************************************************************/
/* BG_INSTR :: PUTBIT_16 :: reserved0 [31:22] */
#define BG_INSTR_PUTBIT_16_reserved0_MASK 0xffc00000
#define BG_INSTR_PUTBIT_16_reserved0_ALIGN 0
#define BG_INSTR_PUTBIT_16_reserved0_BITS 10
#define BG_INSTR_PUTBIT_16_reserved0_SHIFT 22
/* BG_INSTR :: PUTBIT_16 :: CLEN [21:16] */
#define BG_INSTR_PUTBIT_16_CLEN_MASK 0x003f0000
#define BG_INSTR_PUTBIT_16_CLEN_ALIGN 0
#define BG_INSTR_PUTBIT_16_CLEN_BITS 6
#define BG_INSTR_PUTBIT_16_CLEN_SHIFT 16
/* BG_INSTR :: PUTBIT_16 :: CWORD [15:00] */
#define BG_INSTR_PUTBIT_16_CWORD_MASK 0x0000ffff
#define BG_INSTR_PUTBIT_16_CWORD_ALIGN 0
#define BG_INSTR_PUTBIT_16_CWORD_BITS 16
#define BG_INSTR_PUTBIT_16_CWORD_SHIFT 0
/***************************************************************************
*PUTAC - PUT AC
***************************************************************************/
/* BG_INSTR :: PUTAC :: reserved0 [31:09] */
#define BG_INSTR_PUTAC_reserved0_MASK 0xfffffe00
#define BG_INSTR_PUTAC_reserved0_ALIGN 0
#define BG_INSTR_PUTAC_reserved0_BITS 23
#define BG_INSTR_PUTAC_reserved0_SHIFT 9
/* BG_INSTR :: PUTAC :: DCT_RD_ADDRESS [08:00] */
#define BG_INSTR_PUTAC_DCT_RD_ADDRESS_MASK 0x000001ff
#define BG_INSTR_PUTAC_DCT_RD_ADDRESS_ALIGN 0
#define BG_INSTR_PUTAC_DCT_RD_ADDRESS_BITS 9
#define BG_INSTR_PUTAC_DCT_RD_ADDRESS_SHIFT 0
/***************************************************************************
*EXECSTATUS - EXEC STATUS
***************************************************************************/
/* BG_INSTR :: EXECSTATUS :: reserved0 [31:01] */
#define BG_INSTR_EXECSTATUS_reserved0_MASK 0xfffffffe
#define BG_INSTR_EXECSTATUS_reserved0_ALIGN 0
#define BG_INSTR_EXECSTATUS_reserved0_BITS 31
#define BG_INSTR_EXECSTATUS_reserved0_SHIFT 1
/* BG_INSTR :: EXECSTATUS :: EXEC_STATUS [00:00] */
#define BG_INSTR_EXECSTATUS_EXEC_STATUS_MASK 0x00000001
#define BG_INSTR_EXECSTATUS_EXEC_STATUS_ALIGN 0
#define BG_INSTR_EXECSTATUS_EXEC_STATUS_BITS 1
#define BG_INSTR_EXECSTATUS_EXEC_STATUS_SHIFT 0
/***************************************************************************
*REVISION_ID - Letter Box Generator Revision register
***************************************************************************/
/* BG_INSTR :: REVISION_ID :: reserved0 [31:08] */
#define BG_INSTR_REVISION_ID_reserved0_MASK 0xffffff00
#define BG_INSTR_REVISION_ID_reserved0_ALIGN 0
#define BG_INSTR_REVISION_ID_reserved0_BITS 24
#define BG_INSTR_REVISION_ID_reserved0_SHIFT 8
/* BG_INSTR :: REVISION_ID :: MAJOR [07:04] */
#define BG_INSTR_REVISION_ID_MAJOR_MASK 0x000000f0
#define BG_INSTR_REVISION_ID_MAJOR_ALIGN 0
#define BG_INSTR_REVISION_ID_MAJOR_BITS 4
#define BG_INSTR_REVISION_ID_MAJOR_SHIFT 4
/* BG_INSTR :: REVISION_ID :: MINOR [03:00] */
#define BG_INSTR_REVISION_ID_MINOR_MASK 0x0000000f
#define BG_INSTR_REVISION_ID_MINOR_ALIGN 0
#define BG_INSTR_REVISION_ID_MINOR_BITS 4
#define BG_INSTR_REVISION_ID_MINOR_SHIFT 0
#endif /* #ifndef BCM7043_A0_BG_INSTR_H__ */
/* End of File */

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bcm2708_chip/israel_dsp_registers.h Executable file
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bcm2708_chip/jpeg_top.h Executable file
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// This file was generated by the create_regs script
#define JP_BASE 0x7e005000
#define JP_APB_ID 0x4a504547
#define JP_CTRL HW_REGISTER_RW( 0x7e005000 )
#define JP_ICST HW_REGISTER_RW( 0x7e005004 )
#define JP_MCTRL HW_REGISTER_RW( 0x7e005008 )
#define JP_DCCTRL HW_REGISTER_RW( 0x7e00500c )
#define JP_CBA HW_REGISTER_RW( 0x7e005010 )
#define JP_NCB HW_REGISTER_RW( 0x7e005014 )
#define JP_SDA HW_REGISTER_RW( 0x7e005018 )
#define JP_NSB HW_REGISTER_RW( 0x7e00501c )
#define JP_SBO HW_REGISTER_RW( 0x7e005020 )
#define JP_MOP HW_REGISTER_RW( 0x7e005024 )
#define JP_HADDR HW_REGISTER_RW( 0x7e005028 )
#define JP_HWDATA HW_REGISTER_RW( 0x7e00502c )
#define JP_MADDR HW_REGISTER_RW( 0x7e005030 )
#define JP_MWDATA HW_REGISTER_RW( 0x7e005034 )
#define JP_OADDR HW_REGISTER_RW( 0x7e005038 )
#define JP_OWDATA HW_REGISTER_RW( 0x7e00503c )
#define JP_QADDR HW_REGISTER_RW( 0x7e005040 )
#define JP_QWDATA HW_REGISTER_RW( 0x7e005044 )
#define JP_QCTRL HW_REGISTER_RW( 0x7e005048 )
#define JP_C0BA HW_REGISTER_RW( 0x7e00504c )
#define JP_C1BA HW_REGISTER_RW( 0x7e005050 )
#define JP_C2BA HW_REGISTER_RW( 0x7e005054 )
#define JP_C0S HW_REGISTER_RW( 0x7e005058 )
#define JP_C1S HW_REGISTER_RW( 0x7e00505c )
#define JP_C2S HW_REGISTER_RW( 0x7e005060 )
#define JP_C0W HW_REGISTER_RW( 0x7e005064 )
#define JP_C1W HW_REGISTER_RW( 0x7e005068 )
#define JP_C2W HW_REGISTER_RW( 0x7e00506c )

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bcm2708_chip/l2_cache_ctrl.h Executable file
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// This file was generated by the create_regs script
#define L2_BASE 0x7ee01000
#define L2_APB_ID 0x4c324343
#define L2_CONT_OFF HW_REGISTER_RW( 0x7ee01000 )
#define L2_CONT_OFF_MASK 0x00ff0c3f
#define L2_CONT_OFF_WIDTH 24
#define L2_CONT_OFF_RESET 0000000000
#define L2_CONT_OFF_l2_flush_core_limit_BITS 23:20
#define L2_CONT_OFF_l2_flush_core_limit_SET 0x00f00000
#define L2_CONT_OFF_l2_flush_core_limit_CLR 0xff0fffff
#define L2_CONT_OFF_l2_flush_core_limit_MSB 23
#define L2_CONT_OFF_l2_flush_core_limit_LSB 20
#define L2_CONT_OFF_l2_flush_flush_limit_BITS 19:16
#define L2_CONT_OFF_l2_flush_flush_limit_SET 0x000f0000
#define L2_CONT_OFF_l2_flush_flush_limit_CLR 0xfff0ffff
#define L2_CONT_OFF_l2_flush_flush_limit_MSB 19
#define L2_CONT_OFF_l2_flush_flush_limit_LSB 16
#define L2_CONT_OFF_l2_standby_BITS 11:10
#define L2_CONT_OFF_l2_standby_SET 0x00000c00
#define L2_CONT_OFF_l2_standby_CLR 0xfffff3ff
#define L2_CONT_OFF_l2_standby_MSB 11
#define L2_CONT_OFF_l2_standby_LSB 10
#define L2_CONT_OFF_l2_enable_stats_BITS 5:5
#define L2_CONT_OFF_l2_enable_stats_SET 0x00000020
#define L2_CONT_OFF_l2_enable_stats_CLR 0xffffffdf
#define L2_CONT_OFF_l2_enable_stats_MSB 5
#define L2_CONT_OFF_l2_enable_stats_LSB 5
#define L2_CONT_OFF_l2_flush_mode_BITS 4:3
#define L2_CONT_OFF_l2_flush_mode_SET 0x00000018
#define L2_CONT_OFF_l2_flush_mode_CLR 0xffffffe7
#define L2_CONT_OFF_l2_flush_mode_MSB 4
#define L2_CONT_OFF_l2_flush_mode_LSB 3
#define L2_CONT_OFF_l2_flush_BITS 2:2
#define L2_CONT_OFF_l2_flush_SET 0x00000004
#define L2_CONT_OFF_l2_flush_CLR 0xfffffffb
#define L2_CONT_OFF_l2_flush_MSB 2
#define L2_CONT_OFF_l2_flush_LSB 2
#define L2_CONT_OFF_l2_no_wr_allocate_BITS 1:1
#define L2_CONT_OFF_l2_no_wr_allocate_SET 0x00000002
#define L2_CONT_OFF_l2_no_wr_allocate_CLR 0xfffffffd
#define L2_CONT_OFF_l2_no_wr_allocate_MSB 1
#define L2_CONT_OFF_l2_no_wr_allocate_LSB 1
#define L2_CONT_OFF_l2_disable_BITS 0:0
#define L2_CONT_OFF_l2_disable_SET 0x00000001
#define L2_CONT_OFF_l2_disable_CLR 0xfffffffe
#define L2_CONT_OFF_l2_disable_MSB 0
#define L2_CONT_OFF_l2_disable_LSB 0
#define L2_FLUSH_STA HW_REGISTER_RW( 0x7ee01004 )
#define L2_FLUSH_STA_MASK 0x0fffffe0
#define L2_FLUSH_STA_WIDTH 28
#define L2_FLUSH_STA_RESET 0000000000
#define L2_FLUSH_END HW_REGISTER_RW( 0x7ee01008 )
#define L2_FLUSH_END_MASK 0x0fffffe0
#define L2_FLUSH_END_WIDTH 28
#define L2_FLUSH_END_RESET 0x0fffffe0
#define L2_L2_ALIAS_EXCEPTION HW_REGISTER_RW( 0x7ee01080 )
#define L2_L2_ALIAS_EXCEPTION_RESET 0000000000
#define L2_L2_ALIAS_EXCEPTION_ID HW_REGISTER_RO( 0x7ee01084 )
#define L2_L2_ALIAS_EXCEPTION_ID_RESET 0000000000
#define L2_L2_ALIAS_EXCEPTION_ADDR HW_REGISTER_RO( 0x7ee01088 )
#define L2_L2_ALIAS_EXCEPTION_ADDR_RESET 0000000000
#define L2_RD_HITS HW_REGISTER_RW( 0x7ee01100 )
#define L2_RD_HITS_MASK 0xffffffff
#define L2_RD_HITS_WIDTH 32
#define L2_RD_MISSES HW_REGISTER_RO( 0x7ee01104 )
#define L2_RD_MISSES_MASK 0xffffffff
#define L2_RD_MISSES_WIDTH 32
#define L2_WR_HITS HW_REGISTER_RO( 0x7ee01108 )
#define L2_WR_HITS_MASK 0xffffffff
#define L2_WR_HITS_WIDTH 32
#define L2_WR_MISSES HW_REGISTER_RO( 0x7ee0110c )
#define L2_WR_MISSES_MASK 0xffffffff
#define L2_WR_MISSES_WIDTH 32
#define L2_WR_BACKS HW_REGISTER_RO( 0x7ee01110 )
#define L2_WR_BACKS_MASK 0xffffffff
#define L2_WR_BACKS_WIDTH 32
#define L2_IN_FLIGHT HW_REGISTER_RO( 0x7ee01114 )
#define L2_IN_FLIGHT_MASK 0x0000000f
#define L2_IN_FLIGHT_WIDTH 4
#define L2_STALLS HW_REGISTER_RO( 0x7ee0111c )
#define L2_STALLS_MASK 0xffffffff
#define L2_STALLS_WIDTH 32
#define L2_TAG_STALLS HW_REGISTER_RO( 0x7ee01120 )
#define L2_TAG_STALLS_MASK 0xffffffff
#define L2_TAG_STALLS_WIDTH 32
#define L2_SD_STALLS HW_REGISTER_RO( 0x7ee01124 )
#define L2_SD_STALLS_MASK 0xffffffff
#define L2_SD_STALLS_WIDTH 32

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bcm2708_chip/mphi.h Executable file
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// This file was generated by the create_regs script
#define MPHI_BASE 0x7e006000
#define MPHI_APB_ID 0x6d706869
#define MPHI_C0INDDA HW_REGISTER_RW( 0x7e006000 )
#define MPHI_C0INDDA_MASK 0xffffffff
#define MPHI_C0INDDA_WIDTH 32
#define MPHI_C0INDDA_START_BITS 31:0
#define MPHI_C0INDDA_START_SET 0xffffffff
#define MPHI_C0INDDA_START_CLR 0x00000000
#define MPHI_C0INDDA_START_MSB 31
#define MPHI_C0INDDA_START_LSB 0
#define MPHI_C0INDDA_START_RESET 0x0
#define MPHI_C0INDDB HW_REGISTER_RW( 0x7e006004 )
#define MPHI_C0INDDB_MASK 0xffffffff
#define MPHI_C0INDDB_WIDTH 32
#define MPHI_C0INDDB_MORUN_BITS 31:31
#define MPHI_C0INDDB_MORUN_SET 0x80000000
#define MPHI_C0INDDB_MORUN_CLR 0x7fffffff
#define MPHI_C0INDDB_MORUN_MSB 31
#define MPHI_C0INDDB_MORUN_LSB 31
#define MPHI_C0INDDB_MORUN_RESET 0x0
#define MPHI_C0INDDB_MENDINT_BITS 30:30
#define MPHI_C0INDDB_MENDINT_SET 0x40000000
#define MPHI_C0INDDB_MENDINT_CLR 0xbfffffff
#define MPHI_C0INDDB_MENDINT_MSB 30
#define MPHI_C0INDDB_MENDINT_LSB 30
#define MPHI_C0INDDB_MENDINT_RESET 0x0
#define MPHI_C0INDDB_TENDINT_BITS 29:29
#define MPHI_C0INDDB_TENDINT_SET 0x20000000
#define MPHI_C0INDDB_TENDINT_CLR 0xdfffffff
#define MPHI_C0INDDB_TENDINT_MSB 29
#define MPHI_C0INDDB_TENDINT_LSB 29
#define MPHI_C0INDDB_TENDINT_RESET 0x0
#define MPHI_C0INDDB_MTERM_BITS 28:28
#define MPHI_C0INDDB_MTERM_SET 0x10000000
#define MPHI_C0INDDB_MTERM_CLR 0xefffffff
#define MPHI_C0INDDB_MTERM_MSB 28
#define MPHI_C0INDDB_MTERM_LSB 28
#define MPHI_C0INDDB_MTERM_RESET 0x0
#define MPHI_C0INDDB_HANDLE_BITS 27:20
#define MPHI_C0INDDB_HANDLE_SET 0x0ff00000
#define MPHI_C0INDDB_HANDLE_CLR 0xf00fffff
#define MPHI_C0INDDB_HANDLE_MSB 27
#define MPHI_C0INDDB_HANDLE_LSB 20
#define MPHI_C0INDDB_HANDLE_RESET 0x0
#define MPHI_C0INDDB_LENGTH_BITS 19:0
#define MPHI_C0INDDB_LENGTH_SET 0x000fffff
#define MPHI_C0INDDB_LENGTH_CLR 0xfff00000
#define MPHI_C0INDDB_LENGTH_MSB 19
#define MPHI_C0INDDB_LENGTH_LSB 0
#define MPHI_C0INDDB_LENGTH_RESET 0x0
#define MPHI_C1INDDA HW_REGISTER_RW( 0x7e006008 )
#define MPHI_C1INDDA_MASK 0xffffffff
#define MPHI_C1INDDA_WIDTH 32
#define MPHI_C1INDDA_START_BITS 31:0
#define MPHI_C1INDDA_START_SET 0xffffffff
#define MPHI_C1INDDA_START_CLR 0x00000000
#define MPHI_C1INDDA_START_MSB 31
#define MPHI_C1INDDA_START_LSB 0
#define MPHI_C1INDDA_START_RESET 0x0
#define MPHI_C1INDDB HW_REGISTER_RW( 0x7e00600c )
#define MPHI_C1INDDB_MASK 0xffffffff
#define MPHI_C1INDDB_WIDTH 32
#define MPHI_C1INDDB_MORUN_BITS 31:31
#define MPHI_C1INDDB_MORUN_SET 0x80000000
#define MPHI_C1INDDB_MORUN_CLR 0x7fffffff
#define MPHI_C1INDDB_MORUN_MSB 31
#define MPHI_C1INDDB_MORUN_LSB 31
#define MPHI_C1INDDB_MORUN_RESET 0x0
#define MPHI_C1INDDB_MENDINT_BITS 30:30
#define MPHI_C1INDDB_MENDINT_SET 0x40000000
#define MPHI_C1INDDB_MENDINT_CLR 0xbfffffff
#define MPHI_C1INDDB_MENDINT_MSB 30
#define MPHI_C1INDDB_MENDINT_LSB 30
#define MPHI_C1INDDB_MENDINT_RESET 0x0
#define MPHI_C1INDDB_TENDINT_BITS 29:29
#define MPHI_C1INDDB_TENDINT_SET 0x20000000
#define MPHI_C1INDDB_TENDINT_CLR 0xdfffffff
#define MPHI_C1INDDB_TENDINT_MSB 29
#define MPHI_C1INDDB_TENDINT_LSB 29
#define MPHI_C1INDDB_TENDINT_RESET 0x0
#define MPHI_C1INDDB_MTERM_BITS 28:28
#define MPHI_C1INDDB_MTERM_SET 0x10000000
#define MPHI_C1INDDB_MTERM_CLR 0xefffffff
#define MPHI_C1INDDB_MTERM_MSB 28
#define MPHI_C1INDDB_MTERM_LSB 28
#define MPHI_C1INDDB_MTERM_RESET 0x0
#define MPHI_C1INDDB_HANDLE_BITS 27:20
#define MPHI_C1INDDB_HANDLE_SET 0x0ff00000
#define MPHI_C1INDDB_HANDLE_CLR 0xf00fffff
#define MPHI_C1INDDB_HANDLE_MSB 27
#define MPHI_C1INDDB_HANDLE_LSB 20
#define MPHI_C1INDDB_HANDLE_RESET 0x0
#define MPHI_C1INDDB_LENGTH_BITS 19:0
#define MPHI_C1INDDB_LENGTH_SET 0x000fffff
#define MPHI_C1INDDB_LENGTH_CLR 0xfff00000
#define MPHI_C1INDDB_LENGTH_MSB 19
#define MPHI_C1INDDB_LENGTH_LSB 0
#define MPHI_C1INDDB_LENGTH_RESET 0x0
#define MPHI_C0INDS HW_REGISTER_RW( 0x7e006010 )
#define MPHI_C0INDS_MASK 0xdfffffff
#define MPHI_C0INDS_WIDTH 32
#define MPHI_C0INDS_DISCARD_BITS 31:31
#define MPHI_C0INDS_DISCARD_SET 0x80000000
#define MPHI_C0INDS_DISCARD_CLR 0x7fffffff
#define MPHI_C0INDS_DISCARD_MSB 31
#define MPHI_C0INDS_DISCARD_LSB 31
#define MPHI_C0INDS_DISCARD_RESET 0x0
#define MPHI_C0INDS_VALID_BITS 30:30
#define MPHI_C0INDS_VALID_SET 0x40000000
#define MPHI_C0INDS_VALID_CLR 0xbfffffff
#define MPHI_C0INDS_VALID_MSB 30
#define MPHI_C0INDS_VALID_LSB 30
#define MPHI_C0INDS_VALID_RESET 0x0
#define MPHI_C0INDS_HANDLE_BITS 28:21
#define MPHI_C0INDS_HANDLE_SET 0x1fe00000
#define MPHI_C0INDS_HANDLE_CLR 0xe01fffff
#define MPHI_C0INDS_HANDLE_MSB 28
#define MPHI_C0INDS_HANDLE_LSB 21
#define MPHI_C0INDS_HANDLE_RESET 0x0
#define MPHI_C0INDS_WORDS_BITS 20:0
#define MPHI_C0INDS_WORDS_SET 0x001fffff
#define MPHI_C0INDS_WORDS_CLR 0xffe00000
#define MPHI_C0INDS_WORDS_MSB 20
#define MPHI_C0INDS_WORDS_LSB 0
#define MPHI_C0INDS_WORDS_RESET 0x0
#define MPHI_C1INDS HW_REGISTER_RW( 0x7e006014 )
#define MPHI_C1INDS_MASK 0xdfffffff
#define MPHI_C1INDS_WIDTH 32
#define MPHI_C1INDS_DISCARD_BITS 31:31
#define MPHI_C1INDS_DISCARD_SET 0x80000000
#define MPHI_C1INDS_DISCARD_CLR 0x7fffffff
#define MPHI_C1INDS_DISCARD_MSB 31
#define MPHI_C1INDS_DISCARD_LSB 31
#define MPHI_C1INDS_DISCARD_RESET 0x0
#define MPHI_C1INDS_VALID_BITS 30:30
#define MPHI_C1INDS_VALID_SET 0x40000000
#define MPHI_C1INDS_VALID_CLR 0xbfffffff
#define MPHI_C1INDS_VALID_MSB 30
#define MPHI_C1INDS_VALID_LSB 30
#define MPHI_C1INDS_VALID_RESET 0x0
#define MPHI_C1INDS_HANDLE_BITS 28:21
#define MPHI_C1INDS_HANDLE_SET 0x1fe00000
#define MPHI_C1INDS_HANDLE_CLR 0xe01fffff
#define MPHI_C1INDS_HANDLE_MSB 28
#define MPHI_C1INDS_HANDLE_LSB 21
#define MPHI_C1INDS_HANDLE_RESET 0x0
#define MPHI_C1INDS_WORDS_BITS 20:0
#define MPHI_C1INDS_WORDS_SET 0x001fffff
#define MPHI_C1INDS_WORDS_CLR 0xffe00000
#define MPHI_C1INDS_WORDS_MSB 20
#define MPHI_C1INDS_WORDS_LSB 0
#define MPHI_C1INDS_WORDS_RESET 0x0
#define MPHI_C0INDCF HW_REGISTER_RW( 0x7e006018 )
#define MPHI_C0INDCF_MASK 0xffffffff
#define MPHI_C0INDCF_WIDTH 32
#define MPHI_C0INDCF_EMPTY_BITS 31:31
#define MPHI_C0INDCF_EMPTY_SET 0x80000000
#define MPHI_C0INDCF_EMPTY_CLR 0x7fffffff
#define MPHI_C0INDCF_EMPTY_MSB 31
#define MPHI_C0INDCF_EMPTY_LSB 31
#define MPHI_C0INDCF_EMPTY_RESET 0x0
#define MPHI_C0INDCF_LENERR_BITS 30:30
#define MPHI_C0INDCF_LENERR_SET 0x40000000
#define MPHI_C0INDCF_LENERR_CLR 0xbfffffff
#define MPHI_C0INDCF_LENERR_MSB 30
#define MPHI_C0INDCF_LENERR_LSB 30
#define MPHI_C0INDCF_LENERR_RESET 0x0
#define MPHI_C0INDCF_ORUN_BITS 29:29
#define MPHI_C0INDCF_ORUN_SET 0x20000000
#define MPHI_C0INDCF_ORUN_CLR 0xdfffffff
#define MPHI_C0INDCF_ORUN_MSB 29
#define MPHI_C0INDCF_ORUN_LSB 29
#define MPHI_C0INDCF_ORUN_RESET 0x0
#define MPHI_C0INDCF_MTERM_BITS 28:28
#define MPHI_C0INDCF_MTERM_SET 0x10000000
#define MPHI_C0INDCF_MTERM_CLR 0xefffffff
#define MPHI_C0INDCF_MTERM_MSB 28
#define MPHI_C0INDCF_MTERM_LSB 28
#define MPHI_C0INDCF_MTERM_RESET 0x0
#define MPHI_C0INDCF_HANDLE_BITS 27:20
#define MPHI_C0INDCF_HANDLE_SET 0x0ff00000
#define MPHI_C0INDCF_HANDLE_CLR 0xf00fffff
#define MPHI_C0INDCF_HANDLE_MSB 27
#define MPHI_C0INDCF_HANDLE_LSB 20
#define MPHI_C0INDCF_HANDLE_RESET 0x0
#define MPHI_C0INDCF_LENGTH_BITS 19:0
#define MPHI_C0INDCF_LENGTH_SET 0x000fffff
#define MPHI_C0INDCF_LENGTH_CLR 0xfff00000
#define MPHI_C0INDCF_LENGTH_MSB 19
#define MPHI_C0INDCF_LENGTH_LSB 0
#define MPHI_C0INDCF_LENGTH_RESET 0x0
#define MPHI_C1INDCF HW_REGISTER_RW( 0x7e00601c )
#define MPHI_C1INDCF_MASK 0xffffffff
#define MPHI_C1INDCF_WIDTH 32
#define MPHI_C1INDCF_EMPTY_BITS 31:31
#define MPHI_C1INDCF_EMPTY_SET 0x80000000
#define MPHI_C1INDCF_EMPTY_CLR 0x7fffffff
#define MPHI_C1INDCF_EMPTY_MSB 31
#define MPHI_C1INDCF_EMPTY_LSB 31
#define MPHI_C1INDCF_EMPTY_RESET 0x0
#define MPHI_C1INDCF_LENERR_BITS 30:30
#define MPHI_C1INDCF_LENERR_SET 0x40000000
#define MPHI_C1INDCF_LENERR_CLR 0xbfffffff
#define MPHI_C1INDCF_LENERR_MSB 30
#define MPHI_C1INDCF_LENERR_LSB 30
#define MPHI_C1INDCF_LENERR_RESET 0x0
#define MPHI_C1INDCF_ORUN_BITS 29:29
#define MPHI_C1INDCF_ORUN_SET 0x20000000
#define MPHI_C1INDCF_ORUN_CLR 0xdfffffff
#define MPHI_C1INDCF_ORUN_MSB 29
#define MPHI_C1INDCF_ORUN_LSB 29
#define MPHI_C1INDCF_ORUN_RESET 0x0
#define MPHI_C1INDCF_MTERM_BITS 28:28
#define MPHI_C1INDCF_MTERM_SET 0x10000000
#define MPHI_C1INDCF_MTERM_CLR 0xefffffff
#define MPHI_C1INDCF_MTERM_MSB 28
#define MPHI_C1INDCF_MTERM_LSB 28
#define MPHI_C1INDCF_MTERM_RESET 0x0
#define MPHI_C1INDCF_HANDLE_BITS 27:20
#define MPHI_C1INDCF_HANDLE_SET 0x0ff00000
#define MPHI_C1INDCF_HANDLE_CLR 0xf00fffff
#define MPHI_C1INDCF_HANDLE_MSB 27
#define MPHI_C1INDCF_HANDLE_LSB 20
#define MPHI_C1INDCF_HANDLE_RESET 0x0
#define MPHI_C1INDCF_LENGTH_BITS 19:0
#define MPHI_C1INDCF_LENGTH_SET 0x000fffff
#define MPHI_C1INDCF_LENGTH_CLR 0xfff00000
#define MPHI_C1INDCF_LENGTH_MSB 19
#define MPHI_C1INDCF_LENGTH_LSB 0
#define MPHI_C1INDCF_LENGTH_RESET 0x0
#define MPHI_C0INDFS HW_REGISTER_RW( 0x7e006020 )
#define MPHI_C0INDFS_MASK 0xffffffff
#define MPHI_C0INDFS_WIDTH 32
#define MPHI_C0INDFS_CFIFOLVL_BITS 31:16
#define MPHI_C0INDFS_CFIFOLVL_SET 0xffff0000
#define MPHI_C0INDFS_CFIFOLVL_CLR 0x0000ffff
#define MPHI_C0INDFS_CFIFOLVL_MSB 31
#define MPHI_C0INDFS_CFIFOLVL_LSB 16
#define MPHI_C0INDFS_CFIFOLVL_RESET 0x0
#define MPHI_C0INDFS_DFIFOLVL_BITS 15:0
#define MPHI_C0INDFS_DFIFOLVL_SET 0x0000ffff
#define MPHI_C0INDFS_DFIFOLVL_CLR 0xffff0000
#define MPHI_C0INDFS_DFIFOLVL_MSB 15
#define MPHI_C0INDFS_DFIFOLVL_LSB 0
#define MPHI_C0INDFS_DFIFOLVL_RESET 0x0
#define MPHI_C1INDFS HW_REGISTER_RW( 0x7e006024 )
#define MPHI_C1INDFS_MASK 0xffffffff
#define MPHI_C1INDFS_WIDTH 32
#define MPHI_C1INDFS_CFIFOLVL_BITS 31:16
#define MPHI_C1INDFS_CFIFOLVL_SET 0xffff0000
#define MPHI_C1INDFS_CFIFOLVL_CLR 0x0000ffff
#define MPHI_C1INDFS_CFIFOLVL_MSB 31
#define MPHI_C1INDFS_CFIFOLVL_LSB 16
#define MPHI_C1INDFS_CFIFOLVL_RESET 0x0
#define MPHI_C1INDFS_DFIFOLVL_BITS 15:0
#define MPHI_C1INDFS_DFIFOLVL_SET 0x0000ffff
#define MPHI_C1INDFS_DFIFOLVL_CLR 0xffff0000
#define MPHI_C1INDFS_DFIFOLVL_MSB 15
#define MPHI_C1INDFS_DFIFOLVL_LSB 0
#define MPHI_C1INDFS_DFIFOLVL_RESET 0x0
#define MPHI_OUTDDA HW_REGISTER_RW( 0x7e006028 )
#define MPHI_OUTDDA_MASK 0xffffffff
#define MPHI_OUTDDA_WIDTH 32
#define MPHI_OUTDDA_START_BITS 31:0
#define MPHI_OUTDDA_START_SET 0xffffffff
#define MPHI_OUTDDA_START_CLR 0x00000000
#define MPHI_OUTDDA_START_MSB 31
#define MPHI_OUTDDA_START_LSB 0
#define MPHI_OUTDDA_START_RESET 0x0
#define MPHI_OUTDDB HW_REGISTER_RW( 0x7e00602c )
#define MPHI_OUTDDB_MASK 0x3fffffff
#define MPHI_OUTDDB_WIDTH 30
#define MPHI_OUTDDB_TENDINT_BITS 29:29
#define MPHI_OUTDDB_TENDINT_SET 0x20000000
#define MPHI_OUTDDB_TENDINT_CLR 0xdfffffff
#define MPHI_OUTDDB_TENDINT_MSB 29
#define MPHI_OUTDDB_TENDINT_LSB 29
#define MPHI_OUTDDB_TENDINT_RESET 0x0
#define MPHI_OUTDDB_CHANNEL_BITS 28:28
#define MPHI_OUTDDB_CHANNEL_SET 0x10000000
#define MPHI_OUTDDB_CHANNEL_CLR 0xefffffff
#define MPHI_OUTDDB_CHANNEL_MSB 28
#define MPHI_OUTDDB_CHANNEL_LSB 28
#define MPHI_OUTDDB_CHANNEL_RESET 0x0
#define MPHI_OUTDDB_HANDLE_BITS 27:20
#define MPHI_OUTDDB_HANDLE_SET 0x0ff00000
#define MPHI_OUTDDB_HANDLE_CLR 0xf00fffff
#define MPHI_OUTDDB_HANDLE_MSB 27
#define MPHI_OUTDDB_HANDLE_LSB 20
#define MPHI_OUTDDB_HANDLE_RESET 0x0
#define MPHI_OUTDDB_LENGTH_BITS 19:0
#define MPHI_OUTDDB_LENGTH_SET 0x000fffff
#define MPHI_OUTDDB_LENGTH_CLR 0xfff00000
#define MPHI_OUTDDB_LENGTH_MSB 19
#define MPHI_OUTDDB_LENGTH_LSB 0
#define MPHI_OUTDDB_LENGTH_RESET 0x0
#define MPHI_OUTDS HW_REGISTER_RW( 0x7e006030 )
#define MPHI_OUTDS_MASK 0x5fffffff
#define MPHI_OUTDS_WIDTH 31
#define MPHI_OUTDS_VALID_BITS 30:30
#define MPHI_OUTDS_VALID_SET 0x40000000
#define MPHI_OUTDS_VALID_CLR 0xbfffffff
#define MPHI_OUTDS_VALID_MSB 30
#define MPHI_OUTDS_VALID_LSB 30
#define MPHI_OUTDS_VALID_RESET 0x0
#define MPHI_OUTDS_HANDLE_BITS 28:21
#define MPHI_OUTDS_HANDLE_SET 0x1fe00000
#define MPHI_OUTDS_HANDLE_CLR 0xe01fffff
#define MPHI_OUTDS_HANDLE_MSB 28
#define MPHI_OUTDS_HANDLE_LSB 21
#define MPHI_OUTDS_HANDLE_RESET 0x0
#define MPHI_OUTDS_WORDS_BITS 20:0
#define MPHI_OUTDS_WORDS_SET 0x001fffff
#define MPHI_OUTDS_WORDS_CLR 0xffe00000
#define MPHI_OUTDS_WORDS_MSB 20
#define MPHI_OUTDS_WORDS_LSB 0
#define MPHI_OUTDS_WORDS_RESET 0x0
#define MPHI_OUTDFS HW_REGISTER_RW( 0x7e006034 )
#define MPHI_OUTDFS_MASK 0xffffffff
#define MPHI_OUTDFS_WIDTH 32
#define MPHI_OUTDFS_DFIFOLVL_BITS 15:0
#define MPHI_OUTDFS_DFIFOLVL_SET 0x0000ffff
#define MPHI_OUTDFS_DFIFOLVL_CLR 0xffff0000
#define MPHI_OUTDFS_DFIFOLVL_MSB 15
#define MPHI_OUTDFS_DFIFOLVL_LSB 0
#define MPHI_OUTDFS_DFIFOLVL_RESET 0x0
#define MPHI_MINFS HW_REGISTER_RW( 0x7e006038 )
#define MPHI_MINFS_MASK 0xbfffffff
#define MPHI_MINFS_WIDTH 32
#define MPHI_MINFS_OFLOW_BITS 31:31
#define MPHI_MINFS_OFLOW_SET 0x80000000
#define MPHI_MINFS_OFLOW_CLR 0x7fffffff
#define MPHI_MINFS_OFLOW_MSB 31
#define MPHI_MINFS_OFLOW_LSB 31
#define MPHI_MINFS_OFLOW_RESET 0x0
#define MPHI_MINFS_RPTR_BITS 29:20
#define MPHI_MINFS_RPTR_SET 0x3ff00000
#define MPHI_MINFS_RPTR_CLR 0xc00fffff
#define MPHI_MINFS_RPTR_MSB 29
#define MPHI_MINFS_RPTR_LSB 20
#define MPHI_MINFS_RPTR_RESET 0x0
#define MPHI_MINFS_WPTR_BITS 19:10
#define MPHI_MINFS_WPTR_SET 0x000ffc00
#define MPHI_MINFS_WPTR_CLR 0xfff003ff
#define MPHI_MINFS_WPTR_MSB 19
#define MPHI_MINFS_WPTR_LSB 10
#define MPHI_MINFS_WPTR_RESET 0x0
#define MPHI_MINFS_LEVEL_BITS 9:0
#define MPHI_MINFS_LEVEL_SET 0x000003ff
#define MPHI_MINFS_LEVEL_CLR 0xfffffc00
#define MPHI_MINFS_LEVEL_MSB 9
#define MPHI_MINFS_LEVEL_LSB 0
#define MPHI_MINFS_LEVEL_RESET 0x0
#define MPHI_MOUTFS HW_REGISTER_RW( 0x7e00603c )
#define MPHI_MOUTFS_MASK 0xbfffffff
#define MPHI_MOUTFS_WIDTH 32
#define MPHI_MOUTFS_UFLOW_BITS 31:31
#define MPHI_MOUTFS_UFLOW_SET 0x80000000
#define MPHI_MOUTFS_UFLOW_CLR 0x7fffffff
#define MPHI_MOUTFS_UFLOW_MSB 31
#define MPHI_MOUTFS_UFLOW_LSB 31
#define MPHI_MOUTFS_UFLOW_RESET 0x0
#define MPHI_MOUTFS_RPTR_BITS 29:20
#define MPHI_MOUTFS_RPTR_SET 0x3ff00000
#define MPHI_MOUTFS_RPTR_CLR 0xc00fffff
#define MPHI_MOUTFS_RPTR_MSB 29
#define MPHI_MOUTFS_RPTR_LSB 20
#define MPHI_MOUTFS_RPTR_RESET 0x0
#define MPHI_MOUTFS_WPTR_BITS 19:10
#define MPHI_MOUTFS_WPTR_SET 0x000ffc00
#define MPHI_MOUTFS_WPTR_CLR 0xfff003ff
#define MPHI_MOUTFS_WPTR_MSB 19
#define MPHI_MOUTFS_WPTR_LSB 10
#define MPHI_MOUTFS_WPTR_RESET 0x0
#define MPHI_MOUTFS_LEVEL_BITS 9:0
#define MPHI_MOUTFS_LEVEL_SET 0x000003ff
#define MPHI_MOUTFS_LEVEL_CLR 0xfffffc00
#define MPHI_MOUTFS_LEVEL_MSB 9
#define MPHI_MOUTFS_LEVEL_LSB 0
#define MPHI_MOUTFS_LEVEL_RESET 0x0
#define MPHI_AXIPRIV HW_REGISTER_RW( 0x7e006040 )
#define MPHI_AXIPRIV_MASK 0x00000177
#define MPHI_AXIPRIV_WIDTH 9
#define MPHI_AXIPRIV_HSPECEN_BITS 8:8
#define MPHI_AXIPRIV_HSPECEN_SET 0x00000100
#define MPHI_AXIPRIV_HSPECEN_CLR 0xfffffeff
#define MPHI_AXIPRIV_HSPECEN_MSB 8
#define MPHI_AXIPRIV_HSPECEN_LSB 8
#define MPHI_AXIPRIV_HSPECEN_RESET 0x0
#define MPHI_AXIPRIV_RXPROT_BITS 6:4
#define MPHI_AXIPRIV_RXPROT_SET 0x00000070
#define MPHI_AXIPRIV_RXPROT_CLR 0xffffff8f
#define MPHI_AXIPRIV_RXPROT_MSB 6
#define MPHI_AXIPRIV_RXPROT_LSB 4
#define MPHI_AXIPRIV_RXPROT_RESET 0x2
#define MPHI_AXIPRIV_TXPROT_BITS 2:0
#define MPHI_AXIPRIV_TXPROT_SET 0x00000007
#define MPHI_AXIPRIV_TXPROT_CLR 0xfffffff8
#define MPHI_AXIPRIV_TXPROT_MSB 2
#define MPHI_AXIPRIV_TXPROT_LSB 0
#define MPHI_AXIPRIV_TXPROT_RESET 0x2
#define MPHI_RXAXICFG HW_REGISTER_RW( 0x7e006044 )
#define MPHI_RXAXICFG_MASK 0x0001ffff
#define MPHI_RXAXICFG_WIDTH 17
#define MPHI_RXAXICFG_INTHRESH_BITS 16:8
#define MPHI_RXAXICFG_INTHRESH_SET 0x0001ff00
#define MPHI_RXAXICFG_INTHRESH_CLR 0xfffe00ff
#define MPHI_RXAXICFG_INTHRESH_MSB 16
#define MPHI_RXAXICFG_INTHRESH_LSB 8
#define MPHI_RXAXICFG_INTHRESH_RESET 0x0
#define MPHI_RXAXICFG_RXPPRIO_BITS 7:4
#define MPHI_RXAXICFG_RXPPRIO_SET 0x000000f0
#define MPHI_RXAXICFG_RXPPRIO_CLR 0xffffff0f
#define MPHI_RXAXICFG_RXPPRIO_MSB 7
#define MPHI_RXAXICFG_RXPPRIO_LSB 4
#define MPHI_RXAXICFG_RXPPRIO_RESET 0x0
#define MPHI_RXAXICFG_RXNPRIO_BITS 3:0
#define MPHI_RXAXICFG_RXNPRIO_SET 0x0000000f
#define MPHI_RXAXICFG_RXNPRIO_CLR 0xfffffff0
#define MPHI_RXAXICFG_RXNPRIO_MSB 3
#define MPHI_RXAXICFG_RXNPRIO_LSB 0
#define MPHI_RXAXICFG_RXNPRIO_RESET 0x0
#define MPHI_TXAXICFG HW_REGISTER_RW( 0x7e006048 )
#define MPHI_TXAXICFG_MASK 0x0001ffff
#define MPHI_TXAXICFG_WIDTH 17
#define MPHI_TXAXICFG_INTHRESH_BITS 16:8
#define MPHI_TXAXICFG_INTHRESH_SET 0x0001ff00
#define MPHI_TXAXICFG_INTHRESH_CLR 0xfffe00ff
#define MPHI_TXAXICFG_INTHRESH_MSB 16
#define MPHI_TXAXICFG_INTHRESH_LSB 8
#define MPHI_TXAXICFG_INTHRESH_RESET 0x0
#define MPHI_TXAXICFG_TXPPRIO_BITS 7:4
#define MPHI_TXAXICFG_TXPPRIO_SET 0x000000f0
#define MPHI_TXAXICFG_TXPPRIO_CLR 0xffffff0f
#define MPHI_TXAXICFG_TXPPRIO_MSB 7
#define MPHI_TXAXICFG_TXPPRIO_LSB 4
#define MPHI_TXAXICFG_TXPPRIO_RESET 0x0
#define MPHI_TXAXICFG_TXNPRIO_BITS 3:0
#define MPHI_TXAXICFG_TXNPRIO_SET 0x0000000f
#define MPHI_TXAXICFG_TXNPRIO_CLR 0xfffffff0
#define MPHI_TXAXICFG_TXNPRIO_MSB 3
#define MPHI_TXAXICFG_TXNPRIO_LSB 0
#define MPHI_TXAXICFG_TXNPRIO_RESET 0x0
#define MPHI_CTRL HW_REGISTER_RW( 0x7e00604c )
#define MPHI_CTRL_MASK 0x88031111
#define MPHI_CTRL_WIDTH 32
#define MPHI_CTRL_ENABLE_BITS 31:31
#define MPHI_CTRL_ENABLE_SET 0x80000000
#define MPHI_CTRL_ENABLE_CLR 0x7fffffff
#define MPHI_CTRL_ENABLE_MSB 31
#define MPHI_CTRL_ENABLE_LSB 31
#define MPHI_CTRL_ENABLE_RESET 0x0
#define MPHI_CTRL_STBY_BITS 27:27
#define MPHI_CTRL_STBY_SET 0x08000000
#define MPHI_CTRL_STBY_CLR 0xf7ffffff
#define MPHI_CTRL_STBY_MSB 27
#define MPHI_CTRL_STBY_LSB 27
#define MPHI_CTRL_STBY_RESET 0x1
#define MPHI_CTRL_SOFT_RST_DNE_BITS 17:17
#define MPHI_CTRL_SOFT_RST_DNE_SET 0x00020000
#define MPHI_CTRL_SOFT_RST_DNE_CLR 0xfffdffff
#define MPHI_CTRL_SOFT_RST_DNE_MSB 17
#define MPHI_CTRL_SOFT_RST_DNE_LSB 17
#define MPHI_CTRL_SOFT_RST_DNE_RESET 0x0
#define MPHI_CTRL_REQ_SOFT_RST_BITS 16:16
#define MPHI_CTRL_REQ_SOFT_RST_SET 0x00010000
#define MPHI_CTRL_REQ_SOFT_RST_CLR 0xfffeffff
#define MPHI_CTRL_REQ_SOFT_RST_MSB 16
#define MPHI_CTRL_REQ_SOFT_RST_LSB 16
#define MPHI_CTRL_REQ_SOFT_RST_RESET 0x0
#define MPHI_CTRL_EIGHTBIT_BITS 12:12
#define MPHI_CTRL_EIGHTBIT_SET 0x00001000
#define MPHI_CTRL_EIGHTBIT_CLR 0xffffefff
#define MPHI_CTRL_EIGHTBIT_MSB 12
#define MPHI_CTRL_EIGHTBIT_LSB 12
#define MPHI_CTRL_EIGHTBIT_RESET 0x1
#define MPHI_CTRL_INVERT_BITS 8:8
#define MPHI_CTRL_INVERT_SET 0x00000100
#define MPHI_CTRL_INVERT_CLR 0xfffffeff
#define MPHI_CTRL_INVERT_MSB 8
#define MPHI_CTRL_INVERT_LSB 8
#define MPHI_CTRL_INVERT_RESET 0x0
#define MPHI_CTRL_DIRECT_BITS 4:4
#define MPHI_CTRL_DIRECT_SET 0x00000010
#define MPHI_CTRL_DIRECT_CLR 0xffffffef
#define MPHI_CTRL_DIRECT_MSB 4
#define MPHI_CTRL_DIRECT_LSB 4
#define MPHI_CTRL_DIRECT_RESET 0x0
#define MPHI_CTRL_HATVAL_BITS 0:0
#define MPHI_CTRL_HATVAL_SET 0x00000001
#define MPHI_CTRL_HATVAL_CLR 0xfffffffe
#define MPHI_CTRL_HATVAL_MSB 0
#define MPHI_CTRL_HATVAL_LSB 0
#define MPHI_CTRL_HATVAL_RESET 0x0
#define MPHI_INTSTAT HW_REGISTER_RW( 0x7e006050 )
#define MPHI_INTSTAT_MASK 0xf9111111
#define MPHI_INTSTAT_WIDTH 32
#define MPHI_INTSTAT_HSTEND_BITS 31:31
#define MPHI_INTSTAT_HSTEND_SET 0x80000000
#define MPHI_INTSTAT_HSTEND_CLR 0x7fffffff
#define MPHI_INTSTAT_HSTEND_MSB 31
#define MPHI_INTSTAT_HSTEND_LSB 31
#define MPHI_INTSTAT_HSTEND_RESET 0x0
#define MPHI_INTSTAT_HSDISC_BITS 30:30
#define MPHI_INTSTAT_HSDISC_SET 0x40000000
#define MPHI_INTSTAT_HSDISC_CLR 0xbfffffff
#define MPHI_INTSTAT_HSDISC_MSB 30
#define MPHI_INTSTAT_HSDISC_LSB 30
#define MPHI_INTSTAT_HSDISC_RESET 0x0
#define MPHI_INTSTAT_IMFOFLW_BITS 29:29
#define MPHI_INTSTAT_IMFOFLW_SET 0x20000000
#define MPHI_INTSTAT_IMFOFLW_CLR 0xdfffffff
#define MPHI_INTSTAT_IMFOFLW_MSB 29
#define MPHI_INTSTAT_IMFOFLW_LSB 29
#define MPHI_INTSTAT_IMFOFLW_RESET 0x0
#define MPHI_INTSTAT_OMFUFLW_BITS 28:28
#define MPHI_INTSTAT_OMFUFLW_SET 0x10000000
#define MPHI_INTSTAT_OMFUFLW_CLR 0xefffffff
#define MPHI_INTSTAT_OMFUFLW_MSB 28
#define MPHI_INTSTAT_OMFUFLW_LSB 28
#define MPHI_INTSTAT_OMFUFLW_RESET 0x0
#define MPHI_INTSTAT_HSDCFOFLW_BITS 27:27
#define MPHI_INTSTAT_HSDCFOFLW_SET 0x08000000
#define MPHI_INTSTAT_HSDCFOFLW_CLR 0xf7ffffff
#define MPHI_INTSTAT_HSDCFOFLW_MSB 27
#define MPHI_INTSTAT_HSDCFOFLW_LSB 27
#define MPHI_INTSTAT_HSDCFOFLW_RESET 0x0
#define MPHI_INTSTAT_RX1DISC_BITS 24:24
#define MPHI_INTSTAT_RX1DISC_SET 0x01000000
#define MPHI_INTSTAT_RX1DISC_CLR 0xfeffffff
#define MPHI_INTSTAT_RX1DISC_MSB 24
#define MPHI_INTSTAT_RX1DISC_LSB 24
#define MPHI_INTSTAT_RX1DISC_RESET 0x0
#define MPHI_INTSTAT_RX0DISC_BITS 20:20
#define MPHI_INTSTAT_RX0DISC_SET 0x00100000
#define MPHI_INTSTAT_RX0DISC_CLR 0xffefffff
#define MPHI_INTSTAT_RX0DISC_MSB 20
#define MPHI_INTSTAT_RX0DISC_LSB 20
#define MPHI_INTSTAT_RX0DISC_RESET 0x0
#define MPHI_INTSTAT_TXEND_BITS 16:16
#define MPHI_INTSTAT_TXEND_SET 0x00010000
#define MPHI_INTSTAT_TXEND_CLR 0xfffeffff
#define MPHI_INTSTAT_TXEND_MSB 16
#define MPHI_INTSTAT_TXEND_LSB 16
#define MPHI_INTSTAT_TXEND_RESET 0x0
#define MPHI_INTSTAT_RX1TEND_BITS 12:12
#define MPHI_INTSTAT_RX1TEND_SET 0x00001000
#define MPHI_INTSTAT_RX1TEND_CLR 0xffffefff
#define MPHI_INTSTAT_RX1TEND_MSB 12
#define MPHI_INTSTAT_RX1TEND_LSB 12
#define MPHI_INTSTAT_RX1TEND_RESET 0x0
#define MPHI_INTSTAT_RX1MEND_BITS 8:8
#define MPHI_INTSTAT_RX1MEND_SET 0x00000100
#define MPHI_INTSTAT_RX1MEND_CLR 0xfffffeff
#define MPHI_INTSTAT_RX1MEND_MSB 8
#define MPHI_INTSTAT_RX1MEND_LSB 8
#define MPHI_INTSTAT_RX1MEND_RESET 0x0
#define MPHI_INTSTAT_RX0TEND_BITS 4:4
#define MPHI_INTSTAT_RX0TEND_SET 0x00000010
#define MPHI_INTSTAT_RX0TEND_CLR 0xffffffef
#define MPHI_INTSTAT_RX0TEND_MSB 4
#define MPHI_INTSTAT_RX0TEND_LSB 4
#define MPHI_INTSTAT_RX0TEND_RESET 0x0
#define MPHI_INTSTAT_RX0MEND_BITS 0:0
#define MPHI_INTSTAT_RX0MEND_SET 0x00000001
#define MPHI_INTSTAT_RX0MEND_CLR 0xfffffffe
#define MPHI_INTSTAT_RX0MEND_MSB 0
#define MPHI_INTSTAT_RX0MEND_LSB 0
#define MPHI_INTSTAT_RX0MEND_RESET 0x0
#define MPHI_VERSION HW_REGISTER_RO( 0x7e006054 )
#define MPHI_VERSION_MASK 0xffffffff
#define MPHI_VERSION_WIDTH 32
#define MPHI_INTCTRL HW_REGISTER_RW( 0x7e006058 )
#define MPHI_INTCTRL_MASK 0x00111111
#define MPHI_INTCTRL_WIDTH 21
#define MPHI_INTCTRL_HSDCOFLW_BITS 20:20
#define MPHI_INTCTRL_HSDCOFLW_SET 0x00100000
#define MPHI_INTCTRL_HSDCOFLW_CLR 0xffefffff
#define MPHI_INTCTRL_HSDCOFLW_MSB 20
#define MPHI_INTCTRL_HSDCOFLW_LSB 20
#define MPHI_INTCTRL_HSDCOFLW_RESET 0x0
#define MPHI_INTCTRL_HSDISC_BITS 16:16
#define MPHI_INTCTRL_HSDISC_SET 0x00010000
#define MPHI_INTCTRL_HSDISC_CLR 0xfffeffff
#define MPHI_INTCTRL_HSDISC_MSB 16
#define MPHI_INTCTRL_HSDISC_LSB 16
#define MPHI_INTCTRL_HSDISC_RESET 0x0
#define MPHI_INTCTRL_OMFUFLW_BITS 12:12
#define MPHI_INTCTRL_OMFUFLW_SET 0x00001000
#define MPHI_INTCTRL_OMFUFLW_CLR 0xffffefff
#define MPHI_INTCTRL_OMFUFLW_MSB 12
#define MPHI_INTCTRL_OMFUFLW_LSB 12
#define MPHI_INTCTRL_OMFUFLW_RESET 0x0
#define MPHI_INTCTRL_IMFOFLW_BITS 8:8
#define MPHI_INTCTRL_IMFOFLW_SET 0x00000100
#define MPHI_INTCTRL_IMFOFLW_CLR 0xfffffeff
#define MPHI_INTCTRL_IMFOFLW_MSB 8
#define MPHI_INTCTRL_IMFOFLW_LSB 8
#define MPHI_INTCTRL_IMFOFLW_RESET 0x0
#define MPHI_INTCTRL_RX1DISC_BITS 4:4
#define MPHI_INTCTRL_RX1DISC_SET 0x00000010
#define MPHI_INTCTRL_RX1DISC_CLR 0xffffffef
#define MPHI_INTCTRL_RX1DISC_MSB 4
#define MPHI_INTCTRL_RX1DISC_LSB 4
#define MPHI_INTCTRL_RX1DISC_RESET 0x0
#define MPHI_INTCTRL_RX0DISC_BITS 0:0
#define MPHI_INTCTRL_RX0DISC_SET 0x00000001
#define MPHI_INTCTRL_RX0DISC_CLR 0xfffffffe
#define MPHI_INTCTRL_RX0DISC_MSB 0
#define MPHI_INTCTRL_RX0DISC_LSB 0
#define MPHI_INTCTRL_RX0DISC_RESET 0x0
#define MPHI_HSINDCF HW_REGISTER_RW( 0x7e00605c )
#define MPHI_HSINDCF_MASK 0xdfffffff
#define MPHI_HSINDCF_WIDTH 32
#define MPHI_HSINDCF_EMPTY_BITS 31:31
#define MPHI_HSINDCF_EMPTY_SET 0x80000000
#define MPHI_HSINDCF_EMPTY_CLR 0x7fffffff
#define MPHI_HSINDCF_EMPTY_MSB 31
#define MPHI_HSINDCF_EMPTY_LSB 31
#define MPHI_HSINDCF_EMPTY_RESET 0x0
#define MPHI_HSINDCF_LENERR_BITS 30:30
#define MPHI_HSINDCF_LENERR_SET 0x40000000
#define MPHI_HSINDCF_LENERR_CLR 0xbfffffff
#define MPHI_HSINDCF_LENERR_MSB 30
#define MPHI_HSINDCF_LENERR_LSB 30
#define MPHI_HSINDCF_LENERR_RESET 0x0
#define MPHI_HSINDCF_MTERM_BITS 28:28
#define MPHI_HSINDCF_MTERM_SET 0x10000000
#define MPHI_HSINDCF_MTERM_CLR 0xefffffff
#define MPHI_HSINDCF_MTERM_MSB 28
#define MPHI_HSINDCF_MTERM_LSB 28
#define MPHI_HSINDCF_MTERM_RESET 0x0
#define MPHI_HSINDCF_HANDLE_BITS 27:20
#define MPHI_HSINDCF_HANDLE_SET 0x0ff00000
#define MPHI_HSINDCF_HANDLE_CLR 0xf00fffff
#define MPHI_HSINDCF_HANDLE_MSB 27
#define MPHI_HSINDCF_HANDLE_LSB 20
#define MPHI_HSINDCF_HANDLE_RESET 0x0
#define MPHI_HSINDCF_LENGTH_BITS 19:0
#define MPHI_HSINDCF_LENGTH_SET 0x000fffff
#define MPHI_HSINDCF_LENGTH_CLR 0xfff00000
#define MPHI_HSINDCF_LENGTH_MSB 19
#define MPHI_HSINDCF_LENGTH_LSB 0
#define MPHI_HSINDCF_LENGTH_RESET 0x0
#define MPHI_HSINDS HW_REGISTER_RW( 0x7e006060 )
#define MPHI_HSINDS_MASK 0xdfffffff
#define MPHI_HSINDS_WIDTH 32
#define MPHI_HSINDS_DISCARD_BITS 31:31
#define MPHI_HSINDS_DISCARD_SET 0x80000000
#define MPHI_HSINDS_DISCARD_CLR 0x7fffffff
#define MPHI_HSINDS_DISCARD_MSB 31
#define MPHI_HSINDS_DISCARD_LSB 31
#define MPHI_HSINDS_DISCARD_RESET 0x0
#define MPHI_HSINDS_VALID_BITS 30:30
#define MPHI_HSINDS_VALID_SET 0x40000000
#define MPHI_HSINDS_VALID_CLR 0xbfffffff
#define MPHI_HSINDS_VALID_MSB 30
#define MPHI_HSINDS_VALID_LSB 30
#define MPHI_HSINDS_VALID_RESET 0x0
#define MPHI_HSINDS_HANDLE_BITS 28:21
#define MPHI_HSINDS_HANDLE_SET 0x1fe00000
#define MPHI_HSINDS_HANDLE_CLR 0xe01fffff
#define MPHI_HSINDS_HANDLE_MSB 28
#define MPHI_HSINDS_HANDLE_LSB 21
#define MPHI_HSINDS_HANDLE_RESET 0x0
#define MPHI_HSINDS_WORDS_BITS 20:0
#define MPHI_HSINDS_WORDS_SET 0x001fffff
#define MPHI_HSINDS_WORDS_CLR 0xffe00000
#define MPHI_HSINDS_WORDS_MSB 20
#define MPHI_HSINDS_WORDS_LSB 0
#define MPHI_HSINDS_WORDS_RESET 0x0
#define MPHI_HSINDDA HW_REGISTER_RW( 0x7e006064 )
#define MPHI_HSINDDA_MASK 0xffffffff
#define MPHI_HSINDDA_WIDTH 32
#define MPHI_HSINDDA_START_BITS 31:0
#define MPHI_HSINDDA_START_SET 0xffffffff
#define MPHI_HSINDDA_START_CLR 0x00000000
#define MPHI_HSINDDA_START_MSB 31
#define MPHI_HSINDDA_START_LSB 0
#define MPHI_HSINDDA_START_RESET 0x0
#define MPHI_HSINDDB HW_REGISTER_RW( 0x7e006068 )
#define MPHI_HSINDDB_MASK 0x2fffffff
#define MPHI_HSINDDB_WIDTH 30
#define MPHI_HSINDDB_TENDINT_BITS 29:29
#define MPHI_HSINDDB_TENDINT_SET 0x20000000
#define MPHI_HSINDDB_TENDINT_CLR 0xdfffffff
#define MPHI_HSINDDB_TENDINT_MSB 29
#define MPHI_HSINDDB_TENDINT_LSB 29
#define MPHI_HSINDDB_TENDINT_RESET 0x0
#define MPHI_HSINDDB_HANDLE_BITS 27:20
#define MPHI_HSINDDB_HANDLE_SET 0x0ff00000
#define MPHI_HSINDDB_HANDLE_CLR 0xf00fffff
#define MPHI_HSINDDB_HANDLE_MSB 27
#define MPHI_HSINDDB_HANDLE_LSB 20
#define MPHI_HSINDDB_HANDLE_RESET 0x0
#define MPHI_HSINDDB_LENGTH_BITS 19:0
#define MPHI_HSINDDB_LENGTH_SET 0x000fffff
#define MPHI_HSINDDB_LENGTH_CLR 0xfff00000
#define MPHI_HSINDDB_LENGTH_MSB 19
#define MPHI_HSINDDB_LENGTH_LSB 0
#define MPHI_HSINDDB_LENGTH_RESET 0x0
#define MPHI_HSINDFS HW_REGISTER_RW( 0x7e00606c )
#define MPHI_HSINDFS_MASK 0xffff0001
#define MPHI_HSINDFS_WIDTH 32
#define MPHI_HSINDFS_CFIFOLVL_BITS 31:16
#define MPHI_HSINDFS_CFIFOLVL_SET 0xffff0000
#define MPHI_HSINDFS_CFIFOLVL_CLR 0x0000ffff
#define MPHI_HSINDFS_CFIFOLVL_MSB 31
#define MPHI_HSINDFS_CFIFOLVL_LSB 16
#define MPHI_HSINDFS_CFIFOLVL_RESET 0x0
#define MPHI_HSINDFS_DFIFOLVL_BITS 0:0
#define MPHI_HSINDFS_DFIFOLVL_SET 0x00000001
#define MPHI_HSINDFS_DFIFOLVL_CLR 0xfffffffe
#define MPHI_HSINDFS_DFIFOLVL_MSB 0
#define MPHI_HSINDFS_DFIFOLVL_LSB 0
#define MPHI_HSINDFS_DFIFOLVL_RESET 0x0

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bcm2708_chip/multicore_sync.h Executable file
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// This file was generated by the create_regs script
#define MS_BASE 0x7e000000
#define MS_APB_ID 0x4d554c54
#define MS_SEMA_0 HW_REGISTER_RW( 0x7e000000 )
#define MS_SEMA_0_MASK 0x00000001
#define MS_SEMA_0_WIDTH 1
#define MS_SEMA_0_RESET 0000000000
#define MS_SEMA_0_MASK_BITS 0:0
#define MS_SEMA_0_MASK_SET 0x00000001
#define MS_SEMA_0_MASK_CLR 0xfffffffe
#define MS_SEMA_0_MASK_MSB 0
#define MS_SEMA_0_MASK_LSB 0
#define MS_SEMA_1 HW_REGISTER_RW( 0x7e000004 )
#define MS_SEMA_1_MASK 0x00000001
#define MS_SEMA_1_WIDTH 1
#define MS_SEMA_1_RESET 0000000000
#define MS_SEMA_1_MASK_BITS 0:0
#define MS_SEMA_1_MASK_SET 0x00000001
#define MS_SEMA_1_MASK_CLR 0xfffffffe
#define MS_SEMA_1_MASK_MSB 0
#define MS_SEMA_1_MASK_LSB 0
#define MS_SEMA_2 HW_REGISTER_RW( 0x7e000008 )
#define MS_SEMA_2_MASK 0x00000001
#define MS_SEMA_2_WIDTH 1
#define MS_SEMA_2_RESET 0000000000
#define MS_SEMA_2_MASK_BITS 0:0
#define MS_SEMA_2_MASK_SET 0x00000001
#define MS_SEMA_2_MASK_CLR 0xfffffffe
#define MS_SEMA_2_MASK_MSB 0
#define MS_SEMA_2_MASK_LSB 0
#define MS_SEMA_3 HW_REGISTER_RW( 0x7e00000c )
#define MS_SEMA_3_MASK 0x00000001
#define MS_SEMA_3_WIDTH 1
#define MS_SEMA_3_RESET 0000000000
#define MS_SEMA_3_MASK_BITS 0:0
#define MS_SEMA_3_MASK_SET 0x00000001
#define MS_SEMA_3_MASK_CLR 0xfffffffe
#define MS_SEMA_3_MASK_MSB 0
#define MS_SEMA_3_MASK_LSB 0
#define MS_SEMA_4 HW_REGISTER_RW( 0x7e000010 )
#define MS_SEMA_4_MASK 0x00000001
#define MS_SEMA_4_WIDTH 1
#define MS_SEMA_4_RESET 0000000000
#define MS_SEMA_4_MASK_BITS 0:0
#define MS_SEMA_4_MASK_SET 0x00000001
#define MS_SEMA_4_MASK_CLR 0xfffffffe
#define MS_SEMA_4_MASK_MSB 0
#define MS_SEMA_4_MASK_LSB 0
#define MS_SEMA_5 HW_REGISTER_RW( 0x7e000014 )
#define MS_SEMA_5_MASK 0x00000001
#define MS_SEMA_5_WIDTH 1
#define MS_SEMA_5_RESET 0000000000
#define MS_SEMA_5_MASK_BITS 0:0
#define MS_SEMA_5_MASK_SET 0x00000001
#define MS_SEMA_5_MASK_CLR 0xfffffffe
#define MS_SEMA_5_MASK_MSB 0
#define MS_SEMA_5_MASK_LSB 0
#define MS_SEMA_6 HW_REGISTER_RW( 0x7e000018 )
#define MS_SEMA_6_MASK 0x00000001
#define MS_SEMA_6_WIDTH 1
#define MS_SEMA_6_RESET 0000000000
#define MS_SEMA_6_MASK_BITS 0:0
#define MS_SEMA_6_MASK_SET 0x00000001
#define MS_SEMA_6_MASK_CLR 0xfffffffe
#define MS_SEMA_6_MASK_MSB 0
#define MS_SEMA_6_MASK_LSB 0
#define MS_SEMA_7 HW_REGISTER_RW( 0x7e00001c )
#define MS_SEMA_7_MASK 0x00000001
#define MS_SEMA_7_WIDTH 1
#define MS_SEMA_7_RESET 0000000000
#define MS_SEMA_7_MASK_BITS 0:0
#define MS_SEMA_7_MASK_SET 0x00000001
#define MS_SEMA_7_MASK_CLR 0xfffffffe
#define MS_SEMA_7_MASK_MSB 0
#define MS_SEMA_7_MASK_LSB 0
#define MS_SEMA_8 HW_REGISTER_RW( 0x7e000020 )
#define MS_SEMA_8_MASK 0x00000001
#define MS_SEMA_8_WIDTH 1
#define MS_SEMA_8_RESET 0000000000
#define MS_SEMA_8_MASK_BITS 0:0
#define MS_SEMA_8_MASK_SET 0x00000001
#define MS_SEMA_8_MASK_CLR 0xfffffffe
#define MS_SEMA_8_MASK_MSB 0
#define MS_SEMA_8_MASK_LSB 0
#define MS_SEMA_9 HW_REGISTER_RW( 0x7e000024 )
#define MS_SEMA_9_MASK 0x00000001
#define MS_SEMA_9_WIDTH 1
#define MS_SEMA_9_RESET 0000000000
#define MS_SEMA_9_MASK_BITS 0:0
#define MS_SEMA_9_MASK_SET 0x00000001
#define MS_SEMA_9_MASK_CLR 0xfffffffe
#define MS_SEMA_9_MASK_MSB 0
#define MS_SEMA_9_MASK_LSB 0
#define MS_SEMA_10 HW_REGISTER_RW( 0x7e000028 )
#define MS_SEMA_10_MASK 0x00000001
#define MS_SEMA_10_WIDTH 1
#define MS_SEMA_10_RESET 0000000000
#define MS_SEMA_10_MASK_BITS 0:0
#define MS_SEMA_10_MASK_SET 0x00000001
#define MS_SEMA_10_MASK_CLR 0xfffffffe
#define MS_SEMA_10_MASK_MSB 0
#define MS_SEMA_10_MASK_LSB 0
#define MS_SEMA_11 HW_REGISTER_RW( 0x7e00002c )
#define MS_SEMA_11_MASK 0x00000001
#define MS_SEMA_11_WIDTH 1
#define MS_SEMA_11_RESET 0000000000
#define MS_SEMA_11_MASK_BITS 0:0
#define MS_SEMA_11_MASK_SET 0x00000001
#define MS_SEMA_11_MASK_CLR 0xfffffffe
#define MS_SEMA_11_MASK_MSB 0
#define MS_SEMA_11_MASK_LSB 0
#define MS_SEMA_12 HW_REGISTER_RW( 0x7e000030 )
#define MS_SEMA_12_MASK 0x00000001
#define MS_SEMA_12_WIDTH 1
#define MS_SEMA_12_RESET 0000000000
#define MS_SEMA_12_MASK_BITS 0:0
#define MS_SEMA_12_MASK_SET 0x00000001
#define MS_SEMA_12_MASK_CLR 0xfffffffe
#define MS_SEMA_12_MASK_MSB 0
#define MS_SEMA_12_MASK_LSB 0
#define MS_SEMA_13 HW_REGISTER_RW( 0x7e000034 )
#define MS_SEMA_13_MASK 0x00000001
#define MS_SEMA_13_WIDTH 1
#define MS_SEMA_13_RESET 0000000000
#define MS_SEMA_13_MASK_BITS 0:0
#define MS_SEMA_13_MASK_SET 0x00000001
#define MS_SEMA_13_MASK_CLR 0xfffffffe
#define MS_SEMA_13_MASK_MSB 0
#define MS_SEMA_13_MASK_LSB 0
#define MS_SEMA_14 HW_REGISTER_RW( 0x7e000038 )
#define MS_SEMA_14_MASK 0x00000001
#define MS_SEMA_14_WIDTH 1
#define MS_SEMA_14_RESET 0000000000
#define MS_SEMA_14_MASK_BITS 0:0
#define MS_SEMA_14_MASK_SET 0x00000001
#define MS_SEMA_14_MASK_CLR 0xfffffffe
#define MS_SEMA_14_MASK_MSB 0
#define MS_SEMA_14_MASK_LSB 0
#define MS_SEMA_15 HW_REGISTER_RW( 0x7e00003c )
#define MS_SEMA_15_MASK 0x00000001
#define MS_SEMA_15_WIDTH 1
#define MS_SEMA_15_RESET 0000000000
#define MS_SEMA_15_MASK_BITS 0:0
#define MS_SEMA_15_MASK_SET 0x00000001
#define MS_SEMA_15_MASK_CLR 0xfffffffe
#define MS_SEMA_15_MASK_MSB 0
#define MS_SEMA_15_MASK_LSB 0
#define MS_SEMA_16 HW_REGISTER_RW( 0x7e000040 )
#define MS_SEMA_16_MASK 0x00000001
#define MS_SEMA_16_WIDTH 1
#define MS_SEMA_16_RESET 0000000000
#define MS_SEMA_16_MASK_BITS 0:0
#define MS_SEMA_16_MASK_SET 0x00000001
#define MS_SEMA_16_MASK_CLR 0xfffffffe
#define MS_SEMA_16_MASK_MSB 0
#define MS_SEMA_16_MASK_LSB 0
#define MS_SEMA_17 HW_REGISTER_RW( 0x7e000044 )
#define MS_SEMA_17_MASK 0x00000001
#define MS_SEMA_17_WIDTH 1
#define MS_SEMA_17_RESET 0000000000
#define MS_SEMA_17_MASK_BITS 0:0
#define MS_SEMA_17_MASK_SET 0x00000001
#define MS_SEMA_17_MASK_CLR 0xfffffffe
#define MS_SEMA_17_MASK_MSB 0
#define MS_SEMA_17_MASK_LSB 0
#define MS_SEMA_18 HW_REGISTER_RW( 0x7e000048 )
#define MS_SEMA_18_MASK 0x00000001
#define MS_SEMA_18_WIDTH 1
#define MS_SEMA_18_RESET 0000000000
#define MS_SEMA_18_MASK_BITS 0:0
#define MS_SEMA_18_MASK_SET 0x00000001
#define MS_SEMA_18_MASK_CLR 0xfffffffe
#define MS_SEMA_18_MASK_MSB 0
#define MS_SEMA_18_MASK_LSB 0
#define MS_SEMA_19 HW_REGISTER_RW( 0x7e00004c )
#define MS_SEMA_19_MASK 0x00000001
#define MS_SEMA_19_WIDTH 1
#define MS_SEMA_19_RESET 0000000000
#define MS_SEMA_19_MASK_BITS 0:0
#define MS_SEMA_19_MASK_SET 0x00000001
#define MS_SEMA_19_MASK_CLR 0xfffffffe
#define MS_SEMA_19_MASK_MSB 0
#define MS_SEMA_19_MASK_LSB 0
#define MS_SEMA_20 HW_REGISTER_RW( 0x7e000050 )
#define MS_SEMA_20_MASK 0x00000001
#define MS_SEMA_20_WIDTH 1
#define MS_SEMA_20_RESET 0000000000
#define MS_SEMA_20_MASK_BITS 0:0
#define MS_SEMA_20_MASK_SET 0x00000001
#define MS_SEMA_20_MASK_CLR 0xfffffffe
#define MS_SEMA_20_MASK_MSB 0
#define MS_SEMA_20_MASK_LSB 0
#define MS_SEMA_21 HW_REGISTER_RW( 0x7e000054 )
#define MS_SEMA_21_MASK 0x00000001
#define MS_SEMA_21_WIDTH 1
#define MS_SEMA_21_RESET 0000000000
#define MS_SEMA_21_MASK_BITS 0:0
#define MS_SEMA_21_MASK_SET 0x00000001
#define MS_SEMA_21_MASK_CLR 0xfffffffe
#define MS_SEMA_21_MASK_MSB 0
#define MS_SEMA_21_MASK_LSB 0
#define MS_SEMA_22 HW_REGISTER_RW( 0x7e000058 )
#define MS_SEMA_22_MASK 0x00000001
#define MS_SEMA_22_WIDTH 1
#define MS_SEMA_22_RESET 0000000000
#define MS_SEMA_22_MASK_BITS 0:0
#define MS_SEMA_22_MASK_SET 0x00000001
#define MS_SEMA_22_MASK_CLR 0xfffffffe
#define MS_SEMA_22_MASK_MSB 0
#define MS_SEMA_22_MASK_LSB 0
#define MS_SEMA_23 HW_REGISTER_RW( 0x7e00005c )
#define MS_SEMA_23_MASK 0x00000001
#define MS_SEMA_23_WIDTH 1
#define MS_SEMA_23_RESET 0000000000
#define MS_SEMA_23_MASK_BITS 0:0
#define MS_SEMA_23_MASK_SET 0x00000001
#define MS_SEMA_23_MASK_CLR 0xfffffffe
#define MS_SEMA_23_MASK_MSB 0
#define MS_SEMA_23_MASK_LSB 0
#define MS_SEMA_24 HW_REGISTER_RW( 0x7e000060 )
#define MS_SEMA_24_MASK 0x00000001
#define MS_SEMA_24_WIDTH 1
#define MS_SEMA_24_RESET 0000000000
#define MS_SEMA_24_MASK_BITS 0:0
#define MS_SEMA_24_MASK_SET 0x00000001
#define MS_SEMA_24_MASK_CLR 0xfffffffe
#define MS_SEMA_24_MASK_MSB 0
#define MS_SEMA_24_MASK_LSB 0
#define MS_SEMA_25 HW_REGISTER_RW( 0x7e000064 )
#define MS_SEMA_25_MASK 0x00000001
#define MS_SEMA_25_WIDTH 1
#define MS_SEMA_25_RESET 0000000000
#define MS_SEMA_25_MASK_BITS 0:0
#define MS_SEMA_25_MASK_SET 0x00000001
#define MS_SEMA_25_MASK_CLR 0xfffffffe
#define MS_SEMA_25_MASK_MSB 0
#define MS_SEMA_25_MASK_LSB 0
#define MS_SEMA_26 HW_REGISTER_RW( 0x7e000068 )
#define MS_SEMA_26_MASK 0x00000001
#define MS_SEMA_26_WIDTH 1
#define MS_SEMA_26_RESET 0000000000
#define MS_SEMA_26_MASK_BITS 0:0
#define MS_SEMA_26_MASK_SET 0x00000001
#define MS_SEMA_26_MASK_CLR 0xfffffffe
#define MS_SEMA_26_MASK_MSB 0
#define MS_SEMA_26_MASK_LSB 0
#define MS_SEMA_27 HW_REGISTER_RW( 0x7e00006c )
#define MS_SEMA_27_MASK 0x00000001
#define MS_SEMA_27_WIDTH 1
#define MS_SEMA_27_RESET 0000000000
#define MS_SEMA_27_MASK_BITS 0:0
#define MS_SEMA_27_MASK_SET 0x00000001
#define MS_SEMA_27_MASK_CLR 0xfffffffe
#define MS_SEMA_27_MASK_MSB 0
#define MS_SEMA_27_MASK_LSB 0
#define MS_SEMA_28 HW_REGISTER_RW( 0x7e000070 )
#define MS_SEMA_28_MASK 0x00000001
#define MS_SEMA_28_WIDTH 1
#define MS_SEMA_28_RESET 0000000000
#define MS_SEMA_28_MASK_BITS 0:0
#define MS_SEMA_28_MASK_SET 0x00000001
#define MS_SEMA_28_MASK_CLR 0xfffffffe
#define MS_SEMA_28_MASK_MSB 0
#define MS_SEMA_28_MASK_LSB 0
#define MS_SEMA_29 HW_REGISTER_RW( 0x7e000074 )
#define MS_SEMA_29_MASK 0x00000001
#define MS_SEMA_29_WIDTH 1
#define MS_SEMA_29_RESET 0000000000
#define MS_SEMA_29_MASK_BITS 0:0
#define MS_SEMA_29_MASK_SET 0x00000001
#define MS_SEMA_29_MASK_CLR 0xfffffffe
#define MS_SEMA_29_MASK_MSB 0
#define MS_SEMA_29_MASK_LSB 0
#define MS_SEMA_30 HW_REGISTER_RW( 0x7e000078 )
#define MS_SEMA_30_MASK 0x00000001
#define MS_SEMA_30_WIDTH 1
#define MS_SEMA_30_RESET 0000000000
#define MS_SEMA_30_MASK_BITS 0:0
#define MS_SEMA_30_MASK_SET 0x00000001
#define MS_SEMA_30_MASK_CLR 0xfffffffe
#define MS_SEMA_30_MASK_MSB 0
#define MS_SEMA_30_MASK_LSB 0
#define MS_SEMA_31 HW_REGISTER_RW( 0x7e00007c )
#define MS_SEMA_31_MASK 0x00000001
#define MS_SEMA_31_WIDTH 1
#define MS_SEMA_31_RESET 0000000000
#define MS_SEMA_31_MASK_BITS 0:0
#define MS_SEMA_31_MASK_SET 0x00000001
#define MS_SEMA_31_MASK_CLR 0xfffffffe
#define MS_SEMA_31_MASK_MSB 0
#define MS_SEMA_31_MASK_LSB 0
#define MS_STATUS HW_REGISTER_RO( 0x7e000080 )
#define MS_STATUS_MASK 0xffffffff
#define MS_STATUS_WIDTH 32
#define MS_STATUS_RESET 0000000000
#define MS_STATUS_STATUS_BITS 31:0
#define MS_STATUS_STATUS_SET 0xffffffff
#define MS_STATUS_STATUS_CLR 0x00000000
#define MS_STATUS_STATUS_MSB 31
#define MS_STATUS_STATUS_LSB 0
#define MS_IREQ_0 HW_REGISTER_RW( 0x7e000084 )
#define MS_IREQ_0_MASK 0xffffffff
#define MS_IREQ_0_WIDTH 32
#define MS_IREQ_0_RESET 0000000000
#define MS_IREQ_0_IREQ_0_BITS 31:0
#define MS_IREQ_0_IREQ_0_SET 0xffffffff
#define MS_IREQ_0_IREQ_0_CLR 0x00000000
#define MS_IREQ_0_IREQ_0_MSB 31
#define MS_IREQ_0_IREQ_0_LSB 0
#define MS_IREQ_1 HW_REGISTER_RW( 0x7e000088 )
#define MS_IREQ_1_MASK 0xffffffff
#define MS_IREQ_1_WIDTH 32
#define MS_IREQ_1_RESET 0000000000
#define MS_IREQ_1_IREQ_1_BITS 31:0
#define MS_IREQ_1_IREQ_1_SET 0xffffffff
#define MS_IREQ_1_IREQ_1_CLR 0x00000000
#define MS_IREQ_1_IREQ_1_MSB 31
#define MS_IREQ_1_IREQ_1_LSB 0
#define MS_ICSET_0 HW_REGISTER_RW( 0x7e000090 )
#define MS_ICSET_0_MASK 0x00000001
#define MS_ICSET_0_WIDTH 1
#define MS_ICSET_0_RESET 0000000000
#define MS_ICSET_0_ICSET_0_BITS 0:0
#define MS_ICSET_0_ICSET_0_SET 0x00000001
#define MS_ICSET_0_ICSET_0_CLR 0xfffffffe
#define MS_ICSET_0_ICSET_0_MSB 0
#define MS_ICSET_0_ICSET_0_LSB 0
#define MS_ICSET_1 HW_REGISTER_RW( 0x7e000094 )
#define MS_ICSET_1_MASK 0x00000001
#define MS_ICSET_1_WIDTH 1
#define MS_ICSET_1_RESET 0000000000
#define MS_ICSET_1_ICSET_1_BITS 0:0
#define MS_ICSET_1_ICSET_1_SET 0x00000001
#define MS_ICSET_1_ICSET_1_CLR 0xfffffffe
#define MS_ICSET_1_ICSET_1_MSB 0
#define MS_ICSET_1_ICSET_1_LSB 0
#define MS_ICCLR_0 HW_REGISTER_RW( 0x7e000098 )
#define MS_ICCLR_0_MASK 0x00000001
#define MS_ICCLR_0_WIDTH 1
#define MS_ICCLR_0_RESET 0000000000
#define MS_ICCLR_0_ICCLR_0_BITS 0:0
#define MS_ICCLR_0_ICCLR_0_SET 0x00000001
#define MS_ICCLR_0_ICCLR_0_CLR 0xfffffffe
#define MS_ICCLR_0_ICCLR_0_MSB 0
#define MS_ICCLR_0_ICCLR_0_LSB 0
#define MS_ICCLR_1 HW_REGISTER_RW( 0x7e00009c )
#define MS_ICCLR_1_MASK 0x00000001
#define MS_ICCLR_1_WIDTH 1
#define MS_ICCLR_1_RESET 0000000000
#define MS_ICCLR_1_ICCLR_1_BITS 0:0
#define MS_ICCLR_1_ICCLR_1_SET 0x00000001
#define MS_ICCLR_1_ICCLR_1_CLR 0xfffffffe
#define MS_ICCLR_1_ICCLR_1_MSB 0
#define MS_ICCLR_1_ICCLR_1_LSB 0
#define MS_MBOX_0 HW_REGISTER_RW( 0x7e0000a0 )
#define MS_MBOX_0_MASK 0xffffffff
#define MS_MBOX_0_WIDTH 32
#define MS_MBOX_0_RESET 0000000000
#define MS_MBOX_0_MBOX_BITS 31:0
#define MS_MBOX_0_MBOX_SET 0xffffffff
#define MS_MBOX_0_MBOX_CLR 0x00000000
#define MS_MBOX_0_MBOX_MSB 31
#define MS_MBOX_0_MBOX_LSB 0
#define MS_MBOX_1 HW_REGISTER_RW( 0x7e0000a4 )
#define MS_MBOX_1_MASK 0xffffffff
#define MS_MBOX_1_WIDTH 32
#define MS_MBOX_1_RESET 0000000000
#define MS_MBOX_1_MBOX_BITS 31:0
#define MS_MBOX_1_MBOX_SET 0xffffffff
#define MS_MBOX_1_MBOX_CLR 0x00000000
#define MS_MBOX_1_MBOX_MSB 31
#define MS_MBOX_1_MBOX_LSB 0
#define MS_MBOX_2 HW_REGISTER_RW( 0x7e0000a8 )
#define MS_MBOX_2_MASK 0xffffffff
#define MS_MBOX_2_WIDTH 32
#define MS_MBOX_2_RESET 0000000000
#define MS_MBOX_2_MBOX_BITS 31:0
#define MS_MBOX_2_MBOX_SET 0xffffffff
#define MS_MBOX_2_MBOX_CLR 0x00000000
#define MS_MBOX_2_MBOX_MSB 31
#define MS_MBOX_2_MBOX_LSB 0
#define MS_MBOX_3 HW_REGISTER_RW( 0x7e0000ac )
#define MS_MBOX_3_MASK 0xffffffff
#define MS_MBOX_3_WIDTH 32
#define MS_MBOX_3_RESET 0000000000
#define MS_MBOX_3_MBOX_BITS 31:0
#define MS_MBOX_3_MBOX_SET 0xffffffff
#define MS_MBOX_3_MBOX_CLR 0x00000000
#define MS_MBOX_3_MBOX_MSB 31
#define MS_MBOX_3_MBOX_LSB 0
#define MS_MBOX_4 HW_REGISTER_RW( 0x7e0000b0 )
#define MS_MBOX_4_MASK 0xffffffff
#define MS_MBOX_4_WIDTH 32
#define MS_MBOX_4_RESET 0000000000
#define MS_MBOX_4_MBOX_BITS 31:0
#define MS_MBOX_4_MBOX_SET 0xffffffff
#define MS_MBOX_4_MBOX_CLR 0x00000000
#define MS_MBOX_4_MBOX_MSB 31
#define MS_MBOX_4_MBOX_LSB 0
#define MS_MBOX_5 HW_REGISTER_RW( 0x7e0000b4 )
#define MS_MBOX_5_MASK 0xffffffff
#define MS_MBOX_5_WIDTH 32
#define MS_MBOX_5_RESET 0000000000
#define MS_MBOX_5_MBOX_BITS 31:0
#define MS_MBOX_5_MBOX_SET 0xffffffff
#define MS_MBOX_5_MBOX_CLR 0x00000000
#define MS_MBOX_5_MBOX_MSB 31
#define MS_MBOX_5_MBOX_LSB 0
#define MS_MBOX_6 HW_REGISTER_RW( 0x7e0000b8 )
#define MS_MBOX_6_MASK 0xffffffff
#define MS_MBOX_6_WIDTH 32
#define MS_MBOX_6_RESET 0000000000
#define MS_MBOX_6_MBOX_BITS 31:0
#define MS_MBOX_6_MBOX_SET 0xffffffff
#define MS_MBOX_6_MBOX_CLR 0x00000000
#define MS_MBOX_6_MBOX_MSB 31
#define MS_MBOX_6_MBOX_LSB 0
#define MS_MBOX_7 HW_REGISTER_RW( 0x7e0000bc )
#define MS_MBOX_7_MASK 0xffffffff
#define MS_MBOX_7_WIDTH 32
#define MS_MBOX_7_RESET 0000000000
#define MS_MBOX_7_MBOX_BITS 31:0
#define MS_MBOX_7_MBOX_SET 0xffffffff
#define MS_MBOX_7_MBOX_CLR 0x00000000
#define MS_MBOX_7_MBOX_MSB 31
#define MS_MBOX_7_MBOX_LSB 0
#define MS_VPUSEMA_0 HW_REGISTER_RW( 0x7e0000c0 )
#define MS_VPUSEMA_0_VPUSEMA_0_BITS 0:0
#define MS_VPUSEMA_0_VPUSEMA_0_SET 0x00000001
#define MS_VPUSEMA_0_VPUSEMA_0_CLR 0xfffffffe
#define MS_VPUSEMA_0_VPUSEMA_0_MSB 0
#define MS_VPUSEMA_0_VPUSEMA_0_LSB 0
#define MS_VPUSEMA_1 HW_REGISTER_RW( 0x7e0000c4 )
#define MS_VPUSEMA_1_VPUSEMA_1_BITS 0:0
#define MS_VPUSEMA_1_VPUSEMA_1_SET 0x00000001
#define MS_VPUSEMA_1_VPUSEMA_1_CLR 0xfffffffe
#define MS_VPUSEMA_1_VPUSEMA_1_MSB 0
#define MS_VPUSEMA_1_VPUSEMA_1_LSB 0
#define MS_VPU_STAT HW_REGISTER_RO( 0x7e0000c8 )
#define MS_VPU_STAT_MASK 0x00ff00ff
#define MS_VPU_STAT_WIDTH 24
#define MS_VPU_STAT_VPU_STAT_BITS 0:0
#define MS_VPU_STAT_VPU_STAT_SET 0x00000001
#define MS_VPU_STAT_VPU_STAT_CLR 0xfffffffe
#define MS_VPU_STAT_VPU_STAT_MSB 0
#define MS_VPU_STAT_VPU_STAT_LSB 0

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bcm2708_chip/nexus_uba.h Executable file
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// This file was generated by the create_regs script
#define NU_BASE 0x7e008000
#define NU_HOSTIO_OF HW_REGISTER_RW( 0x7e008000 )
#define NU_HOSTIO_OF_MASK 0xffffffff
#define NU_HOSTIO_OF_WIDTH 32
#define NU_HOSTIO_OF_RESET 0000000000

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bcm2708_chip/otp.h Executable file
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// This file was generated by the create_regs script
#define OTP_BASE 0x7e20f000
#define OTP_APB_ID 0x206f7470
#define OTP_BOOTMODE_REG HW_REGISTER_RW( 0x7e20f000 )
#define OTP_BOOTMODE_REG_MASK 0xffffffff
#define OTP_BOOTMODE_REG_WIDTH 32
#define OTP_CONFIG_REG HW_REGISTER_RW( 0x7e20f004 )
#define OTP_CONFIG_REG_MASK 0x00000007
#define OTP_CONFIG_REG_WIDTH 3
#define OTP_CTRL_LO_REG HW_REGISTER_RW( 0x7e20f008 )
#define OTP_CTRL_LO_REG_MASK 0xffffffff
#define OTP_CTRL_LO_REG_WIDTH 32
#define OTP_CTRL_HI_REG HW_REGISTER_RW( 0x7e20f00c )
#define OTP_CTRL_HI_REG_MASK 0x0000ffff
#define OTP_CTRL_HI_REG_WIDTH 16
#define OTP_STATUS_REG HW_REGISTER_RO( 0x7e20f010 )
#define OTP_STATUS_REG_MASK 0xffffffff
#define OTP_STATUS_REG_WIDTH 32
#define OTP_BITSEL_REG HW_REGISTER_RW( 0x7e20f014 )
#define OTP_BITSEL_REG_MASK 0x0000001f
#define OTP_BITSEL_REG_WIDTH 5
#define OTP_DATA_REG HW_REGISTER_RW( 0x7e20f018 )
#define OTP_DATA_REG_MASK 0x0000001f
#define OTP_DATA_REG_WIDTH 5
#define OTP_ADDR_REG HW_REGISTER_RW( 0x7e20f01c )
#define OTP_ADDR_REG_MASK 0x0000001f
#define OTP_ADDR_REG_WIDTH 5
#define OTP_WRITE_DATA_READ_REG HW_REGISTER_RW( 0x7e20f020 )
#define OTP_WRITE_DATA_READ_REG_MASK 0xffffffff
#define OTP_WRITE_DATA_READ_REG_WIDTH 32
#define OTP_INIT_STATUS_REG HW_REGISTER_RW( 0x7e20f024 )
#define OTP_INIT_STATUS_REG_MASK 0xffffffff
#define OTP_INIT_STATUS_REG_WIDTH 32

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bcm2708_chip/pcm.h Executable file
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// This file was generated by the create_regs script
#define PCM_BASE 0x7e203000
#define PCM_CS_A HW_REGISTER_RW( 0x7e203000 )
#define PCM_CS_A_MASK 0x03ffe3ff
#define PCM_CS_A_WIDTH 26
#define PCM_CS_A_RESET 0000000000
#define PCM_CS_A_STBY_BITS 25:25
#define PCM_CS_A_STBY_SET 0x02000000
#define PCM_CS_A_STBY_CLR 0xfdffffff
#define PCM_CS_A_STBY_MSB 25
#define PCM_CS_A_STBY_LSB 25
#define PCM_CS_A_SYNC_BITS 24:24
#define PCM_CS_A_SYNC_SET 0x01000000
#define PCM_CS_A_SYNC_CLR 0xfeffffff
#define PCM_CS_A_SYNC_MSB 24
#define PCM_CS_A_SYNC_LSB 24
#define PCM_CS_A_RXSEX_BITS 23:23
#define PCM_CS_A_RXSEX_SET 0x00800000
#define PCM_CS_A_RXSEX_CLR 0xff7fffff
#define PCM_CS_A_RXSEX_MSB 23
#define PCM_CS_A_RXSEX_LSB 23
#define PCM_CS_A_RXF_BITS 22:22
#define PCM_CS_A_RXF_SET 0x00400000
#define PCM_CS_A_RXF_CLR 0xffbfffff
#define PCM_CS_A_RXF_MSB 22
#define PCM_CS_A_RXF_LSB 22
#define PCM_CS_A_TXE_BITS 21:21
#define PCM_CS_A_TXE_SET 0x00200000
#define PCM_CS_A_TXE_CLR 0xffdfffff
#define PCM_CS_A_TXE_MSB 21
#define PCM_CS_A_TXE_LSB 21
#define PCM_CS_A_RXD_BITS 20:20
#define PCM_CS_A_RXD_SET 0x00100000
#define PCM_CS_A_RXD_CLR 0xffefffff
#define PCM_CS_A_RXD_MSB 20
#define PCM_CS_A_RXD_LSB 20
#define PCM_CS_A_TXD_BITS 19:19
#define PCM_CS_A_TXD_SET 0x00080000
#define PCM_CS_A_TXD_CLR 0xfff7ffff
#define PCM_CS_A_TXD_MSB 19
#define PCM_CS_A_TXD_LSB 19
#define PCM_CS_A_RXR_BITS 18:18
#define PCM_CS_A_RXR_SET 0x00040000
#define PCM_CS_A_RXR_CLR 0xfffbffff
#define PCM_CS_A_RXR_MSB 18
#define PCM_CS_A_RXR_LSB 18
#define PCM_CS_A_TXW_BITS 17:17
#define PCM_CS_A_TXW_SET 0x00020000
#define PCM_CS_A_TXW_CLR 0xfffdffff
#define PCM_CS_A_TXW_MSB 17
#define PCM_CS_A_TXW_LSB 17
#define PCM_CS_A_RXERR_BITS 16:16
#define PCM_CS_A_RXERR_SET 0x00010000
#define PCM_CS_A_RXERR_CLR 0xfffeffff
#define PCM_CS_A_RXERR_MSB 16
#define PCM_CS_A_RXERR_LSB 16
#define PCM_CS_A_TXERR_BITS 15:15
#define PCM_CS_A_TXERR_SET 0x00008000
#define PCM_CS_A_TXERR_CLR 0xffff7fff
#define PCM_CS_A_TXERR_MSB 15
#define PCM_CS_A_TXERR_LSB 15
#define PCM_CS_A_RXSYNC_BITS 14:14
#define PCM_CS_A_RXSYNC_SET 0x00004000
#define PCM_CS_A_RXSYNC_CLR 0xffffbfff
#define PCM_CS_A_RXSYNC_MSB 14
#define PCM_CS_A_RXSYNC_LSB 14
#define PCM_CS_A_TXSYNC_BITS 13:13
#define PCM_CS_A_TXSYNC_SET 0x00002000
#define PCM_CS_A_TXSYNC_CLR 0xffffdfff
#define PCM_CS_A_TXSYNC_MSB 13
#define PCM_CS_A_TXSYNC_LSB 13
#define PCM_CS_A_DMAEN_BITS 9:9
#define PCM_CS_A_DMAEN_SET 0x00000200
#define PCM_CS_A_DMAEN_CLR 0xfffffdff
#define PCM_CS_A_DMAEN_MSB 9
#define PCM_CS_A_DMAEN_LSB 9
#define PCM_CS_A_RXTHR_BITS 8:7
#define PCM_CS_A_RXTHR_SET 0x00000180
#define PCM_CS_A_RXTHR_CLR 0xfffffe7f
#define PCM_CS_A_RXTHR_MSB 8
#define PCM_CS_A_RXTHR_LSB 7
#define PCM_CS_A_TXTHR_BITS 6:5
#define PCM_CS_A_TXTHR_SET 0x00000060
#define PCM_CS_A_TXTHR_CLR 0xffffff9f
#define PCM_CS_A_TXTHR_MSB 6
#define PCM_CS_A_TXTHR_LSB 5
#define PCM_CS_A_RXCLR_BITS 4:4
#define PCM_CS_A_RXCLR_SET 0x00000010
#define PCM_CS_A_RXCLR_CLR 0xffffffef
#define PCM_CS_A_RXCLR_MSB 4
#define PCM_CS_A_RXCLR_LSB 4
#define PCM_CS_A_TXCLR_BITS 3:3
#define PCM_CS_A_TXCLR_SET 0x00000008
#define PCM_CS_A_TXCLR_CLR 0xfffffff7
#define PCM_CS_A_TXCLR_MSB 3
#define PCM_CS_A_TXCLR_LSB 3
#define PCM_CS_A_TXON_BITS 2:2
#define PCM_CS_A_TXON_SET 0x00000004
#define PCM_CS_A_TXON_CLR 0xfffffffb
#define PCM_CS_A_TXON_MSB 2
#define PCM_CS_A_TXON_LSB 2
#define PCM_CS_A_RXON_BITS 1:1
#define PCM_CS_A_RXON_SET 0x00000002
#define PCM_CS_A_RXON_CLR 0xfffffffd
#define PCM_CS_A_RXON_MSB 1
#define PCM_CS_A_RXON_LSB 1
#define PCM_CS_A_EN_BITS 0:0
#define PCM_CS_A_EN_SET 0x00000001
#define PCM_CS_A_EN_CLR 0xfffffffe
#define PCM_CS_A_EN_MSB 0
#define PCM_CS_A_EN_LSB 0
#define PCM_FIFO_A HW_REGISTER_RW( 0x7e203004 )
#define PCM_FIFO_A_MASK 0xffffffff
#define PCM_FIFO_A_WIDTH 32
#define PCM_MODE_A HW_REGISTER_RW( 0x7e203008 )
#define PCM_MODE_A_MASK 0x1fffffff
#define PCM_MODE_A_WIDTH 29
#define PCM_MODE_A_RESET 0000000000
#define PCM_MODE_A_CLK_DIS_BITS 28:28
#define PCM_MODE_A_CLK_DIS_SET 0x10000000
#define PCM_MODE_A_CLK_DIS_CLR 0xefffffff
#define PCM_MODE_A_CLK_DIS_MSB 28
#define PCM_MODE_A_CLK_DIS_LSB 28
#define PCM_MODE_A_PDMN_BITS 27:27
#define PCM_MODE_A_PDMN_SET 0x08000000
#define PCM_MODE_A_PDMN_CLR 0xf7ffffff
#define PCM_MODE_A_PDMN_MSB 27
#define PCM_MODE_A_PDMN_LSB 27
#define PCM_MODE_A_PDME_BITS 26:26
#define PCM_MODE_A_PDME_SET 0x04000000
#define PCM_MODE_A_PDME_CLR 0xfbffffff
#define PCM_MODE_A_PDME_MSB 26
#define PCM_MODE_A_PDME_LSB 26
#define PCM_MODE_A_FRXP_BITS 25:25
#define PCM_MODE_A_FRXP_SET 0x02000000
#define PCM_MODE_A_FRXP_CLR 0xfdffffff
#define PCM_MODE_A_FRXP_MSB 25
#define PCM_MODE_A_FRXP_LSB 25
#define PCM_MODE_A_FTXP_BITS 24:24
#define PCM_MODE_A_FTXP_SET 0x01000000
#define PCM_MODE_A_FTXP_CLR 0xfeffffff
#define PCM_MODE_A_FTXP_MSB 24
#define PCM_MODE_A_FTXP_LSB 24
#define PCM_MODE_A_CLKM_BITS 23:23
#define PCM_MODE_A_CLKM_SET 0x00800000
#define PCM_MODE_A_CLKM_CLR 0xff7fffff
#define PCM_MODE_A_CLKM_MSB 23
#define PCM_MODE_A_CLKM_LSB 23
#define PCM_MODE_A_CLKI_BITS 22:22
#define PCM_MODE_A_CLKI_SET 0x00400000
#define PCM_MODE_A_CLKI_CLR 0xffbfffff
#define PCM_MODE_A_CLKI_MSB 22
#define PCM_MODE_A_CLKI_LSB 22
#define PCM_MODE_A_FSM_BITS 21:21
#define PCM_MODE_A_FSM_SET 0x00200000
#define PCM_MODE_A_FSM_CLR 0xffdfffff
#define PCM_MODE_A_FSM_MSB 21
#define PCM_MODE_A_FSM_LSB 21
#define PCM_MODE_A_FSI_BITS 20:20
#define PCM_MODE_A_FSI_SET 0x00100000
#define PCM_MODE_A_FSI_CLR 0xffefffff
#define PCM_MODE_A_FSI_MSB 20
#define PCM_MODE_A_FSI_LSB 20
#define PCM_MODE_A_FLEN_BITS 19:10
#define PCM_MODE_A_FLEN_SET 0x000ffc00
#define PCM_MODE_A_FLEN_CLR 0xfff003ff
#define PCM_MODE_A_FLEN_MSB 19
#define PCM_MODE_A_FLEN_LSB 10
#define PCM_MODE_A_FSLEN_BITS 9:0
#define PCM_MODE_A_FSLEN_SET 0x000003ff
#define PCM_MODE_A_FSLEN_CLR 0xfffffc00
#define PCM_MODE_A_FSLEN_MSB 9
#define PCM_MODE_A_FSLEN_LSB 0
#define PCM_RXC_A HW_REGISTER_RW( 0x7e20300c )
#define PCM_RXC_A_MASK 0xffffffff
#define PCM_RXC_A_WIDTH 32
#define PCM_RXC_A_RESET 0000000000
#define PCM_RXC_A_CH1WEX_BITS 31:31
#define PCM_RXC_A_CH1WEX_SET 0x80000000
#define PCM_RXC_A_CH1WEX_CLR 0x7fffffff
#define PCM_RXC_A_CH1WEX_MSB 31
#define PCM_RXC_A_CH1WEX_LSB 31
#define PCM_RXC_A_CH1EN_BITS 30:30
#define PCM_RXC_A_CH1EN_SET 0x40000000
#define PCM_RXC_A_CH1EN_CLR 0xbfffffff
#define PCM_RXC_A_CH1EN_MSB 30
#define PCM_RXC_A_CH1EN_LSB 30
#define PCM_RXC_A_CH1POS_BITS 29:20
#define PCM_RXC_A_CH1POS_SET 0x3ff00000
#define PCM_RXC_A_CH1POS_CLR 0xc00fffff
#define PCM_RXC_A_CH1POS_MSB 29
#define PCM_RXC_A_CH1POS_LSB 20
#define PCM_RXC_A_CH1WID_BITS 19:16
#define PCM_RXC_A_CH1WID_SET 0x000f0000
#define PCM_RXC_A_CH1WID_CLR 0xfff0ffff
#define PCM_RXC_A_CH1WID_MSB 19
#define PCM_RXC_A_CH1WID_LSB 16
#define PCM_RXC_A_CH2WEX_BITS 15:15
#define PCM_RXC_A_CH2WEX_SET 0x00008000
#define PCM_RXC_A_CH2WEX_CLR 0xffff7fff
#define PCM_RXC_A_CH2WEX_MSB 15
#define PCM_RXC_A_CH2WEX_LSB 15
#define PCM_RXC_A_CH2EN_BITS 14:14
#define PCM_RXC_A_CH2EN_SET 0x00004000
#define PCM_RXC_A_CH2EN_CLR 0xffffbfff
#define PCM_RXC_A_CH2EN_MSB 14
#define PCM_RXC_A_CH2EN_LSB 14
#define PCM_RXC_A_CH2POS_BITS 13:4
#define PCM_RXC_A_CH2POS_SET 0x00003ff0
#define PCM_RXC_A_CH2POS_CLR 0xffffc00f
#define PCM_RXC_A_CH2POS_MSB 13
#define PCM_RXC_A_CH2POS_LSB 4
#define PCM_RXC_A_CH2WID_BITS 3:0
#define PCM_RXC_A_CH2WID_SET 0x0000000f
#define PCM_RXC_A_CH2WID_CLR 0xfffffff0
#define PCM_RXC_A_CH2WID_MSB 3
#define PCM_RXC_A_CH2WID_LSB 0
#define PCM_TXC_A HW_REGISTER_RW( 0x7e203010 )
#define PCM_TXC_A_MASK 0xffffffff
#define PCM_TXC_A_WIDTH 32
#define PCM_TXC_A_RESET 0000000000
#define PCM_TXC_A_CH1WEX_BITS 31:31
#define PCM_TXC_A_CH1WEX_SET 0x80000000
#define PCM_TXC_A_CH1WEX_CLR 0x7fffffff
#define PCM_TXC_A_CH1WEX_MSB 31
#define PCM_TXC_A_CH1WEX_LSB 31
#define PCM_TXC_A_CH1EN_BITS 30:30
#define PCM_TXC_A_CH1EN_SET 0x40000000
#define PCM_TXC_A_CH1EN_CLR 0xbfffffff
#define PCM_TXC_A_CH1EN_MSB 30
#define PCM_TXC_A_CH1EN_LSB 30
#define PCM_TXC_A_CH1POS_BITS 29:20
#define PCM_TXC_A_CH1POS_SET 0x3ff00000
#define PCM_TXC_A_CH1POS_CLR 0xc00fffff
#define PCM_TXC_A_CH1POS_MSB 29
#define PCM_TXC_A_CH1POS_LSB 20
#define PCM_TXC_A_CH1WID_BITS 19:16
#define PCM_TXC_A_CH1WID_SET 0x000f0000
#define PCM_TXC_A_CH1WID_CLR 0xfff0ffff
#define PCM_TXC_A_CH1WID_MSB 19
#define PCM_TXC_A_CH1WID_LSB 16
#define PCM_TXC_A_CH2WEX_BITS 15:15
#define PCM_TXC_A_CH2WEX_SET 0x00008000
#define PCM_TXC_A_CH2WEX_CLR 0xffff7fff
#define PCM_TXC_A_CH2WEX_MSB 15
#define PCM_TXC_A_CH2WEX_LSB 15
#define PCM_TXC_A_CH2EN_BITS 14:14
#define PCM_TXC_A_CH2EN_SET 0x00004000
#define PCM_TXC_A_CH2EN_CLR 0xffffbfff
#define PCM_TXC_A_CH2EN_MSB 14
#define PCM_TXC_A_CH2EN_LSB 14
#define PCM_TXC_A_CH2POS_BITS 13:4
#define PCM_TXC_A_CH2POS_SET 0x00003ff0
#define PCM_TXC_A_CH2POS_CLR 0xffffc00f
#define PCM_TXC_A_CH2POS_MSB 13
#define PCM_TXC_A_CH2POS_LSB 4
#define PCM_TXC_A_CH2WID_BITS 3:0
#define PCM_TXC_A_CH2WID_SET 0x0000000f
#define PCM_TXC_A_CH2WID_CLR 0xfffffff0
#define PCM_TXC_A_CH2WID_MSB 3
#define PCM_TXC_A_CH2WID_LSB 0
#define PCM_DREQ_A HW_REGISTER_RW( 0x7e203014 )
#define PCM_DREQ_A_MASK 0x7f7f7f7f
#define PCM_DREQ_A_WIDTH 31
#define PCM_DREQ_A_RESET 0x10303020
#define PCM_DREQ_A_TX_PANIC_BITS 30:24
#define PCM_DREQ_A_TX_PANIC_SET 0x7f000000
#define PCM_DREQ_A_TX_PANIC_CLR 0x80ffffff
#define PCM_DREQ_A_TX_PANIC_MSB 30
#define PCM_DREQ_A_TX_PANIC_LSB 24
#define PCM_DREQ_A_RX_PANIC_BITS 22:16
#define PCM_DREQ_A_RX_PANIC_SET 0x007f0000
#define PCM_DREQ_A_RX_PANIC_CLR 0xff80ffff
#define PCM_DREQ_A_RX_PANIC_MSB 22
#define PCM_DREQ_A_RX_PANIC_LSB 16
#define PCM_DREQ_A_TX_BITS 14:8
#define PCM_DREQ_A_TX_SET 0x00007f00
#define PCM_DREQ_A_TX_CLR 0xffff80ff
#define PCM_DREQ_A_TX_MSB 14
#define PCM_DREQ_A_TX_LSB 8
#define PCM_DREQ_A_RX_BITS 6:0
#define PCM_DREQ_A_RX_SET 0x0000007f
#define PCM_DREQ_A_RX_CLR 0xffffff80
#define PCM_DREQ_A_RX_MSB 6
#define PCM_DREQ_A_RX_LSB 0
#define PCM_INTEN_A HW_REGISTER_RW( 0x7e203018 )
#define PCM_INTEN_A_MASK 0x0000000f
#define PCM_INTEN_A_WIDTH 4
#define PCM_INTEN_A_RESET 0000000000
#define PCM_INTEN_A_RXERR_BITS 3:3
#define PCM_INTEN_A_RXERR_SET 0x00000008
#define PCM_INTEN_A_RXERR_CLR 0xfffffff7
#define PCM_INTEN_A_RXERR_MSB 3
#define PCM_INTEN_A_RXERR_LSB 3
#define PCM_INTEN_A_TXERR_BITS 2:2
#define PCM_INTEN_A_TXERR_SET 0x00000004
#define PCM_INTEN_A_TXERR_CLR 0xfffffffb
#define PCM_INTEN_A_TXERR_MSB 2
#define PCM_INTEN_A_TXERR_LSB 2
#define PCM_INTEN_A_RXR_BITS 1:1
#define PCM_INTEN_A_RXR_SET 0x00000002
#define PCM_INTEN_A_RXR_CLR 0xfffffffd
#define PCM_INTEN_A_RXR_MSB 1
#define PCM_INTEN_A_RXR_LSB 1
#define PCM_INTEN_A_TXW_BITS 0:0
#define PCM_INTEN_A_TXW_SET 0x00000001
#define PCM_INTEN_A_TXW_CLR 0xfffffffe
#define PCM_INTEN_A_TXW_MSB 0
#define PCM_INTEN_A_TXW_LSB 0
#define PCM_INTSTC_A HW_REGISTER_RW( 0x7e20301c )
#define PCM_INTSTC_A_MASK 0x0000000f
#define PCM_INTSTC_A_WIDTH 4
#define PCM_INTSTC_A_RESET 0000000000
#define PCM_INTSTC_A_RXERR_BITS 3:3
#define PCM_INTSTC_A_RXERR_SET 0x00000008
#define PCM_INTSTC_A_RXERR_CLR 0xfffffff7
#define PCM_INTSTC_A_RXERR_MSB 3
#define PCM_INTSTC_A_RXERR_LSB 3
#define PCM_INTSTC_A_TXERR_BITS 2:2
#define PCM_INTSTC_A_TXERR_SET 0x00000004
#define PCM_INTSTC_A_TXERR_CLR 0xfffffffb
#define PCM_INTSTC_A_TXERR_MSB 2
#define PCM_INTSTC_A_TXERR_LSB 2
#define PCM_INTSTC_A_RXR_BITS 1:1
#define PCM_INTSTC_A_RXR_SET 0x00000002
#define PCM_INTSTC_A_RXR_CLR 0xfffffffd
#define PCM_INTSTC_A_RXR_MSB 1
#define PCM_INTSTC_A_RXR_LSB 1
#define PCM_INTSTC_A_TXW_BITS 0:0
#define PCM_INTSTC_A_TXW_SET 0x00000001
#define PCM_INTSTC_A_TXW_CLR 0xfffffffe
#define PCM_INTSTC_A_TXW_MSB 0
#define PCM_INTSTC_A_TXW_LSB 0
#define PCM_GRAY HW_REGISTER_RW( 0x7e203020 )
#define PCM_GRAY_MASK 0x003ffff7
#define PCM_GRAY_WIDTH 22
#define PCM_GRAY_RESET 0000000000
#define PCM_GRAY_RXFIFOLEVEL_BITS 21:16
#define PCM_GRAY_RXFIFOLEVEL_SET 0x003f0000
#define PCM_GRAY_RXFIFOLEVEL_CLR 0xffc0ffff
#define PCM_GRAY_RXFIFOLEVEL_MSB 21
#define PCM_GRAY_RXFIFOLEVEL_LSB 16
#define PCM_GRAY_FLUSHED_BITS 15:10
#define PCM_GRAY_FLUSHED_SET 0x0000fc00
#define PCM_GRAY_FLUSHED_CLR 0xffff03ff
#define PCM_GRAY_FLUSHED_MSB 15
#define PCM_GRAY_FLUSHED_LSB 10
#define PCM_GRAY_RXLEVEL_BITS 9:4
#define PCM_GRAY_RXLEVEL_SET 0x000003f0
#define PCM_GRAY_RXLEVEL_CLR 0xfffffc0f
#define PCM_GRAY_RXLEVEL_MSB 9
#define PCM_GRAY_RXLEVEL_LSB 4
#define PCM_GRAY_FLUSH_BITS 2:2
#define PCM_GRAY_FLUSH_SET 0x00000004
#define PCM_GRAY_FLUSH_CLR 0xfffffffb
#define PCM_GRAY_FLUSH_MSB 2
#define PCM_GRAY_FLUSH_LSB 2
#define PCM_GRAY_CLR_BITS 1:1
#define PCM_GRAY_CLR_SET 0x00000002
#define PCM_GRAY_CLR_CLR 0xfffffffd
#define PCM_GRAY_CLR_MSB 1
#define PCM_GRAY_CLR_LSB 1
#define PCM_GRAY_EN_BITS 0:0
#define PCM_GRAY_EN_SET 0x00000001
#define PCM_GRAY_EN_CLR 0xfffffffe
#define PCM_GRAY_EN_MSB 0
#define PCM_GRAY_EN_LSB 0

11
bcm2708_chip/perfmon.h Executable file
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// This file was generated by the create_regs script
#define PRM_BASE 0x7e20d000
#define PRM_CS HW_REGISTER_RW( 0x7e20d000 )
#define PRM_CS_MASK 0xffffffff
#define PRM_CS_WIDTH 32
#define PRM_CV HW_REGISTER_RW( 0x7e20d004 )
#define PRM_CV_MASK 0xffffffff
#define PRM_CV_WIDTH 32
#define PRM_SCC HW_REGISTER_RW( 0x7e20d008 )
#define PRM_SCC_MASK 0xffffffff
#define PRM_SCC_WIDTH 32

36
bcm2708_chip/peri_image_arb_ctrl.h Executable file
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// This file was generated by the create_regs script
#define PIARBCTL_BASE 0x7e80a000
#define PIARBCTL_CAM HW_REGISTER_RW( 0x7e80a000 )
#define PIARBCTL_CAM_MASK 0x0000ffff
#define PIARBCTL_CAM_WIDTH 16
#define PIARBCTL_CAM_RESET 0000000000
#define PIARBCTL_CAM_CHANNEL_INIBIT_BITS 15:8
#define PIARBCTL_CAM_CHANNEL_INIBIT_SET 0x0000ff00
#define PIARBCTL_CAM_CHANNEL_INIBIT_CLR 0xffff00ff
#define PIARBCTL_CAM_CHANNEL_INIBIT_MSB 15
#define PIARBCTL_CAM_CHANNEL_INIBIT_LSB 8
#define PIARBCTL_CAM_CHANNEL_INIBIT_RESET 0x0
#define PIARBCTL_CAM_ALGORITHM_BITS 7:6
#define PIARBCTL_CAM_ALGORITHM_SET 0x000000c0
#define PIARBCTL_CAM_ALGORITHM_CLR 0xffffff3f
#define PIARBCTL_CAM_ALGORITHM_MSB 7
#define PIARBCTL_CAM_ALGORITHM_LSB 6
#define PIARBCTL_CAM_ALGORITHM_RESET 0x0
#define PIARBCTL_CAM_THRESHOLD_BITS 5:4
#define PIARBCTL_CAM_THRESHOLD_SET 0x00000030
#define PIARBCTL_CAM_THRESHOLD_CLR 0xffffffcf
#define PIARBCTL_CAM_THRESHOLD_MSB 5
#define PIARBCTL_CAM_THRESHOLD_LSB 4
#define PIARBCTL_CAM_THRESHOLD_RESET 0x0
#define PIARBCTL_CAM_DELAY_BITS 3:2
#define PIARBCTL_CAM_DELAY_SET 0x0000000c
#define PIARBCTL_CAM_DELAY_CLR 0xfffffff3
#define PIARBCTL_CAM_DELAY_MSB 3
#define PIARBCTL_CAM_DELAY_LSB 2
#define PIARBCTL_CAM_DELAY_RESET 0x0
#define PIARBCTL_CAM_LIMIT_BITS 1:0
#define PIARBCTL_CAM_LIMIT_SET 0x00000003
#define PIARBCTL_CAM_LIMIT_CLR 0xfffffffc
#define PIARBCTL_CAM_LIMIT_MSB 1
#define PIARBCTL_CAM_LIMIT_LSB 0
#define PIARBCTL_CAM_LIMIT_RESET 0x0

42
bcm2708_chip/pixel_valve0.h Executable file
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// This file was generated by the create_regs script
#define PIXELVALVE0_BASE 0x7e206000
#define PIXELVALVE0_APB_ID 0x70697876
#define PIXELVALVE0_C HW_REGISTER_RW( 0x7e206000 )
#define PIXELVALVE0_C_MASK 0x00ffffff
#define PIXELVALVE0_C_WIDTH 24
#define PIXELVALVE0_VC HW_REGISTER_RW( 0x7e206004 )
#define PIXELVALVE0_VC_MASK 0x007fffff
#define PIXELVALVE0_VC_WIDTH 23
#define PIXELVALVE0_VSYNCD_EVEN HW_REGISTER_RW( 0x7e206008 )
#define PIXELVALVE0_VSYNCD_EVEN_MASK 0x0001ffff
#define PIXELVALVE0_VSYNCD_EVEN_WIDTH 17
#define PIXELVALVE0_HORZA HW_REGISTER_RW( 0x7e20600c )
#define PIXELVALVE0_HORZA_MASK 0xffffffff
#define PIXELVALVE0_HORZA_WIDTH 32
#define PIXELVALVE0_HORZB HW_REGISTER_RW( 0x7e206010 )
#define PIXELVALVE0_HORZB_MASK 0xffffffff
#define PIXELVALVE0_HORZB_WIDTH 32
#define PIXELVALVE0_VERTA HW_REGISTER_RW( 0x7e206014 )
#define PIXELVALVE0_VERTA_MASK 0xffffffff
#define PIXELVALVE0_VERTA_WIDTH 32
#define PIXELVALVE0_VERTB HW_REGISTER_RW( 0x7e206018 )
#define PIXELVALVE0_VERTB_MASK 0xffffffff
#define PIXELVALVE0_VERTB_WIDTH 32
#define PIXELVALVE0_VERTA_EVEN HW_REGISTER_RW( 0x7e20601c )
#define PIXELVALVE0_VERTA_EVEN_MASK 0xffffffff
#define PIXELVALVE0_VERTA_EVEN_WIDTH 32
#define PIXELVALVE0_VERTB_EVEN HW_REGISTER_RW( 0x7e206020 )
#define PIXELVALVE0_VERTB_EVEN_MASK 0xffffffff
#define PIXELVALVE0_VERTB_EVEN_WIDTH 32
#define PIXELVALVE0_INTEN HW_REGISTER_RW( 0x7e206024 )
#define PIXELVALVE0_INTEN_MASK 0x000003ff
#define PIXELVALVE0_INTEN_WIDTH 10
#define PIXELVALVE0_INTSTAT HW_REGISTER_RW( 0x7e206028 )
#define PIXELVALVE0_INTSTAT_MASK 0x000003ff
#define PIXELVALVE0_INTSTAT_WIDTH 10
#define PIXELVALVE0_STAT HW_REGISTER_RW( 0x7e20602c )
#define PIXELVALVE0_STAT_MASK 0x000003ff
#define PIXELVALVE0_STAT_WIDTH 10
#define PIXELVALVE0_DSI_HACT_ACT HW_REGISTER_RW( 0x7e206030 )
#define PIXELVALVE0_DSI_HACT_ACT_MASK 0x0000ffff
#define PIXELVALVE0_DSI_HACT_ACT_WIDTH 16

42
bcm2708_chip/pixel_valve1.h Executable file
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// This file was generated by the create_regs script
#define PIXELVALVE1_BASE 0x7e207000
#define PIXELVALVE1_APB_ID 0x70697876
#define PIXELVALVE1_C HW_REGISTER_RW( 0x7e207000 )
#define PIXELVALVE1_C_MASK 0x00ffffff
#define PIXELVALVE1_C_WIDTH 24
#define PIXELVALVE1_VC HW_REGISTER_RW( 0x7e207004 )
#define PIXELVALVE1_VC_MASK 0x007fffff
#define PIXELVALVE1_VC_WIDTH 23
#define PIXELVALVE1_VSYNCD_EVEN HW_REGISTER_RW( 0x7e207008 )
#define PIXELVALVE1_VSYNCD_EVEN_MASK 0x0001ffff
#define PIXELVALVE1_VSYNCD_EVEN_WIDTH 17
#define PIXELVALVE1_HORZA HW_REGISTER_RW( 0x7e20700c )
#define PIXELVALVE1_HORZA_MASK 0xffffffff
#define PIXELVALVE1_HORZA_WIDTH 32
#define PIXELVALVE1_HORZB HW_REGISTER_RW( 0x7e207010 )
#define PIXELVALVE1_HORZB_MASK 0xffffffff
#define PIXELVALVE1_HORZB_WIDTH 32
#define PIXELVALVE1_VERTA HW_REGISTER_RW( 0x7e207014 )
#define PIXELVALVE1_VERTA_MASK 0xffffffff
#define PIXELVALVE1_VERTA_WIDTH 32
#define PIXELVALVE1_VERTB HW_REGISTER_RW( 0x7e207018 )
#define PIXELVALVE1_VERTB_MASK 0xffffffff
#define PIXELVALVE1_VERTB_WIDTH 32
#define PIXELVALVE1_VERTA_EVEN HW_REGISTER_RW( 0x7e20701c )
#define PIXELVALVE1_VERTA_EVEN_MASK 0xffffffff
#define PIXELVALVE1_VERTA_EVEN_WIDTH 32
#define PIXELVALVE1_VERTB_EVEN HW_REGISTER_RW( 0x7e207020 )
#define PIXELVALVE1_VERTB_EVEN_MASK 0xffffffff
#define PIXELVALVE1_VERTB_EVEN_WIDTH 32
#define PIXELVALVE1_INTEN HW_REGISTER_RW( 0x7e207024 )
#define PIXELVALVE1_INTEN_MASK 0x000003ff
#define PIXELVALVE1_INTEN_WIDTH 10
#define PIXELVALVE1_INTSTAT HW_REGISTER_RW( 0x7e207028 )
#define PIXELVALVE1_INTSTAT_MASK 0x000003ff
#define PIXELVALVE1_INTSTAT_WIDTH 10
#define PIXELVALVE1_STAT HW_REGISTER_RW( 0x7e20702c )
#define PIXELVALVE1_STAT_MASK 0x000003ff
#define PIXELVALVE1_STAT_WIDTH 10
#define PIXELVALVE1_DSI_HACT_ACT HW_REGISTER_RW( 0x7e207030 )
#define PIXELVALVE1_DSI_HACT_ACT_MASK 0x0000ffff
#define PIXELVALVE1_DSI_HACT_ACT_WIDTH 16

42
bcm2708_chip/pixel_valve2.h Executable file
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// This file was generated by the create_regs script
#define PIXELVALVE2_BASE 0x7e807000
#define PIXELVALVE2_APB_ID 0x70697876
#define PIXELVALVE2_C HW_REGISTER_RW( 0x7e807000 )
#define PIXELVALVE2_C_MASK 0x00ffffff
#define PIXELVALVE2_C_WIDTH 24
#define PIXELVALVE2_VC HW_REGISTER_RW( 0x7e807004 )
#define PIXELVALVE2_VC_MASK 0x007fffff
#define PIXELVALVE2_VC_WIDTH 23
#define PIXELVALVE2_VSYNCD_EVEN HW_REGISTER_RW( 0x7e807008 )
#define PIXELVALVE2_VSYNCD_EVEN_MASK 0x0001ffff
#define PIXELVALVE2_VSYNCD_EVEN_WIDTH 17
#define PIXELVALVE2_HORZA HW_REGISTER_RW( 0x7e80700c )
#define PIXELVALVE2_HORZA_MASK 0xffffffff
#define PIXELVALVE2_HORZA_WIDTH 32
#define PIXELVALVE2_HORZB HW_REGISTER_RW( 0x7e807010 )
#define PIXELVALVE2_HORZB_MASK 0xffffffff
#define PIXELVALVE2_HORZB_WIDTH 32
#define PIXELVALVE2_VERTA HW_REGISTER_RW( 0x7e807014 )
#define PIXELVALVE2_VERTA_MASK 0xffffffff
#define PIXELVALVE2_VERTA_WIDTH 32
#define PIXELVALVE2_VERTB HW_REGISTER_RW( 0x7e807018 )
#define PIXELVALVE2_VERTB_MASK 0xffffffff
#define PIXELVALVE2_VERTB_WIDTH 32
#define PIXELVALVE2_VERTA_EVEN HW_REGISTER_RW( 0x7e80701c )
#define PIXELVALVE2_VERTA_EVEN_MASK 0xffffffff
#define PIXELVALVE2_VERTA_EVEN_WIDTH 32
#define PIXELVALVE2_VERTB_EVEN HW_REGISTER_RW( 0x7e807020 )
#define PIXELVALVE2_VERTB_EVEN_MASK 0xffffffff
#define PIXELVALVE2_VERTB_EVEN_WIDTH 32
#define PIXELVALVE2_INTEN HW_REGISTER_RW( 0x7e807024 )
#define PIXELVALVE2_INTEN_MASK 0x000003ff
#define PIXELVALVE2_INTEN_WIDTH 10
#define PIXELVALVE2_INTSTAT HW_REGISTER_RW( 0x7e807028 )
#define PIXELVALVE2_INTSTAT_MASK 0x000003ff
#define PIXELVALVE2_INTSTAT_WIDTH 10
#define PIXELVALVE2_STAT HW_REGISTER_RW( 0x7e80702c )
#define PIXELVALVE2_STAT_MASK 0x000003ff
#define PIXELVALVE2_STAT_WIDTH 10
#define PIXELVALVE2_DSI_HACT_ACT HW_REGISTER_RW( 0x7e807030 )
#define PIXELVALVE2_DSI_HACT_ACT_MASK 0x0000ffff
#define PIXELVALVE2_DSI_HACT_ACT_WIDTH 16

276
bcm2708_chip/pwm.h Executable file
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// This file was generated by the create_regs script
#define PWM_BASE 0x7e20c000
#define PWM_APB_ID 0x70776d30
#define PWM_CTL HW_REGISTER_RW( 0x7e20c000 )
#define PWM_CTL_MASK 0xbfbfbfff
#define PWM_CTL_WIDTH 32
#define PWM_CTL_RESET 0000000000
#define PWM_CTL_PWEN1_BITS 0:0
#define PWM_CTL_PWEN1_SET 0x00000001
#define PWM_CTL_PWEN1_CLR 0xfffffffe
#define PWM_CTL_PWEN1_MSB 0
#define PWM_CTL_PWEN1_LSB 0
#define PWM_CTL_MODE1_BITS 1:1
#define PWM_CTL_MODE1_SET 0x00000002
#define PWM_CTL_MODE1_CLR 0xfffffffd
#define PWM_CTL_MODE1_MSB 1
#define PWM_CTL_MODE1_LSB 1
#define PWM_CTL_RPTL1_BITS 2:2
#define PWM_CTL_RPTL1_SET 0x00000004
#define PWM_CTL_RPTL1_CLR 0xfffffffb
#define PWM_CTL_RPTL1_MSB 2
#define PWM_CTL_RPTL1_LSB 2
#define PWM_CTL_SBIT1_BITS 3:3
#define PWM_CTL_SBIT1_SET 0x00000008
#define PWM_CTL_SBIT1_CLR 0xfffffff7
#define PWM_CTL_SBIT1_MSB 3
#define PWM_CTL_SBIT1_LSB 3
#define PWM_CTL_POLA1_BITS 4:4
#define PWM_CTL_POLA1_SET 0x00000010
#define PWM_CTL_POLA1_CLR 0xffffffef
#define PWM_CTL_POLA1_MSB 4
#define PWM_CTL_POLA1_LSB 4
#define PWM_CTL_USEF1_BITS 5:5
#define PWM_CTL_USEF1_SET 0x00000020
#define PWM_CTL_USEF1_CLR 0xffffffdf
#define PWM_CTL_USEF1_MSB 5
#define PWM_CTL_USEF1_LSB 5
#define PWM_CTL_CLRF1_BITS 6:6
#define PWM_CTL_CLRF1_SET 0x00000040
#define PWM_CTL_CLRF1_CLR 0xffffffbf
#define PWM_CTL_CLRF1_MSB 6
#define PWM_CTL_CLRF1_LSB 6
#define PWM_CTL_MSEN1_BITS 7:7
#define PWM_CTL_MSEN1_SET 0x00000080
#define PWM_CTL_MSEN1_CLR 0xffffff7f
#define PWM_CTL_MSEN1_MSB 7
#define PWM_CTL_MSEN1_LSB 7
#define PWM_CTL_PWEN2_BITS 8:8
#define PWM_CTL_PWEN2_SET 0x00000100
#define PWM_CTL_PWEN2_CLR 0xfffffeff
#define PWM_CTL_PWEN2_MSB 8
#define PWM_CTL_PWEN2_LSB 8
#define PWM_CTL_MODE2_BITS 9:9
#define PWM_CTL_MODE2_SET 0x00000200
#define PWM_CTL_MODE2_CLR 0xfffffdff
#define PWM_CTL_MODE2_MSB 9
#define PWM_CTL_MODE2_LSB 9
#define PWM_CTL_RPTL2_BITS 10:10
#define PWM_CTL_RPTL2_SET 0x00000400
#define PWM_CTL_RPTL2_CLR 0xfffffbff
#define PWM_CTL_RPTL2_MSB 10
#define PWM_CTL_RPTL2_LSB 10
#define PWM_CTL_SBIT2_BITS 11:11
#define PWM_CTL_SBIT2_SET 0x00000800
#define PWM_CTL_SBIT2_CLR 0xfffff7ff
#define PWM_CTL_SBIT2_MSB 11
#define PWM_CTL_SBIT2_LSB 11
#define PWM_CTL_POLA2_BITS 12:12
#define PWM_CTL_POLA2_SET 0x00001000
#define PWM_CTL_POLA2_CLR 0xffffefff
#define PWM_CTL_POLA2_MSB 12
#define PWM_CTL_POLA2_LSB 12
#define PWM_CTL_USEF2_BITS 13:13
#define PWM_CTL_USEF2_SET 0x00002000
#define PWM_CTL_USEF2_CLR 0xffffdfff
#define PWM_CTL_USEF2_MSB 13
#define PWM_CTL_USEF2_LSB 13
#define PWM_CTL_MSEN2_BITS 15:15
#define PWM_CTL_MSEN2_SET 0x00008000
#define PWM_CTL_MSEN2_CLR 0xffff7fff
#define PWM_CTL_MSEN2_MSB 15
#define PWM_CTL_MSEN2_LSB 15
#define PWM_CTL_PWEN3_BITS 16:16
#define PWM_CTL_PWEN3_SET 0x00010000
#define PWM_CTL_PWEN3_CLR 0xfffeffff
#define PWM_CTL_PWEN3_MSB 16
#define PWM_CTL_PWEN3_LSB 16
#define PWM_CTL_MODE3_BITS 17:17
#define PWM_CTL_MODE3_SET 0x00020000
#define PWM_CTL_MODE3_CLR 0xfffdffff
#define PWM_CTL_MODE3_MSB 17
#define PWM_CTL_MODE3_LSB 17
#define PWM_CTL_RPTL3_BITS 18:18
#define PWM_CTL_RPTL3_SET 0x00040000
#define PWM_CTL_RPTL3_CLR 0xfffbffff
#define PWM_CTL_RPTL3_MSB 18
#define PWM_CTL_RPTL3_LSB 18
#define PWM_CTL_SBIT3_BITS 19:19
#define PWM_CTL_SBIT3_SET 0x00080000
#define PWM_CTL_SBIT3_CLR 0xfff7ffff
#define PWM_CTL_SBIT3_MSB 19
#define PWM_CTL_SBIT3_LSB 19
#define PWM_CTL_POLA3_BITS 20:20
#define PWM_CTL_POLA3_SET 0x00100000
#define PWM_CTL_POLA3_CLR 0xffefffff
#define PWM_CTL_POLA3_MSB 20
#define PWM_CTL_POLA3_LSB 20
#define PWM_CTL_USEF3_BITS 21:21
#define PWM_CTL_USEF3_SET 0x00200000
#define PWM_CTL_USEF3_CLR 0xffdfffff
#define PWM_CTL_USEF3_MSB 21
#define PWM_CTL_USEF3_LSB 21
#define PWM_CTL_MSEN3_BITS 23:23
#define PWM_CTL_MSEN3_SET 0x00800000
#define PWM_CTL_MSEN3_CLR 0xff7fffff
#define PWM_CTL_MSEN3_MSB 23
#define PWM_CTL_MSEN3_LSB 23
#define PWM_CTL_PWEN4_BITS 24:24
#define PWM_CTL_PWEN4_SET 0x01000000
#define PWM_CTL_PWEN4_CLR 0xfeffffff
#define PWM_CTL_PWEN4_MSB 24
#define PWM_CTL_PWEN4_LSB 24
#define PWM_CTL_MODE4_BITS 25:25
#define PWM_CTL_MODE4_SET 0x02000000
#define PWM_CTL_MODE4_CLR 0xfdffffff
#define PWM_CTL_MODE4_MSB 25
#define PWM_CTL_MODE4_LSB 25
#define PWM_CTL_RPTL4_BITS 26:26
#define PWM_CTL_RPTL4_SET 0x04000000
#define PWM_CTL_RPTL4_CLR 0xfbffffff
#define PWM_CTL_RPTL4_MSB 26
#define PWM_CTL_RPTL4_LSB 26
#define PWM_CTL_SBIT4_BITS 27:27
#define PWM_CTL_SBIT4_SET 0x08000000
#define PWM_CTL_SBIT4_CLR 0xf7ffffff
#define PWM_CTL_SBIT4_MSB 27
#define PWM_CTL_SBIT4_LSB 27
#define PWM_CTL_POLA4_BITS 28:28
#define PWM_CTL_POLA4_SET 0x10000000
#define PWM_CTL_POLA4_CLR 0xefffffff
#define PWM_CTL_POLA4_MSB 28
#define PWM_CTL_POLA4_LSB 28
#define PWM_CTL_USEF4_BITS 29:29
#define PWM_CTL_USEF4_SET 0x20000000
#define PWM_CTL_USEF4_CLR 0xdfffffff
#define PWM_CTL_USEF4_MSB 29
#define PWM_CTL_USEF4_LSB 29
#define PWM_CTL_MSEN4_BITS 31:31
#define PWM_CTL_MSEN4_SET 0x80000000
#define PWM_CTL_MSEN4_CLR 0x7fffffff
#define PWM_CTL_MSEN4_MSB 31
#define PWM_CTL_MSEN4_LSB 31
#define PWM_STA HW_REGISTER_RW( 0x7e20c004 )
#define PWM_STA_MASK 0x00001fff
#define PWM_STA_WIDTH 13
#define PWM_STA_RESET 0000000000
#define PWM_STA_FULL1_BITS 0:0
#define PWM_STA_FULL1_SET 0x00000001
#define PWM_STA_FULL1_CLR 0xfffffffe
#define PWM_STA_FULL1_MSB 0
#define PWM_STA_FULL1_LSB 0
#define PWM_STA_EMPT1_BITS 1:1
#define PWM_STA_EMPT1_SET 0x00000002
#define PWM_STA_EMPT1_CLR 0xfffffffd
#define PWM_STA_EMPT1_MSB 1
#define PWM_STA_EMPT1_LSB 1
#define PWM_STA_WERR1_BITS 2:2
#define PWM_STA_WERR1_SET 0x00000004
#define PWM_STA_WERR1_CLR 0xfffffffb
#define PWM_STA_WERR1_MSB 2
#define PWM_STA_WERR1_LSB 2
#define PWM_STA_RERR1_BITS 3:3
#define PWM_STA_RERR1_SET 0x00000008
#define PWM_STA_RERR1_CLR 0xfffffff7
#define PWM_STA_RERR1_MSB 3
#define PWM_STA_RERR1_LSB 3
#define PWM_STA_GAPO1_BITS 4:4
#define PWM_STA_GAPO1_SET 0x00000010
#define PWM_STA_GAPO1_CLR 0xffffffef
#define PWM_STA_GAPO1_MSB 4
#define PWM_STA_GAPO1_LSB 4
#define PWM_STA_GAPO2_BITS 5:5
#define PWM_STA_GAPO2_SET 0x00000020
#define PWM_STA_GAPO2_CLR 0xffffffdf
#define PWM_STA_GAPO2_MSB 5
#define PWM_STA_GAPO2_LSB 5
#define PWM_STA_GAPO3_BITS 6:6
#define PWM_STA_GAPO3_SET 0x00000040
#define PWM_STA_GAPO3_CLR 0xffffffbf
#define PWM_STA_GAPO3_MSB 6
#define PWM_STA_GAPO3_LSB 6
#define PWM_STA_GAPO4_BITS 7:7
#define PWM_STA_GAPO4_SET 0x00000080
#define PWM_STA_GAPO4_CLR 0xffffff7f
#define PWM_STA_GAPO4_MSB 7
#define PWM_STA_GAPO4_LSB 7
#define PWM_STA_BERR_BITS 8:8
#define PWM_STA_BERR_SET 0x00000100
#define PWM_STA_BERR_CLR 0xfffffeff
#define PWM_STA_BERR_MSB 8
#define PWM_STA_BERR_LSB 8
#define PWM_STA_STA1_BITS 9:9
#define PWM_STA_STA1_SET 0x00000200
#define PWM_STA_STA1_CLR 0xfffffdff
#define PWM_STA_STA1_MSB 9
#define PWM_STA_STA1_LSB 9
#define PWM_STA_STA2_BITS 10:10
#define PWM_STA_STA2_SET 0x00000400
#define PWM_STA_STA2_CLR 0xfffffbff
#define PWM_STA_STA2_MSB 10
#define PWM_STA_STA2_LSB 10
#define PWM_STA_STA3_BITS 11:11
#define PWM_STA_STA3_SET 0x00000800
#define PWM_STA_STA3_CLR 0xfffff7ff
#define PWM_STA_STA3_MSB 11
#define PWM_STA_STA3_LSB 11
#define PWM_STA_STA4_BITS 12:12
#define PWM_STA_STA4_SET 0x00001000
#define PWM_STA_STA4_CLR 0xffffefff
#define PWM_STA_STA4_MSB 12
#define PWM_STA_STA4_LSB 12
#define PWM_DMAC HW_REGISTER_RW( 0x7e20c008 )
#define PWM_DMAC_MASK 0x8000ffff
#define PWM_DMAC_WIDTH 32
#define PWM_DMAC_RESET 0x00000707
#define PWM_DMAC_DREQ_BITS 7:0
#define PWM_DMAC_DREQ_SET 0x000000ff
#define PWM_DMAC_DREQ_CLR 0xffffff00
#define PWM_DMAC_DREQ_MSB 7
#define PWM_DMAC_DREQ_LSB 0
#define PWM_DMAC_PANIC_BITS 15:8
#define PWM_DMAC_PANIC_SET 0x0000ff00
#define PWM_DMAC_PANIC_CLR 0xffff00ff
#define PWM_DMAC_PANIC_MSB 15
#define PWM_DMAC_PANIC_LSB 8
#define PWM_DMAC_ENAB_BITS 31:31
#define PWM_DMAC_ENAB_SET 0x80000000
#define PWM_DMAC_ENAB_CLR 0x7fffffff
#define PWM_DMAC_ENAB_MSB 31
#define PWM_DMAC_ENAB_LSB 31
#define PWM_RNG1 HW_REGISTER_RW( 0x7e20c010 )
#define PWM_RNG1_MASK 0xffffffff
#define PWM_RNG1_WIDTH 32
#define PWM_RNG1_RESET 0x00000020
#define PWM_DAT1 HW_REGISTER_RW( 0x7e20c014 )
#define PWM_DAT1_MASK 0xffffffff
#define PWM_DAT1_WIDTH 32
#define PWM_DAT1_RESET 0000000000
#define PWM_FIF1 HW_REGISTER_RW( 0x7e20c018 )
#define PWM_FIF1_MASK 0xffffffff
#define PWM_FIF1_WIDTH 32
#define PWM_FIF1_RESET 0000000000
#define PWM_RNG2 HW_REGISTER_RW( 0x7e20c020 )
#define PWM_RNG2_MASK 0xffffffff
#define PWM_RNG2_WIDTH 32
#define PWM_RNG2_RESET 0x00000020
#define PWM_DAT2 HW_REGISTER_RW( 0x7e20c024 )
#define PWM_DAT2_MASK 0xffffffff
#define PWM_DAT2_WIDTH 32
#define PWM_DAT2_RESET 0000000000
#define PWM_RNG3 HW_REGISTER_RW( 0x7e20c030 )
#define PWM_RNG3_MASK 0000000000
#define PWM_RNG3_WIDTH 0
#define PWM_RNG3_RESET 0x00000020
#define PWM_DAT3 HW_REGISTER_RW( 0x7e20c034 )
#define PWM_DAT3_MASK 0000000000
#define PWM_DAT3_WIDTH 0
#define PWM_DAT3_RESET 0000000000
#define PWM_RNG4 HW_REGISTER_RW( 0x7e20c040 )
#define PWM_RNG4_MASK 0000000000
#define PWM_RNG4_WIDTH 0
#define PWM_RNG4_RESET 0x00000020
#define PWM_DAT4 HW_REGISTER_RW( 0x7e20c044 )
#define PWM_DAT4_MASK 0000000000
#define PWM_DAT4_WIDTH 0
#define PWM_DAT4_RESET 0000000000

87
bcm2708_chip/register_map.h Executable file
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// This file was generated by the create_regs script
#ifndef _INCLUDE_BCM2708_CHIP_REGISTER_MAP_H
#define _INCLUDE_BCM2708_CHIP_REGISTER_MAP_H
#include "./../../../../chip/verification/code/vcinclude/multicore_sync.h"
#include "./../../../../chip/verification/code/vcinclude/ccp2tx.h"
#include "./../../../../chip/verification/code/vcinclude/intctrl0.h"
#include "./../../../../chip/verification/code/vcinclude/intctrl1.h"
#include "./../../../../chip/verification/code/vcinclude/timer.h"
#include "./../../../../chip/verification/code/vcinclude/txp.h"
#include "./../../../../chip/verification/code/vcinclude/jpeg_top.h"
#include "./../../../../chip/verification/code/vcinclude/mphi.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma0.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma1.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma2.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma3.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma4.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma5.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma6.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite7.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite8.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite9.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite10.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite11.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite12.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite13.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_lite14.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma_top.h"
#include "./../../../../chip/verification/code/vcinclude/nexus_uba.h"
#include "./../../../../chip/verification/code/vcinclude/system_arbiter_ctrl.h"
#include "./../../../../chip/verification/code/vcinclude/axi_performance0.h"
#include "./../../../../chip/verification/code/vcinclude/apb_async_bridge_ctrl.h"
#include "./../../../../chip/verification/code/vcinclude/cpr_powman.h"
#include "./../../../../chip/verification/code/vcinclude/cpr_clkman.h"
#include "./../../../../chip/verification/code/vcinclude/cpr_apb2wtap.h"
#include "./../../../../chip/verification/code/vcinclude/cpr_avs2wtap.h"
#include "./../../../../chip/verification/code/vcinclude/rng.h"
#include "./../../../../chip/verification/code/vcinclude/sdc_ctrl.h"
#include "./../../../../chip/verification/code/vcinclude/l2_cache_ctrl.h"
#include "./../../../../chip/verification/code/vcinclude/vpu_l1_cache_ctrl.h"
#include "./../../../../chip/verification/code/vcinclude/vpu_arb_ctrl.h"
#include "./../../../../chip/verification/code/vcinclude/axi_dma15.h"
#include "./../../../../chip/verification/code/vcinclude/sdc_addr_front.h"
#include "./../../../../chip/verification/code/vcinclude/sdc_dq_front.h"
#include "./../../../../chip/verification/code/vcinclude/axi_performance1.h"
#include "./../../../../chip/verification/code/vcinclude/hvs.h"
#include "./../../../../chip/verification/code/vcinclude/h264.h"
#include "./../../../../chip/verification/code/vcinclude/isp.h"
#include "./../../../../chip/verification/code/vcinclude/v3d.h"
#include "./../../../../chip/verification/code/vcinclude/usb.h"
#include "./../../../../chip/verification/code/vcinclude/smi.h"
#include "./../../../../chip/verification/code/vcinclude/emmc.h"
#include "./../../../../chip/verification/code/vcinclude/dsi4.h"
#include "./../../../../chip/verification/code/vcinclude/hdmicore.h"
#include "./../../../../chip/verification/code/vcinclude/ave_in.h"
#include "./../../../../chip/verification/code/vcinclude/ave_out.h"
#include "./../../../../chip/verification/code/vcinclude/gpio.h"
#include "./../../../../chip/verification/code/vcinclude/uart_arm.h"
#include "./../../../../chip/verification/code/vcinclude/sdhost.h"
#include "./../../../../chip/verification/code/vcinclude/pcm.h"
#include "./../../../../chip/verification/code/vcinclude/spi_master.h"
#include "./../../../../chip/verification/code/vcinclude/i2c0.h"
#include "./../../../../chip/verification/code/vcinclude/pixel_valve0.h"
#include "./../../../../chip/verification/code/vcinclude/pixel_valve1.h"
#include "./../../../../chip/verification/code/vcinclude/dpi.h"
#include "./../../../../chip/verification/code/vcinclude/dsi.h"
#include "./../../../../chip/verification/code/vcinclude/testbus.h"
#include "./../../../../chip/verification/code/vcinclude/fpga_peripheral.h"
#include "./../../../../chip/verification/code/vcinclude/fpga_microblaze.h"
#include "./../../../../chip/verification/code/vcinclude/pwm.h"
#include "./../../../../chip/verification/code/vcinclude/perfmon.h"
#include "./../../../../chip/verification/code/vcinclude/tectl.h"
#include "./../../../../chip/verification/code/vcinclude/otp.h"
#include "./../../../../chip/verification/code/vcinclude/slimbus.h"
#include "./../../../../chip/verification/code/vcinclude/cpg.h"
#include "./../../../../chip/verification/code/vcinclude/tempsens.h"
#include "./../../../../chip/verification/code/vcinclude/i2c_spi_slv.h"
#include "./../../../../chip/verification/code/vcinclude/cam0.h"
#include "./../../../../chip/verification/code/vcinclude/cam1.h"
#include "./../../../../chip/verification/code/vcinclude/clkman_image.h"
#include "./../../../../chip/verification/code/vcinclude/i2c1.h"
#include "./../../../../chip/verification/code/vcinclude/i2c2.h"
#include "./../../../../chip/verification/code/vcinclude/vec.h"
#include "./../../../../chip/verification/code/vcinclude/pixel_valve2.h"
#include "./../../../../chip/verification/code/vcinclude/hdmi.h"
#include "./../../../../chip/verification/code/vcinclude/hdcp.h"
#include "./../../../../chip/verification/code/vcinclude/peri_image_arb_ctrl.h"
#endif

1774
bcm2708_chip/register_map_macros.h Executable file
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18
bcm2708_chip/rng.h Executable file
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// This file was generated by the create_regs script
#define RNG_BASE 0x7e104000
#define RNG_APB_ID 0x20726e67
#define RNG_CTRL HW_REGISTER_RW( 0x7e104000 )
#define RNG_CTRL_MASK 0xffffffff
#define RNG_CTRL_WIDTH 32
#define RNG_STATUS HW_REGISTER_RW( 0x7e104004 )
#define RNG_STATUS_MASK 0xffffffff
#define RNG_STATUS_WIDTH 32
#define RNG_DATA HW_REGISTER_RW( 0x7e104008 )
#define RNG_DATA_MASK 0xffffffff
#define RNG_DATA_WIDTH 32
#define RNG_FF_THRESHOLD HW_REGISTER_RW( 0x7e10400c )
#define RNG_FF_THRESHOLD_MASK 0xffffffff
#define RNG_FF_THRESHOLD_WIDTH 32
#define RNG_INT_MASK HW_REGISTER_RW( 0x7e104010 )
#define RNG_INT_MASK_MASK 0xffffffff
#define RNG_INT_MASK_WIDTH 32

43
bcm2708_chip/rng_a0.h Executable file
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#ifndef __BCM2708A0__
// This file was generated by the create_regs script
#define RNG_BASE 0x7e104000
#define RNG_APB_ID 0x20726e67
#define RNG_CTRL HW_REGISTER_RW( 0x7e104000 )
#define RNG_CTRL_MASK 0xffffffff
#define RNG_CTRL_WIDTH 32
#define RNG_STATUS HW_REGISTER_RW( 0x7e104004 )
#define RNG_STATUS_MASK 0xffffffff
#define RNG_STATUS_WIDTH 32
#define RNG_DATA HW_REGISTER_RW( 0x7e104008 )
#define RNG_DATA_MASK 0xffffffff
#define RNG_DATA_WIDTH 32
#define RNG_FF_THRESHOLD HW_REGISTER_RW( 0x7e10400c )
#define RNG_FF_THRESHOLD_MASK 0xffffffff
#define RNG_FF_THRESHOLD_WIDTH 32
#define RNG_INT_MASK HW_REGISTER_RW( 0x7e104010 )
#define RNG_INT_MASK_MASK 0xffffffff
#define RNG_INT_MASK_WIDTH 32
#else
// This file was generated by the create_regs script
#define RNG_BASE 0x7ee03000
#define RNG_APB_ID 0x20726e67
#define RNG_CTRL HW_REGISTER_RW( 0x7ee03000 )
#define RNG_CTRL_MASK 0xffffffff
#define RNG_CTRL_WIDTH 32
#define RNG_STATUS HW_REGISTER_RW( 0x7ee03004 )
#define RNG_STATUS_MASK 0xffffffff
#define RNG_STATUS_WIDTH 32
#define RNG_DATA HW_REGISTER_RW( 0x7ee03008 )
#define RNG_DATA_MASK 0xffffffff
#define RNG_DATA_WIDTH 32
#define RNG_FF_THRESHOLD HW_REGISTER_RW( 0x7ee0300c )
#define RNG_FF_THRESHOLD_MASK 0xffffffff
#define RNG_FF_THRESHOLD_WIDTH 32
#define RNG_INT_MASK HW_REGISTER_RW( 0x7ee03010 )
#define RNG_INT_MASK_MASK 0xffffffff
#define RNG_INT_MASK_WIDTH 32
#endif

44
bcm2708_chip/rnghw.h Executable file
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/*=============================================================================
Copyright (c) 2007 Broadcom Europe Limited. All rights reserved.
Project : BCM2707
Module : RNG hardware header
File : $RCSfile: rnghw.h,v $
Revision : $Revision: 1.2 $
FILE DESCRIPTION
Definition of bits within RNG hardware registers.
=============================================================================*/
#ifndef RNGHW_H
#define RNGHW_H
#define RNG_READFIELD(_w,_f) (((unsigned long)(_w) / _f) & (_f##_MASK))
enum
{
RNG_CTRL_RBG_2X = (1 << 1),
RNG_CTRL_RBG_EN = (1 << 0),
RNG_STATUS_WARM_CNT = (1 << 0),
RNG_STATUS_WARM_CNT_MASK = 0xfffff,
RNG_STATUS_VAL = (1 << 24),
RNG_STATUS_VAL_MASK = 0xff,
RNG_FF_THRESHOLD_MAX = 0x04,
// BCM2707_B0:
// RNG interrupt no longer uses Crypto local interrupt register
// It is connected to interrupt bit 52 : ISRC1_0 bit 52-32=20 (0x0100000)
// Mask has 6 IRQ/reg => floor(52/8)=6 Bits = 16:19
RNG_INT_MASK_ENABLE = (1 << 16),
RNG_INT_MASK_DISABLE = (0 << 16),
RNG_SIMCTRL_DEBUG = (1 << 0),
RNG_SIMCTRL_SECURE = (1 << 1)
};
#endif

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