171 lines
8.4 KiB
C
Executable File
171 lines
8.4 KiB
C
Executable File
//
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// Auxiliary I/O header file
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//
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#define AUX_IO_BASE 0x7E215000
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#define AUX_IRQ (AUX_IO_BASE+0x000)
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#define AUX_ENABLES (AUX_IO_BASE+0x004)
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#define AUX_ENABLE_MINIUART 0x01
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#define AUX_ENABLE_SPI0 0x02
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#define AUX_ENABLE_SPI1 0x04
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//
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// Micro UART
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//
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// Baud rate = sysclk/(8*(BAUD_REG+1))
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#define AUX_MU_IO_REG (AUX_IO_BASE+0x040) // Write=TX read=RX
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#define AUX_MU_BDLS_REG (AUX_IO_BASE+0x040) // Baudrate LS
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#define AUX_MU_BDMS_REG (AUX_IO_BASE+0x044) // Baudrate MS.
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#define AUX_MU_IER_REG (AUX_IO_BASE+0x044) // IRQ enbl. reg.
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#define AUX_MU_IER_RXIRQEN 0x01 //
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#define AUX_MU_IER_TXIRQEN 0x02 //
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// Line interrupts are not supported
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#define AUX_MU_IIR_REG (AUX_IO_BASE+0x048) // IRQ status reg
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#define AUX_MU_IIR_NOIRQS 0x01 // No irq pending
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#define AUX_MU_IIR_IRQ 0x06 // 10 = rec irq, 01 = tx irq
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// Timeout is not supported
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#define AUX_MU_FCR_REG (AUX_IO_BASE+0x048) // FIFO control reg
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#define AUX_MU_FCR_RXCLR 0x02 // Flush receive FF
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#define AUX_MU_FCR_TXCLR 0x04 // Flush transmit fifo
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#define AUX_MU_LCR_REG (AUX_IO_BASE+0x04C) // Line control reg.
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#define AUX_MU_LCR_7BITS 0x02 // 7 bits mode
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#define AUX_MU_LCR_8BITS 0x03 // 8 bits mode
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#define AUX_MU_LCR_BREAK 0x40 // send break
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#define AUX_MU_LCR_DLAB 0x80 // DLAB access
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// 5 & 6 bits are not supported
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// 2 stop bits are not supported
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// Parity bits are not supported
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#define AUX_MU_MCR_REG (AUX_IO_BASE+0x050) // Modem control reg.
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#define AUX_MU_MCR_RTS 0x02 // Set RTS high
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// DTR is not supported
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// Out1/2 are not supported
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// Loopback is not supported
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#define AUX_MU_LSR_REG (AUX_IO_BASE+0x054) // Line status reg.
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#define AUX_MU_LSR_DR 0x01 // Receive Data ready
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#define AUX_MU_LSR_OE 0x02 // Receiver overrun error
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#define AUX_MU_LSR_THRE 0x20 // Transmitter holding register
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#define AUX_MU_LSR_TEMT 0x40 // Transmitter empty
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// Parity bits (and thus errors) are not supported
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// Framing errors are not detected
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// Break detect is not (yet) supported
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#define AUX_MU_MSR_REG (AUX_IO_BASE+0x058) // Modem status reg.
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#define AUX_MU_MSR_CTS 0x10
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// Delta CTS not supported
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// DCE,DCD not supportred
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#define AUX_MU_SCRATCH (AUX_IO_BASE+0x05C) // Scratch reg.
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// None 16550 features
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#define AUX_MU_CNTL_REG (AUX_IO_BASE+0x060) // AUX control reg.
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#define AUX_MU_CNTL_REC_ENBL 0x01 // receiver enable
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#define AUX_MU_CNTL_TRN_ENBL 0x02 // transmitter enable
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#define AUX_MU_CNTL_AUTO_RTR 0x04 // RTR set by RX FF level
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#define AUX_MU_CNTL_AUTO_CTS 0x08 // CTS auto stops transmitter
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#define AUX_MU_CNTL_FLOW3 0x00 // Stop on RX FF 3 entries left
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#define AUX_MU_CNTL_FLOW2 0x10 // Stop on RX FF 2 entries left
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#define AUX_MU_CNTL_FLOW1 0x20 // Stop on RX FF 1 entries left
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#define AUX_MU_CNTL_FLOW4 0x30 // Stop on RX FF 4 entries left
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#define AUX_MU_CNTL_AURTRINV 0x40 // Invert AUTO RTR polarity
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#define AUX_MU_CNTL_AUCTSINV 0x80 // Invert AUTO CTS polarity
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#define AUX_MU_STAT_REG (AUX_IO_BASE+0x064) // AUX status reg.
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#define AUX_MU_STAT_RX_DATA 0x00000001 // RX FF has value
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#define AUX_MU_STAT_TX_SPACE 0x00000002 // TX FF has space (not full)
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#define AUX_MU_STAT_RX_IDLE 0x00000004 // Receiver is idle
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#define AUX_MU_STAT_TX_IDLE 0x00000008 // Transmitter is idle
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#define AUX_MU_STAT_RX_OFLW 0x00000010 // Receiver FF overflow error
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#define AUX_MU_STAT_TX_FULL 0x00000020 // Transmit FF full
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#define AUX_MU_STAT_RTR 0x00000040 // Status of the RTR line
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#define AUX_MU_STAT_CTS 0x00000080 // Status of the CTS line (fully synced)
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#define AUX_MU_STAT_TXEMPTY 0x00000100 // TX FF is empty
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#define AUX_MU_STAT_TXDONE 0x00000200 // TX FF is empty and TX is idle
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#define AUX_MU_STAT_RXFILL 0x00FF0000 // RX FF fill level
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#define AUX_MU_STAT_TXFILL 0xFF000000 // TX FF fill level
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#define AUX_MU_BAUD_REG (AUX_IO_BASE+0x068) // Baudrate reg (16 bits)
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// Baud rate = sysclk/(8*(BAUD_REG+1))
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//
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// SPI 0 (SPI1 in the device!)
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//
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#define AUX_SPI0_CNTL0_REG (AUX_IO_BASE+0x080) // control reg 0
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#define AUX_SPI_CNTL0_BITS 0x0000003F // Number of bits to send/receive
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#define AUX_SPI_CNTL0_OUTMS 0x00000040 // Shift MS bit out first)
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#define AUX_SPI_CNTL0_INVCLK 0x00000080 // Invert SPI_CLK
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#define AUX_SPI_CNTL0_OUTRISE 0x00000100 // data out leaves on rising clock edge
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#define AUX_SPI_CNTL0_OUTFALL 0x00000000 // data out leaves on falling clock edge
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#define AUX_SPI_CNTL0_FFCLR 0x00000200 // Reset fifos (Set and clear bit)
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#define AUX_SPI_CNTL0_INRISE 0x00000400 // data in on rising clock edge
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#define AUX_SPI_CNTL0_INFALL 0x00000000 // data in on falling clock edge
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#define AUX_SPI_CNTL0_SERENBL 0x00000800 // Serial enable (does not disable FFs)
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#define AUX_SPI_CNTL0_HOLD0 0x00000000 // Dout hold 0 sys clock cycles
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#define AUX_SPI_CNTL0_HOLD4 0x00001000 // Dout hold 4 sys clock cycle
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#define AUX_SPI_CNTL0_HOLD7 0x00002000 // Dout hold 7 sys clock cycles
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#define AUX_SPI_CNTL0_HOLD10 0x00003000 // Dout hold 10 sys clock cycles
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#define AUX_SPI_CNTL0_VARWID 0x00004000 // Variable width mode (din[15-12]=bits)
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#define AUX_SPI_CNTL0_CSFROMFF 0x00008000 // CS pattern comesfrom MS 3 TX FIFO bits
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#define AUX_SPI_CNTL0_POSTIN 0x00010000 // Load last bit after cycles finished
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#define AUX_SPI_CNTL0_CS_HIGH 0x000E0000 // All CS are high
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#define AUX_SPI_CNTL0_CS0_N 0x000C0000 // CS 0 low
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#define AUX_SPI_CNTL0_CS1_N 0x000A0000 // CS 1 low
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#define AUX_SPI_CNTL0_CS2_N 0x00060000 // CS 2 low
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#define AUX_SPI_CNTL0_CSA_N 0x00000000 // ALL CS low (test only)
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#define AUX_SPI_CNTL0_SPEED 0xFFF00000 // SPI clock = sysclock/(2xspeed)
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#define AUX_SPI_CNTL0_SPEEDSHFT 20 // Speed shift left value
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#define AUX_SPI0_CNTL1_REG (AUX_IO_BASE+0x084) // control reg 1
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#define AUX_SPI_CNTL1_HOLDIN 0x00000001 // Do not clear DIN register at start
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#define AUX_SPI_CNTL1_INMS 0x00000002 // Shift data in MS first MS--->LS
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//#define AUX_SPI_CNTL1_CS_NOW 0x00000004 // Assert CS pattern now
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#define AUX_SPI_CNTL1_EMPTYIRQ 0x00000040 // IRQ on TX Fifo empty
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#define AUX_SPI_CNTL1_DONEIRQ 0x00000080 // IRQ on IDLE AND TxFifo empty
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#define AUX_SPI_CNTL1_CSPLUS1 0x00000100 // CS HI plus 1 bit
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#define AUX_SPI_CNTL1_CSPLUS2 0x00000200 // CS HI plus 2 bit
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#define AUX_SPI_CNTL1_CSPLUS3 0x00000300 // CS HI plus 3 bit
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#define AUX_SPI_CNTL1_CSPLUS4 0x00000400 // CS HI plus 4 bit
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#define AUX_SPI_CNTL1_CSPLUS5 0x00000500 // CS HI plus 5 bit
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#define AUX_SPI_CNTL1_CSPLUS6 0x00000600 // CS HI plus 6 bit
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#define AUX_SPI_CNTL1_CSPLUS7 0x00000700 // CS HI plus 7 bit
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#define AUX_SPI0_STAT_REG (AUX_IO_BASE+0x088) // Status reg.
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#define AUX_SPI_STAT_BITCNT 0x0000003F // Bits remaining to be shifted out
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#define AUX_SPI_STAT_BUSY 0x00000040 // FSM is busy
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#define AUX_SPI_STAT_RXEMPTY 0x00000080 // RX FF is empty
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#define AUX_SPI_STAT_RXFULL 0x00000100 // RX FF is full
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#define AUX_SPI_STAT_TXEMPTY 0x00000200 // TX FF is empyt
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#define AUX_SPI_STAT_TXFULL 0x00000400 // TX FF is full
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#define AUX_SPI_STAT_RXFILL 0x000F0000 // RX FF fill level
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#define AUX_SPI_STAT_TXFILL 0x0F000000 // TX FF fill level
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#define AUX_SPI0_PEEK_REG (AUX_IO_BASE+0x08C) // Read but do not take from FF
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#define AUX_SPI0_IO_REG (AUX_IO_BASE+0x0A0) // Write = TX, read=RX
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#define AUX_SPI0_TXHOLD_REG (AUX_IO_BASE+0x0B0) // Write = TX keep cs, read=RX
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//
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// SPI 1 (SPI2 in the device!)
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//
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#define AUX_SPI1_CNTL0_REG (AUX_IO_BASE+0x0C0)
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#define AUX_SPI1_CNTL1_REG (AUX_IO_BASE+0x0C4)
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#define AUX_SPI1_STAT_REG (AUX_IO_BASE+0x0C8)
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#define AUX_SPI1_PEEK_REG (AUX_IO_BASE+0x0CC)
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#define AUX_SPI1_IO_REG (AUX_IO_BASE+0x0E0)
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#define AUX_SPI1_TXHOLD_REG (AUX_IO_BASE+0x0F0) // Write = TX keep cs, read=RX
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//
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// Some usefull GPIO macros
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//
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#define CLR_GPIO(g) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))&= ~(7<<(((g)%10)*3))
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#define SET_GPIO_ALT(g,a) *(volatile uint32_t *)(GP_BASE+(((g)/10)<<2))|= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3))
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