200 lines
15 KiB
C
Executable File
200 lines
15 KiB
C
Executable File
// This file was generated by the create_regs script
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#define CAM0_BASE 0x7e800000
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#define CAM0_APB_ID 0x7563616d
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#define CAM0_CAMCTL HW_REGISTER_RW( 0x7e800000 )
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#define CAM0_CAMCTL_MASK 0xffffffff
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#define CAM0_CAMCTL_WIDTH 32
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#define CAM0_CAMCTL_RESET 0000000000
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#define CAM0_CAMSTA HW_REGISTER_RW( 0x7e800004 )
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#define CAM0_CAMSTA_MASK 0xffffffff
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#define CAM0_CAMSTA_WIDTH 32
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#define CAM0_CAMSTA_RESET 0000000000
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#define CAM0_CAMANA HW_REGISTER_RW( 0x7e800008 )
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#define CAM0_CAMANA_MASK 0xffffffff
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#define CAM0_CAMANA_WIDTH 32
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#define CAM0_CAMANA_RESET 0x00000777
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#define CAM0_CAMPRI HW_REGISTER_RW( 0x7e80000c )
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#define CAM0_CAMPRI_MASK 0xffffffff
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#define CAM0_CAMPRI_WIDTH 32
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#define CAM0_CAMPRI_RESET 0000000000
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#define CAM0_CAMCLK HW_REGISTER_RW( 0x7e800010 )
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#define CAM0_CAMCLK_MASK 0xffffffff
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#define CAM0_CAMCLK_WIDTH 32
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#define CAM0_CAMCLK_RESET 0x00000002
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#define CAM0_CAMCLT HW_REGISTER_RW( 0x7e800014 )
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#define CAM0_CAMCLT_MASK 0xffffffff
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#define CAM0_CAMCLT_WIDTH 32
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#define CAM0_CAMCLT_RESET 0000000000
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#define CAM0_CAMDAT0 HW_REGISTER_RW( 0x7e800018 )
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#define CAM0_CAMDAT0_MASK 0xffffffff
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#define CAM0_CAMDAT0_WIDTH 32
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#define CAM0_CAMDAT0_RESET 0x00000002
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#define CAM0_CAMDAT1 HW_REGISTER_RW( 0x7e80001c )
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#define CAM0_CAMDAT1_MASK 0xffffffff
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#define CAM0_CAMDAT1_WIDTH 32
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#define CAM0_CAMDAT1_RESET 0x00000002
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#define CAM0_CAMDAT2 HW_REGISTER_RW( 0x7e800020 )
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#define CAM0_CAMDAT2_MASK 0xffffffff
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#define CAM0_CAMDAT2_WIDTH 32
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#define CAM0_CAMDAT2_RESET 0x00000002
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#define CAM0_CAMDAT3 HW_REGISTER_RW( 0x7e800024 )
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#define CAM0_CAMDAT3_MASK 0xffffffff
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#define CAM0_CAMDAT3_WIDTH 32
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#define CAM0_CAMDAT3_RESET 0x00000002
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#define CAM0_CAMDLT HW_REGISTER_RW( 0x7e800028 )
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#define CAM0_CAMDLT_MASK 0xffffffff
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#define CAM0_CAMDLT_WIDTH 32
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#define CAM0_CAMDLT_RESET 0000000000
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#define CAM0_CAMCMP0 HW_REGISTER_RW( 0x7e80002c )
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#define CAM0_CAMCMP0_MASK 0xffffffff
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#define CAM0_CAMCMP0_WIDTH 32
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#define CAM0_CAMCMP0_RESET 0000000000
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#define CAM0_CAMCMP1 HW_REGISTER_RW( 0x7e800030 )
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#define CAM0_CAMCMP1_MASK 0xffffffff
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#define CAM0_CAMCMP1_WIDTH 32
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#define CAM0_CAMCMP1_RESET 0000000000
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#define CAM0_CAMCAP0 HW_REGISTER_RW( 0x7e800034 )
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#define CAM0_CAMCAP0_MASK 0xffffffff
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#define CAM0_CAMCAP0_WIDTH 32
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#define CAM0_CAMCAP0_RESET 0000000000
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#define CAM0_CAMCAP1 HW_REGISTER_RW( 0x7e800038 )
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#define CAM0_CAMCAP1_MASK 0xffffffff
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#define CAM0_CAMCAP1_WIDTH 32
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#define CAM0_CAMCAP1_RESET 0000000000
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#define CAM0_CAMDBG0 HW_REGISTER_RW( 0x7e8000f0 )
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#define CAM0_CAMDBG0_MASK 0xffffffff
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#define CAM0_CAMDBG0_WIDTH 32
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#define CAM0_CAMDBG0_RESET 0000000000
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#define CAM0_CAMDBG1 HW_REGISTER_RW( 0x7e8000f4 )
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#define CAM0_CAMDBG1_MASK 0xffffffff
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#define CAM0_CAMDBG1_WIDTH 32
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#define CAM0_CAMDBG1_RESET 0000000000
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#define CAM0_CAMDBG2 HW_REGISTER_RW( 0x7e8000f8 )
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#define CAM0_CAMDBG2_MASK 0xffffffff
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#define CAM0_CAMDBG2_WIDTH 32
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#define CAM0_CAMDBG2_RESET 0000000000
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#define CAM0_CAMDBG3 HW_REGISTER_RW( 0x7e8000fc )
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#define CAM0_CAMDBG3_MASK 0xffffffff
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#define CAM0_CAMDBG3_WIDTH 32
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#define CAM0_CAMDBG3_RESET 0000000000
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#define CAM0_CAMICTL HW_REGISTER_RW( 0x7e800100 )
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#define CAM0_CAMICTL_MASK 0xffffffff
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#define CAM0_CAMICTL_WIDTH 32
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#define CAM0_CAMICTL_RESET 0000000000
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#define CAM0_CAMISTA HW_REGISTER_RW( 0x7e800104 )
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#define CAM0_CAMISTA_MASK 0xffffffff
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#define CAM0_CAMISTA_WIDTH 32
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#define CAM0_CAMISTA_RESET 0000000000
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#define CAM0_CAMIDI0 HW_REGISTER_RW( 0x7e800108 )
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#define CAM0_CAMIDI0_MASK 0xffffffff
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#define CAM0_CAMIDI0_WIDTH 32
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#define CAM0_CAMIDI0_RESET 0000000000
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#define CAM0_CAMIPIPE HW_REGISTER_RW( 0x7e80010c )
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#define CAM0_CAMIPIPE_MASK 0xffffffff
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#define CAM0_CAMIPIPE_WIDTH 32
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#define CAM0_CAMIPIPE_RESET 0000000000
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#define CAM0_CAMIBSA0 HW_REGISTER_RW( 0x7e800110 )
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#define CAM0_CAMIBSA0_MASK 0xffffffff
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#define CAM0_CAMIBSA0_WIDTH 32
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#define CAM0_CAMIBSA0_RESET 0000000000
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#define CAM0_CAMIBEA0 HW_REGISTER_RW( 0x7e800114 )
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#define CAM0_CAMIBEA0_MASK 0xffffffff
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#define CAM0_CAMIBEA0_WIDTH 32
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#define CAM0_CAMIBEA0_RESET 0000000000
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#define CAM0_CAMIBLS HW_REGISTER_RW( 0x7e800118 )
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#define CAM0_CAMIBLS_MASK 0xffffffff
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#define CAM0_CAMIBLS_WIDTH 32
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#define CAM0_CAMIBLS_RESET 0000000000
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#define CAM0_CAMIBWP HW_REGISTER_RW( 0x7e80011c )
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#define CAM0_CAMIBWP_MASK 0xffffffff
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#define CAM0_CAMIBWP_WIDTH 32
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#define CAM0_CAMIBWP_RESET 0000000000
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#define CAM0_CAMIHWIN HW_REGISTER_RW( 0x7e800120 )
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#define CAM0_CAMIHWIN_MASK 0xffffffff
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#define CAM0_CAMIHWIN_WIDTH 32
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#define CAM0_CAMIHWIN_RESET 0000000000
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#define CAM0_CAMIHSTA HW_REGISTER_RW( 0x7e800124 )
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#define CAM0_CAMIHSTA_MASK 0xffffffff
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#define CAM0_CAMIHSTA_WIDTH 32
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#define CAM0_CAMIHSTA_RESET 0000000000
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#define CAM0_CAMIVWIN HW_REGISTER_RW( 0x7e800128 )
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#define CAM0_CAMIVWIN_MASK 0xffffffff
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#define CAM0_CAMIVWIN_WIDTH 32
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#define CAM0_CAMIVWIN_RESET 0000000000
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#define CAM0_CAMIVSTA HW_REGISTER_RW( 0x7e80012c )
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#define CAM0_CAMIVSTA_MASK 0xffffffff
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#define CAM0_CAMIVSTA_WIDTH 32
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#define CAM0_CAMIVSTA_RESET 0000000000
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#define CAM0_CAMICC HW_REGISTER_RW( 0x7e800130 )
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#define CAM0_CAMICC_MASK 0xffffffff
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#define CAM0_CAMICC_WIDTH 32
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#define CAM0_CAMICC_RESET 0000000000
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#define CAM0_CAMICS HW_REGISTER_RW( 0x7e800134 )
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#define CAM0_CAMICS_MASK 0xffffffff
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#define CAM0_CAMICS_WIDTH 32
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#define CAM0_CAMICS_RESET 0000000000
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#define CAM0_CAMIDC HW_REGISTER_RW( 0x7e800138 )
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#define CAM0_CAMIDC_MASK 0xffffffff
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#define CAM0_CAMIDC_WIDTH 32
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#define CAM0_CAMIDC_RESET 0000000000
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#define CAM0_CAMIDPO HW_REGISTER_RW( 0x7e80013c )
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#define CAM0_CAMIDPO_MASK 0xffffffff
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#define CAM0_CAMIDPO_WIDTH 32
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#define CAM0_CAMIDPO_RESET 0000000000
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#define CAM0_CAMIDCA HW_REGISTER_RW( 0x7e800140 )
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#define CAM0_CAMIDCA_MASK 0xffffffff
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#define CAM0_CAMIDCA_WIDTH 32
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#define CAM0_CAMIDCA_RESET 0000000000
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#define CAM0_CAMIDCD HW_REGISTER_RW( 0x7e800144 )
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#define CAM0_CAMIDCD_MASK 0xffffffff
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#define CAM0_CAMIDCD_WIDTH 32
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#define CAM0_CAMIDCD_RESET 0000000000
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#define CAM0_CAMIDS HW_REGISTER_RW( 0x7e800148 )
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#define CAM0_CAMIDS_MASK 0xffffffff
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#define CAM0_CAMIDS_WIDTH 32
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#define CAM0_CAMIDS_RESET 0000000000
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#define CAM0_CAMDCS HW_REGISTER_RW( 0x7e800200 )
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#define CAM0_CAMDCS_MASK 0xffffffff
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#define CAM0_CAMDCS_WIDTH 32
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#define CAM0_CAMDCS_RESET 0000000000
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#define CAM0_CAMDBSA0 HW_REGISTER_RW( 0x7e800204 )
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#define CAM0_CAMDBSA0_MASK 0xffffffff
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#define CAM0_CAMDBSA0_WIDTH 32
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#define CAM0_CAMDBSA0_RESET 0000000000
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#define CAM0_CAMDBEA0 HW_REGISTER_RW( 0x7e800208 )
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#define CAM0_CAMDBEA0_MASK 0xffffffff
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#define CAM0_CAMDBEA0_WIDTH 32
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#define CAM0_CAMDBEA0_RESET 0000000000
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#define CAM0_CAMDBWP HW_REGISTER_RW( 0x7e80020c )
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#define CAM0_CAMDBWP_MASK 0xffffffff
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#define CAM0_CAMDBWP_WIDTH 32
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#define CAM0_CAMDBWP_RESET 0000000000
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#define CAM0_CAMDBCTL HW_REGISTER_RW( 0x7e800300 )
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#define CAM0_CAMDBCTL_MASK 0xffffffff
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#define CAM0_CAMDBCTL_WIDTH 32
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#define CAM0_CAMDBCTL_RESET 0000000000
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#define CAM0_CAMIBSA1 HW_REGISTER_RW( 0x7e800304 )
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#define CAM0_CAMIBSA1_MASK 0xffffffff
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#define CAM0_CAMIBSA1_WIDTH 32
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#define CAM0_CAMIBSA1_RESET 0000000000
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#define CAM0_CAMIBEA1 HW_REGISTER_RW( 0x7e800308 )
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#define CAM0_CAMIBEA1_MASK 0xffffffff
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#define CAM0_CAMIBEA1_WIDTH 32
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#define CAM0_CAMIBEA1_RESET 0000000000
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#define CAM0_CAMIDI1 HW_REGISTER_RW( 0x7e80030c )
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#define CAM0_CAMIDI1_MASK 0xffffffff
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#define CAM0_CAMIDI1_WIDTH 32
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#define CAM0_CAMIDI1_RESET 0000000000
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#define CAM0_CAMDBSA1 HW_REGISTER_RW( 0x7e800310 )
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#define CAM0_CAMDBSA1_MASK 0xffffffff
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#define CAM0_CAMDBSA1_WIDTH 32
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#define CAM0_CAMDBSA1_RESET 0000000000
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#define CAM0_CAMDBEA1 HW_REGISTER_RW( 0x7e800314 )
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#define CAM0_CAMDBEA1_MASK 0xffffffff
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#define CAM0_CAMDBEA1_WIDTH 32
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#define CAM0_CAMDBEA1_RESET 0000000000
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#define CAM0_CAMMISC HW_REGISTER_RW( 0x7e800400 )
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#define CAM0_CAMMISC_MASK 0xffffffff
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#define CAM0_CAMMISC_WIDTH 32
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#define CAM0_CAMMISC_RESET 0000000000
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