132 lines
10 KiB
C
Executable File
132 lines
10 KiB
C
Executable File
// This file was generated by the create_regs script
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#define CAM1_BASE 0x7e801000
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#define CAM1_APB_ID 0x7563616d
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#define CAM1_CTL HW_REGISTER_RW( 0x7e801000 )
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#define CAM1_CTL_MASK 0xffffffff
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#define CAM1_CTL_WIDTH 32
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#define CAM1_CTL_RESET 0000000000
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#define CAM1_STA HW_REGISTER_RW( 0x7e801004 )
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#define CAM1_STA_MASK 0xffffffff
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#define CAM1_STA_WIDTH 32
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#define CAM1_STA_RESET 0000000000
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#define CAM1_ANA HW_REGISTER_RW( 0x7e801008 )
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#define CAM1_ANA_MASK 0xffffffff
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#define CAM1_ANA_WIDTH 32
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#define CAM1_ANA_RESET 0000000000
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#define CAM1_PRI HW_REGISTER_RW( 0x7e80100c )
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#define CAM1_PRI_MASK 0xffffffff
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#define CAM1_PRI_WIDTH 32
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#define CAM1_PRI_RESET 0000000000
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#define CAM1_CLK HW_REGISTER_RW( 0x7e801010 )
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#define CAM1_CLK_MASK 0xffffffff
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#define CAM1_CLK_WIDTH 32
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#define CAM1_CLK_RESET 0000000000
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#define CAM1_DAT0 HW_REGISTER_RW( 0x7e801014 )
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#define CAM1_DAT0_MASK 0xffffffff
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#define CAM1_DAT0_WIDTH 32
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#define CAM1_DAT0_RESET 0000000000
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#define CAM1_DAT1 HW_REGISTER_RW( 0x7e801018 )
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#define CAM1_DAT1_MASK 0xffffffff
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#define CAM1_DAT1_WIDTH 32
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#define CAM1_DAT1_RESET 0000000000
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#define CAM1_DAT2 HW_REGISTER_RW( 0x7e80101c )
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#define CAM1_DAT2_MASK 0xffffffff
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#define CAM1_DAT2_WIDTH 32
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#define CAM1_DAT2_RESET 0000000000
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#define CAM1_DAT3 HW_REGISTER_RW( 0x7e801020 )
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#define CAM1_DAT3_MASK 0xffffffff
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#define CAM1_DAT3_WIDTH 32
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#define CAM1_DAT3_RESET 0000000000
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#define CAM1_CMP0 HW_REGISTER_RW( 0x7e801024 )
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#define CAM1_CMP0_MASK 0xffffffff
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#define CAM1_CMP0_WIDTH 32
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#define CAM1_CMP0_RESET 0000000000
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#define CAM1_CMP1 HW_REGISTER_RW( 0x7e801028 )
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#define CAM1_CMP1_MASK 0xffffffff
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#define CAM1_CMP1_WIDTH 32
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#define CAM1_CMP1_RESET 0000000000
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#define CAM1_CAP0 HW_REGISTER_RW( 0x7e80102c )
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#define CAM1_CAP0_MASK 0xffffffff
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#define CAM1_CAP0_WIDTH 32
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#define CAM1_CAP0_RESET 0000000000
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#define CAM1_CAP1 HW_REGISTER_RW( 0x7e801030 )
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#define CAM1_CAP1_MASK 0xffffffff
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#define CAM1_CAP1_WIDTH 32
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#define CAM1_CAP1_RESET 0000000000
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#define CAM1_DBG0 HW_REGISTER_RW( 0x7e8010f0 )
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#define CAM1_DBG0_MASK 0xffffffff
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#define CAM1_DBG0_WIDTH 32
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#define CAM1_DBG0_RESET 0000000000
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#define CAM1_DBG1 HW_REGISTER_RW( 0x7e8010f4 )
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#define CAM1_DBG1_MASK 0xffffffff
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#define CAM1_DBG1_WIDTH 32
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#define CAM1_DBG1_RESET 0000000000
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#define CAM1_DBG2 HW_REGISTER_RW( 0x7e8010f8 )
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#define CAM1_DBG2_MASK 0xffffffff
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#define CAM1_DBG2_WIDTH 32
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#define CAM1_DBG2_RESET 0000000000
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#define CAM1_ICTL HW_REGISTER_RW( 0x7e801100 )
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#define CAM1_ICTL_MASK 0xffffffff
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#define CAM1_ICTL_WIDTH 32
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#define CAM1_ICTL_RESET 0000000000
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#define CAM1_ISTA HW_REGISTER_RW( 0x7e801104 )
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#define CAM1_ISTA_MASK 0xffffffff
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#define CAM1_ISTA_WIDTH 32
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#define CAM1_ISTA_RESET 0000000000
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#define CAM1_IDI HW_REGISTER_RW( 0x7e801108 )
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#define CAM1_IDI_MASK 0xffffffff
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#define CAM1_IDI_WIDTH 32
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#define CAM1_IDI_RESET 0000000000
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#define CAM1_IPIPE HW_REGISTER_RW( 0x7e80110c )
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#define CAM1_IPIPE_MASK 0xffffffff
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#define CAM1_IPIPE_WIDTH 32
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#define CAM1_IPIPE_RESET 0000000000
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#define CAM1_IBSA HW_REGISTER_RW( 0x7e801110 )
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#define CAM1_IBSA_MASK 0xffffffff
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#define CAM1_IBSA_WIDTH 32
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#define CAM1_IBSA_RESET 0000000000
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#define CAM1_IBEA HW_REGISTER_RW( 0x7e801114 )
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#define CAM1_IBEA_MASK 0xffffffff
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#define CAM1_IBEA_WIDTH 32
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#define CAM1_IBEA_RESET 0000000000
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#define CAM1_IBLS HW_REGISTER_RW( 0x7e801118 )
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#define CAM1_IBLS_MASK 0xffffffff
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#define CAM1_IBLS_WIDTH 32
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#define CAM1_IBLS_RESET 0000000000
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#define CAM1_IBWP HW_REGISTER_RW( 0x7e80111c )
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#define CAM1_IBWP_MASK 0xffffffff
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#define CAM1_IBWP_WIDTH 32
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#define CAM1_IBWP_RESET 0000000000
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#define CAM1_IHWIN HW_REGISTER_RW( 0x7e801120 )
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#define CAM1_IHWIN_MASK 0xffffffff
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#define CAM1_IHWIN_WIDTH 32
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#define CAM1_IHWIN_RESET 0000000000
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#define CAM1_IHSTA HW_REGISTER_RW( 0x7e801124 )
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#define CAM1_IHSTA_MASK 0xffffffff
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#define CAM1_IHSTA_WIDTH 32
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#define CAM1_IHSTA_RESET 0000000000
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#define CAM1_IVWIN HW_REGISTER_RW( 0x7e801128 )
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#define CAM1_IVWIN_MASK 0xffffffff
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#define CAM1_IVWIN_WIDTH 32
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#define CAM1_IVWIN_RESET 0000000000
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#define CAM1_IVSTA HW_REGISTER_RW( 0x7e80112c )
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#define CAM1_IVSTA_MASK 0xffffffff
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#define CAM1_IVSTA_WIDTH 32
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#define CAM1_IVSTA_RESET 0000000000
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#define CAM1_DCS HW_REGISTER_RW( 0x7e801200 )
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#define CAM1_DCS_MASK 0xffffffff
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#define CAM1_DCS_WIDTH 32
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#define CAM1_DCS_RESET 0000000000
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#define CAM1_DBSA HW_REGISTER_RW( 0x7e801204 )
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#define CAM1_DBSA_MASK 0xffffffff
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#define CAM1_DBSA_WIDTH 32
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#define CAM1_DBSA_RESET 0000000000
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#define CAM1_DBEA HW_REGISTER_RW( 0x7e801208 )
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#define CAM1_DBEA_MASK 0xffffffff
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#define CAM1_DBEA_WIDTH 32
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#define CAM1_DBEA_RESET 0000000000
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#define CAM1_DBWP HW_REGISTER_RW( 0x7e801208 )
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#define CAM1_DBWP_MASK 0xffffffff
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#define CAM1_DBWP_WIDTH 32
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#define CAM1_DBWP_RESET 0000000000
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