76 lines
5.3 KiB
C
Executable File
76 lines
5.3 KiB
C
Executable File
// This file was generated by the create_regs script
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#define CMI_PASSWORD 0x5a000000
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#define CMI_BASE 0x7e802000
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#define CMI_APB_ID 0x00636d69
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#define CMI_CAM0 HW_REGISTER_RW( 0x7e802000 )
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#define CMI_CAM0_MASK 0x0000003f
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#define CMI_CAM0_WIDTH 6
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#define CMI_CAM0_RESET 0000000000
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#define CMI_CAM0_RX1SRC_BITS 5:4
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#define CMI_CAM0_RX1SRC_SET 0x00000030
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#define CMI_CAM0_RX1SRC_CLR 0xffffffcf
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#define CMI_CAM0_RX1SRC_MSB 5
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#define CMI_CAM0_RX1SRC_LSB 4
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#define CMI_CAM0_RX0SRC_BITS 3:2
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#define CMI_CAM0_RX0SRC_SET 0x0000000c
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#define CMI_CAM0_RX0SRC_CLR 0xfffffff3
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#define CMI_CAM0_RX0SRC_MSB 3
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#define CMI_CAM0_RX0SRC_LSB 2
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#define CMI_CAM0_HSSRC_BITS 1:0
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#define CMI_CAM0_HSSRC_SET 0x00000003
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#define CMI_CAM0_HSSRC_CLR 0xfffffffc
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#define CMI_CAM0_HSSRC_MSB 1
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#define CMI_CAM0_HSSRC_LSB 0
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#define CMI_CAM1 HW_REGISTER_RW( 0x7e802004 )
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#define CMI_CAM1_MASK 0x000003ff
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#define CMI_CAM1_WIDTH 10
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#define CMI_CAM1_RESET 0000000000
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#define CMI_CAM1_RX3SRC_BITS 9:8
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#define CMI_CAM1_RX3SRC_SET 0x00000300
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#define CMI_CAM1_RX3SRC_CLR 0xfffffcff
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#define CMI_CAM1_RX3SRC_MSB 9
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#define CMI_CAM1_RX3SRC_LSB 8
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#define CMI_CAM1_RX2SRC_BITS 7:6
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#define CMI_CAM1_RX2SRC_SET 0x000000c0
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#define CMI_CAM1_RX2SRC_CLR 0xffffff3f
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#define CMI_CAM1_RX2SRC_MSB 7
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#define CMI_CAM1_RX2SRC_LSB 6
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#define CMI_CAM1_RX1SRC_BITS 5:4
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#define CMI_CAM1_RX1SRC_SET 0x00000030
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#define CMI_CAM1_RX1SRC_CLR 0xffffffcf
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#define CMI_CAM1_RX1SRC_MSB 5
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#define CMI_CAM1_RX1SRC_LSB 4
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#define CMI_CAM1_RX0SRC_BITS 3:2
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#define CMI_CAM1_RX0SRC_SET 0x0000000c
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#define CMI_CAM1_RX0SRC_CLR 0xfffffff3
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#define CMI_CAM1_RX0SRC_MSB 3
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#define CMI_CAM1_RX0SRC_LSB 2
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#define CMI_CAM1_HSSRC_BITS 1:0
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#define CMI_CAM1_HSSRC_SET 0x00000003
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#define CMI_CAM1_HSSRC_CLR 0xfffffffc
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#define CMI_CAM1_HSSRC_MSB 1
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#define CMI_CAM1_HSSRC_LSB 0
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#define CMI_CAMTEST HW_REGISTER_RW( 0x7e802008 )
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#define CMI_CAMTEST_MASK 0x0000001f
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#define CMI_CAMTEST_WIDTH 5
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#define CMI_CAMTEST_RESET 0000000000
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#define CMI_CAMTEST_ENAB_BITS 4:4
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#define CMI_CAMTEST_ENAB_SET 0x00000010
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#define CMI_CAMTEST_ENAB_CLR 0xffffffef
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#define CMI_CAMTEST_ENAB_MSB 4
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#define CMI_CAMTEST_ENAB_LSB 4
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#define CMI_CAMTEST_SRC_BITS 3:0
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#define CMI_CAMTEST_SRC_SET 0x0000000f
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#define CMI_CAMTEST_SRC_CLR 0xfffffff0
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#define CMI_CAMTEST_SRC_MSB 3
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#define CMI_CAMTEST_SRC_LSB 0
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#define CMI_USBCTL HW_REGISTER_RW( 0x7e802010 )
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#define CMI_USBCTL_MASK 0x00000040
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#define CMI_USBCTL_WIDTH 7
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#define CMI_USBCTL_RESET 0x00000040
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#define CMI_USBCTL_GATE_BITS 6:6
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#define CMI_USBCTL_GATE_SET 0x00000040
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#define CMI_USBCTL_GATE_CLR 0xffffffbf
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#define CMI_USBCTL_GATE_MSB 6
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#define CMI_USBCTL_GATE_LSB 6
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