841 lines
59 KiB
C
Executable File
841 lines
59 KiB
C
Executable File
// This file was generated by the create_regs script
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#define PM_PASSWORD 0x5a000000
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#define PM_BASE 0x7e100000
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#define PM_APB_ID 0x0000706d
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#define PM_GNRIC HW_REGISTER_RW( 0x7e100000 )
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#define PM_GNRIC_MASK 0x007f1fff
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#define PM_GNRIC_WIDTH 23
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#define PM_GNRIC_RESET 0000000000
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#define PM_GNRIC_CFG_BITS 22:16
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#define PM_GNRIC_CFG_SET 0x007f0000
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#define PM_GNRIC_CFG_CLR 0xff80ffff
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#define PM_GNRIC_CFG_MSB 22
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#define PM_GNRIC_CFG_LSB 16
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#define PM_GNRIC_ENAB_BITS 12:12
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#define PM_GNRIC_ENAB_SET 0x00001000
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#define PM_GNRIC_ENAB_CLR 0xffffefff
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#define PM_GNRIC_ENAB_MSB 12
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#define PM_GNRIC_ENAB_LSB 12
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#define PM_GNRIC_RSTN_BITS 11:6
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#define PM_GNRIC_RSTN_SET 0x00000fc0
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#define PM_GNRIC_RSTN_CLR 0xfffff03f
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#define PM_GNRIC_RSTN_MSB 11
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#define PM_GNRIC_RSTN_LSB 6
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#define PM_GNRIC_ISFUNC_BITS 5:5
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#define PM_GNRIC_ISFUNC_SET 0x00000020
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#define PM_GNRIC_ISFUNC_CLR 0xffffffdf
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#define PM_GNRIC_ISFUNC_MSB 5
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#define PM_GNRIC_ISFUNC_LSB 5
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#define PM_GNRIC_MRDONE_BITS 4:4
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#define PM_GNRIC_MRDONE_SET 0x00000010
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#define PM_GNRIC_MRDONE_CLR 0xffffffef
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#define PM_GNRIC_MRDONE_MSB 4
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#define PM_GNRIC_MRDONE_LSB 4
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#define PM_GNRIC_MEMREP_BITS 3:3
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#define PM_GNRIC_MEMREP_SET 0x00000008
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#define PM_GNRIC_MEMREP_CLR 0xfffffff7
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#define PM_GNRIC_MEMREP_MSB 3
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#define PM_GNRIC_MEMREP_LSB 3
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#define PM_GNRIC_ISPOW_BITS 2:2
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#define PM_GNRIC_ISPOW_SET 0x00000004
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#define PM_GNRIC_ISPOW_CLR 0xfffffffb
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#define PM_GNRIC_ISPOW_MSB 2
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#define PM_GNRIC_ISPOW_LSB 2
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#define PM_GNRIC_POWOK_BITS 1:1
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#define PM_GNRIC_POWOK_SET 0x00000002
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#define PM_GNRIC_POWOK_CLR 0xfffffffd
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#define PM_GNRIC_POWOK_MSB 1
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#define PM_GNRIC_POWOK_LSB 1
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#define PM_GNRIC_POWUP_BITS 0:0
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#define PM_GNRIC_POWUP_SET 0x00000001
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#define PM_GNRIC_POWUP_CLR 0xfffffffe
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#define PM_GNRIC_POWUP_MSB 0
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#define PM_GNRIC_POWUP_LSB 0
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#define PM_AUDIO HW_REGISTER_RW( 0x7e100004 )
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#define PM_AUDIO_MASK 0x003fffff
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#define PM_AUDIO_WIDTH 22
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#define PM_AUDIO_RESET 0x003000ff
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#define PM_AUDIO_RSTN_BITS 21:21
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#define PM_AUDIO_RSTN_SET 0x00200000
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#define PM_AUDIO_RSTN_CLR 0xffdfffff
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#define PM_AUDIO_RSTN_MSB 21
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#define PM_AUDIO_RSTN_LSB 21
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#define PM_AUDIO_CTRLEN_BITS 20:20
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#define PM_AUDIO_CTRLEN_SET 0x00100000
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#define PM_AUDIO_CTRLEN_CLR 0xffefffff
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#define PM_AUDIO_CTRLEN_MSB 20
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#define PM_AUDIO_CTRLEN_LSB 20
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#define PM_AUDIO_APSM_BITS 19:0
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#define PM_AUDIO_APSM_SET 0x000fffff
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#define PM_AUDIO_APSM_CLR 0xfff00000
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#define PM_AUDIO_APSM_MSB 19
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#define PM_AUDIO_APSM_LSB 0
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#define PM_STATUS HW_REGISTER_RO( 0x7e100018 )
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#define PM_STATUS_MASK 0x00ffffff
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#define PM_STATUS_WIDTH 24
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#define PM_STATUS_RESET 0000000000
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#define PM_IMAGE HW_REGISTER_RW( 0x7e100108 )
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#define PM_IMAGE_MASK 0x007f11ff
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#define PM_IMAGE_WIDTH 23
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#define PM_IMAGE_RESET 0x00001000
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#define PM_IMAGE_CFG_BITS 22:16
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#define PM_IMAGE_CFG_SET 0x007f0000
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#define PM_IMAGE_CFG_CLR 0xff80ffff
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#define PM_IMAGE_CFG_MSB 22
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#define PM_IMAGE_CFG_LSB 16
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#define PM_IMAGE_ENAB_BITS 12:12
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#define PM_IMAGE_ENAB_SET 0x00001000
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#define PM_IMAGE_ENAB_CLR 0xffffefff
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#define PM_IMAGE_ENAB_MSB 12
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#define PM_IMAGE_ENAB_LSB 12
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#define PM_IMAGE_ISPRSTN_BITS 8:8
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#define PM_IMAGE_ISPRSTN_SET 0x00000100
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#define PM_IMAGE_ISPRSTN_CLR 0xfffffeff
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#define PM_IMAGE_ISPRSTN_MSB 8
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#define PM_IMAGE_ISPRSTN_LSB 8
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#define PM_IMAGE_H264RSTN_BITS 7:7
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#define PM_IMAGE_H264RSTN_SET 0x00000080
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#define PM_IMAGE_H264RSTN_CLR 0xffffff7f
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#define PM_IMAGE_H264RSTN_MSB 7
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#define PM_IMAGE_H264RSTN_LSB 7
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#define PM_IMAGE_PERIRSTN_BITS 6:6
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#define PM_IMAGE_PERIRSTN_SET 0x00000040
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#define PM_IMAGE_PERIRSTN_CLR 0xffffffbf
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#define PM_IMAGE_PERIRSTN_MSB 6
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#define PM_IMAGE_PERIRSTN_LSB 6
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#define PM_IMAGE_ISFUNC_BITS 5:5
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#define PM_IMAGE_ISFUNC_SET 0x00000020
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#define PM_IMAGE_ISFUNC_CLR 0xffffffdf
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#define PM_IMAGE_ISFUNC_MSB 5
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#define PM_IMAGE_ISFUNC_LSB 5
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#define PM_IMAGE_MRDONE_BITS 4:4
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#define PM_IMAGE_MRDONE_SET 0x00000010
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#define PM_IMAGE_MRDONE_CLR 0xffffffef
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#define PM_IMAGE_MRDONE_MSB 4
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#define PM_IMAGE_MRDONE_LSB 4
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#define PM_IMAGE_MEMREP_BITS 3:3
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#define PM_IMAGE_MEMREP_SET 0x00000008
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#define PM_IMAGE_MEMREP_CLR 0xfffffff7
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#define PM_IMAGE_MEMREP_MSB 3
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#define PM_IMAGE_MEMREP_LSB 3
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#define PM_IMAGE_ISPOW_BITS 2:2
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#define PM_IMAGE_ISPOW_SET 0x00000004
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#define PM_IMAGE_ISPOW_CLR 0xfffffffb
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#define PM_IMAGE_ISPOW_MSB 2
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#define PM_IMAGE_ISPOW_LSB 2
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#define PM_IMAGE_POWOK_BITS 1:1
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#define PM_IMAGE_POWOK_SET 0x00000002
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#define PM_IMAGE_POWOK_CLR 0xfffffffd
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#define PM_IMAGE_POWOK_MSB 1
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#define PM_IMAGE_POWOK_LSB 1
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#define PM_IMAGE_POWUP_BITS 0:0
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#define PM_IMAGE_POWUP_SET 0x00000001
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#define PM_IMAGE_POWUP_CLR 0xfffffffe
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#define PM_IMAGE_POWUP_MSB 0
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#define PM_IMAGE_POWUP_LSB 0
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#define PM_GRAFX HW_REGISTER_RW( 0x7e10010c )
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#define PM_GRAFX_MASK 0x007f107f
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#define PM_GRAFX_WIDTH 23
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#define PM_GRAFX_RESET 0x00001000
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#define PM_GRAFX_CFG_BITS 22:16
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#define PM_GRAFX_CFG_SET 0x007f0000
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#define PM_GRAFX_CFG_CLR 0xff80ffff
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#define PM_GRAFX_CFG_MSB 22
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#define PM_GRAFX_CFG_LSB 16
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#define PM_GRAFX_ENAB_BITS 12:12
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#define PM_GRAFX_ENAB_SET 0x00001000
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#define PM_GRAFX_ENAB_CLR 0xffffefff
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#define PM_GRAFX_ENAB_MSB 12
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#define PM_GRAFX_ENAB_LSB 12
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#define PM_GRAFX_V3DRSTN_BITS 6:6
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#define PM_GRAFX_V3DRSTN_SET 0x00000040
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#define PM_GRAFX_V3DRSTN_CLR 0xffffffbf
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#define PM_GRAFX_V3DRSTN_MSB 6
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#define PM_GRAFX_V3DRSTN_LSB 6
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#define PM_GRAFX_ISFUNC_BITS 5:5
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#define PM_GRAFX_ISFUNC_SET 0x00000020
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#define PM_GRAFX_ISFUNC_CLR 0xffffffdf
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#define PM_GRAFX_ISFUNC_MSB 5
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#define PM_GRAFX_ISFUNC_LSB 5
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#define PM_GRAFX_MRDONE_BITS 4:4
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#define PM_GRAFX_MRDONE_SET 0x00000010
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#define PM_GRAFX_MRDONE_CLR 0xffffffef
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#define PM_GRAFX_MRDONE_MSB 4
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#define PM_GRAFX_MRDONE_LSB 4
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#define PM_GRAFX_MEMREP_BITS 3:3
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#define PM_GRAFX_MEMREP_SET 0x00000008
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#define PM_GRAFX_MEMREP_CLR 0xfffffff7
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#define PM_GRAFX_MEMREP_MSB 3
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#define PM_GRAFX_MEMREP_LSB 3
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#define PM_GRAFX_ISPOW_BITS 2:2
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#define PM_GRAFX_ISPOW_SET 0x00000004
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#define PM_GRAFX_ISPOW_CLR 0xfffffffb
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#define PM_GRAFX_ISPOW_MSB 2
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#define PM_GRAFX_ISPOW_LSB 2
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#define PM_GRAFX_POWOK_BITS 1:1
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#define PM_GRAFX_POWOK_SET 0x00000002
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#define PM_GRAFX_POWOK_CLR 0xfffffffd
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#define PM_GRAFX_POWOK_MSB 1
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#define PM_GRAFX_POWOK_LSB 1
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#define PM_GRAFX_POWUP_BITS 0:0
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#define PM_GRAFX_POWUP_SET 0x00000001
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#define PM_GRAFX_POWUP_CLR 0xfffffffe
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#define PM_GRAFX_POWUP_MSB 0
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#define PM_GRAFX_POWUP_LSB 0
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#define PM_PROC HW_REGISTER_RW( 0x7e100110 )
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#define PM_PROC_MASK 0x007f107f
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#define PM_PROC_WIDTH 23
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#define PM_PROC_RESET 0000000000
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#define PM_PROC_CFG_BITS 22:16
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#define PM_PROC_CFG_SET 0x007f0000
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#define PM_PROC_CFG_CLR 0xff80ffff
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#define PM_PROC_CFG_MSB 22
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#define PM_PROC_CFG_LSB 16
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#define PM_PROC_ENAB_BITS 12:12
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#define PM_PROC_ENAB_SET 0x00001000
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#define PM_PROC_ENAB_CLR 0xffffefff
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#define PM_PROC_ENAB_MSB 12
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#define PM_PROC_ENAB_LSB 12
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#define PM_PROC_ARMRSTN_BITS 6:6
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#define PM_PROC_ARMRSTN_SET 0x00000040
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#define PM_PROC_ARMRSTN_CLR 0xffffffbf
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#define PM_PROC_ARMRSTN_MSB 6
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#define PM_PROC_ARMRSTN_LSB 6
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#define PM_PROC_ISFUNC_BITS 5:5
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#define PM_PROC_ISFUNC_SET 0x00000020
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#define PM_PROC_ISFUNC_CLR 0xffffffdf
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#define PM_PROC_ISFUNC_MSB 5
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#define PM_PROC_ISFUNC_LSB 5
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#define PM_PROC_MRDONE_BITS 4:4
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#define PM_PROC_MRDONE_SET 0x00000010
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#define PM_PROC_MRDONE_CLR 0xffffffef
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#define PM_PROC_MRDONE_MSB 4
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#define PM_PROC_MRDONE_LSB 4
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#define PM_PROC_MEMREP_BITS 3:3
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#define PM_PROC_MEMREP_SET 0x00000008
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#define PM_PROC_MEMREP_CLR 0xfffffff7
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#define PM_PROC_MEMREP_MSB 3
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#define PM_PROC_MEMREP_LSB 3
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#define PM_PROC_ISPOW_BITS 2:2
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#define PM_PROC_ISPOW_SET 0x00000004
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#define PM_PROC_ISPOW_CLR 0xfffffffb
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#define PM_PROC_ISPOW_MSB 2
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#define PM_PROC_ISPOW_LSB 2
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#define PM_PROC_POWOK_BITS 1:1
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#define PM_PROC_POWOK_SET 0x00000002
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#define PM_PROC_POWOK_CLR 0xfffffffd
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#define PM_PROC_POWOK_MSB 1
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#define PM_PROC_POWOK_LSB 1
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#define PM_PROC_POWUP_BITS 0:0
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#define PM_PROC_POWUP_SET 0x00000001
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#define PM_PROC_POWUP_CLR 0xfffffffe
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#define PM_PROC_POWUP_MSB 0
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#define PM_PROC_POWUP_LSB 0
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#define PM_RSTC HW_REGISTER_RW( 0x7e10001c )
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#define PM_RSTC_MASK 0x00333333
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#define PM_RSTC_WIDTH 22
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#define PM_RSTC_RESET 0x00000102
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#define PM_RSTC_HRCFG_BITS 21:20
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#define PM_RSTC_HRCFG_SET 0x00300000
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#define PM_RSTC_HRCFG_CLR 0xffcfffff
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#define PM_RSTC_HRCFG_MSB 21
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#define PM_RSTC_HRCFG_LSB 20
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#define PM_RSTC_FRCFG_BITS 17:16
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#define PM_RSTC_FRCFG_SET 0x00030000
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#define PM_RSTC_FRCFG_CLR 0xfffcffff
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#define PM_RSTC_FRCFG_MSB 17
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#define PM_RSTC_FRCFG_LSB 16
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#define PM_RSTC_QRCFG_BITS 13:12
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#define PM_RSTC_QRCFG_SET 0x00003000
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#define PM_RSTC_QRCFG_CLR 0xffffcfff
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#define PM_RSTC_QRCFG_MSB 13
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#define PM_RSTC_QRCFG_LSB 12
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#define PM_RSTC_SRCFG_BITS 9:8
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#define PM_RSTC_SRCFG_SET 0x00000300
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#define PM_RSTC_SRCFG_CLR 0xfffffcff
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#define PM_RSTC_SRCFG_MSB 9
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#define PM_RSTC_SRCFG_LSB 8
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#define PM_RSTC_WRCFG_BITS 5:4
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#define PM_RSTC_WRCFG_SET 0x00000030
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#define PM_RSTC_WRCFG_CLR 0xffffffcf
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#define PM_RSTC_WRCFG_MSB 5
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#define PM_RSTC_WRCFG_LSB 4
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#define PM_RSTC_DRCFG_BITS 1:0
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#define PM_RSTC_DRCFG_SET 0x00000003
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#define PM_RSTC_DRCFG_CLR 0xfffffffc
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#define PM_RSTC_DRCFG_MSB 1
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#define PM_RSTC_DRCFG_LSB 0
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#define PM_RSTS HW_REGISTER_RW( 0x7e100020 )
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#define PM_RSTS_MASK 0x00001777
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#define PM_RSTS_WIDTH 13
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#define PM_RSTS_RESET 0x00001000
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#define PM_RSTS_HADPOR_BITS 12:12
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#define PM_RSTS_HADPOR_SET 0x00001000
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#define PM_RSTS_HADPOR_CLR 0xffffefff
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#define PM_RSTS_HADPOR_MSB 12
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#define PM_RSTS_HADPOR_LSB 12
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#define PM_RSTS_HADSRH_BITS 10:10
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#define PM_RSTS_HADSRH_SET 0x00000400
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#define PM_RSTS_HADSRH_CLR 0xfffffbff
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#define PM_RSTS_HADSRH_MSB 10
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#define PM_RSTS_HADSRH_LSB 10
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#define PM_RSTS_HADSRF_BITS 9:9
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#define PM_RSTS_HADSRF_SET 0x00000200
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#define PM_RSTS_HADSRF_CLR 0xfffffdff
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#define PM_RSTS_HADSRF_MSB 9
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#define PM_RSTS_HADSRF_LSB 9
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#define PM_RSTS_HADSRQ_BITS 8:8
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#define PM_RSTS_HADSRQ_SET 0x00000100
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#define PM_RSTS_HADSRQ_CLR 0xfffffeff
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#define PM_RSTS_HADSRQ_MSB 8
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#define PM_RSTS_HADSRQ_LSB 8
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#define PM_RSTS_HADWRH_BITS 6:6
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#define PM_RSTS_HADWRH_SET 0x00000040
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#define PM_RSTS_HADWRH_CLR 0xffffffbf
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#define PM_RSTS_HADWRH_MSB 6
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#define PM_RSTS_HADWRH_LSB 6
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#define PM_RSTS_HADWRF_BITS 5:5
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#define PM_RSTS_HADWRF_SET 0x00000020
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#define PM_RSTS_HADWRF_CLR 0xffffffdf
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#define PM_RSTS_HADWRF_MSB 5
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#define PM_RSTS_HADWRF_LSB 5
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#define PM_RSTS_HADWRQ_BITS 4:4
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#define PM_RSTS_HADWRQ_SET 0x00000010
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#define PM_RSTS_HADWRQ_CLR 0xffffffef
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#define PM_RSTS_HADWRQ_MSB 4
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#define PM_RSTS_HADWRQ_LSB 4
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#define PM_RSTS_HADDRH_BITS 2:2
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#define PM_RSTS_HADDRH_SET 0x00000004
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#define PM_RSTS_HADDRH_CLR 0xfffffffb
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#define PM_RSTS_HADDRH_MSB 2
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#define PM_RSTS_HADDRH_LSB 2
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#define PM_RSTS_HADDRF_BITS 1:1
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#define PM_RSTS_HADDRF_SET 0x00000002
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#define PM_RSTS_HADDRF_CLR 0xfffffffd
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#define PM_RSTS_HADDRF_MSB 1
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#define PM_RSTS_HADDRF_LSB 1
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#define PM_RSTS_HADDRQ_BITS 0:0
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#define PM_RSTS_HADDRQ_SET 0x00000001
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#define PM_RSTS_HADDRQ_CLR 0xfffffffe
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#define PM_RSTS_HADDRQ_MSB 0
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#define PM_RSTS_HADDRQ_LSB 0
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#define PM_WDOG HW_REGISTER_RW( 0x7e100024 )
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#define PM_WDOG_MASK 0x000fffff
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#define PM_WDOG_WIDTH 20
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#define PM_WDOG_RESET 0000000000
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#define PM_WDOG_TIME_BITS 19:0
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#define PM_WDOG_TIME_SET 0x000fffff
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#define PM_WDOG_TIME_CLR 0xfff00000
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#define PM_WDOG_TIME_MSB 19
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#define PM_WDOG_TIME_LSB 0
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#define PM_PADS0 HW_REGISTER_RW( 0x7e100028 )
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#define PM_PADS0_MASK 0x0000003f
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#define PM_PADS0_WIDTH 6
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#define PM_PADS0_RESET 0x0000001b
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#define PM_PADS0_DRIVE_BITS 2:0
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#define PM_PADS0_DRIVE_SET 0x00000007
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#define PM_PADS0_DRIVE_CLR 0xfffffff8
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#define PM_PADS0_DRIVE_MSB 2
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#define PM_PADS0_DRIVE_LSB 0
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#define PM_PADS0_HYST_BITS 3:3
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#define PM_PADS0_HYST_SET 0x00000008
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#define PM_PADS0_HYST_CLR 0xfffffff7
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#define PM_PADS0_HYST_MSB 3
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#define PM_PADS0_HYST_LSB 3
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#define PM_PADS0_SLEW_BITS 4:4
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#define PM_PADS0_SLEW_SET 0x00000010
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#define PM_PADS0_SLEW_CLR 0xffffffef
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#define PM_PADS0_SLEW_MSB 4
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#define PM_PADS0_SLEW_LSB 4
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#define PM_PADS0_POWOK_BITS 5:5
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#define PM_PADS0_POWOK_SET 0x00000020
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#define PM_PADS0_POWOK_CLR 0xffffffdf
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#define PM_PADS0_POWOK_MSB 5
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#define PM_PADS0_POWOK_LSB 5
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#define PM_PADS2 HW_REGISTER_RW( 0x7e10002c )
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#define PM_PADS2_MASK 0x0000003f
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#define PM_PADS2_WIDTH 6
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#define PM_PADS2_RESET 0x0000001b
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#define PM_PADS2_DRIVE_BITS 2:0
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#define PM_PADS2_DRIVE_SET 0x00000007
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#define PM_PADS2_DRIVE_CLR 0xfffffff8
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#define PM_PADS2_DRIVE_MSB 2
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#define PM_PADS2_DRIVE_LSB 0
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#define PM_PADS2_HYST_BITS 3:3
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#define PM_PADS2_HYST_SET 0x00000008
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#define PM_PADS2_HYST_CLR 0xfffffff7
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#define PM_PADS2_HYST_MSB 3
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#define PM_PADS2_HYST_LSB 3
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#define PM_PADS2_SLEW_BITS 4:4
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#define PM_PADS2_SLEW_SET 0x00000010
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#define PM_PADS2_SLEW_CLR 0xffffffef
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#define PM_PADS2_SLEW_MSB 4
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#define PM_PADS2_SLEW_LSB 4
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#define PM_PADS2_POWOK_BITS 5:5
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#define PM_PADS2_POWOK_SET 0x00000020
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#define PM_PADS2_POWOK_CLR 0xffffffdf
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#define PM_PADS2_POWOK_MSB 5
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#define PM_PADS2_POWOK_LSB 5
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#define PM_PADS3 HW_REGISTER_RW( 0x7e100030 )
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#define PM_PADS3_MASK 0x0000003f
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#define PM_PADS3_WIDTH 6
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#define PM_PADS3_RESET 0x0000001b
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#define PM_PADS3_DRIVE_BITS 2:0
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#define PM_PADS3_DRIVE_SET 0x00000007
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#define PM_PADS3_DRIVE_CLR 0xfffffff8
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#define PM_PADS3_DRIVE_MSB 2
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#define PM_PADS3_DRIVE_LSB 0
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#define PM_PADS3_HYST_BITS 3:3
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#define PM_PADS3_HYST_SET 0x00000008
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#define PM_PADS3_HYST_CLR 0xfffffff7
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#define PM_PADS3_HYST_MSB 3
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#define PM_PADS3_HYST_LSB 3
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#define PM_PADS3_SLEW_BITS 4:4
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#define PM_PADS3_SLEW_SET 0x00000010
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#define PM_PADS3_SLEW_CLR 0xffffffef
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#define PM_PADS3_SLEW_MSB 4
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#define PM_PADS3_SLEW_LSB 4
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#define PM_PADS3_POWOK_BITS 5:5
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#define PM_PADS3_POWOK_SET 0x00000020
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#define PM_PADS3_POWOK_CLR 0xffffffdf
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#define PM_PADS3_POWOK_MSB 5
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#define PM_PADS3_POWOK_LSB 5
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#define PM_PADS4 HW_REGISTER_RW( 0x7e100034 )
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#define PM_PADS4_MASK 0x0000003f
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#define PM_PADS4_WIDTH 6
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#define PM_PADS4_RESET 0x0000001b
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#define PM_PADS4_DRIVE_BITS 2:0
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#define PM_PADS4_DRIVE_SET 0x00000007
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#define PM_PADS4_DRIVE_CLR 0xfffffff8
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#define PM_PADS4_DRIVE_MSB 2
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#define PM_PADS4_DRIVE_LSB 0
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#define PM_PADS4_HYST_BITS 3:3
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#define PM_PADS4_HYST_SET 0x00000008
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#define PM_PADS4_HYST_CLR 0xfffffff7
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#define PM_PADS4_HYST_MSB 3
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#define PM_PADS4_HYST_LSB 3
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#define PM_PADS4_SPARE_BITS 4:4
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#define PM_PADS4_SPARE_SET 0x00000010
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#define PM_PADS4_SPARE_CLR 0xffffffef
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#define PM_PADS4_SPARE_MSB 4
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#define PM_PADS4_SPARE_LSB 4
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#define PM_PADS4_POWOK_BITS 5:5
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#define PM_PADS4_POWOK_SET 0x00000020
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#define PM_PADS4_POWOK_CLR 0xffffffdf
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#define PM_PADS4_POWOK_MSB 5
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#define PM_PADS4_POWOK_LSB 5
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#define PM_PADS5 HW_REGISTER_RW( 0x7e100038 )
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#define PM_PADS5_MASK 0x0000007f
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#define PM_PADS5_WIDTH 7
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#define PM_PADS5_RESET 0x0000001b
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#define PM_PADS5_DRIVE_BITS 2:0
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#define PM_PADS5_DRIVE_SET 0x00000007
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#define PM_PADS5_DRIVE_CLR 0xfffffff8
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#define PM_PADS5_DRIVE_MSB 2
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#define PM_PADS5_DRIVE_LSB 0
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#define PM_PADS5_HYST_BITS 3:3
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#define PM_PADS5_HYST_SET 0x00000008
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#define PM_PADS5_HYST_CLR 0xfffffff7
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#define PM_PADS5_HYST_MSB 3
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#define PM_PADS5_HYST_LSB 3
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#define PM_PADS5_SLEW_BITS 4:4
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#define PM_PADS5_SLEW_SET 0x00000010
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#define PM_PADS5_SLEW_CLR 0xffffffef
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#define PM_PADS5_SLEW_MSB 4
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#define PM_PADS5_SLEW_LSB 4
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#define PM_PADS5_POWOK_BITS 5:5
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#define PM_PADS5_POWOK_SET 0x00000020
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#define PM_PADS5_POWOK_CLR 0xffffffdf
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#define PM_PADS5_POWOK_MSB 5
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#define PM_PADS5_POWOK_LSB 5
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#define PM_PADS5_I2CMODE_BITS 6:6
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#define PM_PADS5_I2CMODE_SET 0x00000040
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#define PM_PADS5_I2CMODE_CLR 0xffffffbf
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#define PM_PADS5_I2CMODE_MSB 6
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#define PM_PADS5_I2CMODE_LSB 6
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#define PM_PADS6 HW_REGISTER_RW( 0x7e10003c )
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#define PM_PADS6_MASK 0x00000123
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#define PM_PADS6_WIDTH 9
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#define PM_PADS6_RESET 0000000000
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#define PM_PADS6_DRIVE_BITS 1:0
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#define PM_PADS6_DRIVE_SET 0x00000003
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#define PM_PADS6_DRIVE_CLR 0xfffffffc
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#define PM_PADS6_DRIVE_MSB 1
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#define PM_PADS6_DRIVE_LSB 0
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#define PM_PADS6_POWOK_BITS 5:5
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#define PM_PADS6_POWOK_SET 0x00000020
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#define PM_PADS6_POWOK_CLR 0xffffffdf
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#define PM_PADS6_POWOK_MSB 5
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#define PM_PADS6_POWOK_LSB 5
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#define PM_PADS6_PD_BITS 8:8
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#define PM_PADS6_PD_SET 0x00000100
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#define PM_PADS6_PD_CLR 0xfffffeff
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#define PM_PADS6_PD_MSB 8
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#define PM_PADS6_PD_LSB 8
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#define PM_CAM0 HW_REGISTER_RW( 0x7e100044 )
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#define PM_CAM0_MASK 0x001fffff
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#define PM_CAM0_WIDTH 21
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#define PM_CAM0_RESET 0000000000
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#define PM_CAM0_CTRLEN_BITS 0:0
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#define PM_CAM0_CTRLEN_SET 0x00000001
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#define PM_CAM0_CTRLEN_CLR 0xfffffffe
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#define PM_CAM0_CTRLEN_MSB 0
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#define PM_CAM0_CTRLEN_LSB 0
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#define PM_CAM0_LDOLPEN_BITS 1:1
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#define PM_CAM0_LDOLPEN_SET 0x00000002
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#define PM_CAM0_LDOLPEN_CLR 0xfffffffd
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#define PM_CAM0_LDOLPEN_MSB 1
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#define PM_CAM0_LDOLPEN_LSB 1
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#define PM_CAM0_LDOHPEN_BITS 2:2
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#define PM_CAM0_LDOHPEN_SET 0x00000004
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#define PM_CAM0_LDOHPEN_CLR 0xfffffffb
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#define PM_CAM0_LDOHPEN_MSB 2
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#define PM_CAM0_LDOHPEN_LSB 2
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#define PM_CAM0_LDOCTRL_BITS 20:3
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#define PM_CAM0_LDOCTRL_SET 0x001ffff8
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#define PM_CAM0_LDOCTRL_CLR 0xffe00007
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#define PM_CAM0_LDOCTRL_MSB 20
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#define PM_CAM0_LDOCTRL_LSB 3
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#define PM_CAM1 HW_REGISTER_RW( 0x7e100048 )
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#define PM_CAM1_MASK 0x001fffff
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#define PM_CAM1_WIDTH 21
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#define PM_CAM1_RESET 0000000000
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#define PM_CAM1_CTRLEN_BITS 0:0
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#define PM_CAM1_CTRLEN_SET 0x00000001
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#define PM_CAM1_CTRLEN_CLR 0xfffffffe
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#define PM_CAM1_CTRLEN_MSB 0
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#define PM_CAM1_CTRLEN_LSB 0
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#define PM_CAM1_LDOLPEN_BITS 1:1
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#define PM_CAM1_LDOLPEN_SET 0x00000002
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#define PM_CAM1_LDOLPEN_CLR 0xfffffffd
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#define PM_CAM1_LDOLPEN_MSB 1
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#define PM_CAM1_LDOLPEN_LSB 1
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#define PM_CAM1_LDOHPEN_BITS 2:2
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#define PM_CAM1_LDOHPEN_SET 0x00000004
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#define PM_CAM1_LDOHPEN_CLR 0xfffffffb
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#define PM_CAM1_LDOHPEN_MSB 2
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#define PM_CAM1_LDOHPEN_LSB 2
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#define PM_CAM1_LDOCTRL_BITS 20:3
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#define PM_CAM1_LDOCTRL_SET 0x001ffff8
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#define PM_CAM1_LDOCTRL_CLR 0xffe00007
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#define PM_CAM1_LDOCTRL_MSB 20
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#define PM_CAM1_LDOCTRL_LSB 3
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#define PM_CCP2TX HW_REGISTER_RW( 0x7e10004c )
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#define PM_CCP2TX_MASK 0x0007ffff
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#define PM_CCP2TX_WIDTH 19
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#define PM_CCP2TX_RESET 0000000000
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#define PM_CCP2TX_CTRLEN_BITS 0:0
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#define PM_CCP2TX_CTRLEN_SET 0x00000001
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#define PM_CCP2TX_CTRLEN_CLR 0xfffffffe
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#define PM_CCP2TX_CTRLEN_MSB 0
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#define PM_CCP2TX_CTRLEN_LSB 0
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#define PM_CCP2TX_LDOEN_BITS 1:1
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#define PM_CCP2TX_LDOEN_SET 0x00000002
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#define PM_CCP2TX_LDOEN_CLR 0xfffffffd
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#define PM_CCP2TX_LDOEN_MSB 1
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#define PM_CCP2TX_LDOEN_LSB 1
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#define PM_CCP2TX_LDOCTRL_BITS 18:2
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#define PM_CCP2TX_LDOCTRL_SET 0x0007fffc
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#define PM_CCP2TX_LDOCTRL_CLR 0xfff80003
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#define PM_CCP2TX_LDOCTRL_MSB 18
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#define PM_CCP2TX_LDOCTRL_LSB 2
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#define PM_DSI0 HW_REGISTER_RW( 0x7e100050 )
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#define PM_DSI0_MASK 0x001fffff
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#define PM_DSI0_WIDTH 21
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#define PM_DSI0_RESET 0000000000
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#define PM_DSI0_CTRLEN_BITS 0:0
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#define PM_DSI0_CTRLEN_SET 0x00000001
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#define PM_DSI0_CTRLEN_CLR 0xfffffffe
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#define PM_DSI0_CTRLEN_MSB 0
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#define PM_DSI0_CTRLEN_LSB 0
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#define PM_DSI0_LDOLPEN_BITS 1:1
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#define PM_DSI0_LDOLPEN_SET 0x00000002
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#define PM_DSI0_LDOLPEN_CLR 0xfffffffd
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#define PM_DSI0_LDOLPEN_MSB 1
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#define PM_DSI0_LDOLPEN_LSB 1
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#define PM_DSI0_LDOHPEN_BITS 2:2
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#define PM_DSI0_LDOHPEN_SET 0x00000004
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#define PM_DSI0_LDOHPEN_CLR 0xfffffffb
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#define PM_DSI0_LDOHPEN_MSB 2
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#define PM_DSI0_LDOHPEN_LSB 2
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#define PM_DSI0_LDOCTRL_BITS 20:3
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#define PM_DSI0_LDOCTRL_SET 0x001ffff8
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#define PM_DSI0_LDOCTRL_CLR 0xffe00007
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#define PM_DSI0_LDOCTRL_MSB 20
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#define PM_DSI0_LDOCTRL_LSB 3
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#define PM_DSI1 HW_REGISTER_RW( 0x7e100054 )
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#define PM_DSI1_MASK 0x001fffff
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#define PM_DSI1_WIDTH 21
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#define PM_DSI1_RESET 0000000000
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#define PM_DSI1_CTRLEN_BITS 0:0
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#define PM_DSI1_CTRLEN_SET 0x00000001
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#define PM_DSI1_CTRLEN_CLR 0xfffffffe
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#define PM_DSI1_CTRLEN_MSB 0
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#define PM_DSI1_CTRLEN_LSB 0
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#define PM_DSI1_LDOLPEN_BITS 1:1
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#define PM_DSI1_LDOLPEN_SET 0x00000002
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#define PM_DSI1_LDOLPEN_CLR 0xfffffffd
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#define PM_DSI1_LDOLPEN_MSB 1
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#define PM_DSI1_LDOLPEN_LSB 1
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#define PM_DSI1_LDOHPEN_BITS 2:2
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#define PM_DSI1_LDOHPEN_SET 0x00000004
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#define PM_DSI1_LDOHPEN_CLR 0xfffffffb
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#define PM_DSI1_LDOHPEN_MSB 2
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#define PM_DSI1_LDOHPEN_LSB 2
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#define PM_DSI1_LDOCTRL_BITS 20:3
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#define PM_DSI1_LDOCTRL_SET 0x001ffff8
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#define PM_DSI1_LDOCTRL_CLR 0xffe00007
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#define PM_DSI1_LDOCTRL_MSB 20
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#define PM_DSI1_LDOCTRL_LSB 3
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#define PM_HDMI HW_REGISTER_RW( 0x7e100058 )
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#define PM_HDMI_MASK 0x000fffff
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#define PM_HDMI_WIDTH 20
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#define PM_HDMI_RESET 0x00080002
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#define PM_HDMI_CTRLEN_BITS 0:0
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#define PM_HDMI_CTRLEN_SET 0x00000001
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#define PM_HDMI_CTRLEN_CLR 0xfffffffe
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#define PM_HDMI_CTRLEN_MSB 0
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#define PM_HDMI_CTRLEN_LSB 0
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#define PM_HDMI_LDOPD_BITS 1:1
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#define PM_HDMI_LDOPD_SET 0x00000002
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#define PM_HDMI_LDOPD_CLR 0xfffffffd
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#define PM_HDMI_LDOPD_MSB 1
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#define PM_HDMI_LDOPD_LSB 1
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#define PM_HDMI_LDOCTRL_BITS 18:2
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#define PM_HDMI_LDOCTRL_SET 0x0007fffc
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#define PM_HDMI_LDOCTRL_CLR 0xfff80003
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#define PM_HDMI_LDOCTRL_MSB 18
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#define PM_HDMI_LDOCTRL_LSB 2
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#define PM_HDMI_RSTDR_BITS 19:19
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#define PM_HDMI_RSTDR_SET 0x00080000
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#define PM_HDMI_RSTDR_CLR 0xfff7ffff
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#define PM_HDMI_RSTDR_MSB 19
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#define PM_HDMI_RSTDR_LSB 19
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#define PM_USB HW_REGISTER_RW( 0x7e10005c )
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#define PM_USB_MASK 0x00000001
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#define PM_USB_WIDTH 1
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#define PM_USB_RESET 0000000000
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#define PM_USB_CTRLEN_BITS 0:0
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#define PM_USB_CTRLEN_SET 0x00000001
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#define PM_USB_CTRLEN_CLR 0xfffffffe
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#define PM_USB_CTRLEN_MSB 0
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#define PM_USB_CTRLEN_LSB 0
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#define PM_PXLDO HW_REGISTER_RW( 0x7e100060 )
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#define PM_PXLDO_MASK 0x0003ffff
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#define PM_PXLDO_WIDTH 18
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#define PM_PXLDO_RESET 0000000000
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#define PM_PXLDO_CTRL_BITS 15:0
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#define PM_PXLDO_CTRL_SET 0x0000ffff
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#define PM_PXLDO_CTRL_CLR 0xffff0000
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#define PM_PXLDO_CTRL_MSB 15
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#define PM_PXLDO_CTRL_LSB 0
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#define PM_PXLDO_RSTOSCDR_BITS 16:16
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#define PM_PXLDO_RSTOSCDR_SET 0x00010000
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#define PM_PXLDO_RSTOSCDR_CLR 0xfffeffff
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#define PM_PXLDO_RSTOSCDR_MSB 16
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#define PM_PXLDO_RSTOSCDR_LSB 16
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#define PM_PXLDO_RSTPLLDR_BITS 17:17
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#define PM_PXLDO_RSTPLLDR_SET 0x00020000
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#define PM_PXLDO_RSTPLLDR_CLR 0xfffdffff
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#define PM_PXLDO_RSTPLLDR_MSB 17
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#define PM_PXLDO_RSTPLLDR_LSB 17
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#define PM_PXBG HW_REGISTER_RW( 0x7e100064 )
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#define PM_PXBG_MASK 0x0000ffff
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#define PM_PXBG_WIDTH 16
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#define PM_PXBG_RESET 0000000000
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#define PM_PXBG_CTRL_BITS 15:0
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#define PM_PXBG_CTRL_SET 0x0000ffff
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#define PM_PXBG_CTRL_CLR 0xffff0000
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#define PM_PXBG_CTRL_MSB 15
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#define PM_PXBG_CTRL_LSB 0
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#define PM_DFT HW_REGISTER_RW( 0x7e100068 )
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#define PM_DFT_MASK 0x00000003
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#define PM_DFT_WIDTH 2
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#define PM_DFT_RESET 0000000000
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#define PM_DFT_ALLOWAUDIOCKSTOP_BITS 0:0
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#define PM_DFT_ALLOWAUDIOCKSTOP_SET 0x00000001
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#define PM_DFT_ALLOWAUDIOCKSTOP_CLR 0xfffffffe
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#define PM_DFT_ALLOWAUDIOCKSTOP_MSB 0
|
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#define PM_DFT_ALLOWAUDIOCKSTOP_LSB 0
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#define PM_DFT_STOPALLCLOCKS_BITS 1:1
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#define PM_DFT_STOPALLCLOCKS_SET 0x00000002
|
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#define PM_DFT_STOPALLCLOCKS_CLR 0xfffffffd
|
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#define PM_DFT_STOPALLCLOCKS_MSB 1
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#define PM_DFT_STOPALLCLOCKS_LSB 1
|
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#define PM_SMPS HW_REGISTER_RW( 0x7e10006c )
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#define PM_SMPS_MASK 0x00000007
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#define PM_SMPS_WIDTH 3
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#define PM_SMPS_RESET 0000000000
|
|
#define PM_SMPS_CTRLEN_BITS 0:0
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#define PM_SMPS_CTRLEN_SET 0x00000001
|
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#define PM_SMPS_CTRLEN_CLR 0xfffffffe
|
|
#define PM_SMPS_CTRLEN_MSB 0
|
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#define PM_SMPS_CTRLEN_LSB 0
|
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#define PM_SMPS_RSTDR_BITS 1:1
|
|
#define PM_SMPS_RSTDR_SET 0x00000002
|
|
#define PM_SMPS_RSTDR_CLR 0xfffffffd
|
|
#define PM_SMPS_RSTDR_MSB 1
|
|
#define PM_SMPS_RSTDR_LSB 1
|
|
#define PM_SMPS_UPEN_BITS 2:2
|
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#define PM_SMPS_UPEN_SET 0x00000004
|
|
#define PM_SMPS_UPEN_CLR 0xfffffffb
|
|
#define PM_SMPS_UPEN_MSB 2
|
|
#define PM_SMPS_UPEN_LSB 2
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|
#define PM_XOSC HW_REGISTER_RW( 0x7e100070 )
|
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#define PM_XOSC_MASK 0x00000001
|
|
#define PM_XOSC_WIDTH 1
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#define PM_XOSC_RESET 0000000000
|
|
#define PM_XOSC_USESEC_BITS 0:0
|
|
#define PM_XOSC_USESEC_SET 0x00000001
|
|
#define PM_XOSC_USESEC_CLR 0xfffffffe
|
|
#define PM_XOSC_USESEC_MSB 0
|
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#define PM_XOSC_USESEC_LSB 0
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|
#define PM_SPAREW HW_REGISTER_RW( 0x7e100074 )
|
|
#define PM_SPAREW_MASK 0x00ffffff
|
|
#define PM_SPAREW_WIDTH 24
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#define PM_SPAREW_RESET 0000000000
|
|
#define PM_SPAREW_SPARE_BITS 23:0
|
|
#define PM_SPAREW_SPARE_SET 0x00ffffff
|
|
#define PM_SPAREW_SPARE_CLR 0xff000000
|
|
#define PM_SPAREW_SPARE_MSB 23
|
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#define PM_SPAREW_SPARE_LSB 0
|
|
#define PM_SPARER HW_REGISTER_RO( 0x7e100078 )
|
|
#define PM_SPARER_MASK 0x00ffffff
|
|
#define PM_SPARER_WIDTH 24
|
|
#define PM_SPARER_RESET 0000000000
|
|
#define PM_SPARER_SPARE_BITS 23:0
|
|
#define PM_SPARER_SPARE_SET 0x00ffffff
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#define PM_SPARER_SPARE_CLR 0xff000000
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#define PM_SPARER_SPARE_MSB 23
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#define PM_SPARER_SPARE_LSB 0
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#define PM_AVS_RSTDR HW_REGISTER_RW( 0x7e10007c )
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#define PM_AVS_RSTDR_MASK 0x0000003f
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#define PM_AVS_RSTDR_WIDTH 6
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#define PM_AVS_RSTDR_RESET 0000000000
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#define PM_AVS_RSTDR_PERI_A_BITS 0:0
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#define PM_AVS_RSTDR_PERI_A_SET 0x00000001
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#define PM_AVS_RSTDR_PERI_A_CLR 0xfffffffe
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#define PM_AVS_RSTDR_PERI_A_MSB 0
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#define PM_AVS_RSTDR_PERI_A_LSB 0
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#define PM_AVS_RSTDR_SYSTEM_A_BITS 1:1
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#define PM_AVS_RSTDR_SYSTEM_A_SET 0x00000002
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#define PM_AVS_RSTDR_SYSTEM_A_CLR 0xfffffffd
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#define PM_AVS_RSTDR_SYSTEM_A_MSB 1
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#define PM_AVS_RSTDR_SYSTEM_A_LSB 1
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#define PM_AVS_RSTDR_H264_I_BITS 2:2
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#define PM_AVS_RSTDR_H264_I_SET 0x00000004
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#define PM_AVS_RSTDR_H264_I_CLR 0xfffffffb
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#define PM_AVS_RSTDR_H264_I_MSB 2
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#define PM_AVS_RSTDR_H264_I_LSB 2
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#define PM_AVS_RSTDR_V3D_G_BITS 3:3
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#define PM_AVS_RSTDR_V3D_G_SET 0x00000008
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#define PM_AVS_RSTDR_V3D_G_CLR 0xfffffff7
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#define PM_AVS_RSTDR_V3D_G_MSB 3
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#define PM_AVS_RSTDR_V3D_G_LSB 3
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#define PM_AVS_RSTDR_ARM_P_BITS 4:4
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#define PM_AVS_RSTDR_ARM_P_SET 0x00000010
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#define PM_AVS_RSTDR_ARM_P_CLR 0xffffffef
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#define PM_AVS_RSTDR_ARM_P_MSB 4
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#define PM_AVS_RSTDR_ARM_P_LSB 4
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#define PM_AVS_RSTDR_ROSC_BITS 5:5
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#define PM_AVS_RSTDR_ROSC_SET 0x00000020
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#define PM_AVS_RSTDR_ROSC_CLR 0xffffffdf
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#define PM_AVS_RSTDR_ROSC_MSB 5
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#define PM_AVS_RSTDR_ROSC_LSB 5
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#define PM_AVS_STAT HW_REGISTER_RW( 0x7e100080 )
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#define PM_AVS_STAT_MASK 0x0000001f
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#define PM_AVS_STAT_WIDTH 5
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#define PM_AVS_STAT_RESET 0000000000
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#define PM_AVS_STAT_ALERT_PERI_A_BITS 0:0
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#define PM_AVS_STAT_ALERT_PERI_A_SET 0x00000001
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#define PM_AVS_STAT_ALERT_PERI_A_CLR 0xfffffffe
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#define PM_AVS_STAT_ALERT_PERI_A_MSB 0
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#define PM_AVS_STAT_ALERT_PERI_A_LSB 0
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#define PM_AVS_STAT_ALERT_SYSTEM_A_BITS 1:1
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#define PM_AVS_STAT_ALERT_SYSTEM_A_SET 0x00000002
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#define PM_AVS_STAT_ALERT_SYSTEM_A_CLR 0xfffffffd
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#define PM_AVS_STAT_ALERT_SYSTEM_A_MSB 1
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#define PM_AVS_STAT_ALERT_SYSTEM_A_LSB 1
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#define PM_AVS_STAT_ALERT_H264_I_BITS 2:2
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#define PM_AVS_STAT_ALERT_H264_I_SET 0x00000004
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#define PM_AVS_STAT_ALERT_H264_I_CLR 0xfffffffb
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#define PM_AVS_STAT_ALERT_H264_I_MSB 2
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#define PM_AVS_STAT_ALERT_H264_I_LSB 2
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#define PM_AVS_STAT_ALERT_V3D_G_BITS 3:3
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#define PM_AVS_STAT_ALERT_V3D_G_SET 0x00000008
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#define PM_AVS_STAT_ALERT_V3D_G_CLR 0xfffffff7
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#define PM_AVS_STAT_ALERT_V3D_G_MSB 3
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#define PM_AVS_STAT_ALERT_V3D_G_LSB 3
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#define PM_AVS_STAT_ALERT_ARM_P_BITS 4:4
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#define PM_AVS_STAT_ALERT_ARM_P_SET 0x00000010
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#define PM_AVS_STAT_ALERT_ARM_P_CLR 0xffffffef
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#define PM_AVS_STAT_ALERT_ARM_P_MSB 4
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#define PM_AVS_STAT_ALERT_ARM_P_LSB 4
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#define PM_AVS_EVENT HW_REGISTER_RW( 0x7e100084 )
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#define PM_AVS_EVENT_MASK 0x0000001f
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#define PM_AVS_EVENT_WIDTH 5
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#define PM_AVS_EVENT_RESET 0000000000
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#define PM_AVS_EVENT_ALERT_PERI_A_BITS 0:0
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#define PM_AVS_EVENT_ALERT_PERI_A_SET 0x00000001
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#define PM_AVS_EVENT_ALERT_PERI_A_CLR 0xfffffffe
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#define PM_AVS_EVENT_ALERT_PERI_A_MSB 0
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#define PM_AVS_EVENT_ALERT_PERI_A_LSB 0
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#define PM_AVS_EVENT_ALERT_SYSTEM_A_BITS 1:1
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#define PM_AVS_EVENT_ALERT_SYSTEM_A_SET 0x00000002
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#define PM_AVS_EVENT_ALERT_SYSTEM_A_CLR 0xfffffffd
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#define PM_AVS_EVENT_ALERT_SYSTEM_A_MSB 1
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#define PM_AVS_EVENT_ALERT_SYSTEM_A_LSB 1
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#define PM_AVS_EVENT_ALERT_H264_I_BITS 2:2
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#define PM_AVS_EVENT_ALERT_H264_I_SET 0x00000004
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#define PM_AVS_EVENT_ALERT_H264_I_CLR 0xfffffffb
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#define PM_AVS_EVENT_ALERT_H264_I_MSB 2
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#define PM_AVS_EVENT_ALERT_H264_I_LSB 2
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#define PM_AVS_EVENT_ALERT_V3D_G_BITS 3:3
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#define PM_AVS_EVENT_ALERT_V3D_G_SET 0x00000008
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#define PM_AVS_EVENT_ALERT_V3D_G_CLR 0xfffffff7
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#define PM_AVS_EVENT_ALERT_V3D_G_MSB 3
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#define PM_AVS_EVENT_ALERT_V3D_G_LSB 3
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#define PM_AVS_EVENT_ALERT_ARM_P_BITS 4:4
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#define PM_AVS_EVENT_ALERT_ARM_P_SET 0x00000010
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#define PM_AVS_EVENT_ALERT_ARM_P_CLR 0xffffffef
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#define PM_AVS_EVENT_ALERT_ARM_P_MSB 4
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#define PM_AVS_EVENT_ALERT_ARM_P_LSB 4
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#define PM_AVS_INTEN HW_REGISTER_RW( 0x7e100088 )
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#define PM_AVS_INTEN_MASK 0x0000001f
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#define PM_AVS_INTEN_WIDTH 5
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#define PM_AVS_INTEN_RESET 0000000000
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#define PM_AVS_INTEN_ALERT_PERI_A_BITS 0:0
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#define PM_AVS_INTEN_ALERT_PERI_A_SET 0x00000001
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#define PM_AVS_INTEN_ALERT_PERI_A_CLR 0xfffffffe
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#define PM_AVS_INTEN_ALERT_PERI_A_MSB 0
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#define PM_AVS_INTEN_ALERT_PERI_A_LSB 0
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#define PM_AVS_INTEN_ALERT_SYSTEM_A_BITS 1:1
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#define PM_AVS_INTEN_ALERT_SYSTEM_A_SET 0x00000002
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#define PM_AVS_INTEN_ALERT_SYSTEM_A_CLR 0xfffffffd
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#define PM_AVS_INTEN_ALERT_SYSTEM_A_MSB 1
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#define PM_AVS_INTEN_ALERT_SYSTEM_A_LSB 1
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#define PM_AVS_INTEN_ALERT_H264_I_BITS 2:2
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#define PM_AVS_INTEN_ALERT_H264_I_SET 0x00000004
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#define PM_AVS_INTEN_ALERT_H264_I_CLR 0xfffffffb
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#define PM_AVS_INTEN_ALERT_H264_I_MSB 2
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#define PM_AVS_INTEN_ALERT_H264_I_LSB 2
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#define PM_AVS_INTEN_ALERT_V3D_G_BITS 3:3
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#define PM_AVS_INTEN_ALERT_V3D_G_SET 0x00000008
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#define PM_AVS_INTEN_ALERT_V3D_G_CLR 0xfffffff7
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#define PM_AVS_INTEN_ALERT_V3D_G_MSB 3
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#define PM_AVS_INTEN_ALERT_V3D_G_LSB 3
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#define PM_AVS_INTEN_ALERT_ARM_P_BITS 4:4
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#define PM_AVS_INTEN_ALERT_ARM_P_SET 0x00000010
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#define PM_AVS_INTEN_ALERT_ARM_P_CLR 0xffffffef
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#define PM_AVS_INTEN_ALERT_ARM_P_MSB 4
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#define PM_AVS_INTEN_ALERT_ARM_P_LSB 4
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#define PM_DUMMY HW_REGISTER_RO( 0x7e1000fc )
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#define PM_DUMMY_MASK 0x00000001
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#define PM_DUMMY_WIDTH 1
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#define PM_DUMMY_RESET 0x00000001
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#define PM_DUMMY_ONE_BITS 0:0
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#define PM_DUMMY_ONE_SET 0x00000001
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#define PM_DUMMY_ONE_CLR 0xfffffffe
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#define PM_DUMMY_ONE_MSB 0
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#define PM_DUMMY_ONE_LSB 0
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