434 lines
30 KiB
C
Executable File
434 lines
30 KiB
C
Executable File
// This file was generated by the create_regs script
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#define CS_BASE 0x7e802000
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#define CS_APB_ID 0x43534932
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#define CS_RC HW_REGISTER_RW( 0x7e802000 )
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#define CS_RC_MASK 0xffffc07f
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#define CS_RC_WIDTH 32
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#define CS_RC_RESET 0x77ce0000
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#define CS_RC_CTATADJ_MSB 31
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#define CS_RC_CTATADJ_LSB 28
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#define CS_RC_PTATADJ_MSB 27
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#define CS_RC_PTATADJ_LSB 24
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#define CS_RC_RPP_MSB 23
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#define CS_RC_RPP_LSB 20
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#define CS_RC_RNP_MSB 19
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#define CS_RC_RNP_LSB 19
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#define CS_RC_BPD_MSB 18
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#define CS_RC_BPD_LSB 18
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#define CS_RC_APD_MSB 17
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#define CS_RC_APD_LSB 17
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#define CS_RC_FOE_MSB 16
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#define CS_RC_FOE_LSB 16
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#define CS_RC_FOF_MSB 15
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#define CS_RC_FOF_LSB 15
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#define CS_RC_RSYN_MSB 14
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#define CS_RC_RSYN_LSB 14
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#define CS_RC_F16B_MSB 6
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#define CS_RC_F16B_LSB 6
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#define CS_RC_GEN_MSB 5
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#define CS_RC_GEN_LSB 5
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#define CS_RC_LENC_MSB 4
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#define CS_RC_LENC_LSB 4
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#define CS_RC_LEN4_MSB 3
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#define CS_RC_LEN4_LSB 3
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#define CS_RC_LEN3_MSB 2
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#define CS_RC_LEN3_LSB 2
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#define CS_RC_LEN2_MSB 1
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#define CS_RC_LEN2_LSB 1
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#define CS_RC_LEN1_MSB 0
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#define CS_RC_LEN1_LSB 0
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#define CS_RS HW_REGISTER_RW( 0x7e802004 )
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#define CS_RS_MASK 0x0000033f
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#define CS_RS_WIDTH 10
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#define CS_RS_RESET 0000000000
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#define CS_RS_IS1_MSB 9
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#define CS_RS_IS1_LSB 9
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#define CS_RS_IS0_MSB 8
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#define CS_RS_IS0_LSB 8
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#define CS_RS_OFF_MSB 5
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#define CS_RS_OFF_LSB 5
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#define CS_RS_OFP_MSB 4
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#define CS_RS_OFP_LSB 4
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#define CS_RS_PEC_MSB 3
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#define CS_RS_PEC_LSB 3
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#define CS_RS_PED_MSB 2
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#define CS_RS_PED_LSB 2
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#define CS_RS_OEB_MSB 1
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#define CS_RS_OEB_LSB 1
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#define CS_RS_GEF_MSB 0
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#define CS_RS_GEF_LSB 0
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#define CS_RDLS HW_REGISTER_RW( 0x7e802008 )
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#define CS_RDLS_MASK 0x3fffffff
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#define CS_RDLS_WIDTH 30
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#define CS_RDLS_RESET 0000000000
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#define CS_RDLS_CEC_MSB 29
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#define CS_RDLS_CEC_LSB 29
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#define CS_RDLS_ESEC_MSB 28
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#define CS_RDLS_ESEC_LSB 28
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#define CS_RDLS_EEEC_MSB 27
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#define CS_RDLS_EEEC_LSB 27
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#define CS_RDLS_SOTSEC_MSB 26
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#define CS_RDLS_SOTSEC_LSB 26
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#define CS_RDLS_SOTEC_MSB 25
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#define CS_RDLS_SOTEC_LSB 25
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#define CS_RDLS_ULPSC_MSB 24
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#define CS_RDLS_ULPSC_LSB 24
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#define CS_RDLS_CE4_MSB 23
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#define CS_RDLS_CE4_LSB 23
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#define CS_RDLS_ESE4_MSB 22
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#define CS_RDLS_ESE4_LSB 22
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#define CS_RDLS_EEE4_MSB 21
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#define CS_RDLS_EEE4_LSB 21
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#define CS_RDLS_SOTSE4_MSB 20
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#define CS_RDLS_SOTSE4_LSB 20
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#define CS_RDLS_SOTE4_MSB 19
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#define CS_RDLS_SOTE4_LSB 19
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#define CS_RDLS_ULPS4_MSB 18
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#define CS_RDLS_ULPS4_LSB 18
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#define CS_RDLS_CE3_MSB 17
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#define CS_RDLS_CE3_LSB 17
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#define CS_RDLS_ESE3_MSB 16
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#define CS_RDLS_ESE3_LSB 16
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#define CS_RDLS_EEE3_MSB 15
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#define CS_RDLS_EEE3_LSB 15
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#define CS_RDLS_SOTSE3_MSB 14
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#define CS_RDLS_SOTSE3_LSB 14
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#define CS_RDLS_SOTE3_MSB 13
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#define CS_RDLS_SOTE3_LSB 13
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#define CS_RDLS_ULPS3_MSB 12
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#define CS_RDLS_ULPS3_LSB 12
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#define CS_RDLS_CE2_MSB 11
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#define CS_RDLS_CE2_LSB 11
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#define CS_RDLS_ESE2_MSB 10
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#define CS_RDLS_ESE2_LSB 10
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#define CS_RDLS_EEE2_MSB 9
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#define CS_RDLS_EEE2_LSB 9
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#define CS_RDLS_SOTSE2_MSB 8
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#define CS_RDLS_SOTSE2_LSB 8
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#define CS_RDLS_SOTE2_MSB 7
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#define CS_RDLS_SOTE2_LSB 7
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#define CS_RDLS_ULPS2_MSB 6
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#define CS_RDLS_ULPS2_LSB 6
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#define CS_RDLS_CE1_MSB 5
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#define CS_RDLS_CE1_LSB 5
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#define CS_RDLS_ESE1_MSB 4
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#define CS_RDLS_ESE1_LSB 4
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#define CS_RDLS_EEE1_MSB 3
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#define CS_RDLS_EEE1_LSB 3
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#define CS_RDLS_SOTSE1_MSB 2
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#define CS_RDLS_SOTSE1_LSB 2
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#define CS_RDLS_SOTE1_MSB 1
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#define CS_RDLS_SOTE1_LSB 1
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#define CS_RDLS_ULPS1_MSB 0
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#define CS_RDLS_ULPS1_LSB 0
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#define CS_RGSP HW_REGISTER_RO( 0x7e80200c )
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#define CS_RGSP_MASK 0x00ffffff
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#define CS_RGSP_WIDTH 24
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#define CS_RGSP_DATA_MSB 23
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#define CS_RGSP_DATA_LSB 8
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#define CS_RGSP_VC_MSB 7
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#define CS_RGSP_VC_LSB 6
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#define CS_RGSP_DT_MSB 5
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#define CS_RGSP_DT_LSB 0
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#define CS_TREN HW_REGISTER_RW( 0x7e802010 )
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#define CS_TREN_MASK 0x000003ff
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#define CS_TREN_WIDTH 10
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#define CS_TREN_RESET 0000000000
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#define CS_TREN_TROVC_MSB 9
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#define CS_TREN_TROVC_LSB 9
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#define CS_TREN_TROV4_MSB 8
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#define CS_TREN_TROV4_LSB 8
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#define CS_TREN_TROV3_MSB 7
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#define CS_TREN_TROV3_LSB 7
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#define CS_TREN_TROV2_MSB 6
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#define CS_TREN_TROV2_LSB 6
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#define CS_TREN_TROV1_MSB 5
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#define CS_TREN_TROV1_LSB 5
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#define CS_TREN_TRENC_MSB 4
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#define CS_TREN_TRENC_LSB 4
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#define CS_TREN_TREN4_MSB 3
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#define CS_TREN_TREN4_LSB 3
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#define CS_TREN_TREN3_MSB 2
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#define CS_TREN_TREN3_LSB 2
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#define CS_TREN_TREN2_MSB 1
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#define CS_TREN_TREN2_LSB 1
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#define CS_TREN_TREN1_MSB 0
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#define CS_TREN_TREN1_LSB 0
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#define CS_THSSTO HW_REGISTER_RW( 0x7e802014 )
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#define CS_THSSTO_MASK 0x0000ffff
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#define CS_THSSTO_WIDTH 16
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#define CS_THSSTO_RESET 0000000000
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#define CS_THSSTO_THSSTO_MSB 15
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#define CS_THSSTO_THSSTO_LSB 0
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#define CS_THSSET HW_REGISTER_RW( 0x7e802018 )
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#define CS_THSSET_MASK 0x00000fff
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#define CS_THSSET_WIDTH 12
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#define CS_THSSET_RESET 0000000000
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#define CS_THSSET_TD_MSB 11
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#define CS_THSSET_TD_LSB 8
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#define CS_THSSET_HSMC_MSB 7
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#define CS_THSSET_HSMC_LSB 0
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#define CS_THSCKTO HW_REGISTER_RW( 0x7e80201c )
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#define CS_THSCKTO_MASK 0x0000ffff
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#define CS_THSCKTO_WIDTH 16
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#define CS_THSCKTO_RESET 0000000000
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#define CS_THSCKTO_THSCKTO_MSB 15
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#define CS_THSCKTO_THSCKTO_LSB 0
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#define CS_DBGDPHY HW_REGISTER_RO( 0x7e802080 )
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#define CS_DBGDPHY_MASK 0x000fffff
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#define CS_DBGDPHY_WIDTH 20
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#define CS_DBGDPHY__MSB 19
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#define CS_DBGDPHY__LSB 0
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#define CS_DBGMISC HW_REGISTER_RO( 0x7e802084 )
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#define CS_DBGMISC_MASK 0x000001ff
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#define CS_DBGMISC_WIDTH 9
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#define CS_DBGMISC__MSB 8
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#define CS_DBGMISC__LSB 0
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#define CS_TRIG HW_REGISTER_RO( 0x7e802088 )
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#define CS_TRIG_MASK 0x000fffff
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#define CS_TRIG_WIDTH 20
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#define CS_TRIG__MSB 19
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#define CS_TRIG__LSB 0
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#define CS_SRST HW_REGISTER_RW( 0x7e802090 )
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#define CS_SRST_MASK 0x00000001
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#define CS_SRST_WIDTH 1
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#define CS_SRST__MSB 0
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#define CS_SRST__LSB 0
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#define CS_RDR3 HW_REGISTER_RO( 0x7e802094 )
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#define CS_RDR3_MASK 0x00001fff
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#define CS_RDR3_WIDTH 13
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#define CS_RDR3__MSB 12
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#define CS_RDR3__LSB 0
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#define CS_RC0 HW_REGISTER_RW( 0x7e802100 )
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#define CS_RC0_MASK 0x1fff1f07
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#define CS_RC0_WIDTH 29
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#define CS_RC0_RESET 0000000000
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#define CS_RC0_LCIE_MSB 28
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#define CS_RC0_LCIE_LSB 16
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#define CS_RC0_GSPIE_MSB 12
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#define CS_RC0_GSPIE_LSB 12
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#define CS_RC0_LEIE_MSB 11
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#define CS_RC0_LEIE_LSB 11
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#define CS_RC0_LSIE_MSB 10
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#define CS_RC0_LSIE_LSB 10
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#define CS_RC0_FEIE_MSB 9
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#define CS_RC0_FEIE_LSB 9
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#define CS_RC0_FSIE_MSB 8
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#define CS_RC0_FSIE_LSB 8
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#define CS_RC0_VC_MSB 2
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#define CS_RC0_VC_LSB 1
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#define CS_RC0_CHEN_MSB 0
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#define CS_RC0_CHEN_LSB 0
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#define CS_RPC0 HW_REGISTER_RW( 0x7e802104 )
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#define CS_RPC0_MASK 0x01ff1f1f
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#define CS_RPC0_WIDTH 25
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#define CS_RPC0_RESET 0x00200000
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#define CS_RPC0_EBL_MSB 24
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#define CS_RPC0_EBL_LSB 16
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#define CS_RPC0_EAP_MSB 12
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#define CS_RPC0_EAP_LSB 12
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#define CS_RPC0_EP_MSB 11
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#define CS_RPC0_EP_LSB 8
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#define CS_RPC0_DAP_MSB 4
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#define CS_RPC0_DAP_LSB 4
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#define CS_RPC0_DP_MSB 3
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#define CS_RPC0_DP_LSB 0
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#define CS_RS0 HW_REGISTER_RW( 0x7e802108 )
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#define CS_RS0_MASK 0x01ffffff
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#define CS_RS0_WIDTH 25
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#define CS_RS0_RESET 0000000000
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#define CS_RS0_DBO_MSB 24
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#define CS_RS0_DBO_LSB 24
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#define CS_RS0_IBO_MSB 23
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#define CS_RS0_IBO_LSB 23
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#define CS_RS0_CRCE_MSB 22
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#define CS_RS0_CRCE_LSB 22
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#define CS_RS0_LCI_MSB 21
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#define CS_RS0_LCI_LSB 21
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#define CS_RS0_GSPI_MSB 20
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#define CS_RS0_GSPI_LSB 20
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#define CS_RS0_LEI_MSB 19
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#define CS_RS0_LEI_LSB 19
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#define CS_RS0_LSI_MSB 18
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#define CS_RS0_LSI_LSB 18
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#define CS_RS0_FEI_MSB 17
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#define CS_RS0_FEI_LSB 17
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#define CS_RS0_FSI_MSB 16
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#define CS_RS0_FSI_LSB 16
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#define CS_RS0_FNUM_MSB 15
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#define CS_RS0_FNUM_LSB 0
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#define CS_RSA0 HW_REGISTER_RW( 0x7e80210c )
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#define CS_RSA0_MASK 0x3fffffff
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#define CS_RSA0_WIDTH 30
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#define CS_RSA0_RESET 0000000000
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#define CS_RSA0__MSB 29
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#define CS_RSA0__LSB 0
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#define CS_REA0 HW_REGISTER_RW( 0x7e802110 )
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#define CS_REA0_MASK 0x3fffffff
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#define CS_REA0_WIDTH 30
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#define CS_REA0_RESET 0000000000
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#define CS_REA0__MSB 29
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#define CS_REA0__LSB 0
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#define CS_RWP0 HW_REGISTER_RO( 0x7e802114 )
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#define CS_RWP0_MASK 0x3fffffff
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#define CS_RWP0_WIDTH 30
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#define CS_RWP0__MSB 29
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#define CS_RWP0__LSB 0
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#define CS_RBC0 HW_REGISTER_RO( 0x7e802118 )
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#define CS_RBC0_MASK 0xffffffff
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#define CS_RBC0_WIDTH 32
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#define CS_RBC0__MSB 31
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#define CS_RBC0__LSB 0
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#define CS_RLS0 HW_REGISTER_RW( 0x7e80211c )
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#define CS_RLS0_MASK 0x0000ffff
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#define CS_RLS0_WIDTH 16
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#define CS_RLS0_RESET 0000000000
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#define CS_RLS0__MSB 15
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#define CS_RLS0__LSB 0
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#define CS_RDSA0 HW_REGISTER_RW( 0x7e802120 )
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#define CS_RDSA0_MASK 0x3fffffff
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#define CS_RDSA0_WIDTH 30
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#define CS_RDSA0_RESET 0000000000
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#define CS_RDSA0__MSB 29
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#define CS_RDSA0__LSB 0
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#define CS_RDEA0 HW_REGISTER_RW( 0x7e802124 )
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#define CS_RDEA0_MASK 0x3fffffff
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#define CS_RDEA0_WIDTH 30
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#define CS_RDEA0_RESET 0000000000
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#define CS_RDEA0__MSB 29
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#define CS_RDEA0__LSB 0
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#define CS_RDS0 HW_REGISTER_RW( 0x7e802128 )
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#define CS_RDS0_MASK 0x0000ffff
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#define CS_RDS0_WIDTH 16
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#define CS_RDS0_RESET 0000000000
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#define CS_RDS0__MSB 15
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#define CS_RDS0__LSB 0
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#define CS_DTOV0 HW_REGISTER_RW( 0x7e80212c )
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#define CS_DTOV0_MASK 0x00007f7f
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#define CS_DTOV0_WIDTH 15
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#define CS_DTOV0_RESET 0000000000
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#define CS_DTOV0_IMEN_MSB 14
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#define CS_DTOV0_IMEN_LSB 14
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#define CS_DTOV0_IMDT_MSB 13
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#define CS_DTOV0_IMDT_LSB 8
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#define CS_DTOV0_EMEN_MSB 6
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#define CS_DTOV0_EMEN_LSB 6
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#define CS_DTOV0_EMDT_MSB 5
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#define CS_DTOV0_EMDT_LSB 0
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#define CS_RC1 HW_REGISTER_RW( 0x7e802200 )
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#define CS_RC1_MASK 0x1fff1f07
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#define CS_RC1_WIDTH 29
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#define CS_RC1_RESET 0000000000
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#define CS_RC1_LCIE_MSB 28
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#define CS_RC1_LCIE_LSB 16
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#define CS_RC1_GSPIE_MSB 12
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#define CS_RC1_GSPIE_LSB 12
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#define CS_RC1_LEIE_MSB 11
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#define CS_RC1_LEIE_LSB 11
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#define CS_RC1_LSIE_MSB 10
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#define CS_RC1_LSIE_LSB 10
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#define CS_RC1_FEIE_MSB 9
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#define CS_RC1_FEIE_LSB 9
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#define CS_RC1_FSIE_MSB 8
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#define CS_RC1_FSIE_LSB 8
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#define CS_RC1_VC_MSB 2
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#define CS_RC1_VC_LSB 1
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#define CS_RC1_CHEN_MSB 0
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#define CS_RC1_CHEN_LSB 0
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#define CS_RPC1 HW_REGISTER_RW( 0x7e802204 )
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#define CS_RPC1_MASK 0x01ff1f1f
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#define CS_RPC1_WIDTH 25
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#define CS_RPC1_RESET 0x00200000
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#define CS_RPC1_EBL_MSB 24
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#define CS_RPC1_EBL_LSB 16
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#define CS_RPC1_EAP_MSB 12
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#define CS_RPC1_EAP_LSB 12
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#define CS_RPC1_EP_MSB 11
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#define CS_RPC1_EP_LSB 8
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#define CS_RPC1_DAP_MSB 4
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#define CS_RPC1_DAP_LSB 4
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#define CS_RPC1_DP_MSB 3
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#define CS_RPC1_DP_LSB 0
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#define CS_RS1 HW_REGISTER_RW( 0x7e802208 )
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#define CS_RS1_MASK 0x01ffffff
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#define CS_RS1_WIDTH 25
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#define CS_RS1_RESET 0000000000
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#define CS_RS1_DBO_MSB 24
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#define CS_RS1_DBO_LSB 24
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#define CS_RS1_IBO_MSB 23
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#define CS_RS1_IBO_LSB 23
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#define CS_RS1_CRCE_MSB 22
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#define CS_RS1_CRCE_LSB 22
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#define CS_RS1_LCI_MSB 21
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#define CS_RS1_LCI_LSB 21
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#define CS_RS1_GSPI_MSB 20
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#define CS_RS1_GSPI_LSB 20
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#define CS_RS1_LEI_MSB 19
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#define CS_RS1_LEI_LSB 19
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#define CS_RS1_LSI_MSB 18
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#define CS_RS1_LSI_LSB 18
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#define CS_RS1_FEI_MSB 17
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#define CS_RS1_FEI_LSB 17
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#define CS_RS1_FSI_MSB 16
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#define CS_RS1_FSI_LSB 16
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#define CS_RS1_FNUM_MSB 15
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#define CS_RS1_FNUM_LSB 0
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#define CS_RSA1 HW_REGISTER_RW( 0x7e80220c )
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#define CS_RSA1_MASK 0x3fffffff
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#define CS_RSA1_WIDTH 30
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#define CS_RSA1_RESET 0000000000
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#define CS_RSA1__MSB 29
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#define CS_RSA1__LSB 0
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#define CS_REA1 HW_REGISTER_RW( 0x7e802210 )
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#define CS_REA1_MASK 0x3fffffff
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#define CS_REA1_WIDTH 30
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#define CS_REA1_RESET 0000000000
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#define CS_REA1__MSB 29
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#define CS_REA1__LSB 0
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#define CS_RWP1 HW_REGISTER_RO( 0x7e802214 )
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#define CS_RWP1_MASK 0x3fffffff
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#define CS_RWP1_WIDTH 30
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#define CS_RWP1__MSB 29
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#define CS_RWP1__LSB 0
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#define CS_RBC1 HW_REGISTER_RO( 0x7e802218 )
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#define CS_RBC1_MASK 0xffffffff
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#define CS_RBC1_WIDTH 32
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#define CS_RBC1__MSB 31
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#define CS_RBC1__LSB 0
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#define CS_RLS1 HW_REGISTER_RW( 0x7e80221c )
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#define CS_RLS1_MASK 0x0000ffff
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#define CS_RLS1_WIDTH 16
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#define CS_RLS1_RESET 0000000000
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#define CS_RLS1__MSB 15
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#define CS_RLS1__LSB 0
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#define CS_RDSA1 HW_REGISTER_RW( 0x7e802220 )
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#define CS_RDSA1_MASK 0x3fffffff
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#define CS_RDSA1_WIDTH 30
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#define CS_RDSA1_RESET 0000000000
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#define CS_RDSA1__MSB 29
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#define CS_RDSA1__LSB 0
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#define CS_RDEA1 HW_REGISTER_RW( 0x7e802224 )
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#define CS_RDEA1_MASK 0x3fffffff
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#define CS_RDEA1_WIDTH 30
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#define CS_RDEA1_RESET 0000000000
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#define CS_RDEA1__MSB 29
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#define CS_RDEA1__LSB 0
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#define CS_RDS1 HW_REGISTER_RW( 0x7e802228 )
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#define CS_RDS1_MASK 0x0000ffff
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#define CS_RDS1_WIDTH 16
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#define CS_RDS1_RESET 0000000000
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#define CS_RDS1__MSB 15
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#define CS_RDS1__LSB 0
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#define CS_DTOV1 HW_REGISTER_RW( 0x7e80222c )
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#define CS_DTOV1_MASK 0x00007f7f
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#define CS_DTOV1_WIDTH 15
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#define CS_DTOV1_RESET 0000000000
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#define CS_DTOV1_IMEN_MSB 14
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#define CS_DTOV1_IMEN_LSB 14
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#define CS_DTOV1_IMDT_MSB 13
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#define CS_DTOV1_IMDT_LSB 8
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#define CS_DTOV1_EMEN_MSB 6
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#define CS_DTOV1_EMEN_LSB 6
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#define CS_DTOV1_EMDT_MSB 5
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#define CS_DTOV1_EMDT_LSB 0
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